[PATCH v5 6/9] coresight: add support for CPU debug module

2017-03-25 Thread Leo Yan 
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".

Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we can check program counter value with
combined CPU exception level, secure state, etc. So this is helpful for
analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
loop with IRQ disabled. In this case the CPU cannot switch context and
handle any interrupt (including IPIs), as the result it cannot handle
SMP call for stack dump.

This patch is to enable coresight debug module, so firstly this driver
is to bind apb clock for debug module and this is to ensure the debug
module can be accessed from program or external debugger. And the driver
uses sample-based registers for debug purpose, e.g. when system triggers
panic, the driver will dump program counter and combined context
registers (EDCIDSR, EDVIDSR); by parsing context registers so can
quickly get to know CPU secure state, exception level, etc.

Some of the debug module registers are located in CPU power domain, so
this requires the CPU power domain stays on when access related debug
registers, but the power management for CPU power domain is quite
dependent on SoC integration for power management. For the platforms
which with sane power controller implementations, this driver follows
the method to set EDPRCR to try to pull the CPU out of low power state
and then set 'no power down request' bit so the CPU has no chance to
lose power.

If the SoC has not followed up this design well for power management
controller, the driver introduces module parameter "idle_constraint".
Setting this parameter for latency requirement in microseconds, finally
we can constrain all or partial idle states to ensure the CPU power
domain is enabled, this is a backup method to access coresight CPU
debug component safely.

Signed-off-by: Leo Yan 
---
 drivers/hwtracing/coresight/Kconfig   |  11 +
 drivers/hwtracing/coresight/Makefile  |   1 +
 drivers/hwtracing/coresight/coresight-cpu-debug.c | 704 ++
 3 files changed, 716 insertions(+)
 create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c

diff --git a/drivers/hwtracing/coresight/Kconfig 
b/drivers/hwtracing/coresight/Kconfig
index 130cb21..18d7931 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -89,4 +89,15 @@ config CORESIGHT_STM
  logging useful software events or data coming from various entities
  in the system, possibly running different OSs
 
+config CORESIGHT_CPU_DEBUG
+   tristate "CoreSight CPU Debug driver"
+   depends on ARM || ARM64
+   depends on DEBUG_FS
+   help
+ This driver provides support for coresight debugging module. This
+ is primarily used to dump sample-based profiling registers when
+ system triggers panic, the driver will parse context registers so
+ can quickly get to know program counter (PC), secure state,
+ exception level, etc.
+
 endif
diff --git a/drivers/hwtracing/coresight/Makefile 
b/drivers/hwtracing/coresight/Makefile
index af480d9..433d590 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
coresight-etm4x-sysfs.o
 obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
 obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
+obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c 
b/drivers/hwtracing/coresight/coresight-cpu-debug.c
new file mode 100644
index 000..fbec1d1
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -0,0 +1,704 @@
+/*
+ * Copyright (c) 2017 Linaro Limited. All rights reserved.
+ *
+ * Author: Leo Yan 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "coresight-priv.h"
+
+#define EDPCSR 0x0A0
+#define EDCIDSR

[PATCH v5 4/9] coresight: refactor with function of_coresight_get_cpu

2017-03-25 Thread Leo Yan 
This is refactor to add function of_coresight_get_cpu(), so it's used to
retrieve CPU id for coresight component. Finally can use it as a common
function for multiple places.

Suggested-by: Mathieu Poirier 
Signed-off-by: Leo Yan 
---
 drivers/hwtracing/coresight/of_coresight.c | 43 +++---
 include/linux/coresight.h  |  2 ++
 2 files changed, 30 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c 
b/drivers/hwtracing/coresight/of_coresight.c
index 1a77280..78d2399 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -101,15 +101,39 @@ static int of_coresight_alloc_memory(struct device *dev,
return 0;
 }
 
+int of_coresight_get_cpu(struct device_node *node)
+{
+   int cpu;
+   bool found;
+   struct device_node *dn, *np;
+
+   dn = of_parse_phandle(node, "cpu", 0);
+
+   /* Affinity defaults to CPU0 */
+   if (!dn)
+   return 0;
+
+   for_each_possible_cpu(cpu) {
+   np = of_cpu_device_node_get(cpu);
+   found = (dn == np);
+   of_node_put(np);
+   if (found)
+   break;
+   }
+   of_node_put(dn);
+
+   /* Affinity to CPU0 if no cpu nodes are found */
+   return found ? cpu : 0;
+}
+EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
+
 struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, struct device_node *node)
 {
-   int i = 0, ret = 0, cpu;
+   int i = 0, ret = 0;
struct coresight_platform_data *pdata;
struct of_endpoint endpoint, rendpoint;
struct device *rdev;
-   bool found;
-   struct device_node *dn, *np;
struct device_node *ep = NULL;
struct device_node *rparent = NULL;
struct device_node *rport = NULL;
@@ -176,18 +200,7 @@ struct coresight_platform_data 
*of_get_coresight_platform_data(
} while (ep);
}
 
-   dn = of_parse_phandle(node, "cpu", 0);
-   for_each_possible_cpu(cpu) {
-   np = of_cpu_device_node_get(cpu);
-   found = (dn == np);
-   of_node_put(np);
-   if (found)
-   break;
-   }
-   of_node_put(dn);
-
-   /* Affinity to CPU0 if no cpu nodes are found */
-   pdata->cpu = found ? cpu : 0;
+   pdata->cpu = of_coresight_get_cpu(node);
 
return pdata;
 }
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 2a5982c..bf96678 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -263,9 +263,11 @@ static inline int coresight_timeout(void __iomem *addr, 
u32 offset,
 #endif
 
 #ifdef CONFIG_OF
+extern int of_coresight_get_cpu(struct device_node *node);
 extern struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, struct device_node *node);
 #else
+static inline int of_coresight_get_cpu(struct device_node *node) { return 0; }
 static inline struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, struct device_node *node) { return NULL; }
 #endif
-- 
2.7.4

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[PATCH v5 0/9] coresight: enable debug module

2017-03-25 Thread Leo Yan 
ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
Sample-based Profiling Extension" has description for sampling
registers, we can utilize these registers to check program counter
value with combined CPU exception level, secure state, etc. So this is
helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
with IRQ disabled; the 'hang' CPU cannot switch context and handle any
interrupt, so it cannot handle SMP call for stack dump, etc.

This patch series is to enable coresight debug module with sample-based
registers and register call back notifier for PCSR register dumping
when panic happens, so we can see below dumping info for panic; and
this patch series has considered the conditions for access permission
for debug registers self, so this can avoid access debug registers when
CPU power domain is off; the driver also try to figure out the CPU is
in secure or non-secure state.

Patch 0001 is to document the dt binding; patch 0002 is to document
boot parameters used in kernel command line.

Patch 0003 is used to fix the func of_get_coresight_platform_data()
doesn't properly drop the reference to the CPU node pointer; and
patch 0004 is refactor to add new function of_coresight_get_cpu().
Patch 0005 is to add const quality to structure device_node.

Patch 0006 is the driver for CPU debug module.

Patches 0007/0008 in this series are to enable debug unit on 96boards
Hikey, patch 0007 is to add apb clock for debug unit and patch 0006
is to add DT nodes for debug unit. Patch 0009 is to enable debug on
96boards DB410c. Have verified on both two boards.

We can enable debugging with two method, adding parameters into kernel
command line for build-in module:
  coresight_cpu_debug.enable=1
  coresight_cpu_debug.idle_constraint=0

Or we can wait the system has booted up to use debugfs nodes to enable
debugging and set idle constraints:
  # echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
  # echo 0 > /sys/kernel/debug/coresight_cpu_debug/idle_constraint

As result we can get below log after input command:
echo c > /proc/sysrq-trigger:

ARM external debug module:
CPU[0]:
 EDPRSR:  000b (Power:On DLK:Unlock)
 EDPCSR:  [] handle_IPI+0xe4/0x150
 EDCIDSR: 
 EDVIDSR: 9000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
CPU[1]:
 EDPRSR:  000b (Power:On DLK:Unlock)
 EDPCSR:  [] debug_notifier_call+0x108/0x288
 EDCIDSR: 
 EDVIDSR: 9000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)

[...]

Changes from v4:
* This version is mainly credit to ARM colleagues many contribution
  ideas for better quality (Thanks a lot Suzuki, Mike and Sudeep!).
* According to Suzuki suggestion, refined debug module driver to avoid
  memory leak for drvdata struct, handle PCSAMPLE_MODE=1, use flag
  drvdata.pc_has_offset to indicate if PCSR has offset, minor fixes.
* According to Mathieu suggestion, refined dt binding description.
* Changed driver to support module mode;
* According to Mike suggestion and very appreciate the pseudo code,
  added support to force CPU powered up with register EDPRCR;
* According to discussions, added command line and debugfs nodes to
  support enabling debugging for boot time, or later can dynamically
  enable/disable debugging by debugfs.
* According to Rob Herring suggestion, one minor fixes in DT binding.
* According to Stephen Boyd suggestion, add const quality to structure
  device_node. And used use of_cpu_device_node_get() to replace
  of_get_cpu_node() in patch 0003.

Changes from v3:
* Added Suzuki K Poulose's patch to fix issue for the func
  of_get_coresight_platform_data() doesn't properly drop the reference
  to the CPU node pointer.
* According to Suzuki suggestion, added code to handl the corner case
  for ARMv8 CPU with aarch32 mode.
* According to Suzuki suggestion, changed compatible string to
  "arm,coresight-cpu-debug".
* According to Mathieu suggestion, added "power-domains" as optional
  properties.

Changes from v2:
* According to Mathieu Poirier suggestion, applied some minor fixes.
* Added two extra patches for enabling debug module on Hikey.

Changes from v1:
* According to Mike Leach suggestion, removed the binding for debug
  module clocks which have been directly provided by CPU clocks.
* According to Mathieu Poirier suggestion, added function
  of_coresight_get_cpu() and some minor refactors for debug module
  driver.

Changes from RFC:
* According to Mike Leach suggestion, added check for EDPRSR to avoid
  lockup; added supporting EDVIDSR and EDCIDSR registers.
* According to Mark Rutland and Mathieu Poirier suggestion, rewrote
  the documentation for DT binding.
* According to Mark and Mathieu suggestion, refined debug driver.


Leo Yan (8):
  coresight: bindings for CPU debug module
  doc: Add documentation for Coresight CPU debug
  coresight: refactor with function of_coresight_get_cpu
  coresight: use const for device_node structures
  coresight: add support for CPU debug module
  clk: hi6220: add debug

[PATCH v5 1/9] coresight: bindings for CPU debug module

2017-03-25 Thread Leo Yan 
According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
Chapter 'Part H: External debug', the CPU can integrate debug module
and it can support self-hosted debug and external debug. Especially
for supporting self-hosted debug, this means the program can access
the debug module from mmio region; and usually the mmio region is
integrated with coresight.

So add document for binding debug component, includes binding to APB
clock; and also need specify the CPU node which the debug module is
dedicated to specific CPU.

Suggested-by: Mike Leach 
Reviewed-by: Mathieu Poirier 
Signed-off-by: Leo Yan 
---
 .../bindings/arm/coresight-cpu-debug.txt   | 48 ++
 1 file changed, 48 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt 
b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
new file mode 100644
index 000..7ef3824
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
@@ -0,0 +1,48 @@
+* CoreSight CPU Debug Component:
+
+CoreSight CPU debug component are compliant with the ARMv8 architecture
+reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+external debug module is mainly used for two modes: self-hosted debug and
+external debug, and it can be accessed from mmio region from Coresight
+and eventually the debug module connects with CPU for debugging. And the
+debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc;
+usually every CPU has one dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be "arm,coresight-cpu-debug"; supplemented with
+   "arm,primecell" since this driver is using the AMBA bus
+  interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+using the AMBA framework, the name of the clock providing
+   the interconnect should be "apb_pclk" and the clock is
+   mandatory. The interface between the debug logic and the
+   processor core is clocked by the internal CPU clock, so it
+   is enabled with CPU clock by default.
+
+- cpu : the CPU phandle the debug module is affined to. When omitted
+   the module is considered to belong to CPU0.
+
+Optional properties:
+
+- power-domains: a phandle to the debug power domain. We use "power-domains"
+ binding to turn on the debug logic if it has own dedicated
+power domain and if necessary to use "idle_constraint" in
+kernel command line or debugfs node to constrain idle states
+to ensure registers in the CPU power domain are accessible.
+
+Example:
+
+   debug@f659 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf659 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
-- 
2.7.4

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[PATCH v5 3/9] coresight: of_get_coresight_platform_data: Add missing of_node_put

2017-03-25 Thread Leo Yan 
From: Suzuki K Poulose 

The of_get_coresight_platform_data iterates over the possible CPU nodes
to find a given cpu phandle. However it does not drop the reference
to the node pointer returned by the of_get_coresight_platform_data.

This patch also introduces another minor fix is to use
of_cpu_device_node_get() to replace of_get_cpu_node().

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
[Leo: minor tweaks for of_get_coresight_platform_data]
Signed-off-by: Leo Yan 
---
 drivers/hwtracing/coresight/of_coresight.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c 
b/drivers/hwtracing/coresight/of_coresight.c
index 629e031..1a77280 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -108,7 +108,8 @@ struct coresight_platform_data 
*of_get_coresight_platform_data(
struct coresight_platform_data *pdata;
struct of_endpoint endpoint, rendpoint;
struct device *rdev;
-   struct device_node *dn;
+   bool found;
+   struct device_node *dn, *np;
struct device_node *ep = NULL;
struct device_node *rparent = NULL;
struct device_node *rport = NULL;
@@ -175,17 +176,19 @@ struct coresight_platform_data 
*of_get_coresight_platform_data(
} while (ep);
}
 
-   /* Affinity defaults to CPU0 */
-   pdata->cpu = 0;
dn = of_parse_phandle(node, "cpu", 0);
-   for (cpu = 0; dn && cpu < nr_cpu_ids; cpu++) {
-   if (dn == of_get_cpu_node(cpu, NULL)) {
-   pdata->cpu = cpu;
+   for_each_possible_cpu(cpu) {
+   np = of_cpu_device_node_get(cpu);
+   found = (dn == np);
+   of_node_put(np);
+   if (found)
break;
-   }
}
of_node_put(dn);
 
+   /* Affinity to CPU0 if no cpu nodes are found */
+   pdata->cpu = found ? cpu : 0;
+
return pdata;
 }
 EXPORT_SYMBOL_GPL(of_get_coresight_platform_data);
-- 
2.7.4

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[PATCH v5 7/9] clk: hi6220: add debug APB clock

2017-03-25 Thread Leo Yan 
The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.

Signed-off-by: Leo Yan 
---
 drivers/clk/hisilicon/clk-hi6220.c   | 1 +
 include/dt-bindings/clock/hi6220-clock.h | 5 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
index c0e8e1f..2ae151c 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -134,6 +134,7 @@ static struct hisi_gate_clock 
hi6220_separated_gate_clks_sys[] __initdata = {
{ HI6220_UART4_PCLK,"uart4_pclk","uart4_src",  
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8,  0, },
{ HI6220_SPI_CLK,   "spi_clk",   "clk_150m",   
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9,  0, },
{ HI6220_TSENSOR_CLK,   "tsensor_clk",   "clk_bus",
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
+   { HI6220_DAPB_CLK,  "dapb_clk",  "cs_dapb",
CLK_SET_RATE_PARENT|CLK_IS_CRITICAL,   0x230, 18, 0, },
{ HI6220_MMU_CLK,   "mmu_clk",   "ddrc_axi1",  
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
{ HI6220_HIFI_SEL,  "hifi_sel",  "hifi_src",   
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0,  0, },
{ HI6220_MMC0_SYSPLL,   "mmc0_syspll",   "syspll", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1,  0, },
diff --git a/include/dt-bindings/clock/hi6220-clock.h 
b/include/dt-bindings/clock/hi6220-clock.h
index 6b03c84..b8ba665 100644
--- a/include/dt-bindings/clock/hi6220-clock.h
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -124,7 +124,10 @@
 #define HI6220_CS_DAPB 57
 #define HI6220_CS_ATB_DIV  58
 
-#define HI6220_SYS_NR_CLKS 59
+/* gate clock */
+#define HI6220_DAPB_CLK59
+
+#define HI6220_SYS_NR_CLKS 60
 
 /* clk in Hi6220 media controller */
 /* gate clocks */
-- 
2.7.4

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[PATCH v5 5/9] coresight: use const for device_node structures

2017-03-25 Thread Leo Yan 
Almost low level functions from open firmware have used const to
qualify device_node structures, so add const for device_node
parameters in of_coresight related functions.

Signed-off-by: Leo Yan 
---
 drivers/hwtracing/coresight/of_coresight.c | 6 +++---
 include/linux/coresight.h  | 8 
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c 
b/drivers/hwtracing/coresight/of_coresight.c
index 78d2399..46eec0f 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -52,7 +52,7 @@ of_coresight_get_endpoint_device(struct device_node *endpoint)
   endpoint, of_dev_node_match);
 }
 
-static void of_coresight_get_ports(struct device_node *node,
+static void of_coresight_get_ports(const struct device_node *node,
   int *nr_inport, int *nr_outport)
 {
struct device_node *ep = NULL;
@@ -101,7 +101,7 @@ static int of_coresight_alloc_memory(struct device *dev,
return 0;
 }
 
-int of_coresight_get_cpu(struct device_node *node)
+int of_coresight_get_cpu(const struct device_node *node)
 {
int cpu;
bool found;
@@ -128,7 +128,7 @@ int of_coresight_get_cpu(struct device_node *node)
 EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
 
 struct coresight_platform_data *of_get_coresight_platform_data(
-   struct device *dev, struct device_node *node)
+   struct device *dev, const struct device_node *node)
 {
int i = 0, ret = 0;
struct coresight_platform_data *pdata;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index bf96678..4915254 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -263,13 +263,13 @@ static inline int coresight_timeout(void __iomem *addr, 
u32 offset,
 #endif
 
 #ifdef CONFIG_OF
-extern int of_coresight_get_cpu(struct device_node *node);
+extern int of_coresight_get_cpu(const struct device_node *node);
 extern struct coresight_platform_data *of_get_coresight_platform_data(
-   struct device *dev, struct device_node *node);
+   struct device *dev, const struct device_node *node);
 #else
-static inline int of_coresight_get_cpu(struct device_node *node) { return 0; }
+static inline int of_coresight_get_cpu(const struct device_node *node) { 
return 0; }
 static inline struct coresight_platform_data *of_get_coresight_platform_data(
-   struct device *dev, struct device_node *node) { return NULL; }
+   struct device *dev, const struct device_node *node) { return NULL; }
 #endif
 
 #ifdef CONFIG_PID_NS
-- 
2.7.4

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[PATCH v5 8/9] arm64: dts: hi6220: register debug module

2017-03-25 Thread Leo Yan 
Bind debug module driver for Hi6220.

Signed-off-by: Leo Yan 
---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 +++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 470461d..467aa15 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -913,5 +913,69 @@
};
};
};
+
+   debug@f659 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf659 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f6592000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf6592000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f6594000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf6594000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f6596000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf6596000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f65d {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf65d 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f65d2000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf65d2000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f65d4000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf65d4000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@f65d6000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0 0xf65d6000 0 0x1000>;
+   clocks = <_ctrl HI6220_DAPB_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
};
 };
-- 
2.7.4

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[PATCH v5 9/9] arm64: dts: qcom: msm8916: Add debug unit

2017-03-25 Thread Leo Yan 
Add debug unit on Qualcomm msm8916 based platforms, including the
DragonBoard 410c board.

Signed-off-by: Leo Yan 
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..3af814b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1104,6 +1104,38 @@
};
};
 
+   debug@85 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0x85 0x1000>;
+   clocks = < RPM_QDSS_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@852000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0x852000 0x1000>;
+   clocks = < RPM_QDSS_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@854000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0x854000 0x1000>;
+   clocks = < RPM_QDSS_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
+   debug@856000 {
+   compatible = "arm,coresight-cpu-debug","arm,primecell";
+   reg = <0x856000 0x1000>;
+   clocks = < RPM_QDSS_CLK>;
+   clock-names = "apb_pclk";
+   cpu = <>;
+   };
+
etm@85c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85c000 0x1000>;
-- 
2.7.4

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[PATCH v5 2/9] doc: Add documentation for Coresight CPU debug

2017-03-25 Thread Leo Yan 
Update kernel-parameters.txt to add two new parameters:

- coresight_cpu_debug.enable is a knob to enable debugging at boot time.
- coresight_cpu_debug.idle_constraint is used to constrain idle states
  to ensure Coresight CPU debug component can be accessible.

Signed-off-by: Leo Yan 
---
 Documentation/admin-guide/kernel-parameters.txt | 21 +
 1 file changed, 21 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 2ba45ca..6ed57d9 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -650,6 +650,27 @@
/proc//coredump_filter.
See also Documentation/filesystems/proc.txt.
 
+   coresight_cpu_debug.enable
+   [ARM,ARM64]
+   Format: 
+   Enable/disable the CPU sampling based debugging.
+   0: default value, disable debugging
+   1: enable debugging at boot time
+
+   coresight_cpu_debug.idle_constraint
+   [ARM,ARM64]
+   Format: 
+   Some platforms have designed the idle states to disable
+   CPU power domain and need manually set constraint so
+   can access coresight CPU debug component safely. Setting
+   this parameter for latency requirement in
+   microseconds, finally we can constraint all or partial
+   idle states to ensure the CPU power domain is enabled.
+   Default is -1, which means no limiation to CPU idle
+   states; if set to 0, this means disabling all idle
+   states; user can choose other platform dependent values
+   so can disable specific idle states for the platform.
+
cpuidle.off=1   [CPU_IDLE]
disable the cpuidle sub-system
 
-- 
2.7.4

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Re: [PATCH] hibernation: on 32-bit x86, disabled in favor of KASLR

2017-03-25 Thread Kees Cook 
On Sat, Mar 25, 2017 at 7:54 AM, Evgenii Shatokhin
 wrote:
> On 23.03.2017 18:30, Rafael J. Wysocki wrote:
>>
>> On Thu, Mar 23, 2017 at 2:23 PM, Evgenii Shatokhin
>>  wrote:
>>>
>>> On 23.03.2017 03:27, Kees Cook wrote:


 This is a modified revert of commit 65fe935dd238 ("x86/KASLR, x86/power:
 Remove x86 hibernation restrictions"), since it appears that 32-bit
 hibernation still can't support KASLR. 64-bit is fine. Since people have
 been running with KASLR by default on 32-bit since v4.8, this disables
 hibernation (with a warning). Booting with "nokaslr" will disable KASLR
 and enable hibernation.

 Reported-by: Evgenii Shatokhin 
 Signed-off-by: Kees Cook 
 Cc: sta...@vger.kernel.org # v4.8+
>>>
>>>
>>>
>>> The patch does not work as intended on my system, unfortunately.
>>>
>>> I tried the mainline kernel v4.11-rc3 and added this patch. With
>>> "nokaslr"
>>> in the kernel command line, the system fails to hibernate. It complains
>>> this
>>> way in the log:
>>>
>>> <...>
>>> kernel: PM: writing image.
>>> kernel: PM: Cannot find swap device, try swapon -a.
>>> kernel: PM: Cannot get swap writer
>>> kernel: PM: Basic memory bitmaps freed
>>> kernel: Restarting tasks ... done.
>>> systemd[1]: Time has been changed
>>> systemd[3948]: Time has been changed
>>> systemd[14825]: Time has been changed
>>> systemd[1]: systemd-hibernate.service: main process exited, code=exited,
>>> status=1/FAILURE
>>> systemd[1]: Failed to start Hibernate.
>>> <...>
>>>
>>> The swap device (swap file, actually) is available, however:
>>> -
>>> # swapon -s
>>> Filename  Type  SizeUsed  Priority
>>> /swap file  6297596 0 -1
>>> -
>>>
>>> I built the same kernel without this patch then, added "nokaslr" in the
>>> kernel command line again, and the system hibernates and resumes fine.
>>
>>
>> With the patch applied and "nokaslr" in the kernel command line, what
>> shows up when you do
>>
>> $ cat /sys/power/state
>>
>> ?
>
>
> freeze standby mem disk
>
> However, I think now that the patch itself is OK.
>
> I experimented with the patched kernel a bit more and found that hibernate
> does work when I place "nokaslr" before "resume=xxx resume_offset=xxx" in
> the kernel command line and does not work when I place "nokaslr" after these
> options. So I guess there is an issue with parsing of the kernel command
> line somewhere (dracut scripts? systemd? I do not know). If resume= or
> resume_offset= were corrupted, that might have been the reason why the
> system could not find the swap file when hibernating.
>
> Anyway, that issue is clearly unrelated to this patch and the patch itself
> works OK for me.
>
> Thanks a lot!
>
> Tested-by: Evgenii Shatokhin 

Ah, right. Hm, that is kind of the fault of the patch (and the prior
disabling too). Let me see if I can find a better solution...

-Kees

-- 
Kees Cook
Pixel Security
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Re: [PATCH] hibernation: on 32-bit x86, disabled in favor of KASLR

2017-03-25 Thread Evgenii Shatokhin 

On 23.03.2017 18:30, Rafael J. Wysocki wrote:

On Thu, Mar 23, 2017 at 2:23 PM, Evgenii Shatokhin
 wrote:

On 23.03.2017 03:27, Kees Cook wrote:


This is a modified revert of commit 65fe935dd238 ("x86/KASLR, x86/power:
Remove x86 hibernation restrictions"), since it appears that 32-bit
hibernation still can't support KASLR. 64-bit is fine. Since people have
been running with KASLR by default on 32-bit since v4.8, this disables
hibernation (with a warning). Booting with "nokaslr" will disable KASLR
and enable hibernation.

Reported-by: Evgenii Shatokhin 
Signed-off-by: Kees Cook 
Cc: sta...@vger.kernel.org # v4.8+



The patch does not work as intended on my system, unfortunately.

I tried the mainline kernel v4.11-rc3 and added this patch. With "nokaslr"
in the kernel command line, the system fails to hibernate. It complains this
way in the log:

<...>
kernel: PM: writing image.
kernel: PM: Cannot find swap device, try swapon -a.
kernel: PM: Cannot get swap writer
kernel: PM: Basic memory bitmaps freed
kernel: Restarting tasks ... done.
systemd[1]: Time has been changed
systemd[3948]: Time has been changed
systemd[14825]: Time has been changed
systemd[1]: systemd-hibernate.service: main process exited, code=exited,
status=1/FAILURE
systemd[1]: Failed to start Hibernate.
<...>

The swap device (swap file, actually) is available, however:
-
# swapon -s
Filename  Type  SizeUsed  Priority
/swap file  6297596 0 -1
-

I built the same kernel without this patch then, added "nokaslr" in the
kernel command line again, and the system hibernates and resumes fine.


With the patch applied and "nokaslr" in the kernel command line, what
shows up when you do

$ cat /sys/power/state

?


freeze standby mem disk

However, I think now that the patch itself is OK.

I experimented with the patched kernel a bit more and found that 
hibernate does work when I place "nokaslr" before "resume=xxx 
resume_offset=xxx" in the kernel command line and does not work when I 
place "nokaslr" after these options. So I guess there is an issue with 
parsing of the kernel command line somewhere (dracut scripts? systemd? I 
do not know). If resume= or resume_offset= were corrupted, that might 
have been the reason why the system could not find the swap file when 
hibernating.


Anyway, that issue is clearly unrelated to this patch and the patch 
itself works OK for me.


Thanks a lot!

Tested-by: Evgenii Shatokhin 

Regards,
Evgenii
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