Re: [PATCH v4 2/3] usb: gadget: f_uac2: split out audio core

[Ruslan Bilovol]

On Mon, May 22, 2017 at 6:58 PM, Jassi Brar  wrote:
> On Thu, May 18, 2017 at 4:07 AM, Ruslan Bilovol
>  wrote:
>> Abstract the peripheral side ALSA sound card code from
>> the f_uac2 function into a component that can be called
>> by various functions, so the various flavors can be split
>> apart and selectively reused.
>>
>> Visible changes:
>>  - add uac_params structure to pass audio paramteres for
>>g_audio_setup
>>  - make ALSA sound card's name configurable
>>  - add [in/out]_ep_maxpsize
>>  - allocate snd_uac_chip structure during g_audio_setup
>>  - add u_audio_[start/stop]_[capture/playback] functions
>>
>> Signed-off-by: Ruslan Bilovol 
>> ---
>>  drivers/usb/gadget/Kconfig|   4 +
>>  drivers/usb/gadget/function/Makefile  |   1 +
>>  drivers/usb/gadget/function/f_uac2.c  | 721 
>> --
>>  drivers/usb/gadget/function/u_audio.c | 661 +++
>>  drivers/usb/gadget/function/u_audio.h |  95 +
>>  drivers/usb/gadget/legacy/Kconfig |   1 +
>>  6 files changed, 846 insertions(+), 637 deletions(-)
>>  create mode 100644 drivers/usb/gadget/function/u_audio.c
>>  create mode 100644 drivers/usb/gadget/function/u_audio.h
>>
>> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
>> index c164d6b..2ba0ace 100644
>> --- a/drivers/usb/gadget/Kconfig
>> +++ b/drivers/usb/gadget/Kconfig
>> @@ -158,6 +158,9 @@ config USB_U_SERIAL
>>  config USB_U_ETHER
>> tristate
>>
>> +config USB_U_AUDIO
>> +   tristate
>> +
>>  config USB_F_SERIAL
>> tristate
>>
>> @@ -381,6 +384,7 @@ config USB_CONFIGFS_F_UAC2
>> depends on SND
>> select USB_LIBCOMPOSITE
>> select SND_PCM
>> +   select USB_U_AUDIO
>> select USB_F_UAC2
>> help
>>   This Audio function is compatible with USB Audio Class
>> diff --git a/drivers/usb/gadget/function/Makefile 
>> b/drivers/usb/gadget/function/Makefile
>> index cb8c225..b29f2ae 100644
>> --- a/drivers/usb/gadget/function/Makefile
>> +++ b/drivers/usb/gadget/function/Makefile
>> @@ -32,6 +32,7 @@ usb_f_mass_storage-y  := f_mass_storage.o 
>> storage_common.o
>>  obj-$(CONFIG_USB_F_MASS_STORAGE)+= usb_f_mass_storage.o
>>  usb_f_fs-y := f_fs.o
>>  obj-$(CONFIG_USB_F_FS) += usb_f_fs.o
>> +obj-$(CONFIG_USB_U_AUDIO)  += u_audio.o
>>  usb_f_uac1-y   := f_uac1.o u_uac1.o
>>  obj-$(CONFIG_USB_F_UAC1)   += usb_f_uac1.o
>>  usb_f_uac2-y   := f_uac2.o
>> diff --git a/drivers/usb/gadget/function/f_uac2.c 
>> b/drivers/usb/gadget/function/f_uac2.c
>> index d4565b5..059a14a 100644
>> --- a/drivers/usb/gadget/function/f_uac2.c
>> +++ b/drivers/usb/gadget/function/f_uac2.c
>> @@ -15,10 +15,7 @@
>>  #include 
>>  #include 
>>
>> -#include 
>> -#include 
>> -#include 
>> -
>> +#include "u_audio.h"
>>  #include "u_uac2.h"
>>
>>  /*
>> @@ -50,455 +47,23 @@
>>  #define UNFLW_CTRL 8
>>  #define OVFLW_CTRL 10
>>
>> -struct uac2_req {
>> -   struct uac2_rtd_params *pp; /* parent param */
>> -   struct usb_request *req;
>> -};
>> -
>> -struct uac2_rtd_params {
>> -   struct snd_uac2_chip *uac2; /* parent chip */
>> -   bool ep_enabled; /* if the ep is enabled */
>> -   /* Size of the ring buffer */
>> -   size_t dma_bytes;
>> -   unsigned char *dma_area;
>> -
>> -   struct snd_pcm_substream *ss;
>> -
>> -   /* Ring buffer */
>> -   ssize_t hw_ptr;
>> -
>> -   void *rbuf;
>> -
>> -   size_t period_size;
>> -
>> -   unsigned max_psize;
>> -   struct uac2_req *ureq;
>> -
>> -   spinlock_t lock;
>> -};
>> -
>> -struct snd_uac2_chip {
>> -   struct uac2_rtd_params p_prm;
>> -   struct uac2_rtd_params c_prm;
>> -
>> -   struct snd_card *card;
>> -   struct snd_pcm *pcm;
>> -
>> -   /* timekeeping for the playback endpoint */
>> -   unsigned int p_interval;
>> -   unsigned int p_residue;
>> -
>> -   /* pre-calculated values for playback iso completion */
>> -   unsigned int p_pktsize;
>> -   unsigned int p_pktsize_residue;
>> -   unsigned int p_framesize;
>> +struct f_uac2 {
>> +   struct g_audio g_audio;
>> +   u8 ac_intf, as_in_intf, as_out_intf;
>> +   u8 ac_alt, as_in_alt, as_out_alt;   /* needed for get_alt() */
>>  };
>>
>> -#define BUFF_SIZE_MAX  (PAGE_SIZE * 16)
>> -#define PRD_SIZE_MAX   PAGE_SIZE
>> -#define MIN_PERIODS4
>> -
>> -static struct snd_pcm_hardware uac2_pcm_hardware = {
>> -   .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER
>> -| SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID
>> -| SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
>> -   .rates = SNDRV_PCM_RATE_CONTINUOUS,
>> -   .periods_max = BUFF_SIZE_MAX / PRD_SIZE_MAX,
>> -   .buffer_bytes_max = BUFF_SIZE_MAX,
>> -   .period_bytes_max = 

Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[Linus Walleij]

On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng  wrote:

> R40 is said to be an upgrade of A20, and its pin configuration is also
> similar to A20 (and thus similar to A10).
>
> Add support for R40 to the A10 pinctrl driver.
>
> Signed-off-by: Icenowy Zheng 

Since I applied patches 2-5 you only need to resend from this point
for pin control.

Please send pin control patches separately from the rest of the series if you
can, and rebase on my "devel" branch, so I don't have to sift throgh so much
patches to find what I need to apply and what I can ignore.

Yours,
Linus Walleij
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Re: [PATCH v13 0/9] coresight: enable debug module

[Mathieu Poirier]

On 25 May 2017 at 09:57, Leo Yan  wrote:
> ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
> Sample-based Profiling Extension" has description for sampling
> registers, we can utilize these registers to check program counter
> value with combined CPU exception level, secure state, etc. So this is
> helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
> with IRQ disabled; the 'hang' CPU cannot switch context and handle any
> interrupt, so it cannot handle SMP call for stack dump, etc.
>
> This patch series is to enable coresight debug module with sample-based
> registers and register call back notifier for PCSR register dumping
> when panic happens, so we can see below dumping info for panic; and
> this patch series has considered the conditions for access permission
> for debug registers self, so this can avoid access debug registers when
> CPU power domain is off; the driver also try to figure out the CPU is
> in secure or non-secure state.

I have queued patches 1 to 7 to my tree.  I can't do anything about
patches 8 and 9 because they haven't been ack'ed.  From here you can
either chase them to get an ACK or send a separate patch to them
directly.

Thanks,
Mathieu

>
> Patch 0001 is to document the dt binding; patch 0002 adds one detailed
> document to describe the Coresight debug module implementation, the
> clock and power domain impaction on the driver, some examples for usage.
>
> Patch 0003 is to document boot parameters used in kernel command line.
>
> Patch 0004 is to add file entries for MAINTAINERS.
>
> Patch 0005 is used to fix the func of_get_coresight_platform_data()
> doesn't properly drop the reference to the CPU node pointer; and
> patch 0006 is refactor to add new function of_coresight_get_cpu().
>
> Patch 0007 is the driver for CPU debug module.
>
> Patch 0008 in this series are to enable debug unit on 96boards Hikey,
> Patch 0009 is to enable debug on 96boards DB410c. Have verified on both
> two boards.
>
> We can enable debugging with two methods, adding parameters into kernel
> command line for build-in module:
>   coresight_cpu_debug.enable=1
>
> Or we can wait the system has booted up to use debugfs nodes to enable
> debugging:
>   # echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
>
> As result we can get below log after input command:
> echo c > /proc/sysrq-trigger:
>
> ARM external debug module:
> coresight-cpu-debug 85.debug: CPU[0]:
> coresight-cpu-debug 85.debug:  EDPRSR:  0001 (Power:On DLK:Unlock)
> coresight-cpu-debug 85.debug:  EDPCSR:  [] 
> handle_IPI+0x174/0x1d8
> coresight-cpu-debug 85.debug:  EDCIDSR: 
> coresight-cpu-debug 85.debug:  EDVIDSR: 9000 (State:Non-secure 
> Mode:EL1/0 Width:64bits VMID:0)
> coresight-cpu-debug 852000.debug: CPU[1]:
> coresight-cpu-debug 852000.debug:  EDPRSR:  0001 (Power:On DLK:Unlock)
> coresight-cpu-debug 852000.debug:  EDPCSR:  [] 
> debug_notifier_call+0x23c/0x358
> coresight-cpu-debug 852000.debug:  EDCIDSR: 
> coresight-cpu-debug 852000.debug:  EDVIDSR: 9000 (State:Non-secure 
> Mode:EL1/0 Width:64bits VMID:0)
>
> [...]
>
> Changes from v12:
> * Fix build warning for 'ARCH=arm' reported by kbuild test robot.
>
> Changes from v11:
> * Dismissed checkpatch.pl warning about "quoted string split across
>   multiple lines" and "line over 80 characters".
>
> Changes from v10:
> * Followed Liviu suggestion to improve readability of the documentation.
> * ARM Juno DTS binding patch has been picked by Sudeep, so this patch
>   set has not included anymore. Great!
>
> Changes from v9:
> * Used dev_xyz() to replace pr_xyz() for print log.
> * Added DT binding patch for Juno shared by Suzuki.
>
> Changes from v8:
> * According to Mathieu suggestions to split the doc into two patches,
>   one is for kernel parameter and another is for driver documentation.
> * Add file entries to MAINTAINERS.
> * According to Mathieu suggestions, refined functions
>   debug_enable_func()/debug_disable_func().
>
> Changes from v7:
> * Fix operator priority bug.
> * Minor sequence adjustment for function debug_func_exit().
>
> Changes from v6:
> * According to Suzuki and Mathieu suggestions, refined debug module
>   driver to install panic notifier when insmod module; refined function
>   debug_force_cpu_powered_up() for CPU power state checking; some minor
>   fixing for output log, adding comments for memory barrier, code
>   alignment.
>
> Changes from v5:
> * According to Suzuki and Mathieu suggestions, refined debug module
>   driver to drop unused structure members, refactored initialization
>   code to distinguish hardware implementation features, refactored
>   flow for forcing CPU powered up, supported pm_runtime operations.
> * Added one new doc file: Documentation/trace/coresight-cpu-debug.txt,
>   which is used to describe detailed info for implementation, clock
>   and power domain impaction on debug module, and exmaples for common
> 

Re: [PATCH v3 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl

[Linus Walleij]

On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng  wrote:

> Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
> (especially A20), and can use modified version of the A10/A20 pinctrl
> driver.
>
> Add a compatible string for it.
>
> Signed-off-by: Icenowy Zheng 
> Acked-by: Rob Herring 
> ---
> Changes in v3:
> - Added Rob's ACK.

Patch applied with Chen-Yu's review tag.

Yours,
Linus Walleij
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Re: [PATCH v3 04/10] pinctrl: sunxi: drop dedicated A20 driver

[Linus Walleij]

On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng  wrote:

> As we added A20 support to A10 pinctrl driver, now we can delete the
> dedicated A20 pinctrl driver, which is duplicated code.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Only remove the A20 driver(A10 driver for A20 is enabled in
>   the previous commit now).

Patch applied with Chen-Yu's review tag, and I also fixed
up the Makefile by removing the rule for this file.

Yours,
Linus Walleij
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Re: [PATCH v3 03/10] pinctrl: sunxi: add A20 support to A10 driver

[Linus Walleij]

On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng  wrote:

> As A20 is designed as a pin-compatible upgrade of A10, their pin
> controller are very similar, and can share one driver.
>
> Add A20 support to the A10 driver.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Enable A10 driver for A20 and disable A20 driver in this commit, in
>   order to prevent A10 driver from conflicting with A20 driver.

Patch applied with Chen-Yu's review tag.

Yours,
Linus Walleij
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Re: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs

[Linus Walleij]

On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng  wrote:

> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>
> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
> into A10 driver, and add R40 support into it.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Commit message change.

Patch applied with Chen-Yu's review tag.

Yours,
Linus Walleij
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Re: [PATCH 20/29] sync_file.txt: standardize document format

[Mauro Carvalho Chehab]

Em Wed, 24 May 2017 22:36:36 -0300
Gustavo Padovan  escreveu:

> Hi Mauro,
> 
> 2017-05-18 Mauro Carvalho Chehab :
> 
> > Each text file under Documentation follows a different
> > format. Some doesn't even have titles!
> > 
> > Change its representation to follow the adopted standard,
> > using ReST markups for it to be parseable by Sphinx:
> > - Use markup for document title and authorship;
> > - Mark literal blocks;
> > - Use a numbered list for references.
> > 
> > Signed-off-by: Mauro Carvalho Chehab 
> > ---
> >  Documentation/sync_file.txt | 23 +--
> >  1 file changed, 13 insertions(+), 10 deletions(-)  
> 
> We went ahead and applied this to drm-misc-next. Thanks.

OK!

Thanks!
Mauro
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Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[Chen-Yu Tsai]

On Mon, May 29, 2017 at 9:19 PM,   wrote:
> 在 2017-05-29 21:11，Chen-Yu Tsai 写道：
>>
>> On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
>>>
>>> R40 is said to be an upgrade of A20, and its pin configuration is also
>>> similar to A20 (and thus similar to A10).
>>>
>>> Add support for R40 to the A10 pinctrl driver.
>>>
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  drivers/pinctrl/sunxi/Kconfig |   2 +-
>>>  drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272
>>> +-
>>>  2 files changed, 197 insertions(+), 77 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/sunxi/Kconfig
>>> b/drivers/pinctrl/sunxi/Kconfig
>>> index 624d84e6c936..9d01da3b90bd 100644
>>> --- a/drivers/pinctrl/sunxi/Kconfig
>>> +++ b/drivers/pinctrl/sunxi/Kconfig
>>> @@ -7,7 +7,7 @@ config PINCTRL_SUNXI
>>> select GPIOLIB
>>>
>>>  config PINCTRL_SUN4I_A10
>>> -   def_bool MACH_SUN4I || MACH_SUN7I
>>> +   def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
>>> select PINCTRL_SUNXI
>>>
>>>  config PINCTRL_SUN5I
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>>> b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>>> index 159580c04b14..0f6ca8391ea7 100644
>>> --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>>
>>
>> [...]
>>
>>> @@ -162,14 +183,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[]
>>> = {
>>>   SUNXI_FUNCTION(0x3, "can"),   /* RX */
>>>   SUNXI_FUNCTION(0x4, "uart1"), /* RING */
>>>   SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GNULL / ETXERR
>>> */
>>> -PINCTRL_SUN7I_A20),
>>> +PINCTRL_SUN7I_A20 |
>>> +PINCTRL_SUN8I_R40),
>>>   SUNXI_FUNCTION_VARIANT(0x6, "i2s1",   /* DI */
>>> -PINCTRL_SUN7I_A20)),
>>> +PINCTRL_SUN7I_A20 |
>>> +PINCTRL_SUN8I_R40)),
>>> /* Hole */
>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>>>   SUNXI_FUNCTION(0x0, "gpio_in"),
>>>   SUNXI_FUNCTION(0x1, "gpio_out"),
>>> - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>>> + SUNXI_FUNCTION(0x2, "i2c0"),  /* SCK */
>>> + SUNXI_FUNCTION_VARIANT(0x3,
>>> +"pll-lock-dbg",
>>
>>
>> Can you stick to underscores to be consistent?
>
>
> OK...
> This is a so strange pin name and I just picked the datasheet
> name.
>
> I don't care how to name it as I don't even know what this is.
>
>
>>
>>> +PINCTRL_SUN8I_R40)),
>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>>>   SUNXI_FUNCTION(0x0, "gpio_in"),
>>>   SUNXI_FUNCTION(0x1, "gpio_out"),
>>> @@ -177,11 +203,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[]
>>> = {
>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>>>   SUNXI_FUNCTION(0x0, "gpio_in"),
>>>   SUNXI_FUNCTION(0x1, "gpio_out"),
>>> - SUNXI_FUNCTION(0x2, "pwm")),  /* PWM0 */
>>> + SUNXI_FUNCTION_VARIANT(0x2, "pwm",/* PWM0 */
>>> +PINCTRL_SUN4I_A10 |
>>> +PINCTRL_SUN7I_A20),
>>> + SUNXI_FUNCTION_VARIANT(0x3, "pwm",/* PWM0 */
>>> +PINCTRL_SUN8I_R40)),
>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>>>   SUNXI_FUNCTION(0x0, "gpio_in"),
>>>   SUNXI_FUNCTION(0x1, "gpio_out"),
>>> - SUNXI_FUNCTION(0x2, "ir0"),   /* TX */
>>> + SUNXI_FUNCTION_VARIANT(0x2, "ir0",/* TX */
>>> +PINCTRL_SUN4I_A10 |
>>> +PINCTRL_SUN7I_A20),
>>> + SUNXI_FUNCTION_VARIANT(0x3, "pwm0",   /* PWM1 */
>>
>>
>> The numbering is wrong. Just drop the number altogether, like all the
>> other instances.
>>
>>> +PINCTRL_SUN8I_R40),
>>> /*
>>>  * The SPDIF block is not referenced at all in the A10
>>> user
>>>  * manual. However it is described in the code leaked and
>>> the
>>> @@ -205,7 +239,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] =
>>> {
>>>   SUNXI_FUNCTION_VARIANT(0x2, "i2s",/* MCLK */
>>>  PINCTRL_SUN4I_A10),
>>>   SUNXI_FUNCTION_VARIANT(0x2, "i2s0",   /* MCLK */
>>> -PINCTRL_SUN7I_A20),
>>> +PINCTRL_SUN7I_A20 |
>>> +PINCTRL_SUN8I_R40),
>>

Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[icenowy]

在 2017-05-29 21:11，Chen-Yu Tsai 写道：

On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:

R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).

Add support for R40 to the A10 pinctrl driver.

Signed-off-by: Icenowy Zheng 
---
 drivers/pinctrl/sunxi/Kconfig |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 
+-

 2 files changed, 197 insertions(+), 77 deletions(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig 
b/drivers/pinctrl/sunxi/Kconfig

index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB

 config PINCTRL_SUN4I_A10
-   def_bool MACH_SUN4I || MACH_SUN7I
+   def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI

 config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c

index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c


[...]

@@ -162,14 +183,19 @@ static const struct sunxi_desc_pin 
sun4i_a10_pins[] = {

  SUNXI_FUNCTION(0x3, "can"), /* RX */
  SUNXI_FUNCTION(0x4, "uart1"),   /* RING */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
-PINCTRL_SUN7I_A20),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40),
  SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2c0")),   /* SCK */
+ SUNXI_FUNCTION(0x2, "i2c0"),/* SCK */
+ SUNXI_FUNCTION_VARIANT(0x3,
+"pll-lock-dbg",


Can you stick to underscores to be consistent?


OK...
This is a so strange pin name and I just picked the datasheet
name.

I don't care how to name it as I don't even know what this is.




+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -177,11 +203,19 @@ static const struct sunxi_desc_pin 
sun4i_a10_pins[] = {

SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "pwm")),/* PWM0 */
+ SUNXI_FUNCTION_VARIANT(0x2, "pwm",  /* PWM0 */
+PINCTRL_SUN4I_A10 |
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm",  /* PWM0 */
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "ir0"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x2, "ir0",  /* TX */
+PINCTRL_SUN4I_A10 |
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm0", /* PWM1 */


The numbering is wrong. Just drop the number altogether, like all the
other instances.


+PINCTRL_SUN8I_R40),
/*
 * The SPDIF block is not referenced at all in the A10 user
 * manual. However it is described in the code leaked and the
@@ -205,7 +239,8 @@ static const struct sunxi_desc_pin 
sun4i_a10_pins[] = {

  SUNXI_FUNCTION_VARIANT(0x2, "i2s",  /* MCLK */
 PINCTRL_SUN4I_A10),
  SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
-PINCTRL_SUN7I_A20),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40),


Maybe we could use "i2s" instead, like on the A10. I don't know where
i2s1 is used, but it certainly isn't routed outside the SoC, and i2s2
looks like it's for dw-hdmi's audio path.


Nope, it's routed at PA bank, see pins start at PA14.

Changing this name will also break existing A20 device trees, if any of
them use I2S.




  SUNXI_FUNCTION(0x3, "ac97")),   /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
 

Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[Chen-Yu Tsai]

On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
> R40 is said to be an upgrade of A20, and its pin configuration is also
> similar to A20 (and thus similar to A10).
> 
> Add support for R40 to the A10 pinctrl driver.
> 
> Signed-off-by: Icenowy Zheng 
> ---
>  drivers/pinctrl/sunxi/Kconfig |   2 +-
>  drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 
> +-
>  2 files changed, 197 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 624d84e6c936..9d01da3b90bd 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -7,7 +7,7 @@ config PINCTRL_SUNXI
>   select GPIOLIB
>  
>  config PINCTRL_SUN4I_A10
> - def_bool MACH_SUN4I || MACH_SUN7I
> + def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
>   select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN5I
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
> b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
> index 159580c04b14..0f6ca8391ea7 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c

[...]

> @@ -162,14 +183,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
> SUNXI_FUNCTION(0x3, "can"),   /* RX */
> SUNXI_FUNCTION(0x4, "uart1"), /* RING */
> SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GNULL / ETXERR */
> -  PINCTRL_SUN7I_A20),
> +  PINCTRL_SUN7I_A20 |
> +  PINCTRL_SUN8I_R40),
> SUNXI_FUNCTION_VARIANT(0x6, "i2s1",   /* DI */
> -  PINCTRL_SUN7I_A20)),
> +  PINCTRL_SUN7I_A20 |
> +  PINCTRL_SUN8I_R40)),
>   /* Hole */
>   SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> -   SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
> +   SUNXI_FUNCTION(0x2, "i2c0"),  /* SCK */
> +   SUNXI_FUNCTION_VARIANT(0x3,
> +  "pll-lock-dbg",

Can you stick to underscores to be consistent?

> +  PINCTRL_SUN8I_R40)),
>   SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> @@ -177,11 +203,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
>   SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> -   SUNXI_FUNCTION(0x2, "pwm")),  /* PWM0 */
> +   SUNXI_FUNCTION_VARIANT(0x2, "pwm",/* PWM0 */
> +  PINCTRL_SUN4I_A10 |
> +  PINCTRL_SUN7I_A20),
> +   SUNXI_FUNCTION_VARIANT(0x3, "pwm",/* PWM0 */
> +  PINCTRL_SUN8I_R40)),
>   SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> -   SUNXI_FUNCTION(0x2, "ir0"),   /* TX */
> +   SUNXI_FUNCTION_VARIANT(0x2, "ir0",/* TX */
> +  PINCTRL_SUN4I_A10 |
> +  PINCTRL_SUN7I_A20),
> +   SUNXI_FUNCTION_VARIANT(0x3, "pwm0",   /* PWM1 */

The numbering is wrong. Just drop the number altogether, like all the
other instances.

> +  PINCTRL_SUN8I_R40),
>   /*
>* The SPDIF block is not referenced at all in the A10 user
>* manual. However it is described in the code leaked and the
> @@ -205,7 +239,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
> SUNXI_FUNCTION_VARIANT(0x2, "i2s",/* MCLK */
>PINCTRL_SUN4I_A10),
> SUNXI_FUNCTION_VARIANT(0x2, "i2s0",   /* MCLK */
> -  PINCTRL_SUN7I_A20),
> +  PINCTRL_SUN7I_A20 |
> +  PINCTRL_SUN8I_R40),

Maybe we could use "i2s" instead, like on the A10. I don't know where
i2s1 is used, but it certainly isn't routed outside the SoC, and i2s2
looks like it's for dw-hdmi's audio path.

> SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
>   SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> SUNXI_FUNCTION(0x0, "gpio_in"),

[...]

> @@ -237,31 +275,41 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
> SUNXI_FUNCTION_VARIANT(0x2, "i2s",/* DO1 */
>PINCTRL_SUN4I_A10),
> 

Re: [PATCH 1/8] i2c: rename core source file to allow refactorization

[Jarkko Nikula]

On 05/26/2017 11:20 AM, Wolfram Sang wrote:

--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -583,7 +583,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 */

/*
-* i2c-core.c always sets the buffer length of
+* i2c-core always sets the buffer length of
 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 * be adjusted when receiving the first byte.
 * Thus we can't stop the transaction here.


FWIW,

Acked-by: Jarkko Nikula 
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Re: [PATCH v3 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

[Chen-Yu Tsai]

On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng  wrote:
> From: Chen-Yu Tsai 
>
> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
> form factor and position of various connectors, leds and buttons is
> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
> as the latest Banana Pi M64.
>
> It features:
>
>   - X-Powers AXP221s PMIC connected to i2c0
>   - 2 GB DDR3 DRAM
>   - 8 GB eMMC
>   - micro SD card slot
>   - DC power jack
>   - HDMI output
>   - MIPI DSI connector
>   - 2x USB 2.0 hosts
>   - 1x USB 2.0 OTG
>   - gigabit ethernet with Realtek RTL8211E transceiver
>   - WiFi/Bluetooth with AP6212 chip, with external antenna connector
>   - SATA and power connectors for native SATA support
>   - camera sensor connector
>   - consumer IR receiver
>   - audio out headphone jack
>   - onboard microphone
>   - red, green, and blue LEDs
>   - debug UART pins
>   - Li-Po battery connector
>   - Raspberry Pi B+ compatible GPIO header
>   - power, reset, and boot control buttons
>
> This patch adds a dts file that enables debug UART and MMC support.
>
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Pinmux changes.
>
>  arch/arm/boot/dts/Makefile|   1 +
>  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 157 
> ++
>  2 files changed, 158 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f68d6e0bc746..697c600bba28 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -910,6 +910,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-h3-orangepi-plus.dtb \
> sun8i-h3-orangepi-plus2e.dtb \
> sun8i-r16-parrot.dtb \
> +   sun8i-r40-bananapi-m2-ultra.dtb \
> sun8i-v3s-licheepi-zero.dtb \
> sun8i-v3s-licheepi-zero-dock.dtb
>  dtb-$(CONFIG_MACH_SUN9I) += \
> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
> b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> new file mode 100644
> index ..c4e69847cea1
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright (C) 2017 Chen-Yu Tsai 
> + * Copyright (C) 2017 Icenowy Zheng 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-r40.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +/ {
> +   model = "Banana Pi BPI-M2-Ultra";
> +   compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";

The vendor prefix "bananapi" was merged into -next through Rob's DT tree:

https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?h=dt/next=79d45aed23f02022607501cd0d3c404592e027f8

Lets use that instead.

> +
> +   aliases {
> +   serial0 = 
> +   };
> +
> +   

[PATCH v2 00/11] introduce crypto wait for async op

[Gilad Ben-Yossef]

Many users of kernel async. crypto services have a pattern of
starting an async. crypto op and than using a completion
to wait for it to end, resulting of the same code repeating
itself in multiple places, sometime with coding errors.

This patch aims to introduce a generic "wait for async.
crypto op to complete" functions and move all the users
I could find to use it.  This gets rid of almost 300
lines of code and uncovered a few bugs in existing code
(separate bug fix patch set sent previously).

The patch set was boot tested on x86_64 and arm64 which
at the very least tests the crypto users via testmgr
but I am less confident regarding some of the other
users and would love more testers.
 
Changes from v1:
- Address review comments from Eric Biggers.
- Separated out bug fixes of existing code and rebase
  on top of that patch set.
- Rename 'ecr' to 'wait' in fscrypto code.
- Split patch introducing the new API from the change
  moving over the algif code which it originated from
  to the new API.
- Inline crypto_wait_req().
- Some code indentation fixes.

Gilad Ben-Yossef (11):
  crypto: introduce crypto wait for async op
  crypto: move algif to generic async completion
  crypto: move pub key to generic async completion
  crypto: move drbg to generic async completion
  crypto: move gcm to generic async completion
  crypto: move testmgr to generic async completion
  dm: move dm-verity to generic async completion
  fscrypt: move to generic async completion
  cifs: move to generic async completion
  ima: move to generic async completion
  crypto: adapt api sample to use async. op wait

 Documentation/crypto/api-samples.rst |  52 ++
 crypto/af_alg.c  |  27 -
 crypto/algif_aead.c  |  14 +--
 crypto/algif_hash.c  |  29 +++---
 crypto/algif_skcipher.c  |  15 ++-
 crypto/api.c |  13 +++
 crypto/asymmetric_keys/public_key.c  |  28 +-
 crypto/drbg.c|  34 ++-
 crypto/gcm.c |  32 ++
 crypto/testmgr.c | 184 +++
 drivers/md/dm-verity-target.c|  81 ---
 drivers/md/dm-verity.h   |   5 -
 fs/cifs/smb2ops.c|  30 +-
 fs/crypto/crypto.c   |  28 +-
 fs/crypto/fname.c|  36 ++-
 fs/crypto/fscrypt_private.h  |  10 --
 fs/crypto/keyinfo.c  |  21 +---
 include/crypto/drbg.h|   3 +-
 include/crypto/if_alg.h  |  14 ---
 include/linux/crypto.h   |  41 
 security/integrity/ima/ima_crypto.c  |  56 ---
 21 files changed, 220 insertions(+), 533 deletions(-)

-- 
2.1.4

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[PATCH v2 05/11] crypto: move gcm to generic async completion

[Gilad Ben-Yossef]

gcm is starting an async. crypto op and waiting for it complete.
Move it over to generic code doing the same.

Signed-off-by: Gilad Ben-Yossef 
---
 crypto/gcm.c | 32 ++--
 1 file changed, 6 insertions(+), 26 deletions(-)

diff --git a/crypto/gcm.c b/crypto/gcm.c
index 3841b5e..fb923a5 100644
--- a/crypto/gcm.c
+++ b/crypto/gcm.c
@@ -16,7 +16,6 @@
 #include 
 #include 
 #include "internal.h"
-#include 
 #include 
 #include 
 #include 
@@ -78,11 +77,6 @@ struct crypto_gcm_req_priv_ctx {
} u;
 };
 
-struct crypto_gcm_setkey_result {
-   int err;
-   struct completion completion;
-};
-
 static struct {
u8 buf[16];
struct scatterlist sg;
@@ -98,17 +92,6 @@ static inline struct crypto_gcm_req_priv_ctx 
*crypto_gcm_reqctx(
return (void *)PTR_ALIGN((u8 *)aead_request_ctx(req), align + 1);
 }
 
-static void crypto_gcm_setkey_done(struct crypto_async_request *req, int err)
-{
-   struct crypto_gcm_setkey_result *result = req->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   result->err = err;
-   complete(>completion);
-}
-
 static int crypto_gcm_setkey(struct crypto_aead *aead, const u8 *key,
 unsigned int keylen)
 {
@@ -119,7 +102,7 @@ static int crypto_gcm_setkey(struct crypto_aead *aead, 
const u8 *key,
be128 hash;
u8 iv[16];
 
-   struct crypto_gcm_setkey_result result;
+   struct crypto_wait wait;
 
struct scatterlist sg[1];
struct skcipher_request req;
@@ -140,21 +123,18 @@ static int crypto_gcm_setkey(struct crypto_aead *aead, 
const u8 *key,
if (!data)
return -ENOMEM;
 
-   init_completion(>result.completion);
+   crypto_init_wait(>wait);
sg_init_one(data->sg, >hash, sizeof(data->hash));
skcipher_request_set_tfm(>req, ctr);
skcipher_request_set_callback(>req, CRYPTO_TFM_REQ_MAY_SLEEP |
  CRYPTO_TFM_REQ_MAY_BACKLOG,
- crypto_gcm_setkey_done,
- >result);
+ crypto_req_done,
+ >wait);
skcipher_request_set_crypt(>req, data->sg, data->sg,
   sizeof(data->hash), data->iv);
 
-   err = crypto_skcipher_encrypt(>req);
-   if (err == -EINPROGRESS || err == -EBUSY) {
-   wait_for_completion(>result.completion);
-   err = data->result.err;
-   }
+   err = crypto_wait_req(crypto_skcipher_encrypt(>req),
+   >wait);
 
if (err)
goto out;
-- 
2.1.4

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[PATCH v2 02/11] crypto: move algif to generic async completion

[Gilad Ben-Yossef]

algif starts several async crypto ops and waits for their completion.
Move it over to generic code doing the same.

Signed-off-by: Gilad Ben-Yossef 
---
 crypto/af_alg.c | 27 ---
 crypto/algif_aead.c | 14 +++---
 crypto/algif_hash.c | 29 +
 crypto/algif_skcipher.c | 15 +++
 include/crypto/if_alg.h | 14 --
 5 files changed, 27 insertions(+), 72 deletions(-)

diff --git a/crypto/af_alg.c b/crypto/af_alg.c
index 3556d8e..bf4acaf 100644
--- a/crypto/af_alg.c
+++ b/crypto/af_alg.c
@@ -480,33 +480,6 @@ int af_alg_cmsg_send(struct msghdr *msg, struct 
af_alg_control *con)
 }
 EXPORT_SYMBOL_GPL(af_alg_cmsg_send);
 
-int af_alg_wait_for_completion(int err, struct af_alg_completion *completion)
-{
-   switch (err) {
-   case -EINPROGRESS:
-   case -EBUSY:
-   wait_for_completion(>completion);
-   reinit_completion(>completion);
-   err = completion->err;
-   break;
-   };
-
-   return err;
-}
-EXPORT_SYMBOL_GPL(af_alg_wait_for_completion);
-
-void af_alg_complete(struct crypto_async_request *req, int err)
-{
-   struct af_alg_completion *completion = req->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   completion->err = err;
-   complete(>completion);
-}
-EXPORT_SYMBOL_GPL(af_alg_complete);
-
 static int __init af_alg_init(void)
 {
int err = proto_register(_proto, 0);
diff --git a/crypto/algif_aead.c b/crypto/algif_aead.c
index 8af664f..677b336 100644
--- a/crypto/algif_aead.c
+++ b/crypto/algif_aead.c
@@ -57,7 +57,7 @@ struct aead_ctx {
 
void *iv;
 
-   struct af_alg_completion completion;
+   struct crypto_wait wait;
 
unsigned long used;
 
@@ -648,10 +648,10 @@ static int aead_recvmsg_sync(struct socket *sock, struct 
msghdr *msg, int flags)
   used, ctx->iv);
aead_request_set_ad(>aead_req, ctx->aead_assoclen);
 
-   err = af_alg_wait_for_completion(ctx->enc ?
-crypto_aead_encrypt(>aead_req) :
-crypto_aead_decrypt(>aead_req),
->completion);
+   err = crypto_wait_req(ctx->enc ?
+crypto_aead_encrypt(>aead_req) :
+crypto_aead_decrypt(>aead_req),
+>wait);
 
if (err) {
/* EBADMSG implies a valid cipher operation took place */
@@ -912,7 +912,7 @@ static int aead_accept_parent_nokey(void *private, struct 
sock *sk)
ctx->enc = 0;
ctx->tsgl.cur = 0;
ctx->aead_assoclen = 0;
-   af_alg_init_completion(>completion);
+   crypto_init_wait(>wait);
sg_init_table(ctx->tsgl.sg, ALG_MAX_PAGES);
INIT_LIST_HEAD(>list);
 
@@ -920,7 +920,7 @@ static int aead_accept_parent_nokey(void *private, struct 
sock *sk)
 
aead_request_set_tfm(>aead_req, aead);
aead_request_set_callback(>aead_req, CRYPTO_TFM_REQ_MAY_BACKLOG,
- af_alg_complete, >completion);
+ crypto_req_done, >wait);
 
sk->sk_destruct = aead_sock_destruct;
 
diff --git a/crypto/algif_hash.c b/crypto/algif_hash.c
index 5e92bd2..a2fa6d1 100644
--- a/crypto/algif_hash.c
+++ b/crypto/algif_hash.c
@@ -26,7 +26,7 @@ struct hash_ctx {
 
u8 *result;
 
-   struct af_alg_completion completion;
+   struct crypto_wait wait;
 
unsigned int len;
bool more;
@@ -88,8 +88,7 @@ static int hash_sendmsg(struct socket *sock, struct msghdr 
*msg,
if ((msg->msg_flags & MSG_MORE))
hash_free_result(sk, ctx);
 
-   err = af_alg_wait_for_completion(crypto_ahash_init(>req),
-   >completion);
+   err = crypto_wait_req(crypto_ahash_init(>req), >wait);
if (err)
goto unlock;
}
@@ -110,8 +109,8 @@ static int hash_sendmsg(struct socket *sock, struct msghdr 
*msg,
 
ahash_request_set_crypt(>req, ctx->sgl.sg, NULL, len);
 
-   err = af_alg_wait_for_completion(crypto_ahash_update(>req),
->completion);
+   err = crypto_wait_req(crypto_ahash_update(>req),
+   >wait);
af_alg_free_sg(>sgl);
if (err)
goto unlock;
@@ -129,8 +128,8 @@ static int hash_sendmsg(struct socket *sock, struct msghdr 
*msg,
goto unlock;
 
ahash_request_set_crypt(>req, NULL, ctx->result, 0);
-   err = af_alg_wait_for_completion(crypto_ahash_final(>req),
->completion);
+   err = crypto_wait_req(crypto_ahash_final(>req),
+ 

[PATCH v2 03/11] crypto: move pub key to generic async completion

[Gilad Ben-Yossef]

public_key_verify_signature() is starting an async crypto op and
waiting for it to complete. Move it over to generic code doing
the same.

Signed-off-by: Gilad Ben-Yossef 
---
 crypto/asymmetric_keys/public_key.c | 28 
 1 file changed, 4 insertions(+), 24 deletions(-)

diff --git a/crypto/asymmetric_keys/public_key.c 
b/crypto/asymmetric_keys/public_key.c
index 3cd6e12..d916235 100644
--- a/crypto/asymmetric_keys/public_key.c
+++ b/crypto/asymmetric_keys/public_key.c
@@ -57,29 +57,13 @@ static void public_key_destroy(void *payload0, void 
*payload3)
public_key_signature_free(payload3);
 }
 
-struct public_key_completion {
-   struct completion completion;
-   int err;
-};
-
-static void public_key_verify_done(struct crypto_async_request *req, int err)
-{
-   struct public_key_completion *compl = req->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   compl->err = err;
-   complete(>completion);
-}
-
 /*
  * Verify a signature using a public key.
  */
 int public_key_verify_signature(const struct public_key *pkey,
const struct public_key_signature *sig)
 {
-   struct public_key_completion compl;
+   struct crypto_wait cwait;
struct crypto_akcipher *tfm;
struct akcipher_request *req;
struct scatterlist sig_sg, digest_sg;
@@ -131,20 +115,16 @@ int public_key_verify_signature(const struct public_key 
*pkey,
sg_init_one(_sg, output, outlen);
akcipher_request_set_crypt(req, _sg, _sg, sig->s_size,
   outlen);
-   init_completion();
+   crypto_init_wait();
akcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
  CRYPTO_TFM_REQ_MAY_SLEEP,
- public_key_verify_done, );
+ crypto_req_done, );
 
/* Perform the verification calculation.  This doesn't actually do the
 * verification, but rather calculates the hash expected by the
 * signature and returns that to us.
 */
-   ret = crypto_akcipher_verify(req);
-   if ((ret == -EINPROGRESS) || (ret == -EBUSY)) {
-   wait_for_completion();
-   ret = compl.err;
-   }
+   ret = crypto_wait_req(crypto_akcipher_verify(req), );
if (ret < 0)
goto out_free_output;
 
-- 
2.1.4

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[PATCH v2 04/11] crypto: move drbg to generic async completion

[Gilad Ben-Yossef]

DRBG is starting an async. crypto op and waiting for it complete.
Move it over to generic code doing the same.

The code now also passes CRYPTO_TFM_REQ_MAY_SLEEP flag indicating
crypto request memory allocation may use GFP_KERNEL which should
be perfectly fine as the code is obviously sleeping for the
completion of the request any way.

Signed-off-by: Gilad Ben-Yossef 
---
 crypto/drbg.c | 34 --
 include/crypto/drbg.h |  3 +--
 2 files changed, 9 insertions(+), 28 deletions(-)

diff --git a/crypto/drbg.c b/crypto/drbg.c
index cdb27ac..101d9f0 100644
--- a/crypto/drbg.c
+++ b/crypto/drbg.c
@@ -1651,16 +1651,6 @@ static int drbg_fini_sym_kernel(struct drbg_state *drbg)
return 0;
 }
 
-static void drbg_skcipher_cb(struct crypto_async_request *req, int error)
-{
-   struct drbg_state *drbg = req->data;
-
-   if (error == -EINPROGRESS)
-   return;
-   drbg->ctr_async_err = error;
-   complete(>ctr_completion);
-}
-
 static int drbg_init_sym_kernel(struct drbg_state *drbg)
 {
struct crypto_cipher *tfm;
@@ -1699,8 +1689,9 @@ static int drbg_init_sym_kernel(struct drbg_state *drbg)
return -ENOMEM;
}
drbg->ctr_req = req;
-   skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
-   drbg_skcipher_cb, drbg);
+   skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
+   CRYPTO_TFM_REQ_MAY_SLEEP,
+   crypto_req_done, >ctr_wait);
 
alignmask = crypto_skcipher_alignmask(sk_tfm);
drbg->ctr_null_value_buf = kzalloc(DRBG_CTR_NULL_LEN + alignmask,
@@ -1761,21 +1752,12 @@ static int drbg_kcapi_sym_ctr(struct drbg_state *drbg,
/* Output buffer may not be valid for SGL, use scratchpad */
skcipher_request_set_crypt(drbg->ctr_req, _in, _out,
   cryptlen, drbg->V);
-   ret = crypto_skcipher_encrypt(drbg->ctr_req);
-   switch (ret) {
-   case 0:
-   break;
-   case -EINPROGRESS:
-   case -EBUSY:
-   wait_for_completion(>ctr_completion);
-   if (!drbg->ctr_async_err) {
-   reinit_completion(>ctr_completion);
-   break;
-   }
-   default:
+   ret = crypto_wait_req(crypto_skcipher_encrypt(drbg->ctr_req),
+   >ctr_wait);
+   if (ret)
goto out;
-   }
-   init_completion(>ctr_completion);
+
+   crypto_init_wait(>ctr_wait);
 
memcpy(outbuf, drbg->outscratchpad, cryptlen);
 
diff --git a/include/crypto/drbg.h b/include/crypto/drbg.h
index 22f884c..8f94110 100644
--- a/include/crypto/drbg.h
+++ b/include/crypto/drbg.h
@@ -126,8 +126,7 @@ struct drbg_state {
__u8 *ctr_null_value;   /* CTR mode aligned zero buf */
__u8 *outscratchpadbuf; /* CTR mode output scratchpad */
 __u8 *outscratchpad;   /* CTR mode aligned outbuf */
-   struct completion ctr_completion;   /* CTR mode async handler */
-   int ctr_async_err;  /* CTR mode async error */
+   struct crypto_wait ctr_wait;/* CTR mode async wait obj */
 
bool seeded;/* DRBG fully seeded? */
bool pr;/* Prediction resistance enabled? */
-- 
2.1.4

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[PATCH v2 06/11] crypto: move testmgr to generic async completion

[Gilad Ben-Yossef]

testmgr is starting async. crypto ops and waiting for them to complete.
Move it over to generic code doing the same.

This also provides a test of the generic crypto async. wait code.

Signed-off-by: Gilad Ben-Yossef 
---
 crypto/testmgr.c | 184 +--
 1 file changed, 56 insertions(+), 128 deletions(-)

diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 6f5f3ed..4b779ca 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -76,11 +76,6 @@ int alg_test(const char *driver, const char *alg, u32 type, 
u32 mask)
 #define ENCRYPT 1
 #define DECRYPT 0
 
-struct tcrypt_result {
-   struct completion completion;
-   int err;
-};
-
 struct aead_test_suite {
struct {
const struct aead_testvec *vecs;
@@ -155,17 +150,6 @@ static void hexdump(unsigned char *buf, unsigned int len)
buf, len, false);
 }
 
-static void tcrypt_complete(struct crypto_async_request *req, int err)
-{
-   struct tcrypt_result *res = req->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   res->err = err;
-   complete(>completion);
-}
-
 static int testmgr_alloc_buf(char *buf[XBUFSIZE])
 {
int i;
@@ -193,20 +177,10 @@ static void testmgr_free_buf(char *buf[XBUFSIZE])
free_page((unsigned long)buf[i]);
 }
 
-static int wait_async_op(struct tcrypt_result *tr, int ret)
-{
-   if (ret == -EINPROGRESS || ret == -EBUSY) {
-   wait_for_completion(>completion);
-   reinit_completion(>completion);
-   ret = tr->err;
-   }
-   return ret;
-}
-
 static int ahash_partial_update(struct ahash_request **preq,
struct crypto_ahash *tfm, const struct hash_testvec *template,
void *hash_buff, int k, int temp, struct scatterlist *sg,
-   const char *algo, char *result, struct tcrypt_result *tresult)
+   const char *algo, char *result, struct crypto_wait *wait)
 {
char *state;
struct ahash_request *req;
@@ -236,7 +210,7 @@ static int ahash_partial_update(struct ahash_request **preq,
}
ahash_request_set_callback(req,
CRYPTO_TFM_REQ_MAY_BACKLOG,
-   tcrypt_complete, tresult);
+   crypto_req_done, wait);
 
memcpy(hash_buff, template->plaintext + temp,
template->tap[k]);
@@ -247,7 +221,7 @@ static int ahash_partial_update(struct ahash_request **preq,
pr_err("alg: hash: Failed to import() for %s\n", algo);
goto out;
}
-   ret = wait_async_op(tresult, crypto_ahash_update(req));
+   ret = crypto_wait_req(crypto_ahash_update(req), wait);
if (ret)
goto out;
*preq = req;
@@ -272,7 +246,7 @@ static int __test_hash(struct crypto_ahash *tfm,
char *result;
char *key;
struct ahash_request *req;
-   struct tcrypt_result tresult;
+   struct crypto_wait wait;
void *hash_buff;
char *xbuf[XBUFSIZE];
int ret = -ENOMEM;
@@ -286,7 +260,7 @@ static int __test_hash(struct crypto_ahash *tfm,
if (testmgr_alloc_buf(xbuf))
goto out_nobuf;
 
-   init_completion();
+   crypto_init_wait();
 
req = ahash_request_alloc(tfm, GFP_KERNEL);
if (!req) {
@@ -295,7 +269,7 @@ static int __test_hash(struct crypto_ahash *tfm,
goto out_noreq;
}
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
-  tcrypt_complete, );
+  crypto_req_done, );
 
j = 0;
for (i = 0; i < tcount; i++) {
@@ -335,26 +309,26 @@ static int __test_hash(struct crypto_ahash *tfm,
 
ahash_request_set_crypt(req, sg, result, template[i].psize);
if (use_digest) {
-   ret = wait_async_op(, crypto_ahash_digest(req));
+   ret = crypto_wait_req(crypto_ahash_digest(req), );
if (ret) {
pr_err("alg: hash: digest failed on test %d "
   "for %s: ret=%d\n", j, algo, -ret);
goto out;
}
} else {
-   ret = wait_async_op(, crypto_ahash_init(req));
+   ret = crypto_wait_req(crypto_ahash_init(req), );
if (ret) {
pr_err("alt: hash: init failed on test %d "
   "for %s: ret=%d\n", j, algo, -ret);
goto out;
}
-   ret = wait_async_op(, crypto_ahash_update(req));
+   ret = crypto_wait_req(crypto_ahash_update(req), );
if (ret) {
pr_err("alt: hash: update failed on test %d "
  

[PATCH v2 08/11] fscrypt: move to generic async completion

[Gilad Ben-Yossef]

fscrypt starts several async. crypto ops and waiting for them to
complete. Move it over to generic code doing the same.

Signed-off-by: Gilad Ben-Yossef 
---
 fs/crypto/crypto.c  | 28 
 fs/crypto/fname.c   | 36 ++--
 fs/crypto/fscrypt_private.h | 10 --
 fs/crypto/keyinfo.c | 21 +++--
 4 files changed, 13 insertions(+), 82 deletions(-)

diff --git a/fs/crypto/crypto.c b/fs/crypto/crypto.c
index 6d6eca3..227db85 100644
--- a/fs/crypto/crypto.c
+++ b/fs/crypto/crypto.c
@@ -125,21 +125,6 @@ struct fscrypt_ctx *fscrypt_get_ctx(const struct inode 
*inode, gfp_t gfp_flags)
 }
 EXPORT_SYMBOL(fscrypt_get_ctx);
 
-/**
- * page_crypt_complete() - completion callback for page crypto
- * @req: The asynchronous cipher request context
- * @res: The result of the cipher operation
- */
-static void page_crypt_complete(struct crypto_async_request *req, int res)
-{
-   struct fscrypt_completion_result *ecr = req->data;
-
-   if (res == -EINPROGRESS)
-   return;
-   ecr->res = res;
-   complete(>completion);
-}
-
 int fscrypt_do_page_crypto(const struct inode *inode, fscrypt_direction_t rw,
   u64 lblk_num, struct page *src_page,
   struct page *dest_page, unsigned int len,
@@ -150,7 +135,7 @@ int fscrypt_do_page_crypto(const struct inode *inode, 
fscrypt_direction_t rw,
u8 padding[FS_XTS_TWEAK_SIZE - sizeof(__le64)];
} xts_tweak;
struct skcipher_request *req = NULL;
-   DECLARE_FS_COMPLETION_RESULT(ecr);
+   DECLARE_CRYPTO_WAIT(wait);
struct scatterlist dst, src;
struct fscrypt_info *ci = inode->i_crypt_info;
struct crypto_skcipher *tfm = ci->ci_ctfm;
@@ -168,7 +153,7 @@ int fscrypt_do_page_crypto(const struct inode *inode, 
fscrypt_direction_t rw,
 
skcipher_request_set_callback(
req, CRYPTO_TFM_REQ_MAY_BACKLOG | CRYPTO_TFM_REQ_MAY_SLEEP,
-   page_crypt_complete, );
+   crypto_req_done, );
 
BUILD_BUG_ON(sizeof(xts_tweak) != FS_XTS_TWEAK_SIZE);
xts_tweak.index = cpu_to_le64(lblk_num);
@@ -180,14 +165,9 @@ int fscrypt_do_page_crypto(const struct inode *inode, 
fscrypt_direction_t rw,
sg_set_page(, src_page, len, offs);
skcipher_request_set_crypt(req, , , len, _tweak);
if (rw == FS_DECRYPT)
-   res = crypto_skcipher_decrypt(req);
+   res = crypto_wait_req(crypto_skcipher_decrypt(req), );
else
-   res = crypto_skcipher_encrypt(req);
-   if (res == -EINPROGRESS || res == -EBUSY) {
-   BUG_ON(req->base.data != );
-   wait_for_completion();
-   res = ecr.res;
-   }
+   res = crypto_wait_req(crypto_skcipher_encrypt(req), );
skcipher_request_free(req);
if (res) {
printk_ratelimited(KERN_ERR
diff --git a/fs/crypto/fname.c b/fs/crypto/fname.c
index d1bb02b..d5732c9 100644
--- a/fs/crypto/fname.c
+++ b/fs/crypto/fname.c
@@ -15,21 +15,6 @@
 #include "fscrypt_private.h"
 
 /**
- * fname_crypt_complete() - completion callback for filename crypto
- * @req: The asynchronous cipher request context
- * @res: The result of the cipher operation
- */
-static void fname_crypt_complete(struct crypto_async_request *req, int res)
-{
-   struct fscrypt_completion_result *ecr = req->data;
-
-   if (res == -EINPROGRESS)
-   return;
-   ecr->res = res;
-   complete(>completion);
-}
-
-/**
  * fname_encrypt() - encrypt a filename
  *
  * The caller must have allocated sufficient memory for the @oname string.
@@ -40,7 +25,7 @@ static int fname_encrypt(struct inode *inode,
const struct qstr *iname, struct fscrypt_str *oname)
 {
struct skcipher_request *req = NULL;
-   DECLARE_FS_COMPLETION_RESULT(ecr);
+   DECLARE_CRYPTO_WAIT(ecr);
struct fscrypt_info *ci = inode->i_crypt_info;
struct crypto_skcipher *tfm = ci->ci_ctfm;
int res = 0;
@@ -76,17 +61,12 @@ static int fname_encrypt(struct inode *inode,
}
skcipher_request_set_callback(req,
CRYPTO_TFM_REQ_MAY_BACKLOG | CRYPTO_TFM_REQ_MAY_SLEEP,
-   fname_crypt_complete, );
+   crypto_req_done, );
sg_init_one(, oname->name, cryptlen);
skcipher_request_set_crypt(req, , , cryptlen, iv);
 
/* Do the encryption */
-   res = crypto_skcipher_encrypt(req);
-   if (res == -EINPROGRESS || res == -EBUSY) {
-   /* Request is being completed asynchronously; wait for it */
-   wait_for_completion();
-   res = ecr.res;
-   }
+   res = crypto_wait_req(crypto_skcipher_encrypt(req), );
skcipher_request_free(req);
if (res < 0) {
printk_ratelimited(KERN_ERR
@@ -110,7 +90,7 @@ 

[PATCH v2 11/11] crypto: adapt api sample to use async. op wait

[Gilad Ben-Yossef]

The code sample is waiting for an async. crypto op completion.
Adapt sample to use the new generic infrastructure to do the same.

This also fixes a possible data coruption bug created by the
use of wait_for_completion_interruptible() without dealing
correctly with an interrupt aborting the wait prior to the
async op finishing.

Signed-off-by: Gilad Ben-Yossef 
---
 Documentation/crypto/api-samples.rst | 52 +++-
 1 file changed, 10 insertions(+), 42 deletions(-)

diff --git a/Documentation/crypto/api-samples.rst 
b/Documentation/crypto/api-samples.rst
index d021fd9..73b466b 100644
--- a/Documentation/crypto/api-samples.rst
+++ b/Documentation/crypto/api-samples.rst
@@ -7,59 +7,27 @@ Code Example For Symmetric Key Cipher Operation
 ::
 
 
-struct tcrypt_result {
-struct completion completion;
-int err;
-};
-
 /* tie all data structures together */
 struct skcipher_def {
 struct scatterlist sg;
 struct crypto_skcipher *tfm;
 struct skcipher_request *req;
-struct tcrypt_result result;
+struct crypto_wait wait;
 };
 
-/* Callback function */
-static void test_skcipher_cb(struct crypto_async_request *req, int error)
-{
-struct tcrypt_result *result = req->data;
-
-if (error == -EINPROGRESS)
-return;
-result->err = error;
-complete(>completion);
-pr_info("Encryption finished successfully\n");
-}
-
 /* Perform cipher operation */
 static unsigned int test_skcipher_encdec(struct skcipher_def *sk,
  int enc)
 {
-int rc = 0;
+int rc;
 
 if (enc)
-rc = crypto_skcipher_encrypt(sk->req);
+rc = crypto_wait_req(crypto_skcipher_encrypt(sk->req), >wait);
 else
-rc = crypto_skcipher_decrypt(sk->req);
-
-switch (rc) {
-case 0:
-break;
-case -EINPROGRESS:
-case -EBUSY:
-rc = wait_for_completion_interruptible(
->result.completion);
-if (!rc && !sk->result.err) {
-reinit_completion(>result.completion);
-break;
-}
-default:
-pr_info("skcipher encrypt returned with %d result %d\n",
-rc, sk->result.err);
-break;
-}
-init_completion(>result.completion);
+rc = crypto_wait_req(crypto_skcipher_decrypt(sk->req), >wait);
+
+   if (rc)
+   pr_info("skcipher encrypt returned with result %d\n", rc);
 
 return rc;
 }
@@ -89,8 +57,8 @@ Code Example For Symmetric Key Cipher Operation
 }
 
 skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
-  test_skcipher_cb,
-  );
+  crypto_req_done,
+  );
 
 /* AES 256 with random key */
 get_random_bytes(, 32);
@@ -122,7 +90,7 @@ Code Example For Symmetric Key Cipher Operation
 /* We encrypt one block */
 sg_init_one(, scratchpad, 16);
 skcipher_request_set_crypt(req, , , 16, ivdata);
-init_completion();
+crypto_init_wait();
 
 /* encrypt data */
 ret = test_skcipher_encdec(, 1);
-- 
2.1.4

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[PATCH v2 07/11] dm: move dm-verity to generic async completion

[Gilad Ben-Yossef]

dm-verity is starting async. crypto ops and waiting for them to complete.
Move it over to generic code doing the same.

This also fixes a possible data coruption bug created by the
use of wait_for_completion_interruptible() without dealing
correctly with an interrupt aborting the wait prior to the
async op finishing.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/md/dm-verity-target.c | 81 +++
 drivers/md/dm-verity.h|  5 ---
 2 files changed, 20 insertions(+), 66 deletions(-)

diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c
index 1ec9b2c..f183b43 100644
--- a/drivers/md/dm-verity-target.c
+++ b/drivers/md/dm-verity-target.c
@@ -92,74 +92,33 @@ static sector_t verity_position_at_level(struct dm_verity 
*v, sector_t block,
return block >> (level * v->hash_per_block_bits);
 }
 
-/*
- * Callback function for asynchrnous crypto API completion notification
- */
-static void verity_op_done(struct crypto_async_request *base, int err)
-{
-   struct verity_result *res = (struct verity_result *)base->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   res->err = err;
-   complete(>completion);
-}
-
-/*
- * Wait for async crypto API callback
- */
-static inline int verity_complete_op(struct verity_result *res, int ret)
-{
-   switch (ret) {
-   case 0:
-   break;
-
-   case -EINPROGRESS:
-   case -EBUSY:
-   ret = wait_for_completion_interruptible(>completion);
-   if (!ret)
-   ret = res->err;
-   reinit_completion(>completion);
-   break;
-
-   default:
-   DMERR("verity_wait_hash: crypto op submission failed: %d", ret);
-   }
-
-   if (unlikely(ret < 0))
-   DMERR("verity_wait_hash: crypto op failed: %d", ret);
-
-   return ret;
-}
-
 static int verity_hash_update(struct dm_verity *v, struct ahash_request *req,
const u8 *data, size_t len,
-   struct verity_result *res)
+   struct crypto_wait *wait)
 {
struct scatterlist sg;
 
sg_init_one(, data, len);
ahash_request_set_crypt(req, , NULL, len);
 
-   return verity_complete_op(res, crypto_ahash_update(req));
+   return crypto_wait_req(crypto_ahash_update(req), wait);
 }
 
 /*
  * Wrapper for crypto_ahash_init, which handles verity salting.
  */
 static int verity_hash_init(struct dm_verity *v, struct ahash_request *req,
-   struct verity_result *res)
+   struct crypto_wait *wait)
 {
int r;
 
ahash_request_set_tfm(req, v->tfm);
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_SLEEP |
CRYPTO_TFM_REQ_MAY_BACKLOG,
-   verity_op_done, (void *)res);
-   init_completion(>completion);
+   crypto_req_done, (void *)wait);
+   crypto_init_wait(wait);
 
-   r = verity_complete_op(res, crypto_ahash_init(req));
+   r = crypto_wait_req(crypto_ahash_init(req), wait);
 
if (unlikely(r < 0)) {
DMERR("crypto_ahash_init failed: %d", r);
@@ -167,18 +126,18 @@ static int verity_hash_init(struct dm_verity *v, struct 
ahash_request *req,
}
 
if (likely(v->salt_size && (v->version >= 1)))
-   r = verity_hash_update(v, req, v->salt, v->salt_size, res);
+   r = verity_hash_update(v, req, v->salt, v->salt_size, wait);
 
return r;
 }
 
 static int verity_hash_final(struct dm_verity *v, struct ahash_request *req,
-u8 *digest, struct verity_result *res)
+u8 *digest, struct crypto_wait *wait)
 {
int r;
 
if (unlikely(v->salt_size && (!v->version))) {
-   r = verity_hash_update(v, req, v->salt, v->salt_size, res);
+   r = verity_hash_update(v, req, v->salt, v->salt_size, wait);
 
if (r < 0) {
DMERR("verity_hash_final failed updating salt: %d", r);
@@ -187,7 +146,7 @@ static int verity_hash_final(struct dm_verity *v, struct 
ahash_request *req,
}
 
ahash_request_set_crypt(req, NULL, digest, 0);
-   r = verity_complete_op(res, crypto_ahash_final(req));
+   r = crypto_wait_req(crypto_ahash_final(req), wait);
 out:
return r;
 }
@@ -196,17 +155,17 @@ int verity_hash(struct dm_verity *v, struct ahash_request 
*req,
const u8 *data, size_t len, u8 *digest)
 {
int r;
-   struct verity_result res;
+   struct crypto_wait wait;
 
-   r = verity_hash_init(v, req, );
+   r = verity_hash_init(v, req, );
if (unlikely(r < 0))
goto out;
 
-   r = verity_hash_update(v, req, data, len, );
+   r = verity_hash_update(v, req, 

[PATCH v2 09/11] cifs: move to generic async completion

[Gilad Ben-Yossef]

cifs starts an async. crypto op and waits for their completion.
Move it over to generic code doing the same.

Signed-off-by: Gilad Ben-Yossef 
Acked-by: Pavel Shilovsky 
---
 fs/cifs/smb2ops.c | 30 --
 1 file changed, 4 insertions(+), 26 deletions(-)

diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index c586918..c0e1882 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -1707,22 +1707,6 @@ init_sg(struct smb_rqst *rqst, u8 *sign)
return sg;
 }
 
-struct cifs_crypt_result {
-   int err;
-   struct completion completion;
-};
-
-static void cifs_crypt_complete(struct crypto_async_request *req, int err)
-{
-   struct cifs_crypt_result *res = req->data;
-
-   if (err == -EINPROGRESS)
-   return;
-
-   res->err = err;
-   complete(>completion);
-}
-
 static int
 smb2_get_enc_key(struct TCP_Server_Info *server, __u64 ses_id, int enc, u8 
*key)
 {
@@ -1763,12 +1747,10 @@ crypt_message(struct TCP_Server_Info *server, struct 
smb_rqst *rqst, int enc)
struct aead_request *req;
char *iv;
unsigned int iv_len;
-   struct cifs_crypt_result result = {0, };
+   DECLARE_CRYPTO_WAIT(wait);
struct crypto_aead *tfm;
unsigned int crypt_len = le32_to_cpu(tr_hdr->OriginalMessageSize);
 
-   init_completion();
-
rc = smb2_get_enc_key(server, tr_hdr->SessionId, enc, key);
if (rc) {
cifs_dbg(VFS, "%s: Could not get %scryption key\n", __func__,
@@ -1826,14 +1808,10 @@ crypt_message(struct TCP_Server_Info *server, struct 
smb_rqst *rqst, int enc)
aead_request_set_ad(req, assoc_data_len);
 
aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
- cifs_crypt_complete, );
+ crypto_req_done, );
 
-   rc = enc ? crypto_aead_encrypt(req) : crypto_aead_decrypt(req);
-
-   if (rc == -EINPROGRESS || rc == -EBUSY) {
-   wait_for_completion();
-   rc = result.err;
-   }
+   rc = crypto_wait_req(enc ? crypto_aead_encrypt(req)
+   : crypto_aead_decrypt(req), );
 
if (!rc && enc)
memcpy(_hdr->Signature, sign, SMB2_SIGNATURE_SIZE);
-- 
2.1.4

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[PATCH v2 10/11] ima: move to generic async completion

[Gilad Ben-Yossef]

ima starts several async crypto ops and  waits for their completions.
Move it over to generic code doing the same.

Signed-off-by: Gilad Ben-Yossef 
Acked-by: Mimi Zohar 
---
 security/integrity/ima/ima_crypto.c | 56 +++--
 1 file changed, 17 insertions(+), 39 deletions(-)

diff --git a/security/integrity/ima/ima_crypto.c 
b/security/integrity/ima/ima_crypto.c
index 802d5d2..0e4db1fe 100644
--- a/security/integrity/ima/ima_crypto.c
+++ b/security/integrity/ima/ima_crypto.c
@@ -27,11 +27,6 @@
 
 #include "ima.h"
 
-struct ahash_completion {
-   struct completion completion;
-   int err;
-};
-
 /* minimum file size for ahash use */
 static unsigned long ima_ahash_minsize;
 module_param_named(ahash_minsize, ima_ahash_minsize, ulong, 0644);
@@ -196,30 +191,13 @@ static void ima_free_atfm(struct crypto_ahash *tfm)
crypto_free_ahash(tfm);
 }
 
-static void ahash_complete(struct crypto_async_request *req, int err)
+static inline int ahash_wait(int err, struct crypto_wait *wait)
 {
-   struct ahash_completion *res = req->data;
 
-   if (err == -EINPROGRESS)
-   return;
-   res->err = err;
-   complete(>completion);
-}
+   err = crypto_wait_req(err, wait);
 
-static int ahash_wait(int err, struct ahash_completion *res)
-{
-   switch (err) {
-   case 0:
-   break;
-   case -EINPROGRESS:
-   case -EBUSY:
-   wait_for_completion(>completion);
-   reinit_completion(>completion);
-   err = res->err;
-   /* fall through */
-   default:
+   if (err)
pr_crit_ratelimited("ahash calculation failed: err: %d\n", err);
-   }
 
return err;
 }
@@ -233,7 +211,7 @@ static int ima_calc_file_hash_atfm(struct file *file,
int rc, read = 0, rbuf_len, active = 0, ahash_rc = 0;
struct ahash_request *req;
struct scatterlist sg[1];
-   struct ahash_completion res;
+   struct crypto_wait wait;
size_t rbuf_size[2];
 
hash->length = crypto_ahash_digestsize(tfm);
@@ -242,12 +220,12 @@ static int ima_calc_file_hash_atfm(struct file *file,
if (!req)
return -ENOMEM;
 
-   init_completion();
+   crypto_init_wait();
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
   CRYPTO_TFM_REQ_MAY_SLEEP,
-  ahash_complete, );
+  crypto_req_done, );
 
-   rc = ahash_wait(crypto_ahash_init(req), );
+   rc = ahash_wait(crypto_ahash_init(req), );
if (rc)
goto out1;
 
@@ -288,7 +266,7 @@ static int ima_calc_file_hash_atfm(struct file *file,
 * read/request, wait for the completion of the
 * previous ahash_update() request.
 */
-   rc = ahash_wait(ahash_rc, );
+   rc = ahash_wait(ahash_rc, );
if (rc)
goto out3;
}
@@ -304,7 +282,7 @@ static int ima_calc_file_hash_atfm(struct file *file,
 * read/request, wait for the completion of the
 * previous ahash_update() request.
 */
-   rc = ahash_wait(ahash_rc, );
+   rc = ahash_wait(ahash_rc, );
if (rc)
goto out3;
}
@@ -318,7 +296,7 @@ static int ima_calc_file_hash_atfm(struct file *file,
active = !active; /* swap buffers, if we use two */
}
/* wait for the last update request to complete */
-   rc = ahash_wait(ahash_rc, );
+   rc = ahash_wait(ahash_rc, );
 out3:
if (read)
file->f_mode &= ~FMODE_READ;
@@ -327,7 +305,7 @@ static int ima_calc_file_hash_atfm(struct file *file,
 out2:
if (!rc) {
ahash_request_set_crypt(req, NULL, hash->digest, 0);
-   rc = ahash_wait(crypto_ahash_final(req), );
+   rc = ahash_wait(crypto_ahash_final(req), );
}
 out1:
ahash_request_free(req);
@@ -527,7 +505,7 @@ static int calc_buffer_ahash_atfm(const void *buf, loff_t 
len,
 {
struct ahash_request *req;
struct scatterlist sg;
-   struct ahash_completion res;
+   struct crypto_wait wait;
int rc, ahash_rc = 0;
 
hash->length = crypto_ahash_digestsize(tfm);
@@ -536,12 +514,12 @@ static int calc_buffer_ahash_atfm(const void *buf, loff_t 
len,
if (!req)
return -ENOMEM;
 
-   init_completion();
+   crypto_init_wait();
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
   CRYPTO_TFM_REQ_MAY_SLEEP,
-  ahash_complete, );
+  

[PATCH v2 01/11] crypto: introduce crypto wait for async op

[Gilad Ben-Yossef]

Invoking a possibly async. crypto op and waiting for completion
while correctly handling backlog processing is a common task
in the crypto API implementation and outside users of it.

This patch adds a generic implementation for doing so in
preparation for using it across the board instead of hand
rolled versions.

Signed-off-by: Gilad Ben-Yossef 
CC: Eric Biggers 
CC: Ofir Drang 
---
 crypto/api.c   | 13 +
 include/linux/crypto.h | 41 +
 2 files changed, 54 insertions(+)

diff --git a/crypto/api.c b/crypto/api.c
index 941cd4c..2a2479d 100644
--- a/crypto/api.c
+++ b/crypto/api.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "internal.h"
 
 LIST_HEAD(crypto_alg_list);
@@ -595,5 +596,17 @@ int crypto_has_alg(const char *name, u32 type, u32 mask)
 }
 EXPORT_SYMBOL_GPL(crypto_has_alg);
 
+void crypto_req_done(struct crypto_async_request *req, int err)
+{
+   struct crypto_wait *wait = req->data;
+
+   if (err == -EINPROGRESS)
+   return;
+
+   wait->err = err;
+   complete(>completion);
+}
+EXPORT_SYMBOL_GPL(crypto_req_done);
+
 MODULE_DESCRIPTION("Cryptographic core API");
 MODULE_LICENSE("GPL");
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 84da997..bb00186 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * Autoloaded crypto modules should only use a prefixed name to avoid allowing
@@ -468,6 +469,45 @@ struct crypto_alg {
 } CRYPTO_MINALIGN_ATTR;
 
 /*
+ * A helper struct for waiting for completion of async crypto ops
+ */
+struct crypto_wait {
+   struct completion completion;
+   int err;
+};
+
+/*
+ * Macro for declaring a crypto op async wait object on stack
+ */
+#define DECLARE_CRYPTO_WAIT(_wait) \
+   struct crypto_wait _wait = { \
+   COMPLETION_INITIALIZER_ONSTACK((_wait).completion), 0 }
+
+/*
+ * Async ops completion helper functioons
+ */
+void crypto_req_done(struct crypto_async_request *req, int err);
+
+static inline int crypto_wait_req(int err, struct crypto_wait *wait)
+{
+   switch (err) {
+   case -EINPROGRESS:
+   case -EBUSY:
+   wait_for_completion(>completion);
+   reinit_completion(>completion);
+   err = wait->err;
+   break;
+   };
+
+   return err;
+}
+
+static inline void crypto_init_wait(struct crypto_wait *wait)
+{
+   init_completion(>completion);
+}
+
+/*
  * Algorithm registration interface.
  */
 int crypto_register_alg(struct crypto_alg *alg);
@@ -1604,5 +1644,6 @@ static inline int crypto_comp_decompress(struct 
crypto_comp *tfm,
src, slen, dst, dlen);
 }
 
+
 #endif /* _LINUX_CRYPTO_H */
 
-- 
2.1.4

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Re: [PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Chen-Yu Tsai]

Hi,

On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng  wrote:
> From: Chen-Yu Tsai 
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
>
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Pinmux changes.
>
>  arch/arm/boot/dts/sun8i-r40.dtsi | 408 
> +++
>  1 file changed, 408 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index ..1d36485c6ef7
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,408 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai 
> + * Copyright 2017 Icenowy Zheng 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   interrupt-parent = <>;
> +
> +   aliases {
> +   };
> +
> +   chosen {
> +   };
> +
> +   clocks {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   ranges;
> +
> +   osc24M: osc24M {
> +   #clock-cells = <0>;
> +   compatible = "fixed-clock";
> +   clock-frequency = <2400>;

Please add the accuracy of the oscillator. Allwinner requires it
to be within +/- 50 ppm for this one.

> +   };
> +
> +   osc32k: osc32k {
> +   #clock-cells = <0>;
> +   compatible = "fixed-clock";
> +   clock-frequency = <32768>;

And +/- 20 ppm for this one.

> +   clock-output-names = "osc32k";
> +   };
> +   };
> +
> +   cpus {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   cpu@0 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <0>;
> +   };
> +
> +   cpu@1 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <1>;
> +   };
> +
> +   cpu@2 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <2>;
> +   };
> +
> +   cpu@3 {
> +   compatible = "arm,cortex-a7";

Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC

[Chen-Yu Tsai]

Hi,

On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
> Allwinner R40 SoC have a clock controller module in the style of the
> SoCs beyond sun6i, however, it's more rich and complex.
> 
> Add support for it.
> 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Rebased on current linux-next.
> Changes in v2:
> - Fixes according to the SoC's user manual.
> 
>  drivers/clk/sunxi-ng/Kconfig  |   10 +
>  drivers/clk/sunxi-ng/Makefile |1 +
>  drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1153 
> +
>  drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   68 ++
>  include/dt-bindings/clock/sun8i-r40-ccu.h |  191 +
>  include/dt-bindings/reset/sun8i-r40-ccu.h |  129 
>  6 files changed, 1552 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
>  create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 67acef3d2494..c11ad3375907 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -157,6 +157,16 @@ config SUN8I_DE2_CCU
>   select SUNXI_CCU_DIV
>   select SUNXI_CCU_GATE
>  
> +config SUN8I_R40_CCU
> + bool "Support for the Allwinner R40 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NKMP
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP

You seem to be missing a few, such as CCU_GATE, CCU_MUX, CCU_PHASE.
The list should at least be the same as the included headers.

> + default MACH_SUN8I
> +
>  config SUN9I_A80_CCU
>   bool "Support for the Allwinner A80 CCU"
>   select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 0185c6ffadcb..217db667a994 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)  += ccu-sun8i-h3.o
>  obj-$(CONFIG_SUN8I_V3S_CCU)  += ccu-sun8i-v3s.o
>  obj-$(CONFIG_SUN8I_DE2_CCU)  += ccu-sun8i-de2.o
>  obj-$(CONFIG_SUN8I_R_CCU)+= ccu-sun8i-r.o
> +obj-$(CONFIG_SUN8I_R40_CCU)  += ccu-sun8i-r40.o
>  obj-$(CONFIG_SUN9I_A80_CCU)  += ccu-sun9i-a80.o
>  obj-$(CONFIG_SUN9I_A80_CCU)  += ccu-sun9i-a80-de.o
>  obj-$(CONFIG_SUN9I_A80_CCU)  += ccu-sun9i-a80-usb.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
> b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
> new file mode 100644
> index ..484a8956f59c
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
> @@ -0,0 +1,1153 @@
> +/*
> + * Copyright (c) 2017 Icenowy Zheng 
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun8i-r40.h"
> +
> +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
> +  "osc24M", 0x000,
> +  8, 5,  /* N */
> +  4, 2,  /* K */
> +  0, 2,  /* M */
> +  16, 2, /* P */

P does not do /8. Please add a limit.

> +  BIT(31),   /* gate */
> +  BIT(28),   /* lock */
> +  0);
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN8I_R40_PLL_AUDIO_REG  0x008
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> +"osc24M", 0x008,
> +8, 7,/* N */
> +0, 5,/* M */
> +BIT(31), /* gate */
> +BIT(28), /* lock */
> +0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> +