[PATCH RFC 4/7] i2c: Add device tree bindings for GENI I2C Controller
Add device tree binding support for I2C Controller in GENI based
QUP Wrapper.
Signed-off-by: Sagar Dharia
Signed-off-by: Karthikeyan Ramasubramanian
---
.../devicetree/bindings/i2c/i2c-qcom-geni.txt | 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
new file mode 100644
index 000..d2fa9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
@@ -0,0 +1,39 @@
+Qualcomm Technologies Inc. GENI based I2C Controller driver
+
+Required properties:
+ - compatible: Should be:
+ * "qcom,i2c-geni.
+ - reg: Should contain QUP register address and length.
+ - interrupts: Should contain I2C interrupt.
+ - clocks: Serial engine core clock, and AHB clocks needed by the device.
+ - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+ should be "active" and "sleep" for the pin confuguration when core is active
+ or when entering sleep state.
+ - #address-cells: Should be <1> Address cells for i2c device address
+ - #size-cells: Should be <0> as i2c addresses have no size component
+ - qcom,wrapper-core: Wrapper QUP core containing this I2C controller.
+
+Optional property:
+ - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to i2c bus binding.
+
+Example:
+
+i2c@a94000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,wrapper-core = <&qup_0>;
+ qcom,clk-freq-out = <40>;
+};
--
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[PATCH RFC 7/7] tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP
This driver supports GENI based UART Controller in the Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable module supporting a wide range of serial interfaces including UART. This driver support console operations using FIFO mode of transfer. Signed-off-by: Girish Mahadevan Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia --- drivers/tty/serial/Kconfig| 10 + drivers/tty/serial/Makefile |1 + drivers/tty/serial/qcom_geni_serial.c | 1447 + 3 files changed, 1458 insertions(+) create mode 100644 drivers/tty/serial/qcom_geni_serial.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index b788fee..1be30e5 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1098,6 +1098,16 @@ config SERIAL_MSM_CONSOLE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON +config SERIAL_QCOM_GENI + tristate "QCOM on-chip GENI based serial port support" + depends on ARCH_QCOM + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Serial driver for Qualcomm Technologies Inc's GENI based QUP + hardware. + config SERIAL_VT8500 bool "VIA VT8500 on-chip serial port support" depends on ARCH_VT8500 diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 842d185..64a8d82 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o +obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c new file mode 100644 index 000..8703fa6 --- /dev/null +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -0,0 +1,1447 @@ +/* + * Copyright (c) 2017, The Linux foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* UART specific GENI registers */ +#define SE_UART_TX_TRANS_CFG (0x25C) +#define SE_UART_TX_WORD_LEN(0x268) +#define SE_UART_TX_STOP_BIT_LEN(0x26C) +#define SE_UART_TX_TRANS_LEN (0x270) +#define SE_UART_RX_TRANS_CFG (0x280) +#define SE_UART_RX_WORD_LEN(0x28C) +#define SE_UART_RX_STALE_CNT (0x294) +#define SE_UART_TX_PARITY_CFG (0x2A4) +#define SE_UART_RX_PARITY_CFG (0x2A8) + +/* SE_UART_TRANS_CFG */ +#define UART_TX_PAR_EN (BIT(0)) +#define UART_CTS_MASK (BIT(1)) + +/* SE_UART_TX_WORD_LEN */ +#define TX_WORD_LEN_MSK(GENMASK(9, 0)) + +/* SE_UART_TX_STOP_BIT_LEN */ +#define TX_STOP_BIT_LEN_MSK(GENMASK(23, 0)) +#define TX_STOP_BIT_LEN_1 (0) +#define TX_STOP_BIT_LEN_1_5(1) +#define TX_STOP_BIT_LEN_2 (2) + +/* SE_UART_TX_TRANS_LEN */ +#define TX_TRANS_LEN_MSK (GENMASK(23, 0)) + +/* SE_UART_RX_TRANS_CFG */ +#define UART_RX_INS_STATUS_BIT (BIT(2)) +#define UART_RX_PAR_EN (BIT(3)) + +/* SE_UART_RX_WORD_LEN */ +#define RX_WORD_LEN_MASK (GENMASK(9, 0)) + +/* SE_UART_RX_STALE_CNT */ +#define RX_STALE_CNT (GENMASK(23, 0)) + +/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ +#define PAR_CALC_EN(BIT(0)) +#define PAR_MODE_MSK (GENMASK(2, 1)) +#define PAR_MODE_SHFT (1) +#define PAR_EVEN (0x00) +#define PAR_ODD(0x01) +#define PAR_SPACE (0x10) +#define PAR_MARK (0x11) + +/* UART M_CMD OP codes */ +#define UART_START_TX (0x1) +#define UART_START_BREAK (0x4) +#define UART_STOP_BREAK(0x5) +/* UART S_CMD OP codes */ +#define UART_START_READ(0x1) +#define UART_PARAM (0x1) + +#define UART_OVERSAMPLING (32) +#define STALE_TIMEOUT (16) +#define DEFAULT_BITS_PER_CHAR (10) +#define GENI_UART_NR_PORTS (15) +#define GENI_UART_CONS_PORTS (1) +#define DEF_FIFO_DEPTH_WORDS (16) +#define DEF_TX_WM (2) +#define DEF_FIFO_WIDTH_BITS(32) +#define UART_CORE2X_VOTE (1) +#
[PATCH RFC 2/7] soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..5108b62
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,15 @@
+Qualcomm Technologies, Inc. GENI Serial Engine Driver
+
+GENI Serial Engine Driver manages the GENI firmware based Qualcomm Universal
+Peripheral (QUP) Wrapper. GENI SE Driver also manages the common aspects of
+individual Serial Engines that composes the QUP Wrapper.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+
+Example:
+ qup_0: qcom,geni_se_qup_0@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ }
--
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[PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller
Add device tree binding support for GENI based UART Controller in the
QUP Wrapper.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Girish Mahadevan
---
.../devicetree/bindings/serial/qcom,geni-uart.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 000..e60ec6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
@@ -0,0 +1,31 @@
+Qualcomm Technologies Inc. GENI based Serial UART Controller driver
+
+This serial UART driver supports console use-cases. This driver is meant
+only for Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP)
+cores and isn't backwards compatible.
+
+Required properties:
+- compatible: should contain "qcom,geni-uart, qcom,geni-console"
+- reg: Should contain UART register location and length.
+- interrupts: Should contain UART core interrupts.
+- clocks: clocks needed for UART, includes the core and AHB clock.
+- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+ Should be "active" and "sleep" for the pin confuguration when core is active
+ or when entering sleep state.
+- qcom,wrapper-core: Wrapper QUP core containing this UART controller.
+
+Example:
+qup_uart11: qcom,qup_uart@0xa88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0xa88000 0x7000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ interrupts = <0 355 0>;
+ qcom,wrapper-core = <&qup_0>;
+};
--
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[PATCH RFC 5/7] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 685 +
3 files changed, 696 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 009345d..caef309 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -838,6 +838,16 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM
+ help
+ If you say yes to this option, support will be included for the
+ built-in I2C interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..6ffe17e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN(0x26C)
+#define SE_I2C_RX_TRANS_LEN(0x270)
+#define SE_I2C_SCL_COUNTERS(0x278)
+#define SE_GENI_IOS(0x908)
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT (1U << 1)
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE (0x1)
+#define I2C_READ (0x2)
+#define I2C_WRITE_READ (0x3)
+#define I2C_ADDR_ONLY (0x4)
+#define I2C_BUS_CLEAR (0x6)
+#define I2C_STOP_ON_BUS(0x7)
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY (BIT(0))
+#define TIMESTAMP_BEFORE (BIT(1))
+#define STOP_STRETCH (BIT(2))
+#define TIMESTAMP_AFTER(BIT(3))
+#define POST_COMMAND_DELAY (BIT(4))
+#define IGNORE_ADD_NACK(BIT(6))
+#define READ_FINISHED_WITH_ACK (BIT(7))
+#define BYPASS_ADDR_PHASE (BIT(8))
+#define SLV_ADDR_MSK (GENMASK(15, 9))
+#define SLV_ADDR_SHFT (9)
+
+#define I2C_CORE2X_VOTE(1)
+#define GP_IRQ00
+#define GP_IRQ11
+#define GP_IRQ22
+#define GP_IRQ33
+#define GP_IRQ44
+#define GP_IRQ55
+#define GENI_OVERRUN 6
+#define GENI_ILLEGAL_CMD 7
+#define GENI_ABORT_DONE8
+#define GENI_TIMEOUT 9
+
+#define I2C_NACK GP_IRQ1
+#define I2C_BUS_PROTO GP_IRQ3
+#define I2C_ARB_LOST GP_IRQ4
+#define DM_I2C_CB_ERR ((BIT(GP_IRQ1) | BIT(GP_IRQ3) | BIT(GP_IRQ4)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHz(freq) (1000 * freq)
+
+struct geni_i2c_dev {
+ struct device *dev;
+ void __iomem *base;
+
[PATCH RFC 0/7] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. Karthikeyan Ramasubramanian (7): qcom-geni-se: Add QCOM GENI SE Driver summary soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver i2c: Add device tree bindings for GENI I2C Controller i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller serial: Add device tree bindings for GENI based UART Controller tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP .../devicetree/bindings/i2c/i2c-qcom-geni.txt | 39 + .../devicetree/bindings/serial/qcom,geni-uart.txt | 31 + .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 15 + Documentation/qcom-geni-se.txt | 56 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile|1 + drivers/i2c/busses/i2c-qcom-geni.c | 685 + drivers/soc/qcom/Kconfig |8 + drivers/soc/qcom/Makefile |1 + drivers/soc/qcom/qcom-geni-se.c| 973 + drivers/tty/serial/Kconfig | 10 + drivers/tty/serial/Makefile|1 + drivers/tty/serial/qcom_geni_serial.c | 1447 include/linux/qcom-geni-se.h | 811 +++ 14 files changed, 4088 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 Documentation/qcom-geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 drivers/tty/serial/qcom_geni_serial.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC 1/7] qcom-geni-se: Add QCOM GENI SE Driver summary
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a programmable module that is composed of multiple Serial Engines (SE) and can support various Serial Interfaces like UART, SPI, I2C, I3C, etc. This document provides a high level overview of the GENI based QUP Wrapper. Signed-off-by: Karthikeyan Ramasubramanian --- Documentation/qcom-geni-se.txt | 56 ++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/qcom-geni-se.txt diff --git a/Documentation/qcom-geni-se.txt b/Documentation/qcom-geni-se.txt new file mode 100644 index 000..dc517ef --- /dev/null +++ b/Documentation/qcom-geni-se.txt @@ -0,0 +1,56 @@ +Introduction + + +Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced +to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper +controller. QUP Wrapper is designed to support various serial bus protocols +like UART, SPI, I2C, I3C, etc. + +Hardware description + + +GENI based QUP is a highly-flexible and programmable module for supporting +a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single +QUP module can provide upto 8 Serial Interfaces, using its internal +Serial Engines. The actual configuration is determined by the target +platform configuration. The protocol supported by each interface is +determined by the firmware loaded to the Serial Engine. Each SE consists +of a DMA Engine and GENI sub modules which enable Serial Engines to +support FIFO and DMA modes of operation. + +:: + + +-+ + |QUP Wrapper | + | ++ | + --QUP & SE Clocks--> | Serial Engine N| +-IO--> + | | ...| | Interface + <---Clock Perf.+++---+| | + State Interface || Serial Engine 1|| | + |||| | + |||| | + <AHB--->||| | + ||++ | + ||| | + ||| | + <--SE IRQ--+++ | + | | + +-+ + + Figure 1: GENI based QUP Wrapper + +Software description + + +GENI SE Wrapper driver is structured into 2 parts: + +geni_se_device represents QUP Wrapper controller. This part of the driver +manages QUP Wrapper information such as hardware version, clock +performance table that is common to all the internal Serial Engines. + +geni_se_rsc represents Serial Engine. This part of the driver manages +Serial Engine information such as clocks, pinctrl states, containing QUP +Wrapper. This part of driver also supports operations(eg. initialize the +concerned Serial Engine, select between FIFO and DMA mode of operation etc.) +that are common to all the Serial Engines and are independent of Serial +Interfaces. -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC 3/7] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm
Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation
programmable module composed of multiple Serial Engines (SE) and supports
a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This
driver also enables managing the serial interface independent aspects of
Serial Engines.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/soc/qcom/Kconfig| 8 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/qcom-geni-se.c | 973
include/linux/qcom-geni-se.h| 811 +
4 files changed, 1793 insertions(+)
create mode 100644 drivers/soc/qcom/qcom-geni-se.c
create mode 100644 include/linux/qcom-geni-se.h
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index b81374b..b306d51 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -3,6 +3,14 @@
#
menu "Qualcomm SoC drivers"
+config QCOM_GENI_SE
+ tristate "QCOM GENI Serial Engine Driver"
+ help
+ This module is used to manage Generic Interface (GENI) firmware based
+ Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This
+ module is also used to manage the common aspects of multiple Serial
+ Engines present in the QUP.
+
config QCOM_GLINK_SSR
tristate "Qualcomm Glink SSR driver"
depends on RPMSG
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 40c56f6..74d5db8 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o
obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
new file mode 100644
index 000..76aecfb
--- /dev/null
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -0,0 +1,973 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MAX_CLK_PERF_LEVEL 32
+
+/**
+ * @struct geni_se_device - Data structure to represent the QUP Wrapper Core
+ * @dev: Device pointer of the QUP wrapper core.
+ * @base: Base address of this instance of QUP wrapper core.
+ * @geni_dev_lock: Lock to protect the device elements.
+ * @num_clk_levels:Number of valid clock levels in clk_perf_tbl.
+ * @clk_perf_tbl: Table of clock frequency input to Serial Engine clock.
+ */
+struct geni_se_device {
+ struct device *dev;
+ void __iomem *base;
+ struct mutex geni_dev_lock;
+ unsigned int num_clk_levels;
+ unsigned long *clk_perf_tbl;
+};
+
+/* Offset of QUP Hardware Version Register */
+#define QUP_HW_VER (0x4)
+
+#define HW_VER_MAJOR_MASK GENMASK(31, 28)
+#define HW_VER_MAJOR_SHFT 28
+#define HW_VER_MINOR_MASK GENMASK(27, 16)
+#define HW_VER_MINOR_SHFT 16
+#define HW_VER_STEP_MASK GENMASK(15, 0)
+
+/**
+ * geni_read_reg_nolog() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset:Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg_nolog(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+EXPORT_SYMBOL(geni_read_reg_nolog);
+
+/**
+ * geni_write_reg_nolog() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset:Offset within the serial engine's register block.
+ */
+void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset)
+{
+ return writel_relaxed(value, (base + offset));
+}
+EXPORT_SYMBOL(geni_write_reg_nolog);
+
+/**
+ * geni_read_reg() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset:Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg(void __iomem *bas
[PATCH v2 2/7] dt-bindings: soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..66f8a16
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,34 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be 1
+- #size-cells: Must be 1
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, spi controller, or some combination of aforementioned devices.
+
+Example:
+ qup0: qcom,geniqup0@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ }
--
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a Linux Foundation Collaborative Project
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[PATCH v2 1/7] qcom-geni-se: Add QCOM GENI SE Driver summary
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a programmable module that is composed of multiple Serial Engines (SE) and can support various Serial Interfaces like UART, SPI, I2C, I3C, etc. This document provides a high level overview of the GENI based QUP Wrapper. Signed-off-by: Karthikeyan Ramasubramanian --- Documentation/qcom-geni-se.txt | 56 ++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/qcom-geni-se.txt diff --git a/Documentation/qcom-geni-se.txt b/Documentation/qcom-geni-se.txt new file mode 100644 index 000..dc517ef --- /dev/null +++ b/Documentation/qcom-geni-se.txt @@ -0,0 +1,56 @@ +Introduction + + +Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced +to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper +controller. QUP Wrapper is designed to support various serial bus protocols +like UART, SPI, I2C, I3C, etc. + +Hardware description + + +GENI based QUP is a highly-flexible and programmable module for supporting +a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single +QUP module can provide upto 8 Serial Interfaces, using its internal +Serial Engines. The actual configuration is determined by the target +platform configuration. The protocol supported by each interface is +determined by the firmware loaded to the Serial Engine. Each SE consists +of a DMA Engine and GENI sub modules which enable Serial Engines to +support FIFO and DMA modes of operation. + +:: + + +-+ + |QUP Wrapper | + | ++ | + --QUP & SE Clocks--> | Serial Engine N| +-IO--> + | | ...| | Interface + <---Clock Perf.+++---+| | + State Interface || Serial Engine 1|| | + |||| | + |||| | + <AHB--->||| | + ||++ | + ||| | + ||| | + <--SE IRQ--+++ | + | | + +-+ + + Figure 1: GENI based QUP Wrapper + +Software description + + +GENI SE Wrapper driver is structured into 2 parts: + +geni_se_device represents QUP Wrapper controller. This part of the driver +manages QUP Wrapper information such as hardware version, clock +performance table that is common to all the internal Serial Engines. + +geni_se_rsc represents Serial Engine. This part of the driver manages +Serial Engine information such as clocks, pinctrl states, containing QUP +Wrapper. This part of driver also supports operations(eg. initialize the +concerned Serial Engine, select between FIFO and DMA mode of operation etc.) +that are common to all the Serial Engines and are independent of Serial +Interfaces. -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/7] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. [v2] * Updated device tree bindings to describe the hardware * Updated SE DT node as child node of QUP Wrapper DT node * Moved common AHB clocks to QUP Wrapper DT node * Use the standard "clock-frequency" I2C property * Update compatible field in UART Controller to reflect hardware manual * Addressed other device tree binding specific comments from Rob Herring Karthikeyan Ramasubramanian (7): qcom-geni-se: Add QCOM GENI SE Driver summary dt-bindings: soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver dt-bindings: i2c: Add device tree bindings for GENI I2C Controller i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller dt-bindings: serial: Add bindings for GENI based UART Controller tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP .../devicetree/bindings/i2c/i2c-qcom-geni.txt | 35 + .../devicetree/bindings/serial/qcom,geni-uart.txt | 29 + .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 66 + Documentation/qcom-geni-se.txt | 56 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile|1 + drivers/i2c/busses/i2c-qcom-geni.c | 656 + drivers/soc/qcom/Kconfig |8 + drivers/soc/qcom/Makefile |1 + drivers/soc/qcom/qcom-geni-se.c| 1016 ++ drivers/tty/serial/Kconfig | 10 + drivers/tty/serial/Makefile|1 + drivers/tty/serial/qcom_geni_serial.c | 1414 include/linux/qcom-geni-se.h | 807 +++ 14 files changed, 4110 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 Documentation/qcom-geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 drivers/tty/serial/qcom_geni_serial.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/7] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 656 +
3 files changed, 667 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 009345d..caef309 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -838,6 +838,16 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM
+ help
+ If you say yes to this option, support will be included for the
+ built-in I2C interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..59ad4da
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN(0x26C)
+#define SE_I2C_RX_TRANS_LEN(0x270)
+#define SE_I2C_SCL_COUNTERS(0x278)
+#define SE_GENI_IOS(0x908)
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT (1U << 1)
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE (0x1)
+#define I2C_READ (0x2)
+#define I2C_WRITE_READ (0x3)
+#define I2C_ADDR_ONLY (0x4)
+#define I2C_BUS_CLEAR (0x6)
+#define I2C_STOP_ON_BUS(0x7)
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY (BIT(0))
+#define TIMESTAMP_BEFORE (BIT(1))
+#define STOP_STRETCH (BIT(2))
+#define TIMESTAMP_AFTER(BIT(3))
+#define POST_COMMAND_DELAY (BIT(4))
+#define IGNORE_ADD_NACK(BIT(6))
+#define READ_FINISHED_WITH_ACK (BIT(7))
+#define BYPASS_ADDR_PHASE (BIT(8))
+#define SLV_ADDR_MSK (GENMASK(15, 9))
+#define SLV_ADDR_SHFT (9)
+
+#define I2C_CORE2X_VOTE(1)
+#define GP_IRQ00
+#define GP_IRQ11
+#define GP_IRQ22
+#define GP_IRQ33
+#define GP_IRQ44
+#define GP_IRQ55
+#define GENI_OVERRUN 6
+#define GENI_ILLEGAL_CMD 7
+#define GENI_ABORT_DONE8
+#define GENI_TIMEOUT 9
+
+#define I2C_NACK GP_IRQ1
+#define I2C_BUS_PROTO GP_IRQ3
+#define I2C_ARB_LOST GP_IRQ4
+#define DM_I2C_CB_ERR ((BIT(GP_IRQ1) | BIT(GP_IRQ3) | BIT(GP_IRQ4)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHz(freq) (1000 * freq)
+
+struct geni_i2c_dev {
+ struct device *dev;
+ void __iomem *bas
[PATCH v2 6/7] dt-bindings: serial: Add bindings for GENI based UART Controller
Add device tree binding support for GENI based UART Controller in the
QUP Wrapper.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Girish Mahadevan
---
.../devicetree/bindings/serial/qcom,geni-uart.txt | 29 ++
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 13 ++
2 files changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 000..e7b9e24
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
@@ -0,0 +1,29 @@
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+The Generic Interface (GENI) Serial Engine based UART controller supports
+console use-cases and is supported only by GENI based Qualcomm Universal
+Peripheral (QUP) cores.
+
+Required properties:
+- compatible: should contain "qcom,geni-debug-uart".
+- reg: Should contain UART register location and length.
+- reg-names: Should contain "se-phys".
+- interrupts: Should contain UART core interrupts.
+- clock-names: Should contain "se-clk".
+- clocks: clocks needed for UART, includes the core clock.
+- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+ Should be "active" and "sleep" for the pin confuguration when core is active
+ or when entering sleep state.
+
+Example:
+uart0: qcom,serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa88000 0x7000>;
+ reg-names = "se-phys";
+ interrupts = <0 355 0>;
+ clock-names = "se-clk";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index 2ffbb3e..c307788 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -26,6 +26,7 @@ controller, spi controller, or some combination of
aforementioned devices.
See the following documentation for child node definitions:
Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
+Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
Example:
qup0: qcom,geniqup0@8c {
@@ -50,4 +51,16 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
};
+
+ uart0: qcom,serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa88000 0x7000>;
+ reg-names = "se-phys";
+ interrupts = <0 355 0>;
+ clock-names = "se-clk";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ };
}
--
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[PATCH v2 3/7] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm
Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation
programmable module composed of multiple Serial Engines (SE) and supports
a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This
driver also enables managing the serial interface independent aspects of
Serial Engines.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/soc/qcom/Kconfig|8 +
drivers/soc/qcom/Makefile |1 +
drivers/soc/qcom/qcom-geni-se.c | 1016 +++
include/linux/qcom-geni-se.h| 807 +++
4 files changed, 1832 insertions(+)
create mode 100644 drivers/soc/qcom/qcom-geni-se.c
create mode 100644 include/linux/qcom-geni-se.h
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index b81374b..b306d51 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -3,6 +3,14 @@
#
menu "Qualcomm SoC drivers"
+config QCOM_GENI_SE
+ tristate "QCOM GENI Serial Engine Driver"
+ help
+ This module is used to manage Generic Interface (GENI) firmware based
+ Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This
+ module is also used to manage the common aspects of multiple Serial
+ Engines present in the QUP.
+
config QCOM_GLINK_SSR
tristate "Qualcomm Glink SSR driver"
depends on RPMSG
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 40c56f6..74d5db8 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o
obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
new file mode 100644
index 000..3f43582
--- /dev/null
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -0,0 +1,1016 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MAX_CLK_PERF_LEVEL 32
+
+/**
+ * @struct geni_se_device - Data structure to represent the QUP Wrapper Core
+ * @dev: Device pointer of the QUP wrapper core.
+ * @base: Base address of this instance of QUP wrapper core.
+ * @m_ahb_clk: Handle to the primary AHB clock.
+ * @s_ahb_clk: Handle to the secondary AHB clock.
+ * @geni_dev_lock: Lock to protect the device elements.
+ * @num_clk_levels:Number of valid clock levels in clk_perf_tbl.
+ * @clk_perf_tbl: Table of clock frequency input to Serial Engine clock.
+ */
+struct geni_se_device {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *m_ahb_clk;
+ struct clk *s_ahb_clk;
+ struct mutex geni_dev_lock;
+ unsigned int num_clk_levels;
+ unsigned long *clk_perf_tbl;
+};
+
+/* Offset of QUP Hardware Version Register */
+#define QUP_HW_VER (0x4)
+
+#define HW_VER_MAJOR_MASK GENMASK(31, 28)
+#define HW_VER_MAJOR_SHFT 28
+#define HW_VER_MINOR_MASK GENMASK(27, 16)
+#define HW_VER_MINOR_SHFT 16
+#define HW_VER_STEP_MASK GENMASK(15, 0)
+
+/**
+ * geni_read_reg_nolog() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset:Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg_nolog(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+EXPORT_SYMBOL(geni_read_reg_nolog);
+
+/**
+ * geni_write_reg_nolog() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset:Offset within the serial engine's register block.
+ */
+void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset)
+{
+ return writel_relaxed(value, (base + offset));
+}
+EXPORT_SYMBOL(geni_write_reg_nolog);
+
+/**
+ * geni_read_reg() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register b
[PATCH v2 4/7] dt-bindings: i2c: Add device tree bindings for GENI I2C Controller
Add device tree binding support for I2C Controller in GENI based
QUP Wrapper.
Signed-off-by: Sagar Dharia
Signed-off-by: Karthikeyan Ramasubramanian
---
.../devicetree/bindings/i2c/i2c-qcom-geni.txt | 35 ++
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 19
2 files changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
new file mode 100644
index 000..ea84be7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
@@ -0,0 +1,35 @@
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+ - compatible: Should be:
+ * "qcom,i2c-geni.
+ - reg: Should contain QUP register address and length.
+ - interrupts: Should contain I2C interrupt.
+ - clock-names: Should contain "se-clk".
+ - clocks: Serial engine core clock needed by the device.
+ - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+ should be "active" and "sleep" for the pin confuguration when core is active
+ or when entering sleep state.
+ - #address-cells: Should be <1> Address cells for i2c device address
+ - #size-cells: Should be <0> as i2c addresses have no size component
+
+Optional property:
+ - clock-frequency : Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to i2c bus binding.
+
+Example:
+
+i2c0: i2c@a94000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se-clk";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index 66f8a16..2ffbb3e 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -24,6 +24,9 @@ A GENI based QUP wrapper controller node can contain 0 or
more child nodes
representing serial devices. These serial devices can be a QCOM UART, I2C
controller, spi controller, or some combination of aforementioned devices.
+See the following documentation for child node definitions:
+Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt
+
Example:
qup0: qcom,geniqup0@8c {
compatible = "qcom,geni-se-qup";
@@ -31,4 +34,20 @@ Example:
clock-names = "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se-clk";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
}
--
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[PATCH v2 7/7] tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP
This driver supports GENI based UART Controller in the Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable module supporting a wide range of serial interfaces including UART. This driver support console operations using FIFO mode of transfer. Signed-off-by: Girish Mahadevan Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia --- drivers/tty/serial/Kconfig| 10 + drivers/tty/serial/Makefile |1 + drivers/tty/serial/qcom_geni_serial.c | 1414 + 3 files changed, 1425 insertions(+) create mode 100644 drivers/tty/serial/qcom_geni_serial.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index b788fee..1be30e5 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1098,6 +1098,16 @@ config SERIAL_MSM_CONSOLE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON +config SERIAL_QCOM_GENI + tristate "QCOM on-chip GENI based serial port support" + depends on ARCH_QCOM + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Serial driver for Qualcomm Technologies Inc's GENI based QUP + hardware. + config SERIAL_VT8500 bool "VIA VT8500 on-chip serial port support" depends on ARCH_VT8500 diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 842d185..64a8d82 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o +obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c new file mode 100644 index 000..0dbd329 --- /dev/null +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -0,0 +1,1414 @@ +/* + * Copyright (c) 2017-2018, The Linux foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* UART specific GENI registers */ +#define SE_UART_TX_TRANS_CFG (0x25C) +#define SE_UART_TX_WORD_LEN(0x268) +#define SE_UART_TX_STOP_BIT_LEN(0x26C) +#define SE_UART_TX_TRANS_LEN (0x270) +#define SE_UART_RX_TRANS_CFG (0x280) +#define SE_UART_RX_WORD_LEN(0x28C) +#define SE_UART_RX_STALE_CNT (0x294) +#define SE_UART_TX_PARITY_CFG (0x2A4) +#define SE_UART_RX_PARITY_CFG (0x2A8) + +/* SE_UART_TRANS_CFG */ +#define UART_TX_PAR_EN (BIT(0)) +#define UART_CTS_MASK (BIT(1)) + +/* SE_UART_TX_WORD_LEN */ +#define TX_WORD_LEN_MSK(GENMASK(9, 0)) + +/* SE_UART_TX_STOP_BIT_LEN */ +#define TX_STOP_BIT_LEN_MSK(GENMASK(23, 0)) +#define TX_STOP_BIT_LEN_1 (0) +#define TX_STOP_BIT_LEN_1_5(1) +#define TX_STOP_BIT_LEN_2 (2) + +/* SE_UART_TX_TRANS_LEN */ +#define TX_TRANS_LEN_MSK (GENMASK(23, 0)) + +/* SE_UART_RX_TRANS_CFG */ +#define UART_RX_INS_STATUS_BIT (BIT(2)) +#define UART_RX_PAR_EN (BIT(3)) + +/* SE_UART_RX_WORD_LEN */ +#define RX_WORD_LEN_MASK (GENMASK(9, 0)) + +/* SE_UART_RX_STALE_CNT */ +#define RX_STALE_CNT (GENMASK(23, 0)) + +/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ +#define PAR_CALC_EN(BIT(0)) +#define PAR_MODE_MSK (GENMASK(2, 1)) +#define PAR_MODE_SHFT (1) +#define PAR_EVEN (0x00) +#define PAR_ODD(0x01) +#define PAR_SPACE (0x10) +#define PAR_MARK (0x11) + +/* UART M_CMD OP codes */ +#define UART_START_TX (0x1) +#define UART_START_BREAK (0x4) +#define UART_STOP_BREAK(0x5) +/* UART S_CMD OP codes */ +#define UART_START_READ(0x1) +#define UART_PARAM (0x1) + +#define UART_OVERSAMPLING (32) +#define STALE_TIMEOUT (16) +#define DEFAULT_BITS_PER_CHAR (10) +#define GENI_UART_NR_PORTS (15) +#define GENI_UART_CONS_PORTS (1) +#define DEF_FIFO_DEPTH_WORDS (16) +#define DEF_TX_WM (2) +#define DEF_FIFO_WIDTH_BITS(32) +#define UART_CORE2X_VO
[PATCH v3 1/4] dt-bindings: soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 89 ++
1 file changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..fe6a0c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,89 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be <1> for Serial Engine Address
+- #size-cells: Must be <1> for Serial Engine Address Size
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, spi controller, or some combination of aforementioned devices.
+Please refer below the child node definitions for the supported serial
+interface protocols.
+
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-i2c".
+- reg: Must contain QUP register address and length.
+- interrupts: Must contain I2C interrupt.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- #address-cells: Must be <1> for i2c device address.
+- #size-cells: Must be <0> as i2c addresses have no size component.
+
+Optional property:
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to i2c bus binding as described in i2c.txt.
+
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-debug-uart".
+- reg: Must contain UART register location and length.
+- interrupts: Must contain UART core interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+
+Example:
+ geniqup@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa88000 0x7000>;
+ interrupts = ;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ };
+ }
--
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[PATCH v3 0/4] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. [v3] * Update the driver dependencies * Use the SPDX License Expression * Squash all the controller device tree bindings together * Use kernel doc format for documentation * Add additional documentation for packing configuration * Use clk_bulk_* API for related clocks * Remove driver references to pinctrl and their states * Replace magic numbers with appropriate macros * Update memory barrier usage and associated comments * Reduce interlacing of register reads/writes * Fix poll_get_char() operation in console UART driver under polling mode * Address other comments from Bjorn Andersson to improve code readability [v2] * Updated device tree bindings to describe the hardware * Updated SE DT node as child node of QUP Wrapper DT node * Moved common AHB clocks to QUP Wrapper DT node * Use the standard "clock-frequency" I2C property * Update compatible field in UART Controller to reflect hardware manual * Addressed other device tree binding specific comments from Rob Herring Karthikeyan Ramasubramanian (4): dt-bindings: soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 89 ++ drivers/i2c/busses/Kconfig | 11 + drivers/i2c/busses/Makefile|1 + drivers/i2c/busses/i2c-qcom-geni.c | 626 +++ drivers/soc/qcom/Kconfig |9 + drivers/soc/qcom/Makefile |1 + drivers/soc/qcom/qcom-geni-se.c| 971 drivers/tty/serial/Kconfig | 11 + drivers/tty/serial/Makefile|1 + drivers/tty/serial/qcom_geni_serial.c | 1181 include/linux/qcom-geni-se.h | 247 11 files changed, 3148 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 drivers/tty/serial/qcom_geni_serial.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/4] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/i2c/busses/Kconfig | 11 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 626 +
3 files changed, 638 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e2954fb..1ddf5cd 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -848,6 +848,17 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM
+ depends on QCOM_GENI_SE
+ help
+ If you say yes to this option, support will be included for the
+ built-in I2C interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..e1e4268
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+#define GP_IRQ00
+#define GP_IRQ11
+#define GP_IRQ22
+#define GP_IRQ33
+#define GP_IRQ44
+#define GP_IRQ55
+#define GENI_OVERRUN 6
+#define GENI_ILLEGAL_CMD 7
+#define GENI_ABORT_DONE8
+#define GENI_TIMEOUT 9
+
+#define I2C_NACK GP_IRQ1
+#define I2C_BUS_PROTO GP_IRQ3
+#define I2C_ARB_LOST GP_IRQ4
+#define DM_I2C_CB_ERR ((BIT(GP_IRQ1) | BIT(GP_IRQ3) | BIT(GP_IRQ4)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHz(freq) (1000 * freq)
+#define PACKING_BYTES_PW 4
+
+struct geni_i2c_dev {
+ struct geni_se se;
+ u32 tx_wm;
+ int irq;
+ int err;
+ struct i2c_adapter adap;
+ struct completion done;
+ struct i2c_msg *cur;
+ int cur_wr;
+ int cur_rd;
+ u32 clk_freq_out;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+struct geni_i2c_err_log {
[PATCH v3 2/4] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia Signed-off-by: Girish Mahadevan --- drivers/soc/qcom/Kconfig| 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c | 971 include/linux/qcom-geni-se.h| 247 ++ 4 files changed, 1228 insertions(+) create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e050eb8..cc460d0 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,15 @@ # menu "Qualcomm SoC drivers" +config QCOM_GENI_SE + tristate "QCOM GENI Serial Engine Driver" + depends on ARCH_QCOM + help + This module is used to manage Generic Interface (GENI) firmware based + Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This + module is also used to manage the common aspects of multiple Serial + Engines present in the QUP. + config QCOM_GLINK_SSR tristate "Qualcomm Glink SSR driver" depends on RPMSG diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index dcebf28..959aa74 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c new file mode 100644 index 000..61335b8 --- /dev/null +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -0,0 +1,971 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: Overview + * + * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced + * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper + * controller. QUP Wrapper is designed to support various serial bus protocols + * like UART, SPI, I2C, I3C, etc. + */ + +/** + * DOC: Hardware description + * + * GENI based QUP is a highly-flexible and programmable module for supporting + * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single + * QUP module can provide upto 8 Serial Interfaces, using its internal + * Serial Engines. The actual configuration is determined by the target + * platform configuration. The protocol supported by each interface is + * determined by the firmware loaded to the Serial Engine. Each SE consists + * of a DMA Engine and GENI sub modules which enable Serial Engines to + * support FIFO and DMA modes of operation. + * + * + * +-+ + * |QUP Wrapper | + * | ++ | + * --QUP & SE Clocks--> | Serial Engine N| +-IO--> + * | | ...| | Interface + * <---Clock Perf.+++---+| | + * State Interface || Serial Engine 1|| | + * |||| | + * |||| | + * <AHB--->||| | + * ||++ | + * ||| | + * ||| | + * <--SE IRQ--+++ | + * | | + * +-+ + * + * Figure 1: GENI based QUP Wrapper + */ + +/** + * DOC: Software description + * + * GENI SE Wrapper driver is structured into 2 parts: + * + * geni_wrapper represents QUP Wrapper controller. This part of the driver + * manages QUP Wrapper information such as hardware version, clock + * performance table that is common to all the internal Serial Engines. + * + * geni_se represents Serial Engine. This part of the driver manages Serial + * Engine information such as clocks, containing QUP Wrapper etc. This part + * of driver a
[PATCH v3 4/4] tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP
This driver supports GENI based UART Controller in the Qualcomm SOCs. The
Qualcomm Generic Interface (GENI) is a programmable module supporting a
wide range of serial interfaces including UART. This driver support console
operations using FIFO mode of transfer.
Signed-off-by: Girish Mahadevan
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Doug Anderson
---
drivers/tty/serial/Kconfig| 11 +
drivers/tty/serial/Makefile |1 +
drivers/tty/serial/qcom_geni_serial.c | 1181 +
3 files changed, 1193 insertions(+)
create mode 100644 drivers/tty/serial/qcom_geni_serial.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3682fd3..c6b1500 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1104,6 +1104,17 @@ config SERIAL_MSM_CONSOLE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
+config SERIAL_QCOM_GENI
+ bool "QCOM on-chip GENI based serial port support"
+ depends on ARCH_QCOM
+ depends on QCOM_GENI_SE
+ select SERIAL_CORE
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Serial driver for Qualcomm Technologies Inc's GENI based QUP
+ hardware.
+
config SERIAL_VT8500
bool "VIA VT8500 on-chip serial port support"
depends on ARCH_VT8500
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 842d185..64a8d82 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
+obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
diff --git a/drivers/tty/serial/qcom_geni_serial.c
b/drivers/tty/serial/qcom_geni_serial.c
new file mode 100644
index 000..8536b7d
--- /dev/null
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -0,0 +1,1181 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* UART specific GENI registers */
+#define SE_UART_TX_TRANS_CFG 0x25c
+#define SE_UART_TX_WORD_LEN0x268
+#define SE_UART_TX_STOP_BIT_LEN0x26c
+#define SE_UART_TX_TRANS_LEN 0x270
+#define SE_UART_RX_TRANS_CFG 0x280
+#define SE_UART_RX_WORD_LEN0x28c
+#define SE_UART_RX_STALE_CNT 0x294
+#define SE_UART_TX_PARITY_CFG 0x2a4
+#define SE_UART_RX_PARITY_CFG 0x2a8
+
+/* SE_UART_TRANS_CFG */
+#define UART_TX_PAR_EN BIT(0)
+#define UART_CTS_MASK BIT(1)
+
+/* SE_UART_TX_WORD_LEN */
+#define TX_WORD_LEN_MSKGENMASK(9, 0)
+
+/* SE_UART_TX_STOP_BIT_LEN */
+#define TX_STOP_BIT_LEN_MSKGENMASK(23, 0)
+#define TX_STOP_BIT_LEN_1 0
+#define TX_STOP_BIT_LEN_1_51
+#define TX_STOP_BIT_LEN_2 2
+
+/* SE_UART_TX_TRANS_LEN */
+#define TX_TRANS_LEN_MSK GENMASK(23, 0)
+
+/* SE_UART_RX_TRANS_CFG */
+#define UART_RX_INS_STATUS_BIT BIT(2)
+#define UART_RX_PAR_EN BIT(3)
+
+/* SE_UART_RX_WORD_LEN */
+#define RX_WORD_LEN_MASK GENMASK(9, 0)
+
+/* SE_UART_RX_STALE_CNT */
+#define RX_STALE_CNT GENMASK(23, 0)
+
+/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
+#define PAR_CALC_ENBIT(0)
+#define PAR_MODE_MSK GENMASK(2, 1)
+#define PAR_MODE_SHFT 1
+#define PAR_EVEN 0x00
+#define PAR_ODD0x01
+#define PAR_SPACE 0x10
+#define PAR_MARK 0x11
+
+/* UART M_CMD OP codes */
+#define UART_START_TX 0x1
+#define UART_START_BREAK 0x4
+#define UART_STOP_BREAK0x5
+/* UART S_CMD OP codes */
+#define UART_START_READ0x1
+#define UART_PARAM 0x1
+
+#define UART_OVERSAMPLING 32
+#define STALE_TIMEOUT 16
+#define DEFAULT_BITS_PER_CHAR 10
+#define GENI_UART_CONS_PORTS 1
+#define DEF_FIFO_DEPTH_WORDS 16
+#define DEF_TX_WM 2
+#define DEF_FIFO_WIDTH_BITS32
+#define UART_CONSOLE_RX_WM 2
+
+#ifdef CONFIG_CONSOLE_POLL
+#define RX_BYTES_PW 1
+#else
+#define RX_BYTES_PW 4
+#endif
+
+struct qcom_geni_serial_port {
+ struct uart_port uport;
+ struct geni_se se;
+ char name[20];
+ u32 tx_fifo_depth;
+ u32 tx_fifo_width;
+ u32 rx_fifo_depth;
+ u32 tx_wm;
+ u32 rx_wm;
+ u32 rx_rfr;
+ int xfer_mode;
+ bool port_setup;
+ int (*handle_rx)(struct uart_port *uport,
+ u32 rx_bytes, bool drop_rx);
+
[PATCH v4 0/6] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. [v4] * Add SPI controller information in device tree binding * Add support for debug UART & I2C controllers in SDM845 device tree * Remove any unnecessary parenthesis & casting * Identify break character in UART line and pass it to the framework * Transmit data from fault handler reliably in debug UART * Map the register block when the UART port is requested * Move concise exported functions as macros or inlines in public header * Move the clock performance table from the wrapper to serial engines * Add a lock to synchronize between IRQ & error handling in I2C controller * Remove any compiler optimization hints like likely/unlikely * Update documentation to clarify tables and hardware blocks [v3] * Update the driver dependencies * Use the SPDX License Expression * Squash all the controller device tree bindings together * Use kernel doc format for documentation * Add additional documentation for packing configuration * Use clk_bulk_* API for related clocks * Remove driver references to pinctrl and their states * Replace magic numbers with appropriate macros * Update memory barrier usage and associated comments * Reduce interlacing of register reads/writes * Fix poll_get_char() operation in console UART driver under polling mode * Address other comments from Bjorn Andersson to improve code readability [v2] * Updated device tree bindings to describe the hardware * Updated SE DT node as child node of QUP Wrapper DT node * Moved common AHB clocks to QUP Wrapper DT node * Use the standard "clock-frequency" I2C property * Update compatible field in UART Controller to reflect hardware manual * Addressed other device tree binding specific comments from Rob Herring Karthikeyan Ramasubramanian (5): dt-bindings: soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP arm64: dts: sdm845: Add I2C controller support Rajendra Nayak (1): arm64: dts: sdm845: Add serial console support .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 123 +++ arch/arm64/boot/dts/qcom/sdm845-mtp.dts| 58 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 67 ++ drivers/i2c/busses/Kconfig | 13 + drivers/i2c/busses/Makefile|1 + drivers/i2c/busses/i2c-qcom-geni.c | 648 +++ drivers/soc/qcom/Kconfig |9 + drivers/soc/qcom/Makefile |1 + drivers/soc/qcom/qcom-geni-se.c| 748 + drivers/tty/serial/Kconfig | 15 + drivers/tty/serial/Makefile|1 + drivers/tty/serial/qcom_geni_serial.c | 1158 include/linux/qcom-geni-se.h | 425 +++ 13 files changed, 3267 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 drivers/tty/serial/qcom_geni_serial.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 5/6] arm64: dts: sdm845: Add serial console support
From: Rajendra Nayak
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 38
2 files changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49..ea3efc5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,43 @@
/ {
model = "Qualcomm Technologies, Inc. SDM845 MTP";
compatible = "qcom,sdm845-mtp";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&soc {
+ geniqup@ac {
+ serial@a84000 {
+ status = "okay";
+ };
+ };
+
+ pinctrl@340 {
+ qup-uart2-default {
+ pinconf_tx {
+ pins = "gpio4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pinconf_rx {
+ pins = "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup-uart2-sleep {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ bias-pull-down;
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 32f8561..59334d9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -194,6 +195,20 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ qup_uart2_default: qup-uart2-default {
+ pinmux {
+ function = "qup9";
+ pins = "gpio4", "gpio5";
+ };
+ };
+
+ qup_uart2_sleep: qup-uart2-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ };
+ };
};
timer@17c9 {
@@ -272,5 +287,28 @@
#interrupt-cells = <4>;
cell-index = <0>;
};
+
+ geniqup@ac {
+ compatible = "qcom,geni-se-qup";
+ reg = <0xac 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart2: serial@a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-1 = <&qup_uart2_sleep>;
+ interrupts = ;
+ status = "disabled";
+ };
+ };
};
};
--
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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the body of a message to majord...@vger.kernel.org
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[PATCH v4 2/6] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia Signed-off-by: Girish Mahadevan --- drivers/soc/qcom/Kconfig| 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c | 748 include/linux/qcom-geni-se.h| 425 +++ 4 files changed, 1183 insertions(+) create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e050eb8..98ca9f5 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,15 @@ # menu "Qualcomm SoC drivers" +config QCOM_GENI_SE + tristate "QCOM GENI Serial Engine Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This driver is used to manage Generic Interface (GENI) firmware based + Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This + driver is also used to manage the common aspects of multiple Serial + Engines present in the QUP. + config QCOM_GLINK_SSR tristate "Qualcomm Glink SSR driver" depends on RPMSG diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index dcebf28..959aa74 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c new file mode 100644 index 000..feed3db2 --- /dev/null +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: Overview + * + * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced + * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper + * controller. QUP Wrapper is designed to support various serial bus protocols + * like UART, SPI, I2C, I3C, etc. + */ + +/** + * DOC: Hardware description + * + * GENI based QUP is a highly-flexible and programmable module for supporting + * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single + * QUP module can provide upto 8 serial interfaces, using its internal + * serial engines. The actual configuration is determined by the target + * platform configuration. The protocol supported by each interface is + * determined by the firmware loaded to the serial engine. Each SE consists + * of a DMA Engine and GENI sub modules which enable serial engines to + * support FIFO and DMA modes of operation. + * + * + * +-+ + * |QUP Wrapper | + * | ++ | + * --QUP & SE Clocks--> | Serial Engine N| +-IO--> + * | | ...| | Interface + * <---Clock Perf.+++---+| | + * State Interface || Serial Engine 1|| | + * |||| | + * |||| | + * <AHB--->||| | + * ||++ | + * ||| | + * ||| | + * <--SE IRQ--+++ | + * | | + * +-+ + * + * Figure 1: GENI based QUP Wrapper + * + * The GENI submodules include primary and secondary sequencers which are + * used to drive TX & RX operations. On serial interfaces that operate using + * master-slave model, primary sequencer drives both TX & RX operations. On + * serial interfaces that operate using peer-to-peer model, primary sequencer + * drives TX operation and secondary sequencer drives RX operation. + */ + +/** + * DOC: Software descripti
[PATCH v4 1/6] dt-bindings: soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 123 +
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..b71b5df
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,123 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be <1> for Serial Engine Address
+- #size-cells: Must be <1> for Serial Engine Address Size
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, SPI controller, or some combination of aforementioned devices.
+Please refer below the child node definitions for the supported serial
+interface protocols.
+
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-i2c".
+- reg: Must contain QUP register address and length.
+- interrupts: Must contain I2C interrupt.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- #address-cells: Must be <1> for I2C device address.
+- #size-cells: Must be <0> as I2C addresses have no size component.
+
+Optional property:
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to I2C bus binding as described in i2c.txt.
+
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-debug-uart".
+- reg: Must contain UART register location and length.
+- interrupts: Must contain UART core interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+
+Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
+
+Required properties:
+- compatible: Must contain "qcom,geni-spi".
+- reg: Must contain SPI register location and length.
+- interrupts: Must contain SPI controller interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
+- #address-cells: Must be <1> to define a chip select address on
+ the SPI bus.
+- #size-cells: Must be <0>.
+
+Optional property:
+- qcom,rt: Indicates if the framework worker thread for this
+ controller device should have real-time priority.
+
+SPI slave nodes must be children of the SPI master node and conform to SPI bus
+binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+ geniqup@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5
[PATCH v4 6/6] arm64: dts: sdm845: Add I2C controller support
Add I2C master controller support for a built-in test I2C slave.
Signed-off-by: Karthikeyan Ramasubramanian
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 19 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 29 +
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index ea3efc5..69445f1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -27,6 +27,10 @@
serial@a84000 {
status = "okay";
};
+
+ i2c@a88000 {
+ status = "okay";
+ };
};
pinctrl@340 {
@@ -50,5 +54,20 @@
bias-pull-down;
};
};
+
+ qup-i2c10-default {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qup-i2c10-sleep {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ bias-pull-up;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 59334d9..9ef056f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -209,6 +209,21 @@
pins = "gpio4", "gpio5";
};
};
+
+ qup_i2c10_default: qup-i2c10-default {
+ pinmux {
+ function = "qup10";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
+ qup_i2c10_sleep: qup-i2c10-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
};
timer@17c9 {
@@ -309,6 +324,20 @@
interrupts = ;
status = "disabled";
};
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_i2c10_default>;
+ pinctrl-1 = <&qup_i2c10_sleep>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
};
--
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a Linux Foundation Collaborative Project
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[PATCH v4 4/6] tty: serial: msm_geni_serial: Add serial driver support for GENI based QUP
This driver supports GENI based UART Controller in the Qualcomm SOCs. The
Qualcomm Generic Interface (GENI) is a programmable module supporting a
wide range of serial interfaces including UART. This driver support console
operations using FIFO mode of transfer.
Signed-off-by: Girish Mahadevan
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Doug Anderson
---
drivers/tty/serial/Kconfig| 15 +
drivers/tty/serial/Makefile |1 +
drivers/tty/serial/qcom_geni_serial.c | 1158 +
3 files changed, 1174 insertions(+)
create mode 100644 drivers/tty/serial/qcom_geni_serial.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3682fd3..d132971 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1104,6 +1104,21 @@ config SERIAL_MSM_CONSOLE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
+config SERIAL_QCOM_GENI
+ tristate "QCOM on-chip GENI based serial port support"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on QCOM_GENI_SE
+ select SERIAL_CORE
+
+config SERIAL_QCOM_GENI_CONSOLE
+ bool "QCOM GENI Serial Console support"
+ depends on SERIAL_QCOM_GENI=y
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Serial console driver for Qualcomm Technologies Inc's GENI based
+ QUP hardware.
+
config SERIAL_VT8500
bool "VIA VT8500 on-chip serial port support"
depends on ARCH_VT8500
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 842d185..64a8d82 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
+obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
diff --git a/drivers/tty/serial/qcom_geni_serial.c
b/drivers/tty/serial/qcom_geni_serial.c
new file mode 100644
index 000..1442777
--- /dev/null
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -0,0 +1,1158 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* UART specific GENI registers */
+#define SE_UART_TX_TRANS_CFG 0x25c
+#define SE_UART_TX_WORD_LEN0x268
+#define SE_UART_TX_STOP_BIT_LEN0x26c
+#define SE_UART_TX_TRANS_LEN 0x270
+#define SE_UART_RX_TRANS_CFG 0x280
+#define SE_UART_RX_WORD_LEN0x28c
+#define SE_UART_RX_STALE_CNT 0x294
+#define SE_UART_TX_PARITY_CFG 0x2a4
+#define SE_UART_RX_PARITY_CFG 0x2a8
+
+/* SE_UART_TRANS_CFG */
+#define UART_TX_PAR_EN BIT(0)
+#define UART_CTS_MASK BIT(1)
+
+/* SE_UART_TX_WORD_LEN */
+#define TX_WORD_LEN_MSKGENMASK(9, 0)
+
+/* SE_UART_TX_STOP_BIT_LEN */
+#define TX_STOP_BIT_LEN_MSKGENMASK(23, 0)
+#define TX_STOP_BIT_LEN_1 0
+#define TX_STOP_BIT_LEN_1_51
+#define TX_STOP_BIT_LEN_2 2
+
+/* SE_UART_TX_TRANS_LEN */
+#define TX_TRANS_LEN_MSK GENMASK(23, 0)
+
+/* SE_UART_RX_TRANS_CFG */
+#define UART_RX_INS_STATUS_BIT BIT(2)
+#define UART_RX_PAR_EN BIT(3)
+
+/* SE_UART_RX_WORD_LEN */
+#define RX_WORD_LEN_MASK GENMASK(9, 0)
+
+/* SE_UART_RX_STALE_CNT */
+#define RX_STALE_CNT GENMASK(23, 0)
+
+/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
+#define PAR_CALC_ENBIT(0)
+#define PAR_MODE_MSK GENMASK(2, 1)
+#define PAR_MODE_SHFT 1
+#define PAR_EVEN 0x00
+#define PAR_ODD0x01
+#define PAR_SPACE 0x10
+#define PAR_MARK 0x11
+
+/* UART M_CMD OP codes */
+#define UART_START_TX 0x1
+#define UART_START_BREAK 0x4
+#define UART_STOP_BREAK0x5
+/* UART S_CMD OP codes */
+#define UART_START_READ0x1
+#define UART_PARAM 0x1
+
+#define UART_OVERSAMPLING 32
+#define STALE_TIMEOUT 16
+#define DEFAULT_BITS_PER_CHAR 10
+#define GENI_UART_CONS_PORTS 1
+#define DEF_FIFO_DEPTH_WORDS 16
+#define DEF_TX_WM 2
+#define DEF_FIFO_WIDTH_BITS32
+#define UART_CONSOLE_RX_WM 2
+
+#ifdef CONFIG_CONSOLE_POLL
+#define RX_BYTES_PW 1
+#else
+#define RX_BYTES_PW 4
+#endif
+
+struct qcom_geni_serial_port {
+ struct uart_port uport;
+ struct geni_se se;
+ char name[20];
+ u32 tx_fifo_depth;
+ u32 tx_fifo_width;
+ u32 rx_fifo_depth;
+ u32 tx_wm;
+ u32 rx_wm;
+ u32 rx_rfr;
+
[PATCH v4 3/6] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/i2c/busses/Kconfig | 13 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 648 +
3 files changed, 662 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e2954fb..89e642a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -848,6 +848,19 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on QCOM_GENI_SE
+ help
+ This driver supports GENI serial engine based I2C controller in
+ master mode on the Qualcomm Technologies Inc.'s SoCs. If you say
+ yes to this option, support will be included for the built-in I2C
+ interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..4926efb
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,648 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+enum geni_i2c_err_code {
+ GP_IRQ0,
+ NACK,
+ GP_IRQ2,
+ BUS_PROTO,
+ ARB_LOST,
+ GP_IRQ5,
+ GENI_OVERRUN,
+ GENI_ILLEGAL_CMD,
+ GENI_ABORT_DONE,
+ GENI_TIMEOUT,
+};
+
+#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHZ(freq) (1000 * freq)
+#define PACKING_BYTES_PW 4
+
+#define ABORT_TIMEOUT HZ
+#define XFER_TIMEOUT HZ
+#define RST_TIMEOUTHZ
+
+struct geni_i2c_dev {
+ struct geni_se se;
+ u32 tx_wm;
+ int irq;
+ int err;
+ struct i2c_adapter adap;
+ struct completion done;
+ struct i2c_msg *cur;
+ int cur_wr;
+ int cur_rd;
+ spinlock_t lock;
+ u32 clk_freq_out;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+struct geni_i2c
[PATCH v5 1/5] dt-bindings: soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 119 +
1 file changed, 119 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..d330c73
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,119 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be <1> for Serial Engine Address
+- #size-cells: Must be <1> for Serial Engine Address Size
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, SPI controller, or some combination of aforementioned devices.
+Please refer below the child node definitions for the supported serial
+interface protocols.
+
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-i2c".
+- reg: Must contain QUP register address and length.
+- interrupts: Must contain I2C interrupt.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- #address-cells: Must be <1> for I2C device address.
+- #size-cells: Must be <0> as I2C addresses have no size component.
+
+Optional property:
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to I2C bus binding as described in i2c.txt.
+
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-debug-uart".
+- reg: Must contain UART register location and length.
+- interrupts: Must contain UART core interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+
+Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
+
+Required properties:
+- compatible: Must contain "qcom,geni-spi".
+- reg: Must contain SPI register location and length.
+- interrupts: Must contain SPI controller interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
+- #address-cells: Must be <1> to define a chip select address on
+ the SPI bus.
+- #size-cells: Must be <0>.
+
+SPI slave nodes must be children of the SPI master node and conform to SPI bus
+binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+ geniqup@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+
[PATCH v5 0/5] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. [v5] * Remove Linux specific property from the device tree binding * Clarify I2C SCL time period documentation * Remove redundant checks in I2C controller driver during timeout * Use 100kHz as the default clock frequency in the I2C controller driver * Disable Wrapper controller by default in the SDM845 device tree and enable it explicitly for SDM845 MTP * Specify I2C clock frequency in the SDM845 device tree * Remove bias configuration for I2C pins under sleep state in device tree * Drop the serial driver from the patch series since it is merged * Specify the UART port options in the SDM845 device tree [v4] * Add SPI controller information in device tree binding * Add support for debug UART & I2C controllers in SDM845 device tree * Remove any unnecessary parenthesis & casting * Identify break character in UART line and pass it to the framework * Transmit data from fault handler reliably in debug UART * Map the register block when the UART port is requested * Move concise exported functions as macros or inlines in public header * Move the clock performance table from the wrapper to serial engines * Add a lock to synchronize between IRQ & error handling in I2C controller * Remove any compiler optimization hints like likely/unlikely * Update documentation to clarify tables and hardware blocks [v3] * Update the driver dependencies * Use the SPDX License Expression * Squash all the controller device tree bindings together * Use kernel doc format for documentation * Add additional documentation for packing configuration * Use clk_bulk_* API for related clocks * Remove driver references to pinctrl and their states * Replace magic numbers with appropriate macros * Update memory barrier usage and associated comments * Reduce interlacing of register reads/writes * Fix poll_get_char() operation in console UART driver under polling mode * Address other comments from Bjorn Andersson to improve code readability [v2] * Updated device tree bindings to describe the hardware * Updated SE DT node as child node of QUP Wrapper DT node * Moved common AHB clocks to QUP Wrapper DT node * Use the standard "clock-frequency" I2C property * Update compatible field in UART Controller to reflect hardware manual * Addressed other device tree binding specific comments from Rob Herring Karthikeyan Ramasubramanian (4): dt-bindings: soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller arm64: dts: sdm845: Add support for an instance of I2C controller Rajendra Nayak (1): arm64: dts: sdm845: Add serial console support .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 119 arch/arm64/boot/dts/qcom/sdm845-mtp.dts| 59 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 68 ++ drivers/i2c/busses/Kconfig | 13 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-qcom-geni.c | 650 ++ drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c| 748 + include/linux/qcom-geni-se.h | 425 10 files changed, 2093 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 4/5] arm64: dts: sdm845: Add serial console support
From: Rajendra Nayak
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
Signed-off-by: Karthikeyan Ramasubramanian
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 41 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 +++
2 files changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49..17b2fb0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,45 @@
/ {
model = "Qualcomm Technologies, Inc. SDM845 MTP";
compatible = "qcom,sdm845-mtp";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&soc {
+ geniqup@ac {
+ status = "okay";
+
+ serial@a84000 {
+ status = "okay";
+ };
+ };
+
+ pinctrl@340 {
+ qup-uart2-default {
+ pinconf_tx {
+ pins = "gpio4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pinconf_rx {
+ pins = "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup-uart2-sleep {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ bias-pull-down;
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 32f8561..71801b9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -194,6 +195,20 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ qup_uart2_default: qup-uart2-default {
+ pinmux {
+ function = "qup9";
+ pins = "gpio4", "gpio5";
+ };
+ };
+
+ qup_uart2_sleep: qup-uart2-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ };
+ };
};
timer@17c9 {
@@ -272,5 +287,29 @@
#interrupt-cells = <4>;
cell-index = <0>;
};
+
+ geniqup@ac {
+ compatible = "qcom,geni-se-qup";
+ reg = <0xac 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ uart2: serial@a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-1 = <&qup_uart2_sleep>;
+ interrupts = ;
+ status = "disabled";
+ };
+ };
};
};
--
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[PATCH v5 3/5] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
---
drivers/i2c/busses/Kconfig | 13 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 650 +
3 files changed, 664 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e2954fb..89e642a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -848,6 +848,19 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on QCOM_GENI_SE
+ help
+ This driver supports GENI serial engine based I2C controller in
+ master mode on the Qualcomm Technologies Inc.'s SoCs. If you say
+ yes to this option, support will be included for the built-in I2C
+ interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..24f859d
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,650 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+enum geni_i2c_err_code {
+ GP_IRQ0,
+ NACK,
+ GP_IRQ2,
+ BUS_PROTO,
+ ARB_LOST,
+ GP_IRQ5,
+ GENI_OVERRUN,
+ GENI_ILLEGAL_CMD,
+ GENI_ABORT_DONE,
+ GENI_TIMEOUT,
+};
+
+#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHZ(freq) (1000 * freq)
+#define PACKING_BYTES_PW 4
+
+#define ABORT_TIMEOUT HZ
+#define XFER_TIMEOUT HZ
+#define RST_TIMEOUTHZ
+
+struct geni_i2c_dev {
+ struct geni_se se;
+ u32 tx_wm;
+ int irq;
+ int err;
+ struct i2c_adapter adap;
+ struct completion done;
+ struct i2c_msg *cur;
+ int cur_wr;
+ int cur_rd;
+ spinlock_t lock;
+ u32 clk_freq_out;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+struct geni_i2c
[PATCH v5 5/5] arm64: dts: sdm845: Add support for an instance of I2C controller
Add one instance of GENI based I2C master controller to enable testing
I2C driver using EEPROM slave.
Signed-off-by: Karthikeyan Ramasubramanian
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 18 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 29 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 17b2fb0..e82c98d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -29,9 +29,27 @@
serial@a84000 {
status = "okay";
};
+
+ i2c@a88000 {
+ status = "okay";
+ };
};
pinctrl@340 {
+ qup-i2c10-default {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qup-i2c10-sleep {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ };
+ };
+
qup-uart2-default {
pinconf_tx {
pins = "gpio4";
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 71801b9..a13836f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -196,6 +196,20 @@
interrupt-controller;
#interrupt-cells = <2>;
+ qup_i2c10_default: qup-i2c10-default {
+ pinmux {
+ function = "qup10";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
+ qup_i2c10_sleep: qup-i2c10-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
qup_uart2_default: qup-uart2-default {
pinmux {
function = "qup9";
@@ -310,6 +324,21 @@
interrupts = ;
status = "disabled";
};
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_i2c10_default>;
+ pinctrl-1 = <&qup_i2c10_sleep>;
+ interrupts = ;
+ clock-frequency = <40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
};
--
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a Linux Foundation Collaborative Project
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[PATCH v5 2/5] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia Signed-off-by: Girish Mahadevan --- drivers/soc/qcom/Kconfig| 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c | 748 include/linux/qcom-geni-se.h| 425 +++ 4 files changed, 1183 insertions(+) create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e050eb8..98ca9f5 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,15 @@ # menu "Qualcomm SoC drivers" +config QCOM_GENI_SE + tristate "QCOM GENI Serial Engine Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This driver is used to manage Generic Interface (GENI) firmware based + Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This + driver is also used to manage the common aspects of multiple Serial + Engines present in the QUP. + config QCOM_GLINK_SSR tristate "Qualcomm Glink SSR driver" depends on RPMSG diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index dcebf28..959aa74 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c new file mode 100644 index 000..feed3db2 --- /dev/null +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: Overview + * + * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced + * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper + * controller. QUP Wrapper is designed to support various serial bus protocols + * like UART, SPI, I2C, I3C, etc. + */ + +/** + * DOC: Hardware description + * + * GENI based QUP is a highly-flexible and programmable module for supporting + * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single + * QUP module can provide upto 8 serial interfaces, using its internal + * serial engines. The actual configuration is determined by the target + * platform configuration. The protocol supported by each interface is + * determined by the firmware loaded to the serial engine. Each SE consists + * of a DMA Engine and GENI sub modules which enable serial engines to + * support FIFO and DMA modes of operation. + * + * + * +-+ + * |QUP Wrapper | + * | ++ | + * --QUP & SE Clocks--> | Serial Engine N| +-IO--> + * | | ...| | Interface + * <---Clock Perf.+++---+| | + * State Interface || Serial Engine 1|| | + * |||| | + * |||| | + * <AHB--->||| | + * ||++ | + * ||| | + * ||| | + * <--SE IRQ--+++ | + * | | + * +-+ + * + * Figure 1: GENI based QUP Wrapper + * + * The GENI submodules include primary and secondary sequencers which are + * used to drive TX & RX operations. On serial interfaces that operate using + * master-slave model, primary sequencer drives both TX & RX operations. On + * serial interfaces that operate using peer-to-peer model, primary sequencer + * drives TX operation and secondary sequencer drives RX operation. + */ + +/** + * DOC: Software descripti
[PATCH v6 5/5] arm64: dts: sdm845: Add support for an instance of I2C controller
Add one instance of GENI based I2C master controller to enable testing
I2C driver using EEPROM slave.
Signed-off-by: Karthikeyan Ramasubramanian
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 19 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 28
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 17b2fb0..dbe3a36 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -29,9 +29,28 @@
serial@a84000 {
status = "okay";
};
+
+ i2c@a88000 {
+ clock-frequency = <40>;
+ status = "okay";
+ };
};
pinctrl@340 {
+ qup-i2c10-default {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qup-i2c10-sleep {
+ pinconf {
+ pins = "gpio55", "gpio56";
+ };
+ };
+
qup-uart2-default {
pinconf_tx {
pins = "gpio4";
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 71801b9..d367020 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -196,6 +196,20 @@
interrupt-controller;
#interrupt-cells = <2>;
+ qup_i2c10_default: qup-i2c10-default {
+ pinmux {
+ function = "qup10";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
+ qup_i2c10_sleep: qup-i2c10-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio55", "gpio56";
+ };
+ };
+
qup_uart2_default: qup-uart2-default {
pinmux {
function = "qup9";
@@ -310,6 +324,20 @@
interrupts = ;
status = "disabled";
};
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_i2c10_default>;
+ pinctrl-1 = <&qup_i2c10_sleep>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
};
--
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[PATCH v6 3/5] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller
This bus driver supports the GENI based i2c hardware controller in the
Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable
module supporting a wide range of serial interfaces including I2C. The
driver supports FIFO mode and DMA mode of transfer and switches modes
dynamically depending on the size of the transfer.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
Reviewed-by: Douglas Anderson
---
drivers/i2c/busses/Kconfig | 13 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-qcom-geni.c | 649 +
3 files changed, 663 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e2954fb..89e642a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -848,6 +848,19 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a target on the
I2C bus.
+config I2C_QCOM_GENI
+ tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on QCOM_GENI_SE
+ help
+ This driver supports GENI serial engine based I2C controller in
+ master mode on the Qualcomm Technologies Inc.'s SoCs. If you say
+ yes to this option, support will be included for the built-in I2C
+ interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-geni.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..201fce1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_QCOM_GENI)+= i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
new file mode 100644
index 000..3220374
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -0,0 +1,649 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+enum geni_i2c_err_code {
+ GP_IRQ0,
+ NACK,
+ GP_IRQ2,
+ BUS_PROTO,
+ ARB_LOST,
+ GP_IRQ5,
+ GENI_OVERRUN,
+ GENI_ILLEGAL_CMD,
+ GENI_ABORT_DONE,
+ GENI_TIMEOUT,
+};
+
+#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
+ << 5)
+
+#define I2C_AUTO_SUSPEND_DELAY 250
+#define KHZ(freq) (1000 * freq)
+#define PACKING_BYTES_PW 4
+
+#define ABORT_TIMEOUT HZ
+#define XFER_TIMEOUT HZ
+#define RST_TIMEOUTHZ
+
+struct geni_i2c_dev {
+ struct geni_se se;
+ u32 tx_wm;
+ int irq;
+ int err;
+ struct i2c_adapter adap;
+ struct completion done;
+ struct i2c_msg *cur;
+ int cur_wr;
+ int cur_rd;
+ spinlock_t lock;
+ u32 clk_freq_out;
+ const struct geni_i2c_clk_fld
[PATCH v6 0/5] Introduce GENI SE Controller Driver
Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper is a next generation programmable module for supporting a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial Interfaces using its internal Serial Engines (SE). The protocol supported by each interface is determined by the firmware loaded to the Serial Engine. This patch series introduces GENI SE Driver to manage the GENI based QUP Wrapper and the common aspects of all SEs inside the QUP Wrapper. This patch series also introduces the UART and I2C Controller drivers to drive the SEs that are programmed with the respective protocols. [v6] * Move the I2C clock-frequency configuration to the SDM845 board file * Remove a redundant comment in the I2C driver [v5] * Remove Linux specific property from the device tree binding * Clarify I2C SCL time period documentation * Remove redundant checks in I2C controller driver during timeout * Use 100kHz as the default clock frequency in the I2C controller driver * Disable Wrapper controller by default in the SDM845 device tree and enable it explicitly for SDM845 MTP * Specify I2C clock frequency in the SDM845 device tree * Remove bias configuration for I2C pins under sleep state in device tree * Drop the serial driver from the patch series since it is merged * Specify the UART port options in the SDM845 device tree [v4] * Add SPI controller information in device tree binding * Add support for debug UART & I2C controllers in SDM845 device tree * Remove any unnecessary parenthesis & casting * Identify break character in UART line and pass it to the framework * Transmit data from fault handler reliably in debug UART * Map the register block when the UART port is requested * Move concise exported functions as macros or inlines in public header * Move the clock performance table from the wrapper to serial engines * Add a lock to synchronize between IRQ & error handling in I2C controller * Remove any compiler optimization hints like likely/unlikely * Update documentation to clarify tables and hardware blocks [v3] * Update the driver dependencies * Use the SPDX License Expression * Squash all the controller device tree bindings together * Use kernel doc format for documentation * Add additional documentation for packing configuration * Use clk_bulk_* API for related clocks * Remove driver references to pinctrl and their states * Replace magic numbers with appropriate macros * Update memory barrier usage and associated comments * Reduce interlacing of register reads/writes * Fix poll_get_char() operation in console UART driver under polling mode * Address other comments from Bjorn Andersson to improve code readability [v2] * Updated device tree bindings to describe the hardware * Updated SE DT node as child node of QUP Wrapper DT node * Moved common AHB clocks to QUP Wrapper DT node * Use the standard "clock-frequency" I2C property * Update compatible field in UART Controller to reflect hardware manual * Addressed other device tree binding specific comments from Rob Herring Karthikeyan Ramasubramanian (4): dt-bindings: soc: qcom: Add device tree binding for GENI SE soc: qcom: Add GENI based QUP Wrapper driver i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller arm64: dts: sdm845: Add support for an instance of I2C controller Rajendra Nayak (1): arm64: dts: sdm845: Add serial console support .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 119 arch/arm64/boot/dts/qcom/sdm845-mtp.dts| 60 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 67 ++ drivers/i2c/busses/Kconfig | 13 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-qcom-geni.c | 649 ++ drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c| 748 + include/linux/qcom-geni-se.h | 425 10 files changed, 2092 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt create mode 100644 drivers/i2c/busses/i2c-qcom-geni.c create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 4/5] arm64: dts: sdm845: Add serial console support
From: Rajendra Nayak
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
Signed-off-by: Karthikeyan Ramasubramanian
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 41 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 +++
2 files changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49..17b2fb0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,45 @@
/ {
model = "Qualcomm Technologies, Inc. SDM845 MTP";
compatible = "qcom,sdm845-mtp";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&soc {
+ geniqup@ac {
+ status = "okay";
+
+ serial@a84000 {
+ status = "okay";
+ };
+ };
+
+ pinctrl@340 {
+ qup-uart2-default {
+ pinconf_tx {
+ pins = "gpio4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pinconf_rx {
+ pins = "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup-uart2-sleep {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ bias-pull-down;
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 32f8561..71801b9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -194,6 +195,20 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ qup_uart2_default: qup-uart2-default {
+ pinmux {
+ function = "qup9";
+ pins = "gpio4", "gpio5";
+ };
+ };
+
+ qup_uart2_sleep: qup-uart2-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ };
+ };
};
timer@17c9 {
@@ -272,5 +287,29 @@
#interrupt-cells = <4>;
cell-index = <0>;
};
+
+ geniqup@ac {
+ compatible = "qcom,geni-se-qup";
+ reg = <0xac 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ uart2: serial@a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-1 = <&qup_uart2_sleep>;
+ interrupts = ;
+ status = "disabled";
+ };
+ };
};
};
--
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-doc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 2/5] soc: qcom: Add GENI based QUP Wrapper driver
This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia Signed-off-by: Girish Mahadevan --- drivers/soc/qcom/Kconfig| 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-geni-se.c | 748 include/linux/qcom-geni-se.h| 425 +++ 4 files changed, 1183 insertions(+) create mode 100644 drivers/soc/qcom/qcom-geni-se.c create mode 100644 include/linux/qcom-geni-se.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e050eb8..98ca9f5 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,15 @@ # menu "Qualcomm SoC drivers" +config QCOM_GENI_SE + tristate "QCOM GENI Serial Engine Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This driver is used to manage Generic Interface (GENI) firmware based + Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This + driver is also used to manage the common aspects of multiple Serial + Engines present in the QUP. + config QCOM_GLINK_SSR tristate "Qualcomm Glink SSR driver" depends on RPMSG diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index dcebf28..959aa74 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_GLINK_SSR) +=glink_ssr.o obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c new file mode 100644 index 000..feed3db2 --- /dev/null +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: Overview + * + * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced + * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper + * controller. QUP Wrapper is designed to support various serial bus protocols + * like UART, SPI, I2C, I3C, etc. + */ + +/** + * DOC: Hardware description + * + * GENI based QUP is a highly-flexible and programmable module for supporting + * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single + * QUP module can provide upto 8 serial interfaces, using its internal + * serial engines. The actual configuration is determined by the target + * platform configuration. The protocol supported by each interface is + * determined by the firmware loaded to the serial engine. Each SE consists + * of a DMA Engine and GENI sub modules which enable serial engines to + * support FIFO and DMA modes of operation. + * + * + * +-+ + * |QUP Wrapper | + * | ++ | + * --QUP & SE Clocks--> | Serial Engine N| +-IO--> + * | | ...| | Interface + * <---Clock Perf.+++---+| | + * State Interface || Serial Engine 1|| | + * |||| | + * |||| | + * <AHB--->||| | + * ||++ | + * ||| | + * ||| | + * <--SE IRQ--+++ | + * | | + * +-+ + * + * Figure 1: GENI based QUP Wrapper + * + * The GENI submodules include primary and secondary sequencers which are + * used to drive TX & RX operations. On serial interfaces that operate using + * master-slave model, primary sequencer drives both TX & RX operations. On + * serial interfaces that operate using peer-to-peer model, primary sequencer + * drives TX operation and secondary sequencer drives RX operation. + */ + +/** + * DOC: Software descripti
[PATCH v6 1/5] dt-bindings: soc: qcom: Add device tree binding for GENI SE
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian
Signed-off-by: Sagar Dharia
Signed-off-by: Girish Mahadevan
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 119 +
1 file changed, 119 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 000..d330c73
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,119 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be <1> for Serial Engine Address
+- #size-cells: Must be <1> for Serial Engine Address Size
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, SPI controller, or some combination of aforementioned devices.
+Please refer below the child node definitions for the supported serial
+interface protocols.
+
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-i2c".
+- reg: Must contain QUP register address and length.
+- interrupts: Must contain I2C interrupt.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- #address-cells: Must be <1> for I2C device address.
+- #size-cells: Must be <0> as I2C addresses have no size component.
+
+Optional property:
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+ When missing default to 40Hz.
+
+Child nodes should conform to I2C bus binding as described in i2c.txt.
+
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-debug-uart".
+- reg: Must contain UART register location and length.
+- interrupts: Must contain UART core interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+
+Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
+
+Required properties:
+- compatible: Must contain "qcom,geni-spi".
+- reg: Must contain SPI register location and length.
+- interrupts: Must contain SPI controller interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
+- #address-cells: Must be <1> to define a chip select address on
+ the SPI bus.
+- #size-cells: Must be <0>.
+
+SPI slave nodes must be children of the SPI master node and conform to SPI bus
+binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+ geniqup@8c {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa94000 0x4000>;
+ interrupts = ;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+
