Re: [PATCH v2 1/3] dt-bindings: add compatible string for Allwinner V3s SoC
在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Maxime,
Ping. Have you checked this patchset?
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
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Re: [PATCH v2 1/3] dt-bindings: add compatible string for Allwinner V3s SoC
在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Maxime, Chen-Yu, ping.
Could you queue this patchset to 4.15?
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
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[PATCH v2 2/3] ARM: sunxi: fix the core number of V3s in sunxi README
The Allwinner V3s SoC is not quad-core, but single-core.
Fix this in the README file.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/README | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..de791e18ccef 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -33,6 +33,11 @@ SunXi family
- Next Thing Co GR8 (sun5i)
+* Single ARM Cortex-A7 based SoCs
+ - Allwinner V3s (sun8i)
++ Datasheet
+ http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+
* Dual ARM Cortex-A7 based SoCs
- Allwinner A20 (sun7i)
+ User Manual
@@ -71,10 +76,6 @@ SunXi family
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
- - Allwinner V3s (sun8i)
-+ Datasheet
- http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
-
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
--
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[PATCH v2 3/3] ARM: sunxi: add support for R40 SoC
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Fix alphabetical orders.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index de791e18ccef..f8efc21998bf 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -76,6 +76,12 @@ SunXi family
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet
+ https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index f35c6ada5a65..e4beec3d9ad3 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 7ab353fb25f2..5e9602ce1573 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -65,6 +65,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
+ "allwinner,sun8i-r40",
"allwinner,sun8i-v3s",
NULL,
};
--
2.13.5
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[PATCH v2 1/3] dt-bindings: add compatible string for Allwinner V3s SoC
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
--
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Re: [PATCH 2/2] ARM: sunxi: add support for R40 SoC
在 2017-08-21 17:34，Maxime Ripard 写道：
Hi,
On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm/sunxi/README
b/Documentation/arm/sunxi/README
index d7b1f016bd62..4fa836782e46 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,12 @@ SunXi family
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet
+
https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
Please sort it by alphabetical order.
I prefer to sort it by the wafer ID (the number after w in the official
ID).
The current document can be explained to follow the alphabetical order
or the wafer ID.
P.S. there's some error in the V3s datasheet position, and if it's fixed
we can still continue to make the two kinds of order both meaningful ;-)
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index f35c6ada5a65..e4beec3d9ad3 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 7ab353fb25f2..311e6c4fc4f4 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] =
{
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+ "allwinner,sun8i-r40",
And same thing here.
Thanks!
Maxime
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[PATCH 2/2] ARM: sunxi: add support for R40 SoC
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..4fa836782e46 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,12 @@ SunXi family
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet
+ https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index f35c6ada5a65..e4beec3d9ad3 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 7ab353fb25f2..311e6c4fc4f4 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+ "allwinner,sun8i-r40",
NULL,
};
--
2.13.0
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[PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
--
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Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
在 2017-08-12 12:04，Chen-Yu Tsai 写道： On Sat, Jul 22, 2017 at 11:00 AM, <icen...@aosc.io> wrote: 在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: [...] + +/* + * For the special bit in gate part, please see the BSP source code at + * https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665 + */ +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_sata_clk, "pll-sata", + "osc24M", 0x034, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31) | BIT(14), /* gate */ + BIT(28),/* lock */ + 0); I think this is a somewhat simplified approach. From what I understand of the user manual, the SATA clock path look like: [ PLL-PERIPH0-SATA ] -\ mux @ 0x34 bit 30 --- gate @ 0x34 bit 14 --- ... [ PLL-SATA ] -/ ... from above ... --\ mux @ 0xc8 bit 24 --- gate @ 0xc8 bit 31 [ external oscillator ] -/ If you choose to simplify the implementation, please include a detailed note as to why you chose to do so, and the validity of the simplification. I think it can be fully implemented... But how should I call the internal clock controlled by the mux @ 0x34 bit 30? sata-pll-mux? I choose to call it pll-sata-out, as the mux @ 0x34 bit 30 is called "PLL_OUTPUT_SEL". ChenYu ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Rebased on current linux-next. Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h ... +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7,/* N */ N has minimum and maximum limits. These constraints are never implemented in old SoCs. -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver
在 2017-05-29 21:11，Chen-Yu Tsai 写道：
On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272
+-
2 files changed, 197 insertions(+), 77 deletions(-)
diff --git a/drivers/pinctrl/sunxi/Kconfig
b/drivers/pinctrl/sunxi/Kconfig
index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I || MACH_SUN7I
+ def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
[...]
@@ -162,14 +183,19 @@ static const struct sunxi_desc_pin
sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "can"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
-PINCTRL_SUN7I_A20),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_FUNCTION(0x2, "i2c0"),/* SCK */
+ SUNXI_FUNCTION_VARIANT(0x3,
+"pll-lock-dbg",
Can you stick to underscores to be consistent?
OK...
This is a so strange pin name and I just picked the datasheet
name.
I don't care how to name it as I don't even know what this is.
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -177,11 +203,19 @@ static const struct sunxi_desc_pin
sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "pwm")),/* PWM0 */
+ SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
+PINCTRL_SUN4I_A10 |
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "ir0"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */
+PINCTRL_SUN4I_A10 |
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm0", /* PWM1 */
The numbering is wrong. Just drop the number altogether, like all the
other instances.
+PINCTRL_SUN8I_R40),
/*
* The SPDIF block is not referenced at all in the A10 user
* manual. However it is described in the code leaked and the
@@ -205,7 +239,8 @@ static const struct sunxi_desc_pin
sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
-PINCTRL_SUN7I_A20),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40),
Maybe we could use "i2s" instead, like on the A10. I don't know where
i2s1 is used, but it certainly isn't routed outside the SoC, and i2s2
looks like it's for dw-hdmi's audio path.
Nope, it's r
[PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai <w...@csie.org>
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Pinmux changes.
arch/arm/boot/dts/sun8i-r40.dtsi | 408 +++
1 file changed, 408 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..1d36485c6ef7
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ aliases {
+ };
+
+ chosen {
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ re
[PATCH v3 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: - Added Rob's ACK. Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index b53224473672..3ab9f7849a19 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -22,6 +22,7 @@ Required properties: "allwinner,sun8i-a83t-pinctrl" "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" + "allwinner,sun8i-r40-pinctrl" "allwinner,sun50i-a64-pinctrl" "allwinner,sun50i-a64-r-pinctrl" "allwinner,sun50i-h5-pinctrl" -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Commit message change.
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a9d315a1256c..1bfc0d8a55df 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -87,6 +87,9 @@
#define PINCTRL_SUN5I_GR8 BIT(3)
#define PINCTRL_SUN6I_A31 BIT(4)
#define PINCTRL_SUN6I_A31S BIT(5)
+#define PINCTRL_SUN4I_A10 BIT(6)
+#define PINCTRL_SUN7I_A20 BIT(7)
+#define PINCTRL_SUN8I_R40 BIT(8)
struct sunxi_desc_function {
unsigned long variant;
--
2.12.2
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 07/10] dt-bindings: add compatible string for Allwinner R40 CCU
Allwinner R40 has a clock controlling unit like the ones on other Allwinner SoCs after sun6i, and can also use a CCU-based driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: - Rebased on current linux-next. - Added Rob's ACK. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 34b2a9249a94..80926c5db86b 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -9,6 +9,7 @@ Required properties : - "allwinner,sun8i-a83t-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-r-ccu" + - "allwinner,sun8i-r40-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
From: Chen-Yu Tsai <w...@csie.org>
The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 2 GB DDR3 DRAM
- 8 GB eMMC
- micro SD card slot
- DC power jack
- HDMI output
- MIPI DSI connector
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 chip, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- consumer IR receiver
- audio out headphone jack
- onboard microphone
- red, green, and blue LEDs
- debug UART pins
- Li-Po battery connector
- Raspberry Pi B+ compatible GPIO header
- power, reset, and boot control buttons
This patch adds a dts file that enables debug UART and MMC support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Pinmux changes.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 157 ++
2 files changed, 158 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f68d6e0bc746..697c600bba28 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -910,6 +910,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-parrot.dtb \
+ sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..c4e69847cea1
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Banana Pi BPI-M2-Ultra";
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ };
+};
+
+ {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x34&
[PATCH v3 03/10] pinctrl: sunxi: add A20 support to A10 driver
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Enable A10 driver for A20 and disable A20 driver in this commit, in
order to prevent A10 driver from conflicting with A20 driver.
drivers/pinctrl/sunxi/Kconfig | 4 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
2 files changed, 226 insertions(+), 65 deletions(-)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 793e6f94fa0b..8224932e77a6 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I
+ def_bool MACH_SUN4I || MACH_SUN7I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
@@ -24,7 +24,7 @@ config PINCTRL_SUN6I_A31_R
select PINCTRL_SUNXI
config PINCTRL_SUN7I_A20
- def_bool MACH_SUN7I
+ bool
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fb30b86a97ee..159580c04b14 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -24,101 +24,147 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2")),/* RTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
- SUNXI_FUNCTION(0x4, "uart2")),/* CTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2")),/* TX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
- SUNXI_FUNCTION(0x4, "uart2")),/* RX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
[PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Rebased on current linux-next. Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 67acef3d2494..c11ad3375907 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -157,6 +157,16 @@ config SUN8I_DE2_CCU select SUNXI_CCU_DIV select SUNXI_CCU_GATE +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 0185c6ffadcb..217db667a994 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)+= ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..484a8956f59c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4, /* M */ +
[PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 +-
2 files changed, 197 insertions(+), 77 deletions(-)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I || MACH_SUN7I
+ def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "
[PATCH v3 04/10] pinctrl: sunxi: drop dedicated A20 driver
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Only remove the A20 driver(A10 driver for A20 is enabled in
the previous commit now).
drivers/pinctrl/sunxi/Kconfig |4 -
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 -
2 files changed, 1060 deletions(-)
delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 8224932e77a6..624d84e6c936 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -23,10 +23,6 @@ config PINCTRL_SUN6I_A31_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
-config PINCTRL_SUN7I_A20
- bool
- select PINCTRL_SUNXI
-
config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
deleted file mode 100644
index b6f4c68ffb39..
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-/*
- * Allwinner A20 SoCs pinctrl driver.
- *
- * Copyright (C) 2014 Maxime Ripard
- *
- * Maxime Ripard <maxime.rip...@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include
-#include
-#include
-#include
-#include
-
-#include "pinctrl-sunxi.h"
-
-static const struct sunxi_desc_pin sun7i_a20_pins[] = {
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
- SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
- SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2"), /* TX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
- SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
- SUNXI_FUNCTION(0x4, "uart2"), /* RX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
- SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
- SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
- SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
- SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
- SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-
[PATCH v3 00/10] Initial Allwinner R40 support
This is the first non-RFC version of this patchset, which added basical support including I2C, UART and MMC to the mainline Linux. The pinctrl driver of A20 is also merged into the one of A10 before R40 support is added into the A10 driver. Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (8): arm: sunxi: add support for R40 SoC pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs pinctrl: sunxi: add A20 support to A10 driver pinctrl: sunxi: drop dedicated A20 driver dt-bindings: add compatible string for Allwinner R40 pinctrl pinctrl: sunxi: add support of R40 to A10 pinctrl driver dt-bindings: add compatible string for Allwinner R40 CCU clk: sunxi-ng: support R40 SoC Documentation/arm/sunxi/README |6 + Documentation/devicetree/bindings/arm/sunxi.txt|1 + .../devicetree/bindings/clock/sunxi-ccu.txt|1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt |1 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 157 +++ arch/arm/boot/dts/sun8i-r40.dtsi | 408 +++ arch/arm/mach-sunxi/sunxi.c|1 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ drivers/pinctrl/sunxi/Kconfig |6 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 449 ++-- drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 -- drivers/pinctrl/sunxi/pinctrl-sunxi.h |3 + include/dt-bindings/clock/sun8i-r40-ccu.h | 191 include/dt-bindings/reset/sun8i-r40-ccu.h | 129 +++ 18 files changed, 2497 insertions(+), 1145 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 01/10] arm: sunxi: add support for R40 SoC
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Use V1.0 documents.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..af56321137e8 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,12 @@ SunXi family
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet
+
https://github.com/tinalinux/docs/blob/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+
https://github.com/tinalinux/docs/blob/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..b3ffe6cf821a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index f44e3acb5c90..aea616759451 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+ "allwinner,sun8i-r40",
NULL,
};
--
2.12.2
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[PATCH v2 01/10] arm: sunxi: add support for R40 SoC
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Documentation/arm/sunxi/README | 4
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..25c814adcd47 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,10 @@ SunXi family
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet Draft
+ http://linux-sunxi.org/File:Allwinner_R40_Datasheet_V0.1.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..b3ffe6cf821a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index f44e3acb5c90..aea616759451 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+ "allwinner,sun8i-r40",
NULL,
};
--
2.12.2
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[PATCH v2 08/10] clk: sunxi-ng: support R40 SoC
From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 64088e599404..e6884eafde44 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -140,6 +140,16 @@ config SUN8I_V3S_CCU default MACH_SUN8I depends on MACH_SUN8I || COMPILE_TEST +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 0ec02fe14c50..aa00b641484e 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..0cc1b1ab7c3f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icen...@aosc.xyz> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4, /* M */
[PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU
Allwinner R40 has a clock controlling unit like the ones on other Allwinner SoCs after sun6i, and can also use a CCU-based driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index e9c5a1d9834a..b2ae26428423 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -8,6 +8,7 @@ Required properties : - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-r-ccu" + - "allwinner,sun8i-r40-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 +-
2 files changed, 197 insertions(+), 77 deletions(-)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I || MACH_SUN7I
+ def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "
[PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index b53224473672..3ab9f7849a19 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -22,6 +22,7 @@ Required properties: "allwinner,sun8i-a83t-pinctrl" "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" + "allwinner,sun8i-r40-pinctrl" "allwinner,sun50i-a64-pinctrl" "allwinner,sun50i-a64-r-pinctrl" "allwinner,sun50i-h5-pinctrl" -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 04/10] pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, and enable A10 driver for A20.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig |6 +-
drivers/pinctrl/sunxi/Makefile|1 -
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 -
3 files changed, 1 insertion(+), 1062 deletions(-)
delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 793e6f94fa0b..624d84e6c936 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I
+ def_bool MACH_SUN4I || MACH_SUN7I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
@@ -23,10 +23,6 @@ config PINCTRL_SUN6I_A31_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
-config PINCTRL_SUN7I_A20
- def_bool MACH_SUN7I
- select PINCTRL_SUNXI
-
config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index df4ccd6cd44c..efe1e64ef4f1 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,7 +6,6 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I)+= pinctrl-sun5i.o
obj-$(CONFIG_PINCTRL_SUN6I_A31)+= pinctrl-sun6i-a31.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
-obj-$(CONFIG_PINCTRL_SUN7I_A20)+= pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
deleted file mode 100644
index b6f4c68ffb39..
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-/*
- * Allwinner A20 SoCs pinctrl driver.
- *
- * Copyright (C) 2014 Maxime Ripard
- *
- * Maxime Ripard <maxime.rip...@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include
-#include
-#include
-#include
-#include
-
-#include "pinctrl-sunxi.h"
-
-static const struct sunxi_desc_pin sun7i_a20_pins[] = {
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
- SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
- SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2"), /* TX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
- SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
- SUNXI_FUNCTION(0x4, "uart2"), /* RX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
- SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5)
[PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai <w...@csie.org>
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++
1 file changed, 404 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..20d4705a8206
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,404 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ aliases {
+ };
+
+ chosen {
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x4000 0x8000>;
+ };
+
+
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver
于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
><maxime.rip...@free-electrons.com> 写到:
>> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> >> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
>> >> + {
>> >> + .compatible = "allwinner,sun4i-a10-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN4I_A10
>> >> + },
>> >> + {
>> >> + .compatible = "allwinner,sun7i-a20-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN7I_A20
>> >> + },
>> >> {}
>> >> };
>> >
>> >This means you're going to have two drivers probing for the same
>> >device: this driver, and the old one. This is not ok, and probably
>> >introduces some corner cases.
>>
>> The A20 driver is dropped in the next commit.
>
>Yes, and that is an issue for bisectability. Anyone that will checkout
>between those two commits will have a broken kernel, and that is not
>ok. Any commit should be in a working state.
Squash them together?
>
>Maxime
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[PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
1 file changed, 224 insertions(+), 63 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fb30b86a97ee..159580c04b14 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -24,101 +24,147 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2")),/* RTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
- SUNXI_FUNCTION(0x4, "uart2")),/* CTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2")),/* TX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
- SUNXI_FUNCTION(0x4, "uart2")),/* RX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
- SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
+ SUNXI_FUNCTION(0x3, "
[PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a9d315a1256c..1bfc0d8a55df 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -87,6 +87,9 @@
#define PINCTRL_SUN5I_GR8 BIT(3)
#define PINCTRL_SUN6I_A31 BIT(4)
#define PINCTRL_SUN6I_A31S BIT(5)
+#define PINCTRL_SUN4I_A10 BIT(6)
+#define PINCTRL_SUN7I_A20 BIT(7)
+#define PINCTRL_SUN8I_R40 BIT(8)
struct sunxi_desc_function {
unsigned long variant;
--
2.12.2
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Re: [PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver
于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote: >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout. >> >> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support >> into A10 driver, and add R40 support into it. > >While your commit log is good, the commit title is misleading since >you're not adding it to the A10 driver. You just adding SoC IDs >definitions Is "pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs" OK? > >Maxime -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver
于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> -{ .compatible = "allwinner,sun4i-a10-pinctrl", },
>> +{
>> +.compatible = "allwinner,sun4i-a10-pinctrl",
>> +.data = (void *)PINCTRL_SUN4I_A10
>> +},
>> +{
>> +.compatible = "allwinner,sun7i-a20-pinctrl",
>> +.data = (void *)PINCTRL_SUN7I_A20
>> +},
>> {}
>> };
>
>This means you're going to have two drivers probing for the same
>device: this driver, and the old one. This is not ok, and probably
>introduces some corner cases.
The A20 driver is dropped in the next commit.
>
>Maxime
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[PATCH v2 00/10] Initial Allwinner R40 support
This is the first non-RFC version of this patchset, which added basical support including I2C, UART and MMC to the mainline Linux. The pinctrl driver of A20 is also merged into the one of A10 before R40 support is added into the A10 driver. Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (8): arm: sunxi: add support for R40 SoC pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver pinctrl: sunxi: add A20 support to A10 driver pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version dt-bindings: add compatible string for Allwinner R40 pinctrl pinctrl: sunxi: add support of R40 to A10 pinctrl driver dt-bindings: add compatible string for Allwinner R40 CCU clk: sunxi-ng: support R40 SoC Documentation/arm/sunxi/README |4 + Documentation/devicetree/bindings/arm/sunxi.txt|1 + .../devicetree/bindings/clock/sunxi-ccu.txt|1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt |1 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 161 +++ arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++ arch/arm/mach-sunxi/sunxi.c|1 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ drivers/pinctrl/sunxi/Kconfig |6 +- drivers/pinctrl/sunxi/Makefile |1 - drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 449 ++-- drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 -- drivers/pinctrl/sunxi/pinctrl-sunxi.h |3 + include/dt-bindings/clock/sun8i-r40-ccu.h | 191 include/dt-bindings/reset/sun8i-r40-ccu.h | 129 +++ 19 files changed, 2495 insertions(+), 1146 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
