Re: [PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write
Hi, Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > No functional change. dw_pcie_cfg_read/dw_pcie_cfg_write doesn't do > anything specific to access configuration space. It can be just renamed > to dw_pcie_read/dw_pcie_write and used to read/write data to dbi space. > This is in preparation for added endpoint support to linux kernel. > > Cc: Jingoo Han> Cc: Murali Karicheri > Cc: Joao Pinto > Cc: Stanimir Varbanov > Cc: Pratyush Anand > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pci-dra7xx.c | 16 > drivers/pci/dwc/pci-exynos.c |4 ++-- > drivers/pci/dwc/pci-keystone-dw.c |4 ++-- > drivers/pci/dwc/pcie-designware.c | 12 ++-- > drivers/pci/dwc/pcie-designware.h |4 ++-- > drivers/pci/dwc/pcie-qcom.c |2 +- > drivers/pci/dwc/pcie-spear13xx.c | 24 > 7 files changed, 33 insertions(+), 33 deletions(-) > > diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c > index aeeab74..38b0c9a 100644 > --- a/drivers/pci/dwc/pci-dra7xx.c > +++ b/drivers/pci/dwc/pci-dra7xx.c > @@ -114,22 +114,22 @@ static int dra7xx_pcie_establish_link(struct > dra7xx_pcie *dra7xx) > } > > if (dra7xx->link_gen == 1) { > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > - 4, ); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > + 4, ); > if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCAP, 4, reg); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCAP, 4, reg); > } > > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > - 2, ); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > + 2, ); > if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCTL2, 2, reg); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCTL2, 2, reg); > } > } > > diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c > index c179e7a..e3fbff4 100644 > --- a/drivers/pci/dwc/pci-exynos.c > +++ b/drivers/pci/dwc/pci-exynos.c > @@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, > int where, int size, > int ret; > > exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); > - ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); > + ret = dw_pcie_read(pp->dbi_base + where, size, val); > exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); > return ret; > } > @@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, > int where, int size, > int ret; > > exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); > - ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); > + ret = dw_pcie_write(pp->dbi_base + where, size, val); > exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); > return ret; > } > diff --git a/drivers/pci/dwc/pci-keystone-dw.c > b/drivers/pci/dwc/pci-keystone-dw.c > index 9397c46..4875334 100644 > --- a/drivers/pci/dwc/pci-keystone-dw.c > +++ b/drivers/pci/dwc/pci-keystone-dw.c > @@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct > pci_bus *bus, > > addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); > > - return dw_pcie_cfg_read(addr + where, size, val); > + return dw_pcie_read(addr + where, size, val); > } > > int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, > @@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct > pci_bus *bus, > > addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); > > - return dw_pcie_cfg_write(addr + where, size, val); > + return dw_pcie_write(addr + where, size, val); > } > > /** > diff --git a/drivers/pci/dwc/pcie-designware.c > b/drivers/pci/dwc/pcie-designware.c > index 0b928dc..d0ea310 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -33,7 +33,7 @@ > > static struct pci_ops dw_pcie_ops; > > -int dw_pcie_cfg_read(void __iomem *addr, int size, u32
[PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write
No functional change. dw_pcie_cfg_read/dw_pcie_cfg_write doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read/dw_pcie_write and used to read/write data to dbi space. This is in preparation for added endpoint support to linux kernel. Cc: Jingoo HanCc: Murali Karicheri Cc: Joao Pinto Cc: Stanimir Varbanov Cc: Pratyush Anand Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 16 drivers/pci/dwc/pci-exynos.c |4 ++-- drivers/pci/dwc/pci-keystone-dw.c |4 ++-- drivers/pci/dwc/pcie-designware.c | 12 ++-- drivers/pci/dwc/pcie-designware.h |4 ++-- drivers/pci/dwc/pcie-qcom.c |2 +- drivers/pci/dwc/pcie-spear13xx.c | 24 7 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index aeeab74..38b0c9a 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -114,22 +114,22 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) } if (dra7xx->link_gen == 1) { - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, -4, ); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, +4, ); if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCAP, 4, reg); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCAP, 4, reg); } - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, -2, ); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, +2, ); if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCTL2, 2, reg); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCTL2, 2, reg); } } diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c index c179e7a..e3fbff4 100644 --- a/drivers/pci/dwc/pci-exynos.c +++ b/drivers/pci/dwc/pci-exynos.c @@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, int ret; exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); - ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); + ret = dw_pcie_read(pp->dbi_base + where, size, val); exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); return ret; } @@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, int ret; exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); - ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); + ret = dw_pcie_write(pp->dbi_base + where, size, val); exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); return ret; } diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c index 9397c46..4875334 100644 --- a/drivers/pci/dwc/pci-keystone-dw.c +++ b/drivers/pci/dwc/pci-keystone-dw.c @@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - return dw_pcie_cfg_read(addr + where, size, val); + return dw_pcie_read(addr + where, size, val); } int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, @@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - return dw_pcie_cfg_write(addr + where, size, val); + return dw_pcie_write(addr + where, size, val); } /** diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 0b928dc..d0ea310 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -33,7 +33,7 @@ static struct pci_ops dw_pcie_ops; -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) +int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; @@ -54,7 +54,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size,