Re: [PATCH v4 03/11] drm/hisilicon: Add crtc driver for ADE
On 8 February 2016 at 18:59, Archit Taneja wrote: > > > On 02/06/2016 08:54 AM, Xinliang Liu wrote: >> >> Add crtc funcs and helper funcs for ADE. >> >> v4: None. >> v3: >> - Make ade as the master driver. >> - Use port to connect with encoder. >> - A few cleanup. >> v2: >> - Remove abtraction layer. >> >> Signed-off-by: Xinliang Liu >> --- >> drivers/gpu/drm/hisilicon/kirin/Makefile| 3 +- >> drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 280 +++ >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 458 >> >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 15 + >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + >> 5 files changed, 763 insertions(+), 1 deletion(-) >> create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h >> create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c >> >> diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile >> b/drivers/gpu/drm/hisilicon/kirin/Makefile >> index cb346de47d48..2a61ab006ddb 100644 >> --- a/drivers/gpu/drm/hisilicon/kirin/Makefile >> +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile >> @@ -1,3 +1,4 @@ >> -kirin-drm-y := kirin_drm_drv.o >> +kirin-drm-y := kirin_drm_drv.o \ >> + kirin_drm_ade.o >> >> obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o >> diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h >> b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h >> new file mode 100644 >> index ..78020747abfe >> --- /dev/null >> +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h >> @@ -0,0 +1,280 @@ >> +/* >> + * Copyright (c) 2016 Linaro Limited. >> + * Copyright (c) 2014-2016 Hisilicon Limited. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#ifndef __KIRIN_ADE_REG_H__ >> +#define __KIRIN_ADE_REG_H__ >> + >> +/* >> + * ADE Registers >> + */ >> +#define MASK(x)(BIT(x) - 1) >> + >> +#define ADE_CTRL 0x0004 >> +#define FRM_END_START_OFST 0 >> +#define FRM_END_START_MASK MASK(2) >> +#define ADE_CTRL1 0x008C >> +#define AUTO_CLK_GATE_EN_OFST 0 >> +#define AUTO_CLK_GATE_EN BIT(0) >> +#define ADE_ROT_SRC_CFG0x0010 >> +#define ADE_DISP_SRC_CFG 0x0018 >> +#define ADE_WDMA2_SRC_CFG 0x001C >> +#define ADE_SEC_OVLY_SRC_CFG 0x0020 >> +#define ADE_WDMA3_SRC_CFG 0x0024 >> +#define ADE_OVLY1_TRANS_CFG0x002C >> +#define ADE_EN 0x0100 >> +#define ADE_DISABLE0 >> +#define ADE_ENABLE 1 >> +#define INTR_MASK_CPU(x) (0x0C10 + (x) * 0x4) >> +#define ADE_FRM_DISGARD_CTRL 0x00A4 >> +/* reset and reload regs */ >> +#define ADE_SOFT_RST_SEL(x)(0x0078 + (x) * 0x4) >> +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) >> +#define RDMA_OFST 0 >> +#define CLIP_OFST 15 >> +#define SCL_OFST 21 >> +#define CTRAN_OFST 24 >> +#define OVLY_OFST 37 /* 32+5 */ >> +/* channel regs */ >> +#define RD_CH_PE(x)(0x1000 + (x) * 0x80) >> +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) >> +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) >> +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) >> +#define RD_CH_STRIDE(x)(0x1010 + (x) * 0x80) >> +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) >> +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) >> +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) >> +#define RD_CH_EN(x)(0x1020 + (x) * 0x80) >> +#define RD_CH_STATUS(x)(0x1024 + (x) * 0x80) >> +#define RD_CH_DISP_CTRL0x1404 >> +#define RD_CH_DISP_ADDR0x1408 >> +#define RD_CH_DISP_SIZE0x140C >> +#define RD_CH_DISP_STRIDE 0x1410 >> +#define RD_CH_DISP_SPACE 0x1414 >> +#define RD_CH_DISP_EN 0x142C >> +/* clip regs */ >> +#define ADE_CLIP_DISABLE(x)(0x6800 + (x) * 0x100) >> +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) >> +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) >> +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) >> +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) >> +/* scale regs */ >> +#define ADE_SCL1_MUX_CFG 0x000C >> +#define ADE_SCL2_SRC_CFG 0x0014 >> +#define ADE_SCL3_MUX_CFG 0x0008 >> +#define ADE_SCL_CTRL(x)(0x3000 + (x) * 0x800) >> +#define ADE_SCL_HSP(x) (0x3004
Re: [PATCH v4 03/11] drm/hisilicon: Add crtc driver for ADE
On 02/06/2016 08:54 AM, Xinliang Liu wrote: Add crtc funcs and helper funcs for ADE. v4: None. v3: - Make ade as the master driver. - Use port to connect with encoder. - A few cleanup. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu --- drivers/gpu/drm/hisilicon/kirin/Makefile| 3 +- drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 280 +++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 458 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 15 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + 5 files changed, 763 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index cb346de47d48..2a61ab006ddb 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,3 +1,4 @@ -kirin-drm-y := kirin_drm_drv.o +kirin-drm-y := kirin_drm_drv.o \ + kirin_drm_ade.o obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h new file mode 100644 index ..78020747abfe --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __KIRIN_ADE_REG_H__ +#define __KIRIN_ADE_REG_H__ + +/* + * ADE Registers + */ +#define MASK(x)(BIT(x) - 1) + +#define ADE_CTRL 0x0004 +#define FRM_END_START_OFST 0 +#define FRM_END_START_MASK MASK(2) +#define ADE_CTRL1 0x008C +#define AUTO_CLK_GATE_EN_OFST 0 +#define AUTO_CLK_GATE_EN BIT(0) +#define ADE_ROT_SRC_CFG0x0010 +#define ADE_DISP_SRC_CFG 0x0018 +#define ADE_WDMA2_SRC_CFG 0x001C +#define ADE_SEC_OVLY_SRC_CFG 0x0020 +#define ADE_WDMA3_SRC_CFG 0x0024 +#define ADE_OVLY1_TRANS_CFG0x002C +#define ADE_EN 0x0100 +#define ADE_DISABLE0 +#define ADE_ENABLE 1 +#define INTR_MASK_CPU(x) (0x0C10 + (x) * 0x4) +#define ADE_FRM_DISGARD_CTRL 0x00A4 +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL(x)(0x0078 + (x) * 0x4) +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) +#define RDMA_OFST 0 +#define CLIP_OFST 15 +#define SCL_OFST 21 +#define CTRAN_OFST 24 +#define OVLY_OFST 37 /* 32+5 */ +/* channel regs */ +#define RD_CH_PE(x)(0x1000 + (x) * 0x80) +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x)(0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) +#define RD_CH_EN(x)(0x1020 + (x) * 0x80) +#define RD_CH_STATUS(x)(0x1024 + (x) * 0x80) +#define RD_CH_DISP_CTRL0x1404 +#define RD_CH_DISP_ADDR0x1408 +#define RD_CH_DISP_SIZE0x140C +#define RD_CH_DISP_STRIDE 0x1410 +#define RD_CH_DISP_SPACE 0x1414 +#define RD_CH_DISP_EN 0x142C +/* clip regs */ +#define ADE_CLIP_DISABLE(x)(0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) +/* scale regs */ +#define ADE_SCL1_MUX_CFG 0x000C +#define ADE_SCL2_SRC_CFG 0x0014 +#define ADE_SCL3_MUX_CFG 0x0008 +#define ADE_SCL_CTRL(x)(0x3000 + (x) * 0x800) +#define ADE_SCL_HSP(x) (0x3004 + (x) * 0x800) +#define ADE_SCL_UV_HSP(x) (0x3008 + (x) * 0x800) +#define ADE_SCL_VSP(x) (0x300C + (x) * 0x800) +#define ADE_SCL_UV_VSP(x) (0x3010 + (x) * 0x800) +#define ADE_SCL_ORES(x)(0x3014 + (x) * 0x800) +#define ADE_SCL_IRES(x)(0x3018 + (x) * 0x800) +#define ADE_SCL_START(x)
[PATCH v4 03/11] drm/hisilicon: Add crtc driver for ADE
Add crtc funcs and helper funcs for ADE. v4: None. v3: - Make ade as the master driver. - Use port to connect with encoder. - A few cleanup. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu --- drivers/gpu/drm/hisilicon/kirin/Makefile| 3 +- drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 280 +++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 458 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 15 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + 5 files changed, 763 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index cb346de47d48..2a61ab006ddb 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,3 +1,4 @@ -kirin-drm-y := kirin_drm_drv.o +kirin-drm-y := kirin_drm_drv.o \ + kirin_drm_ade.o obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h new file mode 100644 index ..78020747abfe --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __KIRIN_ADE_REG_H__ +#define __KIRIN_ADE_REG_H__ + +/* + * ADE Registers + */ +#define MASK(x)(BIT(x) - 1) + +#define ADE_CTRL 0x0004 +#define FRM_END_START_OFST 0 +#define FRM_END_START_MASK MASK(2) +#define ADE_CTRL1 0x008C +#define AUTO_CLK_GATE_EN_OFST 0 +#define AUTO_CLK_GATE_EN BIT(0) +#define ADE_ROT_SRC_CFG0x0010 +#define ADE_DISP_SRC_CFG 0x0018 +#define ADE_WDMA2_SRC_CFG 0x001C +#define ADE_SEC_OVLY_SRC_CFG 0x0020 +#define ADE_WDMA3_SRC_CFG 0x0024 +#define ADE_OVLY1_TRANS_CFG0x002C +#define ADE_EN 0x0100 +#define ADE_DISABLE0 +#define ADE_ENABLE 1 +#define INTR_MASK_CPU(x) (0x0C10 + (x) * 0x4) +#define ADE_FRM_DISGARD_CTRL 0x00A4 +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL(x)(0x0078 + (x) * 0x4) +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) +#define RDMA_OFST 0 +#define CLIP_OFST 15 +#define SCL_OFST 21 +#define CTRAN_OFST 24 +#define OVLY_OFST 37 /* 32+5 */ +/* channel regs */ +#define RD_CH_PE(x)(0x1000 + (x) * 0x80) +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x)(0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) +#define RD_CH_EN(x)(0x1020 + (x) * 0x80) +#define RD_CH_STATUS(x)(0x1024 + (x) * 0x80) +#define RD_CH_DISP_CTRL0x1404 +#define RD_CH_DISP_ADDR0x1408 +#define RD_CH_DISP_SIZE0x140C +#define RD_CH_DISP_STRIDE 0x1410 +#define RD_CH_DISP_SPACE 0x1414 +#define RD_CH_DISP_EN 0x142C +/* clip regs */ +#define ADE_CLIP_DISABLE(x)(0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) +/* scale regs */ +#define ADE_SCL1_MUX_CFG 0x000C +#define ADE_SCL2_SRC_CFG 0x0014 +#define ADE_SCL3_MUX_CFG 0x0008 +#define ADE_SCL_CTRL(x)(0x3000 + (x) * 0x800) +#define ADE_SCL_HSP(x) (0x3004 + (x) * 0x800) +#define ADE_SCL_UV_HSP(x) (0x3008 + (x) * 0x800) +#define ADE_SCL_VSP(x) (0x300C + (x) * 0x800) +#define ADE_SCL_UV_VSP(x) (0x3010 + (x) * 0x800) +#define ADE_SCL_ORES(x)(0x3014 + (x) * 0x800) +#define ADE_SCL_IRES(x)(0x3018 + (x) * 0x800) +#define ADE_SCL_START(x) (0x301C + (x) * 0x800) +#define ADE_SCL_ERR(x)
