On 7/22/13 10:17 PM, Christian Ruppert wrote: On Wed, Jul 17, 2013 at
11:39:58PM +0900, Shinya Kuribayashi wrote:
On 7/16/13 8:16 PM, Christian Ruppert wrote: On Sat, Jul 13, 2013 at
02:36:43PM +0900, Shinya Kuribayashi wrote:
Basically, DW I2C core provides a good enough (and quite direct) way
to control tHIGH and tLOW timing specs, *HCNT and *LCNT registers.
But from my experience (with a slightly old version of DW I2C core
around 2005, version 1.06a or so), DW I2C core was apparently lacking
in an appropriate hardware mechanism to meet tHD;STA timing spec. We
then found that we could meet tHD;STA by increasing *HCNT values, so
that's what currently we have in i2c-designware.c I know with that
workaround applied, tHIGH is to be configured with a larger value
than necessary, but we have no choice. For I2C bus systems, we must
meet every timing constraint strictly as required. If DW I2C core
cannot meet tHD;STA without the sacrifice of tHIGH, and I would call
it a hardware bug.
I agree. However, tHD;STA [min] is defined to the same value as tHIGH
[min] for all modes in the I2C specification. Do I understand you
correctly that the SCL_HCNT parameters control at the same time tHIGH
and tHD;STA?
*HCNT value does affect both tHIGH and tHD;STA at the same time.
But we have to make sure that composition of tHIGH is different
from the one of tHD;STA.
For tHIGH
--
DW I2C core is aware of the SCL rising transition (tr) and can
ignore it. It starts counting the HIGH period of the SCL signal
(tHIGH) after the SCL input voltage increases at VIH.
This is described in the data book as an ideal configuration,
and the resulting formula would be:
HCNT + (1+4+3) = IC_CLK * tHIGH ... (a)
please refer to the data book for details about (1+4+3) part.
For tLOW
DW I2C core starts counting the SCL CNTs for the LOW period of
the SCL signal (tLOW) as soon as it pulls the SCL line _without_
_confirming_ the SCL input voltage decreases at VIL.
In order to meet the tLOW timing spec, we need to take into
account the fall time of SCL signal (tf), so the resulting
formula should be:
LCNT + 1 = IC_CLK * (tLOW + tf)
please refer to the data book for details about '+1' part.
For tHD;STA
---
There is no explanation about tHD;STA in the data book. We
only have (my) experimental result; tHD;STA turned out to be
proportional to 'HCNT + 3'. The formula is:
HCNT + 3 = IC_CLK * (tHD;STA + tf) ... (b)
DW I2C core seems to start counting the SCL CNTs for the HIGH
period of the SCL signel (tHD;STA) as soon as it pulls the _SDA_
line without confirming the SDA input voltage decreases at VIL,
so we have to take into account the SDA falling transition (tf)
here.
As can be expected from (a) and (b), if tHD;STA [min] is defined
to the same value as tHIGH [min], we need to have larger HCNT
value than necessary for tHIGH, to meet tHD;STA constraint.
[...]
Hrmmm... This makes my head spin. Do you think the following code
snippet represents an accurate method to calculate the register values?
If you agree I'll prepare a patch based on that for the DW I2C. The
question will be, however, how to obtain the transition times.
Please find my comments below.
/*
*t_f;SDA
* |-|
* _ _ . . .
* \/
* SDA \ /
*\/ t_r;SCLt_f;SCL
* |-||-|
* __
* \ /\
* SCL\ / \
* \_/\___ . . .
*|--| |-| ||
*t_HD;STAt_LOW t_HIGH
*
* ||---| ||
* ( HCNT LCNTHCNT ) * 1/f_SYS
Composition is: HCNT+3 LCNT+1 HCNT+(1+4+3)
The offsets for the HCNT are different in the cases of tHD;STA and
t_HIGH. It's based on my experimental result and we can't know how
DW I2C core actually counts those period, but it can be easily
imagined that for DW I2C core, the way to count t_HD;STA is similar
to the way to count t_LOW; it starts counting CNTs as soon as it
pulls the SCL/SDA line, then waits for given CNTs.
I think your equations and snippet code are based on the assumption
that DW I2C core must be counting the number of CNTs for the HIGH
period of the SCL signal (that's t_HD;STA and t_HIGH) in the same
way, but I don't think so. From my observation and experimental
results, it must be different. We couldn't know what actually is,
though.
*
* HCNT = f_SYS * max(t_HD;STA + t_f;SDA , t_HIGH)
* = f_SYS * (t_HIGH + t_f;SDA) because T_HD;STA == T_HIGH
* LCNT = f_SYS * (t_f;SCL + t_LOW)
* HCNT + LCNT + t_r;SCL = 1/f_SCL = t_SCL
As said before, all t_SCL things should go away. Please forget
about 100kbps, 400kbps, and so on. Bus/clock speed is totally
pointless concept for
