Re: [PATCH] i2c: tegra: match return type of wait_for_completion_timeout
On Sun, Mar 1, 2015 at 11:17 PM, Nicholas Mc Guire wrote: > return type of wait_for_completion_timeout is unsigned long not int. As ret > was only used for wait_for_completion_timeout here it is renamed to time_left > the type changed to unsigned long and references fixed up. > > Signed-off-by: Nicholas Mc Guire Looks good! Reviewed-by: Alexandre Courbot -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] DT: i2c: Deprecate adi,adxl34x compatible string
(CC'ing Dmitry) On Monday 02 March 2015 07:40:49 Wolfram Sang wrote: > On Thu, Feb 26, 2015 at 04:27:49PM +0200, Laurent Pinchart wrote: > > On Monday 26 January 2015 13:09:47 Wolfram Sang wrote: > > If you drop adi,adxl346, checkpatch will start complaining if it > > encounters it in a .dts. > > Boah, this is annoying. That means we need an 346 entry even if it > is not different from 345 (which is fine by me). > >>> > >>> To be clear: you need the entry in the documentation. It can be > >>> omitted from the driver if it's not (yet) used for matching. > >> > >> Well, I don't really like that behaviour, but I don't like > >> i2c/trivial-devices.txt as well, so I'll just apply the patch and live > >> with it :) > > > > What happened to this patch ? > > My idea was that Dmitry takes them both because they are related: > > http://article.gmane.org/gmane.linux.drivers.i2c/21763 I'm fine with that. Dmitry ? -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/4] i2c: mux-pinctrl: Rework to honor disabled child nodes
On 02/27/2015 05:24 AM, Sebastian Hesselbarth wrote:
I2C mux pinctrl driver currently determines the number of sub-busses by
counting available pinctrl-names. Unfortunately, this requires each
incarnation of the devicetree node with different available sub-busses
to be rewritten.
This patch reworks i2c-mux-pinctrl driver to count the number of
available sub-nodes instead. The rework should be compatible to the old
way of probing for sub-busses and additionally allows to disable unused
sub-busses with standard DT property status = "disabled".
This also amends the corresponding devicetree binding documentation to
reflect the new functionality to disable unused sub-nodes. While at it,
also fix two references to binding documentation files that miss an "i2c-"
prefix.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
-For each named state defined in the pinctrl-names property, an I2C child bus
-will be created. I2C child bus numbers are assigned based on the index into
-the pinctrl-names property.
+For each enabled child node an I2C child bus will be created. I2C child bus
+numbers are assigned based on the order of child nodes.
I think that I2C bus numbers are an internal concept for the OS. As
such, we should probably remove any mention re: the bus numbers from the
binding.
-The only exception is that no bus will be created for a state named "idle". If
-such a state is defined, it must be the last entry in pinctrl-names. For
-example:
+There must be a corresponding pinctrl-names entry for each enabled child
+node at the position of the child node's "reg" property. Also, there can be
+an idle pinctrl state defined at the end of possible pinctrl states. If such
+a state is defined, it must be the last entry in pinctrl-names. For example:
What about gaps in the numbering sequence? IIRC, in a situation with 5
nodes with reg 0, 1, 2, 3, 4 but where only the nodes with reg of 1, 3
enabled, we only want 2 entries in pinctrl-names? If so, "at the
position of the child node's "reg" property" isn't correct, since "at
the position" implies there must be gaps in pinctrl-names. "In the same
order as the reg property values for enabled subnodes" might be a better
description.
Perhaps I'm misremembering and you explicitly didn't want to remove
entries from pinctrl-names if child nodes were disabled? If so, then
surely then in the text above, "for each enabled child" should be
replaced with "for each child"?
@@ -68,6 +68,7 @@ Example:
pinctrl-1 = <&state_i2cmux_pta>;
pinctrl-2 = <&state_i2cmux_idle>;
+ /* Enabled child bus 0 */
i2c@0 {
reg = <0>;
#address-cells = <1>;
@@ -79,10 +80,12 @@ Example:
};
};
+ /* Disabled child bus 1 */
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
To make the example cover more cases, perhaps make child node i2c@0
disabled and i2c@1 enabled. Then, the example would show what happens to
pinctrl-names when there are gaps in the reg property numbering space of
enabled children?
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[PATCH 2/2] i2c: jz4780: Add i2c bus controller driver for Ingenic JZ4780
Adds the i2c bus controller driver for the Ingenic JZ4780 SoC.
Signed-off-by: Zubair Lutfullah Kakakhel
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-jz4780.c | 820
3 files changed, 830 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-jz4780.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 22da9c2..50b0c91 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -909,6 +909,15 @@ config I2C_RCAR
This driver can also be built as a module. If so, the module
will be called i2c-rcar.
+config I2C_JZ4780
+ tristate "JZ4780 I2C controller interface support"
+ depends on MACH_JZ4780
+ help
+If you say yes to this option, support will be included for the
+Ingenic JZ4780 I2C controller.
+
+If you don't know what to do here, say N.
+
comment "External I2C/SMBus adapter drivers"
config I2C_DIOLAN_U2C
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3638feb..c08cfdb 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
+obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
obj-$(CONFIG_I2C_MESON)+= i2c-meson.o
obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c
new file mode 100644
index 000..22bcf71
--- /dev/null
+++ b/drivers/i2c/busses/i2c-jz4780.c
@@ -0,0 +1,820 @@
+/*
+ * Ingenic JZ4780 I2C bus driver
+ *
+ * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
+ * Copyright (C) 2015 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define JZ4780_I2C_CTRL0x00
+#define JZ4780_I2C_TAR 0x04
+#define JZ4780_I2C_SAR 0x08
+#define JZ4780_I2C_DC 0x10
+#define JZ4780_I2C_SHCNT 0x14
+#define JZ4780_I2C_SLCNT 0x18
+#define JZ4780_I2C_FHCNT 0x1C
+#define JZ4780_I2C_FLCNT 0x20
+#define JZ4780_I2C_INTST 0x2C
+#define JZ4780_I2C_INTM0x30
+#define JZ4780_I2C_RXTL0x38
+#define JZ4780_I2C_TXTL0x3C
+#define JZ4780_I2C_CINTR 0x40
+#define JZ4780_I2C_CRXUF 0x44
+#define JZ4780_I2C_CRXOF 0x48
+#define JZ4780_I2C_CTXOF 0x4C
+#define JZ4780_I2C_CRXREQ 0x50
+#define JZ4780_I2C_CTXABRT 0x54
+#define JZ4780_I2C_CRXDONE 0x58
+#define JZ4780_I2C_CACT0x5C
+#define JZ4780_I2C_CSTP0x60
+#define JZ4780_I2C_CSTT0x64
+#define JZ4780_I2C_CGC 0x68
+#define JZ4780_I2C_ENB 0x6C
+#define JZ4780_I2C_STA 0x70
+#define JZ4780_I2C_TXABRT 0x80
+#define JZ4780_I2C_DMACR 0x88
+#define JZ4780_I2C_DMATDLR 0x8C
+#define JZ4780_I2C_DMARDLR 0x90
+#define JZ4780_I2C_SDASU 0x94
+#define JZ4780_I2C_ACKGC 0x98
+#define JZ4780_I2C_ENSTA 0x9C
+#define JZ4780_I2C_SDAHD 0xD0
+
+#define JZ4780_I2C_CTRL_STPHLD BIT(7)
+#define JZ4780_I2C_CTRL_SLVDIS BIT(6)
+#define JZ4780_I2C_CTRL_REST BIT(5)
+#define JZ4780_I2C_CTRL_MATP BIT(4)
+#define JZ4780_I2C_CTRL_SATP BIT(3)
+#define JZ4780_I2C_CTRL_SPDF BIT(2)
+#define JZ4780_I2C_CTRL_SPDS BIT(1)
+#define JZ4780_I2C_CTRL_MD BIT(0)
+
+#define JZ4780_I2C_STA_SLVACT BIT(6)
+#define JZ4780_I2C_STA_MSTACT BIT(5)
+#define JZ4780_I2C_STA_RFF BIT(4)
+#define JZ4780_I2C_STA_RFNEBIT(3)
+#define JZ4780_I2C_STA_TFE BIT(2)
+#define JZ4780_I2C_STA_TFNFBIT(1)
+#define JZ4780_I2C_STA_ACT BIT(0)
+
+static const char * const jz4780_i2c_abrt_src[] = {
+ "ABRT_7B_ADDR_NOACK",
+ "ABRT_10ADDR1_NOACK",
+ "ABRT_10ADDR2_NOACK",
+ "ABRT_XDATA_NOACK",
+ "ABRT_GCALL_NOACK",
+ "ABRT_GCALL_READ",
+ "ABRT_HS_ACKD",
+ "SBYTE_ACKDET",
+ "ABRT_HS_NORSTRT",
+ "SBYTE_NORSTRT",
+ "ABRT_10B_RD_NORSTRT",
+ "ABRT_MASTER_DIS",
+
[PATCH 1/2] dt-bindings: i2c: Add dt binding documentation for ingenic jz4780 SoC
Adds DT documentation for the the i2c controller for the JZ4780 SoC
Signed-off-by: Zubair Lutfullah Kakakhel
---
.../devicetree/bindings/i2c/i2c-jz4780.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
new file mode 100644
index 000..8ba2266
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
@@ -0,0 +1,38 @@
+* Ingenic JZ4780 I2C Bus controller
+
+Required properties:
+- compatible: should be "ingenic,jz4780-i2c"
+- reg: Should contain the address & size of the I2C controller registers.
+- interrupts: Should specify the interrupt provided by parent.
+- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
+- clock-frequency: desired I2C bus clock frequency in Hz.
+
+Recommended properties:
+- pinctrl-names: should be "default";
+- pinctrl-0: phandle to pinctrl function
+
+Optional properties:
+- interrupt-parent: Should be the phandle of the interrupt controller that
+ delivers interrupts to the I2C block.
+
+Example SoC file
+
+/ {
+ i2c4: i2c4@0x10054000 {
+ compatible = "ingenic,jz4780-i2c";
+ reg = <0x10054000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <56>;
+
+ clocks = <&cgu JZ4780_CLK_SMB4>;
+ };
+};
+
+Example board file
+
+&i2c4 {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c4_data>;
+}
--
1.9.1
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[PATCH 0/2] i2c: jz4780: Add Ingenic JZ4780 i2c driver
Hi, Here we have two patches that add support for the i2c controller present in the Ingenic JZ4780. Feedback welcome. Thank-you ZubairLK Zubair Lutfullah Kakakhel (2): dt-bindings: i2c: Add dt binding documentation for ingenic jz4780 SoC i2c: jz4780: Add i2c bus controller driver for Ingenic JZ4780 .../devicetree/bindings/i2c/i2c-jz4780.txt | 38 + drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-jz4780.c| 820 + 4 files changed, 868 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-jz4780.txt create mode 100644 drivers/i2c/busses/i2c-jz4780.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/4] ARM: dts: sun8i: Add Reduced Serial Bus controller device node to A23 dtsi
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A23 dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 382ebd137ee4..fd9b4c811a5f 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -600,6 +600,13 @@
#size-cells = <0>;
#gpio-cells = <3>;
+ r_rsb_pins: r_rsb {
+ allwinner,pins = "PL0", "PL1";
+ allwinner,function = "s_rsb";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
r_uart_pins_a: r_uart@0 {
allwinner,pins = "PL2", "PL3";
allwinner,function = "s_uart";
@@ -607,5 +614,19 @@
allwinner,pull = ;
};
};
+
+ r_rsb: i2c@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = ;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <300>;
+ resets = <&apb0_rst 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
--
2.1.4
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[PATCH v2 1/4] i2c: sunxi: Add Reduced Serial Bus (RSB) support
The RSB controller looks like an SMBus controller which only supports byte
and word data transfers. It can also do double-word data transfers, but the
I2C subsystem does not support this, nor have we seen devices using this.
The RSB differs from standard SMBus protocol on several aspects:
- it uses addresses set at runtime to address slaves. Runtime addresses
are sent to slaves using their 12bit hardware addresses. Up to 15
runtime addresses are available.
- it adds a parity bit every 8bits of data and address for read and
write accesses; this replaces the ack bit
- only one read access is required to read a byte (instead of a write
followed by a read access in standard SMBus protocol)
- there's no Ack bit after each read access
This means this bus cannot be used to interface with standard SMBus
devices (known devices supporting this interface are the AXP223, AXP806,
AXP809 PMICs and the AC100 codec/RTC). However the RSB protocol is an
extension of P2WI, which was close enough to SMBus to be integrated into
the I2C subsystem in commit 3e833490fae5 ("i2c: sunxi: add P2WI (Push/Pull
2 Wire Interface) controller support").
Signed-off-by: Chen-Yu Tsai
---
drivers/i2c/busses/Kconfig | 12 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-sunxi-rsb.c | 458 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-sunxi-rsb.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 22da9c2ffa22..cf9337877181 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -840,6 +840,18 @@ config I2C_SUN6I_P2WI
This interface is used to connect to specific PMIC devices (like the
AXP221).
+config I2C_SUNXI_RSB
+ tristate "Allwinner Reduced Serial Bus controller"
+ depends on RESET_CONTROLLER
+ depends on MACH_SUN8I || MACH_SUN9I || COMPILE_TEST
+ help
+ If you say yes to this option, support will be included for the
+ Reduced Serial Bus controller embedded in some sunxi SOCs.
+ The RSB looks like an SMBus controller (which supports only byte
+ accesses), but requires setting runtime addresses for slave devices.
+ This interface is used to connect to specific PMIC devices (like the
+ AXP223) or peripherals (like the AC100).
+
config I2C_TEGRA
tristate "NVIDIA Tegra internal I2C controller"
depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3638feb6677e..f95d50315003 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_I2C_SIRF)+= i2c-sirf.o
obj-$(CONFIG_I2C_ST) += i2c-st.o
obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
+obj-$(CONFIG_I2C_SUNXI_RSB)+= i2c-sunxi-rsb.o
obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o
obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o
obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
diff --git a/drivers/i2c/busses/i2c-sunxi-rsb.c
b/drivers/i2c/busses/i2c-sunxi-rsb.c
new file mode 100644
index ..7e9be3e14b8a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi-rsb.c
@@ -0,0 +1,458 @@
+/*
+ * RSB (Reduced Serial Bus) driver.
+ *
+ * Author: Chen-Yu Tsai
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * The RSB controller looks like an SMBus controller which only supports
+ * byte and word data transfers. But, it differs from standard SMBus
+ * protocol on several aspects:
+ * - it uses addresses set at runtime to address slaves. Runtime addresses
+ * are sent to slaves using their 12bit hardware addresses. Up to 15
+ * runtime addresses are available.
+ * - it adds a parity bit every 8bits of data and address for read and
+ * write accesses; this replaces the ack bit
+ * - only one read access is required to read a byte (instead of a write
+ * followed by a read access in standard SMBus protocol)
+ * - there's no Ack bit after each read access
+ *
+ * This means this bus cannot be used to interface with standard SMBus
+ * devices. Devices known to support this interface include the AXP223,
+ * AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers.
+ *
+ * A description of the operation and wire protocol can be found in the
+ * RSB section of Allwinner's A80 user manual, which can be found at
+ *
+ * https://github.com/allwinner-zh/documents/tree/master/A80
+ *
+ * This document is officially released by Allwinner.
+ *
+ * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+/* RSB registers */
+#define RSB_CTRL 0x0 /* Global control */
+#define RSB_C
[PATCH v2 4/4] ARM: dts: sun8i: ippo-q8h-v5: Enable Reduced Serial Bus controller
The Reduced Serial Bus controller is used to talk to the onboard PMIC.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 4cb25f8267c8..31882e6e7a38 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -125,6 +125,10 @@
};
};
+&r_rsb {
+ status = "okay";
+};
+
&r_uart {
pinctrl-names = "default";
pinctrl-0 = <&r_uart_pins_a>;
--
2.1.4
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[PATCH v2 2/4] i2c: sunxi: Add Reduced Serial Bus (RSB) DT bindings documentation
Reduced Serial Bus (RSB) is an SMBus like bus used to communicate
with some PMICs (like the AXP223) or other peripherals.
The RSB DT bindings are pretty much the same as the one defined for
the marvell's mv64xxx controller, with the additional RSB specific
"allwinner,rsb-hw-addr" property for slave device nodes.
There are 2 types of addresses for RSB devices, a hardware address
and a runtime (software) configurable address. The former is only
used when configuring the latter. All read/write accesses use the
runtime address.
It would seem straightforward to use the hardware address in the
DT bindings as the slave's address. However this will not work as
the hardware address is 12 bits wide, and at least 1 device, the
AC100 audio codec, has the highest bit set. This address would be
incompatible with I2C (7 or 10 bit addresses) and likely rejected.
Hence this binding uses statically allocated (by the author of the
DT) runtime addresses for the slave's "reg" property. The hardware
address is put in a separete named property. When writing a new DT,
the author must take care to not have multiple slave devices use
the same address. It is recommended to follow whatever conventions
the hardware vendor uses.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/i2c/i2c-sunxi-rsb.txt | 54 ++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi-rsb.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi-rsb.txt
b/Documentation/devicetree/bindings/i2c/i2c-sunxi-rsb.txt
new file mode 100644
index ..9b1f2dd2e17a
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi-rsb.txt
@@ -0,0 +1,54 @@
+
+* Allwinner RSB (Reduced Serial Bus) controller
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device.
+ - compatible : Should be "allwinner,sun8i-a23-rsb".
+ - interrupts : The interrupt line connected to the RSB peripheral.
+ - clocks : The gate clk connected to the RSB peripheral.
+ - resets : The reset line connected to the RSB peripheral.
+ - #address-cells : always 1 (for RSB runtime addresses)
+ - #size-cells : always 0
+
+Optional properties :
+
+ - clock-frequency : Desired RSB bus clock frequency in Hz. If not set
+the default frequency is 100kHz. Maximum is 20MHz.
+
+An RSB device node may contain up to 15 child nodes each encoding an RSB
+slave device.
+
+Slave device properties:
+ Required properties:
+ - reg : The runtime address used to access the device.
+ - allwinner,rsb-hw-addr : The RSB hardware address for the device. This
+is only used when configuring the runtime
+address of the device.
+
+ Valid runtime addresses - There are only 15 valid runtime addresses:
+
+ 0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b,
+ 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff
+
+
+Example:
+
+ rsb@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <0 39 4>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <300>;
+ resets = <&apb0_rst 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axp223: pmic@2d {
+ compatible = "x-powers,axp223", "x-powers,axp221";
+ reg = <0x2d>;
+ allwinner,rsb-hw-addr = <0x3e3>;
+
+ /* ... */
+ };
+ };
--
2.1.4
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[PATCH v2 0/4] i2c: sunxi: Add Reduced Serial Bus (RSB) support
Hi everyone, This is v2 of my Allwinner Reduced Serial Bus series. v2 addresses comments raised by Arnd: - #address-cells and #size-cells added to DT bindings - DT bindings commit message expanded to include explanation of hardware/runtime addresses and why the runtime address is used for the slave devices' "reg" property. This series adds support for the Reduced Serial Bus (RSB) controller found on newer Allwinner SoCs, such as the A23 or A80. The RSB is used to communicate with companion ICs, notably the bundled PMIC. RSB is an improvement over P2WI that was found on the A31 SoC. The main new feature is support for multiple slave devices on the same bus, using addresses that are configured at runtime. The slave devices also have a hardware address, which is only used when setting the runtime address. Like the P2WI, the RSB is an SMBus like interface, supporting byte, word and double-word transfers only. However, the wire protocol is different so only RSB compatible devices can be used. This class currently consists of the AXP223, AXP806, AXP809 PMICs, and the AC100 audio codec, all from X-Powers. Following the P2WI driver, we hope this driver can be integrated into the I2C subsystem as well. Patch 1 adds the driver supporting RSB. Patch 2 documents the device tree bindings for the driver. Patch 3 adds a device node for RSB to the A23 dtsi. Patch 4 enables the RSB for the only supported A23 device. Only the A23 is enabled at the moment. The A80 uses the same IP block with no differences, but the related clock/reset/pinctrl drivers are still WIP. Regards, ChenYu Chen-Yu Tsai (4): i2c: sunxi: Add Reduced Serial Bus (RSB) support i2c: sunxi: Add Reduced Serial Bus (RSB) DT bindings documentation ARM: dts: sun8i: Add Reduced Serial Bus controller device node to A23 dtsi ARM: dts: sun8i: ippo-q8h-v5: Enable Reduced Serial Bus controller .../devicetree/bindings/i2c/i2c-sunxi-rsb.txt | 54 +++ arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts| 4 + arch/arm/boot/dts/sun8i-a23.dtsi | 21 + drivers/i2c/busses/Kconfig | 12 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-sunxi-rsb.c | 458 + 6 files changed, 550 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi-rsb.txt create mode 100644 drivers/i2c/busses/i2c-sunxi-rsb.c -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
