Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
On 17.07.2015 17:08, Wolfram Sang wrote:
+
+ eeprom@42 {
+ compatible = linux,slave-24c02;
+ //FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42
+ reg = 0xc042;
I used it in this way:
reg = (I2C_OWN_SLAVE_ADDRESS | 0x42);
+ };
};
/* Expansion GEN2_I2C_* */
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Re: [RFC 0/9] i2c: slave: improve i2c client address spaces and their DT support
Hello Wolfram, On 17.07.2015 17:08, Wolfram Sang wrote: As promised here is my RFC to improve address spaces for I2C. This should give i2c seperate address spaces for standard clients, 10 bit clients, and our own slave clients. So, you can now have a 7 bit slave at 0x50 and a 10 bit slave at 0x050. Or, you can have a slave driver listening at some address and at the same time have a client driver talking to this address. Note that this is only the core support for that separation, I am still not sure if there is hardware being able talking to its own slave address, but we will see. This RFC and while I did some quick tests, it is not thoroughly tested. But I wanted to push it out before I leave the computer for the weekend. It still shows what path I chose to solve the problem. So, comments on that and further testing are more than welcome! BTW Andrey, I did not modify your patch and couldn't get the i2c-slave-eeprom driver to work with my Jetson TK1. Does this work for you? Thanks, Wolfram Thanks for the patches. Slave mode works for me. The series looks good. Only hardcoded values in patch 4 confuse me a little. -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
Hi Wolfram,
Thank you for the patch.
On Friday 17 July 2015 16:08:29 Wolfram Sang wrote:
Not-Signed-off-by: Wolfram Sang w...@the-dreams.de
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index
bd43ed6d6ec7c0..4d5f2a4c4da1ce 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1,5 +1,6 @@
/dts-v1/;
+#include dt-bindings/i2c/i2c.h
#include dt-bindings/input/input.h
#include tegra124.dtsi
@@ -1390,6 +1391,12 @@
reg = 0x56;
pagesize = 8;
};
+
+ eeprom@42 {
+ compatible = linux,slave-24c02;
+ //FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42
+ reg = 0xc042;
The node name doesn't match the reg property anymore. Isn't that considered as
a problem ?
+ };
};
/* Expansion GEN2_I2C_* */
--
Regards,
Laurent Pinchart
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Re: [PATCH-v4 00/11] i2c: pxa: Fixes, cleanup and support for pxa910 family
On Monday 20 July 2015 12:36 PM, Vaibhav Hiremath wrote: On Saturday 18 July 2015 01:19 AM, Robert Jarzmik wrote: Vaibhav Hiremath vaibhav.hirem...@linaro.org writes: So, I applied patches 1-6 to for-next to make some progress. The others need more thought because of the bindings which shall be discussed replying to the patches in question. Thanks for the updated work with lots of proper references. OK, Thanks and no issues. Lets discuss more on the bindings. I made a simple try on my reference platform with the whole patchset. It oopses on a NULL dereference. The stack is in [1]. I think it boils down to : - i2c_pxa_do_sclk_adj() - reg_ilcr = readl(_ILCR(i2c)); I also think the faulty patch is : - i2c: pxa: Add ILCR (tLow tHigh) configuration support My case, an I2C master case, I'd like you to find the issue and fix it. Which is this reference platform? Can you share few details - - reference Platform? - DT file if you could - Boot log (if you could) I am using pxa1928 based platform, and I do not see any issues. Having said that, I see issues in the patch for non PXA910 platform, where i2c_pxa_do_sclk_adj() will be called unconditionally and obviously reg_ilcr and reg_wcr are not set. I will fix this and send the patch. Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH-v4 00/11] i2c: pxa: Fixes, cleanup and support for pxa910 family
On Saturday 18 July 2015 01:19 AM, Robert Jarzmik wrote: Vaibhav Hiremath vaibhav.hirem...@linaro.org writes: So, I applied patches 1-6 to for-next to make some progress. The others need more thought because of the bindings which shall be discussed replying to the patches in question. Thanks for the updated work with lots of proper references. OK, Thanks and no issues. Lets discuss more on the bindings. I made a simple try on my reference platform with the whole patchset. It oopses on a NULL dereference. The stack is in [1]. I think it boils down to : - i2c_pxa_do_sclk_adj() - reg_ilcr = readl(_ILCR(i2c)); I also think the faulty patch is : - i2c: pxa: Add ILCR (tLow tHigh) configuration support My case, an I2C master case, I'd like you to find the issue and fix it. Which is this reference platform? Can you share few details - - reference Platform? - DT file if you could - Boot log (if you could) I am using pxa1928 based platform, and I do not see any issues. Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH-v4 00/11] i2c: pxa: Fixes, cleanup and support for pxa910 family
On Monday 20 July 2015 12:39 PM, Vaibhav Hiremath wrote:
On Monday 20 July 2015 12:36 PM, Vaibhav Hiremath wrote:
On Saturday 18 July 2015 01:19 AM, Robert Jarzmik wrote:
Vaibhav Hiremath vaibhav.hirem...@linaro.org writes:
So, I applied patches 1-6 to for-next to make some progress.
The others need more thought because of the bindings which shall be
discussed replying to the patches in question.
Thanks for the updated work with lots of proper references.
OK, Thanks and no issues.
Lets discuss more on the bindings.
I made a simple try on my reference platform with the whole patchset.
It oopses on a NULL dereference.
The stack is in [1].
I think it boils down to :
- i2c_pxa_do_sclk_adj()
- reg_ilcr = readl(_ILCR(i2c));
I also think the faulty patch is :
- i2c: pxa: Add ILCR (tLow tHigh) configuration support
My case, an I2C master case, I'd like you to find the issue and fix it.
Which is this reference platform?
Can you share few details -
- reference Platform?
- DT file if you could
- Boot log (if you could)
I am using pxa1928 based platform, and I do not see any issues.
Having said that,
I see issues in the patch for non PXA910 platform, where
i2c_pxa_do_sclk_adj() will be called unconditionally and obviously
reg_ilcr and reg_wcr are not set.
I will fix this and send the patch.
This should fix the issue -
hvaibhav@hvaibhav-ThinkPad-T440p:~/projects/mainline/linux$ git diff
drivers/i2c/busses/i2c-pxa.c
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index e0aa087..9e372fc 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -590,6 +590,9 @@ static void i2c_pxa_do_sclk_adj(struct pxa_i2c *i2c)
{
unsigned int reg_ilcr;
+ if (!i2c-reg_ilcr)
+ return;
+
reg_ilcr = readl(_ILCR(i2c));
/* For standard/fast mode tlow and thigh counters are same */
If you are ok, I will re-spin the patch and submit.
Thanks,
Vaibhav
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Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
+
+ eeprom@42 {
+ compatible = linux,slave-24c02;
+ //FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42
+ reg = 0xc042;
The node name doesn't match the reg property anymore. Isn't that considered
as
a problem ?
Hmm, true. So far, Rob (CCed) was fine with this approach:
http://www.spinics.net/lists/linux-tegra/msg22760.html
@Rob: If we introduce flag bits in the MSBs of an I2C address, the reg
property is different from the node name. Is this a problem?
Thanks,
Wolfram
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Re: [RFC 0/9] i2c: slave: improve i2c client address spaces and their DT support
Thanks for the patches. Slave mode works for me. Okay, need to have a closer look this week. I combined two I2C busses on my Jetson TK1. While the initialization of the slave works fine, reading from the slave via the second I2C controller does not work (yet). The series looks good. Great. I'd be happy for Acked-by or Tested-by tags if possible. Only hardcoded values in patch 4 confuse me a little. Yes, they will most likely be replaced by defines in the next series. We will need them in another place, too. However, since userspace relies on them, they should never be changed. signature.asc Description: Digital signature
Re: [PATCH V4 2/7] qup: i2c: factor out common code for reuse
Hi Sricharan,
On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
- unsigned long left;
- int ret;
+ int ret = 0;
- qup-msg = msg;
- qup-pos = 0;
+ /*
+ * The QUP block will issue a NACK and STOP on the bus when
reaching
+ * the end of the read, the length of the read is specified as
one byte
+ * which limits the possible read to 256 (QUP_READ_LIMIT)
bytes.
+ */
+ if (msg-len QUP_READ_LIMIT) {
+ dev_err(qup-dev, HW not capable of reads over %d bytes\n,
+ QUP_READ_LIMIT);
+ return -EINVAL;
+ }
This should be removed. Please see qup_i2c_quirks.
Regards,
Ivan
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Re: [RFC 0/9] i2c: slave: improve i2c client address spaces and their DT support
On 17.07.2015 17:08, Wolfram Sang wrote: As promised here is my RFC to improve address spaces for I2C. This should give i2c seperate address spaces for standard clients, 10 bit clients, and our own slave clients. So, you can now have a 7 bit slave at 0x50 and a 10 bit slave at 0x050. Or, you can have a slave driver listening at some address and at the same time have a client driver talking to this address. Note that this is only the core support for that separation, I am still not sure if there is hardware being able talking to its own slave address, but we will see. This RFC and while I did some quick tests, it is not thoroughly tested. But I wanted to push it out before I leave the computer for the weekend. It still shows what path I chose to solve the problem. So, comments on that and further testing are more than welcome! BTW Andrey, I did not modify your patch and couldn't get the i2c-slave-eeprom driver to work with my Jetson TK1. Does this work for you? Thanks, Wolfram Andrey Danin (1): i2c: tegra: implement slave mode Wolfram Sang (8): dt-bindings: add header for generic I2C flags in bindings i2c: add a flag to mark clients as slaves i2c: apply address offset for slaves, too i2c: rename address check functions i2c: make address check indpendent from client struct i2c: apply DT flags when probing i2c: take address space into account when checking for used addresses dts: tegra: WIP: hack dts to test new dt flags for i2c arch/arm/boot/dts/tegra124-jetson-tk1.dts | 7 ++ drivers/i2c/busses/Kconfig| 1 + drivers/i2c/busses/i2c-tegra.c| 119 ++ drivers/i2c/i2c-core.c| 69 +++-- include/dt-bindings/i2c/i2c.h | 18 + include/linux/i2c.h | 9 ++- 6 files changed, 197 insertions(+), 26 deletions(-) create mode 100644 include/dt-bindings/i2c/i2c.h The series is Tested-by: Andrey Danin danind...@mail.ru -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
+//FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42 +reg = 0xc042; I used it in this way: reg = (I2C_OWN_SLAVE_ADDRESS | 0x42); Ah, nice, it was that easy :) Thanks! signature.asc Description: Digital signature
Re: [PATCH V4 3/7] i2c: qup: Add V2 tags support
Hi Sricharan,
On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write. This new tagging version
supports bam dma and transfers of more than 256 bytes without 'stop'
in between. Adding the support for the same.
IIRC, more than 256 bytes in message is supported only in BAM(DMA)
mode, if this is true, please be more explicit in commit message.
You haven't tried to read more than 256 bytes with this
patch, right? See qup_i2c_quirks ;-)
struct qup_i2c_dev {
struct device*dev;
void __iomem*base;
@@ -117,6 +138,7 @@ struct qup_i2c_dev {
int in_blk_sz;
unsigned longone_byte_t;
+ struct qup_i2c_blockblk;
struct i2c_msg*msg;
/* Current posion in user message buffer */
@@ -126,6 +148,14 @@ struct qup_i2c_dev {
/* QUP core errors */
u32 qup_err;
+ int use_v2_tags;
+
+ int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
+ struct i2c_msg *msg);
+
+ int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
+ struct i2c_msg *msg);
+
Do we really need additional level of indirection?
We have separate struct i2c_algorithm, then we have common
qup_i2c_read/write methods and then we have different
read/write sub functions. I don't think 3-4 lines code reuse
deserve increased complexity.
snip
+static void qup_i2c_get_blk_data(struct qup_i2c_dev *qup,
+ struct i2c_msg *msg)
+{
This is more like set_blk_metadata. Second argument could fit line above.
+ memset(qup-blk, 0, sizeof(qup-blk));
+
+ if (!qup-use_v2_tags) {
+ if (!(msg-flags I2C_M_RD))
+ qup-blk.tx_tag_len = 1;
+ return;
+ }
+
+ qup-blk.data_len = msg-len;
+ qup-blk.count = (msg-len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
+
+ /* 4 bytes for first block and 2 writes for rest */
+ qup-blk.tx_tag_len = 4 + (qup-blk.count - 1) * 2;
+
+ /* There are 2 tag bytes that are read in to fifo for every block */
+ if (msg-flags I2C_M_RD)
+ qup-blk.rx_tag_len = qup-blk.count * 2;
+}
+
snip
+static int qup_i2c_get_tags(u8 *tags, struct qup_i2c_dev *qup,
+ struct i2c_msg *msg)
+{
This is more like set_tags.
+ u16 addr = (msg-addr 1) | ((msg-flags I2C_M_RD) == I2C_M_RD);
+ int len = 0;
+ int data_len;
+
+ if (qup-blk.pos == 0) {
+ tags[len++] = QUP_TAG_V2_START;
+ tags[len++] = addr 0xff;
+
+ if (msg-flags I2C_M_TEN)
+ tags[len++] = addr 8;
+ }
+
+ /* Send _STOP commands for the last block */
+ if (qup-blk.pos == (qup-blk.count - 1)) {
+ if (msg-flags I2C_M_RD)
+ tags[len++] = QUP_TAG_V2_DATARD_STOP;
+ else
+ tags[len++] = QUP_TAG_V2_DATAWR_STOP;
+ } else {
+ if (msg-flags I2C_M_RD)
+ tags[len++] = QUP_TAG_V2_DATARD;
+ else
+ tags[len++] = QUP_TAG_V2_DATAWR;
+ }
+
+ data_len = qup_i2c_get_data_len(qup);
+
+ /* 0 implies 256 bytes */
+ if (data_len == QUP_READ_LIMIT)
+ tags[len++] = 0;
+ else
+ tags[len++] = data_len;
+
+ return len;
+}
+
Regards,
Ivan
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Re: [PATCH v2 1/4] i2c: tegra: implement slave mode
On Fri, Apr 03, 2015 at 09:46:26PM +0200, Wolfram Sang wrote:
+static void tegra_i2c_slave_write(struct tegra_i2c_dev *i2c_dev, u32 val)
+{
+ i2c_writel(i2c_dev, val, I2C_SL_RCVD);
+
+ /*
+* TODO: A correct fix needs to be found for this.
+*
+* We experience less incomplete messages with this delay than without
+* it, but we don't know why. Help is appreciated.
+*/
Uh oh. So I assume this is another reason for staging?
I think we can live with this upstream, no need for staging.
+ if (!i2c_dev-slave || !i2c_dev-slave-slave_cb)
+ return -EINVAL;
The core checks for slave_cb being valid.
+ i2c_slave_event(i2c_dev-slave, I2C_SLAVE_STOP, dummy);
You could use value here, too, or?
+ if (!tegra_i2c_slave_isr(irq, i2c_dev))
+ return IRQ_HANDLED;
Minor nit: I'd prefer == 0 here, since it reads if not slave_isr return
handled.
+ if (slave-addr 0x7F)
+ addr2 = (slave-addr 7) | I2C_SL_ADDR2_TEN_BIT_MODE;
Nope. There are 10 bit encodings of addresses 0x000-0x07f, too. So, you
need to check for the flag (slave-flags I2C_CLIENT_TEN).
If you'd fix up these and resend, I'll happily include this patch for 4.3
already.
Thanks,
Wolfram
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Re: [PATCH V4 4/7] i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bit
Hi,
On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
snip
#define ONE_BYTE 0x1
+#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
struct qup_i2c_block {
int count;
@@ -121,6 +122,7 @@ struct qup_i2c_block {
int rx_tag_len;
int data_len;
u8 tags[6];
+ int config_run;
This is not directly related to block control logic, right?
Could it made part of qup_i2c_dev structure?
};
struct qup_i2c_dev {
@@ -152,6 +154,10 @@ struct qup_i2c_dev {
int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
struct i2c_msg *msg);
+ /* Current i2c_msg in i2c_msgs */
+ int cmsg;
+ /* total num of i2c_msgs */
+ int num;
I think it will be simpler with just bool is_last evaluated in main xfer loop.
snip
@@ -374,6 +383,9 @@ static void qup_i2c_get_blk_data(struct qup_i2c_dev *qup,
/* There are 2 tag bytes that are read in to fifo for every block */
if (msg-flags I2C_M_RD)
qup-blk.rx_tag_len = qup-blk.count * 2;
+
+ if (qup-cmsg)
+ qup-blk.config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
This could be moved to qup_i2c_xfer_v2() to avoid repeatedly setting it.
}
Regards,
Ivan
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Re: [PATCH V4 5/7] i2c: qup: Add bam dma capabilities
Hi Sricharan,
On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
QUP cores can be attached to a BAM module, which acts as a dma engine for the
QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data
is written to the output FIFO and the BAM producer pipe received data is read
from the input FIFO.
With BAM capabilities, qup-i2c core can transfer more than 256 bytes, without
a
'stop' which is not possible otherwise.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
drivers/i2c/busses/i2c-qup.c | 431
+--
1 file changed, 415 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index c0757d9..810b021 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -24,6 +24,11 @@
#include linux/of.h
#include linux/platform_device.h
#include linux/pm_runtime.h
+#include linux/dma-mapping.h
+#include linux/scatterlist.h
+#include linux/atomic.h
+#include linux/dmaengine.h
+#include linux/dmapool.h
Keep includes sorted alphabetically.
snip
+#define MX_TX_RX_LEN SZ_64K
+#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
+
+/* Max timeout in ms for 32k bytes */
+#define TOUT_MAX 300
+
struct qup_i2c_block {
int count;
int pos;
@@ -125,6 +143,23 @@ struct qup_i2c_block {
int config_run;
};
+struct qup_i2c_tag {
+ u8 *start;
+ dma_addr_t addr;
+};
+
+struct qup_i2c_bam_rx {
+ struct qup_i2c_tag scratch_tag;
+ struct dma_chan *dma_rx;
+ struct scatterlist *sg_rx;
+};
+
+struct qup_i2c_bam_tx {
+ struct qup_i2c_tag footer_tag;
+ struct dma_chan *dma_tx;
+ struct scatterlist *sg_tx;
+};
+
The only difference between above 2 structures is name of the fields.
Please, just define one struct qup_i2c_bam and instantiate it twice.
struct qup_i2c_dev {
struct device*dev;
void __iomem*base;
@@ -154,14 +189,20 @@ struct qup_i2c_dev {
int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
struct i2c_msg *msg);
+ int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
+ struct i2c_msg *msg);
+
/* Current i2c_msg in i2c_msgs */
int cmsg;
/* total num of i2c_msgs */
int num;
- int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
- struct i2c_msg *msg);
-
+ /* dma parameters */
+ boolis_dma;
+ struct dma_pool *dpool;
+ struct qup_i2c_tag start_tag;
+ struct qup_i2c_bam_rx brx;
+ struct qup_i2c_bam_tx btx;
struct completionxfer;
};
@@ -238,6 +279,14 @@ static int qup_i2c_poll_state(struct qup_i2c_dev *qup,
u32 req_state)
return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
}
+static void qup_i2c_flush(struct qup_i2c_dev *qup)
+{
+ u32 val = readl(qup-base + QUP_STATE);
+
+ val |= QUP_I2C_FLUSH;
+ writel(val, qup-base + QUP_STATE);
+}
+
Used in only one place.
snip
+static void qup_i2c_bam_cb(void *data)
+{
+ struct qup_i2c_dev *qup = data;
+
+ complete(qup-xfer);
+}
+
+void qup_sg_set_buf(struct scatterlist *sg, void *buf, struct qup_i2c_tag
*tg,
+ unsigned int buflen, struct
qup_i2c_dev *qup,
+ int map, int dir)
+{
+ sg_set_buf(sg, buf, buflen);
+ dma_map_sg(qup-dev, sg, 1, dir);
+
+ if (!map)
+ sg_dma_address(sg) = tg-addr + ((u8 *)buf - tg-start);
Changing DMA address that we just mapped?
+}
+
+static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
+{
+ if (qup-btx.dma_tx)
+ dma_release_channel(qup-btx.dma_tx);
+ if (qup-brx.dma_rx)
+ dma_release_channel(qup-brx.dma_rx);
+ qup-btx.dma_tx = NULL;
+ qup-brx.dma_rx = NULL;
+}
+
+static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
+{
+ if (!qup-btx.dma_tx) {
+ qup-btx.dma_tx = dma_request_slave_channel(qup-dev, tx);
Please use dma_request_slave_channel_reason() and let deferred probe work.
+ if (!qup-btx.dma_tx) {
+ dev_err(qup-dev, \n tx channel not available);
+ return -ENODEV;
+ }
+ }
+
+ if (!qup-brx.dma_rx) {
+ qup-brx.dma_rx = dma_request_slave_channel(qup-dev, rx);
+ if (!qup-brx.dma_rx) {
+ dev_err(qup-dev, \n rx channel not available);
+ qup_i2c_rel_dma(qup);
+ return -ENODEV;
+ }
+ }
+ return 0;
+}
+
+static int bam_do_xfer(struct qup_i2c_dev *qup, struct
Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
On Mon, Jul 20, 2015 at 3:45 AM, Wolfram Sang w...@the-dreams.de wrote:
+
+ eeprom@42 {
+ compatible = linux,slave-24c02;
+ //FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42
+ reg = 0xc042;
The node name doesn't match the reg property anymore. Isn't that considered
as
a problem ?
Hmm, true. So far, Rob (CCed) was fine with this approach:
http://www.spinics.net/lists/linux-tegra/msg22760.html
@Rob: If we introduce flag bits in the MSBs of an I2C address, the reg
property is different from the node name. Is this a problem?
No, I don't it is a problem.
Rob
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Re: [PATCH v3 4/4] dt: paz00: define nvec as child of i2c bus
On 07/20/2015 02:35 PM, Andrey Danin wrote:
NVEC driver was reimplemented to use tegra i2c. Use common i2c bindings
for NVEC node.
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts/tegra20-paz00.dts
+ nvec: nvec@45 {
+ compatible = nvidia,nvec-slave;
+ reg = 0x45;
I think you need to or in I2C_OWN_SLAVE_ADDRESS from
dt-bindings/i2c/i2c.h here?
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Re: [RFC 0/9] i2c: slave: improve i2c client address spaces and their DT support
On 07/17/2015 08:08 AM, Wolfram Sang wrote: As promised here is my RFC to improve address spaces for I2C. This should give i2c seperate address spaces for standard clients, 10 bit clients, and our own slave clients. So, you can now have a 7 bit slave at 0x50 and a 10 bit slave at 0x050. Or, you can have a slave driver listening at some address and at the same time have a client driver talking to this address. Note that this is only the core support for that separation, I am still not sure if there is hardware being able talking to its own slave address, but we will see. This RFC and while I did some quick tests, it is not thoroughly tested. But I wanted to push it out before I leave the computer for the weekend. It still shows what path I chose to solve the problem. So, comments on that and further testing are more than welcome! BTW Andrey, I did not modify your patch and couldn't get the i2c-slave-eeprom driver to work with my Jetson TK1. Does this work for you? This approach makes sense to me. I'd expect patch 2/9 dt-bindings: add header for generic I2C flags in bindings to document the flags (or at least mention their existence, and point at the new header file) in the core I2C bindings document. Please consider the series, Acked-by: Stephen Warren swar...@nvidia.com (ack rather than review since I didn't review patch 1, and mostly concentrated on reviewing the concepts of how slaves were represented rather than the coding details). -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] staging/nvec: reimplement on top of tegra i2c driver
On 07/20/2015 02:35 PM, Andrey Danin wrote: Remove i2c controller related code and use tegra i2c driver in slave mode. Update nvec documentation. diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt I would expect this patch to add a new binding file nvidia,nvec-slave.txt so that the filename continues to match the compatible value it documents. This patch introduces a new binding for the NVEC slave as opposed to modifying the existing binding. +- compatible : should be nvidia,nvec-slave. +- reg: the i2c address of the slave controller I think the I2C address to respond to would be clearer? You might also mention that this needs to include flags from dt-bindings/i2c/ic2.h. -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 9/9] dts: tegra: WIP: hack dts to test new dt flags for i2c
On 07/20/2015 10:10 AM, Rob Herring wrote:
On Mon, Jul 20, 2015 at 3:45 AM, Wolfram Sang w...@the-dreams.de wrote:
+
+ eeprom@42 {
+ compatible = linux,slave-24c02;
+ //FIXME: Should be I2C_OWN_SLAVE_ADDRESS | 0x42
+ reg = 0xc042;
The node name doesn't match the reg property anymore. Isn't that considered as
a problem ?
Hmm, true. So far, Rob (CCed) was fine with this approach:
http://www.spinics.net/lists/linux-tegra/msg22760.html
@Rob: If we introduce flag bits in the MSBs of an I2C address, the reg
property is different from the node name. Is this a problem?
No, I don't it is a problem.
The rule so far has been that the unit address (the value in the node
name) must match the first value in the reg property. I don't see why
this rule should change. To solve this, just name the node
eeprom@c042 (or eeprom@4042 with the correction pointed out
earlier in the thread).
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[PATCH v3 1/4] i2c: tegra: implement slave mode
Initialization code is based on NVEC driver.
There is a HW bug in AP20 that was also mentioned in kernel sources
for Toshiba AC100.
Signed-off-by: Andrey Danin danind...@mail.ru
---
Changes for v3:
- handle 10-bit clients properly
Changes for v2:
- remove hack from tegra_i2c_clock_disable
- replace slave status helper functions with local variables
- add constant for default delay count value
- add 10-bit address support
- remove read_slave_start_delay init as zero
- don't reset controller during slave registration
- slave isr returns int instead of bool
- make status related variables in slave u32 instead of unsigned int
- enable i2c slave in Kconfig
- rebase on top of new i2c slave framework
- delay workaround was added from nvec
Signed-off-by: Andrey Danin danind...@mail.ru
---
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-tegra.c | 119 +
2 files changed, 120 insertions(+)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 0b798ae..3c02041 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -888,6 +888,7 @@ config I2C_SUN6I_P2WI
config I2C_TEGRA
tristate NVIDIA Tegra internal I2C controller
depends on ARCH_TEGRA
+ select I2C_SLAVE
help
If you say yes to this option, support will be included for the
I2C controller embedded in NVIDIA Tegra SOCs
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 78a3668..f6ecd28 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -42,8 +42,17 @@
#define I2C_SL_CNFG0x020
#define I2C_SL_CNFG_NACK (11)
#define I2C_SL_CNFG_NEWSL (12)
+#define I2C_SL_RCVD0x024
+#define I2C_SL_STATUS 0x028
+#define I2C_SL_ST_IRQ (13)
+#define I2C_SL_ST_END_TRANS(14)
+#define I2C_SL_ST_RCVD (12)
+#define I2C_SL_ST_RNW (11)
#define I2C_SL_ADDR1 0x02c
#define I2C_SL_ADDR2 0x030
+#define I2C_SL_ADDR2_TEN_BIT_MODE 1
+#define I2C_SL_DELAY_COUNT 0x03c
+#define I2C_SL_DELAY_COUNT_DEFAULT 0x1E
#define I2C_TX_FIFO0x050
#define I2C_RX_FIFO0x054
#define I2C_PACKET_TRANSFER_STATUS 0x058
@@ -125,6 +134,8 @@ enum msg_end_type {
* @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
* applicable if there is no fast clock source i.e. single clock
* source.
+ * @slave_read_start_delay: Workaround for AP20 I2C Slave Controller bug. Delay
+ * before writing data byte into register I2C_SL_RCVD.
*/
struct tegra_i2c_hw_feature {
@@ -133,6 +144,7 @@ struct tegra_i2c_hw_feature {
bool has_single_clk_source;
int clk_divisor_hs_mode;
int clk_divisor_std_fast_mode;
+ int slave_read_start_delay;
};
/**
@@ -173,6 +185,7 @@ struct tegra_i2c_dev {
int msg_read;
u32 bus_clk_rate;
bool is_suspended;
+ struct i2c_client *slave;
};
static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long
reg)
@@ -461,12 +474,78 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
return err;
}
+static void tegra_i2c_slave_write(struct tegra_i2c_dev *i2c_dev, u32 val)
+{
+ i2c_writel(i2c_dev, val, I2C_SL_RCVD);
+
+ /*
+* TODO: A correct fix needs to be found for this.
+*
+* We experience less incomplete messages with this delay than without
+* it, but we don't know why. Help is appreciated.
+*/
+ udelay(100);
+}
+
+static int tegra_i2c_slave_isr(int irq, struct tegra_i2c_dev *i2c_dev)
+{
+ u32 status;
+ u8 value;
+ u8 dummy;
+ u32 is_slave_irq, is_read, is_trans_start, is_trans_end;
+
+ if (!i2c_dev-slave || !i2c_dev-slave-slave_cb)
+ return -EINVAL;
+
+ status = i2c_readl(i2c_dev, I2C_SL_STATUS);
+
+ is_slave_irq = (status I2C_SL_ST_IRQ);
+ is_read = (status I2C_SL_ST_RNW);
+ is_trans_start = (status I2C_SL_ST_RCVD);
+ is_trans_end = (status I2C_SL_ST_END_TRANS);
+
+ if (!is_slave_irq)
+ return -EINVAL;
+
+ /* master sent stop */
+ if (is_trans_end) {
+ i2c_slave_event(i2c_dev-slave, I2C_SLAVE_STOP, dummy);
+ if (!is_trans_start)
+ return 0;
+ }
+
+ if (is_read) {
+ /* i2c master reads data from us */
+ i2c_slave_event(i2c_dev-slave,
+ is_trans_start ? I2C_SLAVE_READ_REQUESTED
+ : I2C_SLAVE_READ_PROCESSED,
+
Re: [Patch v4] driver/clk/clk-si5338: Add common clock framework driver for si5338
Dear Maintainers, Please review and advise if any change is needed. Thanks. York On 06/17/2015 11:49 AM, York Sun wrote: SI5338 is a programmable clock generator. It has 4 sets of inputs, PLL, multisynth and dividers to make 4 outputs. This driver splits them into multiple clocks to comply with common clock framework. See Documentation/devicetree/bindings/clock/silabs,si5338.txt for details. Export __clk_is_prepared from clk.c so drivers can check and unprepare clocks upon removal. Signed-off-by: York Sun york...@freescale.com CC: Mike Turquette mturque...@baylibre.com CC: Sebastian Hesselbarth sebastian.hesselba...@gmail.com CC: Guenter Roeck li...@roeck-us.net CC: Andrey Filippov and...@elphel.com CC: Paul Bolle pebo...@tiscali.nl --- Change log: v4: Add binding silabs,pll-vco Set pll rate initial value Separate COMMON_CLK change from this patch v3: Add calling unprepare upon removal Add registering to clkdev so the clk can be acquired when device tree is not in use Add a dev_info message when driver is removed Add missing static to two functions in clk-si5338.c Cosmatic fix in dt-bindings.clock/clk-si5338.h v2: Fix handling name prefix if the driver is unloaded and loaded again .../devicetree/bindings/clock/silabs,si5338.txt| 178 + drivers/clk/Kconfig| 12 + drivers/clk/Makefile |1 + drivers/clk/clk-si5338.c | 3682 drivers/clk/clk-si5338.h | 305 ++ drivers/clk/clk.c |1 + include/dt-bindings/clock/clk-si5338.h | 68 + include/linux/platform_data/si5338.h | 49 + 8 files changed, 4296 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5338.txt create mode 100644 drivers/clk/clk-si5338.c create mode 100644 drivers/clk/clk-si5338.h create mode 100644 include/dt-bindings/clock/clk-si5338.h create mode 100644 include/linux/platform_data/si5338.h diff --git a/Documentation/devicetree/bindings/clock/silabs,si5338.txt b/Documentation/devicetree/bindings/clock/silabs,si5338.txt new file mode 100644 index 000..807d5f6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5338.txt @@ -0,0 +1,178 @@ +Binding for Silicon Labs Si5338 programmable i2c clock generator. + +Reference +[1] Si5338 Data Sheet +http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5338.pdf + +The Si5338 is a programmable i2c clock generators with up to 4 output +clocks. It has 4 sets of possible input clocks + +IN1/IN2: differential +IN3: single-ended +IN4: single-ended +IN5/IN6: differential + +Additionally, IN1/IN2 can be used as XTAL with different setting. +The clock tree looks like below (without support of zero-delay) + + + IN1/IN2 IN3 IN4 IN5/IN6 + | | | | + --| | | | + | | | | | + | \ / \ / + | \ / \ / + | \ / \ / + XTAL REFCLKFBCLK + | | \ / | + | | \ /| + | | DIVREFCLK DIVFBCLK | + | | \ / | + | | \ / | + | | \ /| + | |PLL | + | | / | | \ | + | | / / \ \ | + | |/ / \ \ | + | | / | | \| + | | | | | || + | | MS0 MS1 MS2 MS3 | + | | | | | || + + OUT0 OUT1 OUT2 OUT3 + +The output clock can choose from any of the above clock as its source, with +exceptions: MS1 can only be used for OUT1, MS2 can only be used for OUT2, MS3 +can only be used for OUT3. + +==I2C device node== + +Required properties: +- compatible: shall be silabs,si5338. +- reg: i2c device address, shall be 0x60, 0x61, 0x70, or 0x71 +- #clock-cells: shall be set to 1 for multiple outputs +- clocks: list of parent clocks in the order of xtal, in1/2, in3, in4, in5/6 + Note, xtal and in1/2 are mutually exclusive. Only one can be set. +- #address-cells: shall be set to 1. +- #size-cells: shall be set to 0. + +Optional properties if not set by platform driver: +- silab,ref-source: source of refclk, valid value is defined as + #define SI5338_REF_SRC_CLKIN12 0 + #define SI5338_REF_SRC_CLKIN3 1 + #define SI5338_REF_SRC_XTAL 4 +- silab,fb-source: source of fbclk, valid value is defined as + #define SI5338_FB_SRC_CLKIN42 + #define SI5338_FB_SRC_CLKIN56 3 + #define SI5338_FB_SRC_NOCLK 5 +- silabs,pll-source: source of pll, valid value is defined as + #define
[PATCH v3 3/4] staging/nvec: remove old code
Signed-off-by: Andrey Danin danind...@mail.ru
---
No changes for v3
No changes for v2
Signed-off-by: Andrey Danin danind...@mail.ru
---
drivers/staging/nvec/nvec.c | 211
1 file changed, 211 deletions(-)
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 7da3dfe..fc0ee5c 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -516,23 +516,6 @@ static void nvec_rx_completed(struct nvec_chip *nvec)
schedule_work(nvec-rx_work);
}
-#if 0
-/**
- * nvec_invalid_flags - Send an error message about invalid flags and jump
- * @nvec: The nvec device
- * @status: The status flags
- * @reset: Whether we shall jump to state 0.
- */
-static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
- bool reset)
-{
- dev_err(nvec-dev, unexpected status flags 0x%02x during state %i\n,
- status, nvec-state);
- if (reset)
- nvec-state = 0;
-}
-#endif /* FIXME: remove old code */
-
/**
* nvec_tx_set - Set the message to transfer (nvec-tx)
* @nvec: A struct nvec_chip
@@ -562,200 +545,6 @@ static void nvec_tx_set(struct nvec_chip *nvec)
(uint)nvec-tx-size, nvec-tx-data[1]);
}
-
-#if 0
-/**
- * nvec_interrupt - Interrupt handler
- * @irq: The IRQ
- * @dev: The nvec device
- *
- * Interrupt handler that fills our RX buffers and empties our TX
- * buffers. This uses a finite state machine with ridiculous amounts
- * of error checking, in order to be fairly reliable.
- */
-static irqreturn_t nvec_interrupt(int irq, void *dev)
-{
- unsigned long status;
- unsigned int received = 0;
- unsigned char to_send = 0xff;
- const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
- struct nvec_chip *nvec = dev;
- unsigned int state = nvec-state;
-
- status = readl(nvec-base + I2C_SL_STATUS);
-
- /* Filter out some errors */
- if ((status irq_mask) == 0 (status ~irq_mask) != 0) {
- dev_err(nvec-dev, unexpected irq mask %lx\n, status);
- return IRQ_HANDLED;
- }
- if ((status I2C_SL_IRQ) == 0) {
- dev_err(nvec-dev, Spurious IRQ\n);
- return IRQ_HANDLED;
- }
-
- /* The EC did not request a read, so it send us something, read it */
- if ((status RNW) == 0) {
- received = readl(nvec-base + I2C_SL_RCVD);
- if (status RCVD)
- writel(0, nvec-base + I2C_SL_RCVD);
- }
-
- if (status == (I2C_SL_IRQ | RCVD))
- nvec-state = 0;
-
- switch (nvec-state) {
- case 0: /* Verify that its a transfer start, the rest later */
- if (status != (I2C_SL_IRQ | RCVD))
- nvec_invalid_flags(nvec, status, false);
- break;
- case 1: /* command byte */
- if (status != I2C_SL_IRQ) {
- nvec_invalid_flags(nvec, status, true);
- } else {
- nvec-rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
- /* Should not happen in a normal world */
- if (unlikely(nvec-rx == NULL)) {
- nvec-state = 0;
- break;
- }
- nvec-rx-data[0] = received;
- nvec-rx-pos = 1;
- nvec-state = 2;
- }
- break;
- case 2: /* first byte after command */
- if (status == (I2C_SL_IRQ | RNW | RCVD)) {
- udelay(33);
- if (nvec-rx-data[0] != 0x01) {
- dev_err(nvec-dev,
- Read without prior read command\n);
- nvec-state = 0;
- break;
- }
- nvec_msg_free(nvec, nvec-rx);
- nvec-state = 3;
- nvec_tx_set(nvec);
- BUG_ON(nvec-tx-size 1);
- to_send = nvec-tx-data[0];
- nvec-tx-pos = 1;
- } else if (status == (I2C_SL_IRQ)) {
- BUG_ON(nvec-rx == NULL);
- nvec-rx-data[1] = received;
- nvec-rx-pos = 2;
- nvec-state = 4;
- } else {
- nvec_invalid_flags(nvec, status, true);
- }
- break;
- case 3: /* EC does a block read, we transmit data */
- if (status END_TRANS) {
- nvec_tx_completed(nvec);
- } else if ((status RNW) == 0 || (status RCVD)) {
- nvec_invalid_flags(nvec, status, true);
- } else if (nvec-tx nvec-tx-pos
[PATCH v3 2/4] staging/nvec: reimplement on top of tegra i2c driver
Remove i2c controller related code and use tegra i2c driver in slave mode.
Update nvec documentation.
Signed-off-by: Andrey Danin danind...@mail.ru
---
Changes for v3:
- resolve conflict: 'nvec != NULL' changed to '!nvec'
Changes for v2:
- remove extra new line
- keep old functions to simplify review
- move nvec_state enum to nvec.c
- use nvec-slave instead of nvec in dts to keep ABI compatibility
- rebased on top of new i2c slave framework
- delay workaround moved to tegra-i2c
- documentation patch is integrated in this commit
- reverted a log message to minimize changes
Signed-off-by: Andrey Danin danind...@mail.ru
---
.../devicetree/bindings/nvec/nvidia,nvec.txt | 21 +-
drivers/staging/nvec/nvec.c| 258 +
drivers/staging/nvec/nvec.h| 10 -
3 files changed, 169 insertions(+), 120 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index 5ae601e..aba34095 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -1,21 +1,6 @@
NVIDIA compliant embedded controller
Required properties:
-- compatible : should be nvidia,nvec.
-- reg : the iomem of the i2c slave controller
-- interrupts : the interrupt line of the i2c slave controller
-- clock-frequency : the frequency of the i2c bus
-- gpios : the gpio used for ec request
-- slave-addr: the i2c address of the slave controller
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- Tegra20/Tegra30:
- - div-clk
- - fast-clk
- Tegra114:
- - div-clk
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- - i2c
+- compatible : should be nvidia,nvec-slave.
+- reg: the i2c address of the slave controller
+- request-gpios : the gpio used for ec request
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 164634d..7da3dfe 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -25,8 +25,8 @@
#include linux/err.h
#include linux/gpio.h
#include linux/interrupt.h
+#include linux/i2c.h
#include linux/io.h
-#include linux/irq.h
#include linux/of.h
#include linux/of_gpio.h
#include linux/list.h
@@ -39,25 +39,19 @@
#include nvec.h
-#define I2C_CNFG 0x00
-#define I2C_CNFG_PACKET_MODE_EN(110)
-#define I2C_CNFG_NEW_MASTER_SFM(111)
-#define I2C_CNFG_DEBOUNCE_CNT_SHIFT12
-
-#define I2C_SL_CNFG0x20
-#define I2C_SL_NEWSL (12)
-#define I2C_SL_NACK(11)
-#define I2C_SL_RESP(10)
-#define I2C_SL_IRQ (13)
-#define END_TRANS (14)
-#define RCVD (12)
-#define RNW(11)
-
-#define I2C_SL_RCVD0x24
-#define I2C_SL_STATUS 0x28
-#define I2C_SL_ADDR1 0x2c
-#define I2C_SL_ADDR2 0x30
-#define I2C_SL_DELAY_COUNT 0x3c
+
+#define I2C_SL_ST_END_TRANS(14)
+#define I2C_SL_ST_IRQ (13)
+#define I2C_SL_ST_RCVD (12)
+#define I2C_SL_ST_RNW (11)
+
+
+enum nvec_state {
+ ST_NONE,
+ ST_RX,
+ ST_TX,
+ ST_TRANS_START,
+};
/**
* enum nvec_msg_category - Message categories for nvec_msg_alloc()
@@ -479,7 +473,7 @@ static void nvec_tx_completed(struct nvec_chip *nvec)
nvec-tx-pos = 0;
nvec_gpio_set_value(nvec, 0);
} else {
- nvec-state = 0;
+ nvec-state = ST_NONE;
}
}
@@ -497,7 +491,7 @@ static void nvec_rx_completed(struct nvec_chip *nvec)
(uint) nvec-rx-pos);
nvec_msg_free(nvec, nvec-rx);
- nvec-state = 0;
+ nvec-state = ST_NONE;
/* Battery quirk - Often incomplete, and likes to crash */
if (nvec-rx-data[0] == NVEC_BAT)
@@ -514,7 +508,7 @@ static void nvec_rx_completed(struct nvec_chip *nvec)
spin_unlock(nvec-rx_lock);
- nvec-state = 0;
+ nvec-state = ST_NONE;
if (!nvec_msg_is_event(nvec-rx))
complete(nvec-ec_transfer);
@@ -522,6 +516,7 @@ static void nvec_rx_completed(struct nvec_chip *nvec)
schedule_work(nvec-rx_work);
}
+#if 0
/**
* nvec_invalid_flags - Send an error message about invalid flags and jump
* @nvec: The nvec device
@@ -536,6 +531,7 @@ static void nvec_invalid_flags(struct nvec_chip *nvec,
unsigned int status,
if (reset)
nvec-state = 0;
}
+#endif /* FIXME: remove old code */
/**
* nvec_tx_set - Set the message to transfer (nvec-tx)
@@ -566,6 +562,8 @@ static void
[PATCH v3 0/4] arm: tegra: implement NVEC driver using tegra i2c.
This version (v3) is for pushing tegra i2c driver to i2c tree. NVEC driver will be reworked later to use i2c core slave framework. NVEC driver contains code to manage tegra i2c controller in slave mode. I2C slave support was implemented in linux kernel. The goal of this patch serie is to implement I2C slave mode in tegra drived and rework NVEC driver to use it. Patches are based on i2c for-next. Changes for v3: - rebase on top of i2c for-next tree - fix 10-bit address condition in tegra i2c driver Changes for v2: - rebased on top of new i2c slave framework. - old code is removed in separate patch - documentation patch is integrated to main nvec patch Thanks in advance *** BLURB HERE *** Andrey Danin (4): i2c: tegra: implement slave mode staging/nvec: reimplement on top of tegra i2c driver staging/nvec: remove old code dt: paz00: define nvec as child of i2c bus .../devicetree/bindings/nvec/nvidia,nvec.txt | 21 +- arch/arm/boot/dts/tegra20-paz00.dts| 22 +- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-tegra.c | 119 ++ drivers/staging/nvec/nvec.c| 411 +++-- drivers/staging/nvec/nvec.h| 10 - 6 files changed, 269 insertions(+), 315 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/4] dt: paz00: define nvec as child of i2c bus
NVEC driver was reimplemented to use tegra i2c. Use common i2c bindings
for NVEC node.
Signed-off-by: Andrey Danin danind...@mail.ru
---
No changes for v3:
Changes for v2:
- swap reg and request-gpios properties
- use nvec-slave instead of nvec to keep ABI compatibility
- place doc in separate patch
Signed-off-by: Andrey Danin danind...@mail.ru
---
arch/arm/boot/dts/tegra20-paz00.dts | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts/tegra20-paz00.dts
index ed7e100..cd5e6ef 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -288,20 +288,16 @@
clock-frequency = 10;
};
- nvec@7000c500 {
- compatible = nvidia,nvec;
- reg = 0x7000c500 0x100;
- interrupts = GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH;
- #address-cells = 1;
- #size-cells = 0;
+ i2c@7000c500 {
+ status = okay;
clock-frequency = 8;
- request-gpios = gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH;
- slave-addr = 138;
- clocks = tegra_car TEGRA20_CLK_I2C3,
-tegra_car TEGRA20_CLK_PLL_P_OUT3;
- clock-names = div-clk, fast-clk;
- resets = tegra_car 67;
- reset-names = i2c;
+
+ nvec: nvec@45 {
+ compatible = nvidia,nvec-slave;
+ reg = 0x45;
+ request-gpios = gpio TEGRA_GPIO(V, 2)
+ GPIO_ACTIVE_HIGH;
+ };
};
i2c@7000d000 {
--
1.9.1
--
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