Re: [PATCH v2 05/10] i2c: rcar: refactor setup of a msg
> can continue that on Lager. In the meantime I could also capture I2C traces > using a scope and send them to you. Cool, thanks! I think I'll start with sending you another trace-printk patch soon. And can you push the branch you were using somewhere? With the config as an additional commit? signature.asc Description: PGP signature
Re: [PATCH] i2c: imx: make bus recovery through pinctrl optional
Hello,
On Tue, Nov 17, 2015 at 06:02:59PM -0600, Li Yang wrote:
> Since commit 1c4b6c3bcf30 ("i2c: imx: implement bus recovery") the driver
> starts to use gpio/pinctrl to do i2c bus recovery. But pinctrl is not
> always available for platforms using this driver such as ls1021a and
> ls1043a, and the device tree binding also mentioned this gpio based
> recovery mechanism as optional. The patch make it really optional that
> the probe function won't bailout when pinctrl is not available and it
> won't try to register recovery functions if pinctrl is NULL when the
> PINCTRL is not enabled at all.
>
> Signed-off-by: Li Yang
> Cc: Gao Pan
> ---
> drivers/i2c/busses/i2c-imx.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index 1e4d99d..7813153 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -1086,12 +1086,6 @@ static int i2c_imx_probe(struct platform_device *pdev)
> return ret;
> }
>
> - i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
> - if (IS_ERR(i2c_imx->pinctrl)) {
> - ret = PTR_ERR(i2c_imx->pinctrl);
> - goto clk_disable;
> - }
> -
> /* Request IRQ */
> ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
> pdev->name, i2c_imx);
> @@ -1125,7 +1119,12 @@ static int i2c_imx_probe(struct platform_device *pdev)
> goto clk_disable;
> }
>
> - i2c_imx_init_recovery_info(i2c_imx, pdev);
> + /* optional bus recovery feature through pinctrl */
> + i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
> + if (IS_ERR_OR_NULL(i2c_imx->pinctrl))
> + dev_info(&pdev->dev, "can't get pinctrl, bus recovery feature
> disabled\n");
> + else
> + i2c_imx_init_recovery_info(i2c_imx, pdev);
I'm pretty sure this is wrong. If pinctrl isn't available
devm_pinctrl_get returns NULL? But AFAIK you must not ignore an error,
so the better thing to do is:
i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(i2c_imx->pinctrl)) {
ret = PTR_ERR(i2c_imx->pinctrl);
goto errorhandling;
}
if (i2c_imx->pinctrl)
i2c_imx_init_recovery_info(i2c_imx, pdev);
else
dev_info(&pdev->dev, "can't get pinctrl, bus recovery feature
disabled\n");
right?
Uwe Kleine-König
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Re: [PATCH v2 05/10] i2c: rcar: refactor setup of a msg
Hi Magnus, On Wednesday 18 November 2015 11:18:00 Magnus Damm wrote: > On Tue, Nov 17, 2015 at 4:00 PM, Wolfram Sang wrote: > > Hi Laurent, > > > >> Sorry for bringing bad news, but as with v1, this patch breaks ADV7511 > >> detection on my Koelsch board. Reverting it on top of the series fixes > >> the problem. > > > > In v1, patch 5/9 was breaking. I hope in v2, it is 6/10 and not 5/10 as > > you replied to (patch 1/10 is the new one)? This bug is strange enough, > > but 5/10 breaking would be extremly crazy. > > > >> You'll find the dmesg and trace logs with your debugging patch applied > >> attached to this e-mail in two versions, one with the whole series > >> applied (- bad) and one with this patch additionally reverted on top of > >> the series (- good). > > > > Thanks for doing this. I'll think about it some more, but it may be that > > I am running out of ideas without being able to connect a scope. Would > > it be possible to exchange our Koelsch and Lager boards for a while? Or > > is your multimedia work Koelsch dependant? > > Swapping boards is of course one option, but shouldn't it also be > possible to reproduce the issue by creating a similar hardware setup > using loopback adapters? The problem is that you cannot reproduce it > on your current hardware, right? If I remember correctly not only has Wolfram not been able to reproduce the problem on his Lager board, but he hasn't been able to reproduce it you the remote access Koelsch board. I'm not sure how he could try to reproduce it locally with a "similar hardware setup" on Lager if it can't be reproduced on a different Koelsch board :-) > Judging by the Koelsch schematics port EXIO_C has GP6_22/GP6_23 routed > as SD2_CD_3/SC2_WP_3 that may be possible to repurpose as > IIC1_SCL_C/IIC1_SDA_C. So if you want to try an IIC master device on > Koeslch with the I2C2 devices that hold the ADV7511 chip then you > should be able to use those ZEBAX adapters and loopback wires. If you > want to sniff the I2C2 signals on Koelsch then the I2C2 bus is exposed > to EXIO_A and EXIO_D. > > On Lager it seems that the GP5_5/GP_6 pins with the I2C2 bus for the > ADV7511 chip has more flexible configuration, so using either IIC or > I2C should be possible. You can sample those pins on EXIO_A with the > ZEBAX break out adapter. > > And either way you should be able to compare the results of the I2C > and IIC masters with GPIO using the bitbang implementation. > > Feel free to let me know exactly what the problem is and I will do my > best to help you out! -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 05/10] i2c: rcar: refactor setup of a msg
Hi Wolfram, On Tue, Nov 17, 2015 at 4:00 PM, Wolfram Sang wrote: > Hi Laurent, > >> Sorry for bringing bad news, but as with v1, this patch breaks ADV7511 >> detection on my Koelsch board. Reverting it on top of the series fixes the >> problem. > > In v1, patch 5/9 was breaking. I hope in v2, it is 6/10 and not 5/10 as > you replied to (patch 1/10 is the new one)? This bug is strange enough, > but 5/10 breaking would be extremly crazy. > >> You'll find the dmesg and trace logs with your debugging patch applied >> attached to this e-mail in two versions, one with the whole series applied (- >> bad) and one with this patch additionally reverted on top of the series (- >> good). > > Thanks for doing this. I'll think about it some more, but it may be that > I am running out of ideas without being able to connect a scope. Would > it be possible to exchange our Koelsch and Lager boards for a while? Or > is your multimedia work Koelsch dependant? Swapping boards is of course one option, but shouldn't it also be possible to reproduce the issue by creating a similar hardware setup using loopback adapters? The problem is that you cannot reproduce it on your current hardware, right? Judging by the Koelsch schematics port EXIO_C has GP6_22/GP6_23 routed as SD2_CD_3/SC2_WP_3 that may be possible to repurpose as IIC1_SCL_C/IIC1_SDA_C. So if you want to try an IIC master device on Koeslch with the I2C2 devices that hold the ADV7511 chip then you should be able to use those ZEBAX adapters and loopback wires. If you want to sniff the I2C2 signals on Koelsch then the I2C2 bus is exposed to EXIO_A and EXIO_D. On Lager it seems that the GP5_5/GP_6 pins with the I2C2 bus for the ADV7511 chip has more flexible configuration, so using either IIC or I2C should be possible. You can sample those pins on EXIO_A with the ZEBAX break out adapter. And either way you should be able to compare the results of the I2C and IIC masters with GPIO using the bitbang implementation. Feel free to let me know exactly what the problem is and I will do my best to help you out! Thanks, / magnus -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] i2c: imx: make bus recovery through pinctrl optional
Since commit 1c4b6c3bcf30 ("i2c: imx: implement bus recovery") the driver
starts to use gpio/pinctrl to do i2c bus recovery. But pinctrl is not
always available for platforms using this driver such as ls1021a and
ls1043a, and the device tree binding also mentioned this gpio based
recovery mechanism as optional. The patch make it really optional that
the probe function won't bailout when pinctrl is not available and it
won't try to register recovery functions if pinctrl is NULL when the
PINCTRL is not enabled at all.
Signed-off-by: Li Yang
Cc: Gao Pan
---
drivers/i2c/busses/i2c-imx.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 1e4d99d..7813153 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1086,12 +1086,6 @@ static int i2c_imx_probe(struct platform_device *pdev)
return ret;
}
- i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
- if (IS_ERR(i2c_imx->pinctrl)) {
- ret = PTR_ERR(i2c_imx->pinctrl);
- goto clk_disable;
- }
-
/* Request IRQ */
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
pdev->name, i2c_imx);
@@ -1125,7 +1119,12 @@ static int i2c_imx_probe(struct platform_device *pdev)
goto clk_disable;
}
- i2c_imx_init_recovery_info(i2c_imx, pdev);
+ /* optional bus recovery feature through pinctrl */
+ i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR_OR_NULL(i2c_imx->pinctrl))
+ dev_info(&pdev->dev, "can't get pinctrl, bus recovery feature
disabled\n");
+ else
+ i2c_imx_init_recovery_info(i2c_imx, pdev);
/* Set up platform driver data */
platform_set_drvdata(pdev, i2c_imx);
--
2.3.3
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Re: [PATCH] i2c: imx: fix build issue for platforms without pinctrl
On Tue, Nov 17, 2015 at 3:11 PM, Li Yang wrote:
> With commit 1c4b6c3b (i2c: imx: implement bus recovery) the driver
> starts to use pinctrl to do i2c bus recovery. But this breaks build
> for platforms that don't implement pinctrl, such as ls1021a and
> ls1043a.
>
> This patch fix the problem by only compiling the bus recovery code
> when CONFIG_PINCTRL is enabled.
Please ignore this patch. I missed the patch from Zhiqiang
(https://patchwork.ozlabs.org/patch/545494/) to fix the same build
issue. Although the driver can build correctly when CONFIG_PINCTRL is
enabled by having included though
. Including the explicitly
seems to be a better fix for the build issue itself.
On the other hand, the driver shouldn't fail to probe or try to
register recovery routine when there is actually no pinctrl support as
the recovery is just an optional function. I can submit another patch
for this.
>
> Reported-by: Ren Xiaofeng
> Signed-off-by: Li Yang
> Cc: Gao Pan
> ---
> drivers/i2c/busses/i2c-imx.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index 1e4d99d..614253a 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -208,11 +208,13 @@ struct imx_i2c_struct {
> unsigned intcur_clk;
> unsigned intbitrate;
> const struct imx_i2c_hwdata *hwdata;
> +#ifdef CONFIG_PINCTRL
> struct i2c_bus_recovery_info rinfo;
>
> struct pinctrl *pinctrl;
> struct pinctrl_state *pinctrl_pins_default;
> struct pinctrl_state *pinctrl_pins_gpio;
> +#endif
>
> struct imx_i2c_dma *dma;
> };
> @@ -902,12 +904,14 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
>
> /* Start I2C transfer */
> result = i2c_imx_start(i2c_imx);
> +#ifdef CONFIG_PINCTRL
> if (result) {
> if (i2c_imx->adapter.bus_recovery_info) {
> i2c_recover_bus(&i2c_imx->adapter);
> result = i2c_imx_start(i2c_imx);
> }
> }
> +#endif
>
> if (result)
> goto fail0;
> @@ -969,6 +973,7 @@ fail0:
> return (result < 0) ? result : num;
> }
>
> +#ifdef CONFIG_PINCTRL
> static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
> {
> struct imx_i2c_struct *i2c_imx;
> @@ -1017,6 +1022,7 @@ static void i2c_imx_init_recovery_info(struct
> imx_i2c_struct *i2c_imx,
> rinfo->recover_bus = i2c_generic_gpio_recovery;
> i2c_imx->adapter.bus_recovery_info = rinfo;
> }
> +#endif
>
> static u32 i2c_imx_func(struct i2c_adapter *adapter)
> {
> @@ -1086,11 +1092,13 @@ static int i2c_imx_probe(struct platform_device *pdev)
> return ret;
> }
>
> +#ifdef CONFIG_PINCTRL
> i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
> if (IS_ERR(i2c_imx->pinctrl)) {
> ret = PTR_ERR(i2c_imx->pinctrl);
> goto clk_disable;
> }
> +#endif
>
> /* Request IRQ */
> ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
> @@ -1125,7 +1133,9 @@ static int i2c_imx_probe(struct platform_device *pdev)
> goto clk_disable;
> }
>
> +#ifdef CONFIG_PINCTRL
> i2c_imx_init_recovery_info(i2c_imx, pdev);
> +#endif
>
> /* Set up platform driver data */
> platform_set_drvdata(pdev, i2c_imx);
> --
> 2.3.3
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH] i2c: imx: fix build issue for platforms without pinctrl
With commit 1c4b6c3b (i2c: imx: implement bus recovery) the driver
starts to use pinctrl to do i2c bus recovery. But this breaks build
for platforms that don't implement pinctrl, such as ls1021a and
ls1043a.
This patch fix the problem by only compiling the bus recovery code
when CONFIG_PINCTRL is enabled.
Reported-by: Ren Xiaofeng
Signed-off-by: Li Yang
Cc: Gao Pan
---
drivers/i2c/busses/i2c-imx.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 1e4d99d..614253a 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -208,11 +208,13 @@ struct imx_i2c_struct {
unsigned intcur_clk;
unsigned intbitrate;
const struct imx_i2c_hwdata *hwdata;
+#ifdef CONFIG_PINCTRL
struct i2c_bus_recovery_info rinfo;
struct pinctrl *pinctrl;
struct pinctrl_state *pinctrl_pins_default;
struct pinctrl_state *pinctrl_pins_gpio;
+#endif
struct imx_i2c_dma *dma;
};
@@ -902,12 +904,14 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
/* Start I2C transfer */
result = i2c_imx_start(i2c_imx);
+#ifdef CONFIG_PINCTRL
if (result) {
if (i2c_imx->adapter.bus_recovery_info) {
i2c_recover_bus(&i2c_imx->adapter);
result = i2c_imx_start(i2c_imx);
}
}
+#endif
if (result)
goto fail0;
@@ -969,6 +973,7 @@ fail0:
return (result < 0) ? result : num;
}
+#ifdef CONFIG_PINCTRL
static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
{
struct imx_i2c_struct *i2c_imx;
@@ -1017,6 +1022,7 @@ static void i2c_imx_init_recovery_info(struct
imx_i2c_struct *i2c_imx,
rinfo->recover_bus = i2c_generic_gpio_recovery;
i2c_imx->adapter.bus_recovery_info = rinfo;
}
+#endif
static u32 i2c_imx_func(struct i2c_adapter *adapter)
{
@@ -1086,11 +1092,13 @@ static int i2c_imx_probe(struct platform_device *pdev)
return ret;
}
+#ifdef CONFIG_PINCTRL
i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(i2c_imx->pinctrl)) {
ret = PTR_ERR(i2c_imx->pinctrl);
goto clk_disable;
}
+#endif
/* Request IRQ */
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
@@ -1125,7 +1133,9 @@ static int i2c_imx_probe(struct platform_device *pdev)
goto clk_disable;
}
+#ifdef CONFIG_PINCTRL
i2c_imx_init_recovery_info(i2c_imx, pdev);
+#endif
/* Set up platform driver data */
platform_set_drvdata(pdev, i2c_imx);
--
2.3.3
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Re: [PATCH v6] at24: Support SMBus read/write of 16-bit devices
On Mon, 16 Nov 2015 18:02:19 -0600 (CST), Aaron Sierra wrote: > Previously, the at24 driver would bail out in the case of a 16-bit > addressable EEPROM attached to an SMBus controller. This is because > SMBus block reads and writes don't map to I2C multi-byte reads and > writes when the offset portion is 2 bytes. > > Instead of bailing out, this patch settles for functioning with single > byte read SMBus cycles. Writes can be block or single-byte, depending > on SMBus controller features. > > Read access is not without some risk. Multiple SMBus cycles are > required to read even one byte. If the SMBus has multiple masters and > one accesses this EEPROM between the dummy address write and the > subsequent current-address-read cycle(s), this driver will receive > data from the wrong address. > > Functionality has been tested with the following devices: > > AT24CM01 attached to Intel ISCH SMBus > AT24C512 attached to Intel I801 SMBus > > Read performance: > 3.6 KB/s with 32-byte* access > > *limited to 32-bytes by I2C_SMBUS_BLOCK_MAX. > > Write performance: > 248 B/s with 1-byte page (default) > 3.9 KB/s with 128-byte* page (via platform data) > > *limited to 31-bytes by I2C_SMBUS_BLOCK_MAX - 1. > > Signed-off-by: Nate Case > Signed-off-by: Aaron Sierra > Reviewed-by: Jean Delvare > --- > v2 - Account for changes related to introduction of > i2c_smbus_read_i2c_block_data_or_emulated() > v3 - Consolidate three patches into one > - Expand comments regarding SMBus multi-master read risks. > - Rely on current-address-read for improved read performance (i.e. one > dummy address write followed by multiple individual byte reads). > This improves performance from 1.4 KiB/s to 3.6 KiB/s. > - Use struct at24_data's writebuf instead of kzalloc-ing > - Only limit write_max by 1-byte when accessing a 16-bit device with > block writes instead of attempting to preserve a power-of-two. > - Style fixes (indentation, parentheses, unnecessary masking, etc.) > v4 - Address 16-bit safety in Kconfig > - Set "count" to zero later in at24_smbus_read_block_data() > - Fix over-80-columns issues in at24_eeprom_read() > - Fix write_max off-by-one in at24_probe() > - Check SMBus functionality needed for 16-bit device reads > - Homogenize indentation of SMBus functionality checks for SMBus write > v5 - 16-bit device read needs READ_BYTE not READ_BYTE_DATA > - Clarify write_max limiting with smbus_max > - Add X-ES copyright > v6 - Update comment associated with SMBus functionality testing for 16-bit > device read (READ_BYTE not READ_BYTE_DATA) > > drivers/misc/eeprom/Kconfig | 5 +- > drivers/misc/eeprom/at24.c | 132 > +++- > 2 files changed, 122 insertions(+), 15 deletions(-) > (...) Sweet, thanks for your patience. Now it's up to Wolfram. -- Jean Delvare SUSE L3 Support -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] i2c: Revert "i2c: xiic: Do not reset controller before every transfer"
On Tue, Nov 17, 2015 at 1:04 PM, Lars-Peter Clausen wrote:
> On 11/17/2015 06:17 AM, Shubhrajyoti Datta wrote:
>> On Mon, Nov 16, 2015 at 7:12 PM, Lars-Peter Clausen wrote:
>>> Commit d701667bb331 ("i2c: xiic: Do not reset controller before every
>>> transfer") removed the reinitialization of the controller before the start
>>> of each transfer. Apparently this change is not safe to make and the commit
>>> results in random I2C bus failures.
>>
>> Which is the platform and the ip version that you saw the issue.
>> Did you see the issue with read and write as well?
>
> The IP version is the axi-iic v2.0 Revision 8. I've tested this on a few
> platforms, custom ones and standard ones and I could reproduce it on most.
> One of them was on the ZED board. The one where I couldn't reproduce it was
> the ZC706. But that doesn't necessarily mean it doesn't happen there, just
> that it is not triggered by the testcase.
All the boards having the same version of the ip is what I have understood.
Thanks for the info I will try to reproduce the issue.
>
> The problem is that it is random corruption,
Of registers?
> so some I2C devices might start
> to behave strangely at some point. The only good more or less reliable way
> to reproduce it that I found was to run i2cdetect a couple of times and at
> least one of them will produce strange behavior.
>
I will try to reproduce the issue at my end thanks.
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[PATCH V5 0/6] i2c: qup: Add support for v2 tags and bam dma
QUP from version 2.1.1 onwards, supports a new format of i2c command tags. Tag codes instructs the controller to perform a operation like read/write. This new tagging version supports and is required for adding bam dma capabilities. V2 tags supports transfer of more than 256 bytes in a single i2c transaction. Also adding bam dma support facilitates transferring each i2c_msg in i2c_msgs without a 'stop' bit in between which is required for some of the clients. Tested this series on apq8074 dragon board eeprom client on i2c bus1 [V5] Addressed few more comments from Ivan T. Ivanov. Squashed patch 2 and 3 as no point in having only few lines of common code between v1 and v2 tags for increased complexity. Couple of non functional review comments fixes in patch 3, 4. Added a change in patch 4 to have proper transfer completion in a corner case. patch 5, 6 unchanged. [V4] Added a patch to factor out some common code. Removed support for freq > 400KHZ as per comments. Addressed comments from Ivan T. Ivanov to keep the code for V2 support in a separate path. Changed the authorship of V2 tags support patch. [V3] Added support to coalesce each i2c_msg in i2c_msgs for fifo and block mode in Patch 2. Also addressed further code comments. http://comments.gmane.org/gmane.linux.drivers.i2c/22497 [V2] Addressed comments from Ivan T. Ivanov, Andy Gross [v1] Initial Version Sricharan R (6): i2c: qup: Change qup_wait_writeready function to use for all timeouts i2c: qup: Add V2 tags support i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bit i2c: qup: Add bam dma capabilities dts: msm8974: Add blsp2_bam dma node dts: msm8974: Add dma channels for blsp2_i2c1 node arch/arm/boot/dts/qcom-msm8974.dtsi | 14 +- drivers/i2c/busses/i2c-qup.c| 931 ++-- 2 files changed, 896 insertions(+), 49 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 3/6] i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bit
The definition of i2c_msg says that
"If this is the last message in a group, it is followed by a STOP.
Otherwise it is followed by the next @i2c_msg transaction segment,
beginning with a (repeated) START"
So the expectation is that there is no 'STOP' bit inbetween individual
i2c_msg segments with repeated 'START'. The QUP i2c hardware has no way
to inform that there should not be a 'STOP' at the end of transaction.
The only way to implement this is to coalesce all the i2c_msg in i2c_msgs
in to one transaction and transfer them. Adding the support for the same.
This is required for some clients like touchscreen which keeps
incrementing counts across individual transfers and 'STOP' bit inbetween
resets the counter, which is not required.
This patch adds the support in non-dma mode.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 715d4d7..f9009d6 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -112,6 +112,7 @@
#define SET_BIT0x1
#define RESET_BIT 0x0
#define ONE_BYTE 0x1
+#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
struct qup_i2c_block {
int count;
@@ -147,6 +148,12 @@ struct qup_i2c_dev {
/* QUP core errors */
u32 qup_err;
+ /* To check if this is the last msg */
+ boolis_last;
+
+ /* To configure when bus is in run state */
+ int config_run;
+
struct completion xfer;
};
@@ -269,7 +276,7 @@ static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int
op, bool val,
status = readl(qup->base + QUP_I2C_STATUS);
if (((opflags & op) >> shift) == val) {
- if (op == QUP_OUT_NOT_EMPTY) {
+ if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
if (!(status & I2C_STATUS_BUS_ACTIVE))
return 0;
} else {
@@ -290,6 +297,8 @@ static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev
*qup,
/* Number of entries to shift out, including the tags */
int total = msg->len + qup->blk.tx_tag_len;
+ total |= qup->config_run;
+
if (total < qup->out_fifo_sz) {
/* FIFO mode */
writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
@@ -443,7 +452,7 @@ static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev
*qup,
}
/* Send _STOP commands for the last block */
- if (qup->blk.pos == (qup->blk.count - 1)) {
+ if ((qup->blk.pos == (qup->blk.count - 1)) && qup->is_last) {
if (msg->flags & I2C_M_RD)
tags[len++] = QUP_TAG_V2_DATARD_STOP;
else
@@ -581,7 +590,6 @@ static int qup_i2c_write_one(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
/* Wait for the outstanding data in the fifo to drain */
ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
-
err:
disable_irq(qup->irq);
qup->msg = NULL;
@@ -608,18 +616,20 @@ static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev
*qup, int len)
int tx_len = qup->blk.tx_tag_len;
len += qup->blk.rx_tag_len;
+ len |= qup->config_run;
+ tx_len |= qup->config_run;
if (len < qup->in_fifo_sz) {
/* FIFO mode */
writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
- writel(len, qup->base + QUP_MX_READ_CNT);
writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
+ writel(len, qup->base + QUP_MX_READ_CNT);
} else {
/* BLOCK mode (transfer data on chunks) */
writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
qup->base + QUP_IO_MODE);
- writel(len, qup->base + QUP_MX_INPUT_CNT);
writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
+ writel(len, qup->base + QUP_MX_INPUT_CNT);
}
}
@@ -866,6 +876,12 @@ static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
goto out;
}
+ qup->is_last = (idx == (num - 1));
+ if (idx)
+ qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
+ else
+ qup->config_run = 0;
+
reinit_completion(&qup->xfer);
if (msgs[idx].flags & I2C_M_RD)
@@ -873,13 +889,13 @@ static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
else
ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
- if (!ret)
- ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
-
if (ret)
break;
[PATCH V5 2/6] i2c: qup: Add V2 tags support
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write. This new tagging version
supports bam dma and transfers of more than 256 bytes without 'stop'
in between. Adding the support for the same.
For each block a data_write/read tag and data_len tag is added to
the output fifo. For the final block of data write_stop/read_stop
tag is used.
Signed-off-by: Andy Gross
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 415 ---
1 file changed, 386 insertions(+), 29 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 81ed120..715d4d7 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -42,6 +42,7 @@
#define QUP_IN_FIFO_BASE 0x218
#define QUP_I2C_CLK_CTL0x400
#define QUP_I2C_STATUS 0x404
+#define QUP_I2C_MASTER_GEN 0x408
/* QUP States and reset values */
#define QUP_RESET_STATE0
@@ -69,6 +70,8 @@
#define QUP_CLOCK_AUTO_GATEBIT(13)
#define I2C_MINI_CORE (2 << 8)
#define I2C_N_VAL 15
+#define I2C_N_VAL_V2 7
+
/* Most significant word offset in FIFO port */
#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
@@ -79,6 +82,7 @@
#define QUP_PACK_ENBIT(15)
#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
+#define QUP_V2_TAGS_EN 1
#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
#define QUP_OUTPUT_FIFO_SIZE(x)(((x) >> 2) & 0x07)
@@ -91,6 +95,13 @@
#define QUP_TAG_STOP (3 << 8)
#define QUP_TAG_REC(4 << 8)
+/* QUP v2 tags */
+#define QUP_TAG_V2_START 0x81
+#define QUP_TAG_V2_DATAWR 0x82
+#define QUP_TAG_V2_DATAWR_STOP 0x83
+#define QUP_TAG_V2_DATARD 0x85
+#define QUP_TAG_V2_DATARD_STOP 0x87
+
/* Status, Error flags */
#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
#define I2C_STATUS_BUS_ACTIVE BIT(8)
@@ -102,6 +113,15 @@
#define RESET_BIT 0x0
#define ONE_BYTE 0x1
+struct qup_i2c_block {
+ int count;
+ int pos;
+ int tx_tag_len;
+ int rx_tag_len;
+ int data_len;
+ u8 tags[6];
+};
+
struct qup_i2c_dev {
struct device *dev;
void __iomem*base;
@@ -117,6 +137,7 @@ struct qup_i2c_dev {
int in_blk_sz;
unsigned long one_byte_t;
+ struct qup_i2c_blockblk;
struct i2c_msg *msg;
/* Current posion in user message buffer */
@@ -263,6 +284,24 @@ static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int
op, bool val,
}
}
+static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
+ struct i2c_msg *msg)
+{
+ /* Number of entries to shift out, including the tags */
+ int total = msg->len + qup->blk.tx_tag_len;
+
+ if (total < qup->out_fifo_sz) {
+ /* FIFO mode */
+ writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
+ writel(total, qup->base + QUP_MX_WRITE_CNT);
+ } else {
+ /* BLOCK mode (transfer data on chunks) */
+ writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
+ qup->base + QUP_IO_MODE);
+ writel(total, qup->base + QUP_MX_OUTPUT_CNT);
+ }
+}
+
static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg
*msg)
{
/* Number of entries to shift out, including the start */
@@ -324,9 +363,189 @@ static int qup_i2c_issue_write(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
return ret;
}
-static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
+static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
+struct i2c_msg *msg)
+{
+ memset(&qup->blk, 0, sizeof(qup->blk));
+
+ qup->blk.data_len = msg->len;
+ qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
+
+ /* 4 bytes for first block and 2 writes for rest */
+ qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
+
+ /* There are 2 tag bytes that are read in to fifo for every block */
+ if (msg->flags & I2C_M_RD)
+ qup->blk.rx_tag_len = qup->blk.count * 2;
+}
+
+static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
+int dlen, u8 *dbuf)
+{
+ u32 val = 0, idx = 0, pos = 0, i = 0, t;
+ int len = tlen + dlen;
+ u8 *buf = tbuf;
+ int ret = 0;
+
+ while (len > 0) {
+ ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
+RESET_BIT, 4 * ONE_BYTE);
+ if (ret) {
+ dev_err(qup->dev, "timeout for fifo out full");
+ retur
[PATCH V5 6/6] dts: msm8974: Add dma channels for blsp2_i2c1 node
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 7786408..bd1be53 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -328,6 +328,8 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
};
spmi_bus: spmi@fc4cf000 {
--
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[PATCH V5 5/6] dts: msm8974: Add blsp2_bam dma node
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 753bdfd..7786408 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,6 @@
/dts-v1/;
-#include
+#include
#include
#include "skeleton.dtsi"
@@ -345,6 +345,16 @@
interrupt-controller;
#interrupt-cells = <4>;
};
+
+ blsp2_dma: dma-controller@f9944000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xf9944000 0x19000>;
+ interrupts = ;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
};
smd {
--
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[PATCH V5 1/6] i2c: qup: Change qup_wait_writeready function to use for all timeouts
qup_wait_writeready waits only on a output fifo empty event.
Change the same function to accept the event and data length
to wait as parameters. This way the same function can be used for
timeouts in other places as well.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 67 +++-
1 file changed, 48 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index fdcbdab..81ed120 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -98,6 +98,9 @@
#define QUP_STATUS_ERROR_FLAGS 0x7c
#define QUP_READ_LIMIT 256
+#define SET_BIT0x1
+#define RESET_BIT 0x0
+#define ONE_BYTE 0x1
struct qup_i2c_dev {
struct device *dev;
@@ -221,26 +224,42 @@ static int qup_i2c_change_state(struct qup_i2c_dev *qup,
u32 state)
return 0;
}
-static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
+/**
+ * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
+ * @qup: The qup_i2c_dev device
+ * @op: The bit/event to wait on
+ * @val: value of the bit to wait on, 0 or 1
+ * @len: The length the bytes to be transferred
+ */
+static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
+ int len)
{
unsigned long timeout;
u32 opflags;
u32 status;
+ u32 shift = __ffs(op);
- timeout = jiffies + HZ;
+ len *= qup->one_byte_t;
+ /* timeout after a wait of twice the max time */
+ timeout = jiffies + len * 4;
for (;;) {
opflags = readl(qup->base + QUP_OPERATIONAL);
status = readl(qup->base + QUP_I2C_STATUS);
- if (!(opflags & QUP_OUT_NOT_EMPTY) &&
- !(status & I2C_STATUS_BUS_ACTIVE))
- return 0;
+ if (((opflags & op) >> shift) == val) {
+ if (op == QUP_OUT_NOT_EMPTY) {
+ if (!(status & I2C_STATUS_BUS_ACTIVE))
+ return 0;
+ } else {
+ return 0;
+ }
+ }
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
- usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
+ usleep_range(len, len * 2);
}
}
@@ -261,13 +280,13 @@ static void qup_i2c_set_write_mode(struct qup_i2c_dev
*qup, struct i2c_msg *msg)
}
}
-static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
+static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
u32 addr = msg->addr << 1;
u32 qup_tag;
- u32 opflags;
int idx;
u32 val;
+ int ret = 0;
if (qup->pos == 0) {
val = QUP_TAG_START | addr;
@@ -279,9 +298,10 @@ static void qup_i2c_issue_write(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
while (qup->pos < msg->len) {
/* Check that there's space in the FIFO for our pair */
- opflags = readl(qup->base + QUP_OPERATIONAL);
- if (opflags & QUP_OUT_FULL)
- break;
+ ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL, RESET_BIT,
+4 * ONE_BYTE);
+ if (ret)
+ return ret;
if (qup->pos == msg->len - 1)
qup_tag = QUP_TAG_STOP;
@@ -300,6 +320,8 @@ static void qup_i2c_issue_write(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
qup->pos++;
idx++;
}
+
+ return ret;
}
static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
@@ -325,7 +347,9 @@ static int qup_i2c_write_one(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
if (ret)
goto err;
- qup_i2c_issue_write(qup, msg);
+ ret = qup_i2c_issue_write(qup, msg);
+ if (ret)
+ goto err;
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
if (ret)
@@ -347,7 +371,7 @@ static int qup_i2c_write_one(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
} while (qup->pos < msg->len);
/* Wait for the outstanding data in the fifo to drain */
- ret = qup_i2c_wait_writeready(qup);
+ ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
err:
disable_irq(qup->irq);
@@ -384,18 +408,19 @@ static void qup_i2c_issue_read(struct qup_i2c_dev *qup,
struct i2c_msg *msg)
}
-static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
+static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
{
- u32 opflags;
u32 val = 0;
in
[PATCH V5 4/6] i2c: qup: Add bam dma capabilities
QUP cores can be attached to a BAM module, which acts as a dma engine for the
QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data
is written to the output FIFO and the BAM producer pipe received data is read
from the input FIFO.
With BAM capabilities, qup-i2c core can transfer more than 256 bytes, without a
'stop' which is not possible otherwise.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 447 ++-
1 file changed, 439 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index f9009d6..4ca1669 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -14,8 +14,12 @@
*
*/
+#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -24,6 +28,7 @@
#include
#include
#include
+#include
/* QUP Registers */
#define QUP_CONFIG 0x000
@@ -33,6 +38,7 @@
#define QUP_OPERATIONAL0x018
#define QUP_ERROR_FLAGS0x01c
#define QUP_ERROR_FLAGS_EN 0x020
+#define QUP_OPERATIONAL_MASK 0x028
#define QUP_HW_VERSION 0x030
#define QUP_MX_OUTPUT_CNT 0x100
#define QUP_OUT_FIFO_BASE 0x110
@@ -52,6 +58,7 @@
#define QUP_STATE_VALIDBIT(2)
#define QUP_I2C_MAST_GEN BIT(4)
+#define QUP_I2C_FLUSH BIT(6)
#define QUP_OPERATIONAL_RESET 0x000ff0
#define QUP_I2C_STATUS_RESET 0xfc
@@ -77,7 +84,10 @@
/* Packing/Unpacking words in FIFOs, and IO modes */
#define QUP_OUTPUT_BLK_MODE(1 << 10)
+#define QUP_OUTPUT_BAM_MODE(3 << 10)
#define QUP_INPUT_BLK_MODE (1 << 12)
+#define QUP_INPUT_BAM_MODE (3 << 12)
+#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
#define QUP_UNPACK_EN BIT(14)
#define QUP_PACK_ENBIT(15)
@@ -94,6 +104,8 @@
#define QUP_TAG_DATA (2 << 8)
#define QUP_TAG_STOP (3 << 8)
#define QUP_TAG_REC(4 << 8)
+#define QUP_BAM_INPUT_EOT 0x93
+#define QUP_BAM_FLUSH_STOP 0x96
/* QUP v2 tags */
#define QUP_TAG_V2_START 0x81
@@ -114,6 +126,12 @@
#define ONE_BYTE 0x1
#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
+#define MX_TX_RX_LEN SZ_64K
+#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
+
+/* Max timeout in ms for 32k bytes */
+#define TOUT_MAX 300
+
struct qup_i2c_block {
int count;
int pos;
@@ -123,6 +141,17 @@ struct qup_i2c_block {
u8 tags[6];
};
+struct qup_i2c_tag {
+ u8 *start;
+ dma_addr_t addr;
+};
+
+struct qup_i2c_bam {
+ struct qup_i2c_tag tag;
+ struct dma_chan *dma;
+ struct scatterlist *sg;
+};
+
struct qup_i2c_dev {
struct device *dev;
void __iomem*base;
@@ -154,6 +183,13 @@ struct qup_i2c_dev {
/* To configure when bus is in run state */
int config_run;
+ /* dma parameters */
+ boolis_dma;
+ struct dma_pool *dpool;
+ struct qup_i2c_tag start_tag;
+ struct qup_i2c_bam brx;
+ struct qup_i2c_bam btx;
+
struct completion xfer;
};
@@ -230,6 +266,14 @@ static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32
req_state)
return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
}
+static void qup_i2c_flush(struct qup_i2c_dev *qup)
+{
+ u32 val = readl(qup->base + QUP_STATE);
+
+ val |= QUP_I2C_FLUSH;
+ writel(val, qup->base + QUP_STATE);
+}
+
static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
{
return qup_i2c_poll_state_mask(qup, 0, 0);
@@ -437,12 +481,14 @@ static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
}
static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
- struct i2c_msg *msg)
+ struct i2c_msg *msg, int is_dma)
{
u16 addr = (msg->addr << 1) | ((msg->flags & I2C_M_RD) == I2C_M_RD);
int len = 0;
int data_len;
+ int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
+
if (qup->blk.pos == 0) {
tags[len++] = QUP_TAG_V2_START;
tags[len++] = addr & 0xff;
@@ -452,7 +498,7 @@ static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev
*qup,
}
/* Send _STOP commands for the last block */
- if ((qup->blk.pos == (qup->blk.count - 1)) && qup->is_last) {
+ if (last) {
if (msg->flags & I2C_M_RD)
tags[len++] = QUP_TAG_V2_DATARD_STOP;
else
@@ -472,6 +518,11 @@ static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev
*qup,
else
tags[len++] = data_len;
+ if ((msg->flags & I
[PATCHv8 5/5] ARM64: dts: add LS1043a-RDB board support
From: Shaohui Xie
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Wenbin Song
Signed-off-by: Hou Zhiqiang
---
V8 - V7:
- Rebased on latest LS2080 patches.
V6: V5 V4 V3
- No change.
V2:
- Remove the useless compatible "simple-bus" from cpld node.
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 116 ++
2 files changed, 117 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index c4957a4..f3c2516 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
new file mode 100644
index 000..ce23557
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -0,0 +1,116 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A RDB Board";
+};
+
+&i2c0 {
+ status = "okay";
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ adt7461a@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ eeprom@52 {
+ compatible = "at24,24c512";
+ reg = <0x52>;
+ };
+ eeprom@53 {
+ compatible = "at24,24c512";
+ reg = <0x53>;
+ };
+ rtc@68 {
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x6000 0x0800
+ 0x1 0x0 0x0 0x7e80 0x0001
+ 0x2 0x0 0x0 0x7fb0 0x0100>;
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x800>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@1,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x1>;
+ };
+
+ cpld: boar
[PATCHv8 1/5] i2c: imx: fix a compiling error
From: Hou Zhiqiang drivers/i2c/busses/i2c-imx.c:978:2: error: implicit declaration of function ‘pinctrl_select_state’ [-Werror=implicit-function-declaration] pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); ^ Signed-off-by: Hou Zhiqiang --- V8: - New patch. drivers/i2c/busses/i2c-imx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 1e4d99d..9bb0b05 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include -- 2.1.0.27.g96db324 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv8 4/5] ARM64: dts: add Freescale LS1043a SoC support
From: Mingkai Hu
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are
similar to LS1021a which also complies to Freescale Chassis 2.1 spec.
Created LS1043a SoC DTSI file to be included by board level DTS files.
Signed-off-by: Li Yang
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mingkai Hu
Signed-off-by: Wenbin Song
---
V8:
- Add the properity 'big-endian' for DCFG DT node
- Add the reboot node.
V7:
- Some update to patch description.
V6:
- No change.
V5:
- Move gic, timer and pmu nodes out of SoC node.
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.
V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node.
Remove reserved memory region for spin-table.
V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 527 +
1 file changed, 527 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
new file mode 100644
index 000..42a6154
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -0,0 +1,527 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /*
+* We expect the enable-method for cpu's to be "psci", but this
+* is dependent on the SoC FW, which will fill this in.
+*
+* Currently supported enable-method is psci v0.2
+*/
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ memory@8000 {
+ device_type =
[PATCHv8 2/5] watchdog: Add support for Freescale Layerscape platforms
From: Shaohui Xie Modify watchdog/Kconfig file to support Layerscape platforms. Signed-off-by: Shaohui Xie Signed-off-by: Hou Zhiqiang Acked-by: Guenter Roeck --- V8: - No change. V6: - Remove a Signed-off. V5: V4 V3 V2 - No change. drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 7a8a6c6..1c427be 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG config IMX2_WDT tristate "IMX2+ Watchdog" - depends on ARCH_MXC + depends on ARCH_MXC || ARCH_LAYERSCAPE select REGMAP_MMIO select WATCHDOG_CORE help -- 2.1.0.27.g96db324 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv8 3/5] Documentation: DT: Add entry for Freescale LS1043a-RDB board
From: Mingkai Hu Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang --- V8 - V2: - No change. Documentation/devicetree/bindings/arm/fsl.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 34c88b0..752a685 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -131,6 +131,10 @@ Example: Freescale ARMv8 based Layerscape SoC family Device Tree Bindings +LS1043A ARMv8 based RDB Board +Required root node properties: +- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; + LS2080A ARMv8 based Simulator model Required root node properties: - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; -- 2.1.0.27.g96db324 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v2 3/9] eeprom: at24: tie up an additional address for at24cs series
The at24cs series EEPROM chips have an additional read-only memory area,
that is visible on a different i2c slave address. Tie it up with a dummy
device.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 5d7c090..08cc327 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -103,6 +103,8 @@ MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes
(default 25)");
#define AT24_BITMASK(x) (BIT(x) - 1)
+#define AT24CS_SERIAL_ADDR(addr) (addr + 0x08)
+
/* create non-zero magic value for given eeprom parameters */
#define AT24_DEVICE_MAGIC(_len, _flags)\
((1 << AT24_SIZE_FLAGS | (_flags)) \
@@ -558,6 +560,8 @@ static int at24_probe(struct i2c_client *client, const
struct i2c_device_id *id)
if (chip.flags & AT24_FLAG_TAKE8ADDR)
num_addresses = 8;
+ else if (chip.flags & AT24_FLAG_SERIAL)
+ num_addresses = 2;
else
num_addresses = DIV_ROUND_UP(chip.byte_len,
(chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256);
@@ -616,12 +620,30 @@ static int at24_probe(struct i2c_client *client, const
struct i2c_device_id *id)
at24->client[0] = client;
/* use dummy devices for multiple-address chips */
- for (i = 1; i < num_addresses; i++) {
- at24->client[i] = i2c_new_dummy(client->adapter,
+ if (at24->chip.flags & AT24_FLAG_TAKE8ADDR) {
+ for (i = 1; i < num_addresses; i++) {
+ at24->client[i] = i2c_new_dummy(client->adapter,
+ client->addr + i);
+ if (!at24->client[i]) {
+ dev_err(&client->dev,
+ "address 0x%02x unavailable\n",
client->addr + i);
- if (!at24->client[i]) {
+ err = -EADDRINUSE;
+ goto err_clients;
+ }
+ }
+ }
+
+ /*
+* at24cs series tie up an additional address for the memory area
+* contining the serial number
+*/
+ if (at24->chip.flags & AT24_FLAG_SERIAL) {
+ at24->client[1] = i2c_new_dummy(client->adapter,
+ AT24CS_SERIAL_ADDR(client->addr));
+ if (!at24->client[1]) {
dev_err(&client->dev, "address 0x%02x unavailable\n",
- client->addr + i);
+ AT24CS_SERIAL_ADDR(client->addr));
err = -EADDRINUSE;
goto err_clients;
}
--
2.1.4
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[RESEND PATCH v2 2/9] eeprom: at24: new flag in platform_data
In preparation for supporting the at24cs EEPROM series add a new flag to
platform data. When set, it should tell the driver that the chip has an
additional read-only memory area that holds a factory pre-programmed serial
number.
Signed-off-by: Bartosz Golaszewski
---
include/linux/platform_data/at24.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/platform_data/at24.h
b/include/linux/platform_data/at24.h
index 8d90f52..5686f91 100644
--- a/include/linux/platform_data/at24.h
+++ b/include/linux/platform_data/at24.h
@@ -47,6 +47,7 @@ struct at24_platform_data {
#define AT24_FLAG_READONLY BIT(6) /* sysfs-entry will be read-only */
#define AT24_FLAG_IRUGOBIT(5) /* sysfs-entry will be
world-readable */
#define AT24_FLAG_TAKE8ADDRBIT(4) /* take always 8 addresses (24c00) */
+#define AT24_FLAG_SERIAL BIT(3) /* factory-programmed serial number */
void(*setup)(struct memory_accessor *, void *context);
void*context;
--
2.1.4
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[RESEND PATCH v2 6/9] eeprom: at24: improve the device_id table readability
Improve the readability of the device table by separating columns with
tabs.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 65fca1e..d474b6d 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -114,23 +114,23 @@ MODULE_PARM_DESC(write_timeout, "Time (in ms) to try
writes (default 25)");
static const struct i2c_device_id at24_ids[] = {
/* needs 8 addresses as A0-A2 are ignored */
- { "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
+ { "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
/* old variants can't be handled with this generic entry! */
- { "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
- { "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
+ { "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
+ { "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
/* spd is a 24c02 in memory DIMMs */
- { "spd", AT24_DEVICE_MAGIC(2048 / 8,
- AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
- { "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
+ { "spd",AT24_DEVICE_MAGIC(2048 / 8,
+ AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
+ { "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
/* 24rf08 quirk is handled at i2c-core */
- { "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
- { "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
- { "24c32", AT24_DEVICE_MAGIC(32768 / 8, AT24_FLAG_ADDR16) },
- { "24c64", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16) },
- { "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
- { "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
- { "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
- { "24c1024", AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
+ { "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
+ { "24c16", AT24_DEVICE_MAGIC(16384 / 8,0) },
+ { "24c32", AT24_DEVICE_MAGIC(32768 / 8,AT24_FLAG_ADDR16) },
+ { "24c64", AT24_DEVICE_MAGIC(65536 / 8,AT24_FLAG_ADDR16) },
+ { "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
+ { "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
+ { "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
+ { "24c1024",AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
{ "at24", 0 },
{ /* END OF LIST */ }
};
--
2.1.4
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[RESEND PATCH v2 0/9] eeprom: at24: at24cs series serial number read
Chips from the at24cs EEPROM series have an additional read-only memory area containing a factory pre-programmed serial number. In order to access it, a dummy write must be executed before reading the serial number bytes. This series adds support for reading the serial number through a sysfs attribute. While we're at it: some of the patches contain readability tweaks and code organization fixes. Tested with at24cs64 and at24cs02 chips (for both 16 and 8 bit address pointers). (rebased against 4.4-rc1) v2: - protect the serial number read with a mutex v1: https://lkml.org/lkml/2015/10/20/162 Bartosz Golaszewski (9): eeprom: at24: platform_data: use BIT() macro eeprom: at24: new flag in platform_data eeprom: at24: tie up an additional address for at24cs series eeprom: at24: support reading of the serial number eeprom: at24: export the serial number through sysfs eeprom: at24: improve the device_id table readability eeprom: at24: add the at24cs series to the list of supported devices eeprom: at24: remove a reduntant if eeprom: at24: readability tweaks drivers/misc/eeprom/at24.c | 187 +++-- include/linux/platform_data/at24.h | 9 +- 2 files changed, 166 insertions(+), 30 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v2 4/9] eeprom: at24: support reading of the serial number
The at24cs series EEPROM chips have an additional read-only memory area
containing a factory pre-programmed serial number. In order to access
it, one has to perform a dummy write before reading the serial number
bytes.
Add a function that allows to access the serial number.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 71 ++
1 file changed, 71 insertions(+)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 08cc327..6182f47 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -163,6 +163,77 @@ static struct i2c_client *at24_translate_offset(struct
at24_data *at24,
return at24->client[i];
}
+static int __attribute__((unused)) at24cs_eeprom_serial_read(
+ struct at24_data *at24,
+ char *buf, unsigned offset,
+ size_t count)
+{
+ unsigned long timeout, read_time;
+ struct i2c_client *client;
+ struct i2c_msg msg[2];
+ u8 addrbuf[2];
+ int status;
+
+ mutex_lock(&at24->lock);
+
+ client = at24->client[1];
+
+ memset(msg, 0, sizeof(msg));
+ msg[0].addr = client->addr;
+ msg[0].buf = addrbuf;
+
+ /*
+* The address pointer of the device is shared between the regular
+* EEPROM array and the serial number block. The dummy write (part of
+* the sequential read protocol) ensures the address pointer is reset
+* to the desired position.
+*/
+ if (at24->chip.flags & AT24_FLAG_ADDR16) {
+ /*
+* For 16 bit address pointers, the word address must contain
+* a '10' sequence in bits 11 and 10 regardless of the
+* intended position of the address pointer.
+*/
+ addrbuf[0] = 0x08;
+ addrbuf[1] = offset;
+ msg[0].len = 2;
+ } else {
+ /*
+* Otherwise the word address must begin with a '10' sequence,
+* regardless of the intended address.
+*/
+ addrbuf[0] = 0x80 + offset;
+ msg[0].len = 1;
+ }
+
+ msg[1].addr = client->addr;
+ msg[1].flags = I2C_M_RD;
+ msg[1].buf = buf;
+ msg[1].len = count;
+
+ /*
+* Reads fail if the previous write didn't complete yet. We may
+* loop a few times until this one succeeds, waiting at least
+* long enough for one entire page write to work.
+*/
+ timeout = jiffies + msecs_to_jiffies(write_timeout);
+ do {
+ read_time = jiffies;
+ status = i2c_transfer(client->adapter, msg, 2);
+ if (status == 2) {
+ mutex_unlock(&at24->lock);
+ return count;
+ }
+
+ /* REVISIT: at HZ=100, this is slw */
+ msleep(1);
+ } while (time_before(read_time, timeout));
+
+ mutex_unlock(&at24->lock);
+
+ return -ETIMEDOUT;
+}
+
static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf,
unsigned offset, size_t count)
{
--
2.1.4
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[RESEND PATCH v2 5/9] eeprom: at24: export the serial number through sysfs
The at24 driver is now capable of reading the serial number from at24cs
EEPROM chips. Export the serial number through sysfs.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 44
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 6182f47..65fca1e 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -65,6 +65,7 @@ struct at24_data {
*/
struct mutex lock;
struct bin_attribute bin;
+ struct bin_attribute *bin_serial;
u8 *writebuf;
unsigned write_max;
@@ -103,6 +104,7 @@ MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes
(default 25)");
#define AT24_BITMASK(x) (BIT(x) - 1)
+#define AT24CS_SERIAL_SIZE 16
#define AT24CS_SERIAL_ADDR(addr) (addr + 0x08)
/* create non-zero magic value for given eeprom parameters */
@@ -163,10 +165,8 @@ static struct i2c_client *at24_translate_offset(struct
at24_data *at24,
return at24->client[i];
}
-static int __attribute__((unused)) at24cs_eeprom_serial_read(
- struct at24_data *at24,
- char *buf, unsigned offset,
- size_t count)
+static int at24cs_eeprom_serial_read(struct at24_data *at24, char *buf,
+unsigned offset, size_t count)
{
unsigned long timeout, read_time;
struct i2c_client *client;
@@ -234,6 +234,16 @@ static int __attribute__((unused))
at24cs_eeprom_serial_read(
return -ETIMEDOUT;
}
+static ssize_t at24cs_bin_serial_read(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct at24_data *at24;
+
+ at24 = dev_get_drvdata(container_of(kobj, struct device, kobj));
+ return at24cs_eeprom_serial_read(at24, buf, off, count);
+}
+
static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf,
unsigned offset, size_t count)
{
@@ -658,6 +668,30 @@ static int at24_probe(struct i2c_client *client, const
struct i2c_device_id *id)
at24->bin.read = at24_bin_read;
at24->bin.size = chip.byte_len;
+ if (at24->chip.flags & AT24_FLAG_SERIAL) {
+ /*
+* For EEPROMs containing the serial number export an
+* additional file allowing allowing convenvient access
+* to it from user-space.
+*/
+ at24->bin_serial = devm_kzalloc(&client->dev,
+ sizeof(struct bin_attribute),
+ GFP_KERNEL);
+ if (!at24->bin_serial)
+ return -ENOMEM;
+
+ sysfs_bin_attr_init(at24->bin_serial);
+ at24->bin_serial->attr.name = "serial";
+ at24->bin_serial->attr.mode = S_IRUSR;
+ at24->bin_serial->read = at24cs_bin_serial_read;
+ at24->bin_serial->size = AT24CS_SERIAL_SIZE;
+
+ err = sysfs_create_bin_file(&client->dev.kobj,
+ at24->bin_serial);
+ if (err)
+ goto err_clients;
+ }
+
at24->macc.read = at24_macc_read;
writable = !(chip.flags & AT24_FLAG_READONLY);
@@ -757,6 +791,8 @@ static int at24_remove(struct i2c_client *client)
at24 = i2c_get_clientdata(client);
sysfs_remove_bin_file(&client->dev.kobj, &at24->bin);
+ if (at24->bin_serial)
+ sysfs_remove_bin_file(&client->dev.kobj, at24->bin_serial);
for (i = 1; i < at24->num_addresses; i++)
i2c_unregister_device(at24->client[i]);
--
2.1.4
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[RESEND PATCH v2 1/9] eeprom: at24: platform_data: use BIT() macro
Use BIT() macro to replace the 0xXX constants in platform_data flags
definitions.
Signed-off-by: Bartosz Golaszewski
---
include/linux/platform_data/at24.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/platform_data/at24.h
b/include/linux/platform_data/at24.h
index c42aa89..8d90f52 100644
--- a/include/linux/platform_data/at24.h
+++ b/include/linux/platform_data/at24.h
@@ -43,10 +43,10 @@ struct at24_platform_data {
u32 byte_len; /* size (sum of all addr) */
u16 page_size; /* for writes */
u8 flags;
-#define AT24_FLAG_ADDR16 0x80/* address pointer is 16 bit */
-#define AT24_FLAG_READONLY 0x40/* sysfs-entry will be read-only */
-#define AT24_FLAG_IRUGO0x20/* sysfs-entry will be
world-readable */
-#define AT24_FLAG_TAKE8ADDR0x10/* take always 8 addresses (24c00) */
+#define AT24_FLAG_ADDR16 BIT(7) /* address pointer is 16 bit */
+#define AT24_FLAG_READONLY BIT(6) /* sysfs-entry will be read-only */
+#define AT24_FLAG_IRUGOBIT(5) /* sysfs-entry will be
world-readable */
+#define AT24_FLAG_TAKE8ADDRBIT(4) /* take always 8 addresses (24c00) */
void(*setup)(struct memory_accessor *, void *context);
void*context;
--
2.1.4
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[RESEND PATCH v2 7/9] eeprom: at24: add the at24cs series to the list of supported devices
The infrastructure for reading of the factory-programmed serial number
for at24cs EEPROM series is now in place. Add the chips that are actually
equipped with the serial number memory area to the list of supported
devices.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index d474b6d..6e28b02 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -117,16 +117,25 @@ static const struct i2c_device_id at24_ids[] = {
{ "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
/* old variants can't be handled with this generic entry! */
{ "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
+ { "24cs01", AT24_DEVICE_MAGIC(1024 / 8, AT24_FLAG_SERIAL) },
{ "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
+ { "24cs02", AT24_DEVICE_MAGIC(2048 / 8, AT24_FLAG_SERIAL) },
/* spd is a 24c02 in memory DIMMs */
{ "spd",AT24_DEVICE_MAGIC(2048 / 8,
AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
{ "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
+ { "24cs04", AT24_DEVICE_MAGIC(4096 / 8, AT24_FLAG_SERIAL) },
/* 24rf08 quirk is handled at i2c-core */
{ "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
+ { "24cs08", AT24_DEVICE_MAGIC(8192 / 8, AT24_FLAG_SERIAL) },
{ "24c16", AT24_DEVICE_MAGIC(16384 / 8,0) },
+ { "24cs16", AT24_DEVICE_MAGIC(16384 / 8,AT24_FLAG_SERIAL) },
{ "24c32", AT24_DEVICE_MAGIC(32768 / 8,AT24_FLAG_ADDR16) },
+ { "24cs32", AT24_DEVICE_MAGIC(32768 / 8,
+ AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL) },
{ "24c64", AT24_DEVICE_MAGIC(65536 / 8,AT24_FLAG_ADDR16) },
+ { "24cs64", AT24_DEVICE_MAGIC(65536 / 8,
+ AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL) },
{ "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
{ "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
{ "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
--
2.1.4
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[RESEND PATCH v2 9/9] eeprom: at24: readability tweaks
Move the macro definitions above the struct definitions and add some
tabs for better readability.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 1288193..3238bf6 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -53,6 +53,14 @@
* which won't work on pure SMBus systems.
*/
+#define AT24_SIZE_BYTELEN 5
+#define AT24_SIZE_FLAGS8
+
+#define AT24_BITMASK(x)(BIT(x) - 1)
+
+#define AT24CS_SERIAL_SIZE 16
+#define AT24CS_SERIAL_ADDR(addr) (addr + 0x08)
+
struct at24_data {
struct at24_platform_data chip;
struct memory_accessor macc;
@@ -99,14 +107,6 @@ static unsigned write_timeout = 25;
module_param(write_timeout, uint, 0);
MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)");
-#define AT24_SIZE_BYTELEN 5
-#define AT24_SIZE_FLAGS 8
-
-#define AT24_BITMASK(x) (BIT(x) - 1)
-
-#define AT24CS_SERIAL_SIZE 16
-#define AT24CS_SERIAL_ADDR(addr) (addr + 0x08)
-
/* create non-zero magic value for given eeprom parameters */
#define AT24_DEVICE_MAGIC(_len, _flags)\
((1 << AT24_SIZE_FLAGS | (_flags)) \
--
2.1.4
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[RESEND PATCH v2 8/9] eeprom: at24: remove a reduntant if
It seems as if the second check for I2C_FUNC_I2C functionality had been
introduced accidentally during a merge. Tt's reduntant, so remove it.
Signed-off-by: Bartosz Golaszewski
---
drivers/misc/eeprom/at24.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 6e28b02..1288193 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -634,10 +634,7 @@ static int at24_probe(struct i2c_client *client, const
struct i2c_device_id *id)
} else {
return -EPFNOSUPPORT;
}
- }
- /* Use I2C operations unless we're stuck with SMBus extensions. */
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
if (i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
use_smbus_write = I2C_SMBUS_I2C_BLOCK_DATA;
--
2.1.4
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