[MeeGo-Dev][PATCH v2] Topcliff: Update PCH_I2C driver to 2.6.35
I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake Reviewed-by: Linus Walleij --- drivers/i2c/busses/Kconfig |8 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 908 ++ 3 files changed, 917 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..b7b132d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,14 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..37491d7 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,908 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#define PCH_I2CESRMSK 0x40/* EEPROM software reset mode */ +#define PCH_I2CESRSTA 0x44/* EEPROM software reset mode status register */ +#define PCH_I2CTMR 0x48/* I2C timer register */ +#define PCH_I2CSRST0xFC/* I2C reset register */ +#define PCH_I2CNF 0xF8/* I2C noise filter register */ + +#define BUS_IDLE_TIMEOUT 20 +#define PCH_I2CCTL_I2CMEN 0x0080 +#define TEN_BIT_ADDR_DEFAULT 0xF000 +#define TEN_BIT_ADDR_MASK 0xF0 +#define PCH_START 0x0020 +#define PCH_ESR_START 0x0001 +#define PCH_BUFF_START 0x1 +#define PCH_REPSTART
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
Hi Alan and Wolfram Sang Sorry, previous patch is invalid patch. Please refer this patch. Thanks, Ohtake (OKISemi) --- I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake Reviewed-by: Linus Walleij --- drivers/i2c/busses/Kconfig |8 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 923 ++ 3 files changed, 932 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..b7b132d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,14 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..abaef96 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,923 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#define PCH_I2CESRMSK 0x40/* EEPROM software reset mode */ +#define PCH_I2CESRSTA 0x44/* EEPROM software reset mode status register */ +#define PCH_I2CTMR 0x48/* I2C timer register */ +#define PCH_I2CSRST0xFC/* I2C reset register */ +#define PCH_I2CNF 0xF8/* I2C noise filter register */ + +#define BUS_IDLE_TIMEOUT 20 +#define PCH_I2CCTL_I2CMEN 0x0080 +#define TEN_BIT_ADDR_DEFAULT 0xF000 +#define TEN_BIT_ADDR_MASK 0xF0 +#define PCH_
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
Hi Alan and Wolfram Sang We have updated for your indications. Please confirm below. Thanks, Ohtake (OKISemi) --- I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake Reviewed-by: Linus Walleij Signed-off-by: Masayuki Ohtake --- drivers/i2c/busses/Kconfig |8 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 929 ++ 3 files changed, 938 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..b7b132d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,14 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..749fcd2 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,929 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#define PCH_I2CESRMSK 0x40/* EEPROM software reset mode */ +#define PCH_I2CESRSTA 0x44/* EEPROM software reset mode status register */ +#define PCH_I2CTMR 0x48/* I2C timer register */ +#define PCH_I2CSRST0xFC/* I2C reset register */ +#define PCH_I2CNF 0xF8/* I2C noise filter register */ + +#define BUS_IDLE_TIMEOUT 20 +#define PCH_I2CCTL_I2CMEN 0x0080 +#define TEN_BIT_ADDR_DEFAULT 0xF000 +#define TEN_BIT_ADDR_
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake Reviewed-by: Linus Walleij --- drivers/i2c/busses/Kconfig | 18 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 944 ++ 3 files changed, 963 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..c5db1e7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,24 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + +config PCH_I2C_CH_COUNT + int "PCH I2C the number of channel count" + range 1 2 + depends on PCH_I2C + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + The number of I2C buses/channels supported by the PCH I2C controller. + PCH I2C of Topcliff supports only one channel. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..ae55a83 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,944 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_MAX_CHNCONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels + available */ +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#define PCH_I2CESRMSK 0x40/* EEPROM software reset
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
Hi Joe, We have updated for your comments. Please confirm below. Thanks, Ohtake(OKISemi) --- I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake --- drivers/i2c/busses/Kconfig | 18 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 943 ++ 3 files changed, 962 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..c5db1e7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,24 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + +config PCH_I2C_CH_COUNT + int "PCH I2C the number of channel count" + range 1 2 + depends on PCH_I2C + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + The number of I2C buses/channels supported by the PCH I2C controller. + PCH I2C of Topcliff supports only one channel. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..f3840bd --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,943 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_MAX_CHNCONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels + available */ +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl re
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
Hi Linus Walleij We have updated for your comments. Please confirm below. --- I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake --- drivers/i2c/busses/Kconfig | 18 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 951 ++ 3 files changed, 970 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..c5db1e7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,24 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + +config PCH_I2C_CH_COUNT + int "PCH I2C the number of channel count" + range 1 2 + depends on PCH_I2C + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + The number of I2C buses/channels supported by the PCH I2C controller. + PCH I2C of Topcliff supports only one channel. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..0933e63 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,951 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_MAX_CHNCONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels + available */ +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#def
[MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
I2C driver of Topcliff PCH Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. Topcliff PCH has I2C I/F. Using this I/F, it is able to access system devices connected to I2C. Signed-off-by: Masayuki Ohtake --- drivers/i2c/busses/Kconfig | 18 + drivers/i2c/busses/Makefile |1 + drivers/i2c/busses/i2c-pch.c | 966 ++ 3 files changed, 985 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/busses/i2c-pch.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbf..c5db1e7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -613,6 +613,24 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config PCH_I2C + tristate "PCH I2C of Intel Topcliff" + depends on PCI + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + This driver can access PCH I2C bus device. + +config PCH_I2C_CH_COUNT + int "PCH I2C the number of channel count" + range 1 2 + depends on PCH_I2C + help + This driver is for PCH(Platform controller Hub) I2C of Topcliff which + is an IOH(Input/Output Hub) for x86 embedded processor. + The number of I2C buses/channels supported by the PCH I2C controller. + PCH I2C of Topcliff supports only one channel. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880b..aa04135 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o +obj-$(CONFIG_PCH_I2C) += i2c-pch.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c new file mode 100644 index 000..fc1b6a0 --- /dev/null +++ b/drivers/i2c/busses/i2c-pch.c @@ -0,0 +1,966 @@ +/* + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_MAX_CHNCONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels + available */ +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ +#define PCH_MAX_CLK10 /* Maximum Clock speed in MHz */ +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ + +#define PCH_I2CSADR0x00/* I2C slave address register */ +#define PCH_I2CCTL 0x04/* I2C control register */ +#define PCH_I2CSR 0x08/* I2C status register */ +#define PCH_I2CDR 0x0C/* I2C data register */ +#define PCH_I2CMON 0x10/* I2C bus monitor register */ +#define PCH_I2CBC 0x14/* I2C bus transfer rate setup counter */ +#define PCH_I2CMOD 0x18/* I2C mode register */ +#define PCH_I2CBUFSLV 0x1C/* I2C buffer mode slave address register */ +#define PCH_I2CBUFSUB 0x20/* I2C buffer mode subaddress register */ +#define PCH_I2CBUFFOR 0x24/* I2C buffer mode format register */ +#define PCH_I2CBUFCTL 0x28/* I2C buffer mode control register */ +#define PCH_I2CBUFMSK 0x2C/* I2C buffer mode interrupt mask register */ +#define PCH_I2CBUFSTA 0x30/* I2C buffer mode status register */ +#define PCH_I2CBUFLEV 0x34/* I2C buffer mode level register */ +#define PCH_I2CESRFOR 0x38/* EEPROM software reset mode format register */ +#define PCH_I2CESRCTL 0x3C/* EEPROM software reset mode ctrl register */ +#define PCH_I2CESRMSK 0x40/* EEPROM software reset mode */ +#define PCH_I2CESR
[PATCH] I2C driver of Topcliff PCH
Hi Arnd,
I have modified for your comments.
Please confirm below.
Thanks, Ohtake
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake
---
drivers/i2c/busses/Kconfig |8 +
drivers/i2c/busses/Makefile |3 +
drivers/i2c/busses/i2c-pch.c | 910 ++
drivers/i2c/busses/i2c-pch.h | 147 +++
drivers/i2c/i2c-dev.c| 21 +
5 files changed, 1089 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
create mode 100644 drivers/i2c/busses/i2c-pch.h
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5f318ce..98e7201 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -7,6 +7,14 @@ menu "I2C Hardware Bus support"
comment "PC SMBus host controller drivers"
depends on PCI
+config PCH_I2C
+ tristate "PCH I2C"
+ depends on PCI
+ help
+ This driver is for PCH I2C of Topcliff which is an IOH for x86
+ embedded processor.
+ This driver can access PCH I2C bus device.
+
config I2C_ALI1535
tristate "ALI 1535"
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 302c551..3e6b8d6 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -75,3 +75,6 @@ obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
EXTRA_CFLAGS += -DDEBUG
endif
+
+obj-$(CONFIG_PCH_I2C) += pch_i2c.o
+pch_i2c-objs := i2c-pch.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 000..7939781
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,910 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i2c-pch.h"
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 5;/* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) | (bitmask)), (addr + offset));
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) & (~(bitmask))), (addr + offset));
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Cleared the registers PCH_I2CCTL,PCH_I2CMOD,PCH_I2CBUFFOR\n,"
+ "PCH_I2CBUFSLV,PCH_I2CBUFSUB,PCH_I2CBUFMSK,\n"
+ "PCH_I2CESRFOR,PCH_I2CESRMSK\n");
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+
[PATCH] I2C driver of Topcliff PCH
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake
---
drivers/i2c/busses/Kconfig |8 +
drivers/i2c/busses/Makefile |3 +
drivers/i2c/busses/i2c-pch.c | 1390 ++
drivers/i2c/busses/i2c-pch.h | 147 +
drivers/i2c/i2c-dev.c| 28 +
5 files changed, 1576 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
create mode 100644 drivers/i2c/busses/i2c-pch.h
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..578fd42 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -7,6 +7,14 @@ menu "I2C Hardware Bus support"
comment "PC SMBus host controller drivers"
depends on PCI
+config PCH_I2C
+ tristate "PCH I2C"
+ depends on PCI
+ help
+ This driver is for PCH I2C of Topcliff which is an IOH for x86
+ embedded processor.
+ This driver can access PCH I2C bus device.
+
config I2C_ALI1535
tristate "ALI 1535"
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..53be4b3 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -78,3 +78,6 @@ obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
EXTRA_CFLAGS += -DDEBUG
endif
+
+obj-$(CONFIG_PCH_I2C) += pch_i2c.o
+pch_i2c-objs := i2c-pch.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 000..58824cc
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i2c-pch.h"
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 5;/* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static s32(*pch_cbr) (struct i2c_algo_pch_data *);
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) | (bitmask)), (addr + offset));
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) & (~(bitmask))), (addr + offset));
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Cleared the registers PCH_I2CCTL,PCH_I2CMOD,PCH_I2CBUFFOR\n,"
+ "PCH_I2CBUFSLV,PCH_I2CBUFSUB,PCH_I2CBUFMSK,\n"
+ "PCH_I2CESRFOR,PCH_I2CESRMSK\n");
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ dev_dbg(adap->pch_adapter.dev.parent, "Fast
