Hi I2C maintainer,
I posted the i2c patch 1 month ago.
But I haven't received any response from you.
Could you review this patch ?
Thanks, Ohtake(OKISemi)
- Original Message -
From: Masayuki Ohtak masa-k...@dsn.okisemi.com
To: Jean Delvare (PC drivers, core) kh...@linux-fr.org; Ben Dooks
(embedded platforms) ben-li...@fluff.org;
Crane Cai crane@amd.com; Samuel Ortiz sa...@linux.intel.com; Linus
Walleij linus.wall...@stericsson.com;
Ralf Baechle r...@linux-mips.org; srinidhi kasagar
srinidhi.kasa...@stericsson.com; linux-i2c@vger.kernel.org;
linux-ker...@vger.kernel.org; j...@perches.com; Linus Walleij
linus.wall...@stericsson.com; Wolfram Sang
w.s...@pengutronix.de; Alan Cox a...@lxorguk.ukuu.org.uk
Cc: yong.y.w...@intel.com; qi.w...@intel.com;
andrew.chih.howe.k...@intel.com; ar...@linux.intel.com; Tomoya
MORINAGA morinaga...@dsn.okisemi.com; Arnd Bergmann a...@arndb.de;
Masayuki Ohtake masa-k...@dsn.okisemi.com
Sent: Thursday, September 16, 2010 5:33 PM
Subject: [MeeGo-Dev][PATCH v2] Topcliff: Update PCH_I2C driver to 2.6.35
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake masa-k...@dsn.okisemi.com
Reviewed-by: Linus Walleij linus.wall...@stericsson.com
---
drivers/i2c/busses/Kconfig |8 +
drivers/i2c/busses/Makefile |1 +
drivers/i2c/busses/i2c-pch.c | 908
++
3 files changed, 917 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..b7b132d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate PCH I2C of Intel Topcliff
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
comment External I2C/SMBus adapter drivers
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 000..37491d7
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,908 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include linux/module.h
+#include linux/kernel.h
+#include linux/delay.h
+#include linux/init.h
+#include linux/errno.h
+#include linux/i2c.h
+#include linux/fs.h
+#include linux/io.h
+#include linux/types.h
+#include linux/interrupt.h
+#include linux/jiffies.h
+#include linux/pci.h
+#include linux/mutex.h
+#include linux/ktime.h
+
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 10 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave
