Re: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
> > > +#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | > > \ > > > + I2C_FUNC_SMBUS_BYTE | > > \ > > > + I2C_FUNC_SMBUS_BYTE_DATA | > > \ > > > + I2C_FUNC_SMBUS_WORD_DATA | > > \ > > > + I2C_FUNC_SMBUS_I2C_BLOCK) > > > > Can't we have I2C_FUNC_SMBUS_EMUL here? (Need checking with > > I2C_SMBUS_QUICK) > > Per my understanding, this I2C host is not able to support I2C_SMBUS_QUICK. Ok. Thanks for checking, will apply this patch. signature.asc Description: Digital signature
RE: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Sunday, March 09, 2014 4:54 PM
> To: Chew, Chiau Ee
> Cc: Mika Westerberg; linux-i2c@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode
> functionality for BYT I2C
>
> On Fri, Mar 07, 2014 at 10:12:50PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee
> >
> > All the I2C controllers on Intel BayTrail LPSS subsystem able to
> > support 10-bit addressing mode functionality.
> >
> > Signed-off-by: Chew, Chiau Ee
> > Signed-off-by: Ong, Boon Leong
> > ---
> > drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++--
> > 1 files changed, 11 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > index f1dabee..87f2fc4 100644
> > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > @@ -64,12 +64,19 @@ struct dw_pci_controller {
> > u32 tx_fifo_depth;
> > u32 rx_fifo_depth;
> > u32 clk_khz;
> > + u32 functionality;
> > };
> >
> > #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER |
> \
> > DW_IC_CON_SLAVE_DISABLE | \
> > DW_IC_CON_RESTART_EN)
> >
> > +#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |
> \
> > + I2C_FUNC_SMBUS_BYTE |
> \
> > + I2C_FUNC_SMBUS_BYTE_DATA |
> \
> > + I2C_FUNC_SMBUS_WORD_DATA |
> \
> > + I2C_FUNC_SMBUS_I2C_BLOCK)
>
> Can't we have I2C_FUNC_SMBUS_EMUL here? (Need checking with
> I2C_SMBUS_QUICK)
Per my understanding, this I2C host is not able to support I2C_SMBUS_QUICK.
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Re: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
On Fri, Mar 07, 2014 at 10:12:50PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee
>
> All the I2C controllers on Intel BayTrail LPSS subsystem able
> to support 10-bit addressing mode functionality.
>
> Signed-off-by: Chew, Chiau Ee
> Signed-off-by: Ong, Boon Leong
> ---
> drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++--
> 1 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c
> b/drivers/i2c/busses/i2c-designware-pcidrv.c
> index f1dabee..87f2fc4 100644
> --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> @@ -64,12 +64,19 @@ struct dw_pci_controller {
> u32 tx_fifo_depth;
> u32 rx_fifo_depth;
> u32 clk_khz;
> + u32 functionality;
> };
>
> #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
> DW_IC_CON_SLAVE_DISABLE | \
> DW_IC_CON_RESTART_EN)
>
> +#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
> + I2C_FUNC_SMBUS_BYTE | \
> + I2C_FUNC_SMBUS_BYTE_DATA | \
> + I2C_FUNC_SMBUS_WORD_DATA | \
> + I2C_FUNC_SMBUS_I2C_BLOCK)
Can't we have I2C_FUNC_SMBUS_EMUL here? (Need checking with
I2C_SMBUS_QUICK)
signature.asc
Description: Digital signature
[PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
From: Chew, Chiau Ee
All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.
Signed-off-by: Chew, Chiau Ee
Signed-off-by: Ong, Boon Leong
---
drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++--
1 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c
b/drivers/i2c/busses/i2c-designware-pcidrv.c
index f1dabee..87f2fc4 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -64,12 +64,19 @@ struct dw_pci_controller {
u32 tx_fifo_depth;
u32 rx_fifo_depth;
u32 clk_khz;
+ u32 functionality;
};
#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
DW_IC_CON_SLAVE_DISABLE | \
DW_IC_CON_RESTART_EN)
+#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
+ I2C_FUNC_SMBUS_BYTE | \
+ I2C_FUNC_SMBUS_BYTE_DATA | \
+ I2C_FUNC_SMBUS_WORD_DATA | \
+ I2C_FUNC_SMBUS_I2C_BLOCK)
+
static struct dw_pci_controller dw_pci_controllers[] = {
[moorestown_0] = {
.bus_num = 0,
@@ -140,6 +147,7 @@ static struct dw_pci_controller dw_pci_controllers[] = {
.tx_fifo_depth = 32,
.rx_fifo_depth = 32,
.clk_khz = 10,
+ .functionality = I2C_FUNC_10BIT_ADDR,
},
};
static struct i2c_algorithm i2c_dw_algo = {
@@ -256,12 +264,9 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
dev->base = pcim_iomap_table(pdev)[0];
dev->dev = &pdev->dev;
- dev->functionality =
- I2C_FUNC_I2C |
- I2C_FUNC_SMBUS_BYTE |
- I2C_FUNC_SMBUS_BYTE_DATA |
- I2C_FUNC_SMBUS_WORD_DATA |
- I2C_FUNC_SMBUS_I2C_BLOCK;
+ dev->functionality = controller->functionality |
+ DW_DEFAULT_FUNCTIONALITY;
+
dev->master_cfg = controller->bus_cfg;
pci_set_drvdata(pdev, dev);
--
1.7.4.4
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