FW: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
-Original Message-
From: linux-i2c-ow...@vger.kernel.org [mailto:linux-i2c-ow...@vger.kernel.org]
On Behalf Of Shinya Kuribayashi
Sent: Monday, October 12, 2009 9:48 PM
To: bar...@tkos.co.il; linux-i2c@vger.kernel.org
Cc: ben-li...@fluff.org; linux-m...@linux-mips.org;
linux-arm-ker...@lists.infradead.org
Subject: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
This driver looks originally meant for armel machines where readw()/
writew() works perfectly fine. But that doens't work for big-endian systems.
This patch converts all 8/16-bit-aware usages to 32-bit variants, so that the
driver works for MIPS big-endian machines, too.
Signed-off-by: Shinya Kuribayashi
---
drivers/i2c/busses/i2c-designware.c | 76 +-
1 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware.c
b/drivers/i2c/busses/i2c-designware.c
index b444762..a4f928e 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -162,14 +162,14 @@ struct dw_i2c_dev {
struct i2c_msg *msgs;
int msgs_num;
int msg_write_idx;
- u16 tx_buf_len;
+ u32 tx_buf_len;
u8 *tx_buf;
int msg_read_idx;
- u16 rx_buf_len;
+ u32 rx_buf_len;
u8 *rx_buf;
int msg_err;
unsigned intstatus;
- u16 abort_source;
+ u32 abort_source;
int irq;
struct i2c_adapter adapter;
unsigned inttx_fifo_depth;
@@ -187,25 +187,25 @@ struct dw_i2c_dev { static void i2c_dw_init(struct
dw_i2c_dev *dev) {
u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
- u16 ic_con;
+ u32 ic_con;
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set standard and fast speed deviders for high/low periods */
- writew((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
+ writel((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
dev->base + DW_IC_SS_SCL_HCNT);
- writew((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
+ writel((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
dev->base + DW_IC_SS_SCL_LCNT);
- writew((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
+ writel((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
dev->base + DW_IC_FS_SCL_HCNT);
- writew((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
+ writel((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
dev->base + DW_IC_FS_SCL_LCNT);
/* configure the i2c master */
ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
- writew(ic_con, dev->base + DW_IC_CON);
+ writel(ic_con, dev->base + DW_IC_CON);
}
/*
@@ -215,7 +215,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
{
int timeout = TIMEOUT;
- while (readb(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
+ while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
if (timeout <= 0) {
dev_warn(dev->dev, "timeout waiting for bus ready\n");
return -ETIMEDOUT;
@@ -239,29 +239,29 @@ i2c_dw_xfer_msg(struct i2c_adapter *adap)
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
struct i2c_msg *msgs = dev->msgs;
int num = dev->msgs_num;
- u16 ic_con, intr_mask;
- int tx_limit = dev->tx_fifo_depth - readb(dev->base + DW_IC_TXFLR);
- int rx_limit = dev->rx_fifo_depth - readb(dev->base + DW_IC_RXFLR);
- u16 addr = msgs[dev->msg_write_idx].addr;
- u16 buf_len = dev->tx_buf_len;
+ u32 ic_con, intr_mask;
+ int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
+ int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
+ u32 addr = msgs[dev->msg_write_idx].addr;
+ u32 buf_len = dev->tx_buf_len;
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set the slave (target) address */
- writew(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
+ writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
/* if the slave address is ten bit address, enable 10BITADDR */
-
FW: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
-Original Message-
From: linux-i2c-ow...@vger.kernel.org [mailto:linux-i2c-ow...@vger.kernel.org]
On Behalf Of Shinya Kuribayashi
Sent: Monday, October 12, 2009 9:48 PM
To: bar...@tkos.co.il; linux-i2c@vger.kernel.org
Cc: ben-li...@fluff.org; linux-m...@linux-mips.org;
linux-arm-ker...@lists.infradead.org
Subject: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
This driver looks originally meant for armel machines where readw()/
writew() works perfectly fine. But that doens't work for big-endian systems.
This patch converts all 8/16-bit-aware usages to 32-bit variants, so that the
driver works for MIPS big-endian machines, too.
Signed-off-by: Shinya Kuribayashi
---
drivers/i2c/busses/i2c-designware.c | 76 +-
1 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware.c
b/drivers/i2c/busses/i2c-designware.c
index b444762..a4f928e 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -162,14 +162,14 @@ struct dw_i2c_dev {
struct i2c_msg *msgs;
int msgs_num;
int msg_write_idx;
- u16 tx_buf_len;
+ u32 tx_buf_len;
u8 *tx_buf;
int msg_read_idx;
- u16 rx_buf_len;
+ u32 rx_buf_len;
u8 *rx_buf;
int msg_err;
unsigned intstatus;
- u16 abort_source;
+ u32 abort_source;
int irq;
struct i2c_adapter adapter;
unsigned inttx_fifo_depth;
@@ -187,25 +187,25 @@ struct dw_i2c_dev { static void i2c_dw_init(struct
dw_i2c_dev *dev) {
u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
- u16 ic_con;
+ u32 ic_con;
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set standard and fast speed deviders for high/low periods */
- writew((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
+ writel((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
dev->base + DW_IC_SS_SCL_HCNT);
- writew((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
+ writel((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
dev->base + DW_IC_SS_SCL_LCNT);
- writew((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
+ writel((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
dev->base + DW_IC_FS_SCL_HCNT);
- writew((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
+ writel((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
dev->base + DW_IC_FS_SCL_LCNT);
/* configure the i2c master */
ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
- writew(ic_con, dev->base + DW_IC_CON);
+ writel(ic_con, dev->base + DW_IC_CON);
}
/*
@@ -215,7 +215,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
{
int timeout = TIMEOUT;
- while (readb(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
+ while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
if (timeout <= 0) {
dev_warn(dev->dev, "timeout waiting for bus ready\n");
return -ETIMEDOUT;
@@ -239,29 +239,29 @@ i2c_dw_xfer_msg(struct i2c_adapter *adap)
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
struct i2c_msg *msgs = dev->msgs;
int num = dev->msgs_num;
- u16 ic_con, intr_mask;
- int tx_limit = dev->tx_fifo_depth - readb(dev->base + DW_IC_TXFLR);
- int rx_limit = dev->rx_fifo_depth - readb(dev->base + DW_IC_RXFLR);
- u16 addr = msgs[dev->msg_write_idx].addr;
- u16 buf_len = dev->tx_buf_len;
+ u32 ic_con, intr_mask;
+ int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
+ int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
+ u32 addr = msgs[dev->msg_write_idx].addr;
+ u32 buf_len = dev->tx_buf_len;
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set the slave (target) address */
- writew(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
+ writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
/* if the slave address is ten bit address, enable 10BITADDR */
-
FW: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
-Original Message-
From: linux-i2c-ow...@vger.kernel.org [mailto:linux-i2c-ow...@vger.kernel.org]
On Behalf Of Shinya Kuribayashi
Sent: Monday, October 12, 2009 9:48 PM
To: bar...@tkos.co.il; linux-i2c@vger.kernel.org
Cc: ben-li...@fluff.org; linux-m...@linux-mips.org;
linux-arm-ker...@lists.infradead.org
Subject: [PATCH 01/16] i2c-designware: Consolidate to use 32-bit word accesses
This driver looks originally meant for armel machines where readw()/
writew() works perfectly fine. But that doens't work for big-endian systems.
This patch converts all 8/16-bit-aware usages to 32-bit variants, so that the
driver works for MIPS big-endian machines, too.
Signed-off-by: Shinya Kuribayashi
---
drivers/i2c/busses/i2c-designware.c | 76 +-
1 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware.c
b/drivers/i2c/busses/i2c-designware.c
index b444762..a4f928e 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -162,14 +162,14 @@ struct dw_i2c_dev {
struct i2c_msg *msgs;
int msgs_num;
int msg_write_idx;
- u16 tx_buf_len;
+ u32 tx_buf_len;
u8 *tx_buf;
int msg_read_idx;
- u16 rx_buf_len;
+ u32 rx_buf_len;
u8 *rx_buf;
int msg_err;
unsigned intstatus;
- u16 abort_source;
+ u32 abort_source;
int irq;
struct i2c_adapter adapter;
unsigned inttx_fifo_depth;
@@ -187,25 +187,25 @@ struct dw_i2c_dev { static void i2c_dw_init(struct
dw_i2c_dev *dev) {
u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
- u16 ic_con;
+ u32 ic_con;
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set standard and fast speed deviders for high/low periods */
- writew((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
+ writel((input_clock_khz * 40 / 1)+1, /* std speed high, 4us */
dev->base + DW_IC_SS_SCL_HCNT);
- writew((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
+ writel((input_clock_khz * 47 / 1)+1, /* std speed low, 4.7us */
dev->base + DW_IC_SS_SCL_LCNT);
- writew((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
+ writel((input_clock_khz * 6 / 1)+1, /* fast speed high, 0.6us */
dev->base + DW_IC_FS_SCL_HCNT);
- writew((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
+ writel((input_clock_khz * 13 / 1)+1, /* fast speed low, 1.3us */
dev->base + DW_IC_FS_SCL_LCNT);
/* configure the i2c master */
ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
- writew(ic_con, dev->base + DW_IC_CON);
+ writel(ic_con, dev->base + DW_IC_CON);
}
/*
@@ -215,7 +215,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
{
int timeout = TIMEOUT;
- while (readb(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
+ while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
if (timeout <= 0) {
dev_warn(dev->dev, "timeout waiting for bus ready\n");
return -ETIMEDOUT;
@@ -239,29 +239,29 @@ i2c_dw_xfer_msg(struct i2c_adapter *adap)
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
struct i2c_msg *msgs = dev->msgs;
int num = dev->msgs_num;
- u16 ic_con, intr_mask;
- int tx_limit = dev->tx_fifo_depth - readb(dev->base + DW_IC_TXFLR);
- int rx_limit = dev->rx_fifo_depth - readb(dev->base + DW_IC_RXFLR);
- u16 addr = msgs[dev->msg_write_idx].addr;
- u16 buf_len = dev->tx_buf_len;
+ u32 ic_con, intr_mask;
+ int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
+ int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
+ u32 addr = msgs[dev->msg_write_idx].addr;
+ u32 buf_len = dev->tx_buf_len;
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
/* Disable the adapter */
- writeb(0, dev->base + DW_IC_ENABLE);
+ writel(0, dev->base + DW_IC_ENABLE);
/* set the slave (target) address */
- writew(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
+ writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
/* if the slave address is ten bit address, enable 10BITADDR */
-
