Re: i2c-davinci.c: CPU FREQ causes lock up due to xfr_complete
On Tuesday 29 July 2014 11:00 PM, Grygorii Strashko wrote:
Hi Jon,
On 07/29/2014 06:53 PM, Jon Cormier wrote:
A slimmer patch suggested by Grygorii Strashko grygorii.stras...@ti.com
Ok. The problem seems to be deeper than at first look.
You have sequence (in Mainline kernel):
cpufreq:
|- notify CPUFREQ_PRECHANGE
|- i2c-davinci will lock put I2C in reset
|- cpufreq_driver-target_index
|- davinci_target()
|- pdata-set_voltage() - It will try to use I2C to set new voltage,
while I2C is in reset or locked! Bug!
|- notify CPUFREQ_POSTCHANGE
|- i2c-davinci will re-enable I2C and adjust I2C clock
Good find. I really wonder how this escaped so far. I can swear cpufreq
transitions were tested multiple times. From the description it looks
like this should hit every single time there is a voltage adjustment.
On DA850 which is the only DaVinci implementing cpufreq, I2C0 input
frequency will remain constant across cpufreq transitions since it
derives from PLL0 AUXCLK which is used pre-multipler/divider. It remains
fixed.
The code seems to have been added for I2C1 which does have a fixed ratio
with cpu clock.
PMIC should usually be put on I2C0 to help prevent these kind of issues.
I see few possible ways to solve it:
1) use CLK notifier instead of CPUfreq notifiers
This will require common clock framework, right? We dont have that on
mach-davinci.
2) do smth similar to 61c7cff8 i2c: S3C24XX I2C frequency scaling support
+ 9bcd04bf i2c: s3c2410: grab adapter lock while changing i2c clock
This looks promising. Although I wonder if delta_f will always remain
zero in s3c24xx_i2c_cpufreq_transition() when the CPUFREQ_PRECHANGE call
is made - because clock tree is not updated yet?
3) update I2C clock in CPUFREQ_POSTCHANGE - may be unsafe
Well, even now the I2C clock is only getting updated in POSTCHANGE,
right? Also, resetting I2C in PRECHANGE seems excessive. It is only
required when changing the prescalar. So you can do:
} else if (val == CPUFREQ_POSTCHANGE) {
davinci_i2c_reset_ctrl(dev, 0);
i2c_davinci_calc_clk_dividers(dev);
davinci_i2c_reset_ctrl(dev, 1);
}
So this along with the i2c_lock_adapter() a la
s3c24xx_i2c_cpufreq_transition() should be the right fix, I guess.
Thanks,
Sekhar
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Re: i2c-davinci.c: CPU FREQ causes lock up due to xfr_complete
On 07/30/2014 09:18 AM, Sekhar Nori wrote:
On Tuesday 29 July 2014 11:00 PM, Grygorii Strashko wrote:
Hi Jon,
On 07/29/2014 06:53 PM, Jon Cormier wrote:
A slimmer patch suggested by Grygorii Strashko grygorii.stras...@ti.com
Ok. The problem seems to be deeper than at first look.
You have sequence (in Mainline kernel):
cpufreq:
|- notify CPUFREQ_PRECHANGE
|- i2c-davinci will lock put I2C in reset
|- cpufreq_driver-target_index
|- davinci_target()
|- pdata-set_voltage() - It will try to use I2C to set new voltage,
while I2C is in reset or locked! Bug!
|- notify CPUFREQ_POSTCHANGE
|- i2c-davinci will re-enable I2C and adjust I2C clock
Good find. I really wonder how this escaped so far. I can swear cpufreq
transitions were tested multiple times. From the description it looks
like this should hit every single time there is a voltage adjustment.
On DA850 which is the only DaVinci implementing cpufreq, I2C0 input
frequency will remain constant across cpufreq transitions since it
derives from PLL0 AUXCLK which is used pre-multipler/divider. It remains
fixed.
The code seems to have been added for I2C1 which does have a fixed ratio
with cpu clock.
PMIC should usually be put on I2C0 to help prevent these kind of issues.
I see few possible ways to solve it:
1) use CLK notifier instead of CPUfreq notifiers
This will require common clock framework, right? We dont have that on
mach-davinci.
:( I've forgotten about that.
2) do smth similar to 61c7cff8 i2c: S3C24XX I2C frequency scaling support
+ 9bcd04bf i2c: s3c2410: grab adapter lock while changing i2c clock
This looks promising. Although I wonder if delta_f will always remain
zero in s3c24xx_i2c_cpufreq_transition() when the CPUFREQ_PRECHANGE call
is made - because clock tree is not updated yet?
That's funny - seems PRE/POST notifiers are called twice for s3c24xx :)
First one from cpufreq core.
Second time from s3c_cpufreq_target() and, looks like, clock
freq will be updated at that time.
3) update I2C clock in CPUFREQ_POSTCHANGE - may be unsafe
Well, even now the I2C clock is only getting updated in POSTCHANGE,
right? Also, resetting I2C in PRECHANGE seems excessive. It is only
required when changing the prescalar. So you can do:
} else if (val == CPUFREQ_POSTCHANGE) {
davinci_i2c_reset_ctrl(dev, 0);
i2c_davinci_calc_clk_dividers(dev);
davinci_i2c_reset_ctrl(dev, 1);
}
So this along with the i2c_lock_adapter() a la
s3c24xx_i2c_cpufreq_transition() should be the right fix, I guess.
Regards,
-grygorii
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Re: i2c-davinci.c: CPU FREQ causes lock up due to xfr_complete
of the i2c bus to communicate with the
PMIC. In this case we dont want the i2c to reset until after we set
the voltage.
Signed-off-by: Cormier, Jonathan jcorm...@criticallink.com
diff --git a/arch/arm/mach-davinci/cpufreq.c
b/arch/arm/mach-davinci/cpufreq.c
index 5bba707..cbaee6c 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -102,8 +102,6 @@ static int davinci_target(struct cpufreq_policy *policy,
if (ret)
return -EINVAL;
-cpufreq_notify_transition(freqs, CPUFREQ_PRECHANGE);
-
/* if moving to higher frequency, up the voltage beforehand */
if (pdata-set_voltage freqs.new freqs.old) {
ret = pdata-set_voltage(idx);
@@ -111,6 +109,8 @@ static int davinci_target(struct cpufreq_policy *policy,
goto out;
}
+cpufreq_notify_transition(freqs, CPUFREQ_PRECHANGE);
+
ret = clk_set_rate(armclk, idx);
if (ret)
goto out;
On Tue, Jul 29, 2014 at 10:38 AM, Brian Niebuhr bnieb...@efji.com wrote:
-Original Message-
From: davinci-linux-open-source-boun...@linux.davincidsp.com
[mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On
Behalf Of Jon Cormier
Sent: Tuesday, July 29, 2014 9:20 AM
To: davinci-linux-open-sou...@linux.davincidsp.com
Cc: Tim Iskander
Subject: i2c-davinci.c: CPU FREQ causes lock up due to xfr_complete
Reported issue:
1. Enable I2C1, flash the new kernel and reboot
2. Immediately after reboot, attempt to change the processor clock: echo
456000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
3. Process blocks
However, if we do the following:
1. Enable I2C1, flash the new kernel and reboot
2. Immediately after reboot, run: i2cdetect -y 2 0x08 0x08 or just
i2cdetect
-y 2
3. Then run: echo 456000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
4. Command succeeds
I found this problem as well, and I haven't had time to put together a
proper patch. Right now we're just working around it. There are several
problems with the use of a completion for this task:
1. If no I2C transfer has occurred, a cpufreq transition will block
forever (which is the bug you found)
2. Once an I2C transfer has occurred the cpufreq transition will never
block since the completion is never reinitialized.
3. Even if you do reinitialize the completion for every I2C transfer, (1)
is not solved and there is still a race condition where the cpufreq
transition could start just before an I2C transfer starts and the I2C
transfer occurs during the cpufreq transition.
Personally I think the correct solution is to use a mutex instead of a
completion. The cpufreq code would take the mutex during the prechange
callback and release it during the postchange callback. Likewise the I2C
transfer function would hold the mutex while an I2C transfer is ongoing.
That way an I2C transfer cannot occur during a cpufreq transition and
vice-versa. As I mentioned, I have not had time to put together a proper
patch, but I would be happy to see this issue addressed if someone else
can do it.
Here's the kernel hung task stack trace:
INFO: task sh:1428 blocked for more than 120 seconds.
echo 0 /proc/sys/kernel/hung_task_timeout_secs disables this message.
sh D c026dc74 0 1428 1426 0x
[c026dc74] (schedule+0x2a8/0x334) from [c026e2e0]
(schedule_timeout+0x1c/0x218)
[c026e2e0] (schedule_timeout+0x1c/0x218) from [c026e164]
(wait_for_common+0xf0/0x1b8)
[c026e164] (wait_for_common+0xf0/0x1b8) from [c019ca1c]
(i2c_davinci_cpufreq_transition+0x18/0x50)
[c019ca1c] (i2c_davinci_cpufreq_transition+0x18/0x50) from [c00599a4]
(notifier_call_chain+0x38/0x68)
[c00599a4] (notifier_call_chain+0x38/0x68) from [c0059a80]
(__srcu_notifier_call_chain+0x40/0x58)
[c0059a80] (__srcu_notifier_call_chain+0x40/0x58) from [c0059aac]
(srcu_notifier_call_chain+0x14/0x18)
[c0059aac] (srcu_notifier_call_chain+0x14/0x18) from [c019dd78]
(cpufreq_notify_transition+0xc8/0xfc)
[c019dd78] (cpufreq_notify_transition+0xc8/0xfc) from [c00373ac]
(davinci_target+0x144/0x154)
[c00373ac] (davinci_target+0x144/0x154) from [c019d404]
(__cpufreq_driver_target+0x28/0x38)
[c019d404] (__cpufreq_driver_target+0x28/0x38) from [c019f260]
(cpufreq_set+0x54/0x70)
[c019f260] (cpufreq_set+0x54/0x70) from [c019d698]
(store_scaling_setspeed+0x58/0x6c)
[c019d698] (store_scaling_setspeed+0x58/0x6c) from [c019e3d0]
(store+0x58/0x74)
[c019e3d0] (store+0x58/0x74) from [c00d8854]
(sysfs_write_file+0x108/0x140)
[c00d8854] (sysfs_write_file+0x108/0x140) from [c009512c]
(vfs_write+0xb0/0x118)
[c009512c] (vfs_write+0xb0/0x118) from [c0095244]
(sys_write+0x3c/0x68)
[c0095244] (sys_write+0x3c/0x68) from [c002bea0]
(ret_fast_syscall+0x0/0x28)
Kernel panic - not syncing: hung_task: blocked tasks
[c003069c] (unwind_backtrace+0x0/0xd0) from [c026d810]
(panic+0x44/0xc8)
[c026d810] (panic+0x44/0xc8) from [c006aa7c] (watchdog+0x1d4
