Re: ICH8 CF timeout (regression)...
On Sat, 04 Aug 2007 15:04:54 +0900 Tejun Heo [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: Tejun, On 03/08/07, Tejun Heo [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: The ICH8 south-bridge I have is the mobile variant and does come equipped with native parallel IDE - see page 447: http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do see 35MB/s with DMA enabled from my CF on the 1 in 15 times the libata-kernel does work. I can dump off and decode the configuration registers for the timing and bus master registers in the working and non-working libata cases, and the legacy ATA working case and see what's different. Does the attached patch change anything? This addresses the issue 100%! Due to the differences between the ICH8 non-mobile and mobile variants, I've cooked the change into a new initialisation structure for the ICH8M in the attached patch, if that helps at all. The changes thus affect (correct) behaviour on the ICH8M in IDE mode only...so should be safe for inclusion. There may be a similar situation with ICH9Ms also. [cc'ing Kristen, hello] I think [P0 P2 IDE IDE] is correct for MAP 01b but can't find anything about it in the datasheet or spec update. Kristen, can you please verify this. The following bug is also fixed by using [P0 P2 IDE IDE]. http://bugzilla.kernel.org/show_bug.cgi?id=8809 Thanks. -- tejun In the data sheet in section 5.15.2.3 it describes a value of map.mv of 1 as meaning that the SATA controller is emulating the logical secondary channel, and the PATA channel will be the primary. For a value of map.mv == 2, we have the SATA controller being primary, and the PATA is secondary. So, if I'm understanding the way ata_piix does mapping, it seems like for a value of 2, we should have [p0, p2, ide, ide] and for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M it seems like 1 should not be a valid value. My reading the ICH8 spec is that ICH8M only implements a map value of 2, and 1 should be reserved (see section 12.1.33). - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ICH8 CF timeout (regression)...
Kristen Carlson Accardi wrote: In the data sheet in section 5.15.2.3 it describes a value of map.mv of 1 as meaning that the SATA controller is emulating the logical secondary channel, and the PATA channel will be the primary. For a value of map.mv == 2, we have the SATA controller being primary, and the PATA is secondary. So, if I'm understanding the way ata_piix does mapping, it seems like for a value of 2, we should have [p0, p2, ide, ide] and for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M it seems like 1 should not be a valid value. My reading the ICH8 spec is that ICH8M only implements a map value of 2, and 1 should be reserved (see section 12.1.33). Alright, thanks a lot. -- tejun - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ICH8 CF timeout (regression)...
Daniel J Blueman wrote: Tejun, On 03/08/07, Tejun Heo [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: The ICH8 south-bridge I have is the mobile variant and does come equipped with native parallel IDE - see page 447: http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do see 35MB/s with DMA enabled from my CF on the 1 in 15 times the libata-kernel does work. I can dump off and decode the configuration registers for the timing and bus master registers in the working and non-working libata cases, and the legacy ATA working case and see what's different. Does the attached patch change anything? This addresses the issue 100%! Due to the differences between the ICH8 non-mobile and mobile variants, I've cooked the change into a new initialisation structure for the ICH8M in the attached patch, if that helps at all. The changes thus affect (correct) behaviour on the ICH8M in IDE mode only...so should be safe for inclusion. There may be a similar situation with ICH9Ms also. [cc'ing Kristen, hello] I think [P0 P2 IDE IDE] is correct for MAP 01b but can't find anything about it in the datasheet or spec update. Kristen, can you please verify this. The following bug is also fixed by using [P0 P2 IDE IDE]. http://bugzilla.kernel.org/show_bug.cgi?id=8809 Thanks. -- tejun - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ICH8 CF timeout (regression)...
On 02/08/07, Mark Lord [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: On 02/08/07, Tejun Heo [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: I'll grab kernel logs from the legacy ATA boot; what else can help debug this issue? No problem testing patches too. Yeap, please post the old log. Not much actually - perhaps I need to enable some debugging: Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx hdc: SanDisk SDCFX-4096, CFA DISK drive ide1 at 0x170-0x177,0x376 on irq 15 hdc: max request size: 128KiB hdc: 8027712 sectors (4110 MB) w/1KiB Cache, CHS=7964/16/63 hdc: hdc1 hdc2 hdc3 --- [2] ata2.00: limiting speed to UDMA/33:PIO4 ata2.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen ata2.00: cmd c8/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 in res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) ata2: soft resetting port ata2.00: configured for UDMA/33 ata2: EH complete What happens after this? More EH occurs - I've left it for ~5 mins, but let me know if longer would give more information, eg if it converges on a lower speed. Would it be useful to compare some of the port setup registers in the working and non-working cases? Or any other debug I can grab? I'm betting that this is the exact same problem we recently debugged for someone else here: there's a Marvell PATA-SATA bridge chip between that CF card and the SATA controller, and it only works with PIO modes. Tejun.. perhaps (for debugging) a simple patch to disallow DMA completely, just to see if PIO works? The ICH8 south-bridge I have is the mobile variant and does come equipped with native parallel IDE - see page 447: http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do see 35MB/s with DMA enabled from my CF on the 1 in 15 times the libata-kernel does work. I can dump off and decode the configuration registers for the timing and bus master registers in the working and non-working libata cases, and the legacy ATA working case and see what's different. Dan -- Daniel J Blueman - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ICH8 CF timeout (regression)...
Tejun,
On 03/08/07, Tejun Heo [EMAIL PROTECTED] wrote:
Daniel J Blueman wrote:
The ICH8 south-bridge I have is the mobile variant and does come
equipped with native parallel IDE - see page 447:
http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
libata-kernel does work.
I can dump off and decode the configuration registers for the timing
and bus master registers in the working and non-working libata cases,
and the legacy ATA working case and see what's different.
Does the attached patch change anything?
This addresses the issue 100%!
Due to the differences between the ICH8 non-mobile and mobile
variants, I've cooked the change into a new initialisation structure
for the ICH8M in the attached patch, if that helps at all.
The changes thus affect (correct) behaviour on the ICH8M in IDE mode
only...so should be safe for inclusion. There may be a similar
situation with ICH9Ms also.
Thanks once again to all who helped!
Daniel
--
Daniel J Blueman
diff -urN linux-2.6.23-rc1.orig/drivers/ata/ata_piix.c linux-2.6.23-rc1/drivers/ata/ata_piix.c
--- linux-2.6.23-rc1.orig/drivers/ata/ata_piix.c 2007-08-03 21:29:02.0 +0100
+++ linux-2.6.23-rc1/drivers/ata/ata_piix.c 2007-08-03 21:24:53.0 +0100
@@ -128,7 +128,8 @@
ich6_sata_ahci = 7,
ich6m_sata_ahci = 8,
ich8_sata_ahci = 9,
- piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
+ ich8m_sata_ahci = 10,
+ piix_pata_mwdma = 11, /* PIIX3 MWDMA only */
/* constants for mapping table */
P0 = 0, /* port 0 */
@@ -232,7 +233,7 @@
/* SATA Controller 2 IDE (ICH8) */
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* Mobile SATA Controller IDE (ICH8M) */
- { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
+ { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8m_sata_ahci },
/* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller IDE (ICH9) */
@@ -428,7 +429,19 @@
/* PM PS SM SS MAP */
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
{ RV, RV, RV, RV },
- { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
+ { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
+ { RV, RV, RV, RV },
+ },
+};
+
+static const struct piix_map_db ich8m_map_db = {
+ .mask = 0x3,
+ .port_enable = 0x3,
+ .map = {
+ /* PM PS SM SS MAP */
+ { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
+ { RV, RV, RV, RV },
+ { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
{ RV, RV, RV, RV },
},
};
@@ -439,6 +452,7 @@
[ich6_sata_ahci] = ich6_map_db,
[ich6m_sata_ahci] = ich6m_map_db,
[ich8_sata_ahci] = ich8_map_db,
+ [ich8m_sata_ahci] = ich8m_map_db,
};
static struct ata_port_info piix_port_info[] = {
@@ -544,7 +558,18 @@
.port_ops = piix_sata_ops,
},
- /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
+ /* ich8m_sata_ahci: 10 */
+ {
+ .sht = piix_sht,
+ .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
+ PIIX_FLAG_AHCI,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA6,
+ .port_ops = piix_sata_ops,
+ },
+
+ /* piix_pata_mwdma: 11: PIIX3 MWDMA only */
{
.sht = piix_sht,
.flags = PIIX_PATA_FLAGS,
Re: ICH8 CF timeout (regression)...
Daniel J Blueman wrote: I'll grab kernel logs from the legacy ATA boot; what else can help debug this issue? No problem testing patches too. Yeap, please post the old log. --- [2] ata2.00: limiting speed to UDMA/33:PIO4 ata2.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen ata2.00: cmd c8/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 in res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) ata2: soft resetting port ata2.00: configured for UDMA/33 ata2: EH complete What happens after this? -- tejun - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ICH8 CF timeout (regression)...
On 02/08/07, Tejun Heo [EMAIL PROTECTED] wrote: Daniel J Blueman wrote: I'll grab kernel logs from the legacy ATA boot; what else can help debug this issue? No problem testing patches too. Yeap, please post the old log. Not much actually - perhaps I need to enable some debugging: Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx hdc: SanDisk SDCFX-4096, CFA DISK drive ide1 at 0x170-0x177,0x376 on irq 15 hdc: max request size: 128KiB hdc: 8027712 sectors (4110 MB) w/1KiB Cache, CHS=7964/16/63 hdc: hdc1 hdc2 hdc3 --- [2] ata2.00: limiting speed to UDMA/33:PIO4 ata2.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen ata2.00: cmd c8/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 in res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) ata2: soft resetting port ata2.00: configured for UDMA/33 ata2: EH complete What happens after this? More EH occurs - I've left it for ~5 mins, but let me know if longer would give more information, eg if it converges on a lower speed. Would it be useful to compare some of the port setup registers in the working and non-working cases? Or any other debug I can grab? -- Daniel J Blueman - To unsubscribe from this list: send the line unsubscribe linux-ide in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
