Re: Issues with SIS 964 chipset on SATA

2005-02-17 Thread Jeff Garzik
Gary Poppitz wrote:
We tracked down a problem with the 964 chipset with a 0x180 ID code that 
may save someone on the list some time.

The chip will only transfer multiples of 4 bytes. Anything else will 
cause it to hang.

After further research, this is popping up on a number of chips (and 
worked around in several vendor drivers).

It looks like I will need to do a workaround for all SATA ATAPI devices: 
 if the transfer is not a multiple of 4 bytes, pad it with an DMA 1-3 
byte DMA segment.

Jeff
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Re: Issues with SIS 964 chipset on SATA

2005-02-17 Thread Jeff Garzik
Mark Lord wrote:
Jens Axboe wrote:

It looks like I will need to do a workaround for all SATA ATAPI 
devices: if the transfer is not a multiple of 4 bytes, pad it with an 
DMA 1-3 byte DMA segment.

Yup, that requirement has existed on most of the hardware
I've done drivers for, both SATA and a lot of PATA chips too.
PATA too?  Interesting...
Jeff

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Re: Issues with SIS 964 chipset on SATA

2005-02-17 Thread Jeff Garzik
Jens Axboe wrote:
On Thu, Feb 17 2005, Jeff Garzik wrote:
It looks like I will need to do a workaround for all SATA ATAPI devices: 
if the transfer is not a multiple of 4 bytes, pad it with an DMA 1-3 
byte DMA segment.

Yeah we definitely need something like that. The optimal solution is to
make sure that all requests are fed through the bounce logic like fs
requests.

Could you elaborate?  I'm not sure I follow.
I hope you're not suggesting leaking 1-3 bytes of random memory, past 
the end of the request, into the DMA stream?

Jeff
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Re: Issues with SIS 964 chipset on SATA

2005-02-07 Thread Jeff Garzik
Gary Poppitz wrote:
We tracked down a problem with the 964 chipset with a 0x180 ID code that 
may save someone on the list some time.

The chip will only transfer multiples of 4 bytes. Anything else will 
cause it to hang.
Interesting, either ULi or SiS set me a needs-to-be-cleaned-up-a-lot fix 
for this.

SATA transport is dword-based, so this is not surprising.
For the SIS (or ULi, I forget) controller, and perhaps others, a 
workaround needs to be applied.  Suggestions/patches welcome.

We may want to guarantee _DMA_ of 4-byte-aligned chunks, but still only 
reflect the true amount in ATAPI CDB.

Jeff
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