[PATCH 16/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 523 +++
2 files changed, 1221 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
+ "gpz0-4", "gpz0-5", "gpz0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_cpif {
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_ese {
+ gpj2: gpj2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_finger {
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = "gpd5-3", "gpd5-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+};
+
+&pinctrl_fsys {
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpr0: gpr0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #in
[PATCH 03/19] clk: samsung: exynos5433: Add clocks using common clock framework
This patch adds the support for CMU (Clock Management Units) of Exynos5433 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks for kernel boot as following: - PLL/MMC/UART/MCT/I2C/SPI Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Acked-by: Inki Dae Acked-by: Geunsik Lim --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 971 + include/dt-bindings/clock/exynos5433.h | 200 +++ 3 files changed, 1172 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5433.c create mode 100644 include/dt-bindings/clock/exynos5433.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 04acd70..9e8bd83 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c new file mode 100644 index 000..25b447a --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Chanwoo Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5443 SoC. + */ + +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +/* + * Register offset definitions for CMU_TOP + */ +#define ISP_PLL_LOCK 0x +#define AUD_PLL_LOCK 0x0004 +#define ISP_PLL_CON0 0x0100 +#define ISP_PLL_CON1 0x0104 +#define ISP_PLL_FREQ_DET 0x0108 +#define AUD_PLL_CON0 0x0110 +#define AUD_PLL_CON1 0x0114 +#define AUD_PLL_CON2 0x0118 +#define AUD_PLL_FREQ_DET 0x011c +#define MUX_SEL_TOP0 0x0200 +#define MUX_SEL_TOP1 0x0204 +#define MUX_SEL_TOP2 0x0208 +#define MUX_SEL_TOP3 0x020c +#define MUX_SEL_TOP4 0x0210 +#define MUX_SEL_TOP_MSCL 0x0220 +#define MUX_SEL_TOP_CAM1 0x0224 +#defineMUX_SEL_TOP_DISP0x0228 +#define MUX_SEL_TOP_FSYS0 0x0230 +#define MUX_SEL_TOP_FSYS1 0x0234 +#define MUX_SEL_TOP_PERIC0 0x0238 +#define MUX_SEL_TOP_PERIC1 0x023c +#define MUX_ENABLE_TOP00x0300 +#define MUX_ENABLE_TOP10x0304 +#define MUX_ENABLE_TOP20x0308 +#define MUX_ENABLE_TOP30x030c +#define MUX_ENABLE_TOP40x0310 +#define MUX_ENABLE_TOP_MSCL0x0320 +#define MUX_ENABLE_TOP_CAM10x0324 +#define MUX_ENABLE_TOP_DISP0x0328 +#define MUX_ENABLE_TOP_FSYS0 0x0330 +#define MUX_ENABLE_TOP_FSYS1 0x0334 +#define MUX_ENABLE_TOP_PERIC0 0x0338 +#define MUX_ENABLE_TOP_PERIC1 0x033c +#define MUX_STAT_TOP0 0x0400 +#define MUX_STAT_TOP1 0x0404 +#define MUX_STAT_TOP2 0x0408 +#define MUX_STAT_TOP3 0x040c +#define MUX_STAT_TOP4 0x0410 +#define MUX_STAT_TOP_MSCL 0x0420 +#define MUX_STAT_TOP_CAM1 0x0424 +#define MUX_STAT_TOP_FSYS0 0x0430 +#define MUX_STAT_TOP_FSYS1 0x0434 +#define MUX_STAT_TOP_PERIC00x0438 +#define MUX_STAT_TOP_PERIC10x043c +#define DIV_TOP0 0x0600 +#define DIV_TOP1 0x0604 +#define DIV_TOP2 0x0608 +#define DIV_TOP3 0x060c +#define DIV_TOP4 0x0610 +#define DIV_TOP_MSCL 0x0618 +#define DIV_TOP_CAM10 0x061c +#define DIV_TOP_CAM11 0x0620 +#define DIV_TOP_FSYS0 0x062c +#define DIV_TOP_FSYS1 0x0630 +#define DIV_TOP_FSYS2 0x0634 +#define DIV_TOP_PERIC0 0x0638 +#define DIV_TOP_PERIC1 0x063c +#define DIV_TOP_PERIC2 0x0640 +#define DIV_TOP_PERIC3 0x0644 +#define DIV_TOP_PERIC4 0x0648 +#define DIV_TOP_PLL_FREQ_DET 0x064c +#define DIV_STAT_TOP0 0x0700 +#define DIV_STAT_TOP1 0x0704 +#define DIV
[PATCH 01/19] pinctrl: exynos: Add support for Exynos5433
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc: Linus Walleij
Signed-off-by: Chanwoo Choi
Acked-by: Geunsik Lim
Acked-by: Inki Dae
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 166 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 8e3e0c0..bd4c4ec 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1268,6 +1268,169 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos5433_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static struct samsung_pin_bank exynos5433_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static struct samsung_pin_bank exynos5433_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static struct samsung_pin_bank exynos5433_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static struct samsung_pin_bank exynos5433_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static struct samsung_pin_bank exynos5433_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static struct samsung_pin_bank exynos5433_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static struct samsung_pin_bank exynos5433_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static struct samsung_pin_bank exynos5433_pin_banks8[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
+ EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
+ EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
+ EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos5433_pin_banks9[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5433_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctr
[PATCH 04/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 89 ++
include/dt-bindings/clock/exynos5433.h | 31 +++-
2 files changed, 118 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 25b447a..e0d71fd 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { "fin_pll", "sclk_mphy_pll",
};
PNAME(mout_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll", };
PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
PNAME(mout_bus_pll_user_t_p) = { "fin_pll", "mout_bus_pll_user", };
+PNAME(mout_mphy_pll_user_t_p) = { "fin_pll", "mout_mphy_pll_user", };
PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = {
"mout_aclk_cam1_552_a",
"mout_mfc_pll_user", };
PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
+ "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
+
PNAME(mout_bus_mphy_pll_user_p)= { "mout_bus_pll_user",
"mout_mphy_pll_user", };
PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
@@ -231,6 +238,13 @@ PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c",
"mout_isp_pll", };
PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
+ "fin_pll", "ioclk_spdif_extclk", };
+PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",
+ "mout_aud_pll_user_t",};
+PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
+ "mout_aud_pll_user_t",};
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
@@ -239,6 +253,14 @@ static struct samsung_fixed_factor_clock
top_fixed_factor_clks[] __initdata = {
FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
};
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 1),
+ FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 1),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 1),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
@@ -284,6 +306,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -292,6 +322,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
+ mout_
[PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 79 +-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 111 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index e0d71fd..11ee2d8 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -259,6 +259,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[]
__initdata = {
FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 1),
+ /* XspiCLK[4:0] input clock for SPI */
+ FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 5000),
+ /* Xi2s1SCLK input clock for I2S1_BCLK */
+ FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -763,6 +771,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
"samsung,exynos5433-cmu-mif",
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC 0x0600
+#define DIV_STAT_PERIC 0x0700
#define ENABLE_ACLK_PERIC 0x0800
#define ENABLE_PCLK_PERIC0 0x0900
#define ENABLE_PCLK_PERIC1 0x0904
@@ -773,6 +782,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
"samsung,exynos5433-cmu-mif",
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+ DIV_STAT_PERIC,
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -782,14 +792,56 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+ /* DIV_PERIC */
+ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "fin_pll", DIV_PERIC, 4, 8),
+ DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "fin_pll", DIV_PERIC, 0, 4),
+};
+
static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIC */
+ GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 31, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 28, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 26, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 25, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
23, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
22, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK
Re: [RFC 0/2] Reenable might_sleep() checks for might_fault() when atomic
On Thu, Nov 27, 2014 at 08:09:19AM +0100, Heiko Carstens wrote:
> On Wed, Nov 26, 2014 at 07:04:47PM +0200, Michael S. Tsirkin wrote:
> > On Wed, Nov 26, 2014 at 05:51:08PM +0100, Christian Borntraeger wrote:
> > > > But this one was > giving users in field false positives.
> > >
> > > So lets try to fix those, ok? If we cant, then tough luck.
> >
> > Sure.
> > I think the simplest way might be to make spinlock disable
> > premption when CONFIG_DEBUG_ATOMIC_SLEEP is enabled.
> >
> > As a result, userspace access will fail and caller will
> > get a nice error.
>
> Yes, _userspace_ now sees unpredictable behaviour, instead of that the
> kernel emits a big loud warning to the console.
So I don't object to adding more debugging at all.
Sure, would be nice.
But the fix is not an unconditional might_sleep
within might_fault, this would trigger false positives.
Rather, detect that you took a spinlock
without disabling preemption.
> Please consider this simple example:
>
> int bar(char __user *ptr)
> {
> ...
> if (copy_to_user(ptr, ...)
> return -EFAULT;
> ...
> }
>
> SYSCALL_DEFINE1(foo, char __user *, ptr)
> {
> int rc;
>
> ...
> rc = bar(ptr);
> if (rc)
> goto out;
> ...
> out:
> return rc;
> }
>
> The above simple system call just works fine, with and without your change,
> however if somebody (incorrectly) changes sys_foo() to the code below:
>
> spin_lock(&lock);
> rc = bar(ptr);
> if (rc)
> goto out;
> out:
> spin_unlock(&lock);
> return rc;
>
> Broken code like above used to generate warnings. With your change we won't
> see any warnings anymore. Instead we get random and bad behaviour:
>
> For !CONFIG_PREEMPT if the page at ptr is not mapped, the kernel will see
> a fault, potentially schedule and potentially deadlock on &lock.
> Without _any_ warning anymore.
>
> For CONFIG_PREEMPT if the page at ptr is mapped, everthing works. However if
> the page is not mapped, userspace now all of the sudden will see an invalid(!)
> -EFAULT return code, instead of that the kernel resolved the page fault.
> Yes, the kernel can't resolve the fault since we hold a spinlock. But the
> above bogus code did give warnings to give you an idea that something probably
> is not correct.
>
> Who on earth is supposed to debug crap like this???
>
> What we really want is:
>
> Code like
> spin_lock(&lock);
> if (copy_to_user(...))
> rc = ...
> spin_unlock(&lock);
> really *should* generate warnings like it did before.
>
> And *only* code like
> spin_lock(&lock);
> page_fault_disable();
> if (copy_to_user(...))
> rc = ...
> page_fault_enable();
> spin_unlock(&lock);
> should not generate warnings, since the author hopefully knew what he did.
>
> We could achieve that by e.g. adding a couple of pagefault disabled bits
> within current_thread_info()->preempt_count, which would allow
> pagefault_disable() and pagefault_enable() to modify a different part of
> preempt_count than it does now, so there is a way to tell if pagefaults have
> been explicitly disabled or are just a side effect of preemption being
> disabled.
> This would allow might_fault() to restore its old sane behaviour for the
> !page_fault_disabled() case.
Exactly. I agree, that would be a useful debugging tool.
In fact this comment in mm/memory.c hints at this:
* it would be nicer only to annotate paths which are not under
* pagefault_disable,
it further says
* however that requires a larger audit and
* providing helpers like get_user_atomic.
but I think that what you outline is a better way to do this.
--
MST
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[PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index dd1e6a1..5d7ff33 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -740,6 +740,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif,
"samsung,exynos5433-cmu-cpif",
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF00x0300
+#define MUX_ENABLE_MIF10x0304
+#define MUX_ENABLE_MIF20x0308
+#define MUX_ENABLE_MIF30x030c
+#define MUX_ENABLE_MIF40x0310
+#define MUX_ENABLE_MIF50x0314
+#define MUX_ENABLE_MIF60x0318
+#define MUX_ENABLE_MIF70x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT0x0c04
+#define DREX_FREQ_CTRL00x1000
+#define DREX_FREQ_CTRL10x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
static unsigned long mif_clk_regs[] __initdata = {
MEM0_PLL_LOCK,
@@ -758,6 +818,66 @@ static unsigned long mif_clk_regs[] __initdata = {
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ MUX_STAT_MIF0,
+ MUX_STAT_MIF1,
+ MUX_STAT_MIF2,
+ MUX_STAT_MIF3,
+ MUX_STAT_MIF4,
+ MUX_STAT_MIF5,
+ MUX_STAT_MIF6,
+ MUX_STAT_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ DIV_STAT_MIF1,
+ DIV_STAT_MIF2,
+ DIV_STAT_MIF3,
+ DIV_STAT_MIF4,
+ DIV_STAT_MIF5,
+ DIV_STAT_MIF_PLL_FREQ_DET,
+ ENABLE_ACLK_MIF0
[PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 ++
drivers/clk/samsung/clk-exynos5433.c | 225 -
include/dt-bindings/clock/exynos5433.h | 52 -
3 files changed, 295 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
+and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
+which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_bus0: clock-controller@0x1360 {
+ compatible = "samsung,exynos5433-cmu-bus0";
+ reg = <0x1360 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus1: clock-controller@0x1480 {
+ compatible = "samsung,exynos5433-cmu-bus1";
+ reg = <0x1480 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus2: clock-controller@0x1340 {
+ compatible = "samsung,exynos5433-cmu-bus2";
+ reg = <0x1340 0x0b04>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 9f28672..f0975e1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -428,7 +428,7 @@ static struct samsung_div_clock top_div_clks[] __initdata =
{
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
"mout_bus_pll_user", DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
"mout_bus_pll_user", DIV_TOP3, 20, 3),
@@ -443,6 +443,14 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
"mout_bus_pll_user", DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
+ DIV_TOP4, 0, 3),
+
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
DIV_TOP_FSYS0, 16, 8),
@@ -506,6 +514,19 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
static struct samsung_gate_clock top_gate_clks[] __initdata = {
/* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+ "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
+ ENABLE_ACLK_TOP, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
+ ENABLE_ACLK_TOP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+ ENABLE_ACLK_TOP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+ ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
ENABLE_ACLK_TOP, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIS_66, "aclk_
[PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 146 -
include/dt-bindings/clock/exynos5433.h | 33 +++-
2 files changed, 176 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 11ee2d8..b09f2cfe 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -248,6 +248,7 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0",
"fin_pll",
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
+ FFACTOR(0, "oscclk_efuse_common", "fin_pll", 1, 1, 0),
/* HACK: fin_pll hardcoded to xusbxti until detection is implemented */
FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
@@ -959,15 +960,69 @@ CLK_OF_DECLARE(exynos5433_cmu_peric,
"samsung,exynos5433-cmu-peric",
/*
* Register offset definitions for CMU_PERIS
*/
-#define ENABLE_ACLK_PERIS 0x0800
-#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
+#define ENABLE_SCLK_PERIS 0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
+#define ENABLE_IP_PERIS0 0x0b00
+#define ENABLE_IP_PERIS1 0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
static unsigned long peris_clk_regs[] __initdata = {
ENABLE_ACLK_PERIS,
ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_TZPC,
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_SECKEY,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+ ENABLE_IP_PERIS0,
+ ENABLE_IP_PERIS1,
+ ENABLE_IP_PERIS_SECURE_TZPC,
+ ENABLE_IP_PERIS_SECURE_SECKEY,
+ ENABLE_IP_PERIS_SECURE_CHIPID,
+ ENABLE_IP_PERIS_SECURE_TOPRTC,
+ ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+ ENABLE_IP_PERIS_SECURE_OTP_CON,
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIS */
+ GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIS */
GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
@@ -989,6 +1044,93 @@ static struct samsung_gate_clock peris_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HDMI_CEC, "pc
Re: linux-next: manual merge of the block tree with the ext4 tree
On Thu, Nov 27, 2014 at 02:53:47PM +1100, Stephen Rothwell wrote:
> Hi Jens,
>
> Today's linux-next merge of the block tree got a conflict in
> fs/fs-writeback.c between commit ef7fdf5e8c87 ("vfs: add support for a
> lazytime mount option")
Mergign that into a branch for linux-next must surely have been a
mistake, as the code isn't anywhere near ready.
I also think it very much should go into through the vfs tree.
--
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[PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = "samsung,exynos5433-cmu-disp";
+ reg = <0x13b9 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 5d7ff33..cd48209 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1",
"fin_pll",
PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
"mout_aud_pll_user_t",};
+PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
FFACTOR(0, "sclk_bus_pll", "fout_bus_pll", 1, 1, 0),
FFACTOR(0, "sclk_mfc_pll", "fout_mfc_pll", 1, 1, 0),
@@ -400,6 +402,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1259,9 +1265,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1336,21 +1342,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
- "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 14, 0, 0),
+ "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
- "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 7, 0, 0),
+ "div_sclk_decon_tv_eclk", ENABLE_SCLK_MI
[PATCH 18/19] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index cfe3de8..a3093d4 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -56,6 +56,11 @@
mshc0 = &mshc_0;
mshc1 = &mshc_1;
mshc2 = &mshc_2;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ spi3 = &spi_3;
+ spi4 = &spi_4;
};
chipid@1000 {
@@ -254,6 +259,35 @@
interrupts = <1 9 0xf04>;
};
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma0: pdma@1561 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1561 0x1000>;
+ interrupts = <0 228 0>;
+ clocks = <&cmu_fsys CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@1560 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1560 0x1000>;
+ interrupts = <0 246 0>;
+ clocks = <&cmu_fsys CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
serial_0: serial@14C1 {
compatible = "samsung,exynos5433-uart";
reg = <0x14C1 0x100>;
@@ -354,6 +388,91 @@
interrupts = <0 442 0>;
};
+ spi_0: spi@14d2 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d2 0x100>;
+ interrupts = <0 432 0>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI0>,
+<&cmu_top CLK_SCLK_SPI0_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
+
+ spi_1: spi@14d3 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d3 0x100>;
+ interrupts = <0 433 0>;
+ dmas = <&pdma0 11>, <&pdma0 10>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI1>,
+<&cmu_top CLK_SCLK_SPI1_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
+
+ spi_2: spi@14d4 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d4 0x100>;
+ interrupts = <0 434 0>;
+ dmas = <&pdma0 13>, <&pdma0 12>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI2>,
+<&cmu_top CLK_SCLK_SPI2_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "defa
[PATCH 14/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 143 +
include/dt-bindings/clock/exynos5433.h | 37 +-
3 files changed, 187 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 589ed93..bf72817 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -30,6 +30,8 @@ Required Properties:
which generates global data buses clock and global peripheral buses clock.
- "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
+ - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
+which generates clocks for GSCALER IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_gscl: clock-controller@0x13cf {
+ compatible = "samsung,exynos5433-cmu-gscl";
+ reg = <0x13cf 0x0b10>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 920bc3c..f515b95 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -543,6 +543,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
+ ENABLE_ACLK_TOP, 15, 0, 0),
+ GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
+ ENABLE_ACLK_TOP, 14, 0, 0),
GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
@@ -3264,3 +3268,142 @@ static void __init exynos5433_cmu_g3d_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL0x0300
+#defineMUX_STAT_GSCL 0x0400
+#defineENABLE_ACLK_GSCL0x0800
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#defineENABLE_PCLK_GSCL0x0900
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#defineENABLE_IP_GSCL0 0x0b00
+#defineENABLE_IP_GSCL1 0x0b04
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL00x0b08
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL10x0b0c
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL20x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)= { "fin_pll", "aclk_gscl_111", };
+PNAME(aclk_gscl_333_user_p)= { "fin_pll", "aclk_gscl_333", };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
+ aclk_gscl_333_user
[PATCH 02/19] clk: samsung: Add binding documentation for Exynos5433 clock controller
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage guide.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 106 +
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000..72cd0ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,106 @@
+* Samsung Exynos5433 CMU (Clock Management Units)
+
+The Exynos5433 clock controller generates and supplies clock to various
+controllers within the Exynos5433 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
+which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
+domains and bus clocks.
+ - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
+which generates clocks for LLI (Low Latency Interface) IP.
+ - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
+which generates clocks for DRAM Memory Controller domain.
+ - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
+which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
+ - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
+which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
+ - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
+which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5433.h header and can be used in device
+tree sources.
+
+Example 1: Examples of clock controller nodes are listed below.
+
+ cmu_top: clock-controller@0x1003 {
+ compatible = "samsung,exynos5433-cmu-top";
+ reg = <0x1003 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_cpif: clock-controller@0x10fc {
+ compatible = "samsung,exynos5433-cmu-cpif";
+ reg = <0x10fc 0x0c04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_mif: clock-controller@0x105b {
+ compatible = "samsung,exynos5433-cmu-mif";
+ reg = <0x105b 0x100c>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peric: clock-controller@0x14c8 {
+ compatible = "samsung,exynos5433-cmu-peric";
+ reg = <0x14c8 0x0b08>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peris: clock-controller@0x1004 {
+ compatible = "samsung,exynos5433-cmu-peris";
+ reg = <0x1004 0x0b20>;
+ #clock-cells = <1>;
+ };
+
+ cmu_fsys: clock-controller@0x156e {
+ compatible = "samsung,exynos5433-cmu-fsys";
+ reg = <0x156e 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller.
+
+ serial_0: serial@14C1 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x14C1 0x100>;
+ interrupts = <0 421 0>;
+ clocks = <&cmu_peric CLK_PCLK_UART0>,
+<&cmu_peric CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "disabled";
+ };
+
+Example 3: SPI controller node that consumes the clock generated by the clock
+ controller.
+
+ spi_0: spi@14d2 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d2 0x100>;
+ interrupts = <0 432 0>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI0>,
+<&cmu_top CLK_SCLK_SPI0_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
--
1.8.5.5
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[PATCH 00/19] arm64: Add the support for new 64-bit Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock control for Exynos5433 using common clk framework
This patchst is based on Exynos7 patchset[1] because Exynos5433 has similiar
feature with Exynos7. Exynos7 did already specify the dependent patchset list.
This patchset has the dependency as following list:
: The Exynos7 patchset[1] specified dependent patchset for 64-bit SoC.
So, this patchset used same dependent patchset of Exynos7 patchset and Exynos7
patchset about pinctrl patch. Additionally, SPI/MMC/PDMA patch [2-5] is used
for kernel booting and mounting rootfs.
1. [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
- [1] http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
2. [PATCH] spi: s3c64xx: add support for exynos7 SPI controller
- [2] http://www.spinics.net/lists/linux-samsung-soc/msg38607.html
3. [PATCH V7] mmc: dw_mmc: Add IDMAC 64-bit address mode support
- [3] https://lkml.org/lkml/2014/10/20/58
4. [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
- [4] http://www.spinics.net/lists/linux-mmc/msg28294.html
5. [PATCH] dmaengine: pl330: Correct device assignment
- [5] https://lkml.org/lkml/2014/11/6/207
Chanwoo Choi (18):
pinctrl: exynos: Add support for Exynos5433
clk: samsung: Add binding documentation for Exynos5433 clock controller
clk: samsung: exynos5433: Add clocks using common clock framework
clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
clk: samsung: exynos5433: Add clocks for CMU_G2D domain
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
clk: samsung: exynos5433: Add clocks for CMU_DISP domain
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
clk: samsung: exynos5433: Add clocks for CMU_G3D domain
clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
serial: samsung: Add the support for Exynos5433 SoC
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/clock/exynos5433-clock.txt | 167 +
arch/arm64/Kconfig | 10 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 684
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5433.c | 3409
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 +
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
drivers/tty/serial/samsung.c | 56 +-
include/dt-bindings/clock/exynos5433.h | 867 +
11 files changed, 6038 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5433.c
create mode 100644 include/dt-bindings/clock/exynos5433.h
--
1.8.5.5
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 17/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433
From: Jaehoon Chung
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Jaehoon Chung
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 3d8b576..cfe3de8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -53,6 +53,9 @@
i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10;
i2c11 = &hsi2c_11;
+ mshc0 = &mshc_0;
+ mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
};
chipid@1000 {
@@ -507,6 +510,45 @@
status = "disabled";
};
+ mshc_0: mshc@1554 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 225 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1554 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC0>,
+<&cmu_fsys CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_1: mshc@1555 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 226 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1555 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC1>,
+<&cmu_fsys CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_2: mshc@1556 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 227 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1556 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC2>,
+<&cmu_fsys CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
--
1.8.5.5
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[PATCH 12/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 285 +
include/dt-bindings/clock/exynos5433.h | 82 +-
2 files changed, 364 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index f0975e1..ee26974 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -467,6 +467,16 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
DIV_TOP_FSYS0, 0, 4),
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
+ "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
+ "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
+ DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
DIV_TOP_PERIC0, 16, 8),
@@ -539,12 +549,20 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
+ ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
+ "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
+ "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
+ "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
@@ -1821,10 +1839,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris,
"samsung,exynos5433-cmu-peris",
#define ENABLE_IP_FSYS10x0b04
/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { "fin_pll", "sclk_ufs_mphy", };
PNAME(mout_aclk_fsys_200_user_p) = { "fin_pll", "aclk_fsys_200", };
+PNAME(mout_sclk_pcie_100_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
+PNAME(mout_sclk_ufsunipro_user_p) = { "fin_pll", "sclk_ufsunipro_fsys",};
PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2_fsys", };
PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1_fsys", };
PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0_fsys", };
+PNAME(mout_sclk_usbhost30_user_p) = { "fin_pll", "sclk_usbhost30_fsys",};
+PNAME(mout_sclk_usbdrd30_user_p) = { "fin_pll", "sclk_usbdrd30_fsys", };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_hsic1_phy", };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_clk48mohci_phy", };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { "fin_pll", "phyclk_usbhost20_phy_freeclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { "fin_pll", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_rx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_rx0_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+ = { "fin_pll", "phyclk_ufs_tx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+ = {
[PATCH 13/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 127 +
include/dt-bindings/clock/exynos5433.h | 25
3 files changed, 160 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 03ae40a..589ed93 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -28,6 +28,8 @@ Required Properties:
- "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
which generates global data buses clock and global peripheral buses clock.
+ - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
+which generates clocks for 3D Graphics Engine IP.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -115,6 +117,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_g3d: clock-controller@0x14aa {
+ compatible = "samsung,exynos5433-cmu-g3d";
+ reg = <0x14aa 0x1000>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index ee26974..920bc3c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3137,3 +3137,130 @@ static void __init exynos5433_cmu_bus2_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_bus2, "samsung,exynos5433-cmu-bus2",
exynos5433_cmu_bus2_init);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK 0x
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FREQ_DET 0x010c
+#define MUX_SEL_G3D0x0200
+#define MUX_ENABLE_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define DIV_G3D0x0600
+#define DIV_G3D_PLL_FREQ_DET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_G3D0x0800
+#define ENABLE_PCLK_G3D0x0900
+#define ENABLE_SCLK_G3D0x0a00
+#define ENABLE_IP_G3D0 0x0b00
+#define ENABLE_IP_G3D1 0x0b04
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT0x0c04
+#define CLK_STOPCTRL 0x1000
+
+static unsigned long g3d_clk_regs[] __initdata = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FREQ_DET,
+ MUX_SEL_G3D,
+ MUX_ENABLE_G3D,
+ MUX_STAT_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FREQ_DET,
+ DIV_STAT_G3D,
+ DIV_STAT_G3D_PLL_FREQ_DET,
+ ENABLE_ACLK_G3D,
+ ENABLE_PCLK_G3D,
+ ENABLE_SCLK_G3D,
+ ENABLE_IP_G3D0,
+ ENABLE_IP_G3D1,
+ CLKOUT_CMU_G3D,
+ CLKOUT_CMU_G3D_DIV_STAT,
+ CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
+PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
+
+static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
+ /* MUX_SEL_G3D */
+ MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
+ MUX_SEL_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1),
+};
+
+static struct samsung_div_clock g3d_div_clks[] __initdata = {
+ /* DIV_G3D */
+ DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
+ 8, 2),
+ DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
+ 4, 3),
+ DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
+ 0, 3),
+};
+
+static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_G3D */
+ GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 7, 0, 0),
+ GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0"
[PATCH 19/19] serial: samsung: Add the support for Exynos5433 SoC
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/tty/serial/samsung.c | 56
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 2338ad8..6f1fb9a 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1766,32 +1766,43 @@ static struct s3c24xx_serial_drv_data
s5pv210_serial_drv_data = {
#endif
#if defined(CONFIG_ARCH_EXYNOS)
+#define EXYNOS_COMMON_SERIAL_DRV_DATA \
+ .info = &(struct s3c24xx_uart_info) { \
+ .name = "Samsung Exynos UART",\
+ .type = PORT_S3C6400, \
+ .has_divslot= 1,\
+ .rx_fifomask= S5PV210_UFSTAT_RXMASK,\
+ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
+ .rx_fifofull= S5PV210_UFSTAT_RXFULL,\
+ .tx_fifofull= S5PV210_UFSTAT_TXFULL,\
+ .tx_fifomask= S5PV210_UFSTAT_TXMASK,\
+ .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
+ .def_clk_sel= S3C2410_UCON_CLKSEL0, \
+ .num_clks = 1,\
+ .clksel_mask= 0,\
+ .clksel_shift = 0,\
+ }, \
+ .def_cfg = &(struct s3c2410_uartcfg) { \
+ .ucon = S5PV210_UCON_DEFAULT, \
+ .ufcon = S5PV210_UFCON_DEFAULT,\
+ .has_fracval= 1,\
+ } \
+
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
- .info = &(struct s3c24xx_uart_info) {
- .name = "Samsung Exynos4 UART",
- .type = PORT_S3C6400,
- .has_divslot= 1,
- .rx_fifomask= S5PV210_UFSTAT_RXMASK,
- .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
- .rx_fifofull= S5PV210_UFSTAT_RXFULL,
- .tx_fifofull= S5PV210_UFSTAT_TXFULL,
- .tx_fifomask= S5PV210_UFSTAT_TXMASK,
- .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
- .def_clk_sel= S3C2410_UCON_CLKSEL0,
- .num_clks = 1,
- .clksel_mask= 0,
- .clksel_shift = 0,
- },
- .def_cfg = &(struct s3c2410_uartcfg) {
- .ucon = S5PV210_UCON_DEFAULT,
- .ufcon = S5PV210_UFCON_DEFAULT,
- .has_fracval= 1,
- },
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
.fifosize = { 256, 64, 16, 16 },
};
+
+static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
+ EXYNOS_COMMON_SERIAL_DRV_DATA,
+ .fifosize = { 64, 256, 16, 256 },
+};
+
#define EXYNOS4210_SERIAL_DRV_DATA
((kernel_ulong_t)&exynos4210_serial_drv_data)
+#define EXYNOS5433_SERIAL_DRV_DATA
((kernel_ulong_t)&exynos5433_serial_drv_data)
#else
#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
+#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
#endif
static struct platform_device_id s3c24xx_serial_driver_ids[] = {
@@ -1813,6 +1824,9 @@ static struct platform_device_id
s3c24xx_serial_driver_ids[] = {
}, {
.name = "exynos4210-uart",
.driver_data= EXYNOS4210_SERIAL_DRV_DATA,
+ }, {
+ .name = "exynos5433-uart",
+ .driver_data= EXYNOS5433_SERIAL_DRV_DATA,
},
{ },
};
@@ -1832,6 +1846,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[]
= {
.data = (void *)S5PV210_SERIAL_DRV_DATA },
{ .compatible = "samsung,exynos4210-uart",
.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
+ { .compatible = "samsung,exynos5433-uart",
+ .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
--
1.8.5.5
--
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[PATCH 10/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk-exynos5433.c | 173 +
include/dt-bindings/clock/exynos5433.h | 53 +++
3 files changed, 233 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 8d3dad4..9a6ae75 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -23,6 +23,8 @@ Required Properties:
which generates clocks for G2D/MDMA IPs.
- "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+ - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
+which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_aud: clock-controller@0x114c {
+ compatible = "samsung,exynos5433-cmu-aud";
+ reg = <0x114c 0x0b04>;
+ #clock-cells = <1>;
+ };
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index cd48209..9f28672 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2456,3 +2456,176 @@ static void __init exynos5433_cmu_disp_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD00x0300
+#define MUX_ENABLE_AUD10x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD0x0800
+#define ENABLE_PCLK_AUD0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ MUX_STAT_AUD0,
+ DIV_AUD0,
+ DIV_AUD1,
+ DIV_STAT_AUD0,
+ DIV_STAT_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { "fin_pll", "fout_aud_pll", };
+PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+PNAME(mout_sclk_aud_i2s_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+ FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 18800),
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+ /* DIV_AUD0 */
+ DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
+ 12, 4),
+ DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
+ 8, 4),
+ DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
+ 4, 4),
+ DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
+ 0, 4),
+
+ /* DIV_AUD1 */
+ DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
+ "mout_aud_pll_user", DIV_AUD1, 16, 5),
+ DI
[PATCH 15/19] arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Chanwoo Choi Acked-by: Geunsik Lim Acked-by: Inki Dae --- arch/arm64/Kconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f4536e0..8a5e8a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -152,6 +152,16 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool "ARMv8 based Samsung Exynos5433" + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 42 +-
3 files changed, 193 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 72cd0ba..27dd77b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -19,6 +19,8 @@ Required Properties:
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+ - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
+which generates clocks for G2D/MDMA IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -70,6 +72,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = <1>;
};
+ cmu_g2d: clock-controller@0x1246 {
+ compatible = "samsung,exynos5433-cmu-g2d";
+ reg = <0x1246 0x0b08>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index b09f2cfe..dd1e6a1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -403,6 +403,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
};
static struct samsung_div_clock top_div_clks[] __initdata = {
+ /* DIV_TOP1 */
+ DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
+ DIV_TOP1, 28, 3),
+ DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
+ DIV_TOP1, 12, 3),
+ DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
+ DIV_TOP1, 8, 3),
+ DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
+ DIV_TOP1, 0, 3),
+
/* DIV_TOP2 */
DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
DIV_TOP2, 0, 3),
@@ -492,6 +506,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
+ ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
+ ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
@@ -1277,3 +1295,129 @@ static void __init exynos5433_cmu_fsys_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0 0x0200
+#define MUX_SEL_ENABLE_G2D00x0300
+#define MUX_SEL_STAT_G2D0 0x0400
+#define DIV_G2D0x0600
+#define DIV_STAT_G2D 0x0700
+#define DIV_ENABLE_ACLK_G2D0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D0x0804
+#define DIV_ENABLE_PCLK_G2D0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D0x0904
+#define DIV_ENABLE_IP_G2D0 0x0b00
+#define DIV_ENABLE_IP_G2D1 0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
+
+static unsigned long g2d_clk_regs[] __initdata = {
+ MUX_SEL_G2D0,
+ MUX_SEL_ENABLE_G2D0,
+ MUX_SEL_STAT_G2D0,
+ DIV_G2D,
+ DIV_STAT_G2D,
+ DIV_ENABLE_ACLK_G2D,
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_PCLK_G2D,
+ DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_IP_G2D0,
+ DIV_E
Re: [PATCH v4] mailbox/omap: adapt to the new mailbox framework
On 4 November 2014 at 04:35, Suman Anna wrote: > The OMAP mailbox driver and its existing clients (remoteproc > for OMAP4+) are adapted to use the generic mailbox framework. > > The main changes for the adaptation are: > - The tasklet used for Tx is replaced with the state machine from > the generic mailbox framework. The workqueue used for processing > the received messages stays intact for minimizing the effects on > the OMAP mailbox clients. > - The existing exported client API, omap_mbox_get, omap_mbox_put and > omap_mbox_send_msg are deleted, as the framework provides equivalent > functionality. A OMAP-specific omap_mbox_request_channel is added > though to support non-DT way of requesting mailboxes. > - The OMAP mailbox driver is integrated with the mailbox framework > through the proper implementations of mbox_chan_ops, except for > .last_tx_done and .peek_data. The OMAP mailbox driver does not need > these ops, as it is completely interrupt driven. > - The OMAP mailbox driver uses a custom of_xlate controller ops that > allows phandles for the pargs specifier instead of indexing to avoid > any channel registration order dependencies. > - The new framework does not support multiple clients operating on a > single channel, so the reference counting logic is simplified. > - The remoteproc driver (current client) is adapted to use the new API. > The notifier callbacks used within this client is replaced with the > regular callbacks from the newer framework. > - The exported OMAP mailbox API are limited to omap_mbox_save_ctx, > omap_mbox_restore_ctx, omap_mbox_enable_irq & omap_mbox_disable_irq, > with the signature modified to take in the new mbox_chan handle instead > of the OMAP specific omap_mbox handle. The first 2 will be removed when > the OMAP mailbox driver is adapted to runtime_pm. The other exported > API omap_mbox_request_channel will be removed once existing legacy > users are converted to DT. > > Cc: Jassi Brar > Cc: Ohad Ben-Cohen > Signed-off-by: Suman Anna > --- > v3->v4: No code changes, switched the example to use the DSP node instead of > WkupM3 in the bindings document & minor commit description changes. Other than > that, this is a repost of the driver adaptation patch [1] from the OMAP > Mailbox > framework adaptation series [2]. This patch is intended for the 3.19 merge > window, > all the dependent patches in [2] are merged as of 3.18-rc2. The DTS patch in > [2] > will be posted separately. > > [1] http://marc.info/?l=linux-omap&m=141038453917790&w=2 > [2] http://marc.info/?l=linux-omap&m=141038447817775&w=2 > > .../devicetree/bindings/mailbox/omap-mailbox.txt | 23 ++ > drivers/mailbox/omap-mailbox.c | 346 > - > drivers/remoteproc/omap_remoteproc.c | 51 +-- > include/linux/omap-mailbox.h | 16 +- > 4 files changed, 256 insertions(+), 180 deletions(-) > Applied to mailbox-devel, Thanks -Jassi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] mailbox: add tx_prepare client callback
On 12 November 2014 at 00:03, Sudeep Holla wrote: > If the mailbox controller expects the payload is in place before > initiating the transmit, then it's impossible to reuse the list > maintained by core mailbox code currently. Maintaining another list > for sending the message in the controller seems totally unnecessary > as core mailbox library already provides that feature. > > This patch introduces tx_prepare callback in mbox_client which > can be used by the core mailbox library before initiating the > transaction through mbox->ops->send_data. The client driver can > implement this callback to ensure the payload is copied to the > shared memory. > > Signed-off-by: Sudeep Holla > Cc: Jassi Brar > Cc: Arnd Bergmann > --- > drivers/mailbox/mailbox.c | 2 ++ > include/linux/mailbox_client.h | 3 +++ > 2 files changed, 5 insertions(+) > Applied to mailbox-devel, Thanks. -Jassi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down
Chander Kashyap wrote:
>
> Exynos7 supports multiple idle states. Core power down is one such
> idle state, where cores can be powered off independently.
>
> This patch adds support for core power down idle state.
>
> Entry latency for core power down idle state is calculated as follows:
> 1. Time difference is measured between cpuidle entry and exit.
> 2. WFI is skipped for measuring the time.
> 3. Select the worst case time in a set of 10 cpuidle transactions,
>with varying load.
>
> Exit latency and min residency values are supplied as per HW team.
>
> Signed-off-by: Chander Kashyap
> Acked-by: Lorenzo Pieralisi
Lorenzo, thanks for your ack. Will apply.
- Kukjin
> ---
> This patch has following dependencies:
> - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
> www.spinics.net/lists/arm-kernel/msg375961.html
> Changes in v2:
> - Moved the cpu-idle-state property after reg property
> - removed the status property.
> Changes in v3:
> - Added the Entry latency calculation in commit message.
> Changes in v4:
> - Corrected the commit message.
> - Corrected the entry latency value.
> Changes in v5:
> - Commit message modified
>
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index d7a37c3..891eef4 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -37,6 +37,7 @@
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0x0>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP>;
> };
>
> cpu@1 {
> @@ -44,6 +45,7 @@
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0x1>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP>;
> };
>
> cpu@2 {
> @@ -51,6 +53,7 @@
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0x2>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP>;
> };
>
> cpu@3 {
> @@ -58,6 +61,20 @@
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0x3>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x001>;
> + entry-latency-us = <34>;
> + exit-latency-us = <150>;
> + min-residency-us = <2100>;
> + };
> };
> };
>
> --
> 1.9.1
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Re: [PATCH v2] hv: hv_fcopy: drop the obsolete message on transfer failure
- Original Message -
> In the case the user-space daemon crashes, hangs or is killed, we
> need to down the semaphore, otherwise, after the daemon starts next
> time, the obsolete data in fcopy_transaction.message or
> fcopy_transaction.fcopy_msg will be used immediately.
>
> Reviewed-by: Vitaly Kuznetsov
> Cc: K. Y. Srinivasan
> Signed-off-by: Dexuan Cui
> ---
>
> v2: I removed the "FCP" prefix as Greg asked.
>
> I also updated the output message a little:
> "FCP: failed to acquire the semaphore" -->
> "can not acquire the semaphore: it is benign"
>
> drivers/hv/hv_fcopy.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/hv/hv_fcopy.c b/drivers/hv/hv_fcopy.c
> index 23b2ce2..c518ad9 100644
> --- a/drivers/hv/hv_fcopy.c
> +++ b/drivers/hv/hv_fcopy.c
> @@ -86,6 +86,15 @@ static void fcopy_work_func(struct work_struct *dummy)
>* process the pending transaction.
>*/
> fcopy_respond_to_host(HV_E_FAIL);
> +
> + /* In the case the user-space daemon crashes, hangs or is killed, we
> + * need to down the semaphore, otherwise, after the daemon starts next
> + * time, the obsolete data in fcopy_transaction.message or
> + * fcopy_transaction.fcopy_msg will be used immediately.
> + */
Looks still racy, what happens if the daemon start before down_trylock()
but after fcopy_respont_to_host() here?
> + if (down_trylock(&fcopy_transaction.read_sema))
> + pr_debug("can not acquire the semaphore: it is benign\n");
typo
> +
> }
>
> static int fcopy_handle_handshake(u32 version)
> --
> 1.9.1
>
> --
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Re: [RFC 0/2] Reenable might_sleep() checks for might_fault() when atomic
On Wed, Nov 26, 2014 at 07:04:47PM +0200, Michael S. Tsirkin wrote:
> On Wed, Nov 26, 2014 at 05:51:08PM +0100, Christian Borntraeger wrote:
> > > But this one was > giving users in field false positives.
> >
> > So lets try to fix those, ok? If we cant, then tough luck.
>
> Sure.
> I think the simplest way might be to make spinlock disable
> premption when CONFIG_DEBUG_ATOMIC_SLEEP is enabled.
>
> As a result, userspace access will fail and caller will
> get a nice error.
Yes, _userspace_ now sees unpredictable behaviour, instead of that the
kernel emits a big loud warning to the console.
Please consider this simple example:
int bar(char __user *ptr)
{
...
if (copy_to_user(ptr, ...)
return -EFAULT;
...
}
SYSCALL_DEFINE1(foo, char __user *, ptr)
{
int rc;
...
rc = bar(ptr);
if (rc)
goto out;
...
out:
return rc;
}
The above simple system call just works fine, with and without your change,
however if somebody (incorrectly) changes sys_foo() to the code below:
spin_lock(&lock);
rc = bar(ptr);
if (rc)
goto out;
out:
spin_unlock(&lock);
return rc;
Broken code like above used to generate warnings. With your change we won't
see any warnings anymore. Instead we get random and bad behaviour:
For !CONFIG_PREEMPT if the page at ptr is not mapped, the kernel will see
a fault, potentially schedule and potentially deadlock on &lock.
Without _any_ warning anymore.
For CONFIG_PREEMPT if the page at ptr is mapped, everthing works. However if
the page is not mapped, userspace now all of the sudden will see an invalid(!)
-EFAULT return code, instead of that the kernel resolved the page fault.
Yes, the kernel can't resolve the fault since we hold a spinlock. But the
above bogus code did give warnings to give you an idea that something probably
is not correct.
Who on earth is supposed to debug crap like this???
What we really want is:
Code like
spin_lock(&lock);
if (copy_to_user(...))
rc = ...
spin_unlock(&lock);
really *should* generate warnings like it did before.
And *only* code like
spin_lock(&lock);
page_fault_disable();
if (copy_to_user(...))
rc = ...
page_fault_enable();
spin_unlock(&lock);
should not generate warnings, since the author hopefully knew what he did.
We could achieve that by e.g. adding a couple of pagefault disabled bits
within current_thread_info()->preempt_count, which would allow
pagefault_disable() and pagefault_enable() to modify a different part of
preempt_count than it does now, so there is a way to tell if pagefaults have
been explicitly disabled or are just a side effect of preemption being
disabled.
This would allow might_fault() to restore its old sane behaviour for the
!page_fault_disabled() case.
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Re: [PATCH v14 0/3] Add drm driver for Rockchip Socs
On 2014年11月27日 10:12, Dave Airlie wrote: Hi Dave Do you mean that I need send you a branch, based on drm-next, merge with iommu tree and rockchip drm? Yes, grab drm-next, git pull the arm/rockchip branch from Joerg's tree, put rockchip drm patches on top, send me pull request. I'll validate it then. Dave. Hi Dave I have send a pull request to you, with Joerg's iommu arm/rockchip branch. I got a same problem when use "make multi_v7_defconfig" as Heiko said: drivers/video/fbdev/Kconfig:5:error: recursive dependency detected! drivers/video/fbdev/Kconfig:5:symbol FB is selected by DRM_KMS_FB_HELPER drivers/gpu/drm/Kconfig:34:symbol DRM_KMS_FB_HELPER is selected by DRM_ROCKCHIP drivers/gpu/drm/rockchip/Kconfig:1:symbol DRM_ROCKCHIP depends on ARM_DMA_USE_IOMMU arch/arm/Kconfig:95:symbol ARM_DMA_USE_IOMMU is selected by VIDEO_OMAP3 drivers/media/platform/Kconfig:96:symbol VIDEO_OMAP3 depends on VIDEO_V4L2 drivers/media/v4l2-core/Kconfig:6:symbol VIDEO_V4L2 depends on I2C drivers/i2c/Kconfig:7:symbol I2C is selected by FB_DDC drivers/video/fbdev/Kconfig:59:symbol FB_DDC is selected by FB_CYBER2000_DDC drivers/video/fbdev/Kconfig:374:symbol FB_CYBER2000_DDC depends on FB_CYBER2000 drivers/video/fbdev/Kconfig:362:symbol FB_CYBER2000 depends on FB I was confused how to solve the recursive dependency, remove depends on ARM_DMA_USE_IOMMU & IOMMU_API? - Mark -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] core drm support for Rockchip SoCs v14
Hi Dave this pull request is for rockchip drm v14, based on Joerg's iommu arm/rockchip branch. The following changes since commit 656d7077d8ffd1c2492d4a0a354367ab2e545059: dt-bindings: iommu: Add documentation for rockchip iommu (2014-11-03 17:29:09 +0100) are available in the git repository at: https://github.com/markyzq/kernel-drm-rockchip.git drm_iommu for you to fetch changes up to aab18af3a93353bc43897b716fd7e12d5998b9bc: dt-bindings: video: Add documentation for rockchip vop (2014-11-27 13:38:17 +0800) Mark Yao (3): drm: rockchip: Add basic drm driver dt-bindings: video: Add for rockchip display subsytem dt-bindings: video: Add documentation for rockchip vop .../devicetree/bindings/video/rockchip-drm.txt | 19 + .../devicetree/bindings/video/rockchip-vop.txt | 58 + drivers/gpu/drm/Kconfig|2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/rockchip/Kconfig | 17 + drivers/gpu/drm/rockchip/Makefile |8 + drivers/gpu/drm/rockchip/rockchip_drm_drv.c| 483 +++ drivers/gpu/drm/rockchip/rockchip_drm_drv.h| 55 + drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 200 +++ drivers/gpu/drm/rockchip/rockchip_drm_fb.h | 28 + drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 210 +++ drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h | 21 + drivers/gpu/drm/rockchip/rockchip_drm_gem.c| 294 drivers/gpu/drm/rockchip/rockchip_drm_gem.h| 54 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 1459 drivers/gpu/drm/rockchip/rockchip_drm_vop.h| 201 +++ 16 files changed, 3110 insertions(+) create mode 100644 Documentation/devicetree/bindings/video/rockchip-drm.txt create mode 100644 Documentation/devicetree/bindings/video/rockchip-vop.txt create mode 100644 drivers/gpu/drm/rockchip/Kconfig create mode 100644 drivers/gpu/drm/rockchip/Makefile create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_drv.c create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_drv.h create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fb.c create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fb.h create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_gem.c create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_gem.h create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop.c create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] fat: Fix oops on corrupted vfat fs
Andrew Morton writes: > On Thu, 27 Nov 2014 00:31:28 +0900 OGAWA Hirofumi > wrote: > >> a) don't bother with ->d_time for positives - we only check it for negatives >> anyway. >> b) make sure to set it at unlink and rmdir time - at *that* point soon-to-be >> negative dentry matches then-current directory contents >> c) don't go into renaming of old alias in vfat_lookup() unless it has >> the same parent (which it will, unless we are seeing corrupted image) >> >> Signed-off-by: Al Viro >> Cc: # 3.17.x >> [Make change minimum, don't call d_move() for dir] >> Signed-off-by: OGAWA Hirofumi > > It's unclear who did the "[Make change minimum.." alteration. > > I do it this way: > [hirof...@mail.parknet.co.jp: make change minimum, don't call d_move() for > dir] I see. OK, I will also use your format next time. > Also, who was the primary author of this patch? It *looks* like it was > Al, unsure. If it was indeed Al then this can be communicated by > putting his From: line at the very top of the changelog body. Ah, sorry. The patch is written by Al, and I was forgetting to add "From:". -- OGAWA Hirofumi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 03/25] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
On Thu, Nov 27, 2014 at 11:55 AM, Kishon Vijay Abraham I wrote: > From: Gabriel FERNANDEZ > > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue > Signed-off-by: Giuseppe Cavallaro > Signed-off-by: Gabriel Fernandez > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/phy/Kconfig |8 + > drivers/phy/Makefile|1 + > drivers/phy/phy-miphy28lp.c | 1177 > +++ > 3 files changed, 1186 insertions(+) > create mode 100644 drivers/phy/phy-miphy28lp.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 2a436e6..cfaced9 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -38,6 +38,14 @@ config PHY_MVEBU_SATA > depends on OF > select GENERIC_PHY > > +config PHY_MIPHY28LP > + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" > + depends on ARCH_STI > + select GENERIC_PHY > + help > + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) > + that is part of STMicroelectronics STiH407 SoC. > + > config PHY_MIPHY365X > tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series" > depends on ARCH_STI > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index c4590fc..30d90a8 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o > obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > +obj-$(CONFIG_PHY_MIPHY28LP)+= phy-miphy28lp.o > obj-$(CONFIG_PHY_MIPHY365X)+= phy-miphy365x.o > obj-$(CONFIG_PHY_RCAR_GEN2)+= phy-rcar-gen2.o > obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o > diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c > new file mode 100644 > index 000..7d592e6 > --- /dev/null > +++ b/drivers/phy/phy-miphy28lp.c > @@ -0,0 +1,1177 @@ > +/* > + * Copyright (C) 2014 STMicroelectronics > + * > + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). > + * > + * Author: Alexandre Torgue > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2, as > + * published by the Free Software Foundation. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* MiPHY registers */ > +#define MIPHY_CONF_RESET 0x00 > +#define RST_APPLI_SW BIT(0) > +#define RST_CONF_SWBIT(1) > +#define RST_MACRO_SW BIT(2) > + > +#define MIPHY_RESET0x01 > +#define RST_PLL_SW BIT(0) > +#define RST_COMP_SWBIT(2) > + > +#define MIPHY_STATUS_1 0x02 > +#define PHY_RDYBIT(0) > +#define HFC_RDYBIT(1) > +#define HFC_PLLBIT(2) > + > +#define MIPHY_CONTROL 0x04 > +#define TERM_EN_SW BIT(2) > +#define DIS_LINK_RST BIT(3) > +#define AUTO_RST_RXBIT(4) > +#define PX_RX_POL BIT(5) > + > +#define MIPHY_BOUNDARY_SEL 0x0a > +#define TX_SEL BIT(6) > +#define SSC_SELBIT(4) > +#define GENSEL_SEL BIT(0) > + > +#define MIPHY_BOUNDARY_1 0x0b > +#define MIPHY_BOUNDARY_2 0x0c > +#define SSC_EN_SW BIT(2) > + > +#define MIPHY_PLL_CLKREF_FREQ 0x0d > +#define MIPHY_SPEED0x0e > +#define TX_SPDSEL_80DEC0 > +#define TX_SPDSEL_40DEC1 > +#define TX_SPDSEL_20DEC2 > +#define RX_SPDSEL_80DEC0 > +#define RX_SPDSEL_40DEC(1 << 2) > +#define RX_SPDSEL_20DEC(2 << 2) > + > +#define MIPHY_CONF 0x0f > +#define MIPHY_CTRL_TEST_SEL0x20 > +#define MIPHY_CTRL_TEST_1 0x21 > +#define MIPHY_CTRL_TEST_2 0x22 > +#define MIPHY_CTRL_TEST_3 0x23 > +#define MIPHY_CTRL_TEST_4 0x24 > +#define MIPHY_FEEDBACK_TEST0x25 > +#define MIPHY_DEBUG_BUS0x26 > +#define MIPHY_DEBUG_STATUS_MSB 0x27 > +#define MIPHY_DEBUG_STATUS_LSB 0x28 > +#define MIPHY_PWR_RAIL_1 0x29 > +#define MIPHY_PWR_RAIL_2 0x2a > +#define MIPHY_SYNCHAR_CONTROL 0x30 > + > +#define MIPHY_COMP_FSM_1 0x3a > +#define COMP_START BIT(6) > + > +#define MIPHY_COMP_FSM_6 0x3f > +#define COMP_DONE BIT(7) > + > +#define MIPHY_COMP_POST
Re: [PATCH v4 2/5] x86, traps: Track entry into and exit from IST context
>
> Signed-off-by: Paul E. McKenney
>
Reviewed-by: Lai Jiangshan
> diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> index 8749f43f3f05..fc0236992655 100644
> --- a/kernel/rcu/tree.c
> +++ b/kernel/rcu/tree.c
> @@ -759,39 +759,71 @@ void rcu_irq_enter(void)
> /**
> * rcu_nmi_enter - inform RCU of entry to NMI context
> *
> - * If the CPU was idle with dynamic ticks active, and there is no
> - * irq handler running, this updates rdtp->dynticks_nmi to let the
> - * RCU grace-period handling know that the CPU is active.
> + * If the CPU was idle from RCU's viewpoint, update rdtp->dynticks and
> + * rdtp->dynticks_nmi_nesting to let the RCU grace-period handling know
> + * that the CPU is active. This implementation permits nested NMIs, as
> + * long as the nesting level does not overflow an int. (You will probably
> + * run out of stack space first.)
> */
> void rcu_nmi_enter(void)
> {
> struct rcu_dynticks *rdtp = this_cpu_ptr(&rcu_dynticks);
> + int incby = 2;
>
> - if (rdtp->dynticks_nmi_nesting == 0 &&
> - (atomic_read(&rdtp->dynticks) & 0x1))
> - return;
> - rdtp->dynticks_nmi_nesting++;
> - smp_mb__before_atomic(); /* Force delay from prior write. */
> - atomic_inc(&rdtp->dynticks);
> - /* CPUs seeing atomic_inc() must see later RCU read-side crit sects */
> - smp_mb__after_atomic(); /* See above. */
> - WARN_ON_ONCE(!(atomic_read(&rdtp->dynticks) & 0x1));
> + /* Complain about underflow. */
> + WARN_ON_ONCE(rdtp->dynticks_nmi_nesting < 0);
> +
> + /*
> + * If idle from RCU viewpoint, atomically increment ->dynticks
> + * to mark non-idle and increment ->dynticks_nmi_nesting by one.
> + * Otherwise, increment ->dynticks_nmi_nesting by two. This means
> + * if ->dynticks_nmi_nesting is equal to one, we are guaranteed
> + * to be in the outermost NMI handler that interrupted an RCU-idle
> + * period (observation due to Andy Lutomirski).
> + */
> + if (!(atomic_read(&rdtp->dynticks) & 0x1)) {
> + smp_mb__before_atomic(); /* Force delay from prior write. */
> + atomic_inc(&rdtp->dynticks);
> + /* atomic_inc() before later RCU read-side crit sects */
> + smp_mb__after_atomic(); /* See above. */
> + WARN_ON_ONCE(!(atomic_read(&rdtp->dynticks) & 0x1));
> + incby = 1;
> + }
> + rdtp->dynticks_nmi_nesting += incby;
I prefer a "else" branch here.
if (!(atomic_read(&rdtp->dynticks) & 0x1)) {
...
WARN_ON_ONCE(rdtp->dynticks_nmi_nesting); /* paired with
"rdtp->dynticks_nmi_nesting = 0" */
rdtp->dynticks_nmi_nesting = 1; /* paired with "if
(rdtp->dynticks_nmi_nesting != 1) {" */
} else {
rdtp->dynticks_nmi_nesting += 2;
}
> + barrier();
> }
>
> /**
> * rcu_nmi_exit - inform RCU of exit from NMI context
> *
> - * If the CPU was idle with dynamic ticks active, and there is no
> - * irq handler running, this updates rdtp->dynticks_nmi to let the
> - * RCU grace-period handling know that the CPU is no longer active.
> + * If we are returning from the outermost NMI handler that interrupted an
> + * RCU-idle period, update rdtp->dynticks and rdtp->dynticks_nmi_nesting
> + * to let the RCU grace-period handling know that the CPU is back to
> + * being RCU-idle.
> */
> void rcu_nmi_exit(void)
> {
> struct rcu_dynticks *rdtp = this_cpu_ptr(&rcu_dynticks);
>
> - if (rdtp->dynticks_nmi_nesting == 0 ||
> - --rdtp->dynticks_nmi_nesting != 0)
> + /*
> + * Check for ->dynticks_nmi_nesting underflow and bad ->dynticks.
> + * (We are exiting an NMI handler, so RCU better be paying attention
> + * to us!)
> + */
> + WARN_ON_ONCE(rdtp->dynticks_nmi_nesting <= 0);
> + WARN_ON_ONCE(!(atomic_read(&rdtp->dynticks) & 0x1));
> +
> + /*
> + * If the nesting level is not 1, the CPU wasn't RCU-idle, so
> + * leave it in non-RCU-idle state.
> + */
> + if (rdtp->dynticks_nmi_nesting != 1) {
> + rdtp->dynticks_nmi_nesting -= 2;
> return;
> + }
> +
> + /* This NMI interrupted an RCU-idle CPU, restore RCU-idleness. */
> + rdtp->dynticks_nmi_nesting = 0;
> /* CPUs seeing atomic_inc() must see prior RCU read-side crit sects */
> smp_mb__before_atomic(); /* See above. */
> atomic_inc(&rdtp->dynticks);
>
> --
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> the body of a message to majord...@vger.kernel.org
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>
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[PATCH] Fix -Wmaybe-uninitialized warning seen with make menuconfig
Fixes the following :
scripts/kconfig/menu.c: In function 'get_symbol_str':
scripts/kconfig/menu.c:590:18: warning: 'jump' may be used uninitialized in
this function [-Wmaybe-uninitialized]
jump->offset = strlen(r->s);
^
scripts/kconfig/menu.c:551:19: note: 'jump' was declared here
struct jump_key *jump;
Signed-off-by: Anish Bhatt
---
scripts/kconfig/menu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index a26cc5d..584e0fc 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -548,7 +548,7 @@ static void get_prompt_str(struct gstr *r, struct property
*prop,
{
int i, j;
struct menu *submenu[8], *menu, *location = NULL;
- struct jump_key *jump;
+ struct jump_key *jump = NULL;
str_printf(r, _("Prompt: %s\n"), _(prop->text));
menu = prop->menu->parent;
--
2.1.3
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Re: [PATCH] Documentation: memory-barriers: Fix typo in the first example
Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it. To match the
> sequence of events, the values of 'A' and 'B' should be loaded
> into 'x' and 'y' respectively.
>
> Signed-off-by: Srikanth Thokala
> ---
> Documentation/memory-barriers.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt
> b/Documentation/memory-barriers.txt
> index 22a969c..2770bce 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -115,8 +115,8 @@ For example, consider the following sequence of events:
> CPU 1 CPU 2
> === ===
> { A == 1; B == 2 }
> - A = 3; x = B;
> - B = 4; y = A;
> + A = 3; x = A;
> + B = 4; y = B;
>
> The set of accesses as seen by the memory system in the middle can be
> arranged
> in 24 different combinations:
> --
> 1.9.1
>
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Re: [PATCH v9 2/6] arm64: ptrace: allow tracer to skip a system call
On 11/26/2014 10:02 PM, Will Deacon wrote: On Wed, Nov 26, 2014 at 04:49:47AM +, AKASHI Takahiro wrote: If tracer modifies a syscall number to -1, this traced system call should be skipped with a return value specified in x0. This patch implements this semantics. Please note: * syscall entry tracing and syscall exit tracing (ftrace tracepoint and audit) are always executed, if enabled, even when skipping a system call (that is, -1). In this way, we can avoid a potential bug where audit_syscall_entry() might be called without audit_syscall_exit() at the previous system call being called, that would cause OOPs in audit_syscall_entry(). Signed-off-by: AKASHI Takahiro --- arch/arm64/kernel/entry.S | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 726b910..946ec52 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -161,6 +161,7 @@ */ sc_nr .reqx25 // number of system calls scno .reqx26 // syscall number +scno_w .reqw26 // syscall number (lower 32 bits) stbl .reqx27 // syscall table pointer tsk .reqx28 // current thread_info @@ -668,8 +669,14 @@ ENDPROC(el0_svc) * switches, and waiting for our parent to respond. */ __sys_trace: - mov x0, sp + cmp scno_w, #-1 // set default errno for I hate that we have to use scno_w, but the only alternative I can think of is using w8 directly, which isn't any better and doesn't work for compat. Ho-hum, I guess we'll stick with what you have. The possible approaches might be: * use 32-bit registers for scno & sc_nr and use "sxtw scno, w8," or * use an extra reg like __sys_trace: mov x0, #0x cmp scno, x0 b.ne 1f + b.ne1f // user-issued syscall(-1) + mov x0, #-ENOSYS + str x0, [sp] Can you use #S_X0 here for clarity, please? Okey. +1: mov x0, sp bl syscall_trace_enter + cmp w0, #-1 // skip the syscall? + b.eq__sys_trace_return_skipped adr lr, __sys_trace_return // return address uxtwscno, w0// syscall number (possibly new) mov x1, sp // pointer to regs @@ -684,6 +691,7 @@ __sys_trace: __sys_trace_return: str x0, [sp]// save returned x0 and update this guy too. Sure. -Takahiro AKASHI Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH net-next] vhost: remove unnecessary forward declarations in vhost.h
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index 3eda654..7d039ef 100644
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -12,8 +12,6 @@
#include
#include
-struct vhost_device;
-
struct vhost_work;
typedef void (*vhost_work_fn_t)(struct vhost_work *work);
@@ -54,8 +52,6 @@ struct vhost_log {
u64 len;
};
-struct vhost_virtqueue;
-
/* The virtqueue structure describes a queue attached to a device. */
struct vhost_virtqueue {
struct vhost_dev *dev;
--
1.9.1
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Re: [PATCH] xen: privcmd: schedule() after private hypercall when non CONFIG_PREEMPT
On 11/26/2014 11:26 PM, Luis R. Rodriguez wrote: From: "Luis R. Rodriguez" Some folks had reported that some xen hypercalls take a long time to complete when issued from the userspace private ioctl mechanism, this can happen for instance with some hypercalls that have many sub-operations, this can happen for instance on hypercalls that use multi-call feature whereby Xen lets one hypercall batch out a series of other hypercalls on the hypervisor. At times such hypercalls can even end up triggering the TASK_UNINTERRUPTIBLE hanger check (default 120 seconds), this a non-issue issue on preemptible kernels though as the kernel may deschedule such long running tasks. Xen for instance supports multicalls to be preempted as well, this is what Xen calls continuation (see xen commit 42217cbc5b which introduced this [0]). On systems without CONFIG_PREEMPT though -- a kernel with voluntary or no preemption -- a long running hypercall will not be descheduled until the hypercall is complete and the ioctl returns to user space. To help with this David had originally implemented support for use of preempt_schedule_irq() [1] for non CONFIG_PREEMPT kernels. This solution never went upstream though and upon review to help refactor this I've concluded that usage of preempt_schedule_irq() would be a bit abussive of existing APIs -- for a few reasons: 0) we want to avoid spreading its use on non CONFIG_PREEMPT kernels 1) we want try to consider solutions that might work for other hypervisors for this same problem, and identify it its an issue even present on other hypervisors or if this is a self inflicted architectural issue caused by use of multicalls 2) there is no documentation or profiling of the exact hypercalls that were causing these issues, nor do we have any context to help evaluate this any further I at least checked with kvm folks and it seems hypercall preemption is not needed there. We can survey other hypervisors... If 'something like preemption' is needed then CONFIG_PREEMPT should just be enabled and encouraged, it seems we want to encourage CONFIG_PREEMPT on xen, specially when multicalls are used. In the meantime this tries to address a solution to help xen on non CONFIG_PREEMPT kernels. One option tested and evaluated was to put private hypercalls in process context, however this would introduce complexities such originating hypercalls from different contexts. Current xen hypercall callback handlers would need to be changed per architecture, for instance, we'd also incur the cost of switching states from user / kernel (this cost is also present if preempt_schedule_irq() is used). There may be other issues which could be introduced with this strategy as well. The simplest *shared* alternative is instead to just explicitly schedule() at the end of a private hypercall on non preempt kernels. This forces our private hypercall call mechanism to try to be fair only on non CONFIG_PREEMPT kernels at the cost of more context switch but keeps the private hypercall context intact. [0] http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=42217cbc5b3e84b8c145d8cfb62dd5de0134b9e8;hp=3a0b9c57d5c9e82c55dd967c84dd06cb43c49ee9 [1] http://ftp.suse.com/pub/people/mcgrof/xen-preempt-hypercalls/0001-x86-xen-allow-privcmd-hypercalls-to-be-preempted.patch Cc: Davidlohr Bueso Cc: Joerg Roedel Cc: Borislav Petkov Cc: Konrad Rzeszutek Wilk Cc: Jan Beulich Cc: Juergen Gross Cc: Olaf Hering Cc: David Vrabel Signed-off-by: Luis R. Rodriguez --- drivers/xen/privcmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c index 569a13b..e29edba 100644 --- a/drivers/xen/privcmd.c +++ b/drivers/xen/privcmd.c @@ -60,6 +60,9 @@ static long privcmd_ioctl_hypercall(void __user *udata) hypercall.arg[0], hypercall.arg[1], hypercall.arg[2], hypercall.arg[3], hypercall.arg[4]); +#ifndef CONFIG_PREEMPT + schedule(); +#endif return ret; } Sorry, I don't think this will solve anything. You're calling schedule() right after the long running hypercall just nanoseconds before returning to the user. I suppose you were mislead by the "int 0x82" in [0]. This is the hypercall from the kernel into the hypervisor, e.g. inside of privcmd_call(). Juergen -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH net-next V3] tun/macvtap: use consume_skb() instead of kfree_skb() when needed
To be more friendly with drop monitor, we should only call kfree_skb() when the packets were dropped and use consume_skb() in other cases. Cc: Eric Dumazet Signed-off-by: Jason Wang --- Changes from V2: - use unlikely() when necessary Changes from V1: - check the return value of tun/macvtap_put_user() --- drivers/net/macvtap.c | 5 - drivers/net/tun.c | 5 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c index 42a80d3..86f6bf8 100644 --- a/drivers/net/macvtap.c +++ b/drivers/net/macvtap.c @@ -862,7 +862,10 @@ static ssize_t macvtap_do_read(struct macvtap_queue *q, } iov_iter_init(&iter, READ, iv, segs, len); ret = macvtap_put_user(q, skb, &iter); - kfree_skb(skb); + if (unlikely(ret < 0)) + kfree_skb(skb); + else + consume_skb(skb); break; } diff --git a/drivers/net/tun.c b/drivers/net/tun.c index ac53a73..82a9bf0 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1363,7 +1363,10 @@ static ssize_t tun_do_read(struct tun_struct *tun, struct tun_file *tfile, iov_iter_init(&iter, READ, iv, segs, len); ret = tun_put_user(tun, tfile, skb, &iter); - kfree_skb(skb); + if (unlikely(ret < 0)) + kfree_skb(skb); + else + consume_skb(skb); return ret; } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL 00/25] phy: for 3.19
Hi Greg, Please find the pull request for 3.19 merge window. This contains improvements in phy core dealing with non-dt boot. It also adds 3 new phy drivers armada375-usb2, berlin-usb and miphy28lp. There is a patch that touches drivers/pinctrl since one of the PHY drivers is present there and it has to be modified to use the modified devm_phy_create API. Let me know If I have to change something. Thanks Kishon The following changes since commit 206c5f60a3d902bc4b56dab2de3e88de5eb06108: Linux 3.18-rc4 (2014-11-09 14:55:29 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git tags/for-3.19 for you to fetch changes up to eee47538ec1f26198cf5da675975b61d7f16135b: phy: add support for USB cluster on the Armada 375 SoC (2014-11-26 11:07:14 +0530) Improvements in phy-core specifically on PHY core finds the PHY in the case of non-dt boot. Adds three new PHY drivers using the PHY framework and some miscellaneous fixes and cleanups. Andrew Lunn (1): Phy: DT binding documentation for Marvell MVEBU SATA phy. Antoine Tenart (2): phy: add the Berlin USB PHY driver Documentation: bindings: add doc for the Berlin USB PHY Gabriel FERNANDEZ (6): phy: Add PHY header file for DT x Driver defines phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY phy: miphy28lp: Add SSC support for SATA phy: miphy28lp: Add SSC support for PCIE phy: miphy28lp: Tune tx impedance across Soc cuts Gregory CLEMENT (3): phy: Use PTR_ERR_OR_ZERO to fix warning raised by coccinelle Phy: DT binding documentation for the Armada 375 USB cluster binding phy: add support for USB cluster on the Armada 375 SoC Heikki Krogerus (5): phy: safer to_phy() macro phy: improved lookup method phy: twl4030: use the new lookup method phy: remove the old lookup method usb: dwc3: host: convey the PHYs to xhci Kishon Vijay Abraham I (1): phy: phy-core: use the np present in of_phandle_args to get the PHY Roman Byshko (1): phy: sun4i: add support for USB phy0 Sebastian Hesselbarth (3): phy: berlin-sata: Move PHY_BASE into private data struct phy: berlin-sata: Add support for BG2 SATA PHY phy: berlin-sata: Document BG2 compatible Vivek Gautam (3): phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS Documentation/devicetree/bindings/ata/marvell.txt |6 + .../devicetree/bindings/phy/berlin-sata-phy.txt|4 +- .../devicetree/bindings/phy/berlin-usb-phy.txt | 16 + .../devicetree/bindings/phy/phy-miphy28lp.txt | 128 ++ .../devicetree/bindings/phy/phy-mvebu.txt | 43 + .../devicetree/bindings/phy/samsung-phy.txt|6 + Documentation/phy.txt | 60 +- drivers/phy/Kconfig| 23 +- drivers/phy/Makefile |3 + drivers/phy/phy-armada375-usb2.c | 158 +++ drivers/phy/phy-bcm-kona-usb2.c|2 +- drivers/phy/phy-berlin-sata.c | 36 +- drivers/phy/phy-berlin-usb.c | 223 drivers/phy/phy-core.c | 115 +- drivers/phy/phy-exynos-dp-video.c |2 +- drivers/phy/phy-exynos-mipi-video.c|2 +- drivers/phy/phy-exynos5-usbdrd.c | 139 ++- drivers/phy/phy-exynos5250-sata.c |2 +- drivers/phy/phy-hix5hd2-sata.c |7 +- drivers/phy/phy-miphy28lp.c| 1283 drivers/phy/phy-miphy365x.c|7 +- drivers/phy/phy-mvebu-sata.c |2 +- drivers/phy/phy-omap-usb2.c|2 +- drivers/phy/phy-qcom-apq8064-sata.c|3 +- drivers/phy/phy-qcom-ipq806x-sata.c|3 +- drivers/phy/phy-rcar-gen2.c|2 +- drivers/phy/phy-samsung-usb2.c |3 +- drivers/phy/phy-spear1310-miphy.c |2 +- drivers/phy/phy-spear1340-miphy.c |2 +- drivers/phy/phy-stih407-usb.c |2 +- drivers/phy/phy-stih41x-usb.c |7 +- drivers/phy/phy-sun4i-usb.c| 11 +- drivers/phy/phy-ti-pipe3.c |2 +- drivers/phy/phy-twl4030-usb.c |9 +- drivers/phy/phy-xgene.c|2 +- drivers/pinctrl/pinctrl-tegra-xusb.c |4 +- drivers/usb/dwc3/host.c| 22 +- include/dt-bindings/phy/phy.h |
[PATCH 02/25] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
From: Gabriel FERNANDEZ
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: alexandre torgue
Signed-off-by: Giuseppe Cavallaro
Signed-off-by: Gabriel Fernandez
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 126
1 file changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 000..b7c13ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,126 @@
+STMicroelectronics STi MIPHY28LP PHY binding
+
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA, PCIe or USB3.
+
+Required properties (controller (parent) node):
+- compatible : Should be "st,miphy28lp-phy".
+- st,syscfg: Should be a phandle of the system configuration register group
+ which contain the SATA, PCIe or USB3 mode setting bits.
+
+Required nodes : A sub-node is required for each channel the controller
+ provides. Address range information including the usual
+ 'reg' and 'reg-names' properties are used inside these
+ nodes to describe the controller's topology. These nodes
+ are translated by the driver's .xlate() function.
+
+Required properties (port (child) node):
+- #phy-cells : Should be 1 (See second example)
+ Cell after port phandle is device type from:
+ - PHY_TYPE_SATA
+ - PHY_TYPE_PCI
+ - PHY_TYPE_USB3
+- reg : Address and length of the register set for the device.
+- reg-names: The names of the register addresses corresponding to the
registers
+ filled in "reg". It can also contain the offset of the system
configuration
+ registers used as glue-logic to setup the device for
SATA/PCIe or USB3
+ devices.
+- resets : phandle to the parent reset controller.
+- reset-names : Associated name must be "miphy-sw-rst".
+
+Optional properties (port (child) node):
+- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic.
This
+ is not available in all the MiPHY. For example, for
STiH407, only the
+ MiPHY0 has this bit.
+- st,osc-force-ext : to select the external oscillator. This can change
from
+ different MiPHY inside the same SoC.
+- st,sata_gen : to select which SATA_SPDMODE has to be set in the
SATA system config
+ register.
+- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative
line and positive
+ line).
+
+example:
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>,
+ <0x114 0x4>, /* sysctrl MiPHY cntrl */
+ <0x818 0x4>, /* sysctrl MiPHY status*/
+ <0xe0 0x4>, /* sysctrl PCIe */
+ <0xec 0x4>; /* sysctrl SATA */
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+ st,osc-rdy;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>,
+ <0x118 0x4>,
+ <0x81c 0x4>,
+ <0xe4 0x4>,
+ <0xf0 0x4>;
+ reg-names = "sata-up",
+ "pcie-up",
+
[PATCH 1/6] ACPICA: iASL: Add support for to_PLD macro.
From: Bob Moore
This macro is intended to simplify the constuction of _PLD buffers.
NOTE: Prototype only, subject to change before this macro is
added to the ACPI specification. David E. Box.
Signed-off-by: David E. Box
Signed-off-by: Bob Moore
Signed-off-by: Lv Zheng
---
drivers/acpi/acpica/utxface.c |4 +++-
include/acpi/acbuffer.h | 14 +++---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/acpi/acpica/utxface.c b/drivers/acpi/acpica/utxface.c
index 502a849..49c873c 100644
--- a/drivers/acpi/acpica/utxface.c
+++ b/drivers/acpi/acpica/utxface.c
@@ -531,7 +531,9 @@ acpi_decode_pld_buffer(u8 *in_buffer,
ACPI_MOVE_32_TO_32(&dword, &buffer[0]);
pld_info->revision = ACPI_PLD_GET_REVISION(&dword);
pld_info->ignore_color = ACPI_PLD_GET_IGNORE_COLOR(&dword);
- pld_info->color = ACPI_PLD_GET_COLOR(&dword);
+ pld_info->red = ACPI_PLD_GET_RED(&dword);
+ pld_info->green = ACPI_PLD_GET_GREEN(&dword);
+ pld_info->blue = ACPI_PLD_GET_BLUE(&dword);
/* Second 32-bit DWord */
diff --git a/include/acpi/acbuffer.h b/include/acpi/acbuffer.h
index 88cb477..d5ec6c8 100644
--- a/include/acpi/acbuffer.h
+++ b/include/acpi/acbuffer.h
@@ -111,7 +111,9 @@ struct acpi_gtm_info {
struct acpi_pld_info {
u8 revision;
u8 ignore_color;
- u32 color;
+ u8 red;
+ u8 green;
+ u8 blue;
u16 width;
u16 height;
u8 user_visible;
@@ -155,8 +157,14 @@ struct acpi_pld_info {
#define ACPI_PLD_GET_IGNORE_COLOR(dword)ACPI_GET_BITS (dword, 7,
ACPI_1BIT_MASK)
#define ACPI_PLD_SET_IGNORE_COLOR(dword,value) ACPI_SET_BITS (dword, 7,
ACPI_1BIT_MASK, value)/* Offset 7, Len 1 */
-#define ACPI_PLD_GET_COLOR(dword) ACPI_GET_BITS (dword, 8,
ACPI_24BIT_MASK)
-#define ACPI_PLD_SET_COLOR(dword,value) ACPI_SET_BITS (dword, 8,
ACPI_24BIT_MASK, value) /* Offset 8, Len 24 */
+#define ACPI_PLD_GET_RED(dword) ACPI_GET_BITS (dword, 8,
ACPI_8BIT_MASK)
+#define ACPI_PLD_SET_RED(dword,value) ACPI_SET_BITS (dword, 8,
ACPI_8BIT_MASK, value)/* Offset 8, Len 8 */
+
+#define ACPI_PLD_GET_GREEN(dword) ACPI_GET_BITS (dword, 16,
ACPI_8BIT_MASK)
+#define ACPI_PLD_SET_GREEN(dword,value) ACPI_SET_BITS (dword, 16,
ACPI_8BIT_MASK, value) /* Offset 16, Len 8 */
+
+#define ACPI_PLD_GET_BLUE(dword)ACPI_GET_BITS (dword, 24,
ACPI_8BIT_MASK)
+#define ACPI_PLD_SET_BLUE(dword,value) ACPI_SET_BITS (dword, 24,
ACPI_8BIT_MASK, value) /* Offset 24, Len 8 */
/* Second 32-bit dword, bits 33:63 */
--
1.7.10
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[PATCH 3/6] ACPICA: Disassembler: Add support for C-style operators and expressions.
From: Bob Moore
Now emit ASL+ code which includes C-style operators.
Optionally, legacy text ASL operators can still be emitted.
This patch only affects compiler/disassembler support which is not in the
Linux kernel.
Signed-off-by: Bob Moore
Signed-off-by: Lv Zheng
---
drivers/acpi/acpica/acglobal.h |1 +
drivers/acpi/acpica/aclocal.h |2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h
index ebf02cc..7f60582 100644
--- a/drivers/acpi/acpica/acglobal.h
+++ b/drivers/acpi/acpica/acglobal.h
@@ -305,6 +305,7 @@ ACPI_INIT_GLOBAL(u8, acpi_gbl_db_output_flags,
ACPI_DB_CONSOLE_OUTPUT);
ACPI_INIT_GLOBAL(u8, acpi_gbl_no_resource_disassembly, FALSE);
ACPI_INIT_GLOBAL(u8, acpi_gbl_ignore_noop_operator, FALSE);
+ACPI_INIT_GLOBAL(u8, acpi_gbl_cstyle_disassembly, TRUE);
ACPI_GLOBAL(u8, acpi_gbl_db_opt_disasm);
ACPI_GLOBAL(u8, acpi_gbl_db_opt_verbose);
diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index c00e7e4..1c218d9 100644
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -722,6 +722,7 @@ union acpi_parse_value {
ACPI_DISASM_ONLY_MEMBERS (\
u8 disasm_flags; /* Used during AML
disassembly */\
u8 disasm_opcode; /* Subtype used for
disassembly */\
+ char*operator_symbol;/* Used for C-style
operator name strings */\
charaml_op_name[16])/* Op name
(debug only) */
/* Flags for disasm_flags field above */
@@ -827,6 +828,7 @@ struct acpi_parse_state {
#define ACPI_PARSEOP_EMPTY_TERMLIST 0x04
#define ACPI_PARSEOP_PREDEF_CHECKED 0x08
#define ACPI_PARSEOP_SPECIAL0x10
+#define ACPI_PARSEOP_COMPOUND 0x20
/*
*
--
1.7.10
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[PATCH 04/25] phy: miphy28lp: Add SSC support for SATA
From: Gabriel FERNANDEZ
This patch to tune on/off the ssc on miphy sata setup.
User can now enable ssc via dt blob, it is useful to reduce
effects of EMI.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/phy-miphy28lp.txt |1 +
drivers/phy/phy-miphy28lp.c| 46
2 files changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index b7c13ad..4a3b4af 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -39,6 +39,7 @@ Optional properties (port (child) node):
register.
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative
line and positive
line).
+- st,scc-on: enable ssc to reduce effects of EMI (only for sata or
PCIe).
example:
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index 7d592e6..d2f797c 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -191,6 +191,8 @@
#define SYSCFG_PCIE_PCIE_VAL 0x80
#define SATA_SPDMODE 1
+#define MIPHY_SATA_BANK_NB 3
+
struct miphy28lp_phy {
struct phy *phy;
struct miphy28lp_dev *phydev;
@@ -200,6 +202,7 @@ struct miphy28lp_phy {
bool osc_force_ext;
bool osc_rdy;
bool px_rx_pol_inv;
+ bool ssc;
struct reset_control *miphy_rst;
@@ -550,6 +553,44 @@ static inline void miphy28_usb3_miphy_reset(struct
miphy28lp_phy *miphy_phy)
writeb_relaxed(0x00, base + MIPHY_CONF);
}
+static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+ u8 val;
+
+ /* Compensate Tx impedance to avoid out of range values */
+ /*
+* Enable the SSC on PLL for all banks
+* SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+*/
+ val = readb_relaxed(base + MIPHY_BOUNDARY_2);
+ val |= SSC_EN_SW;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
+
+ val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
+ val |= SSC_SEL;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
+
+ for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
+ writeb_relaxed(val, base + MIPHY_CONF);
+
+ /* Add value to each reference clock cycle */
+ /* and define the period length of the SSC */
+ writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
+ writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
+ writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
+
+ /* Clear any previous request */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+
+ /* requests the PLL to take in account new parameters */
+ writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
+
+ /* To be sure there is no other pending requests */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+ }
+}
+
static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
{
void __iomem *base = miphy_phy->base;
@@ -585,6 +626,9 @@ static inline int miphy28lp_configure_sata(struct
miphy28lp_phy *miphy_phy)
writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
}
+ if (miphy_phy->ssc)
+ miphy_sata_tune_ssc(miphy_phy);
+
return 0;
}
@@ -1064,6 +1108,8 @@ static int miphy28lp_of_probe(struct device_node *np,
miphy_phy->px_rx_pol_inv =
of_property_read_bool(np, "st,px_rx_pol_inv");
+ miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
+
of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
if (!miphy_phy->sata_gen)
miphy_phy->sata_gen = SATA_GEN1;
--
1.7.9.5
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[PATCH 03/25] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
From: Gabriel FERNANDEZ The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue Signed-off-by: Giuseppe Cavallaro Signed-off-by: Gabriel Fernandez Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/Kconfig |8 + drivers/phy/Makefile|1 + drivers/phy/phy-miphy28lp.c | 1177 +++ 3 files changed, 1186 insertions(+) create mode 100644 drivers/phy/phy-miphy28lp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 2a436e6..cfaced9 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -38,6 +38,14 @@ config PHY_MVEBU_SATA depends on OF select GENERIC_PHY +config PHY_MIPHY28LP + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" + depends on ARCH_STI + select GENERIC_PHY + help + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) + that is part of STMicroelectronics STiH407 SoC. + config PHY_MIPHY365X tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series" depends on ARCH_STI diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c4590fc..30d90a8 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o +obj-$(CONFIG_PHY_MIPHY28LP)+= phy-miphy28lp.o obj-$(CONFIG_PHY_MIPHY365X)+= phy-miphy365x.o obj-$(CONFIG_PHY_RCAR_GEN2)+= phy-rcar-gen2.o obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c new file mode 100644 index 000..7d592e6 --- /dev/null +++ b/drivers/phy/phy-miphy28lp.c @@ -0,0 +1,1177 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). + * + * Author: Alexandre Torgue + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* MiPHY registers */ +#define MIPHY_CONF_RESET 0x00 +#define RST_APPLI_SW BIT(0) +#define RST_CONF_SWBIT(1) +#define RST_MACRO_SW BIT(2) + +#define MIPHY_RESET0x01 +#define RST_PLL_SW BIT(0) +#define RST_COMP_SWBIT(2) + +#define MIPHY_STATUS_1 0x02 +#define PHY_RDYBIT(0) +#define HFC_RDYBIT(1) +#define HFC_PLLBIT(2) + +#define MIPHY_CONTROL 0x04 +#define TERM_EN_SW BIT(2) +#define DIS_LINK_RST BIT(3) +#define AUTO_RST_RXBIT(4) +#define PX_RX_POL BIT(5) + +#define MIPHY_BOUNDARY_SEL 0x0a +#define TX_SEL BIT(6) +#define SSC_SELBIT(4) +#define GENSEL_SEL BIT(0) + +#define MIPHY_BOUNDARY_1 0x0b +#define MIPHY_BOUNDARY_2 0x0c +#define SSC_EN_SW BIT(2) + +#define MIPHY_PLL_CLKREF_FREQ 0x0d +#define MIPHY_SPEED0x0e +#define TX_SPDSEL_80DEC0 +#define TX_SPDSEL_40DEC1 +#define TX_SPDSEL_20DEC2 +#define RX_SPDSEL_80DEC0 +#define RX_SPDSEL_40DEC(1 << 2) +#define RX_SPDSEL_20DEC(2 << 2) + +#define MIPHY_CONF 0x0f +#define MIPHY_CTRL_TEST_SEL0x20 +#define MIPHY_CTRL_TEST_1 0x21 +#define MIPHY_CTRL_TEST_2 0x22 +#define MIPHY_CTRL_TEST_3 0x23 +#define MIPHY_CTRL_TEST_4 0x24 +#define MIPHY_FEEDBACK_TEST0x25 +#define MIPHY_DEBUG_BUS0x26 +#define MIPHY_DEBUG_STATUS_MSB 0x27 +#define MIPHY_DEBUG_STATUS_LSB 0x28 +#define MIPHY_PWR_RAIL_1 0x29 +#define MIPHY_PWR_RAIL_2 0x2a +#define MIPHY_SYNCHAR_CONTROL 0x30 + +#define MIPHY_COMP_FSM_1 0x3a +#define COMP_START BIT(6) + +#define MIPHY_COMP_FSM_6 0x3f +#define COMP_DONE BIT(7) + +#define MIPHY_COMP_POSTP 0x42 +#define MIPHY_TX_CTRL_10x49 +#define TX_REG_STEP_0V 0 +#define TX_REG_STEP_P_25MV 1 +#define TX_REG_STEP_P_50MV 2 +#define TX_REG_STEP_N_25MV 7 +#define TX_REG_STEP_N_50MV 6 +#define TX_REG_STEP_N_75MV 5 + +#define MIPHY_TX_CTRL_20x4a +#define TX_SL
Re: [RFC PATCH] mm/thp: Always allocate transparent hugepages on local node
David Rientjes writes:
> On Mon, 24 Nov 2014, Kirill A. Shutemov wrote:
>
>> > This make sure that we try to allocate hugepages from local node. If
>> > we can't we fallback to small page allocation based on
>> > mempolicy. This is based on the observation that allocating pages
>> > on local node is more beneficial that allocating hugepages on remote node.
>>
>> Local node on allocation is not necessary local node for use.
>> If policy says to use a specific node[s], we should follow.
>>
>
> True, and the interaction between thp and mempolicies is fragile: if a
> process has a MPOL_BIND mempolicy over a set of nodes, that does not
> necessarily mean that we want to allocate thp remotely if it will always
> be accessed remotely. It's simple to benchmark and show that remote
> access latency of a hugepage can exceed that of local pages. MPOL_BIND
> itself is a policy of exclusion, not inclusion, and it's difficult to
> define when local pages and its cost of allocation is better than remote
> thp.
>
> For MPOL_BIND, if the local node is allowed then thp should be forced from
> that node, if the local node is disallowed then allocate from any node in
> the nodemask. For MPOL_INTERLEAVE, I think we should only allocate thp
> from the next node in order, otherwise fail the allocation and fallback to
> small pages. Is this what you meant as well?
>
Something like below
struct page *alloc_hugepage_vma(gfp_t gfp, struct vm_area_struct *vma,
unsigned long addr, int order)
{
struct page *page;
nodemask_t *nmask;
struct mempolicy *pol;
int node = numa_node_id();
unsigned int cpuset_mems_cookie;
retry_cpuset:
pol = get_vma_policy(vma, addr);
cpuset_mems_cookie = read_mems_allowed_begin();
if (unlikely(pol->mode == MPOL_INTERLEAVE)) {
unsigned nid;
nid = interleave_nid(pol, vma, addr, PAGE_SHIFT + order);
mpol_cond_put(pol);
page = alloc_page_interleave(gfp, order, nid);
if (unlikely(!page &&
read_mems_allowed_retry(cpuset_mems_cookie)))
goto retry_cpuset;
return page;
}
nmask = policy_nodemask(gfp, pol);
if (!nmask || node_isset(node, *nmask)) {
mpol_cond_put(pol);
page = alloc_hugepage_exact_node(node, gfp, order);
if (unlikely(!page &&
read_mems_allowed_retry(cpuset_mems_cookie)))
goto retry_cpuset;
return page;
}
/*
* if current node is not part of node mask, try
* the allocation from any node, and we can do retry
* in that case.
*/
page = __alloc_pages_nodemask(gfp, order,
policy_zonelist(gfp, pol, node),
nmask);
mpol_cond_put(pol);
if (unlikely(!page && read_mems_allowed_retry(cpuset_mems_cookie)))
goto retry_cpuset;
return page;
}
-aneesh
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[PATCH 05/25] phy: miphy28lp: Add SSC support for PCIE
From: Gabriel FERNANDEZ
SSC is the technique of modulating the operating frequency of a signal
slightly to spread its radiated emissions over a range of frequencies.
This reduction in the maximum emission for a given frequency helps meet
radiated emission requirements.
These settings are applicable for PCIE with Internal clock.
Signed-off-by: Harsh Gupta
Signed-off-by: Gabriel Fernandez
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-miphy28lp.c | 44 +++
1 file changed, 44 insertions(+)
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index d2f797c..d8ff895 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -192,6 +192,7 @@
#define SATA_SPDMODE 1
#define MIPHY_SATA_BANK_NB 3
+#define MIPHY_PCIE_BANK_NB 2
struct miphy28lp_phy {
struct phy *phy;
@@ -591,6 +592,46 @@ static void miphy_sata_tune_ssc(struct miphy28lp_phy
*miphy_phy)
}
}
+static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+ u8 val;
+
+ /* Compensate Tx impedance to avoid out of range values */
+ /*
+* Enable the SSC on PLL for all banks
+* SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+*/
+ val = readb_relaxed(base + MIPHY_BOUNDARY_2);
+ val |= SSC_EN_SW;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
+
+ val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
+ val |= SSC_SEL;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
+
+ for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
+ writeb_relaxed(val, base + MIPHY_CONF);
+
+ /* Validate Step component */
+ writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
+ writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
+
+ /* Validate Period component */
+ writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
+ writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
+
+ /* Clear any previous request */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+
+ /* requests the PLL to take in account new parameters */
+ writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
+
+ /* To be sure there is no other pending requests */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+ }
+}
+
static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
{
void __iomem *base = miphy_phy->base;
@@ -659,6 +700,9 @@ static inline int miphy28lp_configure_pcie(struct
miphy28lp_phy *miphy_phy)
if (err)
return err;
+ if (miphy_phy->ssc)
+ miphy_pcie_tune_ssc(miphy_phy);
+
return 0;
}
--
1.7.9.5
--
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[PATCH 4/6] ACPICA: Disassembler: Update for C-style expressions.
From: Bob Moore
Add extra set of parens for assignments within an expression.
This patch only affects compiler support which is not in the Linux kernel.
Signed-off-by: Bob Moore
Signed-off-by: Lv Zheng
---
drivers/acpi/acpica/aclocal.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index 1c218d9..80c74e9 100644
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -829,6 +829,7 @@ struct acpi_parse_state {
#define ACPI_PARSEOP_PREDEF_CHECKED 0x08
#define ACPI_PARSEOP_SPECIAL0x10
#define ACPI_PARSEOP_COMPOUND 0x20
+#define ACPI_PARSEOP_ASSIGNMENT 0x40
/*
*
--
1.7.10
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[PATCH 08/25] phy: sun4i: add support for USB phy0
From: Roman Byshko
The driver for sun4i USB phys currently supports
only phy1 and phy2 which are used for USB host
controllers. This patch adds support for USB phy0,
which is used by the musb hdrc USB controller.
Signed-off-by: Roman Byshko
Acked-by: Maxime Ripard
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-sun4i-usb.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0baf5ef..6bd2b0c 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -157,6 +157,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ /* Enable USB 45 Ohm resistor calibration */
+ if (phy->index == 0)
+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+
/* Adjust PHY's magnitude and rate */
sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
@@ -213,7 +217,7 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
{
struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
- if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
+ if (args->args[0] >= data->num_phys)
return ERR_PTR(-ENODEV);
return data->phys[args->args[0]].phy;
@@ -255,8 +259,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (IS_ERR(data->base))
return PTR_ERR(data->base);
- /* Skip 0, 0 is the phy for otg which is not yet supported. */
- for (i = 1; i < data->num_phys; i++) {
+ for (i = 0; i < data->num_phys; i++) {
struct sun4i_usb_phy *phy = data->phys + i;
char name[16];
--
1.7.9.5
--
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[PATCH 06/25] phy: miphy28lp: Tune tx impedance across Soc cuts
From: Gabriel FERNANDEZ
This patch to compensate tx impedance (Sata, PCIe)
depending on Soc cuts the kernel is built for.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/phy-miphy28lp.txt |1 +
drivers/phy/phy-miphy28lp.c| 16
2 files changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index 4a3b4af..46a135d 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -40,6 +40,7 @@ Optional properties (port (child) node):
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative
line and positive
line).
- st,scc-on: enable ssc to reduce effects of EMI (only for sata or
PCIe).
+- st,tx-impedance-comp : to compensate tx impedance avoiding out of range
values.
example:
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index d8ff895..87dcc9a 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -204,6 +204,7 @@ struct miphy28lp_phy {
bool osc_rdy;
bool px_rx_pol_inv;
bool ssc;
+ bool tx_impedance;
struct reset_control *miphy_rst;
@@ -632,6 +633,12 @@ static void miphy_pcie_tune_ssc(struct miphy28lp_phy
*miphy_phy)
}
}
+static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
+{
+ /* Compensate Tx impedance to avoid out of range values */
+ writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
+}
+
static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
{
void __iomem *base = miphy_phy->base;
@@ -670,6 +677,9 @@ static inline int miphy28lp_configure_sata(struct
miphy28lp_phy *miphy_phy)
if (miphy_phy->ssc)
miphy_sata_tune_ssc(miphy_phy);
+ if (miphy_phy->tx_impedance)
+ miphy_tune_tx_impedance(miphy_phy);
+
return 0;
}
@@ -703,6 +713,9 @@ static inline int miphy28lp_configure_pcie(struct
miphy28lp_phy *miphy_phy)
if (miphy_phy->ssc)
miphy_pcie_tune_ssc(miphy_phy);
+ if (miphy_phy->tx_impedance)
+ miphy_tune_tx_impedance(miphy_phy);
+
return 0;
}
@@ -1154,6 +1167,9 @@ static int miphy28lp_of_probe(struct device_node *np,
miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
+ miphy_phy->tx_impedance =
+ of_property_read_bool(np, "st,tx-impedance-comp");
+
of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
if (!miphy_phy->sata_gen)
miphy_phy->sata_gen = SATA_GEN1;
--
1.7.9.5
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[PATCH 07/25] phy: phy-core: use the np present in of_phandle_args to get the PHY
Instead of using the node pointer of the PHY provider and then scanning its
child nodes to get a reference to the PHY, directly use the node pointer
present in of_phandle_args to get a reference to the PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-core.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index ff5eec5..1606ce9 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -414,21 +414,13 @@ struct phy *of_phy_simple_xlate(struct device *dev,
struct of_phandle_args
{
struct phy *phy;
struct class_dev_iter iter;
- struct device_node *node = dev->of_node;
- struct device_node *child;
class_dev_iter_init(&iter, phy_class, NULL, NULL);
while ((dev = class_dev_iter_next(&iter))) {
phy = to_phy(dev);
- if (node != phy->dev.of_node) {
- for_each_child_of_node(node, child) {
- if (child == phy->dev.of_node)
- goto phy_found;
- }
+ if (args->np != phy->dev.of_node)
continue;
- }
-phy_found:
class_dev_iter_exit(&iter);
return phy;
}
--
1.7.9.5
--
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[PATCH 09/25] phy: berlin-sata: Move PHY_BASE into private data struct
From: Sebastian Hesselbarth
Currently, Berlin SATA PHY driver assumes PHY_BASE address being
constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE
is different. Prepare the driver for BG2 support by moving the phy_base
into private driver data.
Acked-by: Antoine Ténart
Signed-off-by: Sebastian Hesselbarth
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-berlin-sata.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 69ced52..cdb46d1 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,7 +30,7 @@
#define MBUS_WRITE_REQUEST_SIZE_128(BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
-#define PHY_BASE 0x200
+#define BG2Q_PHY_BASE 0x200
/* register 0x01 */
#define REF_FREF_SEL_25BIT(0)
@@ -61,15 +61,16 @@ struct phy_berlin_priv {
struct clk *clk;
struct phy_berlin_desc **phys;
unsignednphys;
+ u32 phy_base;
};
-static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg,
- u32 mask, u32 val)
+static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
+ u32 phy_base, u32 reg, u32 mask, u32 val)
{
u32 regval;
/* select register */
- writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR);
+ writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
/* set bits */
regval = readl(ctrl_reg + PORT_VSR_DATA);
@@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy)
writel(regval, priv->base + HOST_VSA_DATA);
/* set PHY mode and ref freq to 25 MHz */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff,
- REF_FREF_SEL_25 | PHY_MODE_SATA);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
+ 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
/* set PHY up to 6 Gbps */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
+ 0x0c00, PHY_GEN_MAX_6_0);
/* set 40 bits width */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
+ 0x0c00, DATA_BIT_WIDTH_40);
/* use max pll rate */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
+ 0x, USE_MAX_PLL_RATE);
/* set Gen3 controller speed */
regval = readl(ctrl_reg + PORT_SCR_CTL);
@@ -218,6 +222,8 @@ static int phy_berlin_sata_probe(struct platform_device
*pdev)
if (!priv->phys)
return -ENOMEM;
+ priv->phy_base = BG2Q_PHY_BASE;
+
dev_set_drvdata(dev, priv);
spin_lock_init(&priv->lock);
--
1.7.9.5
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[PATCH 13/25] Documentation: bindings: add doc for the Berlin USB PHY
From: Antoine Tenart
Document the bindings of the Marvell Berlin USB PHY driver.
Signed-off-by: Antoine Tenart
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/berlin-usb-phy.txt | 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
new file mode 100644
index 000..be33780
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
@@ -0,0 +1,16 @@
+* Marvell Berlin USB PHY
+
+Required properties:
+- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
+- reg: base address and length of the registers
+- #phys-cells: should be 0
+- resets: reference to the reset controller
+
+Example:
+
+ usb-phy@f774000 {
+ compatible = "marvell,berlin2-usb-phy";
+ reg = <0xf774000 0x128>;
+ #phy-cells = <0>;
+ resets = <&chip 0x104 14>;
+ };
--
1.7.9.5
--
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[PATCH 11/25] phy: berlin-sata: Document BG2 compatible
From: Sebastian Hesselbarth Berlin BG2 SATA PHY is slightly different from currently supported BG2Q SATA PHY. Document the new compatible for BG2's PHY. Acked-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/berlin-sata-phy.txt|4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt index 88f8c23..c0155f8 100644 --- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt @@ -2,7 +2,9 @@ Berlin SATA PHY --- Required properties: -- compatible: should be "marvell,berlin2q-sata-phy" +- compatible: should be one of +"marvell,berlin2-sata-phy" +"marvell,berlin2q-sata-phy" - address-cells: should be 1 - size-cells: should be 0 - phy-cells: from the generic PHY bindings, must be 1 -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 12/25] phy: add the Berlin USB PHY driver
From: Antoine Tenart Add the driver driving the Marvell Berlin USB PHY. This allows to initialize the PHY and to use it from the USB driver later. Signed-off-by: Antoine Tenart Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/Kconfig |7 ++ drivers/phy/Makefile |1 + drivers/phy/phy-berlin-usb.c | 224 ++ 3 files changed, 232 insertions(+) create mode 100644 drivers/phy/phy-berlin-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index cfaced9..4144d25 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -15,6 +15,13 @@ config GENERIC_PHY phy users can obtain reference to the PHY. All the users of this framework should select this config. +config PHY_BERLIN_USB + tristate "Marvell Berlin USB PHY Driver" + depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF + select GENERIC_PHY + help + Enable this to support the USB PHY on Marvell Berlin SoCs. + config PHY_BERLIN_SATA tristate "Marvell Berlin SATA PHY driver" depends on ARCH_BERLIN && HAS_IOMEM && OF diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 30d90a8..68022f6 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_GENERIC_PHY) += phy-core.o +obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o diff --git a/drivers/phy/phy-berlin-usb.c b/drivers/phy/phy-berlin-usb.c new file mode 100644 index 000..f9f1306 --- /dev/null +++ b/drivers/phy/phy-berlin-usb.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Tenart + * Jisheng Zhang + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_PHY_PLL0x04 +#define USB_PHY_PLL_CONTROL0x08 +#define USB_PHY_TX_CTRL0 0x10 +#define USB_PHY_TX_CTRL1 0x14 +#define USB_PHY_TX_CTRL2 0x18 +#define USB_PHY_RX_CTRL0x20 +#define USB_PHY_ANALOG 0x34 + +/* USB_PHY_PLL */ +#define CLK_REF_DIV(x) ((x) << 4) +#define FEEDBACK_CLK_DIV(x)((x) << 8) + +/* USB_PHY_PLL_CONTROL */ +#define CLK_STABLE BIT(0) +#define PLL_CTRL_PIN BIT(1) +#define PLL_CTRL_REG BIT(2) +#define PLL_ON BIT(3) +#define PHASE_OFF_TOL_125 (0x0 << 5) +#define PHASE_OFF_TOL_250 BIT(5) +#define KVC0_CALIB (0x0 << 9) +#define KVC0_REG_CTRL BIT(9) +#define KVC0_HIGH (0x0 << 10) +#define KVC0_LOW (0x3 << 10) +#define CLK_BLK_EN BIT(13) + +/* USB_PHY_TX_CTRL0 */ +#define EXT_HS_RCAL_EN BIT(3) +#define EXT_FS_RCAL_EN BIT(4) +#define IMPCAL_VTH_DIV(x) ((x) << 5) +#define EXT_RS_RCAL_DIV(x) ((x) << 8) +#define EXT_FS_RCAL_DIV(x) ((x) << 12) + +/* USB_PHY_TX_CTRL1 */ +#define TX_VDD15_14(0x0 << 4) +#define TX_VDD15_15BIT(4) +#define TX_VDD15_16(0x2 << 4) +#define TX_VDD15_17(0x3 << 4) +#define TX_VDD12_VDD (0x0 << 6) +#define TX_VDD12_11BIT(6) +#define TX_VDD12_12(0x2 << 6) +#define TX_VDD12_13(0x3 << 6) +#define LOW_VDD_EN BIT(8) +#define TX_OUT_AMP(x) ((x) << 9) + +/* USB_PHY_TX_CTRL2 */ +#define TX_CHAN_CTRL_REG(x)((x) << 0) +#define DRV_SLEWRATE(x)((x) << 4) +#define IMP_CAL_FS_HS_DLY_0(0x0 << 6) +#define IMP_CAL_FS_HS_DLY_1BIT(6) +#define IMP_CAL_FS_HS_DLY_2(0x2 << 6) +#define IMP_CAL_FS_HS_DLY_3(0x3 << 6) +#define FS_DRV_EN_MASK(x) ((x) << 8) +#define HS_DRV_EN_MASK(x) ((x) << 12) + +/* USB_PHY_RX_CTRL */ +#define PHASE_FREEZE_DLY_2_CL (0x0 << 0) +#define PHASE_FREEZE_DLY_4_CL BIT(0) +#define ACK_LENGTH_8_CL(0x0 << 2) +#define ACK_LENGTH_12_CL BIT(2) +#define ACK_LENGTH_16_CL (0x2 << 2) +#define ACK_LENGTH_20_CL (0x3 << 2) +#define SQ_LENGTH_3(0x0 << 4) +#define SQ_LENGTH_6BIT(4) +#define SQ_LENGTH_9(0x2 << 4) +#define SQ_LENGTH_12 (0x3 << 4) +#define DISCON_THRESHOLD_260 (0x0 << 6) +#define DISCON_THRESHOLD_270 BIT(6) +#define DISCON_THRESHOLD_280 (0x2 << 6) +#define DISCON_THRESHOLD_290 (0x3 << 6) +#define SQ_THRESHOLD(x)((x) << 8) +#define LPF_COEF(x)((x) << 12) +#define INTPL_CUR_10 (0x0 << 14) +#define INTPL_CUR_20 BIT(14) +#define INTPL_CUR_30 (0x2 << 14) +#define INTPL_CUR_40 (0x3 << 14) + +/* USB_PHY_AN
[PATCH 15/25] phy: improved lookup method
From: Heikki Krogerus
Separates registration of the phy and the lookup. The method
is copied from clkdev.c,
Signed-off-by: Heikki Krogerus
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/phy.txt | 60 +
drivers/phy/phy-core.c | 84 ++-
include/linux/phy/phy.h | 16 +
3 files changed, 115 insertions(+), 45 deletions(-)
diff --git a/Documentation/phy.txt b/Documentation/phy.txt
index c6594af..371361c 100644
--- a/Documentation/phy.txt
+++ b/Documentation/phy.txt
@@ -54,18 +54,14 @@ The PHY driver should create the PHY in order for other
peripheral controllers
to make use of it. The PHY framework provides 2 APIs to create the PHY.
struct phy *phy_create(struct device *dev, struct device_node *node,
- const struct phy_ops *ops,
- struct phy_init_data *init_data);
+ const struct phy_ops *ops);
struct phy *devm_phy_create(struct device *dev, struct device_node *node,
- const struct phy_ops *ops,
- struct phy_init_data *init_data);
+ const struct phy_ops *ops);
The PHY drivers can use one of the above 2 APIs to create the PHY by passing
-the device pointer, phy ops and init_data.
+the device pointer and phy ops.
phy_ops is a set of function pointers for performing PHY operations such as
-init, exit, power_on and power_off. *init_data* is mandatory to get a reference
-to the PHY in the case of non-dt boot. See section *Board File Initialization*
-on how init_data should be used.
+init, exit, power_on and power_off.
Inorder to dereference the private data (in phy_ops), the phy provider driver
can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in
@@ -137,42 +133,18 @@ There are exported APIs like phy_pm_runtime_get,
phy_pm_runtime_get_sync,
phy_pm_runtime_put, phy_pm_runtime_put_sync, phy_pm_runtime_allow and
phy_pm_runtime_forbid for performing PM operations.
-8. Board File Initialization
-
-Certain board file initialization is necessary in order to get a reference
-to the PHY in the case of non-dt boot.
-Say we have a single device that implements 3 PHYs that of USB, SATA and PCIe,
-then in the board file the following initialization should be done.
-
-struct phy_consumer consumers[] = {
- PHY_CONSUMER("dwc3.0", "usb"),
- PHY_CONSUMER("pcie.0", "pcie"),
- PHY_CONSUMER("sata.0", "sata"),
-};
-PHY_CONSUMER takes 2 parameters, first is the device name of the controller
-(PHY consumer) and second is the port name.
-
-struct phy_init_data init_data = {
- .consumers = consumers,
- .num_consumers = ARRAY_SIZE(consumers),
-};
-
-static const struct platform_device pipe3_phy_dev = {
- .name = "pipe3-phy",
- .id = -1,
- .dev = {
- .platform_data = {
- .init_data = &init_data,
- },
- },
-};
-
-then, while doing phy_create, the PHY driver should pass this init_data
- phy_create(dev, ops, pdata->init_data);
-
-and the controller driver (phy consumer) should pass the port name along with
-the device to get a reference to the PHY
- phy_get(dev, "pcie");
+8. PHY Mappings
+
+In order to get reference to a PHY without help from DeviceTree, the framework
+offers lookups which can be compared to clkdev that allow clk structures to be
+bound to devices. A lookup can be made be made during runtime when a handle to
+the struct phy already exists.
+
+The framework offers the following API for registering and unregistering the
+lookups.
+
+int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id);
+void phy_remove_lookup(struct phy *phy, const char *con_id, const char
*dev_id);
9. DeviceTree Binding
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 1606ce9..bc83077 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -26,6 +26,7 @@
static struct class *phy_class;
static DEFINE_MUTEX(phy_provider_mutex);
static LIST_HEAD(phy_provider_list);
+static LIST_HEAD(phys);
static DEFINE_IDA(phy_ida);
static void devm_phy_release(struct device *dev, void *res)
@@ -84,6 +85,87 @@ static struct phy *phy_lookup(struct device *device, const
char *port)
return ERR_PTR(-ENODEV);
}
+/**
+ * phy_create_lookup() - allocate and register PHY/device association
+ * @phy: the phy of the association
+ * @con_id: connection ID string on device
+ * @dev_id: the device of the association
+ *
+ * Creates and registers phy_lookup entry.
+ */
+int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id)
+{
+ struct phy_lookup *pl;
+
+ if (!phy || !dev_id || !con_id)
+ return -EINVAL;
+
+ pl = kzalloc(sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+
+ pl->dev_id = dev_id;
+ pl->con_id = con_id;
+ p
[PATCH 14/25] phy: safer to_phy() macro
From: Heikki Krogerus
This makes to_phy() macro work with other variable names
besides "dev".
Signed-off-by: Heikki Krogerus
Tested-by: Vivek Gautam
Acked-by: Felipe Balbi
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/phy/phy.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 8cb6f81..9fda683 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -110,7 +110,7 @@ struct phy_init_data {
.port = _port,\
}
-#defineto_phy(dev) (container_of((dev), struct phy, dev))
+#defineto_phy(a) (container_of((a), struct phy, dev))
#defineof_phy_provider_register(dev, xlate)\
__of_phy_provider_register((dev), THIS_MODULE, (xlate))
--
1.7.9.5
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[PATCH 17/25] phy: remove the old lookup method
From: Heikki Krogerus
The users of the old method are now converted to the new one.
Signed-off-by: Heikki Krogerus
[ kis...@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated
devm_phy_create API.]
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-bcm-kona-usb2.c |2 +-
drivers/phy/phy-berlin-sata.c|2 +-
drivers/phy/phy-berlin-usb.c |3 +--
drivers/phy/phy-core.c | 49 +++---
drivers/phy/phy-exynos-dp-video.c|2 +-
drivers/phy/phy-exynos-mipi-video.c |2 +-
drivers/phy/phy-exynos5-usbdrd.c |3 +--
drivers/phy/phy-exynos5250-sata.c|2 +-
drivers/phy/phy-hix5hd2-sata.c |2 +-
drivers/phy/phy-miphy28lp.c |2 +-
drivers/phy/phy-miphy365x.c |2 +-
drivers/phy/phy-mvebu-sata.c |2 +-
drivers/phy/phy-omap-usb2.c |2 +-
drivers/phy/phy-qcom-apq8064-sata.c |3 +--
drivers/phy/phy-qcom-ipq806x-sata.c |3 +--
drivers/phy/phy-rcar-gen2.c |2 +-
drivers/phy/phy-samsung-usb2.c |3 +--
drivers/phy/phy-spear1310-miphy.c|2 +-
drivers/phy/phy-spear1340-miphy.c|2 +-
drivers/phy/phy-stih407-usb.c|2 +-
drivers/phy/phy-stih41x-usb.c|2 +-
drivers/phy/phy-sun4i-usb.c |2 +-
drivers/phy/phy-ti-pipe3.c |2 +-
drivers/phy/phy-twl4030-usb.c|2 +-
drivers/phy/phy-xgene.c |2 +-
drivers/pinctrl/pinctrl-tegra-xusb.c |4 +--
include/linux/phy/phy.h | 38 +++---
27 files changed, 34 insertions(+), 110 deletions(-)
diff --git a/drivers/phy/phy-bcm-kona-usb2.c b/drivers/phy/phy-bcm-kona-usb2.c
index c1e0ca3..ef2dc1a 100644
--- a/drivers/phy/phy-bcm-kona-usb2.c
+++ b/drivers/phy/phy-bcm-kona-usb2.c
@@ -117,7 +117,7 @@ static int bcm_kona_usb2_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, phy);
- gphy = devm_phy_create(dev, NULL, &ops, NULL);
+ gphy = devm_phy_create(dev, NULL, &ops);
if (IS_ERR(gphy))
return PTR_ERR(gphy);
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 873e7a8..3e599dc 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -249,7 +249,7 @@ static int phy_berlin_sata_probe(struct platform_device
*pdev)
if (!phy_desc)
return -ENOMEM;
- phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops, NULL);
+ phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
if (IS_ERR(phy)) {
dev_err(dev, "failed to create PHY %d\n", phy_id);
return PTR_ERR(phy);
diff --git a/drivers/phy/phy-berlin-usb.c b/drivers/phy/phy-berlin-usb.c
index f9f1306..c8a8d53 100644
--- a/drivers/phy/phy-berlin-usb.c
+++ b/drivers/phy/phy-berlin-usb.c
@@ -192,8 +192,7 @@ static int phy_berlin_usb_probe(struct platform_device
*pdev)
priv->pll_divider = *((u32 *)match->data);
- priv->phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops,
- NULL);
+ priv->phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
if (IS_ERR(priv->phy)) {
dev_err(&pdev->dev, "failed to create PHY\n");
return PTR_ERR(priv->phy);
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index bc83077..a12d353 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -55,36 +55,6 @@ static int devm_phy_match(struct device *dev, void *res,
void *match_data)
return res == match_data;
}
-static struct phy *phy_lookup(struct device *device, const char *port)
-{
- unsigned int count;
- struct phy *phy;
- struct device *dev;
- struct phy_consumer *consumers;
- struct class_dev_iter iter;
-
- class_dev_iter_init(&iter, phy_class, NULL, NULL);
- while ((dev = class_dev_iter_next(&iter))) {
- phy = to_phy(dev);
-
- if (!phy->init_data)
- continue;
- count = phy->init_data->num_consumers;
- consumers = phy->init_data->consumers;
- while (count--) {
- if (!strcmp(consumers->dev_name, dev_name(device)) &&
- !strcmp(consumers->port, port)) {
- class_dev_iter_exit(&iter);
- return phy;
- }
- consumers++;
- }
- }
-
- class_dev_iter_exit(&iter);
- return ERR_PTR(-ENODEV);
-}
-
/**
* phy_create_lookup() - allocate and register PHY/device association
* @phy: the phy of the association
@@ -148,7 +118,6 @@ static struct phy *phy_find(struct device *dev, const char
*con_id)
{
const char *dev_id = dev
[PATCH 18/25] usb: dwc3: host: convey the PHYs to xhci
From: Heikki Krogerus
On some platforms a PHY may need to be handled also in the
host controller driver. Exynos5420 SoC requires some "PHY
tuning" based on the USB speed. This patch delivers dwc3's
PHYs to the xhci platform device when it's created.
Signed-off-by: Heikki Krogerus
Tested-by: Vivek Gautam
Acked-by: Felipe Balbi
Signed-off-by: Kishon Vijay Abraham I
---
drivers/usb/dwc3/host.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index dcb8ca0..12bfd3c 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -29,8 +29,7 @@ int dwc3_host_init(struct dwc3 *dwc)
xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
if (!xhci) {
dev_err(dwc->dev, "couldn't allocate xHCI device\n");
- ret = -ENOMEM;
- goto err0;
+ return -ENOMEM;
}
dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
@@ -60,22 +59,33 @@ int dwc3_host_init(struct dwc3 *dwc)
goto err1;
}
+ phy_create_lookup(dwc->usb2_generic_phy, "usb2-phy",
+ dev_name(&xhci->dev));
+ phy_create_lookup(dwc->usb3_generic_phy, "usb3-phy",
+ dev_name(&xhci->dev));
+
ret = platform_device_add(xhci);
if (ret) {
dev_err(dwc->dev, "failed to register xHCI device\n");
- goto err1;
+ goto err2;
}
return 0;
-
+err2:
+ phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
+ dev_name(&xhci->dev));
+ phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
+ dev_name(&xhci->dev));
err1:
platform_device_put(xhci);
-
-err0:
return ret;
}
void dwc3_host_exit(struct dwc3 *dwc)
{
+ phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
+ dev_name(&dwc->xhci->dev));
+ phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
+ dev_name(&dwc->xhci->dev));
platform_device_unregister(dwc->xhci);
}
--
1.7.9.5
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[PATCH 20/25] phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
From: Vivek Gautam
Some Exynos boards have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-exynos5-usbdrd.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index 99ba56d..0437401 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -159,6 +159,8 @@ struct exynos5_usbdrd_phy_drvdata {
*reference clocks' for SS and HS operations
* @ref_clk: reference clock to PHY block from which PHY's
* operational clocks are derived
+ * vbus: VBUS regulator for phy
+ * vbus_boost: Boost regulator for VBUS present on few Exynos boards
*/
struct exynos5_usbdrd_phy {
struct device *dev;
@@ -178,6 +180,7 @@ struct exynos5_usbdrd_phy {
u32 extrefclk;
struct clk *ref_clk;
struct regulator *vbus;
+ struct regulator *vbus_boost;
};
static inline
@@ -460,11 +463,20 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
}
/* Enable VBUS supply */
+ if (phy_drd->vbus_boost) {
+ ret = regulator_enable(phy_drd->vbus_boost);
+ if (ret) {
+ dev_err(phy_drd->dev,
+ "Failed to enable VBUS boost supply\n");
+ goto fail_vbus;
+ }
+ }
+
if (phy_drd->vbus) {
ret = regulator_enable(phy_drd->vbus);
if (ret) {
dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
- goto fail_vbus;
+ goto fail_vbus_boost;
}
}
@@ -473,6 +485,10 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
return 0;
+fail_vbus_boost:
+ if (phy_drd->vbus_boost)
+ regulator_disable(phy_drd->vbus_boost);
+
fail_vbus:
clk_disable_unprepare(phy_drd->ref_clk);
if (!phy_drd->drv_data->has_common_clk_gate) {
@@ -497,6 +513,8 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
/* Disable VBUS supply */
if (phy_drd->vbus)
regulator_disable(phy_drd->vbus);
+ if (phy_drd->vbus_boost)
+ regulator_disable(phy_drd->vbus_boost);
clk_disable_unprepare(phy_drd->ref_clk);
if (!phy_drd->drv_data->has_common_clk_gate) {
@@ -690,7 +708,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device
*pdev)
break;
}
- /* Get Vbus regulator */
+ /* Get Vbus regulators */
phy_drd->vbus = devm_regulator_get(dev, "vbus");
if (IS_ERR(phy_drd->vbus)) {
ret = PTR_ERR(phy_drd->vbus);
@@ -701,6 +719,16 @@ static int exynos5_usbdrd_phy_probe(struct platform_device
*pdev)
phy_drd->vbus = NULL;
}
+ phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
+ if (IS_ERR(phy_drd->vbus_boost)) {
+ ret = PTR_ERR(phy_drd->vbus_boost);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+
+ dev_warn(dev, "Failed to get VBUS boost supply regulator\n");
+ phy_drd->vbus_boost = NULL;
+ }
+
dev_vdbg(dev, "Creating usbdrd_phy phy\n");
for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
--
1.7.9.5
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[PATCH 16/25] phy: twl4030: use the new lookup method
From: Heikki Krogerus
Creates the lookup separately. Hard coding the consumer as
it can't be anything else except musb.
Signed-off-by: Heikki Krogerus
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-twl4030-usb.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
index 7b04bef..c45a3aa 100644
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -644,7 +644,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
struct usb_otg *otg;
struct device_node *np = pdev->dev.of_node;
struct phy_provider *phy_provider;
- struct phy_init_data*init_data = NULL;
twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
if (!twl)
@@ -655,7 +654,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
(enum twl4030_usb_mode *)&twl->usb_mode);
else if (pdata) {
twl->usb_mode = pdata->usb_mode;
- init_data = pdata->init_data;
} else {
dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
return -EINVAL;
@@ -680,7 +678,7 @@ static int twl4030_usb_probe(struct platform_device *pdev)
otg->set_host = twl4030_set_host;
otg->set_peripheral = twl4030_set_peripheral;
- phy = devm_phy_create(twl->dev, NULL, &ops, init_data);
+ phy = devm_phy_create(twl->dev, NULL, &ops, NULL);
if (IS_ERR(phy)) {
dev_dbg(&pdev->dev, "Failed to create PHY\n");
return PTR_ERR(phy);
@@ -733,6 +731,11 @@ static int twl4030_usb_probe(struct platform_device *pdev)
return status;
}
+ if (pdata)
+ err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
+ if (err)
+ return err;
+
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(twl->dev);
--
1.7.9.5
--
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linux-next: build warning after merge of the irqchip tree
Hi Jason,
After merging the irqchip tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
include/linux/irqchip/arm-gic.h:109:53: warning: its scope is only this
definition or declaration, which is probably not what you want
In file included from arch/arm/mach-ux500/pm.c:13:0:
include/linux/irqchip/arm-gic.h:109:53: warning: 'struct irq_domain' declared
inside parameter list
int gicv2m_of_init(struct device_node *node, struct irq_domain *parent);
^
and many more similar.
Introduced by commit 853a33ce6932 ("irqchip: gic-v2m: Add support for
ARM GICv2m MSI(-X) doorbell").
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
pgpEE0SxPrJ6C.pgp
Description: OpenPGP digital signature
[PATCH 22/25] phy: Use PTR_ERR_OR_ZERO to fix warning raised by coccinelle
From: Gregory CLEMENT
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: coccinelle/api/ptr_ret.cocci
Signed-off-by: Gregory CLEMENT
Acked-by: Jason Cooper
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-berlin-sata.c |5 +
drivers/phy/phy-hix5hd2-sata.c |5 +
drivers/phy/phy-miphy365x.c|5 +
drivers/phy/phy-stih41x-usb.c |5 +
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 3e599dc..099eee8 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -268,10 +268,7 @@ static int phy_berlin_sata_probe(struct platform_device
*pdev)
phy_provider =
devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
- if (IS_ERR(phy_provider))
- return PTR_ERR(phy_provider);
-
- return 0;
+ return PTR_ERR_OR_ZERO(phy_provider);
}
static const struct of_device_id phy_berlin_sata_of_match[] = {
diff --git a/drivers/phy/phy-hix5hd2-sata.c b/drivers/phy/phy-hix5hd2-sata.c
index a80ff9d..34915b4 100644
--- a/drivers/phy/phy-hix5hd2-sata.c
+++ b/drivers/phy/phy-hix5hd2-sata.c
@@ -164,10 +164,7 @@ static int hix5hd2_sata_phy_probe(struct platform_device
*pdev)
phy_set_drvdata(phy, priv);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
- if (IS_ERR(phy_provider))
- return PTR_ERR(phy_provider);
-
- return 0;
+ return PTR_ERR_OR_ZERO(phy_provider);
}
static const struct of_device_id hix5hd2_sata_phy_of_match[] = {
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 239930e..6ab43a8 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -610,10 +610,7 @@ static int miphy365x_probe(struct platform_device *pdev)
}
provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
- if (IS_ERR(provider))
- return PTR_ERR(provider);
-
- return 0;
+ return PTR_ERR_OR_ZERO(provider);
}
static const struct of_device_id miphy365x_of_match[] = {
diff --git a/drivers/phy/phy-stih41x-usb.c b/drivers/phy/phy-stih41x-usb.c
index 4ab581e..a603801 100644
--- a/drivers/phy/phy-stih41x-usb.c
+++ b/drivers/phy/phy-stih41x-usb.c
@@ -160,10 +160,7 @@ static int stih41x_usb_phy_probe(struct platform_device
*pdev)
phy_set_drvdata(phy, phy_dev);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
- if (IS_ERR(phy_provider))
- return PTR_ERR(phy_provider);
-
- return 0;
+ return PTR_ERR_OR_ZERO(phy_provider);
}
static const struct of_device_id stih41x_usb_phy_of_match[] = {
--
1.7.9.5
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[PATCH 23/25] Phy: DT binding documentation for Marvell MVEBU SATA phy.
From: Andrew Lunn
Describe the binding for the Marvell MVEBU SATA phy. This driver
can be used at least with Kirkwood, Dove and maybe others.
Additionally, update the SATA binding with the properties to link
to the phy nodes.
Signed-off-by: Andrew Lunn
Acked-by: Jason Cooper
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/ata/marvell.txt |6 ++
.../devicetree/bindings/phy/phy-mvebu.txt | 22
2 files changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu.txt
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt
b/Documentation/devicetree/bindings/ata/marvell.txt
index 1c83516..b460edd 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
- interrupts: Interrupt controller is using
- nr-ports : Number of SATA ports in use.
+Optional Properties:
+- phys : List of phandles to sata phys
+- phy-names: Should be "0", "1", etc, one number per phandle
+
Example:
sata@8 {
compatible = "marvell,orion-sata";
reg = <0x8 0x5000>;
interrupts = <21>;
+ phys = <&sata_phy0>, <&sata_phy1>;
+ phy-names = "0", "1";
nr-ports = <2>;
}
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
new file mode 100644
index 000..6cb3364
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -0,0 +1,22 @@
+* Marvell MVEBU SATA PHY
+
+Power control for the SATA phy found on Marvell MVEBU SoCs.
+
+This document extends the binding described in phy-bindings.txt
+
+Required properties :
+
+ - reg: Offset and length of the register set for the SATA device
+ - compatible : Should be "marvell,mvebu-sata-phy"
+ - clocks : phandle of clock and specifier that supplies the device
+ - clock-names: Should be "sata"
+
+Example:
+ sata-phy@84000 {
+ compatible = "marvell,mvebu-sata-phy";
+ reg = <0x84000 0x0334>;
+ clocks = <&gate_clk 15>;
+ clock-names = "sata";
+ #phy-cells = <0>;
+ status = "ok";
+ };
--
1.7.9.5
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[PATCH 5/6] ACPICA: Disassembler: Emit correct string for 0 stop bits.
From: Bob Moore
Was stop_bits_none, corrected to stop_bits_zero.
David E. Box.
Signed-off-by: David E. Box
Signed-off-by: Bob Moore
Signed-off-by: Lv Zheng
---
drivers/acpi/acpica/utresrc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/acpica/utresrc.c b/drivers/acpi/acpica/utresrc.c
index 5cd017c..bc1ff82 100644
--- a/drivers/acpi/acpica/utresrc.c
+++ b/drivers/acpi/acpica/utresrc.c
@@ -263,7 +263,7 @@ const char *acpi_gbl_bpb_decode[] = {
/* UART serial bus stop bits */
const char *acpi_gbl_sb_decode[] = {
- "StopBitsNone",
+ "StopBitsZero",
"StopBitsOne",
"StopBitsOnePlusHalf",
"StopBitsTwo"
--
1.7.10
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[PATCH 24/25] Phy: DT binding documentation for the Armada 375 USB cluster binding
From: Gregory CLEMENT
Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers. This commit adds the Device Tree
binding documentation for this piece of hardware.
Signed-off-by: Gregory CLEMENT
Acked-by: Jason Cooper
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/phy-mvebu.txt | 21
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
index 6cb3364..f95b626 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -20,3 +20,24 @@ Example:
#phy-cells = <0>;
status = "ok";
};
+
+Armada 375 USB cluster
+--
+
+Armada 375 comes with an USB2 host and device controller and an USB3
+controller. The USB cluster control register allows to manage common
+features of both USB controllers.
+
+Required properties:
+
+- compatible: "marvell,armada-375-usb-cluster"
+- reg: Should contain usb cluster register location and length.
+- #phy-cells : from the generic phy bindings, must be 1. Possible
+values are 1 (USB2), 2 (USB3).
+
+Example:
+ usbcluster: usb-cluster@18400 {
+ compatible = "marvell,armada-375-usb-cluster";
+ reg = <0x18400 0x4>;
+ #phy-cells = <1>
+ };
--
1.7.9.5
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[PATCH 21/25] phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS
From: Vivek Gautam This PHY controller is also present on Exynos7 platform in arch-exynos family. So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS. Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/Kconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4144d25..96d43d5 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -208,7 +208,7 @@ config PHY_EXYNOS5250_USB2 config PHY_EXYNOS5_USBDRD tristate "Exynos5 SoC series USB DRD PHY driver" - depends on ARCH_EXYNOS5 && OF + depends on ARCH_EXYNOS && OF depends on HAS_IOMEM depends on USB_DWC3_EXYNOS select GENERIC_PHY -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 6/6] ACPICA: Update version to 20141107.
From: Bob Moore Version 20141107. Signed-off-by: Bob Moore Signed-off-by: Lv Zheng --- include/acpi/acpixf.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index ab2acf6..5ba7846 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -46,7 +46,7 @@ /* Current ACPICA subsystem version in MMDD format */ -#define ACPI_CA_VERSION 0x20140926 +#define ACPI_CA_VERSION 0x20141107 #include #include -- 1.7.10 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 25/25] phy: add support for USB cluster on the Armada 375 SoC
From: Gregory CLEMENT
The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers.
This commit adds a driver integrated in the generic PHY framework to
control this USB cluster feature.
Signed-off-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
[ kis...@ti.com : Made it to use the updated devm_phy_create API and
soem cosmentic changes in Kconfig file.]
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Jason Cooper
---
drivers/phy/Kconfig |6 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-armada375-usb2.c | 158 ++
include/dt-bindings/phy/phy.h|1 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-armada375-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 96d43d5..ccad880 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -29,6 +29,12 @@ config PHY_BERLIN_SATA
help
Enable this to support the SATA PHY on Marvell Berlin SoCs.
+config ARMADA375_USBCLUSTER_PHY
+ def_bool y
+ depends on MACH_ARMADA_375 || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+
config PHY_EXYNOS_MIPI_VIDEO
tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 68022f6..aa74f96 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
+obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
diff --git a/drivers/phy/phy-armada375-usb2.c b/drivers/phy/phy-armada375-usb2.c
new file mode 100644
index 000..ac7d99d
--- /dev/null
+++ b/drivers/phy/phy-armada375-usb2.c
@@ -0,0 +1,158 @@
+/*
+ * USB cluster support for Armada 375 platform.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2 or later. This program is licensed "as is"
+ * without any warranty of any kind, whether express or implied.
+ *
+ * Armada 375 comes with an USB2 host and device controller and an
+ * USB3 controller. The USB cluster control register allows to manage
+ * common features of both USB controllers.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define USB2_PHY_CONFIG_DISABLE BIT(0)
+
+struct armada375_cluster_phy {
+ struct phy *phy;
+ void __iomem *reg;
+ bool use_usb3;
+ int phy_provided;
+};
+
+static int armada375_usb_phy_init(struct phy *phy)
+{
+ struct armada375_cluster_phy *cluster_phy;
+ u32 reg;
+
+ cluster_phy = dev_get_drvdata(phy->dev.parent);
+ if (!cluster_phy)
+ return -ENODEV;
+
+ reg = readl(cluster_phy->reg);
+ if (cluster_phy->use_usb3)
+ reg |= USB2_PHY_CONFIG_DISABLE;
+ else
+ reg &= ~USB2_PHY_CONFIG_DISABLE;
+ writel(reg, cluster_phy->reg);
+
+ return 0;
+}
+
+static struct phy_ops armada375_usb_phy_ops = {
+ .init = armada375_usb_phy_init,
+ .owner = THIS_MODULE,
+};
+
+/*
+ * Only one controller can use this PHY. We shouldn't have the case
+ * when two controllers want to use this PHY. But if this case occurs
+ * then we provide a phy to the first one and return an error for the
+ * next one. This error has also to be an error returned by
+ * devm_phy_optional_get() so different from ENODEV for USB2. In the
+ * USB3 case it still optional and we use ENODEV.
+ */
+static struct phy *armada375_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct armada375_cluster_phy *cluster_phy = dev_get_drvdata(dev);
+
+ if (!cluster_phy)
+ return ERR_PTR(-ENODEV);
+
+ /*
+* Either the phy had never been requested and then the first
+* usb claiming it can get it, or it had already been
+* requested in this case, we only allow to use it with the
+* same configuration.
+*/
+ if (WARN_ON((cluster_phy->phy_provided != PHY_NONE) &&
+ (cluster_phy->phy_provided != args->args[0]))) {
+ dev_err(dev, "This PHY has already been provided!\n");
+ dev_err(dev, "Check your device tree, only one controller can
use it\n.");
+ if (args->args[0] == PHY_TYPE_USB2)
+ return ERR_PTR(-EBUSY);
+ else
+ return ERR_P
[PATCH 19/25] phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support
From: Vivek Gautam
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
Additionally, separate gate control is available for the clock
used for ITP (Isochronous Transfer Packet) generation.
So get the same and control in the phy-exynos5-usbdrd driver.
Suggested-by: Anton Tikhomirov
Signed-off-by: Vivek Gautam
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt|6 ++
drivers/phy/phy-exynos5-usbdrd.c | 104
2 files changed, 92 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c..d5bad92 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
- compatible : Should be set to one of the following supported values:
- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+ - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
- reg : Register offset and length of USB DRD PHY register set;
- clocks: Clock IDs array as required by the controller
- clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
PHY operations, associated by phy name. It is used to
determine bit values for clock settings register.
For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+ - optional clocks: Exynos7 SoC has now following additional
+ gate clocks available:
+ - phy_pipe: for PIPE3 phy
+ - phy_utmi: for UTMI+ phy
+ - itp: for ITP generation
- samsung,pmu-syscon: phandle for PMU system controller interface, used to
control pmu registers for power isolation.
- #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index b3ca3bc..99ba56d 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -141,6 +141,7 @@ struct exynos5_usbdrd_phy_drvdata {
const struct exynos5_usbdrd_phy_config *phy_cfg;
u32 pmu_offset_usbdrd0_phy;
u32 pmu_offset_usbdrd1_phy;
+ bool has_common_clk_gate;
};
/**
@@ -148,6 +149,9 @@ struct exynos5_usbdrd_phy_drvdata {
* @dev: pointer to device instance of this platform device
* @reg_phy: usb phy controller register memory base
* @clk: phy clock for register access
+ * @pipeclk: clock for pipe3 phy
+ * @utmiclk: clock for utmi+ phy
+ * @itpclk: clock for ITP generation
* @drv_data: pointer to SoC level driver data structure
* @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
* instances each with its 'phy' and 'phy_cfg'.
@@ -155,12 +159,14 @@ struct exynos5_usbdrd_phy_drvdata {
*reference clocks' for SS and HS operations
* @ref_clk: reference clock to PHY block from which PHY's
* operational clocks are derived
- * @ref_rate: rate of above reference clock
*/
struct exynos5_usbdrd_phy {
struct device *dev;
void __iomem *reg_phy;
struct clk *clk;
+ struct clk *pipeclk;
+ struct clk *utmiclk;
+ struct clk *itpclk;
const struct exynos5_usbdrd_phy_drvdata *drv_data;
struct phy_usb_instance {
struct phy *phy;
@@ -447,6 +453,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
clk_prepare_enable(phy_drd->ref_clk);
+ if (!phy_drd->drv_data->has_common_clk_gate) {
+ clk_prepare_enable(phy_drd->pipeclk);
+ clk_prepare_enable(phy_drd->utmiclk);
+ clk_prepare_enable(phy_drd->itpclk);
+ }
/* Enable VBUS supply */
if (phy_drd->vbus) {
@@ -464,6 +475,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
fail_vbus:
clk_disable_unprepare(phy_drd->ref_clk);
+ if (!phy_drd->drv_data->has_common_clk_gate) {
+ clk_disable_unprepare(phy_drd->itpclk);
+ clk_disable_unprepare(phy_drd->utmiclk);
+ clk_disable_unprepare(phy_drd->pipeclk);
+ }
return ret;
}
@@ -483,6 +499,11 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
regulator_disable(phy_drd->vbus);
clk_disable_unprepare(phy_drd->ref_clk);
+ if (!phy_drd->drv_data->has_common_clk_gate) {
+ clk_disable_unprepare(phy_drd->itpclk);
+ clk_disable_unprepare(phy_drd->pipeclk);
+ clk_disable_unprepare(phy_drd->utmiclk);
+ }
return 0;
}
@@ -506,6 +527,57 @@ static struct phy_ops exynos5_usbdrd_phy_ops = {
[PATCH 2/6] ACPICA: acpiexec: Add option to specify an object initialization file.
From: Bob Moore
This option (-fi) allows the specification of a file that is used
to specify initialization values for individual namespace objects.
Each line in the file is in the format:
This patch only affects acpiexec which is not in the Linux kernel.
Signed-off-by: Bob Moore
Signed-off-by: Lv Zheng
---
drivers/acpi/acpica/utxfinit.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/acpi/acpica/utxfinit.c b/drivers/acpi/acpica/utxfinit.c
index 13380d8..b1fd688 100644
--- a/drivers/acpi/acpica/utxfinit.c
+++ b/drivers/acpi/acpica/utxfinit.c
@@ -53,6 +53,9 @@
#define _COMPONENT ACPI_UTILITIES
ACPI_MODULE_NAME("utxfinit")
+/* For acpi_exec only */
+void ae_do_object_overrides(void);
+
/***
*
* FUNCTION:acpi_initialize_subsystem
@@ -65,6 +68,7 @@ ACPI_MODULE_NAME("utxfinit")
* called, so any early initialization belongs here.
*
**/
+
acpi_status __init acpi_initialize_subsystem(void)
{
acpi_status status;
@@ -275,6 +279,13 @@ acpi_status __init acpi_initialize_objects(u32 flags)
return_ACPI_STATUS(status);
}
}
+#ifdef ACPI_EXEC_APP
+ /*
+* This call implements the "initialization file" option for acpi_exec.
+* This is the precise point that we want to perform the overrides.
+*/
+ ae_do_object_overrides();
+#endif
/*
* Execute any module-level code that was detected during the table load
--
1.7.10
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[PATCH 01/25] phy: Add PHY header file for DT x Driver defines
From: Gabriel FERNANDEZ This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/phy/phy.h | 18 ++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/phy/phy.h diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h new file mode 100644 index 000..e8c6a3f --- /dev/null +++ b/include/dt-bindings/phy/phy.h @@ -0,0 +1,18 @@ +/* + * + * This header provides constants for the phy framework + * + * Copyright (C) 2014 STMicroelectronics + * Author: Gabriel Fernandez + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _DT_BINDINGS_PHY +#define _DT_BINDINGS_PHY + +#define PHY_TYPE_SATA 1 +#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB2 3 +#define PHY_TYPE_USB3 4 + +#endif /* _DT_BINDINGS_PHY */ -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/6] ACPICA: 20141107 Release
The 20141107 ACPICA kernel-resident subsystem updates are linuxized based on the pm/linux-next branch to form this patchset. The patchset has passed the following build/boot tests. Build tests are performed as follows: 1. i386 + default + COFNIG_ACPI=y 2. i386 + allyes + CONFIG_ACPI=y 3. i386 + default + COFNIG_ACPI=n 4. i386 + allyes + CONFIG_ACPI=n 5. x86_64 + default + COFNIG_ACPI=y 6. x86_64 + allyes + CONFIG_ACPI=y 7. x86_64 + default + COFNIG_ACPI=n 8. x86_64 + allyes + CONFIG_ACPI=n Boot tests are performed as follows: 1. i386 + default + COFNIG_ACPI=y 2. x86_64 + default + COFNIG_ACPI=y Where: 1. i386: machine named as "Dell Inspiron Mini 1010" 2. x86_64: machine named as "HP Compaq 8200 Elite SFF PC" 3. default: kernel configuration with following items enabled: All hardware drivers related to the machines of i386/x86_64 All drivers/acpi configurations All platform drivers The divergences checking result: Before applying (20140926 Release): 852 lines After applying (20141107 Release): 852 lines Bob Moore (6): ACPICA: iASL: Add support for to_PLD macro. ACPICA: acpiexec: Add option to specify an object initialization file. ACPICA: Disassembler: Add support for C-style operators and expressions. ACPICA: Disassembler: Update for C-style expressions. ACPICA: Disassembler: Emit correct string for 0 stop bits. ACPICA: Update version to 20141107. drivers/acpi/acpica/acglobal.h |1 + drivers/acpi/acpica/aclocal.h |3 +++ drivers/acpi/acpica/utresrc.c |2 +- drivers/acpi/acpica/utxface.c |4 +++- drivers/acpi/acpica/utxfinit.c | 11 +++ include/acpi/acbuffer.h| 14 +++--- include/acpi/acpixf.h |2 +- 7 files changed, 31 insertions(+), 6 deletions(-) -- 1.7.10 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 10/25] phy: berlin-sata: Add support for BG2 SATA PHY
From: Sebastian Hesselbarth
Berlin BG2 also has a SATA PHY compatible with the current driver
except different PHY_BASE. Add a new compatible to the driver
reflecting the different PHY_BASE.
Acked-by: Antoine Ténart
Signed-off-by: Sebastian Hesselbarth
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-berlin-sata.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index cdb46d1..873e7a8 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,6 +30,7 @@
#define MBUS_WRITE_REQUEST_SIZE_128(BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
+#define BG2_PHY_BASE 0x080
#define BG2Q_PHY_BASE 0x200
/* register 0x01 */
@@ -222,7 +223,10 @@ static int phy_berlin_sata_probe(struct platform_device
*pdev)
if (!priv->phys)
return -ENOMEM;
- priv->phy_base = BG2Q_PHY_BASE;
+ if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
+ priv->phy_base = BG2_PHY_BASE;
+ else
+ priv->phy_base = BG2Q_PHY_BASE;
dev_set_drvdata(dev, priv);
spin_lock_init(&priv->lock);
@@ -271,6 +275,7 @@ static int phy_berlin_sata_probe(struct platform_device
*pdev)
}
static const struct of_device_id phy_berlin_sata_of_match[] = {
+ { .compatible = "marvell,berlin2-sata-phy" },
{ .compatible = "marvell,berlin2q-sata-phy" },
{ },
};
--
1.7.9.5
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Re: [PATCH] drivers/core/of: Add symlink to device-tree from devices with an OF node
On Wed, 2014-11-26 at 19:39 -0800, Greg KH wrote: > Are you going to resend a changed version of this? Yes, I've been distracted by a few other things, but I suppose I should do it :-) Possibly tomorrow. Arnd, are you doing that helper you suggested to get to the of_node or should I ? Cheers, Ben. > thanks, > > greg k-h > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 4/4] powernv: powerpc: Add winkle support for offline cpus
Hi Ben, On Thursday 27 November 2014 07:25 AM, Benjamin Herrenschmidt wrote: > On Tue, 2014-11-25 at 16:47 +0530, Shreyas B. Prabhu wrote: > >> diff --git a/arch/powerpc/kernel/cpu_setup_power.S >> b/arch/powerpc/kernel/cpu_setup_power.S >> index 4673353..66874aa 100644 >> --- a/arch/powerpc/kernel/cpu_setup_power.S >> +++ b/arch/powerpc/kernel/cpu_setup_power.S >> @@ -55,6 +55,8 @@ _GLOBAL(__setup_cpu_power8) >> beqlr >> li r0,0 >> mtspr SPRN_LPID,r0 >> +mtspr SPRN_WORT,r0 >> +mtspr SPRN_WORC,r0 >> mfspr r3,SPRN_LPCR >> ori r3, r3, LPCR_PECEDH >> bl __init_LPCR >> @@ -75,6 +77,8 @@ _GLOBAL(__restore_cpu_power8) >> li r0,0 >> mtspr SPRN_LPID,r0 >> mfspr r3,SPRN_LPCR >> +mtspr SPRN_WORT,r0 >> +mtspr SPRN_WORC,r0 >> ori r3, r3, LPCR_PECEDH >> bl __init_LPCR >> bl __init_HFSCR > > Clearing WORT and WORC might not be the best thing. We know the HW folks > have been trying to tune those values and we might need to preserve what > the boot FW has set. > > Can you get in touch with them and double check what we should do here ? > I observed these were always 0. I'll speak to HW folks as you suggested. >> diff --git a/arch/powerpc/kernel/exceptions-64s.S >> b/arch/powerpc/kernel/exceptions-64s.S >> index 3311c8d..c9897cb 100644 >> --- a/arch/powerpc/kernel/exceptions-64s.S >> +++ b/arch/powerpc/kernel/exceptions-64s.S >> @@ -112,6 +112,16 @@ BEGIN_FTR_SECTION >> >> cmpwi cr1,r13,2 >> >> +/* Check if last bit of HSPGR0 is set. This indicates whether we are >> + * waking up from winkle */ >> +li r3,1 >> +mfspr r4,SPRN_HSPRG0 >> +and r5,r4,r3 >> +cmpwi cr4,r5,1/* Store result in cr4 for later use */ >> + >> +andcr4,r4,r3 >> +mtspr SPRN_HSPRG0,r4 >> + > > There is an open question here whether adding a beq cr4,+8 after the > cmpwi (or a +4 after the andc) is worthwhile. Can you check ? (either > measure or talk to HW folks). Okay. This because mtspr is heavier op than beq? > Also we could write directly to r13... You mean use mr r13,r4 instead or GET_PACA? >> GET_PACA(r13) >> lbz r0,PACA_THREAD_IDLE_STATE(r13) >> cmpwi cr2,r0,PNV_THREAD_NAP >> diff --git a/arch/powerpc/kernel/idle_power7.S >> b/arch/powerpc/kernel/idle_power7.S >> index c1d590f..78c30b0 100644 >> --- a/arch/powerpc/kernel/idle_power7.S >> +++ b/arch/powerpc/kernel/idle_power7.S >> @@ -19,8 +19,22 @@ >> #include >> #include >> #include >> +#include >> >> #undef DEBUG >> +/* >> + * Use unused space in the interrupt stack to save and restore >> + * registers for winkle support. >> + */ >> +#define _SDR1 GPR3 >> +#define _RPRGPR4 >> +#define _SPURR GPR5 >> +#define _PURR GPR6 >> +#define _TSCR GPR7 >> +#define _DSCR GPR8 >> +#define _AMOR GPR9 >> +#define _PMC5 GPR10 >> +#define _PMC6 GPR11 > > WORT/WORTC need saving restoring The reason I skipped this was because these were always 0. But since its set by FW, I'll save and restore them. > >> /* Idle state entry routines */ >> >> @@ -153,32 +167,60 @@ lwarx_loop1: >> b common_enter >> >> last_thread: >> -LOAD_REG_ADDR(r3, pnv_need_fastsleep_workaround) >> -lbz r3,0(r3) >> -cmpwi r3,1 >> -bne common_enter >> /* >> * Last thread of the core entering sleep. Last thread needs to execute >> * the hardware bug workaround code. Before that, set the lock bit to >> * avoid the race of other threads waking up and undoing workaround >> * before workaround is applied. >> */ >> +LOAD_REG_ADDR(r3, pnv_need_fastsleep_workaround) >> +lbz r3,0(r3) >> +cmpwi r3,1 >> +bne common_enter >> + >> ori r15,r15,PNV_CORE_IDLE_LOCK_BIT >> stwcx. r15,0,r14 >> bne-lwarx_loop1 >> >> /* Fast sleep workaround */ >> +mfcrr16 /* Backup CR to a non-volatile register */ >> li r3,1 >> li r4,1 >> li r0,OPAL_CONFIG_CPU_IDLE_STATE >> bl opal_call_realmode >> +mtcrr16 /* Restore CR */ > > Why isn't the above already in the previous patch ? Also see my comment > about using a non-volatile CR instead. In the previous patch I wasn't using any CR after this OPAL call. Hence I had skipped it. As you suggested I'll avoid this by using CR[234]. > >> /* Clear Lock bit */ >> andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS >> stw r15,0(r14) >> >> -common_enter: /* common code for all the threads entering sleep */ >> +common_enter: /* common code for all the threads entering sleep or winkle*/ >> +bgt cr1,enter_winkle >> IDLE_STATE_ENTER_SEQ(PPC_SLEEP) >> +enter_winkle: >> +/* >> + * Note all register i.e per-core, per-subcore or per-thread is saved >> + * here since any thread in the core might wake up first >> + */ >> +
[PATCH v2] hv: hv_fcopy: drop the obsolete message on transfer failure
In the case the user-space daemon crashes, hangs or is killed, we
need to down the semaphore, otherwise, after the daemon starts next
time, the obsolete data in fcopy_transaction.message or
fcopy_transaction.fcopy_msg will be used immediately.
Reviewed-by: Vitaly Kuznetsov
Cc: K. Y. Srinivasan
Signed-off-by: Dexuan Cui
---
v2: I removed the "FCP" prefix as Greg asked.
I also updated the output message a little:
"FCP: failed to acquire the semaphore" -->
"can not acquire the semaphore: it is benign"
drivers/hv/hv_fcopy.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/hv/hv_fcopy.c b/drivers/hv/hv_fcopy.c
index 23b2ce2..c518ad9 100644
--- a/drivers/hv/hv_fcopy.c
+++ b/drivers/hv/hv_fcopy.c
@@ -86,6 +86,15 @@ static void fcopy_work_func(struct work_struct *dummy)
* process the pending transaction.
*/
fcopy_respond_to_host(HV_E_FAIL);
+
+ /* In the case the user-space daemon crashes, hangs or is killed, we
+* need to down the semaphore, otherwise, after the daemon starts next
+* time, the obsolete data in fcopy_transaction.message or
+* fcopy_transaction.fcopy_msg will be used immediately.
+*/
+ if (down_trylock(&fcopy_transaction.read_sema))
+ pr_debug("can not acquire the semaphore: it is benign\n");
+
}
static int fcopy_handle_handshake(u32 version)
--
1.9.1
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RE: [PATCH] hv: hv_fcopy: drop the obsolete message on transfer failure
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Thursday, November 27, 2014 7:54 AM
> To: Dexuan Cui
> Cc: linux-kernel@vger.kernel.org; driverdev-de...@linuxdriverproject.org;
> o...@aepfle.de; a...@canonical.com; jasow...@redhat.com; KY Srinivasan;
> Haiyang Zhang; vkuzn...@redhat.com
> Subject: Re: [PATCH] hv: hv_fcopy: drop the obsolete message on transfer
> failure
>
> On Tue, Nov 11, 2014 at 09:03:26PM -0800, Dexuan Cui wrote:
> > In the case the user-space daemon crashes, hangs or is killed, we
> > need to down the semaphore, otherwise, after the daemon starts next
> > time, the obsolete data in fcopy_transaction.message or
> > fcopy_transaction.fcopy_msg will be used immediately.
> >
> > Cc: K. Y. Srinivasan
> > Signed-off-by: Dexuan Cui
> > ---
> > drivers/hv/hv_fcopy.c | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/hv/hv_fcopy.c b/drivers/hv/hv_fcopy.c
> > index 23b2ce2..177122a 100644
> > --- a/drivers/hv/hv_fcopy.c
> > +++ b/drivers/hv/hv_fcopy.c
> > @@ -86,6 +86,15 @@ static void fcopy_work_func(struct work_struct
> *dummy)
> > * process the pending transaction.
> > */
> > fcopy_respond_to_host(HV_E_FAIL);
> > +
> > + /* In the case the user-space daemon crashes, hangs or is killed, we
> > +* need to down the semaphore, otherwise, after the daemon starts
> next
> > +* time, the obsolete data in fcopy_transaction.message or
> > +* fcopy_transaction.fcopy_msg will be used immediately.
> > +*/
> > + if (down_trylock(&fcopy_transaction.read_sema))
> > + pr_debug("FCP: failed to acquire the semaphore\n");
>
> Why is "FCP:" needed? pr_debug() should never need any type of prefix.
>
> Please fix.
>
> thanks,
>
> greg k-h
Ok, I'll send a v2 soon.
Thanks,
-- Dexuan
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Re: [PATCHv4 0/3] Kernel Live Patching
(2014/11/26 18:18), Jiri Kosina wrote: > On Wed, 26 Nov 2014, Masami Hiramatsu wrote: > >>> Note to Steve: >>> Masami's IPMODIFY patch is heading for -next via your tree. Once it >>> arrives, >>> I'll rebase and make the change to set IPMODIFY. Do not pull this for -next >>> yet. This version (v4) is for review and gathering acks. >> >> BTW, as we discussed IPMODIFY is an exclusive flag. So if we allocate >> ftrace_ops for each function in each patch, it could be conflict each >> other. > > Yup, this corresponds to what Petr brought up yesterday. There are cases > where all solutions (kpatch, kgraft, klp) would allocate multiple > ftrace_ops for a single function entry (think of patching one function > multiple times in a row). > > So it's not as easy as just setting the flag. > >> Maybe we need to have another ops hashtable to find such conflict and >> new handler to handle it. > > If I understand your proposal correctly, that would sound like a hackish > workaround, trying to basically trick the IPMODIFY flag semantics you just > implemented :) > > What I'd propose instead is to make sure that we always have > just a ftrace_ops per function entry, and only update the pointers there > as necessary. Fortunately we can do the switch atomically, by making use > of ->private. Would you mean per existing function entry, not per klp-func entry? If so, it sounds good to me too :) Thank you, -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Research Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] e1000: remove unused variables
I'm pretty sure those double reads are there for a reason, so most of
this I'm going to have to check on Monday. We have a long holiday
weekend here in the US.
I'm not sure why you're bothering with an old driver like this, but if
you haven't actually tried this on all the hardware it pertains to, I'm
going want to NAK this.
I should do this from my todd.fujin...@intel.com account but it's 10PM
on the first day of a long holiday weekend.
On Thu, 27 Nov 2014, Sudip Mukherjee wrote:
these variables were only being assigned some values, but were never
used.
Signed-off-by: Sudip Mukherjee
---
drivers/net/ethernet/intel/e1000/e1000_hw.c | 142 --
drivers/net/ethernet/intel/e1000/e1000_main.c | 3 -
2 files changed, 66 insertions(+), 79 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.c
b/drivers/net/ethernet/intel/e1000/e1000_hw.c
index 45c8c864..7812f59 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_hw.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_hw.c
@@ -154,7 +154,6 @@ static s32 e1000_set_phy_type(struct e1000_hw *hw)
*/
static void e1000_phy_init_script(struct e1000_hw *hw)
{
- u32 ret_val;
u16 phy_saved_data;
if (hw->phy_init_script) {
@@ -163,7 +162,7 @@ static void e1000_phy_init_script(struct e1000_hw *hw)
/* Save off the current value of register 0x2F5B to be restored
* at the end of this routine.
*/
- ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+ e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
/* Disabled the PHY transmitter */
e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
@@ -402,7 +401,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
{
u32 ctrl;
u32 ctrl_ext;
- u32 icr;
u32 manc;
u32 led_ctrl;
s32 ret_val;
@@ -527,7 +525,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
ew32(IMC, 0x);
/* Clear any pending interrupt events. */
- icr = er32(ICR);
+ er32(ICR);
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
@@ -2396,16 +2394,13 @@ static s32 e1000_check_for_serdes_link_generic(struct
e1000_hw *hw)
*/
s32 e1000_check_for_link(struct e1000_hw *hw)
{
- u32 rxcw = 0;
- u32 ctrl;
u32 status;
u32 rctl;
u32 icr;
- u32 signal = 0;
s32 ret_val;
u16 phy_data;
- ctrl = er32(CTRL);
+ er32(CTRL);
status = er32(STATUS);
/* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
@@ -2414,12 +2409,9 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
*/
if ((hw->media_type == e1000_media_type_fiber) ||
(hw->media_type == e1000_media_type_internal_serdes)) {
- rxcw = er32(RXCW);
+ er32(RXCW);
if (hw->media_type == e1000_media_type_fiber) {
- signal =
- (hw->mac_type >
-e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
if (status & E1000_STATUS_LU)
hw->get_link_status = false;
}
@@ -4698,78 +4690,76 @@ s32 e1000_led_off(struct e1000_hw *hw)
*/
static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
{
- volatile u32 temp;
-
- temp = er32(CRCERRS);
- temp = er32(SYMERRS);
- temp = er32(MPC);
- temp = er32(SCC);
- temp = er32(ECOL);
- temp = er32(MCC);
- temp = er32(LATECOL);
- temp = er32(COLC);
- temp = er32(DC);
- temp = er32(SEC);
- temp = er32(RLEC);
- temp = er32(XONRXC);
- temp = er32(XONTXC);
- temp = er32(XOFFRXC);
- temp = er32(XOFFTXC);
- temp = er32(FCRUC);
-
- temp = er32(PRC64);
- temp = er32(PRC127);
- temp = er32(PRC255);
- temp = er32(PRC511);
- temp = er32(PRC1023);
- temp = er32(PRC1522);
-
- temp = er32(GPRC);
- temp = er32(BPRC);
- temp = er32(MPRC);
- temp = er32(GPTC);
- temp = er32(GORCL);
- temp = er32(GORCH);
- temp = er32(GOTCL);
- temp = er32(GOTCH);
- temp = er32(RNBC);
- temp = er32(RUC);
- temp = er32(RFC);
- temp = er32(ROC);
- temp = er32(RJC);
- temp = er32(TORL);
- temp = er32(TORH);
- temp = er32(TOTL);
- temp = er32(TOTH);
- temp = er32(TPR);
- temp = er32(TPT);
-
- temp = er32(PTC64);
- temp = er32(PTC127);
- temp = er32(PTC255);
- temp = er32(PTC511);
- temp = er32(PTC1023);
- temp = er32(PTC1522);
-
- temp = er32(MPTC);
- temp = er32(BPTC);
+ er32(CRCERRS);
+ er32(SYMERRS);
+ er32(MPC);
+ er32(SCC);
+ er32(ECOL);
+ er32(MCC);
+ er32(LATECOL);
+ er32(COLC);
+ er32(DC);
+ er32(SEC);
+ e
Re: Re: [PATCH v3 0/5] ARM64: Add kernel probes(Kprobes) support
(2014/11/27 3:59), Steve Capper wrote: > The crash is extremely easy to reproduce. > > I've not observed any missed events on a kprobe on an arm64 system > that's still alive. > My (limited!) understanding is that this suggests there could be a > problem with how missed events from a recursive call to memcpy are > being handled. I think so too. BTW, could you bisect that? :) Thank you, -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Research Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4] selftest: size: Add size test for Linux kernel
On Wed, Nov 26, 2014 at 08:27:23PM -0800, Tim Bird wrote:
> --- /dev/null
> +++ b/tools/testing/selftests/size/Makefile
[...]
> +LIBGCC=$(shell $(CC) -print-libgcc-file-name)
> +
> +get_size: get_size.c
> + $(CC) --static -ffreestanding -nostartfiles \
> + -Wl,--entry=_start get_size.c $(LIBGCC) \
> + -o get_size
You don't need -Wl,--entry=_start; that's the default.
You shouldn't need to manually find libgcc, either; the compiler should
do that for you. What goes wrong if you don't include that? If you're
trying to link libgcc statically, try -static-libgcc.
Also, static is normally spelled -static, not --static.
> --- /dev/null
> +++ b/tools/testing/selftests/size/get_size.c
[...]
> +int print(const char *s)
This function, and all the others apart from _start, should be declared
static.
> +void num_to_str(unsigned long num, char *s)
Likewise, static.
> +{
> + unsigned long long temp, div;
> + int started;
> +
> + temp = num;
> + div = 100LL;
> + started = 0;
> + while (div) {
> + if (temp/div || started) {
> + *s++ = (unsigned char)(temp/div + '0');
> + started = 1;
> + }
> + temp -= (temp/div)*div;
> + div /= 10;
> + }
> + *s = 0;
> +}
You'd probably end up with significantly smaller code (and no divisions,
and thus no corner cases on architectures that need a special function
to do unsigned long long division) if you print in hex. You could also
drop the "no leading zeros" logic, and just *always* print a 64-bit
value as 16 hex digits.
> +int print_num(unsigned long num)
Likewise, static.
> +{
> + char num_buf[30];
> +
> + num_to_str(num, num_buf);
> + return print(num_buf);
> +}
> +
> +int print_k_value(const char *s, unsigned long num, unsigned long units)
> +{
> + unsigned long long temp;
> + int ccode;
> +
> + print(s);
> +
> + temp = num;
> + temp = (temp * units)/1024;
> + num = temp;
> + ccode = print_num(num);
> + print("\n");
> + return ccode;
> +}
I'd suggest dropping this entirely, and just always printing the exact
values returned by sysinfo. Drop the multiply, too, and just print
info.mem_unit as well. It's easy to post-process the value in a more
capable environment.
> +/* this program has no main(), as startup libraries are not used */
> +void _start(void)
> +{
> + int ccode;
> + struct sysinfo info;
> + unsigned long used;
> +
> + print("Testing system size.\n");
> + print("1..1\n");
> +
> + ccode = sysinfo(&info);
> + if (ccode < 0) {
> + print("not ok 1 get size runtime size\n");
Shouldn't the "not ok" here and the "ok" below have the same test
description?
> + print("# could not get sysinfo\n");
> + _exit(ccode);
> + }
> + /* ignore cache complexities for now */
> + used = info.totalram - info.freeram - info.bufferram;
> + print_k_value("ok 1 get runtime memory use # size = ", used,
> + info.mem_unit);
> +
> + print("# System runtime memory report (units in Kilobytes):\n");
> + print_k_value("# Total: ", info.totalram, info.mem_unit);
> + print_k_value("# Free: ", info.freeram, info.mem_unit);
> + print_k_value("# Buffer: ", info.bufferram, info.mem_unit);
> + print_k_value("# In use: ", used, info.mem_unit);
> +
> + _exit(0);
> +}
> --
> 1.8.2.2
>
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linux-next: manual merge of the irqchip tree with the mips tree
Hi Jason,
Today's linux-next merge of the irqchip tree got a conflict in
drivers/irqchip/Makefile between commit 8a19b8f19429 ("MIPS: Move GIC
to drivers/irqchip/") from the mips tree and commit 5fe3bba3088c
("irqchip: mtk-sysirq: Add sysirq interrupt polarity support") from the
irqchip tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
diff --cc drivers/irqchip/Makefile
index 021833079c91,5761696368f9..
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@@ -35,7 -37,7 +37,8 @@@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR)+= irq-crossbar.o
- obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
- irq-bcm7120-l2.o
+ obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
+ obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ)+= irq-keystone.o
+obj-$(CONFIG_MIPS_GIC)+= irq-mips-gic.o
+ obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
pgpjzFTnCtFBt.pgp
Description: OpenPGP digital signature
RE: [V5 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor
>First of all, can you fix your mail so that you have a proper 'From'? >That should be your real name (not bpqw), so that it gives a proper patch >author. >If you can't get your mail header to have the right 'From:' line, then it also >works to begin your mail with: Sorry for this confusion. This bpqw email is our software public mailbox dedicated to submit linux patch. Because our personal email title include Chinese name, this will result to messy code in from item. I have ever submit one patch many times by my personal mail, but I always didn't accept maintainer's response. So I think, maybe my patch with Chinese name has been moved into maintainer's junk folder. I don't know my mail from-field with Chinese name can or not be accepted, if can, I will submit next version patch by my personal mail. >> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. >> >> For Micron SPI NOR flash,enabling or disabling quad I/O protocol is >> controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O >> protocol bit 7. >> When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in quad I/O >> mode. >What's the difference between using EVCR and the ENTER QUAD I/O MODE >(35h) command I see in some of your datasheets? Are both supported on all >Micron quad I/O SPI NOR flash? There is no difference between using EVCR and the ENTER QUAD I/O MODE command. But, for some Micron spi nor, there no ENTER Quad I/O command(35h),such as n25q064. for all current Micron spi nor, if it support quad I/O mode, Using EVCR definitely be supported. So, we recommend that enable QUAD I/O mode by writing ECVR. >Also, which SPI NOR is this enabled for? I don't see any Micron entries in >spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag. Yes, we now don't see any Micron entries in spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag. But Micron spi nor in spi_nor_ids[] all support Quad I/O mode. maybe customer want to use default mode(extended I/O mode), When submitted relevant patch, they didn't SPI_NOR_QUAD_READ flag in the spi_nor_ids[]. This patch is just for wanting to enable Micron Quad I/O mode. >> Signed-off-by: bean huo >> Acked-by: Marek Vasut >> --- >> v1-v2: >> Modified to that capture wait_till_ready() >> return value,if error,directly return its >> the value. >> v2-v3: >> Directly use the reurning error value of >> read_reg and write_reg,instead of -EINVAL. >> v3-v4: >> Modify commit logs that wraped into 80 columns >> v4-v5: >> Rebuild new patch based on latest linux-mtd >Please rebase on l2-mtd.git. Sorry if that wasn't clear earlier. OK,I will rebase it and sumbit a new version. Thanks for your suggestion. >> +dev_err(nor->dev, >> +"error while writing EVCR register\n"); >Join the above two lines? Will be fixed it in the next version. >> +return ret; >> +} >> + >> +ret = wait_till_ready(nor); >It's spi_nor_wait_till_ready(), now. OK, will be fixed it. >> >> #define SR_QUAD_EN_MX 0x40/* Macronix Quad I/O */ >> >> +#define EVCR_QUAD_EN_MICRON0x80/* Micron Quad I/O */ >Like with other register bitfields (SR, FSR), please place a comment above to >describe the register, like: OK, will be fixed it. >Brian All in all ,thanks for your response and valuable suggestions. I will rebuild a new version, and submit it . ---Bean Huo--- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 3/4] powernv: cpuidle: Redesign idle states management
Hi Ben, On Thursday 27 November 2014 06:07 AM, Benjamin Herrenschmidt wrote: > >> >> @@ -37,8 +38,7 @@ >> >> /* >> * Pass requested state in r3: >> - * 0 - nap >> - * 1 - sleep >> + * r3 - PNV_THREAD_NAP/SLEEP/WINKLE >> * >> * To check IRQ_HAPPENED in r4 >> * 0 - don't check >> @@ -123,12 +123,62 @@ power7_enter_nap_mode: >> li r4,KVM_HWTHREAD_IN_NAP >> stb r4,HSTATE_HWTHREAD_STATE(r13) >> #endif >> -cmpwi cr0,r3,1 >> -beq 2f >> +stb r3,PACA_THREAD_IDLE_STATE(r13) >> +cmpwi cr1,r3,PNV_THREAD_SLEEP >> +bge cr1,2f >> IDLE_STATE_ENTER_SEQ(PPC_NAP) >> /* No return */ >> -2: IDLE_STATE_ENTER_SEQ(PPC_SLEEP) >> -/* No return */ >> +2: >> +/* Sleep or winkle */ >> +li r7,1 >> +mfspr r8,SPRN_PIR >> +/* >> + * The last 3 bits of PIR represents the thread id of a cpu >> + * in power8. This will need adjusting for power7. >> + */ >> +andi. r8,r8,0x07 /* Get thread id into r8 */ >> +rotld r7,r7,r8 >> + >> +ld r14,PACA_CORE_IDLE_STATE_PTR(r13) > > I assume we have already saved all non-volatile registers ? Because you > are clobbering one here and more below. Yes. At this stage the all non-volatile registers are already saved in stack. > >> +lwarx_loop1: >> +lwarx r15,0,r14 >> +andcr15,r15,r7 /* Clear thread bit */ >> + >> +andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS >> +beq last_thread >> + >> +/* Not the last thread to goto sleep */ >> +stwcx. r15,0,r14 >> +bne-lwarx_loop1 >> +b common_enter >> + >> +last_thread: >> +LOAD_REG_ADDR(r3, pnv_need_fastsleep_workaround) >> +lbz r3,0(r3) >> +cmpwi r3,1 >> +bne common_enter > > This looks wrong. If the workaround is 0, we don't do the stwcx. at > all... Did you try with pnv_need_fastsleep_workaround set to 0 ? It > should work most of the time as long as you don't hit the fairly > rare race window :) > My bad. I missed the stwcx. in the pnv_need_fastsleep_workaround = 0 path. > Also it would be nice to make the above a dynamically patches feature > section, though that means pnv_need_fastsleep_workaround needs to turn > into a CPU feature bit and that needs to be done *very* early on. > > Another option is to patch out manually from the pnv code the pair: > > andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS > beq last_thread > > To turn them into nops by hand rather than using the feature system. > Okay. I'll see which works out best here. >> +/* >> + * Last thread of the core entering sleep. Last thread needs to execute >> + * the hardware bug workaround code. Before that, set the lock bit to >> + * avoid the race of other threads waking up and undoing workaround >> + * before workaround is applied. >> + */ >> +ori r15,r15,PNV_CORE_IDLE_LOCK_BIT >> +stwcx. r15,0,r14 >> +bne-lwarx_loop1 >> + >> +/* Fast sleep workaround */ >> +li r3,1 >> +li r4,1 >> +li r0,OPAL_CONFIG_CPU_IDLE_STATE >> +bl opal_call_realmode >> + >> +/* Clear Lock bit */ > > It's a lock, I would add a lwsync here to be safe, and I would add an > isync before the bne- above. Just to ensure that whatever is done > inside that locked section remains in there. > Okay. Will add it. >> +andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS >> +stw r15,0(r14) >> + >> +common_enter: /* common code for all the threads entering sleep */ >> +IDLE_STATE_ENTER_SEQ(PPC_SLEEP) >> >> _GLOBAL(power7_idle) >> /* Now check if user or arch enabled NAP mode */ >> @@ -141,49 +191,16 @@ _GLOBAL(power7_idle) >> >> _GLOBAL(power7_nap) >> mr r4,r3 >> -li r3,0 >> +li r3,PNV_THREAD_NAP >> b power7_powersave_common >> /* No return */ >> >> _GLOBAL(power7_sleep) >> -li r3,1 >> +li r3,PNV_THREAD_SLEEP >> li r4,1 >> b power7_powersave_common >> /* No return */ >> >> -/* >> - * Make opal call in realmode. This is a generic function to be called >> - * from realmode from reset vector. It handles endianess. >> - * >> - * r13 - paca pointer >> - * r1 - stack pointer >> - * r3 - opal token >> - */ >> -opal_call_realmode: >> -mflrr12 >> -std r12,_LINK(r1) >> -ld r2,PACATOC(r13) >> -/* Set opal return address */ >> -LOAD_REG_ADDR(r0,return_from_opal_call) >> -mtlrr0 >> -/* Handle endian-ness */ >> -li r0,MSR_LE >> -mfmsr r12 >> -andcr12,r12,r0 >> -mtspr SPRN_HSRR1,r12 >> -mr r0,r3 /* Move opal token to r0 */ >> -LOAD_REG_ADDR(r11,opal) >> -ld r12,8(r11) >> -ld r2,0(r11) >> -mtspr SPRN_HSRR0,r12 >> -hrfid >> - >> -return_from_opal_call: >> -FIXUP_ENDIAN >> -ld r0,_LINK(r1) >> -mtlrr0 >> -blr >> - >> #define CHECK_H
Re: [PATCH v9 1/6] arm64: ptrace: add NT_ARM_SYSTEM_CALL regset
On 11/26/2014 09:41 PM, Will Deacon wrote:
Hi Akashi,
On Wed, Nov 26, 2014 at 04:49:46AM +, AKASHI Takahiro wrote:
This regeset is intended to be used to get and set a system call number
while tracing.
There was some discussion about possible approaches to do so:
(1) modify x8 register with ptrace(PTRACE_SETREGSET) indirectly,
and update regs->syscallno later on in syscall_trace_enter(), or
(2) define a dedicated regset for this purpose as on s390, or
(3) support ptrace(PTRACE_SET_SYSCALL) as on arch/arm
Thinking of the fact that user_pt_regs doesn't expose 'syscallno' to
tracer as well as that secure_computing() expects a changed syscall number,
especially case of -1, to be visible before this function returns in
syscall_trace_enter(), (1) doesn't work well.
We will take (2) since it looks much cleaner.
Signed-off-by: AKASHI Takahiro
---
arch/arm64/kernel/ptrace.c | 35 +++
include/uapi/linux/elf.h |1 +
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 8a4ae8e..8b98781 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -551,6 +551,32 @@ static int tls_set(struct task_struct *target, const
struct user_regset *regset,
return ret;
}
+static int system_call_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ struct pt_regs *regs = task_pt_regs(target);
+
+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ ®s->syscallno, 0, -1);
Does this work for big-endian machines? regs->syscallno is a u64, but the
regset defines it as an int. I think you need to copy to a temporary
register first.
Right. I will fix it.
Do you prefer to use s32, instead of int, like other regsets?
Thanks,
-Takahiro AKASHI
Will
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[git pull] Please pull mpe.git for-linus branch (for powerpc)
Hi Linus, Here are five fixes for you to pull please. I think these are all rc6 material, but I'm still learning so let me know if you disagree :) They're all CC'ed to stable except the "Fix PE state format" one which went in this release. cheers The following changes since commit d7ce4377494adfaf8afb15ecf4f07d399bbf13d9: powerpc/fsl_msi: mark the msi cascade handler IRQF_NO_THREAD (2014-11-17 22:00:30 -0600) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git for-linus for you to fetch changes up to 152d44a853e42952f6c8a504fb1f8eefd21fd5fd: powerpc: 32 bit getcpu VDSO function uses 64 bit instructions (2014-11-27 09:42:12 +1100) Anton Blanchard (1): powerpc: 32 bit getcpu VDSO function uses 64 bit instructions Gavin Shan (2): powerpc/eeh: Fix PE state format powerpc/powernv: Replace OPAL_DEASSERT_RESET with EEH_RESET_DEACTIVATE Laurent Dufour (1): powerpc/pseries: Fix endiannes issue in RTAS call from xmon Mahesh Salgaonkar (1): powerpc/powernv: Fix the hmi event version check. arch/powerpc/kernel/eeh_sysfs.c | 2 +- arch/powerpc/kernel/vdso32/getcpu.S | 4 ++-- arch/powerpc/platforms/powernv/opal-hmi.c | 2 +- arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- arch/powerpc/xmon/xmon.c | 6 +++--- 5 files changed, 8 insertions(+), 8 deletions(-) signature.asc Description: This is a digitally signed message part
Re: [PATCH v2 11/19] selftests/memory-hotplug: add install target to enable installing test
(2014/11/12 5:27), Shuah Khan wrote: > Add a new make target to enable installing test. This target > installs test in the kselftest install location and add to the > kselftest script to run the test. Install target can be run > only from top level source dir. > > Signed-off-by: Shuah Khan > --- > tools/testing/selftests/memory-hotplug/Makefile| 17 +- > .../selftests/memory-hotplug/mem-on-off-test.sh| 238 > + > .../selftests/memory-hotplug/on-off-test.sh| 238 > - > 3 files changed, 253 insertions(+), 240 deletions(-) > create mode 100644 tools/testing/selftests/memory-hotplug/mem-on-off-test.sh > delete mode 100644 tools/testing/selftests/memory-hotplug/on-off-test.sh > > diff --git a/tools/testing/selftests/memory-hotplug/Makefile > b/tools/testing/selftests/memory-hotplug/Makefile > index d46b8d4..8921631 100644 > --- a/tools/testing/selftests/memory-hotplug/Makefile > +++ b/tools/testing/selftests/memory-hotplug/Makefile > @@ -1,9 +1,22 @@ > +TEST_STR=/bin/bash ./mem-on-off-test.sh -r 2 || echo memory-hotplug > selftests: [FAIL] > + > all: > > +install: > +ifdef INSTALL_KSFT_PATH > + install ./mem-on-off-test.sh $(INSTALL_KSFT_PATH)/mem-on-off-test.sh > + @echo echo Start memory hotplug test >> $(KSELFTEST) > + @echo "$(TEST_STR)" >> $(KSELFTEST) >> $(KSELFTEST) > + @echo echo End memory hotplug test >> $(KSELFTEST) > + @echo echo == >> $(KSELFTEST) > +else > + @echo Run make kselftest_install in top level source directory > +endif I saw this pattern repeated many times in this series. Can we make it a macro and include it instead of repeating this code? Thank you, -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Research Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [BUG] [PATCH] next: cyapa: fix inop touchpad after resume on Acer C720
Jeremiah, I didn't make the special patch for the linux-next before, so I don't know why this patch is there and have issue. Based on current code in the linux-next, I made below patch to fix this issue. Could you please try again with attached patch fix. Thanks, Dudley > -Original Message- > From: Jeremiah Mahler [mailto:jmmah...@gmail.com] > Sent: 2014?11?27? 4:03 > To: Dudley Du > Cc: linux-kernel@vger.kernel.org > Subject: Re: [BUG] [PATCH] next: cyapa: fix inop touchpad after resume on Acer > C720 > > Dudley, > > On Wed, Nov 26, 2014 at 06:16:00AM +, Dudley Du wrote: > > More info: I did all testings based on kernel 3.14.0 on Acer C70. > > > > I am testing with linux-next 3.18-rc6 on an Acer C720. > > http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ > > > Thanks, > > Dudley > > > [] > > -- > - Jeremiah Mahler >From bb717b1c1525ef6b889f0ef735d920eed9e76e72 Mon Sep 17 00:00:00 2001 From: Dudley Du Date: Thu, 27 Nov 2014 13:35:09 +0800 Subject: [PATCH] input: cyapa: fix irq error issue in cyapa_resume To: dmitry.torok...@gmail.com, jmmah...@gmail.com Cc: ble...@google.com, linux-in...@vger.kernel.org This patch is aimed to fix the irq error happened on cyapa_resume when doing suspend/resume testing. The root cause of this issue is that the cyapa->irq has been removed but still used in the driver. Signed-off-by: Dudley Du --- drivers/input/mouse/cyapa.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/input/mouse/cyapa.c b/drivers/input/mouse/cyapa.c index c84a9eb..caaba7b 100644 --- a/drivers/input/mouse/cyapa.c +++ b/drivers/input/mouse/cyapa.c @@ -938,7 +938,7 @@ static int __maybe_unused cyapa_suspend(struct device *dev) power_mode, error); if (device_may_wakeup(dev)) - cyapa->irq_wake = (enable_irq_wake(cyapa->irq) == 0); + cyapa->irq_wake = (enable_irq_wake(cyapa->client->irq) == 0); mutex_unlock(&input->mutex); @@ -956,7 +956,7 @@ static int __maybe_unused cyapa_resume(struct device *dev) mutex_lock(&input->mutex); if (device_may_wakeup(dev) && cyapa->irq_wake) - disable_irq_wake(cyapa->irq); + disable_irq_wake(cyapa->client->irq); power_mode = input->users ? PWR_MODE_FULL_ACTIVE : PWR_MODE_OFF; error = cyapa_set_power_mode(cyapa, PWR_MODE_FULL_ACTIVE); @@ -964,7 +964,7 @@ static int __maybe_unused cyapa_resume(struct device *dev) dev_warn(dev, "resume: set power mode to %d failed: %d\n", power_mode, error); - enable_irq(cyapa->irq); + enable_irq(cyapa->client->irq); mutex_unlock(&input->mutex); -- 1.9.1 input-cyapa-fix-irq-error-issue-in-cyapa_resume.patch Description: Binary data
Re: [PATCH v2 03/19] selftests: add install target to enable installing selftests
(2014/11/12 5:27), Shuah Khan wrote: > Add a new make target to enable installing selftests. This > new target will call install targets for the tests that are > specified in INSTALL_TARGETS. During install, a script is > generated to run tests that are installed. This script will > be installed in the selftest install directory. Individual > test Makefiles are changed to add to the script. This will > allow new tests to add install and run test commands to the > generated kselftest script. run_tests target runs the > generated kselftest script to run tests when it is initiated > from from "make kselftest" from top level source directory. > > Approach: > > make kselftest_target: > -- exports kselftest INSTALL_KSFT_PATH >default $(INSTALL_MOD_PATH)/lib/kselftest/$(KERNELRELEASE) > -- exports path for ksefltest.sh > -- runs selftests make install target: > > selftests make install target > -- creates kselftest.sh script in install install dir > -- runs install targets for all INSTALL_TARGETS >(Note: ftrace and powerpc aren't included in INSTALL_TARGETS, > to not add more content to patch v1 series. This work > will happen soon. In this series these two targets are > run after running the generated kselftest script, without > any regression in the way these tests are run with > "make kselftest" prior to this work.) > -- install target can be run only from top level source dir. > > Individual test make install targets: > -- install test programs and/or scripts in install dir > -- append to the ksefltest.sh file to add commands to run test > -- install target can be run only from top level source dir. > > Adds the following new ways to initiate selftests: > -- Installing and running kselftest from install directory >by running "make kselftest" > -- Running kselftest script from install directory > > Maintains the following ways to run tests: > -- make -C tools/testing/selftests run_tests > -- make -C tools/testing/selftests TARGETS=target run_tests >Ability specify targets: e.g TARGETS=net > -- make run_tests from tools/testing/selftests > -- make run_tests from individual test directories: >e.g: make run_tests in tools/testing/selftests/breakpoints > > Signed-off-by: Shuah Khan > --- > tools/testing/selftests/Makefile | 31 ++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/tools/testing/selftests/Makefile > b/tools/testing/selftests/Makefile > index 45f145c..b9bdc1d 100644 > --- a/tools/testing/selftests/Makefile > +++ b/tools/testing/selftests/Makefile > @@ -16,6 +16,10 @@ TARGETS += sysctl > TARGETS += firmware > TARGETS += ftrace > > +INSTALL_TARGETS = breakpoints cpu-hotplug efivarfs firmware ipc > +INSTALL_TARGETS += kcmp memfd memory-hotplug mqueue mount net > +INSTALL_TARGETS += ptrace sysctl timers user vm > + > TARGETS_HOTPLUG = cpu-hotplug > TARGETS_HOTPLUG += memory-hotplug > I think KSELFTEST itself should be defined here, since that is not a parameter. > @@ -24,10 +28,35 @@ all: > make -C $$TARGET; \ > done; > > -run_tests: all > +install: > +ifdef INSTALL_KSFT_PATH > + make all > + @echo #!/bin/sh\n# Kselftest Run Tests >> $(KSELFTEST) > + @echo # This file is generated during kselftest_install >> $(KSELFTEST) > + @echo # Please don't change it !!\n >> $(KSELFTEST) > + @echo echo == >> $(KSELFTEST) > + for TARGET in $(INSTALL_TARGETS); do \ > + echo Installing $$TARGET; \ > + make -C $$TARGET install; \ Please pass O= option and others here. > + done; > + chmod +x $(KSELFTEST) > +else > + @echo Run make kselftest_install in top level source directory > +endif > + > +run_tests: > +ifdef INSTALL_KSFT_PATH > + @cd $(INSTALL_KSFT_PATH); ./kselftest.sh; cd - We'd better use some macro instead of ./kselftest.sh? Thank you, > +# TODO: include ftrace and powerpc in install targets > + for TARGET in ftrace powerpc; do \ > + make -C $$TARGET run_tests; \ > + done; > +else > + make all > for TARGET in $(TARGETS); do \ > make -C $$TARGET run_tests; \ > done; > +endif > > hotplug: > for TARGET in $(TARGETS_HOTPLUG); do \ > -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH net-next 0/6] allow eBPF programs to be attached to sockets
Introduce BPF_PROG_TYPE_SOCKET_FILTER type of eBPF programs that can be
attached to sockets with setsockopt().
Allow such programs to access maps via lookup/update/delete helpers.
This feature was previewed by bpf manpage in commit b4fc1a460f30("Merge branch
'bpf-next'")
Now it can actually run.
1st patch adds LD_ABS/LD_IND instruction verification and
2nd patch adds new setsockopt() flag.
Patches 3-6 are examples in assembler and in C.
Though native eBPF programs are way more powerful than classic filters
(attachable through similar setsockopt() call), they don't have skb field
accessors yet. Like skb->pkt_type, skb->dev->ifindex are not accessible.
There are sevaral ways to achieve that. That will be in the next set of patches.
So in this set native eBPF programs can only read data from packet and
access maps.
The most powerful example is sockex2_kern.c from patch 6 where ~200 lines of C
are compiled into ~300 of eBPF instructions.
It shows how quite complex packet parsing can be done.
LLVM used to build examples is at https://github.com/iovisor/llvm
which is fork of llvm trunk that I'm cleaning up for upstreaming.
Alexei Starovoitov (6):
bpf: verifier: add checks for BPF_ABS | BPF_IND instructions
net: sock: allow eBPF programs to be attached to sockets
samples: bpf: example of stateful socket filtering
samples: bpf: elf_bpf file loader
samples: bpf: trivial eBPF program in C
samples: bpf: large eBPF program in C
arch/alpha/include/uapi/asm/socket.h |3 +
arch/avr32/include/uapi/asm/socket.h |3 +
arch/cris/include/uapi/asm/socket.h|3 +
arch/frv/include/uapi/asm/socket.h |3 +
arch/ia64/include/uapi/asm/socket.h|3 +
arch/m32r/include/uapi/asm/socket.h|3 +
arch/mips/include/uapi/asm/socket.h|3 +
arch/mn10300/include/uapi/asm/socket.h |3 +
arch/parisc/include/uapi/asm/socket.h |3 +
arch/powerpc/include/uapi/asm/socket.h |3 +
arch/s390/include/uapi/asm/socket.h|3 +
arch/sparc/include/uapi/asm/socket.h |3 +
arch/xtensa/include/uapi/asm/socket.h |3 +
include/linux/bpf.h|4 +
include/linux/filter.h |1 +
include/uapi/asm-generic/socket.h |3 +
include/uapi/linux/bpf.h |1 +
kernel/bpf/verifier.c | 70 ++-
net/core/filter.c | 97 +-
net/core/sock.c| 13 ++
samples/bpf/Makefile | 20 +++
samples/bpf/bpf_helpers.h | 40 ++
samples/bpf/bpf_load.c | 203 ++
samples/bpf/bpf_load.h | 24
samples/bpf/libbpf.c | 28 +
samples/bpf/libbpf.h | 15 ++-
samples/bpf/sock_example.c | 97 ++
samples/bpf/sockex1_kern.c | 23
samples/bpf/sockex1_user.c | 49
samples/bpf/sockex2_kern.c | 215
samples/bpf/sockex2_user.c | 44 +++
31 files changed, 981 insertions(+), 5 deletions(-)
create mode 100644 samples/bpf/bpf_helpers.h
create mode 100644 samples/bpf/bpf_load.c
create mode 100644 samples/bpf/bpf_load.h
create mode 100644 samples/bpf/sock_example.c
create mode 100644 samples/bpf/sockex1_kern.c
create mode 100644 samples/bpf/sockex1_user.c
create mode 100644 samples/bpf/sockex2_kern.c
create mode 100644 samples/bpf/sockex2_user.c
--
1.7.9.5
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[PATCH net-next 3/6] samples: bpf: example of stateful socket filtering
this socket filter example does:
- creates arraymap in kernel with key 4 bytes and value 8 bytes
- loads eBPF program:
r0 = skb[14 + 9]; // load one byte of ip->proto
*(u32*)(fp - 4) = r0;
value = bpf_map_lookup_elem(map_fd, fp - 4);
if (value)
(*(u64*)value) += 1;
- attaches this program to raw socket
- every second user space reads map[tcp], map[udp], map[icmp] to see
how many packets of given protocol were seen on loopback interface
Signed-off-by: Alexei Starovoitov
---
samples/bpf/Makefile |2 +
samples/bpf/libbpf.c | 28 +
samples/bpf/libbpf.h | 13 ++
samples/bpf/sock_example.c | 97
4 files changed, 140 insertions(+)
create mode 100644 samples/bpf/sock_example.c
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 0718d9ce4619..f46d3492d032 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -3,9 +3,11 @@ obj- := dummy.o
# List of programs to build
hostprogs-y := test_verifier test_maps
+hostprogs-y += sock_example
test_verifier-objs := test_verifier.o libbpf.o
test_maps-objs := test_maps.o libbpf.o
+sock_example-objs := sock_example.o libbpf.o
# Tell kbuild to always build the programs
always := $(hostprogs-y)
diff --git a/samples/bpf/libbpf.c b/samples/bpf/libbpf.c
index 17bb520eb57f..46d50b7ddf79 100644
--- a/samples/bpf/libbpf.c
+++ b/samples/bpf/libbpf.c
@@ -7,6 +7,10 @@
#include
#include
#include
+#include
+#include
+#include
+#include
#include "libbpf.h"
static __u64 ptr_to_u64(void *ptr)
@@ -93,3 +97,27 @@ int bpf_prog_load(enum bpf_prog_type prog_type,
return syscall(__NR_bpf, BPF_PROG_LOAD, &attr, sizeof(attr));
}
+
+int open_raw_sock(const char *name)
+{
+ struct sockaddr_ll sll;
+ int sock;
+
+ sock = socket(PF_PACKET, SOCK_RAW | SOCK_NONBLOCK | SOCK_CLOEXEC,
htons(ETH_P_ALL));
+ if (sock < 0) {
+ printf("cannot create raw socket\n");
+ return -1;
+ }
+
+ memset(&sll, 0, sizeof(sll));
+ sll.sll_family = AF_PACKET;
+ sll.sll_ifindex = if_nametoindex(name);
+ sll.sll_protocol = htons(ETH_P_ALL);
+ if (bind(sock, (struct sockaddr *)&sll, sizeof(sll)) < 0) {
+ printf("bind to %s: %s\n", name, strerror(errno));
+ close(sock);
+ return -1;
+ }
+
+ return sock;
+}
diff --git a/samples/bpf/libbpf.h b/samples/bpf/libbpf.h
index f8678e5f48bf..cc62ad4d95de 100644
--- a/samples/bpf/libbpf.h
+++ b/samples/bpf/libbpf.h
@@ -99,6 +99,16 @@ extern char bpf_log_buf[LOG_BUF_SIZE];
BPF_LD_IMM64_RAW(DST, BPF_PSEUDO_MAP_FD, MAP_FD)
+/* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
+
+#define BPF_LD_ABS(SIZE, IMM) \
+ ((struct bpf_insn) {\
+ .code = BPF_LD | BPF_SIZE(SIZE) | BPF_ABS, \
+ .dst_reg = 0, \
+ .src_reg = 0, \
+ .off = 0, \
+ .imm = IMM })
+
/* Memory load, dst_reg = *(uint *) (src_reg + off16) */
#define BPF_LDX_MEM(SIZE, DST, SRC, OFF) \
@@ -169,4 +179,7 @@ extern char bpf_log_buf[LOG_BUF_SIZE];
.off = 0, \
.imm = 0 })
+/* create RAW socket and bind to interface 'name' */
+int open_raw_sock(const char *name);
+
#endif
diff --git a/samples/bpf/sock_example.c b/samples/bpf/sock_example.c
new file mode 100644
index ..d74b58523458
--- /dev/null
+++ b/samples/bpf/sock_example.c
@@ -0,0 +1,97 @@
+/* eBPF example program:
+ * - creates arraymap in kernel with key 4 bytes and value 8 bytes
+ *
+ * - loads eBPF program:
+ * r0 = skb[14 + 9]; // load one byte of ip->proto
+ * *(u32*)(fp - 4) = r0;
+ * value = bpf_map_lookup_elem(map_fd, fp - 4);
+ * if (value)
+ *(*(u64*)value) += 1;
+ *
+ * - attaches this program to eth0 raw socket
+ *
+ * - every second user space reads map[tcp], map[udp], map[icmp] to see
+ * how many packets of given protocol were seen on eth0
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "libbpf.h"
+
+static int test_sock(void)
+{
+ int sock = -1, map_fd, prog_fd, i, key;
+ long long value = 0, tcp_cnt, udp_cnt, icmp_cnt;
+
+ map_fd = bpf_create_map(BPF_MAP_TYPE_ARRAY, sizeof(key), sizeof(value),
+ 256);
+ if (map_fd < 0) {
+ printf("failed to create map '%s'\n", strerror(errno));
+ goto cleanup;
+ }
+
+ struct bpf_insn prog[] = {
+ BPF_MOV64_REG(BPF_REG_6, BPF_REG_1),
+ BPF_LD_ABS(BPF_B, 14 + 9 /* R0 = ip->proto */),
+ BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_0, -4), /
[PATCH net-next 2/6] net: sock: allow eBPF programs to be attached to sockets
introduce new setsockopt() command: setsockopt(sock, SOL_SOCKET, SO_ATTACH_BPF, &prog_fd, sizeof(prog_fd)) where prog_fd was received from syscall bpf(BPF_PROG_LOAD, attr, ...) and attr->prog_type == BPF_PROG_TYPE_SOCKET_FILTER setsockopt() calls bpf_prog_get() which increments refcnt of the program, so it doesn't get unloaded while socket is using the program. The same eBPF program can be attached to multiple sockets. User task exit automatically closes socket which calls sk_filter_uncharge() which decrements refcnt of eBPF program Signed-off-by: Alexei Starovoitov --- Note, I'm not happy about 'ifdef', but 'select or depend BPF_SYSCALL' will make tinification folks cringe, so use ifdef until native eBPF use cases become widespread. --- arch/alpha/include/uapi/asm/socket.h |3 + arch/avr32/include/uapi/asm/socket.h |3 + arch/cris/include/uapi/asm/socket.h|3 + arch/frv/include/uapi/asm/socket.h |3 + arch/ia64/include/uapi/asm/socket.h|3 + arch/m32r/include/uapi/asm/socket.h|3 + arch/mips/include/uapi/asm/socket.h|3 + arch/mn10300/include/uapi/asm/socket.h |3 + arch/parisc/include/uapi/asm/socket.h |3 + arch/powerpc/include/uapi/asm/socket.h |3 + arch/s390/include/uapi/asm/socket.h|3 + arch/sparc/include/uapi/asm/socket.h |3 + arch/xtensa/include/uapi/asm/socket.h |3 + include/linux/bpf.h|4 ++ include/linux/filter.h |1 + include/uapi/asm-generic/socket.h |3 + net/core/filter.c | 97 +++- net/core/sock.c| 13 + 18 files changed, 155 insertions(+), 2 deletions(-) diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h index e2fe0700b3b4..9a20821b111c 100644 --- a/arch/alpha/include/uapi/asm/socket.h +++ b/arch/alpha/include/uapi/asm/socket.h @@ -89,4 +89,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _UAPI_ASM_SOCKET_H */ diff --git a/arch/avr32/include/uapi/asm/socket.h b/arch/avr32/include/uapi/asm/socket.h index 92121b0f5b98..2b65ed6b277c 100644 --- a/arch/avr32/include/uapi/asm/socket.h +++ b/arch/avr32/include/uapi/asm/socket.h @@ -82,4 +82,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _UAPI__ASM_AVR32_SOCKET_H */ diff --git a/arch/cris/include/uapi/asm/socket.h b/arch/cris/include/uapi/asm/socket.h index 60f60f5b9b35..e2503d9f1869 100644 --- a/arch/cris/include/uapi/asm/socket.h +++ b/arch/cris/include/uapi/asm/socket.h @@ -84,6 +84,9 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _ASM_SOCKET_H */ diff --git a/arch/frv/include/uapi/asm/socket.h b/arch/frv/include/uapi/asm/socket.h index 2c6890209ea6..4823ad125578 100644 --- a/arch/frv/include/uapi/asm/socket.h +++ b/arch/frv/include/uapi/asm/socket.h @@ -82,5 +82,8 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _ASM_SOCKET_H */ diff --git a/arch/ia64/include/uapi/asm/socket.h b/arch/ia64/include/uapi/asm/socket.h index 09a93fb566f6..59be3d87f86d 100644 --- a/arch/ia64/include/uapi/asm/socket.h +++ b/arch/ia64/include/uapi/asm/socket.h @@ -91,4 +91,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _ASM_IA64_SOCKET_H */ diff --git a/arch/m32r/include/uapi/asm/socket.h b/arch/m32r/include/uapi/asm/socket.h index e8589819c274..7bc4cb273856 100644 --- a/arch/m32r/include/uapi/asm/socket.h +++ b/arch/m32r/include/uapi/asm/socket.h @@ -82,4 +82,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _ASM_M32R_SOCKET_H */ diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 2e9ee8c55a10..dec3c850f36b 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -100,4 +100,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _UAPI_ASM_SOCKET_H */ diff --git a/arch/mn10300/include/uapi/asm/socket.h b/arch/mn10300/include/uapi/asm/socket.h index f3492e8c9f70..cab7d6d50051 100644 --- a/arch/mn10300/include/uapi/asm/socket.h +++ b/arch/mn10300/include/uapi/asm/socket.h @@ -82,4 +82,7 @@ #define SO_INCOMING_CPU49 +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + #endif /* _ASM_SOCKET_H */ diff --git a/arch/parisc/include/uapi/asm/socket.h b/arch/parisc/include/uapi/asm/socke
[PATCH net-next 1/6] bpf: verifier: add checks for BPF_ABS | BPF_IND instructions
introduce program type BPF_PROG_TYPE_SOCKET_FILTER that is used
for attaching programs to sockets where ctx == skb.
add verifier checks for ABS/IND instructions which can only be seen
in socket filters, therefore the check:
if (env->prog->aux->prog_type != BPF_PROG_TYPE_SOCKET_FILTER)
verbose("BPF_LD_ABS|IND instructions are only allowed in socket filters\n");
Signed-off-by: Alexei Starovoitov
---
include/uapi/linux/bpf.h |1 +
kernel/bpf/verifier.c| 70 --
2 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index 4a3d0f84f178..45da7ec7d274 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -117,6 +117,7 @@ enum bpf_map_type {
enum bpf_prog_type {
BPF_PROG_TYPE_UNSPEC,
+ BPF_PROG_TYPE_SOCKET_FILTER,
};
/* flags for BPF_MAP_UPDATE_ELEM command */
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index b6a1f7c14a67..a28e09c7825d 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -1172,6 +1172,70 @@ static int check_ld_imm(struct verifier_env *env, struct
bpf_insn *insn)
return 0;
}
+/* verify safety of LD_ABS|LD_IND instructions:
+ * - they can only appear in the programs where ctx == skb
+ * - since they are wrappers of function calls, they scratch R1-R5 registers,
+ * preserve R6-R9, and store return value into R0
+ *
+ * Implicit input:
+ * ctx == skb == R6 == CTX
+ *
+ * Explicit input:
+ * SRC == any register
+ * IMM == 32-bit immediate
+ *
+ * Output:
+ * R0 - 8/16/32-bit skb data converted to cpu endianness
+ */
+static int check_ld_abs(struct verifier_env *env, struct bpf_insn *insn)
+{
+ struct reg_state *regs = env->cur_state.regs;
+ u8 mode = BPF_MODE(insn->code);
+ struct reg_state *reg;
+ int i, err;
+
+ if (env->prog->aux->prog_type != BPF_PROG_TYPE_SOCKET_FILTER) {
+ verbose("BPF_LD_ABS|IND instructions are only allowed in socket
filters\n");
+ return -EINVAL;
+ }
+
+ if (insn->dst_reg != BPF_REG_0 || insn->off != 0 ||
+ (mode == BPF_ABS && insn->src_reg != BPF_REG_0)) {
+ verbose("BPF_LD_ABS uses reserved fields\n");
+ return -EINVAL;
+ }
+
+ /* check whether implicit source operand (register R6) is readable */
+ err = check_reg_arg(regs, BPF_REG_6, SRC_OP);
+ if (err)
+ return err;
+
+ if (regs[BPF_REG_6].type != PTR_TO_CTX) {
+ verbose("at the time of BPF_LD_ABS|IND R6 != pointer to skb\n");
+ return -EINVAL;
+ }
+
+ if (mode == BPF_IND) {
+ /* check explicit source operand */
+ err = check_reg_arg(regs, insn->src_reg, SRC_OP);
+ if (err)
+ return err;
+ }
+
+ /* reset caller saved regs to unreadable */
+ for (i = 0; i < CALLER_SAVED_REGS; i++) {
+ reg = regs + caller_saved[i];
+ reg->type = NOT_INIT;
+ reg->imm = 0;
+ }
+
+ /* mark destination R0 register as readable, since it contains
+* the value fetched from the packet
+*/
+ regs[BPF_REG_0].type = UNKNOWN_VALUE;
+ return 0;
+}
+
/* non-recursive DFS pseudo code
* 1 procedure DFS-iterative(G,v):
* 2 label v as discovered
@@ -1677,8 +1741,10 @@ process_bpf_exit:
u8 mode = BPF_MODE(insn->code);
if (mode == BPF_ABS || mode == BPF_IND) {
- verbose("LD_ABS is not supported yet\n");
- return -EINVAL;
+ err = check_ld_abs(env, insn);
+ if (err)
+ return err;
+
} else if (mode == BPF_IMM) {
err = check_ld_imm(env, insn);
if (err)
--
1.7.9.5
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[PATCH net-next 4/6] samples: bpf: elf_bpf file loader
simple .o parser and loader using BPF syscall.
.o is a standard ELF generated by LLVM backend
It parses elf file compiled by llvm .c->.o
- parses 'maps' section and creates maps via BPF syscall
- parses 'license' section and passes it to syscall
- parses elf relocations for BPF maps and adjusts BPF_LD_IMM64 insns
by storing map_fd into insn->imm and marking such insns as BPF_PSEUDO_MAP_FD
- loads eBPF programs via BPF syscall
One ELF file can contain multiple BPF programs.
int load_bpf_file(char *path);
populates prog_fd[] and map_fd[] with FDs received from bpf syscall
bpf_helpers.h - helper functions available to eBPF programs written in C
Signed-off-by: Alexei Starovoitov
---
These helpers and loader are done as separate patch to make eBPF C examples
(that follow in the next patches) to focus on demonstrating programming
of eBPF in restricted C.
---
samples/bpf/bpf_helpers.h | 40 +
samples/bpf/bpf_load.c| 203 +
samples/bpf/bpf_load.h| 24 ++
3 files changed, 267 insertions(+)
create mode 100644 samples/bpf/bpf_helpers.h
create mode 100644 samples/bpf/bpf_load.c
create mode 100644 samples/bpf/bpf_load.h
diff --git a/samples/bpf/bpf_helpers.h b/samples/bpf/bpf_helpers.h
new file mode 100644
index ..ca0333146006
--- /dev/null
+++ b/samples/bpf/bpf_helpers.h
@@ -0,0 +1,40 @@
+#ifndef __BPF_HELPERS_H
+#define __BPF_HELPERS_H
+
+/* helper macro to place programs, maps, license in
+ * different sections in elf_bpf file. Section names
+ * are interpreted by elf_bpf loader
+ */
+#define SEC(NAME) __attribute__((section(NAME), used))
+
+/* helper functions called from eBPF programs written in C */
+static void *(*bpf_map_lookup_elem)(void *map, void *key) =
+ (void *) BPF_FUNC_map_lookup_elem;
+static int (*bpf_map_update_elem)(void *map, void *key, void *value,
+ unsigned long long flags) =
+ (void *) BPF_FUNC_map_update_elem;
+static int (*bpf_map_delete_elem)(void *map, void *key) =
+ (void *) BPF_FUNC_map_delete_elem;
+
+/* llvm builtin functions that eBPF C program may use to
+ * emit BPF_LD_ABS and BPF_LD_IND instructions
+ */
+struct sk_buff;
+unsigned long long load_byte(void *skb,
+unsigned long long off) asm("llvm.bpf.load.byte");
+unsigned long long load_half(void *skb,
+unsigned long long off) asm("llvm.bpf.load.half");
+unsigned long long load_word(void *skb,
+unsigned long long off) asm("llvm.bpf.load.word");
+
+/* a helper structure used by eBPF C program
+ * to describe map attributes to elf_bpf loader
+ */
+struct bpf_map_def {
+ unsigned int type;
+ unsigned int key_size;
+ unsigned int value_size;
+ unsigned int max_entries;
+};
+
+#endif
diff --git a/samples/bpf/bpf_load.c b/samples/bpf/bpf_load.c
new file mode 100644
index ..1831d236382b
--- /dev/null
+++ b/samples/bpf/bpf_load.c
@@ -0,0 +1,203 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "libbpf.h"
+#include "bpf_helpers.h"
+#include "bpf_load.h"
+
+static char license[128];
+static bool processed_sec[128];
+int map_fd[MAX_MAPS];
+int prog_fd[MAX_PROGS];
+int prog_cnt;
+
+static int load_and_attach(const char *event, struct bpf_insn *prog, int size)
+{
+ int fd;
+ bool is_socket = strncmp(event, "socket", 6) == 0;
+
+ if (!is_socket)
+ /* tracing events tbd */
+ return -1;
+
+ fd = bpf_prog_load(BPF_PROG_TYPE_SOCKET_FILTER,
+ prog, size, license);
+
+ if (fd < 0) {
+ printf("bpf_prog_load() err=%d\n%s", errno, bpf_log_buf);
+ return -1;
+ }
+
+ prog_fd[prog_cnt++] = fd;
+
+ return 0;
+}
+
+static int load_maps(struct bpf_map_def *maps, int len)
+{
+ int i;
+
+ for (i = 0; i < len / sizeof(struct bpf_map_def); i++) {
+
+ map_fd[i] = bpf_create_map(maps[i].type,
+ maps[i].key_size,
+ maps[i].value_size,
+ maps[i].max_entries);
+ if (map_fd[i] < 0)
+ return 1;
+ }
+ return 0;
+}
+
+static int get_sec(Elf *elf, int i, GElf_Ehdr *ehdr, char **shname,
+ GElf_Shdr *shdr, Elf_Data **data)
+{
+ Elf_Scn *scn;
+
+ scn = elf_getscn(elf, i);
+ if (!scn)
+ return 1;
+
+ if (gelf_getshdr(scn, shdr) != shdr)
+ return 2;
+
+ *shname = elf_strptr(elf, ehdr->e_shstrndx, shdr->sh_name);
+ if (!*shname || !shdr->sh_size)
+ return 3;
+
+ *data = elf_getdata(scn, 0);
+ if (!*data || elf_getdata(scn, *data) != NULL)
+ return 4;
+
+ return 0;
+}
+
+static int par
[PATCH net-next 5/6] samples: bpf: trivial eBPF program in C
this example does the same task as previous socket example
in assembler, but this one does it in C.
eBPF program in kernel does:
int index = load_byte(skb, 14 + 9); /* ip_proto */
long *value;
value = bpf_map_lookup_elem(&my_map, &index);
if (value)
__sync_fetch_and_add(value, 1);
Corresponding user space reads map[tcp], map[udp], map[icmp]
and prints protocol stats every second
Signed-off-by: Alexei Starovoitov
---
samples/bpf/Makefile | 14 +
samples/bpf/libbpf.h |2 +-
samples/bpf/sockex1_kern.c | 23 +
samples/bpf/sockex1_user.c | 49
4 files changed, 87 insertions(+), 1 deletion(-)
create mode 100644 samples/bpf/sockex1_kern.c
create mode 100644 samples/bpf/sockex1_user.c
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index f46d3492d032..770d145186c3 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -4,12 +4,26 @@ obj- := dummy.o
# List of programs to build
hostprogs-y := test_verifier test_maps
hostprogs-y += sock_example
+hostprogs-y += sockex1
test_verifier-objs := test_verifier.o libbpf.o
test_maps-objs := test_maps.o libbpf.o
sock_example-objs := sock_example.o libbpf.o
+sockex1-objs := bpf_load.o libbpf.o sockex1_user.o
# Tell kbuild to always build the programs
always := $(hostprogs-y)
+always += sockex1_kern.o
HOSTCFLAGS += -I$(objtree)/usr/include
+
+HOSTCFLAGS_bpf_load.o += -I$(objtree)/usr/include -Wno-unused-variable
+HOSTLOADLIBES_sockex1 += -lelf
+
+# point this to your LLVM backend with bpf support
+LLC=$(srctree)/tools/bpf/llvm/bld/Debug+Asserts/bin/llc
+
+%.o: %.c
+ clang $(NOSTDINC_FLAGS) $(LINUXINCLUDE) $(EXTRA_CFLAGS) \
+ -D__KERNEL__ -Wno-unused-value -Wno-pointer-sign \
+ -O2 -emit-llvm -c $< -o -| $(LLC) -march=bpf -filetype=obj -o $@
diff --git a/samples/bpf/libbpf.h b/samples/bpf/libbpf.h
index cc62ad4d95de..58c5fe1bdba1 100644
--- a/samples/bpf/libbpf.h
+++ b/samples/bpf/libbpf.h
@@ -15,7 +15,7 @@ int bpf_prog_load(enum bpf_prog_type prog_type,
const struct bpf_insn *insns, int insn_len,
const char *license);
-#define LOG_BUF_SIZE 8192
+#define LOG_BUF_SIZE 65536
extern char bpf_log_buf[LOG_BUF_SIZE];
/* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
diff --git a/samples/bpf/sockex1_kern.c b/samples/bpf/sockex1_kern.c
new file mode 100644
index ..e662779467de
--- /dev/null
+++ b/samples/bpf/sockex1_kern.c
@@ -0,0 +1,23 @@
+#include
+#include "bpf_helpers.h"
+
+struct bpf_map_def SEC("maps") my_map = {
+ .type = BPF_MAP_TYPE_ARRAY,
+ .key_size = sizeof(u32),
+ .value_size = sizeof(long),
+ .max_entries = 256,
+};
+
+SEC("socket1")
+int bpf_prog1(struct sk_buff *skb)
+{
+ int index = load_byte(skb, 14 + 9);
+ long *value;
+
+ value = bpf_map_lookup_elem(&my_map, &index);
+ if (value)
+ __sync_fetch_and_add(value, 1);
+
+ return 0;
+}
+char _license[] SEC("license") = "GPL";
diff --git a/samples/bpf/sockex1_user.c b/samples/bpf/sockex1_user.c
new file mode 100644
index ..34a443ff3831
--- /dev/null
+++ b/samples/bpf/sockex1_user.c
@@ -0,0 +1,49 @@
+#include
+#include
+#include
+#include "libbpf.h"
+#include "bpf_load.h"
+#include
+#include
+
+int main(int ac, char **argv)
+{
+ char filename[256];
+ FILE *f;
+ int i, sock;
+
+ snprintf(filename, sizeof(filename), "%s_kern.o", argv[0]);
+
+ if (load_bpf_file(filename)) {
+ printf("%s", bpf_log_buf);
+ return 1;
+ }
+
+ sock = open_raw_sock("lo");
+
+ assert(setsockopt(sock, SOL_SOCKET, SO_ATTACH_BPF, prog_fd,
+ sizeof(prog_fd[0])) == 0);
+
+ f = popen("ping -c5 localhost", "r");
+ (void) f;
+
+ for (i = 0; i < 5; i++) {
+ long long tcp_cnt, udp_cnt, icmp_cnt;
+ int key;
+
+ key = IPPROTO_TCP;
+ assert(bpf_lookup_elem(map_fd[0], &key, &tcp_cnt) == 0);
+
+ key = IPPROTO_UDP;
+ assert(bpf_lookup_elem(map_fd[0], &key, &udp_cnt) == 0);
+
+ key = IPPROTO_ICMP;
+ assert(bpf_lookup_elem(map_fd[0], &key, &icmp_cnt) == 0);
+
+ printf("TCP %lld UDP %lld ICMP %lld packets\n",
+ tcp_cnt, udp_cnt, icmp_cnt);
+ sleep(1);
+ }
+
+ return 0;
+}
--
1.7.9.5
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[PATCH net-next 6/6] samples: bpf: large eBPF program in C
sockex2_kern.c is purposefully large eBPF program in C.
llvm compiles ~200 lines of C code into ~300 eBPF instructions.
It's similar to __skb_flow_dissect() to demonstrate that complex packet parsing
can be done by eBPF.
Then it uses (struct flow_keys)->dst IP address (or hash of ipv6 dst) to keep
stats of number of packets per IP.
User space loads eBPF program, attaches it to loopback interface and prints
dest_ip->#packets stats every second.
Usage:
$sudo samples/bpf/sockex2
ip 127.0.0.1 count 19
ip 127.0.0.1 count 178115
ip 127.0.0.1 count 369437
ip 127.0.0.1 count 559841
ip 127.0.0.1 count 750539
Signed-off-by: Alexei Starovoitov
---
samples/bpf/Makefile |4 +
samples/bpf/sockex2_kern.c | 215
samples/bpf/sockex2_user.c | 44 +
3 files changed, 263 insertions(+)
create mode 100644 samples/bpf/sockex2_kern.c
create mode 100644 samples/bpf/sockex2_user.c
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 770d145186c3..b5b3600dcdf5 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -5,20 +5,24 @@ obj- := dummy.o
hostprogs-y := test_verifier test_maps
hostprogs-y += sock_example
hostprogs-y += sockex1
+hostprogs-y += sockex2
test_verifier-objs := test_verifier.o libbpf.o
test_maps-objs := test_maps.o libbpf.o
sock_example-objs := sock_example.o libbpf.o
sockex1-objs := bpf_load.o libbpf.o sockex1_user.o
+sockex2-objs := bpf_load.o libbpf.o sockex2_user.o
# Tell kbuild to always build the programs
always := $(hostprogs-y)
always += sockex1_kern.o
+always += sockex2_kern.o
HOSTCFLAGS += -I$(objtree)/usr/include
HOSTCFLAGS_bpf_load.o += -I$(objtree)/usr/include -Wno-unused-variable
HOSTLOADLIBES_sockex1 += -lelf
+HOSTLOADLIBES_sockex2 += -lelf
# point this to your LLVM backend with bpf support
LLC=$(srctree)/tools/bpf/llvm/bld/Debug+Asserts/bin/llc
diff --git a/samples/bpf/sockex2_kern.c b/samples/bpf/sockex2_kern.c
new file mode 100644
index ..6f0135f0f217
--- /dev/null
+++ b/samples/bpf/sockex2_kern.c
@@ -0,0 +1,215 @@
+#include
+#include "bpf_helpers.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#define IP_MF 0x2000
+#define IP_OFFSET 0x1FFF
+
+struct vlan_hdr {
+ __be16 h_vlan_TCI;
+ __be16 h_vlan_encapsulated_proto;
+};
+
+struct flow_keys {
+ __be32 src;
+ __be32 dst;
+ union {
+ __be32 ports;
+ __be16 port16[2];
+ };
+ __u16 thoff;
+ __u8 ip_proto;
+};
+
+static inline int proto_ports_offset(__u64 proto)
+{
+ switch (proto) {
+ case IPPROTO_TCP:
+ case IPPROTO_UDP:
+ case IPPROTO_DCCP:
+ case IPPROTO_ESP:
+ case IPPROTO_SCTP:
+ case IPPROTO_UDPLITE:
+ return 0;
+ case IPPROTO_AH:
+ return 4;
+ default:
+ return 0;
+ }
+}
+
+static inline int ip_is_fragment(struct sk_buff *ctx, __u64 nhoff)
+{
+ return load_half(ctx, nhoff + offsetof(struct iphdr, frag_off))
+ & (IP_MF | IP_OFFSET);
+}
+
+static inline __u32 ipv6_addr_hash(struct sk_buff *ctx, __u64 off)
+{
+ __u64 w0 = load_word(ctx, off);
+ __u64 w1 = load_word(ctx, off + 4);
+ __u64 w2 = load_word(ctx, off + 8);
+ __u64 w3 = load_word(ctx, off + 12);
+
+ return (__u32)(w0 ^ w1 ^ w2 ^ w3);
+}
+
+static inline __u64 parse_ip(struct sk_buff *skb, __u64 nhoff, __u64 *ip_proto,
+struct flow_keys *flow)
+{
+ __u64 verlen;
+
+ if (unlikely(ip_is_fragment(skb, nhoff)))
+ *ip_proto = 0;
+ else
+ *ip_proto = load_byte(skb, nhoff + offsetof(struct iphdr,
protocol));
+
+ if (*ip_proto != IPPROTO_GRE) {
+ flow->src = load_word(skb, nhoff + offsetof(struct iphdr,
saddr));
+ flow->dst = load_word(skb, nhoff + offsetof(struct iphdr,
daddr));
+ }
+
+ verlen = load_byte(skb, nhoff + 0/*offsetof(struct iphdr, ihl)*/);
+ if (likely(verlen == 0x45))
+ nhoff += 20;
+ else
+ nhoff += (verlen & 0xF) << 2;
+
+ return nhoff;
+}
+
+static inline __u64 parse_ipv6(struct sk_buff *skb, __u64 nhoff, __u64
*ip_proto,
+ struct flow_keys *flow)
+{
+ *ip_proto = load_byte(skb,
+ nhoff + offsetof(struct ipv6hdr, nexthdr));
+ flow->src = ipv6_addr_hash(skb,
+ nhoff + offsetof(struct ipv6hdr, saddr));
+ flow->dst = ipv6_addr_hash(skb,
+ nhoff + offsetof(struct ipv6hdr, daddr));
+ nhoff += sizeof(struct ipv6hdr);
+
+ return nhoff;
+}
+
+static inline bool flow_dissector(struct sk_buff *skb, struct flow_keys *flow)
+{
+ __u64 nhoff = ETH_HLEN;
+ __u64 ip_proto;
+ __u64 proto = load_half(skb, 12);
+ int poff;
+
+ if (proto == ETH_P_8021AD) {
+
Re: [PATCH] Update MAINTAINERS for solo6x10
On Mon, 17 Nov 2014 20:59:23 +0400 Andrey Utkin wrote: > Signed-off-by: Andrey Utkin > --- > MAINTAINERS | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index bb38f02..f5cef1b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -8787,7 +8787,9 @@ S: Maintained > F: drivers/leds/leds-net48xx.c > > SOFTLOGIC 6x10 MPEG CODEC > -M: Ismael Luceno > +M: Bluecherry Maintainers > +M: Andrey Utkin > +M: Andrey Utkin > L: linux-me...@vger.kernel.org > S: Supported > F: drivers/media/pci/solo6x10/ Please do not remove me, I'm still here, just a little tight on the schedule. Though my corp.bluecherry.net address stopped working again... pgprxRZ5IDnxP.pgp Description: OpenPGP digital signature
Re: [PATCH v2 02/19] kbuild: kselftest_install - add a new make target to install selftests
(2014/11/12 5:27), Shuah Khan wrote: > Add a new make target to install to install kernel selftests. > This new target will build and install selftests. kselftest > target now depends on kselftest_install and runs the generated > kselftest script to reduce duplicate work and for common look > and feel when running tests. > > Approach: > > make kselftest_target: kselftest_install? > -- exports kselftest INSTALL_KSFT_PATH >default $(INSTALL_MOD_PATH)/lib/kselftest/$(KERNELRELEASE) > -- exports path for ksefltest.sh > -- runs selftests make install target: This direction is OK to me. BTW, I've found another path to make selftest in Makefile, Actually you can do make -C tools/ selftest And there are selftest_install and selftest_clean targets (but currently it has a bug and doesn't work, anyway) I think we'd better do subdir make instead of adding these targets. This means that "make kselftest*" should be an alias of "make -C tools/ selftest*" Also, I'd like to request passing some options like as O=$(objtree) so that we can make test kmodules in selftests. Thank you, -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Research Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] staging: lustre: fix sparse warnings related to lock context imbalance
On Wed, Nov 26, 2014 at 12:54:43PM -0800, Greg KH wrote: > > Ugh, how horrid, please just delete these functions and push down the > spin_lock/unlock calls down into the places these are called. > > Same for these. > > Same thing here. Hello Greg, Thanks for your comments, I will write a v2. -- Cheers, Loic -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] e1000: remove unused variables
these variables were only being assigned some values, but were never
used.
Signed-off-by: Sudip Mukherjee
---
drivers/net/ethernet/intel/e1000/e1000_hw.c | 142 --
drivers/net/ethernet/intel/e1000/e1000_main.c | 3 -
2 files changed, 66 insertions(+), 79 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.c
b/drivers/net/ethernet/intel/e1000/e1000_hw.c
index 45c8c864..7812f59 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_hw.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_hw.c
@@ -154,7 +154,6 @@ static s32 e1000_set_phy_type(struct e1000_hw *hw)
*/
static void e1000_phy_init_script(struct e1000_hw *hw)
{
- u32 ret_val;
u16 phy_saved_data;
if (hw->phy_init_script) {
@@ -163,7 +162,7 @@ static void e1000_phy_init_script(struct e1000_hw *hw)
/* Save off the current value of register 0x2F5B to be restored
* at the end of this routine.
*/
- ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+ e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
/* Disabled the PHY transmitter */
e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
@@ -402,7 +401,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
{
u32 ctrl;
u32 ctrl_ext;
- u32 icr;
u32 manc;
u32 led_ctrl;
s32 ret_val;
@@ -527,7 +525,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
ew32(IMC, 0x);
/* Clear any pending interrupt events. */
- icr = er32(ICR);
+ er32(ICR);
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
@@ -2396,16 +2394,13 @@ static s32 e1000_check_for_serdes_link_generic(struct
e1000_hw *hw)
*/
s32 e1000_check_for_link(struct e1000_hw *hw)
{
- u32 rxcw = 0;
- u32 ctrl;
u32 status;
u32 rctl;
u32 icr;
- u32 signal = 0;
s32 ret_val;
u16 phy_data;
- ctrl = er32(CTRL);
+ er32(CTRL);
status = er32(STATUS);
/* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
@@ -2414,12 +2409,9 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
*/
if ((hw->media_type == e1000_media_type_fiber) ||
(hw->media_type == e1000_media_type_internal_serdes)) {
- rxcw = er32(RXCW);
+ er32(RXCW);
if (hw->media_type == e1000_media_type_fiber) {
- signal =
- (hw->mac_type >
-e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
if (status & E1000_STATUS_LU)
hw->get_link_status = false;
}
@@ -4698,78 +4690,76 @@ s32 e1000_led_off(struct e1000_hw *hw)
*/
static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
{
- volatile u32 temp;
-
- temp = er32(CRCERRS);
- temp = er32(SYMERRS);
- temp = er32(MPC);
- temp = er32(SCC);
- temp = er32(ECOL);
- temp = er32(MCC);
- temp = er32(LATECOL);
- temp = er32(COLC);
- temp = er32(DC);
- temp = er32(SEC);
- temp = er32(RLEC);
- temp = er32(XONRXC);
- temp = er32(XONTXC);
- temp = er32(XOFFRXC);
- temp = er32(XOFFTXC);
- temp = er32(FCRUC);
-
- temp = er32(PRC64);
- temp = er32(PRC127);
- temp = er32(PRC255);
- temp = er32(PRC511);
- temp = er32(PRC1023);
- temp = er32(PRC1522);
-
- temp = er32(GPRC);
- temp = er32(BPRC);
- temp = er32(MPRC);
- temp = er32(GPTC);
- temp = er32(GORCL);
- temp = er32(GORCH);
- temp = er32(GOTCL);
- temp = er32(GOTCH);
- temp = er32(RNBC);
- temp = er32(RUC);
- temp = er32(RFC);
- temp = er32(ROC);
- temp = er32(RJC);
- temp = er32(TORL);
- temp = er32(TORH);
- temp = er32(TOTL);
- temp = er32(TOTH);
- temp = er32(TPR);
- temp = er32(TPT);
-
- temp = er32(PTC64);
- temp = er32(PTC127);
- temp = er32(PTC255);
- temp = er32(PTC511);
- temp = er32(PTC1023);
- temp = er32(PTC1522);
-
- temp = er32(MPTC);
- temp = er32(BPTC);
+ er32(CRCERRS);
+ er32(SYMERRS);
+ er32(MPC);
+ er32(SCC);
+ er32(ECOL);
+ er32(MCC);
+ er32(LATECOL);
+ er32(COLC);
+ er32(DC);
+ er32(SEC);
+ er32(RLEC);
+ er32(XONRXC);
+ er32(XONTXC);
+ er32(XOFFRXC);
+ er32(XOFFTXC);
+ er32(FCRUC);
+
+ er32(PRC64);
+ er32(PRC127);
+ er32(PRC255);
+ er32(PRC511);
+ er32(PRC1023);
+ er32(PRC1522);
+
+ er32(GPRC);
+ er32(BPRC);
+ er32(MPRC);
+ er32(GPTC);
+ er32(GORCL);
+ er32(GORCH);
+ er32(GOTCL);
+ er32(GOTCH);
+ er32(RNBC);
+ er32(RUC);
+ er
