Re: [PATCH 3/3] Input: ti_am335x_tsc - Ack pending IRQs at probe and before suspend

[Lee Jones]

On Mon, 16 May 2016, Vignesh R wrote:

> From: Grygorii Strashko 
> 
> It is seen that just enabling the TSC module triggers a HW_PEN IRQ
> without any interaction with touchscreen by user. This results in first
> suspend/resume sequence to fail as system immediately wakes up from
> suspend as soon as HW_PEN IRQ is enabled in suspend handler. due to the
> pending IRQ. Therefore clear all IRQs at probe and also in suspend
> callback for sanity.
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Vignesh R 
> ---
>  drivers/input/touchscreen/ti_am335x_tsc.c | 2 ++
>  include/linux/mfd/ti_am335x_tscadc.h  | 1 +

For the MFD change:
  Acked-by: Lee Jones 

>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/input/touchscreen/ti_am335x_tsc.c 
> b/drivers/input/touchscreen/ti_am335x_tsc.c
> index 4683ed18b9f8..d2c55b5730e6 100644
> --- a/drivers/input/touchscreen/ti_am335x_tsc.c
> +++ b/drivers/input/touchscreen/ti_am335x_tsc.c
> @@ -441,6 +441,7 @@ static int titsc_probe(struct platform_device *pdev)
>   dev_err(>dev, "irq wake enable failed.\n");
>   }
>  
> + titsc_writel(ts_dev, REG_IRQSTATUS, IRQENB_MASK);
>   titsc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO0THRES);
>   titsc_writel(ts_dev, REG_IRQENABLE, IRQENB_EOS);
>   err = titsc_config_wires(ts_dev);
> @@ -506,6 +507,7 @@ static int __maybe_unused titsc_suspend(struct device 
> *dev)
>  
>   tscadc_dev = ti_tscadc_dev_get(to_platform_device(dev));
>   if (device_may_wakeup(tscadc_dev->dev)) {
> + titsc_writel(ts_dev, REG_IRQSTATUS, IRQENB_MASK);
>   idle = titsc_readl(ts_dev, REG_IRQENABLE);
>   titsc_writel(ts_dev, REG_IRQENABLE,
>   (idle | IRQENB_HW_PEN));
> diff --git a/include/linux/mfd/ti_am335x_tscadc.h 
> b/include/linux/mfd/ti_am335x_tscadc.h
> index 1fd50dcfe47c..a7ca0f908ba8 100644
> --- a/include/linux/mfd/ti_am335x_tscadc.h
> +++ b/include/linux/mfd/ti_am335x_tscadc.h
> @@ -60,6 +60,7 @@
>  #define IRQENB_FIFO1OVRRUN   BIT(6)
>  #define IRQENB_FIFO1UNDRFLW  BIT(7)
>  #define IRQENB_PENUP BIT(9)
> +#define IRQENB_MASK  (0x7FF)
>  
>  /* Step Configuration */
>  #define STEPCONFIG_MODE_MASK (3 << 0)

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 3/3] Input: ti_am335x_tsc - Ack pending IRQs at probe and before suspend

[Lee Jones]

On Mon, 16 May 2016, Vignesh R wrote:

> From: Grygorii Strashko 
> 
> It is seen that just enabling the TSC module triggers a HW_PEN IRQ
> without any interaction with touchscreen by user. This results in first
> suspend/resume sequence to fail as system immediately wakes up from
> suspend as soon as HW_PEN IRQ is enabled in suspend handler. due to the
> pending IRQ. Therefore clear all IRQs at probe and also in suspend
> callback for sanity.
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Vignesh R 
> ---
>  drivers/input/touchscreen/ti_am335x_tsc.c | 2 ++
>  include/linux/mfd/ti_am335x_tscadc.h  | 1 +

For the MFD change:
  Acked-by: Lee Jones 

>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/input/touchscreen/ti_am335x_tsc.c 
> b/drivers/input/touchscreen/ti_am335x_tsc.c
> index 4683ed18b9f8..d2c55b5730e6 100644
> --- a/drivers/input/touchscreen/ti_am335x_tsc.c
> +++ b/drivers/input/touchscreen/ti_am335x_tsc.c
> @@ -441,6 +441,7 @@ static int titsc_probe(struct platform_device *pdev)
>   dev_err(>dev, "irq wake enable failed.\n");
>   }
>  
> + titsc_writel(ts_dev, REG_IRQSTATUS, IRQENB_MASK);
>   titsc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO0THRES);
>   titsc_writel(ts_dev, REG_IRQENABLE, IRQENB_EOS);
>   err = titsc_config_wires(ts_dev);
> @@ -506,6 +507,7 @@ static int __maybe_unused titsc_suspend(struct device 
> *dev)
>  
>   tscadc_dev = ti_tscadc_dev_get(to_platform_device(dev));
>   if (device_may_wakeup(tscadc_dev->dev)) {
> + titsc_writel(ts_dev, REG_IRQSTATUS, IRQENB_MASK);
>   idle = titsc_readl(ts_dev, REG_IRQENABLE);
>   titsc_writel(ts_dev, REG_IRQENABLE,
>   (idle | IRQENB_HW_PEN));
> diff --git a/include/linux/mfd/ti_am335x_tscadc.h 
> b/include/linux/mfd/ti_am335x_tscadc.h
> index 1fd50dcfe47c..a7ca0f908ba8 100644
> --- a/include/linux/mfd/ti_am335x_tscadc.h
> +++ b/include/linux/mfd/ti_am335x_tscadc.h
> @@ -60,6 +60,7 @@
>  #define IRQENB_FIFO1OVRRUN   BIT(6)
>  #define IRQENB_FIFO1UNDRFLW  BIT(7)
>  #define IRQENB_PENUP BIT(9)
> +#define IRQENB_MASK  (0x7FF)
>  
>  /* Step Configuration */
>  #define STEPCONFIG_MODE_MASK (3 << 0)

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [linux-sunxi] Re: [PATCH 4/9] spi: sun4i: add DMA support

[Michal Suchanek]

On 20 August 2015 at 16:56, Maxime Ripard
 wrote:

>> + /* Enable Dedicated DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + reg |= SUN4I_CTL_DMAMC_DEDICATED;
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, trigger);
>> + } else {
>> + dev_dbg(>master->dev, "Using PIO mode for transfer\n");
>> +
>> + /* Disable DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG,
>> + reg & ~SUN4I_CTL_DMAMC_DEDICATED);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
>> +
>> + /* Fill the TX FIFO */
>> + /* Filling the fifo fully causes timeout for some reason
>> +  * at least on spi2 on a10s */
>> + sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
>> + }
>> +
>>   /* Start the transfer */
>>   reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>>   sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
>> @@ -303,7 +363,12 @@ static int sun4i_spi_transfer_one(struct spi_master 
>> *master,
>>   goto out;
>>   }
>>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> Nope, this is only meant for async_tx. You should register a callback
> in your transfer that will mark the completion structure as completed,
> and then drain the FIFO only if not using DMA.

What exactly is wrong with this?

I did not observe data corruption. Passing desc_rx to
dma_wait_for_async_tx looks odd on closer inspection, though. Will
look through some other spi driver code.

>> - init_completion(>done);
>> + master->dma_tx = dma_request_slave_channel_reason(>dev, "tx");
>> + if (IS_ERR(master->dma_tx)) {
>> + dev_err(>dev, "Unable to acquire DMA channel TX\n");
>> + ret = PTR_ERR(master->dma_tx);
>> + goto err_free_master;
>> + }
>> +
>> + dma_sconfig.direction = DMA_MEM_TO_DEV;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>> +
>> + ret = dmaengine_slave_config(master->dma_tx, _sconfig);
>> + if (ret) {
>> + dev_err(>dev, "Unable to configure TX DMA slave\n");
>> + goto err_tx_dma_release;
>> + }
>> +
>> + master->dma_rx = dma_request_slave_channel_reason(>dev, "rx");
>> + if (IS_ERR(master->dma_rx)) {
>> + dev_err(>dev, "Unable to acquire DMA channel RX\n");
>> + ret = PTR_ERR(master->dma_rx);
>> + goto err_tx_dma_release;
>> + }
>> +
>> + dma_sconfig.direction = DMA_DEV_TO_MEM;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>
> We can't use a higher bust size?

Who actually does?

It accomplishes the transfer with burst size of 1 so that's good enough.

Researching alignment requirements and other oddities of Chinese
controllers when larger burst size is used can be topic for another
patch.


On 20 August 2015 at 20:58, Mark Brown  wrote:
> On Thu, Aug 20, 2015 at 02:19:46PM -, Emilio López wrote:
>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> What if it's a transmit only transfer?  We'll fall over to this...
>
>> + } else {
>> + sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + }
>
> ...which manually reads data from the FIFO which doesn't seem like what
... which should be empty since RX is not enabled.
> we want, won't it conflict with the DMA?
It does not seem to conflict in practice.


Thanks

Michal

Re: [linux-sunxi] Re: [PATCH 4/9] spi: sun4i: add DMA support

[Michal Suchanek]

On 20 August 2015 at 16:56, Maxime Ripard
 wrote:

>> + /* Enable Dedicated DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + reg |= SUN4I_CTL_DMAMC_DEDICATED;
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, trigger);
>> + } else {
>> + dev_dbg(>master->dev, "Using PIO mode for transfer\n");
>> +
>> + /* Disable DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG,
>> + reg & ~SUN4I_CTL_DMAMC_DEDICATED);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
>> +
>> + /* Fill the TX FIFO */
>> + /* Filling the fifo fully causes timeout for some reason
>> +  * at least on spi2 on a10s */
>> + sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
>> + }
>> +
>>   /* Start the transfer */
>>   reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>>   sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
>> @@ -303,7 +363,12 @@ static int sun4i_spi_transfer_one(struct spi_master 
>> *master,
>>   goto out;
>>   }
>>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> Nope, this is only meant for async_tx. You should register a callback
> in your transfer that will mark the completion structure as completed,
> and then drain the FIFO only if not using DMA.

What exactly is wrong with this?

I did not observe data corruption. Passing desc_rx to
dma_wait_for_async_tx looks odd on closer inspection, though. Will
look through some other spi driver code.

>> - init_completion(>done);
>> + master->dma_tx = dma_request_slave_channel_reason(>dev, "tx");
>> + if (IS_ERR(master->dma_tx)) {
>> + dev_err(>dev, "Unable to acquire DMA channel TX\n");
>> + ret = PTR_ERR(master->dma_tx);
>> + goto err_free_master;
>> + }
>> +
>> + dma_sconfig.direction = DMA_MEM_TO_DEV;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>> +
>> + ret = dmaengine_slave_config(master->dma_tx, _sconfig);
>> + if (ret) {
>> + dev_err(>dev, "Unable to configure TX DMA slave\n");
>> + goto err_tx_dma_release;
>> + }
>> +
>> + master->dma_rx = dma_request_slave_channel_reason(>dev, "rx");
>> + if (IS_ERR(master->dma_rx)) {
>> + dev_err(>dev, "Unable to acquire DMA channel RX\n");
>> + ret = PTR_ERR(master->dma_rx);
>> + goto err_tx_dma_release;
>> + }
>> +
>> + dma_sconfig.direction = DMA_DEV_TO_MEM;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>
> We can't use a higher bust size?

Who actually does?

It accomplishes the transfer with burst size of 1 so that's good enough.

Researching alignment requirements and other oddities of Chinese
controllers when larger burst size is used can be topic for another
patch.


On 20 August 2015 at 20:58, Mark Brown  wrote:
> On Thu, Aug 20, 2015 at 02:19:46PM -, Emilio López wrote:
>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> What if it's a transmit only transfer?  We'll fall over to this...
>
>> + } else {
>> + sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + }
>
> ...which manually reads data from the FIFO which doesn't seem like what
... which should be empty since RX is not enabled.
> we want, won't it conflict with the DMA?
It does not seem to conflict in practice.


Thanks

Michal

Re: CQ and RDMA READ/WRITE APIs

[Christoph Hellwig]

Hi Linus,

we're not talking about a driver here - we're talking about a new API
lifted from a driver to generic code because it's commonly useful.

It's also in entirely new files and not a modification of existing code,
and it's always been clear how it is.  Some of the code has been in
since Linux 4.5 with a properly clear copyright.

I really don't understand Doug's objection, and as said if they have
a weird problem with it we can simply move it to a separate module.

Re: CQ and RDMA READ/WRITE APIs

[Christoph Hellwig]

Hi Linus,

we're not talking about a driver here - we're talking about a new API
lifted from a driver to generic code because it's commonly useful.

It's also in entirely new files and not a modification of existing code,
and it's always been clear how it is.  Some of the code has been in
since Linux 4.5 with a properly clear copyright.

I really don't understand Doug's objection, and as said if they have
a weird problem with it we can simply move it to a separate module.

Re: Do not build vmstat_refresh if there is no procfs support

[kbuild test robot]

Hi,

[auto build test ERROR on next-20160511]
[cannot apply to v4.6-rc7 v4.6-rc6 v4.6-rc5 v4.6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Christoph-Lameter/Do-not-build-vmstat_refresh-if-there-is-no-procfs-support/20160511-233405
config: arm64-allnoconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

   mm/vmstat.c: In function 'vmstat_update':
>> mm/vmstat.c:1436:45: error: 'vmstat_wq' undeclared (first use in this 
>> function)
  queue_delayed_work_on(smp_processor_id(), vmstat_wq,
^
   mm/vmstat.c:1436:45: note: each undeclared identifier is reported only once 
for each function it appears in
   In file included from include/asm-generic/percpu.h:6:0,
from arch/arm64/include/asm/percpu.h:276,
from include/linux/percpu.h:12,
from include/linux/percpu-rwsem.h:6,
from include/linux/fs.h:30,
from mm/vmstat.c:12:
>> mm/vmstat.c:1437:19: error: 'vmstat_work' undeclared (first use in this 
>> function)
this_cpu_ptr(_work),
  ^
   include/linux/percpu-defs.h:206:47: note: in definition of macro 
'__verify_pcpu_ptr'
 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  ^
   include/linux/percpu-defs.h:239:27: note: in expansion of macro 'raw_cpu_ptr'
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
  ^
>> mm/vmstat.c:1437:5: note: in expansion of macro 'this_cpu_ptr'
this_cpu_ptr(_work),
^
   In file included from include/linux/fs.h:32:0,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'quiet_vmstat':
   mm/vmstat.c:1480:42: error: 'vmstat_work' undeclared (first use in this 
function)
 if (!delayed_work_pending(this_cpu_ptr(_work)))
 ^
   include/linux/workqueue.h:26:51: note: in definition of macro 
'work_data_bits'
#define work_data_bits(work) ((unsigned long *)(&(work)->data))
  ^
   include/linux/workqueue.h:271:2: note: in expansion of macro 'work_pending'
 work_pending(&(w)->work)
 ^
>> mm/vmstat.c:1480:7: note: in expansion of macro 'delayed_work_pending'
 if (!delayed_work_pending(this_cpu_ptr(_work)))
  ^
   include/linux/percpu-defs.h:228:2: note: in expansion of macro 
'__verify_pcpu_ptr'
 __verify_pcpu_ptr(ptr);  \
 ^
   include/linux/percpu-defs.h:239:27: note: in expansion of macro 'raw_cpu_ptr'
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
  ^
   mm/vmstat.c:1480:28: note: in expansion of macro 'this_cpu_ptr'
 if (!delayed_work_pending(this_cpu_ptr(_work)))
   ^
   In file included from include/asm-generic/percpu.h:6:0,
from arch/arm64/include/asm/percpu.h:276,
from include/linux/percpu.h:12,
from include/linux/percpu-rwsem.h:6,
from include/linux/fs.h:30,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'vmstat_shepherd':
   mm/vmstat.c:1512:38: error: 'vmstat_work' undeclared (first use in this 
function)
  struct delayed_work *dw = _cpu(vmstat_work, cpu);
 ^
   include/linux/percpu-defs.h:206:47: note: in definition of macro 
'__verify_pcpu_ptr'
 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  ^
   include/linux/percpu-defs.h:256:29: note: in expansion of macro 'per_cpu_ptr'
#define per_cpu(var, cpu) (*per_cpu_ptr(&(var), cpu))
^
>> mm/vmstat.c:1512:30: note: in expansion of macro 'per_cpu'
  struct delayed_work *dw = _cpu(vmstat_work, cpu);
 ^
   mm/vmstat.c:1515:32: error: 'vmstat_wq' undeclared (first use in this 
function)
queue_delayed_work_on(cpu, vmstat_wq, dw, 0);
   ^
   In file included from include/linux/fs.h:32:0,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'start_shepherd_timer':
   mm/vmstat.c:1528:37: error: 'vmstat_work' undeclared (first use in this 
function)
  INIT_DEFERRABLE_WORK(per_cpu_ptr(_work, cpu),
^
   include/linux/workqueue.h:216:16: note: in definition of macro '__INIT_WORK'
  __init_work((_work), _onstack);\
   ^
   

Re: Do not build vmstat_refresh if there is no procfs support

[kbuild test robot]

Hi,

[auto build test ERROR on next-20160511]
[cannot apply to v4.6-rc7 v4.6-rc6 v4.6-rc5 v4.6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Christoph-Lameter/Do-not-build-vmstat_refresh-if-there-is-no-procfs-support/20160511-233405
config: arm64-allnoconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

   mm/vmstat.c: In function 'vmstat_update':
>> mm/vmstat.c:1436:45: error: 'vmstat_wq' undeclared (first use in this 
>> function)
  queue_delayed_work_on(smp_processor_id(), vmstat_wq,
^
   mm/vmstat.c:1436:45: note: each undeclared identifier is reported only once 
for each function it appears in
   In file included from include/asm-generic/percpu.h:6:0,
from arch/arm64/include/asm/percpu.h:276,
from include/linux/percpu.h:12,
from include/linux/percpu-rwsem.h:6,
from include/linux/fs.h:30,
from mm/vmstat.c:12:
>> mm/vmstat.c:1437:19: error: 'vmstat_work' undeclared (first use in this 
>> function)
this_cpu_ptr(_work),
  ^
   include/linux/percpu-defs.h:206:47: note: in definition of macro 
'__verify_pcpu_ptr'
 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  ^
   include/linux/percpu-defs.h:239:27: note: in expansion of macro 'raw_cpu_ptr'
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
  ^
>> mm/vmstat.c:1437:5: note: in expansion of macro 'this_cpu_ptr'
this_cpu_ptr(_work),
^
   In file included from include/linux/fs.h:32:0,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'quiet_vmstat':
   mm/vmstat.c:1480:42: error: 'vmstat_work' undeclared (first use in this 
function)
 if (!delayed_work_pending(this_cpu_ptr(_work)))
 ^
   include/linux/workqueue.h:26:51: note: in definition of macro 
'work_data_bits'
#define work_data_bits(work) ((unsigned long *)(&(work)->data))
  ^
   include/linux/workqueue.h:271:2: note: in expansion of macro 'work_pending'
 work_pending(&(w)->work)
 ^
>> mm/vmstat.c:1480:7: note: in expansion of macro 'delayed_work_pending'
 if (!delayed_work_pending(this_cpu_ptr(_work)))
  ^
   include/linux/percpu-defs.h:228:2: note: in expansion of macro 
'__verify_pcpu_ptr'
 __verify_pcpu_ptr(ptr);  \
 ^
   include/linux/percpu-defs.h:239:27: note: in expansion of macro 'raw_cpu_ptr'
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
  ^
   mm/vmstat.c:1480:28: note: in expansion of macro 'this_cpu_ptr'
 if (!delayed_work_pending(this_cpu_ptr(_work)))
   ^
   In file included from include/asm-generic/percpu.h:6:0,
from arch/arm64/include/asm/percpu.h:276,
from include/linux/percpu.h:12,
from include/linux/percpu-rwsem.h:6,
from include/linux/fs.h:30,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'vmstat_shepherd':
   mm/vmstat.c:1512:38: error: 'vmstat_work' undeclared (first use in this 
function)
  struct delayed_work *dw = _cpu(vmstat_work, cpu);
 ^
   include/linux/percpu-defs.h:206:47: note: in definition of macro 
'__verify_pcpu_ptr'
 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  ^
   include/linux/percpu-defs.h:256:29: note: in expansion of macro 'per_cpu_ptr'
#define per_cpu(var, cpu) (*per_cpu_ptr(&(var), cpu))
^
>> mm/vmstat.c:1512:30: note: in expansion of macro 'per_cpu'
  struct delayed_work *dw = _cpu(vmstat_work, cpu);
 ^
   mm/vmstat.c:1515:32: error: 'vmstat_wq' undeclared (first use in this 
function)
queue_delayed_work_on(cpu, vmstat_wq, dw, 0);
   ^
   In file included from include/linux/fs.h:32:0,
from mm/vmstat.c:12:
   mm/vmstat.c: In function 'start_shepherd_timer':
   mm/vmstat.c:1528:37: error: 'vmstat_work' undeclared (first use in this 
function)
  INIT_DEFERRABLE_WORK(per_cpu_ptr(_work, cpu),
^
   include/linux/workqueue.h:216:16: note: in definition of macro '__INIT_WORK'
  __init_work((_work), _onstack);\
   ^
   

Re: Question About Functions "__free_pages_check" and "check_new_page" in page_alloc.c

[Vlastimil Babka]

On 05/17/2016 03:06 AM, Wang Xiaoqiang wrote:
>>yes it would. Why that would matter. The checks should be in an order
>>which could give us a more specific reason with later checks. bad_page()
> 
> I see, you mean the later "bad_reason" is the superset of the previous one.

Not exactly. It's not possible to sort all the reasons like that. But as
Michal said, bad_page() will print all the relevant info so you can
reconstruct all reasons from it. The bad_reason text is mostly a hint
what to check first.

>>will then print more detailed information.
>>--
>>Michal Hocko
>>SUSE Labs
> 
> thank you, Michal.
> 
> 
>  
> 

Re: Question About Functions "__free_pages_check" and "check_new_page" in page_alloc.c

[Vlastimil Babka]

On 05/17/2016 03:06 AM, Wang Xiaoqiang wrote:
>>yes it would. Why that would matter. The checks should be in an order
>>which could give us a more specific reason with later checks. bad_page()
> 
> I see, you mean the later "bad_reason" is the superset of the previous one.

Not exactly. It's not possible to sort all the reasons like that. But as
Michal said, bad_page() will print all the relevant info so you can
reconstruct all reasons from it. The bad_reason text is mostly a hint
what to check first.

>>will then print more detailed information.
>>--
>>Michal Hocko
>>SUSE Labs
> 
> thank you, Michal.
> 
> 
>  
> 

[PATCH 08/11] dt/bindings: Correct clk binding example for PIC32 serial.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt 
b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
index 65b38bf..7a34345 100644
--- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
@@ -20,7 +20,7 @@ Example:
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
-   clocks = <>;
+   clocks = < PB2CLK>;
pinctrl-names = "default";
pinctrl-0 = <_uart1
_uart1_cts
-- 
1.8.3.1

[PATCH 09/11] dt/bindings: Correct clk binding example for PIC32 DMT.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt 
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
index 852f694..49485f8 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
@@ -8,12 +8,12 @@ Required properties:
 - compatible: must be "microchip,pic32mzda-dmt".
 - reg: physical base address of the controller and length of memory mapped
   region.
-- clocks: phandle of parent clock (should be ).
+- clocks: phandle of source clk. Should be < PB7CLK>.
 
 Example:
 
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
-   clocks = <>;
+   clocks = < PB7CLK>;
};
-- 
1.8.3.1

[PATCH 08/11] dt/bindings: Correct clk binding example for PIC32 serial.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt 
b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
index 65b38bf..7a34345 100644
--- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
@@ -20,7 +20,7 @@ Example:
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
-   clocks = <>;
+   clocks = < PB2CLK>;
pinctrl-names = "default";
pinctrl-0 = <_uart1
_uart1_cts
-- 
1.8.3.1

[PATCH 09/11] dt/bindings: Correct clk binding example for PIC32 DMT.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt 
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
index 852f694..49485f8 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
@@ -8,12 +8,12 @@ Required properties:
 - compatible: must be "microchip,pic32mzda-dmt".
 - reg: physical base address of the controller and length of memory mapped
   region.
-- clocks: phandle of parent clock (should be ).
+- clocks: phandle of source clk. Should be < PB7CLK>.
 
 Example:
 
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
-   clocks = <>;
+   clocks = < PB7CLK>;
};
-- 
1.8.3.1

[PATCH v8 01/10] clk: fix initial state of critical clock's parents

[Erin Lo]

From: James Liao 

This patch fixed wrong state of parent clocks if they are registered
after critical clocks.

Signed-off-by: James Liao 
---
 drivers/clk/clk.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ce39add..bf80e39 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
struct clk_core *parent = __clk_init_parent(orphan);
 
-   if (parent)
+   if (parent) {
clk_core_reparent(orphan, parent);
+
+   if (orphan->prepare_count)
+   clk_core_prepare(parent);
+
+   if (orphan->enable_count)
+   clk_core_enable(parent);
+   }
}
 
/*
-- 
1.9.1

[PATCH v8 07/10] reset: mediatek: Add MT2701 reset controller dt-binding file

[Erin Lo]

From: Shunli Wang 

Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Philipp Zabel 
---
 include/dt-bindings/reset/mt2701-resets.h | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 include/dt-bindings/reset/mt2701-resets.h

diff --git a/include/dt-bindings/reset/mt2701-resets.h 
b/include/dt-bindings/reset/mt2701-resets.h
new file mode 100644
index 000..aaf0305
--- /dev/null
+++ b/include/dt-bindings/reset/mt2701-resets.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015 MediaTek, Shunli Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
+#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
+
+/* INFRACFG resets */
+#define MT2701_INFRA_EMI_REG_RST   0
+#define MT2701_INFRA_DRAMC0_A0_RST 1
+#define MT2701_INFRA_FHCTL_RST 2
+#define MT2701_INFRA_APCIRQ_EINT_RST   3
+#define MT2701_INFRA_APXGPT_RST4
+#define MT2701_INFRA_SCPSYS_RST5
+#define MT2701_INFRA_KP_RST6
+#define MT2701_INFRA_PMIC_WRAP_RST 7
+#define MT2701_INFRA_MIPI_RST  8
+#define MT2701_INFRA_IRRX_RST  9
+#define MT2701_INFRA_CEC_RST   10
+#define MT2701_INFRA_EMI_RST   32
+#define MT2701_INFRA_DRAMC0_RST34
+#define MT2701_INFRA_TRNG_RST  37
+#define MT2701_INFRA_SYSIRQ_RST38
+
+/*  PERICFG resets */
+#define MT2701_PERI_UART0_SW_RST   0
+#define MT2701_PERI_UART1_SW_RST   1
+#define MT2701_PERI_UART2_SW_RST   2
+#define MT2701_PERI_UART3_SW_RST   3
+#define MT2701_PERI_GCPU_SW_RST5
+#define MT2701_PERI_BTIF_SW_RST6
+#define MT2701_PERI_PWM_SW_RST 8
+#define MT2701_PERI_AUXADC_SW_RST  10
+#define MT2701_PERI_DMA_SW_RST 11
+#define MT2701_PERI_NFI_SW_RST 14
+#define MT2701_PERI_NLI_SW_RST 15
+#define MT2701_PERI_THERM_SW_RST   16
+#define MT2701_PERI_MSDC2_SW_RST   17
+#define MT2701_PERI_MSDC0_SW_RST   19
+#define MT2701_PERI_MSDC1_SW_RST   20
+#define MT2701_PERI_I2C0_SW_RST22
+#define MT2701_PERI_I2C1_SW_RST23
+#define MT2701_PERI_I2C2_SW_RST24
+#define MT2701_PERI_I2C3_SW_RST25
+#define MT2701_PERI_USB_SW_RST 28
+#define MT2701_PERI_ETH_SW_RST 29
+#define MT2701_PERI_SPI0_SW_RST33
+
+/* TOPRGU resets */
+#define MT2701_TOPRGU_INFRA_RST0
+#define MT2701_TOPRGU_MM_RST   1
+#define MT2701_TOPRGU_MFG_RST  2
+#define MT2701_TOPRGU_ETHDMA_RST   3
+#define MT2701_TOPRGU_VDEC_RST 4
+#define MT2701_TOPRGU_VENC_IMG_RST 5
+#define MT2701_TOPRGU_DDRPHY_RST   6
+#define MT2701_TOPRGU_MD_RST   7
+#define MT2701_TOPRGU_INFRA_AO_RST 8
+#define MT2701_TOPRGU_CONN_RST 9
+#define MT2701_TOPRGU_APMIXED_RST  10
+#define MT2701_TOPRGU_HIFSYS_RST   11
+#define MT2701_TOPRGU_CONN_MCU_RST 12
+#define MT2701_TOPRGU_BDP_DISP_RST 13
+
+/* HIFSYS resets */
+#define MT2701_HIFSYS_UHOST0_RST   3
+#define MT2701_HIFSYS_UHOST1_RST   4
+#define MT2701_HIFSYS_UPHY0_RST21
+#define MT2701_HIFSYS_UPHY1_RST22
+#define MT2701_HIFSYS_PCIE0_RST24
+#define MT2701_HIFSYS_PCIE1_RST25
+#define MT2701_HIFSYS_PCIE2_RST26
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
-- 
1.9.1

[PATCH v8 01/10] clk: fix initial state of critical clock's parents

[Erin Lo]

From: James Liao 

This patch fixed wrong state of parent clocks if they are registered
after critical clocks.

Signed-off-by: James Liao 
---
 drivers/clk/clk.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ce39add..bf80e39 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
struct clk_core *parent = __clk_init_parent(orphan);
 
-   if (parent)
+   if (parent) {
clk_core_reparent(orphan, parent);
+
+   if (orphan->prepare_count)
+   clk_core_prepare(parent);
+
+   if (orphan->enable_count)
+   clk_core_enable(parent);
+   }
}
 
/*
-- 
1.9.1

[PATCH v8 07/10] reset: mediatek: Add MT2701 reset controller dt-binding file

[Erin Lo]

From: Shunli Wang 

Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Philipp Zabel 
---
 include/dt-bindings/reset/mt2701-resets.h | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 include/dt-bindings/reset/mt2701-resets.h

diff --git a/include/dt-bindings/reset/mt2701-resets.h 
b/include/dt-bindings/reset/mt2701-resets.h
new file mode 100644
index 000..aaf0305
--- /dev/null
+++ b/include/dt-bindings/reset/mt2701-resets.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015 MediaTek, Shunli Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
+#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
+
+/* INFRACFG resets */
+#define MT2701_INFRA_EMI_REG_RST   0
+#define MT2701_INFRA_DRAMC0_A0_RST 1
+#define MT2701_INFRA_FHCTL_RST 2
+#define MT2701_INFRA_APCIRQ_EINT_RST   3
+#define MT2701_INFRA_APXGPT_RST4
+#define MT2701_INFRA_SCPSYS_RST5
+#define MT2701_INFRA_KP_RST6
+#define MT2701_INFRA_PMIC_WRAP_RST 7
+#define MT2701_INFRA_MIPI_RST  8
+#define MT2701_INFRA_IRRX_RST  9
+#define MT2701_INFRA_CEC_RST   10
+#define MT2701_INFRA_EMI_RST   32
+#define MT2701_INFRA_DRAMC0_RST34
+#define MT2701_INFRA_TRNG_RST  37
+#define MT2701_INFRA_SYSIRQ_RST38
+
+/*  PERICFG resets */
+#define MT2701_PERI_UART0_SW_RST   0
+#define MT2701_PERI_UART1_SW_RST   1
+#define MT2701_PERI_UART2_SW_RST   2
+#define MT2701_PERI_UART3_SW_RST   3
+#define MT2701_PERI_GCPU_SW_RST5
+#define MT2701_PERI_BTIF_SW_RST6
+#define MT2701_PERI_PWM_SW_RST 8
+#define MT2701_PERI_AUXADC_SW_RST  10
+#define MT2701_PERI_DMA_SW_RST 11
+#define MT2701_PERI_NFI_SW_RST 14
+#define MT2701_PERI_NLI_SW_RST 15
+#define MT2701_PERI_THERM_SW_RST   16
+#define MT2701_PERI_MSDC2_SW_RST   17
+#define MT2701_PERI_MSDC0_SW_RST   19
+#define MT2701_PERI_MSDC1_SW_RST   20
+#define MT2701_PERI_I2C0_SW_RST22
+#define MT2701_PERI_I2C1_SW_RST23
+#define MT2701_PERI_I2C2_SW_RST24
+#define MT2701_PERI_I2C3_SW_RST25
+#define MT2701_PERI_USB_SW_RST 28
+#define MT2701_PERI_ETH_SW_RST 29
+#define MT2701_PERI_SPI0_SW_RST33
+
+/* TOPRGU resets */
+#define MT2701_TOPRGU_INFRA_RST0
+#define MT2701_TOPRGU_MM_RST   1
+#define MT2701_TOPRGU_MFG_RST  2
+#define MT2701_TOPRGU_ETHDMA_RST   3
+#define MT2701_TOPRGU_VDEC_RST 4
+#define MT2701_TOPRGU_VENC_IMG_RST 5
+#define MT2701_TOPRGU_DDRPHY_RST   6
+#define MT2701_TOPRGU_MD_RST   7
+#define MT2701_TOPRGU_INFRA_AO_RST 8
+#define MT2701_TOPRGU_CONN_RST 9
+#define MT2701_TOPRGU_APMIXED_RST  10
+#define MT2701_TOPRGU_HIFSYS_RST   11
+#define MT2701_TOPRGU_CONN_MCU_RST 12
+#define MT2701_TOPRGU_BDP_DISP_RST 13
+
+/* HIFSYS resets */
+#define MT2701_HIFSYS_UHOST0_RST   3
+#define MT2701_HIFSYS_UHOST1_RST   4
+#define MT2701_HIFSYS_UPHY0_RST21
+#define MT2701_HIFSYS_UPHY1_RST22
+#define MT2701_HIFSYS_PCIE0_RST24
+#define MT2701_HIFSYS_PCIE1_RST25
+#define MT2701_HIFSYS_PCIE2_RST26
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
-- 
1.9.1

[PATCH v8 03/10] clk: mediatek: Refine the makefile to support multiple clock drivers

[Erin Lo]

From: James Liao 

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Reviewed-by: Matthias Brugger 
---
 drivers/clk/Kconfig   |  1 +
 drivers/clk/mediatek/Kconfig  | 23 +++
 drivers/clk/mediatek/Makefile |  6 +++---
 3 files changed, 27 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/mediatek/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2dd371d..34c6aa9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -205,6 +205,7 @@ config COMMON_CLK_OXNAS
 
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
+source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
 source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
new file mode 100644
index 000..dc224e6
--- /dev/null
+++ b/drivers/clk/mediatek/Kconfig
@@ -0,0 +1,23 @@
+#
+# MediaTek SoC drivers
+#
+config COMMON_CLK_MEDIATEK
+   bool
+   ---help---
+ Mediatek SoCs' clock support.
+
+config COMMON_CLK_MT8135
+   bool "Clock driver for Mediatek MT8135"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT8135 clocks.
+
+config COMMON_CLK_MT8173
+   bool "Clock driver for Mediatek MT8173"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT8173 clocks.
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 95fdfac..32e7222 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,4 @@
-obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
-obj-y += clk-mt8135.o
-obj-y += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
-- 
1.9.1

[PATCH v8 03/10] clk: mediatek: Refine the makefile to support multiple clock drivers

[Erin Lo]

From: James Liao 

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Reviewed-by: Matthias Brugger 
---
 drivers/clk/Kconfig   |  1 +
 drivers/clk/mediatek/Kconfig  | 23 +++
 drivers/clk/mediatek/Makefile |  6 +++---
 3 files changed, 27 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/mediatek/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2dd371d..34c6aa9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -205,6 +205,7 @@ config COMMON_CLK_OXNAS
 
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
+source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
 source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
new file mode 100644
index 000..dc224e6
--- /dev/null
+++ b/drivers/clk/mediatek/Kconfig
@@ -0,0 +1,23 @@
+#
+# MediaTek SoC drivers
+#
+config COMMON_CLK_MEDIATEK
+   bool
+   ---help---
+ Mediatek SoCs' clock support.
+
+config COMMON_CLK_MT8135
+   bool "Clock driver for Mediatek MT8135"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT8135 clocks.
+
+config COMMON_CLK_MT8173
+   bool "Clock driver for Mediatek MT8173"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT8173 clocks.
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 95fdfac..32e7222 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,4 @@
-obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
-obj-y += clk-mt8135.o
-obj-y += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
-- 
1.9.1

[PATCH 11/11] dt/bindings: Correct clk binding example for PIC32 gpio.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt 
b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
index ef37528..dd031fc 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -33,7 +33,7 @@ gpio0: gpio0@1f86 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
-   clocks = <>;
+   clocks = < PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <_pinctrl 0 0 16>;
 };
-- 
1.8.3.1

[PATCH 10/11] dt/bindings: Correct clk binding example for PIC32 WDT.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
index d140103..f03a29a 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
@@ -7,12 +7,12 @@ Required properties:
 - compatible: must be "microchip,pic32mzda-wdt".
 - reg: physical base address of the controller and length of memory mapped
   region.
-- clocks: phandle of source clk. should be <> clk.
+- clocks: phandle of source clk. Should be < LPRCCLK>.
 
 Example:
 
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
-   clocks = <>;
+   clocks = < LPRCCLK>;
};
-- 
1.8.3.1

[PATCH 11/11] dt/bindings: Correct clk binding example for PIC32 gpio.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt 
b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
index ef37528..dd031fc 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -33,7 +33,7 @@ gpio0: gpio0@1f86 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
-   clocks = <>;
+   clocks = < PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <_pinctrl 0 0 16>;
 };
-- 
1.8.3.1

[PATCH 10/11] dt/bindings: Correct clk binding example for PIC32 WDT.

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
index d140103..f03a29a 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
@@ -7,12 +7,12 @@ Required properties:
 - compatible: must be "microchip,pic32mzda-wdt".
 - reg: physical base address of the controller and length of memory mapped
   region.
-- clocks: phandle of source clk. should be <> clk.
+- clocks: phandle of source clk. Should be < LPRCCLK>.
 
 Example:
 
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
-   clocks = <>;
+   clocks = < LPRCCLK>;
};
-- 
1.8.3.1

[PATCH v8 06/10] clk: mediatek: Add MT2701 clock support

[Erin Lo]

From: Shunli Wang 

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
---
 drivers/clk/mediatek/Kconfig   |   50 ++
 drivers/clk/mediatek/Makefile  |7 +
 drivers/clk/mediatek/clk-gate.c|   52 ++
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   79 +++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 +++
 drivers/clk/mediatek/clk-mt2701.c  | 1033 
 drivers/clk/mediatek/clk-mtk.c |   40 ++
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |1 +
 14 files changed, 1833 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..5aa6204 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,56 @@ config COMMON_CLK_MEDIATEK
---help---
  Mediatek SoCs' clock support.
 
+config COMMON_CLK_MT2701
+   bool "Clock driver for Mediatek MT2701"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT2701 basic clocks.
+
+config COMMON_CLK_MT2701_MMSYS
+   bool "Clock driver for Mediatek MT2701 mmsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 mmsys clocks.
+
+config COMMON_CLK_MT2701_IMGSYS
+   bool "Clock driver for Mediatek MT2701 imgsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 imgsys clocks.
+
+config COMMON_CLK_MT2701_VDECSYS
+   bool "Clock driver for Mediatek MT2701 vdecsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 vdecsys clocks.
+
+config COMMON_CLK_MT2701_HIFSYS
+   bool "Clock driver for Mediatek MT2701 hifsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 hifsys clocks.
+
+config COMMON_CLK_MT2701_ETHSYS
+   bool "Clock driver for Mediatek MT2701 ethsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 ethsys clocks.
+
+config COMMON_CLK_MT2701_BDPSYS
+   bool "Clock driver for Mediatek MT2701 bdpsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 bdpsys clocks.
+
 config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..19ae7ef 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,11 @@
 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index d8787bf..934bf0e 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
 }
 
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = 

[PATCH v8 06/10] clk: mediatek: Add MT2701 clock support

[Erin Lo]

From: Shunli Wang 

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
---
 drivers/clk/mediatek/Kconfig   |   50 ++
 drivers/clk/mediatek/Makefile  |7 +
 drivers/clk/mediatek/clk-gate.c|   52 ++
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   79 +++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 +++
 drivers/clk/mediatek/clk-mt2701.c  | 1033 
 drivers/clk/mediatek/clk-mtk.c |   40 ++
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |1 +
 14 files changed, 1833 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..5aa6204 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,56 @@ config COMMON_CLK_MEDIATEK
---help---
  Mediatek SoCs' clock support.
 
+config COMMON_CLK_MT2701
+   bool "Clock driver for Mediatek MT2701"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT2701 basic clocks.
+
+config COMMON_CLK_MT2701_MMSYS
+   bool "Clock driver for Mediatek MT2701 mmsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 mmsys clocks.
+
+config COMMON_CLK_MT2701_IMGSYS
+   bool "Clock driver for Mediatek MT2701 imgsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 imgsys clocks.
+
+config COMMON_CLK_MT2701_VDECSYS
+   bool "Clock driver for Mediatek MT2701 vdecsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 vdecsys clocks.
+
+config COMMON_CLK_MT2701_HIFSYS
+   bool "Clock driver for Mediatek MT2701 hifsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 hifsys clocks.
+
+config COMMON_CLK_MT2701_ETHSYS
+   bool "Clock driver for Mediatek MT2701 ethsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 ethsys clocks.
+
+config COMMON_CLK_MT2701_BDPSYS
+   bool "Clock driver for Mediatek MT2701 bdpsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 bdpsys clocks.
+
 config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..19ae7ef 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,11 @@
 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index d8787bf..934bf0e 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
 }
 
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap, 

[PATCH v8 05/10] clk: mediatek: Add dt-bindings for MT2701 clocks

[Erin Lo]

From: Shunli Wang 

Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Reviewed-by: Matthias Brugger 
---
 include/dt-bindings/clock/mt2701-clk.h | 486 +
 1 file changed, 486 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt2701-clk.h

diff --git a/include/dt-bindings/clock/mt2701-clk.h 
b/include/dt-bindings/clock/mt2701-clk.h
new file mode 100644
index 000..2062c67
--- /dev/null
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2701_H
+#define _DT_BINDINGS_CLK_MT2701_H
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL 1
+#define CLK_TOP_SYSPLL_D2  2
+#define CLK_TOP_SYSPLL_D3  3
+#define CLK_TOP_SYSPLL_D5  4
+#define CLK_TOP_SYSPLL_D7  5
+#define CLK_TOP_SYSPLL1_D2 6
+#define CLK_TOP_SYSPLL1_D4 7
+#define CLK_TOP_SYSPLL1_D8 8
+#define CLK_TOP_SYSPLL1_D169
+#define CLK_TOP_SYSPLL2_D2 10
+#define CLK_TOP_SYSPLL2_D4 11
+#define CLK_TOP_SYSPLL2_D8 12
+#define CLK_TOP_SYSPLL3_D2 13
+#define CLK_TOP_SYSPLL3_D4 14
+#define CLK_TOP_SYSPLL4_D2 15
+#define CLK_TOP_SYSPLL4_D4 16
+#define CLK_TOP_UNIVPLL17
+#define CLK_TOP_UNIVPLL_D2 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL_D5 20
+#define CLK_TOP_UNIVPLL_D7 21
+#define CLK_TOP_UNIVPLL_D2622
+#define CLK_TOP_UNIVPLL_D5223
+#define CLK_TOP_UNIVPLL_D108   24
+#define CLK_TOP_USB_PHY48M 25
+#define CLK_TOP_UNIVPLL1_D226
+#define CLK_TOP_UNIVPLL1_D427
+#define CLK_TOP_UNIVPLL1_D828
+#define CLK_TOP_UNIVPLL2_D229
+#define CLK_TOP_UNIVPLL2_D430
+#define CLK_TOP_UNIVPLL2_D831
+#define CLK_TOP_UNIVPLL2_D16   32
+#define CLK_TOP_UNIVPLL2_D32   33
+#define CLK_TOP_UNIVPLL3_D234
+#define CLK_TOP_UNIVPLL3_D435
+#define CLK_TOP_UNIVPLL3_D836
+#define CLK_TOP_MSDCPLL37
+#define CLK_TOP_MSDCPLL_D2 38
+#define CLK_TOP_MSDCPLL_D4 39
+#define CLK_TOP_MSDCPLL_D8 40
+#define CLK_TOP_MMPLL  41
+#define CLK_TOP_MMPLL_D2   42
+#define CLK_TOP_DMPLL  43
+#define CLK_TOP_DMPLL_D2   44
+#define CLK_TOP_DMPLL_D4   45
+#define CLK_TOP_DMPLL_X2   46
+#define CLK_TOP_TVDPLL 47
+#define CLK_TOP_TVDPLL_D2  48
+#define CLK_TOP_TVDPLL_D4  49
+#define CLK_TOP_TVD2PLL50
+#define CLK_TOP_TVD2PLL_D2 51
+#define CLK_TOP_HADDS2PLL_98M  52
+#define CLK_TOP_HADDS2PLL_294M 53
+#define CLK_TOP_HADDS2_FB  54
+#define CLK_TOP_MIPIPLL_D2 55
+#define CLK_TOP_MIPIPLL_D4 56
+#define CLK_TOP_HDMIPLL57
+#define CLK_TOP_HDMIPLL_D2 58
+#define CLK_TOP_HDMIPLL_D3 59
+#define CLK_TOP_HDMI_SCL_RX60
+#define CLK_TOP_HDMI_0_PIX340M 61
+#define CLK_TOP_HDMI_0_DEEP340M62
+#define CLK_TOP_HDMI_0_PLL340M 63
+#define CLK_TOP_AUD1PLL_98M64
+#define CLK_TOP_AUD2PLL_90M65
+#define CLK_TOP_AUDPLL 66
+#define CLK_TOP_AUDPLL_D4  67
+#define CLK_TOP_AUDPLL_D8  68
+#define CLK_TOP_AUDPLL_D16 69
+#define CLK_TOP_AUDPLL_D24 70
+#define 

[PATCH v8 08/10] reset: mediatek: Add MT2701 reset driver

[Erin Lo]

From: Shunli Wang 

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Philipp Zabel 
---
 drivers/clk/mediatek/clk-mt2701-hif.c | 2 ++
 drivers/clk/mediatek/clk-mt2701.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c 
b/drivers/clk/mediatek/clk-mt2701-hif.c
index 3f6cea2..28014bf 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -55,6 +55,8 @@ static void mtk_hifsys_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 1, 0x34);
 }
 
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
diff --git a/drivers/clk/mediatek/clk-mt2701.c 
b/drivers/clk/mediatek/clk-mt2701.c
index 08a2954..b3cde20 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -791,6 +791,8 @@ static void mtk_infrasys_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 2, 0x30);
 }
 
 static const struct mtk_gate_regs peri0_cg_regs = {
@@ -911,6 +913,8 @@ static void mtk_pericfg_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 2, 0x0);
 }
 
 #define MT8590_PLL_FMAX(2000 * MHZ)
-- 
1.9.1

[PATCH v8 09/10] arm: dts: mt2701: Add clock controller device nodes

[Erin Lo]

From: James Liao 

Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
bdpsys. This patch also add two oscillators that provide clocks for
MT2701.

Signed-off-by: James Liao 
---
 arch/arm/boot/dts/mt2701.dtsi | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 8343768..171d4da 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -12,6 +12,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include "skeleton64.dtsi"
@@ -76,6 +77,20 @@
#clock-cells = <0>;
};
 
+   clk26m: oscillator@0 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2600>;
+   clock-output-names = "clk26m";
+   };
+
+   rtc32k: oscillator@1 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32000>;
+   clock-output-names = "rtc32k";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <>;
@@ -85,6 +100,26 @@
 ;
};
 
+   topckgen: syscon@1000 {
+   compatible = "mediatek,mt2701-topckgen", "syscon";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infracfg: syscon@10001000 {
+   compatible = "mediatek,mt2701-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   pericfg: syscon@10003000 {
+   compatible = "mediatek,mt2701-pericfg", "syscon";
+   reg = <0 0x10003000 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
@@ -109,6 +144,13 @@
reg = <0 0x10200100 0 0x1c>;
};
 
+   apmixedsys: syscon@10209000 {
+   compatible = "mediatek,mt2701-apmixedsys", "syscon";
+   reg = <0 0x10209000 0 0x1000>;
+   mediatek,hdmi-ibias = <0xa>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
-- 
1.9.1

[PATCH v8 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT2701

[Erin Lo]

From: James Liao 

This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.

Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Rob Herring 
---
 .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  3 ++-
 .../bindings/arm/mediatek/mediatek,bdpsys.txt  | 22 
 .../bindings/arm/mediatek/mediatek,ethsys.txt  | 22 
 .../bindings/arm/mediatek/mediatek,hifsys.txt  | 24 ++
 .../bindings/arm/mediatek/mediatek,imgsys.txt  |  3 ++-
 .../bindings/arm/mediatek/mediatek,infracfg.txt|  3 ++-
 .../bindings/arm/mediatek/mediatek,mmsys.txt   |  3 ++-
 .../bindings/arm/mediatek/mediatek,pericfg.txt |  3 ++-
 .../bindings/arm/mediatek/mediatek,topckgen.txt|  3 ++-
 .../bindings/arm/mediatek/mediatek,vdecsys.txt |  3 ++-
 10 files changed, 82 insertions(+), 7 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt

diff --git 
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 936166f..cb0054a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the 
system.
 
 Required Properties:
 
-- compatible: Should be:
+- compatible: Should be one of:
+   - "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
new file mode 100644
index 000..4137196
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -0,0 +1,22 @@
+Mediatek bdpsys controller
+
+
+The Mediatek bdpsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-bdpsys", "syscon"
+- #clock-cells: Must be 1
+
+The bdpsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+bdpsys: clock-controller@1c00 {
+   compatible = "mediatek,mt2701-bdpsys", "syscon";
+   reg = <0 0x1c00 0 0x1000>;
+   #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
new file mode 100644
index 000..768f3a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -0,0 +1,22 @@
+Mediatek ethsys controller
+
+
+The Mediatek ethsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-ethsys", "syscon"
+- #clock-cells: Must be 1
+
+The ethsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+ethsys: clock-controller@1b00 {
+   compatible = "mediatek,mt2701-ethsys", "syscon";
+   reg = <0 0x1b00 0 0x1000>;
+   #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
new file mode 100644
index 000..beed7b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
@@ -0,0 +1,24 @@
+Mediatek hifsys controller
+
+
+The Mediatek hifsys controller provides various clocks and reset
+outputs to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-hifsys", "syscon"
+- #clock-cells: Must be 1
+
+The hifsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+hifsys: clock-controller@1a00 {
+   compatible = "mediatek,mt2701-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index b1f2ce1..f6a9166 100644
--- 

[PATCH v8 10/10] arm: dts: mt2701: Use real clock for UARTs

[Erin Lo]

We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.

Signed-off-by: Erin Lo 
---
 arch/arm/boot/dts/mt2701.dtsi | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 171d4da..e79e88f 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -71,12 +71,6 @@
#clock-cells = <0>;
};
 
-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -167,7 +161,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART0_SEL>, < 
CLK_PERI_UART0>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -176,7 +171,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART1_SEL>, < 
CLK_PERI_UART1>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -185,7 +181,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART2_SEL>, < 
CLK_PERI_UART2>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -194,7 +191,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART3_SEL>, < 
CLK_PERI_UART3>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 };
-- 
1.9.1

[PATCH v8 05/10] clk: mediatek: Add dt-bindings for MT2701 clocks

[Erin Lo]

From: Shunli Wang 

Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Reviewed-by: Matthias Brugger 
---
 include/dt-bindings/clock/mt2701-clk.h | 486 +
 1 file changed, 486 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt2701-clk.h

diff --git a/include/dt-bindings/clock/mt2701-clk.h 
b/include/dt-bindings/clock/mt2701-clk.h
new file mode 100644
index 000..2062c67
--- /dev/null
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2701_H
+#define _DT_BINDINGS_CLK_MT2701_H
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL 1
+#define CLK_TOP_SYSPLL_D2  2
+#define CLK_TOP_SYSPLL_D3  3
+#define CLK_TOP_SYSPLL_D5  4
+#define CLK_TOP_SYSPLL_D7  5
+#define CLK_TOP_SYSPLL1_D2 6
+#define CLK_TOP_SYSPLL1_D4 7
+#define CLK_TOP_SYSPLL1_D8 8
+#define CLK_TOP_SYSPLL1_D169
+#define CLK_TOP_SYSPLL2_D2 10
+#define CLK_TOP_SYSPLL2_D4 11
+#define CLK_TOP_SYSPLL2_D8 12
+#define CLK_TOP_SYSPLL3_D2 13
+#define CLK_TOP_SYSPLL3_D4 14
+#define CLK_TOP_SYSPLL4_D2 15
+#define CLK_TOP_SYSPLL4_D4 16
+#define CLK_TOP_UNIVPLL17
+#define CLK_TOP_UNIVPLL_D2 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL_D5 20
+#define CLK_TOP_UNIVPLL_D7 21
+#define CLK_TOP_UNIVPLL_D2622
+#define CLK_TOP_UNIVPLL_D5223
+#define CLK_TOP_UNIVPLL_D108   24
+#define CLK_TOP_USB_PHY48M 25
+#define CLK_TOP_UNIVPLL1_D226
+#define CLK_TOP_UNIVPLL1_D427
+#define CLK_TOP_UNIVPLL1_D828
+#define CLK_TOP_UNIVPLL2_D229
+#define CLK_TOP_UNIVPLL2_D430
+#define CLK_TOP_UNIVPLL2_D831
+#define CLK_TOP_UNIVPLL2_D16   32
+#define CLK_TOP_UNIVPLL2_D32   33
+#define CLK_TOP_UNIVPLL3_D234
+#define CLK_TOP_UNIVPLL3_D435
+#define CLK_TOP_UNIVPLL3_D836
+#define CLK_TOP_MSDCPLL37
+#define CLK_TOP_MSDCPLL_D2 38
+#define CLK_TOP_MSDCPLL_D4 39
+#define CLK_TOP_MSDCPLL_D8 40
+#define CLK_TOP_MMPLL  41
+#define CLK_TOP_MMPLL_D2   42
+#define CLK_TOP_DMPLL  43
+#define CLK_TOP_DMPLL_D2   44
+#define CLK_TOP_DMPLL_D4   45
+#define CLK_TOP_DMPLL_X2   46
+#define CLK_TOP_TVDPLL 47
+#define CLK_TOP_TVDPLL_D2  48
+#define CLK_TOP_TVDPLL_D4  49
+#define CLK_TOP_TVD2PLL50
+#define CLK_TOP_TVD2PLL_D2 51
+#define CLK_TOP_HADDS2PLL_98M  52
+#define CLK_TOP_HADDS2PLL_294M 53
+#define CLK_TOP_HADDS2_FB  54
+#define CLK_TOP_MIPIPLL_D2 55
+#define CLK_TOP_MIPIPLL_D4 56
+#define CLK_TOP_HDMIPLL57
+#define CLK_TOP_HDMIPLL_D2 58
+#define CLK_TOP_HDMIPLL_D3 59
+#define CLK_TOP_HDMI_SCL_RX60
+#define CLK_TOP_HDMI_0_PIX340M 61
+#define CLK_TOP_HDMI_0_DEEP340M62
+#define CLK_TOP_HDMI_0_PLL340M 63
+#define CLK_TOP_AUD1PLL_98M64
+#define CLK_TOP_AUD2PLL_90M65
+#define CLK_TOP_AUDPLL 66
+#define CLK_TOP_AUDPLL_D4  67
+#define CLK_TOP_AUDPLL_D8  68
+#define CLK_TOP_AUDPLL_D16 69
+#define CLK_TOP_AUDPLL_D24 70
+#define CLK_TOP_ETHPLL_500M71
+#define CLK_TOP_VDECPLL72
+#define CLK_TOP_VENCPLL 

[PATCH v8 08/10] reset: mediatek: Add MT2701 reset driver

[Erin Lo]

From: Shunli Wang 

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Philipp Zabel 
---
 drivers/clk/mediatek/clk-mt2701-hif.c | 2 ++
 drivers/clk/mediatek/clk-mt2701.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c 
b/drivers/clk/mediatek/clk-mt2701-hif.c
index 3f6cea2..28014bf 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -55,6 +55,8 @@ static void mtk_hifsys_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 1, 0x34);
 }
 
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
diff --git a/drivers/clk/mediatek/clk-mt2701.c 
b/drivers/clk/mediatek/clk-mt2701.c
index 08a2954..b3cde20 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -791,6 +791,8 @@ static void mtk_infrasys_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 2, 0x30);
 }
 
 static const struct mtk_gate_regs peri0_cg_regs = {
@@ -911,6 +913,8 @@ static void mtk_pericfg_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+   mtk_register_reset_controller(node, 2, 0x0);
 }
 
 #define MT8590_PLL_FMAX(2000 * MHZ)
-- 
1.9.1

[PATCH v8 09/10] arm: dts: mt2701: Add clock controller device nodes

[Erin Lo]

From: James Liao 

Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
bdpsys. This patch also add two oscillators that provide clocks for
MT2701.

Signed-off-by: James Liao 
---
 arch/arm/boot/dts/mt2701.dtsi | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 8343768..171d4da 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -12,6 +12,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include "skeleton64.dtsi"
@@ -76,6 +77,20 @@
#clock-cells = <0>;
};
 
+   clk26m: oscillator@0 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2600>;
+   clock-output-names = "clk26m";
+   };
+
+   rtc32k: oscillator@1 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32000>;
+   clock-output-names = "rtc32k";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <>;
@@ -85,6 +100,26 @@
 ;
};
 
+   topckgen: syscon@1000 {
+   compatible = "mediatek,mt2701-topckgen", "syscon";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infracfg: syscon@10001000 {
+   compatible = "mediatek,mt2701-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   pericfg: syscon@10003000 {
+   compatible = "mediatek,mt2701-pericfg", "syscon";
+   reg = <0 0x10003000 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
@@ -109,6 +144,13 @@
reg = <0 0x10200100 0 0x1c>;
};
 
+   apmixedsys: syscon@10209000 {
+   compatible = "mediatek,mt2701-apmixedsys", "syscon";
+   reg = <0 0x10209000 0 0x1000>;
+   mediatek,hdmi-ibias = <0xa>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
-- 
1.9.1

[PATCH v8 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT2701

[Erin Lo]

From: James Liao 

This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.

Signed-off-by: James Liao 
Tested-by: John Crispin 
Acked-by: Rob Herring 
---
 .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  3 ++-
 .../bindings/arm/mediatek/mediatek,bdpsys.txt  | 22 
 .../bindings/arm/mediatek/mediatek,ethsys.txt  | 22 
 .../bindings/arm/mediatek/mediatek,hifsys.txt  | 24 ++
 .../bindings/arm/mediatek/mediatek,imgsys.txt  |  3 ++-
 .../bindings/arm/mediatek/mediatek,infracfg.txt|  3 ++-
 .../bindings/arm/mediatek/mediatek,mmsys.txt   |  3 ++-
 .../bindings/arm/mediatek/mediatek,pericfg.txt |  3 ++-
 .../bindings/arm/mediatek/mediatek,topckgen.txt|  3 ++-
 .../bindings/arm/mediatek/mediatek,vdecsys.txt |  3 ++-
 10 files changed, 82 insertions(+), 7 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt

diff --git 
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 936166f..cb0054a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the 
system.
 
 Required Properties:
 
-- compatible: Should be:
+- compatible: Should be one of:
+   - "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
new file mode 100644
index 000..4137196
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -0,0 +1,22 @@
+Mediatek bdpsys controller
+
+
+The Mediatek bdpsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-bdpsys", "syscon"
+- #clock-cells: Must be 1
+
+The bdpsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+bdpsys: clock-controller@1c00 {
+   compatible = "mediatek,mt2701-bdpsys", "syscon";
+   reg = <0 0x1c00 0 0x1000>;
+   #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
new file mode 100644
index 000..768f3a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -0,0 +1,22 @@
+Mediatek ethsys controller
+
+
+The Mediatek ethsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-ethsys", "syscon"
+- #clock-cells: Must be 1
+
+The ethsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+ethsys: clock-controller@1b00 {
+   compatible = "mediatek,mt2701-ethsys", "syscon";
+   reg = <0 0x1b00 0 0x1000>;
+   #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
new file mode 100644
index 000..beed7b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
@@ -0,0 +1,24 @@
+Mediatek hifsys controller
+
+
+The Mediatek hifsys controller provides various clocks and reset
+outputs to the system.
+
+Required Properties:
+
+- compatible: Should be:
+   - "mediatek,mt2701-hifsys", "syscon"
+- #clock-cells: Must be 1
+
+The hifsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+hifsys: clock-controller@1a00 {
+   compatible = "mediatek,mt2701-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt 
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index b1f2ce1..f6a9166 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ 

[PATCH v8 10/10] arm: dts: mt2701: Use real clock for UARTs

[Erin Lo]

We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.

Signed-off-by: Erin Lo 
---
 arch/arm/boot/dts/mt2701.dtsi | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 171d4da..e79e88f 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -71,12 +71,6 @@
#clock-cells = <0>;
};
 
-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -167,7 +161,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART0_SEL>, < 
CLK_PERI_UART0>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -176,7 +171,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART1_SEL>, < 
CLK_PERI_UART1>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -185,7 +181,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART2_SEL>, < 
CLK_PERI_UART2>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -194,7 +191,8 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_PERI_UART3_SEL>, < 
CLK_PERI_UART3>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 };
-- 
1.9.1

[PATCH 06/11] dt/bindings: Correct clk binding example for PIC32 SDHCI

[Purna Chandra Mandal]

Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt 
b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
index 71ad57e..3149297 100644
--- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
+++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
@@ -20,7 +20,7 @@ Example:
compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
-   clocks = <>, <>;
+   clocks = < REF4CLK>, < PB5CLK>;
clock-names = "base_clk", "sys_clk";
bus-width = <4>;
cap-sd-highspeed;
-- 
1.8.3.1

[PATCH 07/11] dt/bindings: Correct clk binding example for PIC32 pinctrl

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
index 4b5efa5..29b72e3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
-   clocks = <>;
+   clocks = < PB1CLK>;
 
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
-- 
1.8.3.1

[PATCH 06/11] dt/bindings: Correct clk binding example for PIC32 SDHCI

[Purna Chandra Mandal]

Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt 
b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
index 71ad57e..3149297 100644
--- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
+++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
@@ -20,7 +20,7 @@ Example:
compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
-   clocks = <>, <>;
+   clocks = < REF4CLK>, < PB5CLK>;
clock-names = "base_clk", "sys_clk";
bus-width = <4>;
cap-sd-highspeed;
-- 
1.8.3.1

[PATCH 07/11] dt/bindings: Correct clk binding example for PIC32 pinctrl

[Purna Chandra Mandal]

Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt

Signed-off-by: Purna Chandra Mandal 
---

 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
index 4b5efa5..29b72e3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
-   clocks = <>;
+   clocks = < PB1CLK>;
 
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
-- 
1.8.3.1

[PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.

[Purna Chandra Mandal]

PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.

To fix this use PIC32 specific early clock functions implemented for early
console support.

Signed-off-by: Purna Chandra Mandal 

---
Note: Please pull this complete series through the MIPS tree.

---

 arch/mips/pic32/pic32mzda/time.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index ca6a62b..62a0a78 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -11,13 +11,12 @@
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  */
-#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
-#include 
 
 #include 
 
@@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
 
 void __init plat_time_init(void)
 {
-   struct clk *clk;
+   unsigned long rate = pic32_get_pbclk(7);
 
of_clk_init(NULL);
-   clk = clk_get_sys("cpu_clk", NULL);
-   if (IS_ERR(clk))
-   panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
-   clk_prepare_enable(clk);
-   pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 100);
-   mips_hpt_frequency = clk_get_rate(clk) / 2;
+   pr_info("CPU Clock: %ldMHz\n", rate / 100);
+   mips_hpt_frequency = rate / 2;
 
clocksource_probe();
 }
-- 
1.8.3.1

[PATCH 04/11] irqchip: irq-pic32-evic: Fix bug with external interrupts.

[Purna Chandra Mandal]

From: Joshua Henderson 

The wrong external interrupt bits are being set, offset by 1.

Signed-off-by: Joshua Henderson 
Signed-off-by: Purna Chandra Mandal 

---

 drivers/irqchip/irq-pic32-evic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-pic32-evic.c b/drivers/irqchip/irq-pic32-evic.c
index e7155db..73addb4 100644
--- a/drivers/irqchip/irq-pic32-evic.c
+++ b/drivers/irqchip/irq-pic32-evic.c
@@ -91,7 +91,7 @@ static int pic32_set_type_edge(struct irq_data *data,
/* set polarity for external interrupts only */
for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
if (priv->ext_irqs[i] == data->hwirq) {
-   ret = pic32_set_ext_polarity(i + 1, flow_type);
+   ret = pic32_set_ext_polarity(i, flow_type);
if (ret)
return ret;
}
-- 
1.8.3.1

[PATCH v8 02/10] clk: mediatek: remove __init from clk registration functions

[Erin Lo]

From: James Liao 

Remove __init from functions that will be used by init functions
that support probe deferral.

Signed-off-by: James Liao 
---
 drivers/clk/mediatek/clk-gate.c |  2 +-
 drivers/clk/mediatek/clk-mtk.c  | 12 ++--
 drivers/clk/mediatek/clk-pll.c  |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 2a76901..d8787bf 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -97,7 +97,7 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.disable= mtk_cg_disable_inv,
 };
 
-struct clk * __init mtk_clk_register_gate(
+struct clk *mtk_clk_register_gate(
const char *name,
const char *parent_name,
struct regmap *regmap,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 5ada644..bb30f70 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -24,7 +24,7 @@
 #include "clk-mtk.h"
 #include "clk-gate.h"
 
-struct clk_onecell_data * __init mtk_alloc_clk_data(unsigned int clk_num)
+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
 {
int i;
struct clk_onecell_data *clk_data;
@@ -49,7 +49,7 @@ err_out:
return NULL;
 }
 
-void __init mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
int num, struct clk_onecell_data *clk_data)
 {
int i;
@@ -72,7 +72,7 @@ void __init mtk_clk_register_fixed_clks(const struct 
mtk_fixed_clk *clks,
}
 }
 
-void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data)
 {
int i;
@@ -95,7 +95,7 @@ void __init mtk_clk_register_factors(const struct 
mtk_fixed_factor *clks,
}
 }
 
-int __init mtk_clk_register_gates(struct device_node *node,
+int mtk_clk_register_gates(struct device_node *node,
const struct mtk_gate *clks,
int num, struct clk_onecell_data *clk_data)
 {
@@ -135,7 +135,7 @@ int __init mtk_clk_register_gates(struct device_node *node,
return 0;
 }
 
-struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
 {
struct clk *clk;
@@ -222,7 +222,7 @@ err_out:
return ERR_PTR(ret);
 }
 
-void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
+void mtk_clk_register_composites(const struct mtk_composite *mcs,
int num, void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data)
 {
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 966cab1..0c2deac 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -313,7 +313,7 @@ static struct clk *mtk_clk_register_pll(const struct 
mtk_pll_data *data,
return clk;
 }
 
-void __init mtk_clk_register_plls(struct device_node *node,
+void mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls, struct 
clk_onecell_data *clk_data)
 {
void __iomem *base;
-- 
1.9.1

[PATCH 05/11] serial: pic32_uart: Fix double free of 'sport->irq_fault_name'.

[Purna Chandra Mandal]

Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.

Signed-off-by: Purna Chandra Mandal 

---

 drivers/tty/serial/pic32_uart.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
index 62a43bf..7f8e99b 100644
--- a/drivers/tty/serial/pic32_uart.c
+++ b/drivers/tty/serial/pic32_uart.c
@@ -445,7 +445,6 @@ static int pic32_uart_startup(struct uart_port *port)
   sport->idx);
if (!sport->irq_rx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
-   kfree(sport->irq_fault_name);
ret = -ENOMEM;
goto out_f;
}
-- 
1.8.3.1

[PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.

[Purna Chandra Mandal]

PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.

To fix this use PIC32 specific early clock functions implemented for early
console support.

Signed-off-by: Purna Chandra Mandal 

---
Note: Please pull this complete series through the MIPS tree.

---

 arch/mips/pic32/pic32mzda/time.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index ca6a62b..62a0a78 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -11,13 +11,12 @@
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  */
-#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
-#include 
 
 #include 
 
@@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
 
 void __init plat_time_init(void)
 {
-   struct clk *clk;
+   unsigned long rate = pic32_get_pbclk(7);
 
of_clk_init(NULL);
-   clk = clk_get_sys("cpu_clk", NULL);
-   if (IS_ERR(clk))
-   panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
-   clk_prepare_enable(clk);
-   pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 100);
-   mips_hpt_frequency = clk_get_rate(clk) / 2;
+   pr_info("CPU Clock: %ldMHz\n", rate / 100);
+   mips_hpt_frequency = rate / 2;
 
clocksource_probe();
 }
-- 
1.8.3.1

[PATCH 04/11] irqchip: irq-pic32-evic: Fix bug with external interrupts.

[Purna Chandra Mandal]

From: Joshua Henderson 

The wrong external interrupt bits are being set, offset by 1.

Signed-off-by: Joshua Henderson 
Signed-off-by: Purna Chandra Mandal 

---

 drivers/irqchip/irq-pic32-evic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-pic32-evic.c b/drivers/irqchip/irq-pic32-evic.c
index e7155db..73addb4 100644
--- a/drivers/irqchip/irq-pic32-evic.c
+++ b/drivers/irqchip/irq-pic32-evic.c
@@ -91,7 +91,7 @@ static int pic32_set_type_edge(struct irq_data *data,
/* set polarity for external interrupts only */
for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
if (priv->ext_irqs[i] == data->hwirq) {
-   ret = pic32_set_ext_polarity(i + 1, flow_type);
+   ret = pic32_set_ext_polarity(i, flow_type);
if (ret)
return ret;
}
-- 
1.8.3.1

[PATCH v8 02/10] clk: mediatek: remove __init from clk registration functions

[Erin Lo]

From: James Liao 

Remove __init from functions that will be used by init functions
that support probe deferral.

Signed-off-by: James Liao 
---
 drivers/clk/mediatek/clk-gate.c |  2 +-
 drivers/clk/mediatek/clk-mtk.c  | 12 ++--
 drivers/clk/mediatek/clk-pll.c  |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 2a76901..d8787bf 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -97,7 +97,7 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.disable= mtk_cg_disable_inv,
 };
 
-struct clk * __init mtk_clk_register_gate(
+struct clk *mtk_clk_register_gate(
const char *name,
const char *parent_name,
struct regmap *regmap,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 5ada644..bb30f70 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -24,7 +24,7 @@
 #include "clk-mtk.h"
 #include "clk-gate.h"
 
-struct clk_onecell_data * __init mtk_alloc_clk_data(unsigned int clk_num)
+struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
 {
int i;
struct clk_onecell_data *clk_data;
@@ -49,7 +49,7 @@ err_out:
return NULL;
 }
 
-void __init mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
int num, struct clk_onecell_data *clk_data)
 {
int i;
@@ -72,7 +72,7 @@ void __init mtk_clk_register_fixed_clks(const struct 
mtk_fixed_clk *clks,
}
 }
 
-void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data)
 {
int i;
@@ -95,7 +95,7 @@ void __init mtk_clk_register_factors(const struct 
mtk_fixed_factor *clks,
}
 }
 
-int __init mtk_clk_register_gates(struct device_node *node,
+int mtk_clk_register_gates(struct device_node *node,
const struct mtk_gate *clks,
int num, struct clk_onecell_data *clk_data)
 {
@@ -135,7 +135,7 @@ int __init mtk_clk_register_gates(struct device_node *node,
return 0;
 }
 
-struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
+struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
 {
struct clk *clk;
@@ -222,7 +222,7 @@ err_out:
return ERR_PTR(ret);
 }
 
-void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
+void mtk_clk_register_composites(const struct mtk_composite *mcs,
int num, void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data)
 {
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 966cab1..0c2deac 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -313,7 +313,7 @@ static struct clk *mtk_clk_register_pll(const struct 
mtk_pll_data *data,
return clk;
 }
 
-void __init mtk_clk_register_plls(struct device_node *node,
+void mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls, struct 
clk_onecell_data *clk_data)
 {
void __iomem *base;
-- 
1.9.1

[PATCH 05/11] serial: pic32_uart: Fix double free of 'sport->irq_fault_name'.

[Purna Chandra Mandal]

Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.

Signed-off-by: Purna Chandra Mandal 

---

 drivers/tty/serial/pic32_uart.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
index 62a43bf..7f8e99b 100644
--- a/drivers/tty/serial/pic32_uart.c
+++ b/drivers/tty/serial/pic32_uart.c
@@ -445,7 +445,6 @@ static int pic32_uart_startup(struct uart_port *port)
   sport->idx);
if (!sport->irq_rx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
-   kfree(sport->irq_fault_name);
ret = -ENOMEM;
goto out_f;
}
-- 
1.8.3.1

[PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA.

[Purna Chandra Mandal]

Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.

Signed-off-by: Purna Chandra Mandal 

---
Note: Please pull this complete series through the MIPS tree.

---

 drivers/clk/microchip/clk-pic32mzda.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/microchip/clk-pic32mzda.c 
b/drivers/clk/microchip/clk-pic32mzda.c
index 020a29a..210694b 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
+   .fixed_rate = 32768,
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
-- 
1.8.3.1

[PATCH 01/11] clk: microchip: use readl_poll_timeout() in pbclk_set_rate().

[Purna Chandra Mandal]

pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().

Signed-off-by: Purna Chandra Mandal 
---
Note: Please pull this complete series through the MIPS tree.

---

 drivers/clk/microchip/clk-core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
index ca85cea..c3b3014 100644
--- a/drivers/clk/microchip/clk-core.c
+++ b/drivers/clk/microchip/clk-core.c
@@ -199,9 +199,9 @@ static int pbclk_set_rate(struct clk_hw *hw, unsigned long 
rate,
 
spin_unlock_irqrestore(>core->reg_lock, flags);
 
-   /* wait again, for pbdivready */
-   err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
-   1, LOCK_TIMEOUT_US);
+   /* wait again for DIV_READY */
+   err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
+1, LOCK_TIMEOUT_US);
if (err)
return err;
 
-- 
1.8.3.1

[PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA.

[Purna Chandra Mandal]

Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.

Signed-off-by: Purna Chandra Mandal 

---
Note: Please pull this complete series through the MIPS tree.

---

 drivers/clk/microchip/clk-pic32mzda.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/microchip/clk-pic32mzda.c 
b/drivers/clk/microchip/clk-pic32mzda.c
index 020a29a..210694b 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
+   .fixed_rate = 32768,
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
-- 
1.8.3.1

[PATCH 01/11] clk: microchip: use readl_poll_timeout() in pbclk_set_rate().

[Purna Chandra Mandal]

pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().

Signed-off-by: Purna Chandra Mandal 
---
Note: Please pull this complete series through the MIPS tree.

---

 drivers/clk/microchip/clk-core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
index ca85cea..c3b3014 100644
--- a/drivers/clk/microchip/clk-core.c
+++ b/drivers/clk/microchip/clk-core.c
@@ -199,9 +199,9 @@ static int pbclk_set_rate(struct clk_hw *hw, unsigned long 
rate,
 
spin_unlock_irqrestore(>core->reg_lock, flags);
 
-   /* wait again, for pbdivready */
-   err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
-   1, LOCK_TIMEOUT_US);
+   /* wait again for DIV_READY */
+   err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
+1, LOCK_TIMEOUT_US);
if (err)
return err;
 
-- 
1.8.3.1

[PATCH v8 0/10] Add clock support for Mediatek MT2701

[Erin Lo]

This series is based on clk-next, add clock and reset controller support
for Mediatek MT2701.

This series also refined makefile and Kconfig to support configurable
multiple SoC clock support.

There some code borrowed from [2] in clk-mtk.h, and may need to resolve
conflicts while merging these two series.

changes since v7:
- Rebase to clk-next.
- Implement subsystem clocks in seperated files.
- Replace critical clock enabling with CLK_IS_CRITICAL flag.
- Reduce most clock registrations in CLK_OF_DECLARE().
- Remove __init and __initconst from most init fucntions and data,
  and replace driver registration with platform_driver_register().
- Replace some common function or variable names with unique names.
- Use real clock for UARTs.

changes since v6:
- Rebase to v4.6-rc1.
- Register subsystem clocks in probe() instead of CLK_OF_DECLARE().
- Add clocks that referred by subsystem clocks.
- Fix clk_data size of apmixedsys.
- Add config options for each subsystem clock provider.

changes since v5:
- Rebase to v4.5-rc1 and [1].
- Enable critical clocks for MT2701
- Refine dt-binding documents, add reset controller support for hifsys.

changes since v4:
- Rebase to v4.5-rc1.
- Remove CLK_SET_RATE_PARENT from divider flags.
- Add img_jpgdec_smi clock.
- Move clk/mediatek/Kconfig into menu section in clk/Kconfig.

changes since v3:
- Change the parent of mm_mdp_bls_26m from clk26m to pwm_sel.

changes since v2:
- Fix ethsys definition.
- Replace read-modify-write with regmap_update_bits() in clock operations.
- Move mt2701-resets.h to include/dt-bindings/reset/.
- Add hifsys reset patch from John Crispin.

changes since v1:
- Document MT2701 compatible strings.

[1] https://patchwork.kernel.org/patch/8147901/
[2] http://www.spinics.net/lists/dri-devel/msg106726.html

Erin Lo (1):
  arm: dts: mt2701: Use real clock for UARTs

James Liao (5):
  clk: fix initial state of critical clock's parents
  clk: mediatek: remove __init from clk registration functions
  clk: mediatek: Refine the makefile to support multiple clock drivers
  dt-bindings: ARM: Mediatek: Document bindings for MT2701
  arm: dts: mt2701: Add clock controller device nodes

Shunli Wang (4):
  clk: mediatek: Add dt-bindings for MT2701 clocks
  clk: mediatek: Add MT2701 clock support
  reset: mediatek: Add MT2701 reset controller dt-binding file
  reset: mediatek: Add MT2701 reset driver

 .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |3 +-
 .../bindings/arm/mediatek/mediatek,bdpsys.txt  |   22 +
 .../bindings/arm/mediatek/mediatek,ethsys.txt  |   22 +
 .../bindings/arm/mediatek/mediatek,hifsys.txt  |   24 +
 .../bindings/arm/mediatek/mediatek,imgsys.txt  |3 +-
 .../bindings/arm/mediatek/mediatek,infracfg.txt|3 +-
 .../bindings/arm/mediatek/mediatek,mmsys.txt   |3 +-
 .../bindings/arm/mediatek/mediatek,pericfg.txt |3 +-
 .../bindings/arm/mediatek/mediatek,topckgen.txt|3 +-
 .../bindings/arm/mediatek/mediatek,vdecsys.txt |3 +-
 arch/arm/boot/dts/mt2701.dtsi  |   50 +-
 drivers/clk/Kconfig|1 +
 drivers/clk/clk.c  |9 +-
 drivers/clk/mediatek/Kconfig   |   73 ++
 drivers/clk/mediatek/Makefile  |   13 +-
 drivers/clk/mediatek/clk-gate.c|   54 +-
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +++
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 ++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   81 ++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 ++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 +++
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 ++
 drivers/clk/mediatek/clk-mt2701.c  | 1037 
 drivers/clk/mediatek/clk-mtk.c |   52 +-
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |3 +-
 include/dt-bindings/clock/mt2701-clk.h |  486 +
 include/dt-bindings/reset/mt2701-resets.h  |   83 ++
 29 files changed, 2578 insertions(+), 29 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 create mode 100644 drivers/clk/mediatek/Kconfig
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c
 create mode 100644 

[PATCH v8 0/10] Add clock support for Mediatek MT2701

[Erin Lo]

This series is based on clk-next, add clock and reset controller support
for Mediatek MT2701.

This series also refined makefile and Kconfig to support configurable
multiple SoC clock support.

There some code borrowed from [2] in clk-mtk.h, and may need to resolve
conflicts while merging these two series.

changes since v7:
- Rebase to clk-next.
- Implement subsystem clocks in seperated files.
- Replace critical clock enabling with CLK_IS_CRITICAL flag.
- Reduce most clock registrations in CLK_OF_DECLARE().
- Remove __init and __initconst from most init fucntions and data,
  and replace driver registration with platform_driver_register().
- Replace some common function or variable names with unique names.
- Use real clock for UARTs.

changes since v6:
- Rebase to v4.6-rc1.
- Register subsystem clocks in probe() instead of CLK_OF_DECLARE().
- Add clocks that referred by subsystem clocks.
- Fix clk_data size of apmixedsys.
- Add config options for each subsystem clock provider.

changes since v5:
- Rebase to v4.5-rc1 and [1].
- Enable critical clocks for MT2701
- Refine dt-binding documents, add reset controller support for hifsys.

changes since v4:
- Rebase to v4.5-rc1.
- Remove CLK_SET_RATE_PARENT from divider flags.
- Add img_jpgdec_smi clock.
- Move clk/mediatek/Kconfig into menu section in clk/Kconfig.

changes since v3:
- Change the parent of mm_mdp_bls_26m from clk26m to pwm_sel.

changes since v2:
- Fix ethsys definition.
- Replace read-modify-write with regmap_update_bits() in clock operations.
- Move mt2701-resets.h to include/dt-bindings/reset/.
- Add hifsys reset patch from John Crispin.

changes since v1:
- Document MT2701 compatible strings.

[1] https://patchwork.kernel.org/patch/8147901/
[2] http://www.spinics.net/lists/dri-devel/msg106726.html

Erin Lo (1):
  arm: dts: mt2701: Use real clock for UARTs

James Liao (5):
  clk: fix initial state of critical clock's parents
  clk: mediatek: remove __init from clk registration functions
  clk: mediatek: Refine the makefile to support multiple clock drivers
  dt-bindings: ARM: Mediatek: Document bindings for MT2701
  arm: dts: mt2701: Add clock controller device nodes

Shunli Wang (4):
  clk: mediatek: Add dt-bindings for MT2701 clocks
  clk: mediatek: Add MT2701 clock support
  reset: mediatek: Add MT2701 reset controller dt-binding file
  reset: mediatek: Add MT2701 reset driver

 .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |3 +-
 .../bindings/arm/mediatek/mediatek,bdpsys.txt  |   22 +
 .../bindings/arm/mediatek/mediatek,ethsys.txt  |   22 +
 .../bindings/arm/mediatek/mediatek,hifsys.txt  |   24 +
 .../bindings/arm/mediatek/mediatek,imgsys.txt  |3 +-
 .../bindings/arm/mediatek/mediatek,infracfg.txt|3 +-
 .../bindings/arm/mediatek/mediatek,mmsys.txt   |3 +-
 .../bindings/arm/mediatek/mediatek,pericfg.txt |3 +-
 .../bindings/arm/mediatek/mediatek,topckgen.txt|3 +-
 .../bindings/arm/mediatek/mediatek,vdecsys.txt |3 +-
 arch/arm/boot/dts/mt2701.dtsi  |   50 +-
 drivers/clk/Kconfig|1 +
 drivers/clk/clk.c  |9 +-
 drivers/clk/mediatek/Kconfig   |   73 ++
 drivers/clk/mediatek/Makefile  |   13 +-
 drivers/clk/mediatek/clk-gate.c|   54 +-
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +++
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 ++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   81 ++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 ++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 +++
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 ++
 drivers/clk/mediatek/clk-mt2701.c  | 1037 
 drivers/clk/mediatek/clk-mtk.c |   52 +-
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |3 +-
 include/dt-bindings/clock/mt2701-clk.h |  486 +
 include/dt-bindings/reset/mt2701-resets.h  |   83 ++
 29 files changed, 2578 insertions(+), 29 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 create mode 100644 drivers/clk/mediatek/Kconfig
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c
 create mode 100644 

linux-next: Tree for May 17

[Stephen Rothwell]

Hi all,

Please do not add any v4.8 destined material to your linux-next included
branches until after v4.7-rc1 has been released.

Changes since 20160516:

The vfs tree gained a conflict against the ext4 tree.

The net-next tree gained a conflict against the arm64 tree.

The spi tree lost its build failure.

Non-merge commits (relative to Linus' tree): 9737
 8314 files changed, 424907 insertions(+), 177068 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig (with
CONFIG_BUILD_DOCSRC=n) for x86_64, a multi_v7_defconfig for arm and a
native build of tools/perf. After the final fixups (if any), I do an
x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
(this fails its final link) and pseries_le_defconfig and i386, sparc
and sparc64 defconfig.

Below is a summary of the state of the merge.

I am currently merging 235 trees (counting Linus' and 35 trees of patches
pending for Linus' tree).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (cf6ed9a6682d Merge branch 'ras-core-for-linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip)
Merging fixes/master (b507146bb6b9 Merge branch 'linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6)
Merging kbuild-current/rc-fixes (3d1450d54a4f Makefile: Force gzip and xz on 
module install)
Merging arc-current/for-curr (44549e8f5eea Linux 4.6-rc7)
Merging arm-current/fixes (ec953b70f368 ARM: 8573/1: domain: move 
{set,get}_domain under config guard)
Merging m68k-current/for-linus (9a6462763b17 m68k/mvme16x: Include generic 
)
Merging metag-fixes/fixes (0164a711c97b metag: Fix ioremap_wc/ioremap_cached 
build errors)
Merging powerpc-fixes/fixes (b4c112114aab powerpc: Fix bad inline asm 
constraint in create_zero_mask())
Merging powerpc-merge-mpe/fixes (bc0195aad0da Linux 4.2-rc2)
Merging sparc/master (33656a1f2ee5 Merge branch 'for_linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs)
Merging net/master (2dcd0af568b0 Linux 4.6)
Merging ipsec/master (d6af1a31cc72 vti: Add pmtu handling to vti_xmit.)
Merging ipvs/master (f28f20da704d Merge 
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net)
Merging wireless-drivers/master (cbbba30f1ac9 Merge tag 
'iwlwifi-for-kalle-2016-05-04' of 
https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-fixes)
Merging mac80211/master (e6436be21e77 mac80211: fix statistics leak if 
dev_alloc_name() fails)
Merging sound-current/for-linus (a158f2b79ff1 Merge tag 'asoc-v4.7' of 
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus)
Merging pci-current/for-linus (9a2a5a638f8e PCI: Do not treat EPROBE_DEFER as 
device attach failure)
Merging driver-core.current/driver-core-linus (c3b46c73264b Linux 4.6-rc4)
Merging tty.current/tty-linus (44549e8f5eea Linux 4.6-rc7)
Merging usb.current/usb-linus (44549e8f5eea Linux 4.6-rc7)
Merging usb-gadget-fixes/fixes (38740a5b87d5 usb: gadget: f_fs: Fix 
use-after-free)
Merging usb-serial-fixes/usb-linus (74d2a91aec97 USB: serial: option: add even 
more ZTE device ids)
Merging usb-chipidea-fixes/ci-for-usb-stable (d144dfea8af7 usb: chipidea: otg: 
change workqueue ci_otg as freezable)
Merging staging.current/staging-linus (44549e8f5eea Linux 4.6-rc7)
Merging char-misc.current/char-misc-linus (44549e8f5eea Linux 4.6-rc7)
Merging input-current/for-linus (c52c545ead97 Input: twl6040-vibra - fix DT 
node memory management)
Merging crypto-current/master (256b1cfb9a34 crypto: qat - change the 
adf_ctl_stop_devices to void)
Merging ide/master (1993b176a822 Merge 
git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide)
Merging devicetree-current/devicetree/merge (f76502aa9140 of/dynamic: Fix test 
for PPC_PSERIES)
Merging rr-fixes/fixes (8244062ef1e5 modules: fix longstanding /proc/kallsyms 

linux-next: Tree for May 17

[Stephen Rothwell]

Hi all,

Please do not add any v4.8 destined material to your linux-next included
branches until after v4.7-rc1 has been released.

Changes since 20160516:

The vfs tree gained a conflict against the ext4 tree.

The net-next tree gained a conflict against the arm64 tree.

The spi tree lost its build failure.

Non-merge commits (relative to Linus' tree): 9737
 8314 files changed, 424907 insertions(+), 177068 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig (with
CONFIG_BUILD_DOCSRC=n) for x86_64, a multi_v7_defconfig for arm and a
native build of tools/perf. After the final fixups (if any), I do an
x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
(this fails its final link) and pseries_le_defconfig and i386, sparc
and sparc64 defconfig.

Below is a summary of the state of the merge.

I am currently merging 235 trees (counting Linus' and 35 trees of patches
pending for Linus' tree).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (cf6ed9a6682d Merge branch 'ras-core-for-linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip)
Merging fixes/master (b507146bb6b9 Merge branch 'linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6)
Merging kbuild-current/rc-fixes (3d1450d54a4f Makefile: Force gzip and xz on 
module install)
Merging arc-current/for-curr (44549e8f5eea Linux 4.6-rc7)
Merging arm-current/fixes (ec953b70f368 ARM: 8573/1: domain: move 
{set,get}_domain under config guard)
Merging m68k-current/for-linus (9a6462763b17 m68k/mvme16x: Include generic 
)
Merging metag-fixes/fixes (0164a711c97b metag: Fix ioremap_wc/ioremap_cached 
build errors)
Merging powerpc-fixes/fixes (b4c112114aab powerpc: Fix bad inline asm 
constraint in create_zero_mask())
Merging powerpc-merge-mpe/fixes (bc0195aad0da Linux 4.2-rc2)
Merging sparc/master (33656a1f2ee5 Merge branch 'for_linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs)
Merging net/master (2dcd0af568b0 Linux 4.6)
Merging ipsec/master (d6af1a31cc72 vti: Add pmtu handling to vti_xmit.)
Merging ipvs/master (f28f20da704d Merge 
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net)
Merging wireless-drivers/master (cbbba30f1ac9 Merge tag 
'iwlwifi-for-kalle-2016-05-04' of 
https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-fixes)
Merging mac80211/master (e6436be21e77 mac80211: fix statistics leak if 
dev_alloc_name() fails)
Merging sound-current/for-linus (a158f2b79ff1 Merge tag 'asoc-v4.7' of 
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus)
Merging pci-current/for-linus (9a2a5a638f8e PCI: Do not treat EPROBE_DEFER as 
device attach failure)
Merging driver-core.current/driver-core-linus (c3b46c73264b Linux 4.6-rc4)
Merging tty.current/tty-linus (44549e8f5eea Linux 4.6-rc7)
Merging usb.current/usb-linus (44549e8f5eea Linux 4.6-rc7)
Merging usb-gadget-fixes/fixes (38740a5b87d5 usb: gadget: f_fs: Fix 
use-after-free)
Merging usb-serial-fixes/usb-linus (74d2a91aec97 USB: serial: option: add even 
more ZTE device ids)
Merging usb-chipidea-fixes/ci-for-usb-stable (d144dfea8af7 usb: chipidea: otg: 
change workqueue ci_otg as freezable)
Merging staging.current/staging-linus (44549e8f5eea Linux 4.6-rc7)
Merging char-misc.current/char-misc-linus (44549e8f5eea Linux 4.6-rc7)
Merging input-current/for-linus (c52c545ead97 Input: twl6040-vibra - fix DT 
node memory management)
Merging crypto-current/master (256b1cfb9a34 crypto: qat - change the 
adf_ctl_stop_devices to void)
Merging ide/master (1993b176a822 Merge 
git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide)
Merging devicetree-current/devicetree/merge (f76502aa9140 of/dynamic: Fix test 
for PPC_PSERIES)
Merging rr-fixes/fixes (8244062ef1e5 modules: fix longstanding /proc/kallsyms 

[mm] 23047a96d7: vm-scalability.throughput -23.8% regression

[kernel test robot]

caec526ea4803e9e/0"
job_file: 
"/lkp/scheduled/lkp-hsw01/bisect_vm-scalability-performance-300s-lru-file-readtwice-debian-x86_64-2015-02-07.cgz-x86_64-rhel-23047a96d7cfcfca1a6d026ecaec526ea4803e9e-20160517-25208-1epp6aw-0.yaml"
max_uptime: 1500
initrd: "/osimage/debian/debian-x86_64-2015-02-07.cgz"
bootloader_append:
- root=/dev/ram0
- user=lkp
- 
job=/lkp/scheduled/lkp-hsw01/bisect_vm-scalability-performance-300s-lru-file-readtwice-debian-x86_64-2015-02-07.cgz-x86_64-rhel-23047a96d7cfcfca1a6d026ecaec526ea4803e9e-20160517-25208-1epp6aw-0.yaml
- ARCH=x86_64
- kconfig=x86_64-rhel
- branch=linus/master
- commit=23047a96d7cfcfca1a6d026ecaec526ea4803e9e
- 
BOOT_IMAGE=/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9
- max_uptime=1500
- 
RESULT_ROOT=/result/vm-scalability/performance-300s-lru-file-readtwice/lkp-hsw01/debian-x86_64-2015-02-07.cgz/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/0
- LKP_SERVER=inn
- |2-


  earlyprintk=ttyS0,115200 systemd.log_level=err
  debug apic=debug sysrq_always_enabled rcupdate.rcu_cpu_stall_timeout=100
  panic=-1 softlockup_panic=1 nmi_watchdog=panic oops=panic load_ramdisk=2 
prompt_ramdisk=0
  console=ttyS0,115200 console=tty0 vga=normal

  rw
lkp_initrd: "/lkp/lkp/lkp-x86_64.cgz"
modules_initrd: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/modules.cgz"
bm_initrd: 
"/osimage/deps/debian-x86_64-2015-02-07.cgz/lkp.cgz,/osimage/deps/debian-x86_64-2015-02-07.cgz/run-ipconfig.cgz,/osimage/deps/debian-x86_64-2015-02-07.cgz/turbostat.cgz,/lkp/benchmarks/turbostat.cgz,/lkp/benchmarks/perf-profile-x86_64.cgz,/lkp/benchmarks/vm-scalability.cgz"
linux_headers_initrd: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/linux-headers.cgz"
repeat_to: 2
kernel: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9"
dequeue_time: 2016-05-17 00:25:26.281743408 +08:00
job_state: finished
loadavg: 39.10 58.24 29.31 1/548 9271
start_time: '1463415975'
end_time: '1463416286'
version: "/lkp/lkp/.src-20160516-224742"
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu1/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu10/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu11/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu12/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu13/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu14/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu15/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu16/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu17/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu18/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu19/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu2/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu20/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu21/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu22/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu23/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu24/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu25/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu26/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu27/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu28/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu29/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu3/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu30/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu31/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu32/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu33/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices

[mm] 23047a96d7: vm-scalability.throughput -23.8% regression

[kernel test robot]

caec526ea4803e9e/0"
job_file: 
"/lkp/scheduled/lkp-hsw01/bisect_vm-scalability-performance-300s-lru-file-readtwice-debian-x86_64-2015-02-07.cgz-x86_64-rhel-23047a96d7cfcfca1a6d026ecaec526ea4803e9e-20160517-25208-1epp6aw-0.yaml"
max_uptime: 1500
initrd: "/osimage/debian/debian-x86_64-2015-02-07.cgz"
bootloader_append:
- root=/dev/ram0
- user=lkp
- 
job=/lkp/scheduled/lkp-hsw01/bisect_vm-scalability-performance-300s-lru-file-readtwice-debian-x86_64-2015-02-07.cgz-x86_64-rhel-23047a96d7cfcfca1a6d026ecaec526ea4803e9e-20160517-25208-1epp6aw-0.yaml
- ARCH=x86_64
- kconfig=x86_64-rhel
- branch=linus/master
- commit=23047a96d7cfcfca1a6d026ecaec526ea4803e9e
- 
BOOT_IMAGE=/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9
- max_uptime=1500
- 
RESULT_ROOT=/result/vm-scalability/performance-300s-lru-file-readtwice/lkp-hsw01/debian-x86_64-2015-02-07.cgz/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/0
- LKP_SERVER=inn
- |2-


  earlyprintk=ttyS0,115200 systemd.log_level=err
  debug apic=debug sysrq_always_enabled rcupdate.rcu_cpu_stall_timeout=100
  panic=-1 softlockup_panic=1 nmi_watchdog=panic oops=panic load_ramdisk=2 
prompt_ramdisk=0
  console=ttyS0,115200 console=tty0 vga=normal

  rw
lkp_initrd: "/lkp/lkp/lkp-x86_64.cgz"
modules_initrd: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/modules.cgz"
bm_initrd: 
"/osimage/deps/debian-x86_64-2015-02-07.cgz/lkp.cgz,/osimage/deps/debian-x86_64-2015-02-07.cgz/run-ipconfig.cgz,/osimage/deps/debian-x86_64-2015-02-07.cgz/turbostat.cgz,/lkp/benchmarks/turbostat.cgz,/lkp/benchmarks/perf-profile-x86_64.cgz,/lkp/benchmarks/vm-scalability.cgz"
linux_headers_initrd: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/linux-headers.cgz"
repeat_to: 2
kernel: 
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9"
dequeue_time: 2016-05-17 00:25:26.281743408 +08:00
job_state: finished
loadavg: 39.10 58.24 29.31 1/548 9271
start_time: '1463415975'
end_time: '1463416286'
version: "/lkp/lkp/.src-20160516-224742"
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu1/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu10/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu11/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu12/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu13/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu14/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu15/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu16/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu17/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu18/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu19/cpufreq/scaling_governor
2016-05-17 00:26:13 echo performance > 
/sys/devices/system/cpu/cpu2/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu20/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu21/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu22/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu23/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu24/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu25/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu26/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu27/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu28/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu29/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu3/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu30/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu31/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu32/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices/system/cpu/cpu33/cpufreq/scaling_governor
2016-05-17 00:26:14 echo performance > 
/sys/devices

Re: [PATCH v2] tpm: Factor out common startup code

[Jarkko Sakkinen]

On Mon, May 16, 2016 at 12:25:47PM -0600, Jason Gunthorpe wrote:
> Provide some flags in tpm_class_ops to allow drivers to opt-in to the
> common startup sequence. This is the sequence used by tpm_tis and
> tpm_crb.
> 
> All drivers should set this flag.

The commit message should be a much much more verbose I cannot include
this without a better explanation. Please update this for the next
revision.

> Signed-off-by: Jason Gunthorpe 
> Tested-by: Andrew Zamansky 
> ---
>  drivers/char/tpm/st33zp24/st33zp24.c |  4 +---
>  drivers/char/tpm/tpm-chip.c  | 15 ++
>  drivers/char/tpm/tpm-interface.c | 27 
>  drivers/char/tpm/tpm.h   |  2 ++
>  drivers/char/tpm/tpm2-cmd.c  | 40 
> 
>  drivers/char/tpm/tpm_crb.c   | 10 +
>  drivers/char/tpm/tpm_i2c_atmel.c |  6 +-
>  drivers/char/tpm/tpm_i2c_infineon.c  |  4 +---
>  drivers/char/tpm/tpm_i2c_nuvoton.c   |  7 +--
>  drivers/char/tpm/tpm_tis.c   | 24 +-
>  include/linux/tpm.h  |  6 ++
>  11 files changed, 96 insertions(+), 49 deletions(-)
> 
> v2 has a little typo fix From Andrew in the call to tpm2_startup
> 
> diff --git a/drivers/char/tpm/st33zp24/st33zp24.c 
> b/drivers/char/tpm/st33zp24/st33zp24.c
> index 8d626784cd8d..4556c95f83cb 100644
> --- a/drivers/char/tpm/st33zp24/st33zp24.c
> +++ b/drivers/char/tpm/st33zp24/st33zp24.c
> @@ -532,6 +532,7 @@ static bool st33zp24_req_canceled(struct tpm_chip *chip, 
> u8 status)
>  }
>  
>  static const struct tpm_class_ops st33zp24_tpm = {
> + .flags = TPM_OPS_AUTO_STARTUP,
>   .send = st33zp24_send,
>   .recv = st33zp24_recv,
>   .cancel = st33zp24_cancel,
> @@ -618,9 +619,6 @@ int st33zp24_probe(void *phy_id, const struct 
> st33zp24_phy_ops *ops,
>   tpm_gen_interrupt(chip);
>   }
>  
> - tpm_get_timeouts(chip);
> - tpm_do_selftest(chip);
> -
>   return tpm_chip_register(chip);
>  _tpm_clean_answer:
>   dev_info(>dev, "TPM initialization fail\n");
> diff --git a/drivers/char/tpm/tpm-chip.c b/drivers/char/tpm/tpm-chip.c
> index 274dd0123237..9a36cedd94eb 100644
> --- a/drivers/char/tpm/tpm-chip.c
> +++ b/drivers/char/tpm/tpm-chip.c
> @@ -223,6 +223,21 @@ int tpm_chip_register(struct tpm_chip *chip)
>  {
>   int rc;
>  
> + if (chip->ops->flags & TPM_OPS_PROBE_TPM2) {
> + rc = tpm2_probe(chip);
> + if (rc)
> + return rc;
> + }

Dead code.

> +
> + if (chip->ops->flags & TPM_OPS_AUTO_STARTUP) {
> + if (chip->flags & TPM_CHIP_FLAG_TPM2)
> + rc = tpm2_auto_startup(chip);
> + else
> + rc = tpm1_auto_startup(chip);
> + if (rc)
> + return rc;
> + }
> +
>   rc = tpm1_chip_register(chip);
>   if (rc)
>   return rc;
> diff --git a/drivers/char/tpm/tpm-interface.c 
> b/drivers/char/tpm/tpm-interface.c
> index e2fa89c88304..4e6798ab3a90 100644
> --- a/drivers/char/tpm/tpm-interface.c
> +++ b/drivers/char/tpm/tpm-interface.c
> @@ -842,6 +842,33 @@ int tpm_do_selftest(struct tpm_chip *chip)
>  }
>  EXPORT_SYMBOL_GPL(tpm_do_selftest);
>  
> +/**
> + * tpm1_auto_startup - Perform the standard automatic TPM initialization
> + * sequence
> + * @chip: TPM chip to use
> + *
> + * Returns 0 on success, < 0 in case of fatal error.
> + */
> +int tpm1_auto_startup(struct tpm_chip *chip)
> +{
> + int rc;
> +
> + rc = tpm_get_timeouts(chip);
> + if (rc)
> + goto out;
> + rc = tpm_do_selftest(chip);
> + if (rc) {
> + dev_err(>dev, "TPM self test failed\n");
> + goto out;
> + }
> +
> + return rc;
> +out:
> + if (rc > 0)
> + rc = -ENODEV;
> + return rc;
> +}
> +
>  int tpm_send(u32 chip_num, void *cmd, size_t buflen)
>  {
>   struct tpm_chip *chip;
> diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
> index 28b477e8da6a..a99105f1a5c4 100644
> --- a/drivers/char/tpm/tpm.h
> +++ b/drivers/char/tpm/tpm.h
> @@ -501,6 +501,7 @@ ssize_t tpm_transmit_cmd(struct tpm_chip *chip, void 
> *cmd, int len,
>const char *desc);
>  extern int tpm_get_timeouts(struct tpm_chip *);
>  extern void tpm_gen_interrupt(struct tpm_chip *);
> +int tpm1_auto_startup(struct tpm_chip *chip);
>  extern int tpm_do_selftest(struct tpm_chip *);
>  extern unsigned long tpm_calc_ordinal_duration(struct tpm_chip *, u32);
>  extern int tpm_pm_suspend(struct device *);
> @@ -539,6 +540,7 @@ int tpm2_unseal_trusted(struct tpm_chip *chip,
>  ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id,
>   u32 *value, const char *desc);
>  
> +int tpm2_auto_startup(struct tpm_chip *chip);
>  extern int tpm2_startup(struct tpm_chip *chip, u16 startup_type);
>  

Re: [PATCH v2] tpm: Factor out common startup code

[Jarkko Sakkinen]

On Mon, May 16, 2016 at 12:25:47PM -0600, Jason Gunthorpe wrote:
> Provide some flags in tpm_class_ops to allow drivers to opt-in to the
> common startup sequence. This is the sequence used by tpm_tis and
> tpm_crb.
> 
> All drivers should set this flag.

The commit message should be a much much more verbose I cannot include
this without a better explanation. Please update this for the next
revision.

> Signed-off-by: Jason Gunthorpe 
> Tested-by: Andrew Zamansky 
> ---
>  drivers/char/tpm/st33zp24/st33zp24.c |  4 +---
>  drivers/char/tpm/tpm-chip.c  | 15 ++
>  drivers/char/tpm/tpm-interface.c | 27 
>  drivers/char/tpm/tpm.h   |  2 ++
>  drivers/char/tpm/tpm2-cmd.c  | 40 
> 
>  drivers/char/tpm/tpm_crb.c   | 10 +
>  drivers/char/tpm/tpm_i2c_atmel.c |  6 +-
>  drivers/char/tpm/tpm_i2c_infineon.c  |  4 +---
>  drivers/char/tpm/tpm_i2c_nuvoton.c   |  7 +--
>  drivers/char/tpm/tpm_tis.c   | 24 +-
>  include/linux/tpm.h  |  6 ++
>  11 files changed, 96 insertions(+), 49 deletions(-)
> 
> v2 has a little typo fix From Andrew in the call to tpm2_startup
> 
> diff --git a/drivers/char/tpm/st33zp24/st33zp24.c 
> b/drivers/char/tpm/st33zp24/st33zp24.c
> index 8d626784cd8d..4556c95f83cb 100644
> --- a/drivers/char/tpm/st33zp24/st33zp24.c
> +++ b/drivers/char/tpm/st33zp24/st33zp24.c
> @@ -532,6 +532,7 @@ static bool st33zp24_req_canceled(struct tpm_chip *chip, 
> u8 status)
>  }
>  
>  static const struct tpm_class_ops st33zp24_tpm = {
> + .flags = TPM_OPS_AUTO_STARTUP,
>   .send = st33zp24_send,
>   .recv = st33zp24_recv,
>   .cancel = st33zp24_cancel,
> @@ -618,9 +619,6 @@ int st33zp24_probe(void *phy_id, const struct 
> st33zp24_phy_ops *ops,
>   tpm_gen_interrupt(chip);
>   }
>  
> - tpm_get_timeouts(chip);
> - tpm_do_selftest(chip);
> -
>   return tpm_chip_register(chip);
>  _tpm_clean_answer:
>   dev_info(>dev, "TPM initialization fail\n");
> diff --git a/drivers/char/tpm/tpm-chip.c b/drivers/char/tpm/tpm-chip.c
> index 274dd0123237..9a36cedd94eb 100644
> --- a/drivers/char/tpm/tpm-chip.c
> +++ b/drivers/char/tpm/tpm-chip.c
> @@ -223,6 +223,21 @@ int tpm_chip_register(struct tpm_chip *chip)
>  {
>   int rc;
>  
> + if (chip->ops->flags & TPM_OPS_PROBE_TPM2) {
> + rc = tpm2_probe(chip);
> + if (rc)
> + return rc;
> + }

Dead code.

> +
> + if (chip->ops->flags & TPM_OPS_AUTO_STARTUP) {
> + if (chip->flags & TPM_CHIP_FLAG_TPM2)
> + rc = tpm2_auto_startup(chip);
> + else
> + rc = tpm1_auto_startup(chip);
> + if (rc)
> + return rc;
> + }
> +
>   rc = tpm1_chip_register(chip);
>   if (rc)
>   return rc;
> diff --git a/drivers/char/tpm/tpm-interface.c 
> b/drivers/char/tpm/tpm-interface.c
> index e2fa89c88304..4e6798ab3a90 100644
> --- a/drivers/char/tpm/tpm-interface.c
> +++ b/drivers/char/tpm/tpm-interface.c
> @@ -842,6 +842,33 @@ int tpm_do_selftest(struct tpm_chip *chip)
>  }
>  EXPORT_SYMBOL_GPL(tpm_do_selftest);
>  
> +/**
> + * tpm1_auto_startup - Perform the standard automatic TPM initialization
> + * sequence
> + * @chip: TPM chip to use
> + *
> + * Returns 0 on success, < 0 in case of fatal error.
> + */
> +int tpm1_auto_startup(struct tpm_chip *chip)
> +{
> + int rc;
> +
> + rc = tpm_get_timeouts(chip);
> + if (rc)
> + goto out;
> + rc = tpm_do_selftest(chip);
> + if (rc) {
> + dev_err(>dev, "TPM self test failed\n");
> + goto out;
> + }
> +
> + return rc;
> +out:
> + if (rc > 0)
> + rc = -ENODEV;
> + return rc;
> +}
> +
>  int tpm_send(u32 chip_num, void *cmd, size_t buflen)
>  {
>   struct tpm_chip *chip;
> diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
> index 28b477e8da6a..a99105f1a5c4 100644
> --- a/drivers/char/tpm/tpm.h
> +++ b/drivers/char/tpm/tpm.h
> @@ -501,6 +501,7 @@ ssize_t tpm_transmit_cmd(struct tpm_chip *chip, void 
> *cmd, int len,
>const char *desc);
>  extern int tpm_get_timeouts(struct tpm_chip *);
>  extern void tpm_gen_interrupt(struct tpm_chip *);
> +int tpm1_auto_startup(struct tpm_chip *chip);
>  extern int tpm_do_selftest(struct tpm_chip *);
>  extern unsigned long tpm_calc_ordinal_duration(struct tpm_chip *, u32);
>  extern int tpm_pm_suspend(struct device *);
> @@ -539,6 +540,7 @@ int tpm2_unseal_trusted(struct tpm_chip *chip,
>  ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id,
>   u32 *value, const char *desc);
>  
> +int tpm2_auto_startup(struct tpm_chip *chip);
>  extern int tpm2_startup(struct tpm_chip *chip, u16 startup_type);
>  extern void tpm2_shutdown(struct tpm_chip *chip, u16 

Re: [PATCH 3.14 00/17] 3.14.70-stable review

[Guenter Roeck]

On 05/16/2016 06:14 PM, Greg Kroah-Hartman wrote:

This is the start of the stable review cycle for the 3.14.70 release.
There are 17 patches in this series, all will be posted as a response
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Thu May 19 01:13:32 UTC 2016.
Anything received after that time might be too late.



Early feedback: Commit 'arm64: Make arch_randomize_brk avoid stack area'
breaks arm64 builds.

arch/arm64/kernel/process.c: In function ‘randomize_et_dyn’:
arch/arm64/kernel/process.c:378:9: error: implicit declaration of function 
‘randomize_base’

Guenter

Re: [PATCH 3.14 00/17] 3.14.70-stable review

[Guenter Roeck]

On 05/16/2016 06:14 PM, Greg Kroah-Hartman wrote:

This is the start of the stable review cycle for the 3.14.70 release.
There are 17 patches in this series, all will be posted as a response
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Thu May 19 01:13:32 UTC 2016.
Anything received after that time might be too late.



Early feedback: Commit 'arm64: Make arch_randomize_brk avoid stack area'
breaks arm64 builds.

arch/arm64/kernel/process.c: In function ‘randomize_et_dyn’:
arch/arm64/kernel/process.c:378:9: error: implicit declaration of function 
‘randomize_base’

Guenter

Re: [PATCH] Staging: comedi: quatech_daqp_cs.c: fixed a warning issue

[Amit Ghadge]

Hello Greg KH,

I make patch same like other, I'm new and I nerver see changelog in other 
patches.

Where to add changelog? I followed you are tutorial.

Thanks,
Amit Ghadge
On Mon, May 16, 2016 at 08:34:55PM -0700, Greg KH wrote:
> 
> A: No.
> Q: Should I include quotations after my reply?
> 
> http://daringfireball.net/2007/07/on_top
> 
> On Tue, May 17, 2016 at 08:55:56AM +0530, Amit Ghadge wrote:
> > I check with "./scripts/checkpatch.pl --file --terse 
> > drivers/staging/comedi/drivers/quatech_daqp_cs.c" and show the warning 
> > message,
> > 
> > drivers/staging/comedi/drivers/quatech_daqp_cs.c:646: WARNING: Prefer 
> > 'unsigned int' to bare use of 'unsigned'
> > 
> > This patch reduced the warning message.
> 
> Why didn't you put that information in the changelog area?
> 
> Please do so.
> 
> greg k-h

Re: [PATCH] Staging: comedi: quatech_daqp_cs.c: fixed a warning issue

[Amit Ghadge]

Hello Greg KH,

I make patch same like other, I'm new and I nerver see changelog in other 
patches.

Where to add changelog? I followed you are tutorial.

Thanks,
Amit Ghadge
On Mon, May 16, 2016 at 08:34:55PM -0700, Greg KH wrote:
> 
> A: No.
> Q: Should I include quotations after my reply?
> 
> http://daringfireball.net/2007/07/on_top
> 
> On Tue, May 17, 2016 at 08:55:56AM +0530, Amit Ghadge wrote:
> > I check with "./scripts/checkpatch.pl --file --terse 
> > drivers/staging/comedi/drivers/quatech_daqp_cs.c" and show the warning 
> > message,
> > 
> > drivers/staging/comedi/drivers/quatech_daqp_cs.c:646: WARNING: Prefer 
> > 'unsigned int' to bare use of 'unsigned'
> > 
> > This patch reduced the warning message.
> 
> Why didn't you put that information in the changelog area?
> 
> Please do so.
> 
> greg k-h

[PATCH 02/10] dma: imx-sdma: don't update BD in isr routine

[Jiada Wang]

commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to tasklet.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1f1b64b..887e4e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -656,12 +656,6 @@ static void sdma_event_disable(struct sdma_channel *sdmac, 
unsigned int event)
 
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
-   if (sdmac->desc.callback)
-   sdmac->desc.callback(sdmac->desc.callback_param);
-}
-
-static void sdma_update_channel_loop(struct sdma_channel *sdmac)
-{
struct sdma_buffer_descriptor *bd;
 
/*
@@ -685,6 +679,9 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
sdmac->chn_real_count = bd->mode.count;
bd->mode.count = sdmac->chn_count;
}
+
+   if (sdmac->desc.callback)
+   sdmac->desc.callback(sdmac->desc.callback_param);
}
 }
 
@@ -740,9 +737,6 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
-   sdma_update_channel_loop(sdmac);
-
tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
-- 
2.4.5

[PATCH 02/10] dma: imx-sdma: don't update BD in isr routine

[Jiada Wang]

commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to tasklet.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1f1b64b..887e4e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -656,12 +656,6 @@ static void sdma_event_disable(struct sdma_channel *sdmac, 
unsigned int event)
 
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
-   if (sdmac->desc.callback)
-   sdmac->desc.callback(sdmac->desc.callback_param);
-}
-
-static void sdma_update_channel_loop(struct sdma_channel *sdmac)
-{
struct sdma_buffer_descriptor *bd;
 
/*
@@ -685,6 +679,9 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
sdmac->chn_real_count = bd->mode.count;
bd->mode.count = sdmac->chn_count;
}
+
+   if (sdmac->desc.callback)
+   sdmac->desc.callback(sdmac->desc.callback_param);
}
 }
 
@@ -740,9 +737,6 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
-   sdma_update_channel_loop(sdmac);
-
tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
-- 
2.4.5

[PATCH v1 00/10] *** imx-sdma: misc fix ***

[Jiada Wang]

this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition

Jiada Wang (10):
  dma: imx-sdma: use chn_real_count to report residue for UART
  dma: imx-sdma: don't update BD in isr routine
  dma: imx-sdma: clear BD_RROR flag before pass it to sdma script
  dma: imx-sdma: update sdma channel status for cyclic dma
  dma: imx-sdma: add flag to indicate SDMA channel state
  dma: imx-sdma: add terminate_all support
  dma: imx-sdma: Add synchronization support
  dma: imx-sdma: abort updating channel when it has been terminated
  dma: imx-sdma: disable channel 0 when it timeouts
  dma: imx-sdma: clear channel0 interrupt bit in irq routine

 drivers/dma/imx-sdma.c | 113 +++--
 1 file changed, 82 insertions(+), 31 deletions(-)

-- 
2.4.5

[PATCH 04/10] dma: imx-sdma: update sdma channel status for cyclic dma

[Jiada Wang]

Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.

This patch updates sdmac status to the status of current buffer descriptor.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1489de0..36f5e39 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -670,6 +670,8 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
+   else
+   sdmac->status = DMA_IN_PROGRESS;
 
bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
-- 
2.4.5

[PATCH 03/10] dma: imx-sdma: clear BD_RROR flag before pass it to sdma script

[Jiada Wang]

Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful, but as BD_RROR flag is set, client side
will still think the transfer failed.

This patch clears BD_RROR flag before pass it to sdma script.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 887e4e5..1489de0 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -671,6 +671,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
 
+   bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
-- 
2.4.5

Re: [RFC][PATCH 5/5] sched/core: Add debug code to catch missing update_rq_clock()

[Yuyang Du]

On Mon, May 16, 2016 at 10:46:38AM +0100, Matt Fleming wrote:
> > >  
> > > - rq->clock_skip_update = 0;
> > > + /* Clear ACT, preserve everything else */
> > > + rq->clock_update_flags ^= RQCF_ACT_SKIP;
> > 
> > The comment says "Clear ACT", but this is really xor, and I am not sure
> > this is even what you want.
>  
> Urgh, you're right. I'm not sure what I was thinking when I wrote
> that.

It happens, ;)
 
> > In addition, would it be simpler to do this?
> > 
> > update_rq_clock()
> > if (flags & RQCF_ACT_SKIP)
> > flags <<= 1; /* effective skip is an update */
> > return;
> > 
> > flags = RQCF_UPDATED;
> 
> No because if someone calls rq_clock() immediately after __schedule(),
> or even immediately after we clear RQCF_ACT_SKIP in __schedule(), we
> should trigger a warning since the clock has not actually been
> updated.

Well, I don't know how concurrent it can be, but aren't both update
and read synchronized by rq->lock? So I don't understand the latter
case, and the former should be addressed (missing its own update?).

[PATCH 04/10] dma: imx-sdma: update sdma channel status for cyclic dma

[Jiada Wang]

Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.

This patch updates sdmac status to the status of current buffer descriptor.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1489de0..36f5e39 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -670,6 +670,8 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
+   else
+   sdmac->status = DMA_IN_PROGRESS;
 
bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
-- 
2.4.5

[PATCH 03/10] dma: imx-sdma: clear BD_RROR flag before pass it to sdma script

[Jiada Wang]

Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful, but as BD_RROR flag is set, client side
will still think the transfer failed.

This patch clears BD_RROR flag before pass it to sdma script.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 887e4e5..1489de0 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -671,6 +671,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
 
+   bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
-- 
2.4.5

Re: [RFC][PATCH 5/5] sched/core: Add debug code to catch missing update_rq_clock()

[Yuyang Du]

On Mon, May 16, 2016 at 10:46:38AM +0100, Matt Fleming wrote:
> > >  
> > > - rq->clock_skip_update = 0;
> > > + /* Clear ACT, preserve everything else */
> > > + rq->clock_update_flags ^= RQCF_ACT_SKIP;
> > 
> > The comment says "Clear ACT", but this is really xor, and I am not sure
> > this is even what you want.
>  
> Urgh, you're right. I'm not sure what I was thinking when I wrote
> that.

It happens, ;)
 
> > In addition, would it be simpler to do this?
> > 
> > update_rq_clock()
> > if (flags & RQCF_ACT_SKIP)
> > flags <<= 1; /* effective skip is an update */
> > return;
> > 
> > flags = RQCF_UPDATED;
> 
> No because if someone calls rq_clock() immediately after __schedule(),
> or even immediately after we clear RQCF_ACT_SKIP in __schedule(), we
> should trigger a warning since the clock has not actually been
> updated.

Well, I don't know how concurrent it can be, but aren't both update
and read synchronized by rq->lock? So I don't understand the latter
case, and the former should be addressed (missing its own update?).

[PATCH v1 00/10] *** imx-sdma: misc fix ***

[Jiada Wang]

this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition

Jiada Wang (10):
  dma: imx-sdma: use chn_real_count to report residue for UART
  dma: imx-sdma: don't update BD in isr routine
  dma: imx-sdma: clear BD_RROR flag before pass it to sdma script
  dma: imx-sdma: update sdma channel status for cyclic dma
  dma: imx-sdma: add flag to indicate SDMA channel state
  dma: imx-sdma: add terminate_all support
  dma: imx-sdma: Add synchronization support
  dma: imx-sdma: abort updating channel when it has been terminated
  dma: imx-sdma: disable channel 0 when it timeouts
  dma: imx-sdma: clear channel0 interrupt bit in irq routine

 drivers/dma/imx-sdma.c | 113 +++--
 1 file changed, 82 insertions(+), 31 deletions(-)

-- 
2.4.5

[PATCH 09/10] dma: imx-sdma: disable channel 0 when it timeouts

[Jiada Wang]

Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 43 ++-
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index bc867e5..8b20bf4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -572,6 +572,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, 
int channel)
spin_unlock_irqrestore(>lock, flags);
 }
 
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+   return container_of(chan, struct sdma_channel, chan);
+}
+
+static int sdma_disable_channel(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+   struct sdma_engine *sdma = sdmac->sdma;
+   int channel = sdmac->channel;
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
+   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
+   sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
 /*
  * sdma_run_channel0 - run a channel and wait till it's done
  */
@@ -592,6 +613,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
/* Clear the interrupt status */
writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
} else {
+   sdma_disable_channel(>channel[0].chan);
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
}
 
@@ -916,27 +938,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
return ret;
 }
 
-static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
-{
-   return container_of(chan, struct sdma_channel, chan);
-}
-
-static int sdma_disable_channel(struct dma_chan *chan)
-{
-   struct sdma_channel *sdmac = to_sdma_chan(chan);
-   struct sdma_engine *sdma = sdmac->sdma;
-   int channel = sdmac->channel;
-   unsigned long flags;
-
-   spin_lock_irqsave(>lock, flags);
-   sdmac->enabled = false;
-   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
-   sdmac->status = DMA_ERROR;
-   spin_unlock_irqrestore(>lock, flags);
-
-   return 0;
-}
-
 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 {
struct sdma_engine *sdma = sdmac->sdma;
-- 
2.4.5

[PATCH 06/10] dma: imx-sdma: add terminate_all support

[Jiada Wang]

Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1401,6 +1401,13 @@ static void sdma_issue_pending(struct dma_chan *chan)
sdma_enable_channel(sdma, sdmac->channel);
 }
 
+static int sdma_terminate_all(struct dma_chan *chan)
+{
+   sdma_disable_channel(chan);
+
+   return 0;
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1819,6 +1826,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
+   sdma->dma_device.device_terminate_all = sdma_terminate_all;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH 09/10] dma: imx-sdma: disable channel 0 when it timeouts

[Jiada Wang]

Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 43 ++-
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index bc867e5..8b20bf4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -572,6 +572,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, 
int channel)
spin_unlock_irqrestore(>lock, flags);
 }
 
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+   return container_of(chan, struct sdma_channel, chan);
+}
+
+static int sdma_disable_channel(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+   struct sdma_engine *sdma = sdmac->sdma;
+   int channel = sdmac->channel;
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
+   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
+   sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
 /*
  * sdma_run_channel0 - run a channel and wait till it's done
  */
@@ -592,6 +613,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
/* Clear the interrupt status */
writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
} else {
+   sdma_disable_channel(>channel[0].chan);
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
}
 
@@ -916,27 +938,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
return ret;
 }
 
-static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
-{
-   return container_of(chan, struct sdma_channel, chan);
-}
-
-static int sdma_disable_channel(struct dma_chan *chan)
-{
-   struct sdma_channel *sdmac = to_sdma_chan(chan);
-   struct sdma_engine *sdma = sdmac->sdma;
-   int channel = sdmac->channel;
-   unsigned long flags;
-
-   spin_lock_irqsave(>lock, flags);
-   sdmac->enabled = false;
-   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
-   sdmac->status = DMA_ERROR;
-   spin_unlock_irqrestore(>lock, flags);
-
-   return 0;
-}
-
 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 {
struct sdma_engine *sdma = sdmac->sdma;
-- 
2.4.5

[PATCH 06/10] dma: imx-sdma: add terminate_all support

[Jiada Wang]

Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1401,6 +1401,13 @@ static void sdma_issue_pending(struct dma_chan *chan)
sdma_enable_channel(sdma, sdmac->channel);
 }
 
+static int sdma_terminate_all(struct dma_chan *chan)
+{
+   sdma_disable_channel(chan);
+
+   return 0;
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1819,6 +1826,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
+   sdma->dma_device.device_terminate_all = sdma_terminate_all;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH 01/10] dma: imx-sdma: use chn_real_count to report residue for UART

[Jiada Wang]

For uart rx dma data may not receive fully, so the number
of data read by sdma script once isn't always equal to period_len,
thus residue returned from sdma_tx_status() isn't valid for uart rx
dma. The old way to use chn_real_count to report residue should be
used for uart rx dma.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 0f6fd42..1f1b64b 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -680,6 +680,11 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
+   if (sdmac->peripheral_type == IMX_DMATYPE_UART) {
+   /* restore mode.count after counter readed */
+   sdmac->chn_real_count = bd->mode.count;
+   bd->mode.count = sdmac->chn_count;
+   }
}
 }
 
@@ -1285,6 +1290,9 @@ static struct dma_async_tx_descriptor 
*sdma_prep_dma_cyclic(
goto err_out;
}
 
+   if (sdmac->peripheral_type == IMX_DMATYPE_UART)
+   sdmac->chn_count = period_len;
+
while (buf < buf_len) {
struct sdma_buffer_descriptor *bd = >bd[i];
int param;
@@ -1361,7 +1369,8 @@ static enum dma_status sdma_tx_status(struct dma_chan 
*chan,
struct sdma_channel *sdmac = to_sdma_chan(chan);
u32 residue;
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
+   if ((sdmac->flags & IMX_DMA_SG_LOOP) &&
+   (sdmac->peripheral_type != IMX_DMATYPE_UART))
residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
else
residue = sdmac->chn_count - sdmac->chn_real_count;
-- 
2.4.5

[PATCH 01/10] dma: imx-sdma: use chn_real_count to report residue for UART

[Jiada Wang]

For uart rx dma data may not receive fully, so the number
of data read by sdma script once isn't always equal to period_len,
thus residue returned from sdma_tx_status() isn't valid for uart rx
dma. The old way to use chn_real_count to report residue should be
used for uart rx dma.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 0f6fd42..1f1b64b 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -680,6 +680,11 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
+   if (sdmac->peripheral_type == IMX_DMATYPE_UART) {
+   /* restore mode.count after counter readed */
+   sdmac->chn_real_count = bd->mode.count;
+   bd->mode.count = sdmac->chn_count;
+   }
}
 }
 
@@ -1285,6 +1290,9 @@ static struct dma_async_tx_descriptor 
*sdma_prep_dma_cyclic(
goto err_out;
}
 
+   if (sdmac->peripheral_type == IMX_DMATYPE_UART)
+   sdmac->chn_count = period_len;
+
while (buf < buf_len) {
struct sdma_buffer_descriptor *bd = >bd[i];
int param;
@@ -1361,7 +1369,8 @@ static enum dma_status sdma_tx_status(struct dma_chan 
*chan,
struct sdma_channel *sdmac = to_sdma_chan(chan);
u32 residue;
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
+   if ((sdmac->flags & IMX_DMA_SG_LOOP) &&
+   (sdmac->peripheral_type != IMX_DMATYPE_UART))
residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
else
residue = sdmac->chn_count - sdmac->chn_real_count;
-- 
2.4.5

[PATCH 04/10] dma: imx-sdma: update sdma channel status for cyclic dma

[Jiada Wang]

Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.

This patch updates sdmac status to the status of current buffer descriptor.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1489de0..36f5e39 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -670,6 +670,8 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
+   else
+   sdmac->status = DMA_IN_PROGRESS;
 
bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
-- 
2.4.5

[PATCH 05/10] dma: imx-sdma: add flag to indicate SDMA channel state

[Jiada Wang]

There is race between STOP of SDMA channel and finish of
SDMA transfer, so some times, even after sdma_disable_channel()
is called, the bit of 'terminated channel' in INTR may still get
asserted, thus cause an extra sdma tasklet be called.
Add flag 'enabled' to each sdma channel to indicate its state.
only when SDMA channel is in its enabled state, irq handler
can schedule a sdma tasklet for it.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 36f5e39..ef5d37c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -327,6 +327,7 @@ struct sdma_channel {
unsigned intchn_real_count;
struct tasklet_struct   tasklet;
struct imx_dma_data data;
+   boolenabled;
 };
 
 #define IMX_DMA_SG_LOOPBIT(0)
@@ -562,7 +563,13 @@ static int sdma_config_ownership(struct sdma_channel 
*sdmac,
 
 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 {
+   struct sdma_channel *sdmac = >channel[channel];
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = true;
writel(BIT(channel), sdma->regs + SDMA_H_START);
+   spin_unlock_irqrestore(>lock, flags);
 }
 
 /*
@@ -740,9 +747,12 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   tasklet_schedule(>tasklet);
+   spin_lock(>lock);
+   if (sdmac->enabled)
+   tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
+   spin_unlock(>lock);
}
 
return IRQ_HANDLED;
@@ -906,9 +916,13 @@ static int sdma_disable_channel(struct dma_chan *chan)
struct sdma_channel *sdmac = to_sdma_chan(chan);
struct sdma_engine *sdma = sdmac->sdma;
int channel = sdmac->channel;
+   unsigned long flags;
 
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
 
return 0;
 }
-- 
2.4.5

[PATCH 04/10] dma: imx-sdma: update sdma channel status for cyclic dma

[Jiada Wang]

Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.

This patch updates sdmac status to the status of current buffer descriptor.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1489de0..36f5e39 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -670,6 +670,8 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
+   else
+   sdmac->status = DMA_IN_PROGRESS;
 
bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
-- 
2.4.5

[PATCH 05/10] dma: imx-sdma: add flag to indicate SDMA channel state

[Jiada Wang]

There is race between STOP of SDMA channel and finish of
SDMA transfer, so some times, even after sdma_disable_channel()
is called, the bit of 'terminated channel' in INTR may still get
asserted, thus cause an extra sdma tasklet be called.
Add flag 'enabled' to each sdma channel to indicate its state.
only when SDMA channel is in its enabled state, irq handler
can schedule a sdma tasklet for it.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 36f5e39..ef5d37c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -327,6 +327,7 @@ struct sdma_channel {
unsigned intchn_real_count;
struct tasklet_struct   tasklet;
struct imx_dma_data data;
+   boolenabled;
 };
 
 #define IMX_DMA_SG_LOOPBIT(0)
@@ -562,7 +563,13 @@ static int sdma_config_ownership(struct sdma_channel 
*sdmac,
 
 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 {
+   struct sdma_channel *sdmac = >channel[channel];
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = true;
writel(BIT(channel), sdma->regs + SDMA_H_START);
+   spin_unlock_irqrestore(>lock, flags);
 }
 
 /*
@@ -740,9 +747,12 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   tasklet_schedule(>tasklet);
+   spin_lock(>lock);
+   if (sdmac->enabled)
+   tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
+   spin_unlock(>lock);
}
 
return IRQ_HANDLED;
@@ -906,9 +916,13 @@ static int sdma_disable_channel(struct dma_chan *chan)
struct sdma_channel *sdmac = to_sdma_chan(chan);
struct sdma_engine *sdma = sdmac->sdma;
int channel = sdmac->channel;
+   unsigned long flags;
 
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
 
return 0;
 }
-- 
2.4.5

[PATCH 03/10] dma: imx-sdma: clear BD_RROR flag before pass it to sdma script

[Jiada Wang]

Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful, but as BD_RROR flag is set, client side
will still think the transfer failed.

This patch clears BD_RROR flag before pass it to sdma script.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 887e4e5..1489de0 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -671,6 +671,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
 
+   bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
-- 
2.4.5

[PATCH 02/10] dma: imx-sdma: don't update BD in isr routine

[Jiada Wang]

commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to tasklet.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1f1b64b..887e4e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -656,12 +656,6 @@ static void sdma_event_disable(struct sdma_channel *sdmac, 
unsigned int event)
 
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
-   if (sdmac->desc.callback)
-   sdmac->desc.callback(sdmac->desc.callback_param);
-}
-
-static void sdma_update_channel_loop(struct sdma_channel *sdmac)
-{
struct sdma_buffer_descriptor *bd;
 
/*
@@ -685,6 +679,9 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
sdmac->chn_real_count = bd->mode.count;
bd->mode.count = sdmac->chn_count;
}
+
+   if (sdmac->desc.callback)
+   sdmac->desc.callback(sdmac->desc.callback_param);
}
 }
 
@@ -740,9 +737,6 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
-   sdma_update_channel_loop(sdmac);
-
tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
-- 
2.4.5

[PATCH 03/10] dma: imx-sdma: clear BD_RROR flag before pass it to sdma script

[Jiada Wang]

Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful, but as BD_RROR flag is set, client side
will still think the transfer failed.

This patch clears BD_RROR flag before pass it to sdma script.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 887e4e5..1489de0 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -671,6 +671,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
 
+   bd->mode.status &= ~BD_RROR;
bd->mode.status |= BD_DONE;
sdmac->buf_tail++;
sdmac->buf_tail %= sdmac->num_bd;
-- 
2.4.5

[PATCH 02/10] dma: imx-sdma: don't update BD in isr routine

[Jiada Wang]

commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to tasklet.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1f1b64b..887e4e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -656,12 +656,6 @@ static void sdma_event_disable(struct sdma_channel *sdmac, 
unsigned int event)
 
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
-   if (sdmac->desc.callback)
-   sdmac->desc.callback(sdmac->desc.callback_param);
-}
-
-static void sdma_update_channel_loop(struct sdma_channel *sdmac)
-{
struct sdma_buffer_descriptor *bd;
 
/*
@@ -685,6 +679,9 @@ static void sdma_update_channel_loop(struct sdma_channel 
*sdmac)
sdmac->chn_real_count = bd->mode.count;
bd->mode.count = sdmac->chn_count;
}
+
+   if (sdmac->desc.callback)
+   sdmac->desc.callback(sdmac->desc.callback_param);
}
 }
 
@@ -740,9 +737,6 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = >channel[channel];
 
-   if (sdmac->flags & IMX_DMA_SG_LOOP)
-   sdma_update_channel_loop(sdmac);
-
tasklet_schedule(>tasklet);
 
__clear_bit(channel, );
-- 
2.4.5

[PATCH 08/10] dma: imx-sdma: abort updating channel when it has been terminated

[Jiada Wang]

In case the corresponding channel has already been terminated,
then instead of go on updating channel status, driver should abort from
sdma_handle_channel_loop(), otherwise channel status will be updated
incorrecly.

This patch also adds lock to avoid race between terminate of channel,
and updaing of channel status in sdma_handle_channel_loop().

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 0b23407..bc867e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -664,16 +664,25 @@ static void sdma_event_disable(struct sdma_channel 
*sdmac, unsigned int event)
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
struct sdma_buffer_descriptor *bd;
+   unsigned long flags;
 
/*
 * loop mode. Iterate over descriptors, re-setup them and
 * call callback function.
 */
while (1) {
+   spin_lock_irqsave(>lock, flags);
+   if (!sdmac->enabled) {
+   spin_unlock_irqrestore(>lock, flags);
+   break;
+   }
+
bd = >bd[sdmac->buf_tail];
 
-   if (bd->mode.status & BD_DONE)
+   if (bd->mode.status & BD_DONE) {
+   spin_unlock_irqrestore(>lock, flags);
break;
+   }
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
@@ -690,6 +699,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
bd->mode.count = sdmac->chn_count;
}
 
+   spin_unlock_irqrestore(>lock, flags);
if (sdmac->desc.callback)
sdmac->desc.callback(sdmac->desc.callback_param);
}
-- 
2.4.5

[PATCH 09/10] dma: imx-sdma: disable channel 0 when it timeouts

[Jiada Wang]

Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 43 ++-
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index bc867e5..8b20bf4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -572,6 +572,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, 
int channel)
spin_unlock_irqrestore(>lock, flags);
 }
 
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+   return container_of(chan, struct sdma_channel, chan);
+}
+
+static int sdma_disable_channel(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+   struct sdma_engine *sdma = sdmac->sdma;
+   int channel = sdmac->channel;
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
+   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
+   sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
 /*
  * sdma_run_channel0 - run a channel and wait till it's done
  */
@@ -592,6 +613,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
/* Clear the interrupt status */
writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
} else {
+   sdma_disable_channel(>channel[0].chan);
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
}
 
@@ -916,27 +938,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
return ret;
 }
 
-static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
-{
-   return container_of(chan, struct sdma_channel, chan);
-}
-
-static int sdma_disable_channel(struct dma_chan *chan)
-{
-   struct sdma_channel *sdmac = to_sdma_chan(chan);
-   struct sdma_engine *sdma = sdmac->sdma;
-   int channel = sdmac->channel;
-   unsigned long flags;
-
-   spin_lock_irqsave(>lock, flags);
-   sdmac->enabled = false;
-   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
-   sdmac->status = DMA_ERROR;
-   spin_unlock_irqrestore(>lock, flags);
-
-   return 0;
-}
-
 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 {
struct sdma_engine *sdma = sdmac->sdma;
-- 
2.4.5

[PATCH 08/10] dma: imx-sdma: abort updating channel when it has been terminated

[Jiada Wang]

In case the corresponding channel has already been terminated,
then instead of go on updating channel status, driver should abort from
sdma_handle_channel_loop(), otherwise channel status will be updated
incorrecly.

This patch also adds lock to avoid race between terminate of channel,
and updaing of channel status in sdma_handle_channel_loop().

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 0b23407..bc867e5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -664,16 +664,25 @@ static void sdma_event_disable(struct sdma_channel 
*sdmac, unsigned int event)
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 {
struct sdma_buffer_descriptor *bd;
+   unsigned long flags;
 
/*
 * loop mode. Iterate over descriptors, re-setup them and
 * call callback function.
 */
while (1) {
+   spin_lock_irqsave(>lock, flags);
+   if (!sdmac->enabled) {
+   spin_unlock_irqrestore(>lock, flags);
+   break;
+   }
+
bd = >bd[sdmac->buf_tail];
 
-   if (bd->mode.status & BD_DONE)
+   if (bd->mode.status & BD_DONE) {
+   spin_unlock_irqrestore(>lock, flags);
break;
+   }
 
if (bd->mode.status & BD_RROR)
sdmac->status = DMA_ERROR;
@@ -690,6 +699,7 @@ static void sdma_handle_channel_loop(struct sdma_channel 
*sdmac)
bd->mode.count = sdmac->chn_count;
}
 
+   spin_unlock_irqrestore(>lock, flags);
if (sdmac->desc.callback)
sdmac->desc.callback(sdmac->desc.callback_param);
}
-- 
2.4.5

[PATCH 09/10] dma: imx-sdma: disable channel 0 when it timeouts

[Jiada Wang]

Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 43 ++-
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index bc867e5..8b20bf4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -572,6 +572,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, 
int channel)
spin_unlock_irqrestore(>lock, flags);
 }
 
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+   return container_of(chan, struct sdma_channel, chan);
+}
+
+static int sdma_disable_channel(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+   struct sdma_engine *sdma = sdmac->sdma;
+   int channel = sdmac->channel;
+   unsigned long flags;
+
+   spin_lock_irqsave(>lock, flags);
+   sdmac->enabled = false;
+   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
+   sdmac->status = DMA_ERROR;
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
 /*
  * sdma_run_channel0 - run a channel and wait till it's done
  */
@@ -592,6 +613,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
/* Clear the interrupt status */
writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
} else {
+   sdma_disable_channel(>channel[0].chan);
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
}
 
@@ -916,27 +938,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
return ret;
 }
 
-static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
-{
-   return container_of(chan, struct sdma_channel, chan);
-}
-
-static int sdma_disable_channel(struct dma_chan *chan)
-{
-   struct sdma_channel *sdmac = to_sdma_chan(chan);
-   struct sdma_engine *sdma = sdmac->sdma;
-   int channel = sdmac->channel;
-   unsigned long flags;
-
-   spin_lock_irqsave(>lock, flags);
-   sdmac->enabled = false;
-   writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
-   sdmac->status = DMA_ERROR;
-   spin_unlock_irqrestore(>lock, flags);
-
-   return 0;
-}
-
 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 {
struct sdma_engine *sdma = sdmac->sdma;
-- 
2.4.5

[PATCH 10/10] dma: imx-sdma: clear channel0 interrupt bit in irq routine

[Jiada Wang]

When SDMA channel0 timeouts, even it's disabled in error path,
but sometimes we still see its interrupt bit be asserted,
which causes irq routine be triggered continuously because
no one else clears this bit.

This commit clears channel0 interrupt as well in irq routine,
so that even channel0 timeouts, it won't cause irq storm,
also adds lock to prevent irq routine to clear this bit when
sdma_run_channel0() is busy checking it.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8b20bf4..ca1c984 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -768,12 +768,16 @@ static void sdma_tasklet(unsigned long data)
 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 {
struct sdma_engine *sdma = dev_id;
-   unsigned long stat;
+   unsigned long stat, flags;
+
+   spin_lock_irqsave(>channel_0_lock, flags);
 
stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
+   writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
/* not interested in channel 0 interrupts */
stat &= ~1;
-   writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
+
+   spin_unlock_irqrestore(>channel_0_lock, flags);
 
while (stat) {
int channel = fls(stat) - 1;
-- 
2.4.5

[PATCH 10/10] dma: imx-sdma: clear channel0 interrupt bit in irq routine

[Jiada Wang]

When SDMA channel0 timeouts, even it's disabled in error path,
but sometimes we still see its interrupt bit be asserted,
which causes irq routine be triggered continuously because
no one else clears this bit.

This commit clears channel0 interrupt as well in irq routine,
so that even channel0 timeouts, it won't cause irq storm,
also adds lock to prevent irq routine to clear this bit when
sdma_run_channel0() is busy checking it.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8b20bf4..ca1c984 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -768,12 +768,16 @@ static void sdma_tasklet(unsigned long data)
 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 {
struct sdma_engine *sdma = dev_id;
-   unsigned long stat;
+   unsigned long stat, flags;
+
+   spin_lock_irqsave(>channel_0_lock, flags);
 
stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
+   writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
/* not interested in channel 0 interrupts */
stat &= ~1;
-   writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
+
+   spin_unlock_irqrestore(>channel_0_lock, flags);
 
while (stat) {
int channel = fls(stat) - 1;
-- 
2.4.5

[PATCH 07/10] dma: imx-sdma: Add synchronization support

[Jiada Wang]

Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait for all currently running complete
callbacks to finish.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 040cbf2..0b23407 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1408,6 +1408,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
return 0;
 }
 
+static void sdma_synchronize(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+
+   tasklet_kill(>tasklet);
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1827,6 +1834,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
sdma->dma_device.device_terminate_all = sdma_terminate_all;
+   sdma->dma_device.device_synchronize = sdma_synchronize;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH 06/10] dma: imx-sdma: add terminate_all support

[Jiada Wang]

Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1401,6 +1401,13 @@ static void sdma_issue_pending(struct dma_chan *chan)
sdma_enable_channel(sdma, sdmac->channel);
 }
 
+static int sdma_terminate_all(struct dma_chan *chan)
+{
+   sdma_disable_channel(chan);
+
+   return 0;
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1819,6 +1826,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
+   sdma->dma_device.device_terminate_all = sdma_terminate_all;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH 07/10] dma: imx-sdma: Add synchronization support

[Jiada Wang]

Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait for all currently running complete
callbacks to finish.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 040cbf2..0b23407 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1408,6 +1408,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
return 0;
 }
 
+static void sdma_synchronize(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+
+   tasklet_kill(>tasklet);
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1827,6 +1834,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
sdma->dma_device.device_terminate_all = sdma_terminate_all;
+   sdma->dma_device.device_synchronize = sdma_synchronize;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH 06/10] dma: imx-sdma: add terminate_all support

[Jiada Wang]

Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1401,6 +1401,13 @@ static void sdma_issue_pending(struct dma_chan *chan)
sdma_enable_channel(sdma, sdmac->channel);
 }
 
+static int sdma_terminate_all(struct dma_chan *chan)
+{
+   sdma_disable_channel(chan);
+
+   return 0;
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1819,6 +1826,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
+   sdma->dma_device.device_terminate_all = sdma_terminate_all;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5

[PATCH v1 00/10] *** imx-sdma: misc fix ***

[Jiada Wang]

this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition

Jiada Wang (10):
  dma: imx-sdma: use chn_real_count to report residue for UART
  dma: imx-sdma: don't update BD in isr routine
  dma: imx-sdma: clear BD_RROR flag before pass it to sdma script
  dma: imx-sdma: update sdma channel status for cyclic dma
  dma: imx-sdma: add flag to indicate SDMA channel state
  dma: imx-sdma: add terminate_all support
  dma: imx-sdma: Add synchronization support
  dma: imx-sdma: abort updating channel when it has been terminated
  dma: imx-sdma: disable channel 0 when it timeouts
  dma: imx-sdma: clear channel0 interrupt bit in irq routine

 drivers/dma/imx-sdma.c | 113 +++--
 1 file changed, 82 insertions(+), 31 deletions(-)

-- 
2.4.5

[PATCH 07/10] dma: imx-sdma: Add synchronization support

[Jiada Wang]

Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait for all currently running complete
callbacks to finish.

Signed-off-by: Jiada Wang 
---
 drivers/dma/imx-sdma.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 040cbf2..0b23407 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1408,6 +1408,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
return 0;
 }
 
+static void sdma_synchronize(struct dma_chan *chan)
+{
+   struct sdma_channel *sdmac = to_sdma_chan(chan);
+
+   tasklet_kill(>tasklet);
+}
+
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V134
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V238
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V341
@@ -1827,6 +1834,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
sdma->dma_device.device_issue_pending = sdma_issue_pending;
sdma->dma_device.device_terminate_all = sdma_terminate_all;
+   sdma->dma_device.device_synchronize = sdma_synchronize;
sdma->dma_device.dev->dma_parms = >dma_parms;
dma_set_max_seg_size(sdma->dma_device.dev, 65535);
 
-- 
2.4.5