[PATCH v2 1/4] net: macb: Add support for PTP timestamps in DMA descriptors

[Rafal Ozieblo]

This patch adds support for PTP timestamps in
DMA buffer descriptors. It checks capability at runtime
and uses appropriate buffer descriptor.

Signed-off-by: Rafal Ozieblo 
---
 drivers/net/ethernet/cadence/Kconfig |  10 ++-
 drivers/net/ethernet/cadence/macb.c  | 117 ++-
 drivers/net/ethernet/cadence/macb.h  |  32 +++---
 3 files changed, 122 insertions(+), 37 deletions(-)

diff --git a/drivers/net/ethernet/cadence/Kconfig 
b/drivers/net/ethernet/cadence/Kconfig
index 608bea1..427d65a 100644
--- a/drivers/net/ethernet/cadence/Kconfig
+++ b/drivers/net/ethernet/cadence/Kconfig
@@ -29,7 +29,15 @@ config MACB
  support for the MACB/GEM chip.
 
  To compile this driver as a module, choose M here: the module
- will be called macb.
+ will be macb.
+
+config MACB_USE_HWSTAMP
+   bool "Use IEEE 1588 hwstamp"
+   depends on MACB
+   default y
+   imply PTP_1588_CLOCK
+   ---help---
+ Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.
 
 config MACB_PCI
tristate "Cadence PCI MACB/GEM support"
diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index 91f7492..3151429 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -79,33 +79,84 @@
 #define MACB_HALT_TIMEOUT  1230
 
 /* DMA buffer descriptor might be different size
- * depends on hardware configuration.
+ * depends on hardware configuration:
+ *
+ * 1. dma address width 32 bits:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *
+ * 2. dma address width 64 bits:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: upper 32 bit address of Data Buffer
+ *word 4: unused
+ *
+ * 3. dma address width 32 bits with hardware timestamping:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: timestamp word 1
+ *word 4: timestamp word 2
+ *
+ * 4. dma address width 64 bits with hardware timestamping:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: upper 32 bit address of Data Buffer
+ *word 4: unused
+ *word 5: timestamp word 1
+ *word 6: timestamp word 2
  */
 static unsigned int macb_dma_desc_get_size(struct macb *bp)
 {
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B)
-   return sizeof(struct macb_dma_desc) + sizeof(struct 
macb_dma_desc_64);
+#ifdef MACB_EXT_DESC
+   unsigned int desc_size;
+
+   switch (bp->hw_dma_cap) {
+   case HW_DMA_CAP_64B:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_64);
+   break;
+   case HW_DMA_CAP_PTP:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_ptp);
+   break;
+   case HW_DMA_CAP_64B_PTP:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_64)
+   + sizeof(struct macb_dma_desc_ptp);
+   break;
+   default:
+   desc_size = sizeof(struct macb_dma_desc);
+   }
+   return desc_size;
 #endif
return sizeof(struct macb_dma_desc);
 }
 
-static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int idx)
+static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int 
desc_idx)
 {
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-   /* Dma buffer descriptor is 4 words length (instead of 2 words)
-* for 64b GEM.
-*/
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B)
-   idx <<= 1;
+#ifdef MACB_EXT_DESC
+   switch (bp->hw_dma_cap) {
+   case HW_DMA_CAP_64B:
+   case HW_DMA_CAP_PTP:
+   desc_idx <<= 1;
+   break;
+   case HW_DMA_CAP_64B_PTP:
+   desc_idx *= 3;
+   break;
+   default:
+   break;
+   }
+   return desc_idx;
 #endif
-   return idx;
+   return desc_idx;
 }
 
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct 
macb_dma_desc *desc)
 {
-   return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct 
macb_dma_desc));
+   if (bp->hw_dma_cap & HW_DMA_CAP_64B)
+   return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct 
macb_dma_desc));
+   return NULL;
 }
 #endif
 
@@ -602,7 +653,7 @@ static void macb_set_addr(struct macb *bp, struct 
macb_dma_desc *desc, dma_addr_
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
struct macb_dma_desc_64 *desc_64;
 
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B) {
+   if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
desc_64 = macb_64b_desc(bp, desc);
desc_64->addrh = upper_32_bits(addr);
}
@@ -616,7 +667,7 @@ static dma_addr_t macb_get_addr(struct macb *bp, struct 

[PATCH v2 1/4] net: macb: Add support for PTP timestamps in DMA descriptors

[Rafal Ozieblo]

This patch adds support for PTP timestamps in
DMA buffer descriptors. It checks capability at runtime
and uses appropriate buffer descriptor.

Signed-off-by: Rafal Ozieblo 
---
 drivers/net/ethernet/cadence/Kconfig |  10 ++-
 drivers/net/ethernet/cadence/macb.c  | 117 ++-
 drivers/net/ethernet/cadence/macb.h  |  32 +++---
 3 files changed, 122 insertions(+), 37 deletions(-)

diff --git a/drivers/net/ethernet/cadence/Kconfig 
b/drivers/net/ethernet/cadence/Kconfig
index 608bea1..427d65a 100644
--- a/drivers/net/ethernet/cadence/Kconfig
+++ b/drivers/net/ethernet/cadence/Kconfig
@@ -29,7 +29,15 @@ config MACB
  support for the MACB/GEM chip.
 
  To compile this driver as a module, choose M here: the module
- will be called macb.
+ will be macb.
+
+config MACB_USE_HWSTAMP
+   bool "Use IEEE 1588 hwstamp"
+   depends on MACB
+   default y
+   imply PTP_1588_CLOCK
+   ---help---
+ Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.
 
 config MACB_PCI
tristate "Cadence PCI MACB/GEM support"
diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index 91f7492..3151429 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -79,33 +79,84 @@
 #define MACB_HALT_TIMEOUT  1230
 
 /* DMA buffer descriptor might be different size
- * depends on hardware configuration.
+ * depends on hardware configuration:
+ *
+ * 1. dma address width 32 bits:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *
+ * 2. dma address width 64 bits:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: upper 32 bit address of Data Buffer
+ *word 4: unused
+ *
+ * 3. dma address width 32 bits with hardware timestamping:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: timestamp word 1
+ *word 4: timestamp word 2
+ *
+ * 4. dma address width 64 bits with hardware timestamping:
+ *word 1: 32 bit address of Data Buffer
+ *word 2: control
+ *word 3: upper 32 bit address of Data Buffer
+ *word 4: unused
+ *word 5: timestamp word 1
+ *word 6: timestamp word 2
  */
 static unsigned int macb_dma_desc_get_size(struct macb *bp)
 {
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B)
-   return sizeof(struct macb_dma_desc) + sizeof(struct 
macb_dma_desc_64);
+#ifdef MACB_EXT_DESC
+   unsigned int desc_size;
+
+   switch (bp->hw_dma_cap) {
+   case HW_DMA_CAP_64B:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_64);
+   break;
+   case HW_DMA_CAP_PTP:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_ptp);
+   break;
+   case HW_DMA_CAP_64B_PTP:
+   desc_size = sizeof(struct macb_dma_desc)
+   + sizeof(struct macb_dma_desc_64)
+   + sizeof(struct macb_dma_desc_ptp);
+   break;
+   default:
+   desc_size = sizeof(struct macb_dma_desc);
+   }
+   return desc_size;
 #endif
return sizeof(struct macb_dma_desc);
 }
 
-static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int idx)
+static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int 
desc_idx)
 {
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-   /* Dma buffer descriptor is 4 words length (instead of 2 words)
-* for 64b GEM.
-*/
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B)
-   idx <<= 1;
+#ifdef MACB_EXT_DESC
+   switch (bp->hw_dma_cap) {
+   case HW_DMA_CAP_64B:
+   case HW_DMA_CAP_PTP:
+   desc_idx <<= 1;
+   break;
+   case HW_DMA_CAP_64B_PTP:
+   desc_idx *= 3;
+   break;
+   default:
+   break;
+   }
+   return desc_idx;
 #endif
-   return idx;
+   return desc_idx;
 }
 
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct 
macb_dma_desc *desc)
 {
-   return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct 
macb_dma_desc));
+   if (bp->hw_dma_cap & HW_DMA_CAP_64B)
+   return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct 
macb_dma_desc));
+   return NULL;
 }
 #endif
 
@@ -602,7 +653,7 @@ static void macb_set_addr(struct macb *bp, struct 
macb_dma_desc *desc, dma_addr_
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
struct macb_dma_desc_64 *desc_64;
 
-   if (bp->hw_dma_cap == HW_DMA_CAP_64B) {
+   if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
desc_64 = macb_64b_desc(bp, desc);
desc_64->addrh = upper_32_bits(addr);
}
@@ -616,7 +667,7 @@ static dma_addr_t macb_get_addr(struct macb *bp, struct 
macb_dma_desc *desc)
 #ifdef 

[PATCH v2 01/11] pinctrl: dt-bindings: add documentation for AP806 pin controllers

[Gregory CLEMENT]

Document the device tree binding for the pin controllers found on the
Armada 7K and Armada 8K SoCs.

Acked-by: Rob Herring 
Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 53 
++---
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt 
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 888c50e0d64f..4228d158fb31 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -28,14 +28,53 @@ Required properties:
  - compatible: must be: "marvell,ap806-clock"
  - #clock-cells: must be set to 1
 
+Pinctrl:
+
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+- compatible must be "marvell,ap806-pinctrl",
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name   pinsfunctions
+
+mpp0   0   gpio, sdio(clk), spi0(clk)
+mpp1   1   gpio, sdio(cmd), spi0(miso)
+mpp2   2   gpio, sdio(d0), spi0(mosi)
+mpp3   3   gpio, sdio(d1), spi0(cs0n)
+mpp4   4   gpio, sdio(d2), i2c0(sda)
+mpp5   5   gpio, sdio(d3), i2c0(sdk)
+mpp6   6   gpio, sdio(ds)
+mpp7   7   gpio, sdio(d4), uart1(rxd)
+mpp8   8   gpio, sdio(d5), uart1(txd)
+mpp9   9   gpio, sdio(d6), spi0(cs1n)
+mpp10  10  gpio, sdio(d7)
+mpp11  11  gpio, uart0(txd)
+mpp12  12  gpio, sdio(pw_off), sdio(hw_rst)
+mpp13  13  gpio
+mpp14  14  gpio
+mpp15  15  gpio
+mpp16  16  gpio
+mpp17  17  gpio
+mpp18  18  gpio
+mpp19  19  gpio, uart0(rxd), sdio(pw_off)
+
 Example:
+ap_syscon: system-controller@6f4000 {
+   compatible = "syscon", "simple-mfd";
+   reg = <0x6f4000 0x1000>;
 
-   syscon: system-controller@6f4000 {
-   compatible = "syscon", "simple-mfd";
-   reg = <0x6f4000 0x1000>;
+   ap_clk: clock {
+   compatible = "marvell,ap806-clock";
+   #clock-cells = <1>;
+   };
 
-   ap_clk: clock {
-   compatible = "marvell,ap806-clock";
-   #clock-cells = <1>;
-   };
+   ap_pinctrl: pinctrl {
+   compatible = "marvell,ap806-pinctrl";
};
+};
-- 
git-series 0.9.1

[PATCH v2 01/11] pinctrl: dt-bindings: add documentation for AP806 pin controllers

[Gregory CLEMENT]

Document the device tree binding for the pin controllers found on the
Armada 7K and Armada 8K SoCs.

Acked-by: Rob Herring 
Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 53 
++---
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt 
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 888c50e0d64f..4228d158fb31 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -28,14 +28,53 @@ Required properties:
  - compatible: must be: "marvell,ap806-clock"
  - #clock-cells: must be set to 1
 
+Pinctrl:
+
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+- compatible must be "marvell,ap806-pinctrl",
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name   pinsfunctions
+
+mpp0   0   gpio, sdio(clk), spi0(clk)
+mpp1   1   gpio, sdio(cmd), spi0(miso)
+mpp2   2   gpio, sdio(d0), spi0(mosi)
+mpp3   3   gpio, sdio(d1), spi0(cs0n)
+mpp4   4   gpio, sdio(d2), i2c0(sda)
+mpp5   5   gpio, sdio(d3), i2c0(sdk)
+mpp6   6   gpio, sdio(ds)
+mpp7   7   gpio, sdio(d4), uart1(rxd)
+mpp8   8   gpio, sdio(d5), uart1(txd)
+mpp9   9   gpio, sdio(d6), spi0(cs1n)
+mpp10  10  gpio, sdio(d7)
+mpp11  11  gpio, uart0(txd)
+mpp12  12  gpio, sdio(pw_off), sdio(hw_rst)
+mpp13  13  gpio
+mpp14  14  gpio
+mpp15  15  gpio
+mpp16  16  gpio
+mpp17  17  gpio
+mpp18  18  gpio
+mpp19  19  gpio, uart0(rxd), sdio(pw_off)
+
 Example:
+ap_syscon: system-controller@6f4000 {
+   compatible = "syscon", "simple-mfd";
+   reg = <0x6f4000 0x1000>;
 
-   syscon: system-controller@6f4000 {
-   compatible = "syscon", "simple-mfd";
-   reg = <0x6f4000 0x1000>;
+   ap_clk: clock {
+   compatible = "marvell,ap806-clock";
+   #clock-cells = <1>;
+   };
 
-   ap_clk: clock {
-   compatible = "marvell,ap806-clock";
-   #clock-cells = <1>;
-   };
+   ap_pinctrl: pinctrl {
+   compatible = "marvell,ap806-pinctrl";
};
+};
-- 
git-series 0.9.1

[PATCH v2 03/11] pinctrl: mvebu: remove the offset property for regmap

[Gregory CLEMENT]

The offset property of the pinctrl node, when a regmap is used in the
device tree, was never used nor documented in the binding. Moreover, the
compatible string is enough to let the driver know which offset using.

So this patch removes the property and move the information at the driver
level.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/pinctrl-mvebu.c | 6 +-
 drivers/pinctrl/mvebu/pinctrl-mvebu.h | 2 +-
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c 
b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index e4dda12d371a..163d4614b0f8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -810,21 +810,17 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data 
*data,
 }
 
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev)
+ struct device *syscon_dev, u32 offset)
 {
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(>dev);
struct mvebu_mpp_ctrl_data *mpp_data;
struct regmap *regmap;
-   u32 offset;
int i;
 
regmap = syscon_node_to_regmap(syscon_dev->of_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
 
-   if (of_property_read_u32(pdev->dev.of_node, "offset", ))
-   return -EINVAL;
-
mpp_data = devm_kcalloc(>dev, soc->ncontrols, sizeof(*mpp_data),
GFP_KERNEL);
if (!mpp_data)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h 
b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index c90704e74884..75bba436bf59 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -210,6 +210,6 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data 
*data, unsigned pid,
 int mvebu_pinctrl_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev);
+ struct device *syscon_dev, u32 offset);
 
 #endif
-- 
git-series 0.9.1

[PATCH v2 03/11] pinctrl: mvebu: remove the offset property for regmap

[Gregory CLEMENT]

The offset property of the pinctrl node, when a regmap is used in the
device tree, was never used nor documented in the binding. Moreover, the
compatible string is enough to let the driver know which offset using.

So this patch removes the property and move the information at the driver
level.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/pinctrl-mvebu.c | 6 +-
 drivers/pinctrl/mvebu/pinctrl-mvebu.h | 2 +-
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c 
b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index e4dda12d371a..163d4614b0f8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -810,21 +810,17 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data 
*data,
 }
 
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev)
+ struct device *syscon_dev, u32 offset)
 {
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(>dev);
struct mvebu_mpp_ctrl_data *mpp_data;
struct regmap *regmap;
-   u32 offset;
int i;
 
regmap = syscon_node_to_regmap(syscon_dev->of_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
 
-   if (of_property_read_u32(pdev->dev.of_node, "offset", ))
-   return -EINVAL;
-
mpp_data = devm_kcalloc(>dev, soc->ncontrols, sizeof(*mpp_data),
GFP_KERNEL);
if (!mpp_data)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h 
b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index c90704e74884..75bba436bf59 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -210,6 +210,6 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data 
*data, unsigned pid,
 int mvebu_pinctrl_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev);
+ struct device *syscon_dev, u32 offset);
 
 #endif
-- 
git-series 0.9.1

[PATCH v2 04/11] pinctrl: avoid PLAT_ORION dependency

[Gregory CLEMENT]

From: Russell King 

Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Russell King 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 5bade32d3089..8cb444b60ae9 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,5 +1,3 @@
-if PLAT_ORION
-
 config PINCTRL_MVEBU
bool
select PINMUX
@@ -38,8 +36,6 @@ config PINCTRL_ORION
bool
select PINCTRL_MVEBU
 
-endif
-
 config PINCTRL_ARMADA_37XX
bool
select GENERIC_PINCONF
-- 
git-series 0.9.1

[PATCH v2 04/11] pinctrl: avoid PLAT_ORION dependency

[Gregory CLEMENT]

From: Russell King 

Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Russell King 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 5bade32d3089..8cb444b60ae9 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,5 +1,3 @@
-if PLAT_ORION
-
 config PINCTRL_MVEBU
bool
select PINMUX
@@ -38,8 +36,6 @@ config PINCTRL_ORION
bool
select PINCTRL_MVEBU
 
-endif
-
 config PINCTRL_ARMADA_37XX
bool
select GENERIC_PINCONF
-- 
git-series 0.9.1

[PATCH v2 05/11] arm64: marvell: enable the Armada 7K/8K pinctrl driver

[Gregory CLEMENT]

This commit makes sure the drivers for the Armada 7K/8K pin controllers
are enabled.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/Kconfig.platforms | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index b4e919ac73f6..c8fc2e7f0152 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -113,6 +113,8 @@ config ARCH_MVEBU
select OF_GPIO
select PINCTRL
select PINCTRL_ARMADA_37XX
+   select PINCTRL_ARMADA_AP806
+   select PINCTRL_ARMADA_CP110
help
  This enables support for Marvell EBU familly, including:
   - Armada 3700 SoC Family
-- 
git-series 0.9.1

[PATCH v2 05/11] arm64: marvell: enable the Armada 7K/8K pinctrl driver

[Gregory CLEMENT]

This commit makes sure the drivers for the Armada 7K/8K pin controllers
are enabled.

Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/Kconfig.platforms | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index b4e919ac73f6..c8fc2e7f0152 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -113,6 +113,8 @@ config ARCH_MVEBU
select OF_GPIO
select PINCTRL
select PINCTRL_ARMADA_37XX
+   select PINCTRL_ARMADA_AP806
+   select PINCTRL_ARMADA_CP110
help
  This enables support for Marvell EBU familly, including:
   - Armada 3700 SoC Family
-- 
git-series 0.9.1

[PATCH v2 08/11] arm64: dts: marvell: add pinctrl support for Armada 7K/8K

[Gregory CLEMENT]

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.

The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.

These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.

Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/boot/dts/marvell/armada-7020.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi  | 53 ++-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 60 -
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi |  4 +-
 7 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi

diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi 
b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi 
b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index ..f6c22665d091
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+_syscon0 {
+   cpm_pinctrl: pinctrl {
+   compatible = "marvell,armada-7k-pinctrl";
+   };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi 
b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
 
 / {
model = "Marvell Armada 8020";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi 
b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 33813a75bc30..60fe84f5cbcc 100644
--- 

[PATCH v2 08/11] arm64: dts: marvell: add pinctrl support for Armada 7K/8K

[Gregory CLEMENT]

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.

The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.

These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.

Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/boot/dts/marvell/armada-7020.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi  | 53 ++-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 60 -
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi |  4 +-
 7 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi

diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi 
b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi 
b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index ..f6c22665d091
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+_syscon0 {
+   cpm_pinctrl: pinctrl {
+   compatible = "marvell,armada-7k-pinctrl";
+   };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi 
b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
 
 / {
model = "Marvell Armada 8020";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi 
b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 33813a75bc30..60fe84f5cbcc 100644
--- 

[PATCH v2 07/11] pinctrl: mvebu: add driver for Armada CP110 pinctrl

[Gregory CLEMENT]

From: Hanna Hawa 

This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).

The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.

Signed-off-by: Hanna Hawa 
Reviewed-by: Shadi Ammouri 

[updated for mvebu pinctrl and 4.9 changes:
 - converted to simple_mmio
 - converted to syscon/regmap
 - removed unimplemented .remove function
 - dropped DTS changes
 - defered gpio ranges to DT
 - fixed warning
 - properly set soc->nmodes
 -- rmk]
Signed-off-by: Russell King 

[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin 

[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk 

[ - rebased on 4.12-rc1
  - fixed the 80 character limit for mvebu_mpp_mode array
  - aligned the compatible name on the ones already used
  - fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT 

Tested-by: Thomas Petazzoni 
---
 drivers/pinctrl/mvebu/Kconfig|   4 +-
 drivers/pinctrl/mvebu/Makefile   |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 687 -
 3 files changed, 692 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 0e0b009f2b71..d9773b77ff9f 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -32,6 +32,10 @@ config PINCTRL_ARMADA_AP806
bool
select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_CP110
+   bool
+   select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 455db274b53d..5b03fd55e28d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
 obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
+obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
new file mode 100644
index ..7f85beb45482
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -0,0 +1,687 @@
+/*
+ * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-mvebu.h"
+
+/*
+ * Even if the pin controller is the same the MMP available depend on the SoC
+ * integration.
+ *  - In Armada7K (single CP) almost all the MPPs are available (except the
+ *MMP 39 to 43)
+ *  - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
+ *CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
+ *V_ARMADA_8K_CPS) set which MPP is available to the CPx.
+ * The x_PLUS enum mean that the MPP available for CPx and for Armada70x0
+ */
+enum {
+   V_ARMADA_7K = BIT(0),
+   V_ARMADA_8K_CPM = BIT(1),
+   V_ARMADA_8K_CPS = BIT(2),
+   V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
+   V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
+};
+
+static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_FUNCTION(0,"gpio", NULL),
+MPP_FUNCTION(1,"dev",  "ale1"),
+MPP_FUNCTION(2,"au",   "i2smclk"),
+MPP_FUNCTION(3,"ge0",  "rxd3"),
+MPP_FUNCTION(4,"tdm",  "pclk"),
+MPP_FUNCTION(6,"ptp",  "pulse"),
+MPP_FUNCTION(7,"mss_i2c",  "sda"),
+

[PATCH v2 07/11] pinctrl: mvebu: add driver for Armada CP110 pinctrl

[Gregory CLEMENT]

From: Hanna Hawa 

This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).

The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.

Signed-off-by: Hanna Hawa 
Reviewed-by: Shadi Ammouri 

[updated for mvebu pinctrl and 4.9 changes:
 - converted to simple_mmio
 - converted to syscon/regmap
 - removed unimplemented .remove function
 - dropped DTS changes
 - defered gpio ranges to DT
 - fixed warning
 - properly set soc->nmodes
 -- rmk]
Signed-off-by: Russell King 

[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin 

[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk 

[ - rebased on 4.12-rc1
  - fixed the 80 character limit for mvebu_mpp_mode array
  - aligned the compatible name on the ones already used
  - fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT 

Tested-by: Thomas Petazzoni 
---
 drivers/pinctrl/mvebu/Kconfig|   4 +-
 drivers/pinctrl/mvebu/Makefile   |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 687 -
 3 files changed, 692 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 0e0b009f2b71..d9773b77ff9f 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -32,6 +32,10 @@ config PINCTRL_ARMADA_AP806
bool
select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_CP110
+   bool
+   select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 455db274b53d..5b03fd55e28d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
 obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
+obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
new file mode 100644
index ..7f85beb45482
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -0,0 +1,687 @@
+/*
+ * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-mvebu.h"
+
+/*
+ * Even if the pin controller is the same the MMP available depend on the SoC
+ * integration.
+ *  - In Armada7K (single CP) almost all the MPPs are available (except the
+ *MMP 39 to 43)
+ *  - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
+ *CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
+ *V_ARMADA_8K_CPS) set which MPP is available to the CPx.
+ * The x_PLUS enum mean that the MPP available for CPx and for Armada70x0
+ */
+enum {
+   V_ARMADA_7K = BIT(0),
+   V_ARMADA_8K_CPM = BIT(1),
+   V_ARMADA_8K_CPS = BIT(2),
+   V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
+   V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
+};
+
+static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_FUNCTION(0,"gpio", NULL),
+MPP_FUNCTION(1,"dev",  "ale1"),
+MPP_FUNCTION(2,"au",   "i2smclk"),
+MPP_FUNCTION(3,"ge0",  "rxd3"),
+MPP_FUNCTION(4,"tdm",  "pclk"),
+MPP_FUNCTION(6,"ptp",  "pulse"),
+MPP_FUNCTION(7,"mss_i2c",  "sda"),
+MPP_FUNCTION(8,"uart0","rxd"),
+MPP_FUNCTION(9,"sata0","present_act"),
+MPP_FUNCTION(10,   "ge",   "mdio")),
+   MPP_MODE(1,
+

[PATCH v2 09/11] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

[Gregory CLEMENT]

Document the device tree binding for the gpio controllers found on the
Marvell Armada 7K and Armada 8K SoCs.

Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt  | 
20 
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
24 +++-
 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt  | 
24 +---
 3 files changed, 60 insertions(+), 8 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt 
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 4228d158fb31..0b887440e08a 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -64,6 +64,17 @@ mpp1717  gpio
 mpp18  18  gpio
 mpp19  19  gpio, uart0(rxd), sdio(pw_off)
 
+GPIO:
+-
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
 Example:
 ap_syscon: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
@@ -77,4 +88,13 @@ ap_syscon: system-controller@6f4000 {
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
+
+   ap_gpio: gpio {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x1040>;
+   ngpios = <19>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 19>;
+   };
 };
diff --git 
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt 
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 733beac7724e..655c114ef584 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -149,6 +149,18 @@ mpp60  60  gpio, mss_gpio6, ptp(pulse), tdm(dtx), 
au(i2smclk), spi0(csn1), uart0(r
 mpp61  61  gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), 
spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
 mpp62  62  gpio, mss_gpio4, synce1(clk), ptp(pclk_out), 
sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), 
ge(mdc)
 
+GPIO:
+-
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
 Example:
 
 cpm_syscon0: system-controller@44 {
@@ -163,5 +175,15 @@ cpm_syscon0: system-controller@44 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
-};
 
+   cpm_gpio1: gpio@100 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x100>;
+   ngpios = <32>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 32>;
+   status = "disabled";
+   };
+
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index 42c3bb2d53e8..2c5304ff467c 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -2,17 +2,27 @@
 
 Required properties:
 
-- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
-  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
-  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
-  370. "marvell,mv78200-gpio" should be used for the Discovery
-  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
-  SoCs (MV78230, MV78260, MV78460).
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
+  "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
+
+"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
+Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
+should be used for the Discovery MV78200.
+
+"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
+(MV78230, MV78260, MV78460).
+
+"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
+SoCs (either from AP or CP), see
+Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+and
+Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+for specific details about the offset property.
 
 - reg: Address and length of the register set for the device. Only one
   entry is expected, except for the "marvell,armadaxp-gpio" variant
   for which two entries are expected: one for the 

[PATCH v2 09/11] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

[Gregory CLEMENT]

Document the device tree binding for the gpio controllers found on the
Marvell Armada 7K and Armada 8K SoCs.

Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt  | 
20 
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
24 +++-
 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt  | 
24 +---
 3 files changed, 60 insertions(+), 8 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt 
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 4228d158fb31..0b887440e08a 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -64,6 +64,17 @@ mpp1717  gpio
 mpp18  18  gpio
 mpp19  19  gpio, uart0(rxd), sdio(pw_off)
 
+GPIO:
+-
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
 Example:
 ap_syscon: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
@@ -77,4 +88,13 @@ ap_syscon: system-controller@6f4000 {
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
+
+   ap_gpio: gpio {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x1040>;
+   ngpios = <19>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 19>;
+   };
 };
diff --git 
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt 
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 733beac7724e..655c114ef584 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -149,6 +149,18 @@ mpp60  60  gpio, mss_gpio6, ptp(pulse), tdm(dtx), 
au(i2smclk), spi0(csn1), uart0(r
 mpp61  61  gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), 
spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
 mpp62  62  gpio, mss_gpio4, synce1(clk), ptp(pclk_out), 
sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), 
ge(mdc)
 
+GPIO:
+-
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
 Example:
 
 cpm_syscon0: system-controller@44 {
@@ -163,5 +175,15 @@ cpm_syscon0: system-controller@44 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
-};
 
+   cpm_gpio1: gpio@100 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x100>;
+   ngpios = <32>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 32>;
+   status = "disabled";
+   };
+
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index 42c3bb2d53e8..2c5304ff467c 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -2,17 +2,27 @@
 
 Required properties:
 
-- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
-  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
-  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
-  370. "marvell,mv78200-gpio" should be used for the Discovery
-  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
-  SoCs (MV78230, MV78260, MV78460).
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
+  "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
+
+"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
+Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
+should be used for the Discovery MV78200.
+
+"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
+(MV78230, MV78260, MV78460).
+
+"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
+SoCs (either from AP or CP), see
+Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+and
+Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+for specific details about the offset property.
 
 - reg: Address and length of the register set for the device. Only one
   entry is expected, except for the "marvell,armadaxp-gpio" variant
   for which two entries are expected: one for the general registers,
-  one for the 

[PATCH v2 10/11] gpio: mvebu: Add support for the Armada 7K/8K SoCs

[Gregory CLEMENT]

The Armada 7K and 8K SoCs use the same gpio controller as most of the
other mvebu SoCs. However, the main difference is that the GPIO
controller is part of a bigger system controller, and a syscon is used to
control the overall system controller. Therefore, the driver needs to be
adjusted to retrieve the regmap of the syscon to access registers, and
account for the fact that registers are located at a certain offset
within the regmap.

This commit add the support of the syscon and introduce a new variant for
this case.

It was based on the preliminary work of Thomas Petazzoni.

Tested-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/gpio/gpio-mvebu.c | 212 +--
 1 file changed, 141 insertions(+), 71 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3d03740a20e7..5edb04abd7d7 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,6 +42,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -88,6 +89,7 @@
 #define MVEBU_GPIO_SOC_VARIANT_ORION   0x1
 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+#define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
 
 #define MVEBU_MAX_GPIO_PER_BANK32
 
@@ -108,6 +110,7 @@ struct mvebu_pwm {
 struct mvebu_gpio_chip {
struct gpio_chip   chip;
struct regmap *regs;
+   u32offset;
struct regmap *percpu_regs;
intirqbase;
struct irq_domain *domain;
@@ -139,8 +142,9 @@ static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip 
*mvchip,
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
case MVEBU_GPIO_SOC_VARIANT_MV78200:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_EDGE_CAUSE_OFF;
+   *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
cpu = smp_processor_id();
@@ -183,8 +187,9 @@ mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
 
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_EDGE_MASK_OFF;
+   *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id();
@@ -232,8 +237,9 @@ mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
 
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_LEVEL_MASK_OFF;
+   *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id();
@@ -294,7 +300,7 @@ static void mvebu_gpio_set(struct gpio_chip *chip, unsigned 
int pin, int value)
 {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-   regmap_update_bits(mvchip->regs, GPIO_OUT_OFF,
+   regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -303,16 +309,18 @@ static int mvebu_gpio_get(struct gpio_chip *chip, 
unsigned int pin)
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
u32 u;
 
-   regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, );
+   regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, );
 
if (u & BIT(pin)) {
u32 data_in, in_pol;
 
-   regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, _in);
-   regmap_read(mvchip->regs, GPIO_IN_POL_OFF, _pol);
+   regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
+   _in);
+   regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+   _pol);
u = data_in ^ in_pol;
} else {
-   regmap_read(mvchip->regs, GPIO_OUT_OFF, );
+   regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, );
}
 
return (u >> pin) & 1;
@@ -323,7 +331,7 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, 
unsigned int pin,
 {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-   regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF,
+   regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -340,7 +348,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip 
*chip, unsigned int pin)
if (ret)
return ret;
 
-   regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
+   

[PATCH v2 10/11] gpio: mvebu: Add support for the Armada 7K/8K SoCs

[Gregory CLEMENT]

The Armada 7K and 8K SoCs use the same gpio controller as most of the
other mvebu SoCs. However, the main difference is that the GPIO
controller is part of a bigger system controller, and a syscon is used to
control the overall system controller. Therefore, the driver needs to be
adjusted to retrieve the regmap of the syscon to access registers, and
account for the fact that registers are located at a certain offset
within the regmap.

This commit add the support of the syscon and introduce a new variant for
this case.

It was based on the preliminary work of Thomas Petazzoni.

Tested-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/gpio/gpio-mvebu.c | 212 +--
 1 file changed, 141 insertions(+), 71 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3d03740a20e7..5edb04abd7d7 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,6 +42,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -88,6 +89,7 @@
 #define MVEBU_GPIO_SOC_VARIANT_ORION   0x1
 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+#define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
 
 #define MVEBU_MAX_GPIO_PER_BANK32
 
@@ -108,6 +110,7 @@ struct mvebu_pwm {
 struct mvebu_gpio_chip {
struct gpio_chip   chip;
struct regmap *regs;
+   u32offset;
struct regmap *percpu_regs;
intirqbase;
struct irq_domain *domain;
@@ -139,8 +142,9 @@ static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip 
*mvchip,
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
case MVEBU_GPIO_SOC_VARIANT_MV78200:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_EDGE_CAUSE_OFF;
+   *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
cpu = smp_processor_id();
@@ -183,8 +187,9 @@ mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
 
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_EDGE_MASK_OFF;
+   *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id();
@@ -232,8 +237,9 @@ mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
 
switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION:
+   case MVEBU_GPIO_SOC_VARIANT_A8K:
*map = mvchip->regs;
-   *offset = GPIO_LEVEL_MASK_OFF;
+   *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id();
@@ -294,7 +300,7 @@ static void mvebu_gpio_set(struct gpio_chip *chip, unsigned 
int pin, int value)
 {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-   regmap_update_bits(mvchip->regs, GPIO_OUT_OFF,
+   regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -303,16 +309,18 @@ static int mvebu_gpio_get(struct gpio_chip *chip, 
unsigned int pin)
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
u32 u;
 
-   regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, );
+   regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, );
 
if (u & BIT(pin)) {
u32 data_in, in_pol;
 
-   regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, _in);
-   regmap_read(mvchip->regs, GPIO_IN_POL_OFF, _pol);
+   regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
+   _in);
+   regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+   _pol);
u = data_in ^ in_pol;
} else {
-   regmap_read(mvchip->regs, GPIO_OUT_OFF, );
+   regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, );
}
 
return (u >> pin) & 1;
@@ -323,7 +331,7 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, 
unsigned int pin,
 {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-   regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF,
+   regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -340,7 +348,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip 
*chip, unsigned int pin)
if (ret)
return ret;
 
-   regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
+   regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
   

[PATCH v2 02/11] pinctrl: dt-bindings: add documentation for CP110 pin controllers

[Gregory CLEMENT]

Document the device tree binding for the pin controllers found on the
Armada 7K and Armada 8K SoCs.

Acked-by: Rob Herring 
Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
101 +++-
 1 file changed, 94 insertions(+), 7 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt 
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index e0b9ef5d3dde..733beac7724e 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -67,14 +67,101 @@ Required properties:
  "marvell,cp110-clock"
  - #clock-cells: must be set to 2
 
+Pinctrl:
+
+
+For common binding part and usage, refer to the file
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-7k-pinctrl",
+  "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
+  depending on the specific variant of the SoC being used.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name   pinsfunctions
+
+mpp0   0   gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), 
mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
+mpp1   1   gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), 
ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
+mpp2   2   gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), 
mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
+mpp3   3   gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), 
mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), 
xg(mdio)
+mpp4   4   gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), 
mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
+mpp5   5   gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), 
mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
+mpp6   6   gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), 
sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
+mpp7   7   gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), 
sata0(present_act), led(data), uart0(txd), ptp(clk)
+mpp8   8   gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), 
led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
+mpp9   9   gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), 
pcie(rstoutn), synce2(clk)
+mpp10  10  gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), 
uart0(cts), sata1(present_act)
+mpp11  11  gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), 
uart0(rts), led(clk), uart2(txd), sata0(present_act)
+mpp12  12  gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
+mpp13  13  gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), 
mss_spi(miso)
+mpp14  14  gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), 
au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
+mpp15  15  gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), 
ptp(pulse_cp2cp)
+mpp16  16  gpio, dev(ad6), spi1(clk), mss_spi(clk)
+mpp17  17  gpio, dev(ad5), ge0(txd3)
+mpp18  18  gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
+mpp19  19  gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
+mpp20  20  gpio, dev(ad2), ge0(txd0)
+mpp21  21  gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
+mpp22  22  gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
+mpp23  23  gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
+mpp24  24  gpio, dev(a0), au(i2slrclk)
+mpp25  25  gpio, dev(oen), au(i2sdo_spdifo)
+mpp26  26  gpio, dev(wen0), au(i2sbclk)
+mpp27  27  gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), 
ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
+mpp28  28  gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), 
pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
+mpp29  29  gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), 
pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
+mpp30  30  gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), 
pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), 
led(clk)
+mpp31  31  gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
+mpp32  32  gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), 
au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
+mpp33  33  gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), 
au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1

[PATCH v2 02/11] pinctrl: dt-bindings: add documentation for CP110 pin controllers

[Gregory CLEMENT]

Document the device tree binding for the pin controllers found on the
Armada 7K and Armada 8K SoCs.

Acked-by: Rob Herring 
Signed-off-by: Gregory CLEMENT 
---
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
101 +++-
 1 file changed, 94 insertions(+), 7 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt 
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index e0b9ef5d3dde..733beac7724e 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -67,14 +67,101 @@ Required properties:
  "marvell,cp110-clock"
  - #clock-cells: must be set to 2
 
+Pinctrl:
+
+
+For common binding part and usage, refer to the file
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-7k-pinctrl",
+  "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
+  depending on the specific variant of the SoC being used.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name   pinsfunctions
+
+mpp0   0   gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), 
mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
+mpp1   1   gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), 
ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
+mpp2   2   gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), 
mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
+mpp3   3   gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), 
mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), 
xg(mdio)
+mpp4   4   gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), 
mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
+mpp5   5   gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), 
mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
+mpp6   6   gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), 
sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
+mpp7   7   gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), 
sata0(present_act), led(data), uart0(txd), ptp(clk)
+mpp8   8   gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), 
led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
+mpp9   9   gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), 
pcie(rstoutn), synce2(clk)
+mpp10  10  gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), 
uart0(cts), sata1(present_act)
+mpp11  11  gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), 
uart0(rts), led(clk), uart2(txd), sata0(present_act)
+mpp12  12  gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
+mpp13  13  gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), 
mss_spi(miso)
+mpp14  14  gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), 
au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
+mpp15  15  gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), 
ptp(pulse_cp2cp)
+mpp16  16  gpio, dev(ad6), spi1(clk), mss_spi(clk)
+mpp17  17  gpio, dev(ad5), ge0(txd3)
+mpp18  18  gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
+mpp19  19  gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
+mpp20  20  gpio, dev(ad2), ge0(txd0)
+mpp21  21  gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
+mpp22  22  gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
+mpp23  23  gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
+mpp24  24  gpio, dev(a0), au(i2slrclk)
+mpp25  25  gpio, dev(oen), au(i2sdo_spdifo)
+mpp26  26  gpio, dev(wen0), au(i2sbclk)
+mpp27  27  gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), 
ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
+mpp28  28  gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), 
pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
+mpp29  29  gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), 
pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
+mpp30  30  gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), 
pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), 
led(clk)
+mpp31  31  gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
+mpp32  32  gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), 
au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
+mpp33  33  gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), 
au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
+mpp34  34  gpio, mii(rxerr), sdio(pwr11), 

[PATCH v2 11/11] arm64: dts: marvell: add gpio support for Armada 7K/8K

[Gregory CLEMENT]

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.

The Armada 8K has two CP110 blocks, each having two GPIO controllers.
However, in each CP110 block, one of the GPIO controller cannot be
used: in the master CP110, only the second GPIO controller can be used,
while on the slave CP110, only the first GPIO controller can be used.

On the other side, the Armada 7K has only one CP110, but both its GPIO
controllers can be used.

For this reason, the GPIO controllers are marked as "disabled" in the
armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
enabled in the per-SoC dtsi files.

Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 15 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 16 +-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi| 10 ++-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 21 -
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 22 +-
 5 files changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index f6c22665d091..860b6ae9dcc5 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -46,6 +46,21 @@
 
 #include "armada-cp110-master.dtsi"
 
+/ {
+   aliases {
+   gpio1 = _gpio1;
+   gpio2 = _gpio2;
+   };
+};
+
+_gpio1 {
+   status = "okay";
+};
+
+_gpio2 {
+   status = "okay";
+};
+
 _syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 93d1de03b39a..666ebe96ba0d 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -47,6 +47,22 @@
 #include "armada-cp110-master.dtsi"
 #include "armada-cp110-slave.dtsi"
 
+/ {
+   aliases {
+   gpio1 = _gpio1;
+   gpio2 = _gpio2;
+   };
+};
+
+/* The 80x0 has two CP blocks, but uses only one block from each. */
+_gpio1 {
+   status = "okay";
+};
+
+_gpio2 {
+   status = "okay";
+};
+
 _syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi 
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index c6c30143eb29..f19d5077ba8d 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -57,6 +57,7 @@
aliases {
serial0 = 
serial1 = 
+   gpio0 = _gpio;
};
 
psci {
@@ -256,6 +257,15 @@
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
+
+   ap_gpio: gpio {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x1040>;
+   ngpios = <19>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 19>;
+   };
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi 
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 4788a87fc43c..1bcd549228db 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -104,6 +104,27 @@
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
+
+   cpm_gpio1: gpio@100 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x100>;
+   ngpios = <32>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 32>;
+   status = "disabled";
+
+   };
+
+   cpm_gpio2: gpio@140 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x140>;
+   ngpios = <31>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 32 31>;
+   status = 

[PATCH v2 06/11] pinctrl: mvebu: add driver for Armada AP806 pinctrl

[Gregory CLEMENT]

From: Hanna Hawa 

This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.

Signed-off-by: Hanna Hawa 
Reviewed-by: Shadi Ammouri 
[updated for mvebu pinctrl changes
 - converted to simple_mmio
 - removed unimplemented .remove function
 - removed DTS description
  - converted  to use syscon/regmap
 --rmk]
Signed-off-by: Russell King 
Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/Kconfig|   4 +-
 drivers/pinctrl/mvebu/Makefile   |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c | 140 -
 3 files changed, 145 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 8cb444b60ae9..0e0b009f2b71 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -28,6 +28,10 @@ config PINCTRL_ARMADA_39X
bool
select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_AP806
+   bool
+   select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 60c245a60f39..455db274b53d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
+obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
new file mode 100644
index ..66e442260a4e
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
@@ -0,0 +1,140 @@
+/*
+ * Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni 
+ * Hanna Hawa 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","clk"),
+MPP_FUNCTION(3, "spi0","clk")),
+   MPP_MODE(1,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","cmd"),
+MPP_FUNCTION(3, "spi0","miso")),
+   MPP_MODE(2,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d0"),
+MPP_FUNCTION(3, "spi0","mosi")),
+   MPP_MODE(3,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d1"),
+MPP_FUNCTION(3, "spi0","cs0n")),
+   MPP_MODE(4,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d2"),
+MPP_FUNCTION(3, "i2c0","sda")),
+   MPP_MODE(5,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d3"),
+MPP_FUNCTION(3, "i2c0","sdk")),
+   MPP_MODE(6,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","ds")),
+   MPP_MODE(7,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d4"),
+MPP_FUNCTION(3, "uart1",   "rxd")),
+   MPP_MODE(8,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d5"),
+MPP_FUNCTION(3, "uart1",   "txd")),
+   MPP_MODE(9,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d6"),
+MPP_FUNCTION(3, "spi0","cs1n")),
+   MPP_MODE(10,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d7")),
+   MPP_MODE(11,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(3, "uart0",   

[PATCH v2 11/11] arm64: dts: marvell: add gpio support for Armada 7K/8K

[Gregory CLEMENT]

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.

The Armada 8K has two CP110 blocks, each having two GPIO controllers.
However, in each CP110 block, one of the GPIO controller cannot be
used: in the master CP110, only the second GPIO controller can be used,
while on the slave CP110, only the first GPIO controller can be used.

On the other side, the Armada 7K has only one CP110, but both its GPIO
controllers can be used.

For this reason, the GPIO controllers are marked as "disabled" in the
armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
enabled in the per-SoC dtsi files.

Signed-off-by: Gregory CLEMENT 
---
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 15 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 16 +-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi| 10 ++-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 21 -
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 22 +-
 5 files changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index f6c22665d091..860b6ae9dcc5 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -46,6 +46,21 @@
 
 #include "armada-cp110-master.dtsi"
 
+/ {
+   aliases {
+   gpio1 = _gpio1;
+   gpio2 = _gpio2;
+   };
+};
+
+_gpio1 {
+   status = "okay";
+};
+
+_gpio2 {
+   status = "okay";
+};
+
 _syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi 
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 93d1de03b39a..666ebe96ba0d 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -47,6 +47,22 @@
 #include "armada-cp110-master.dtsi"
 #include "armada-cp110-slave.dtsi"
 
+/ {
+   aliases {
+   gpio1 = _gpio1;
+   gpio2 = _gpio2;
+   };
+};
+
+/* The 80x0 has two CP blocks, but uses only one block from each. */
+_gpio1 {
+   status = "okay";
+};
+
+_gpio2 {
+   status = "okay";
+};
+
 _syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi 
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index c6c30143eb29..f19d5077ba8d 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -57,6 +57,7 @@
aliases {
serial0 = 
serial1 = 
+   gpio0 = _gpio;
};
 
psci {
@@ -256,6 +257,15 @@
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
+
+   ap_gpio: gpio {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x1040>;
+   ngpios = <19>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 19>;
+   };
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi 
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 4788a87fc43c..1bcd549228db 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -104,6 +104,27 @@
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
+
+   cpm_gpio1: gpio@100 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x100>;
+   ngpios = <32>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 0 32>;
+   status = "disabled";
+
+   };
+
+   cpm_gpio2: gpio@140 {
+   compatible = "marvell,armada-8k-gpio";
+   offset = <0x140>;
+   ngpios = <31>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_pinctrl 0 32 31>;
+   status = "disabled";
+   };

[PATCH v2 06/11] pinctrl: mvebu: add driver for Armada AP806 pinctrl

[Gregory CLEMENT]

From: Hanna Hawa 

This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.

Signed-off-by: Hanna Hawa 
Reviewed-by: Shadi Ammouri 
[updated for mvebu pinctrl changes
 - converted to simple_mmio
 - removed unimplemented .remove function
 - removed DTS description
  - converted  to use syscon/regmap
 --rmk]
Signed-off-by: Russell King 
Reviewed-by: Thomas Petazzoni 
Signed-off-by: Gregory CLEMENT 
---
 drivers/pinctrl/mvebu/Kconfig|   4 +-
 drivers/pinctrl/mvebu/Makefile   |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c | 140 -
 3 files changed, 145 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 8cb444b60ae9..0e0b009f2b71 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -28,6 +28,10 @@ config PINCTRL_ARMADA_39X
bool
select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_AP806
+   bool
+   select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 60c245a60f39..455db274b53d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
+obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
new file mode 100644
index ..66e442260a4e
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
@@ -0,0 +1,140 @@
+/*
+ * Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni 
+ * Hanna Hawa 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","clk"),
+MPP_FUNCTION(3, "spi0","clk")),
+   MPP_MODE(1,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","cmd"),
+MPP_FUNCTION(3, "spi0","miso")),
+   MPP_MODE(2,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d0"),
+MPP_FUNCTION(3, "spi0","mosi")),
+   MPP_MODE(3,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d1"),
+MPP_FUNCTION(3, "spi0","cs0n")),
+   MPP_MODE(4,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d2"),
+MPP_FUNCTION(3, "i2c0","sda")),
+   MPP_MODE(5,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d3"),
+MPP_FUNCTION(3, "i2c0","sdk")),
+   MPP_MODE(6,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","ds")),
+   MPP_MODE(7,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d4"),
+MPP_FUNCTION(3, "uart1",   "rxd")),
+   MPP_MODE(8,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d5"),
+MPP_FUNCTION(3, "uart1",   "txd")),
+   MPP_MODE(9,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d6"),
+MPP_FUNCTION(3, "spi0","cs1n")),
+   MPP_MODE(10,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","d7")),
+   MPP_MODE(11,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(3, "uart0",   "txd")),
+   MPP_MODE(12,
+MPP_FUNCTION(0, "gpio",NULL),
+MPP_FUNCTION(1, "sdio","pw_off"),
+MPP_FUNCTION(2, "sdio","hw_rst")),
+   MPP_MODE(13,
+   

[PATCH v2 00/11] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K

[Gregory CLEMENT]

Hi,

As requested by Linus Walleij this series is a merge between the series
"Add support for the pin controllers on the Marvell Armada 7K/8K" [1]
and "Extend mvebu gpio driver to support the controllers of the
Marvell Armada 7K/8K" [2].

The first part of the series is adding the support for the pin
controllers found on the Marvell Armada 7K/8K.

These controllers are compatible with the ones found on the ARM32
mvebu SoCs. However, the pinctrl node in the device tree of theses
SoCs are child of a syscon. So for them we will reuse the regmap
support introduced by Russell King.

Each component of the Armada 7K and 8K comes with their own pin
controller, that's why we have 2 new drivers: one for the CP110 and
one for the AP806.

The second part of the series extends the mvebu gpio driver to support
the gpio controllers found on the Marvell Armada 7K/8K SoCs.

The gpio controllers used on the Marvell Armada 7K/8K SoCs are the
same that the ones used on the ARM32 mvebu SoCs. However, the pinctrl
node in the device tree of theses SoCs are child of a syscon.

The patch modifying the documentation still depend on the ones of the
clk series. For the ap806 a first stable branch is already available:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/log/?h=clk-ap806

Also note that the dts patch have to be merged through the mvebu tree
to avoid merge conflict expected with the ICU series sent a few days
ago.

Thanks,

Gregory

Changelog:
v1 -> v2:

- Merged of the pinctrl and gpio series.

- Rebased on next-20170531 (which contains gpio and pinctrl commit
  already applied).

- Removed already applied patches.

- Remove the modular support of the drivers, suggested by Paul
  Gortmaker.

- Added tested-by from Thomas Petazzoni.

- Added acked-by from Rob Herring.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/507396.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/507405.html

Gregory CLEMENT (8):
  pinctrl: dt-bindings: add documentation for AP806 pin controllers
  pinctrl: dt-bindings: add documentation for CP110 pin controllers
  pinctrl: mvebu: remove the offset property for regmap
  arm64: marvell: enable the Armada 7K/8K pinctrl driver
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
  gpio: mvebu: Add support for the Armada 7K/8K SoCs
  arm64: dts: marvell: add gpio support for Armada 7K/8K

Hanna Hawa (2):
  pinctrl: mvebu: add driver for Armada AP806 pinctrl
  pinctrl: mvebu: add driver for Armada CP110 pinctrl

Russell King (1):
  pinctrl: avoid PLAT_ORION dependency

 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt  |  
73 +++-
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
123 -
 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt  |  
24 ++-
 arch/arm64/Kconfig.platforms   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-7020.dtsi   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi   |  
68 +++-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi   |   
3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi   |   
3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi   |  
76 -
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi  |  
14 +-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi   |  
21 ++-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi|  
22 ++-
 drivers/gpio/gpio-mvebu.c  | 
212 ++
 drivers/pinctrl/mvebu/Kconfig  |  
12 +-
 drivers/pinctrl/mvebu/Makefile |   
2 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c   | 
140 +++-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c   | 
687 -
 drivers/pinctrl/mvebu/pinctrl-mvebu.c  |   
6 +-
 drivers/pinctrl/mvebu/pinctrl-mvebu.h  |   
2 +-
 20 files changed, 1386 insertions(+), 108 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

base-commit: 342db02d4f2e08aed46ecae7c1572582049685d6
-- 
git-series 0.9.1

[PATCH v2 00/11] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K

[Gregory CLEMENT]

Hi,

As requested by Linus Walleij this series is a merge between the series
"Add support for the pin controllers on the Marvell Armada 7K/8K" [1]
and "Extend mvebu gpio driver to support the controllers of the
Marvell Armada 7K/8K" [2].

The first part of the series is adding the support for the pin
controllers found on the Marvell Armada 7K/8K.

These controllers are compatible with the ones found on the ARM32
mvebu SoCs. However, the pinctrl node in the device tree of theses
SoCs are child of a syscon. So for them we will reuse the regmap
support introduced by Russell King.

Each component of the Armada 7K and 8K comes with their own pin
controller, that's why we have 2 new drivers: one for the CP110 and
one for the AP806.

The second part of the series extends the mvebu gpio driver to support
the gpio controllers found on the Marvell Armada 7K/8K SoCs.

The gpio controllers used on the Marvell Armada 7K/8K SoCs are the
same that the ones used on the ARM32 mvebu SoCs. However, the pinctrl
node in the device tree of theses SoCs are child of a syscon.

The patch modifying the documentation still depend on the ones of the
clk series. For the ap806 a first stable branch is already available:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/log/?h=clk-ap806

Also note that the dts patch have to be merged through the mvebu tree
to avoid merge conflict expected with the ICU series sent a few days
ago.

Thanks,

Gregory

Changelog:
v1 -> v2:

- Merged of the pinctrl and gpio series.

- Rebased on next-20170531 (which contains gpio and pinctrl commit
  already applied).

- Removed already applied patches.

- Remove the modular support of the drivers, suggested by Paul
  Gortmaker.

- Added tested-by from Thomas Petazzoni.

- Added acked-by from Rob Herring.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/507396.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/507405.html

Gregory CLEMENT (8):
  pinctrl: dt-bindings: add documentation for AP806 pin controllers
  pinctrl: dt-bindings: add documentation for CP110 pin controllers
  pinctrl: mvebu: remove the offset property for regmap
  arm64: marvell: enable the Armada 7K/8K pinctrl driver
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
  gpio: mvebu: Add support for the Armada 7K/8K SoCs
  arm64: dts: marvell: add gpio support for Armada 7K/8K

Hanna Hawa (2):
  pinctrl: mvebu: add driver for Armada AP806 pinctrl
  pinctrl: mvebu: add driver for Armada CP110 pinctrl

Russell King (1):
  pinctrl: avoid PLAT_ORION dependency

 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt  |  
73 +++-
 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 
123 -
 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt  |  
24 ++-
 arch/arm64/Kconfig.platforms   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-7020.dtsi   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi   |   
2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi   |  
68 +++-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi   |   
3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi   |   
3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi   |  
76 -
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi  |  
14 +-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi   |  
21 ++-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi|  
22 ++-
 drivers/gpio/gpio-mvebu.c  | 
212 ++
 drivers/pinctrl/mvebu/Kconfig  |  
12 +-
 drivers/pinctrl/mvebu/Makefile |   
2 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c   | 
140 +++-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c   | 
687 -
 drivers/pinctrl/mvebu/pinctrl-mvebu.c  |   
6 +-
 drivers/pinctrl/mvebu/pinctrl-mvebu.h  |   
2 +-
 20 files changed, 1386 insertions(+), 108 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

base-commit: 342db02d4f2e08aed46ecae7c1572582049685d6
-- 
git-series 0.9.1

Re: sparc gcc 7.1 compile issue

[David Miller]

From: John Paul Adrian Glaubitz 
Date: Fri, 2 Jun 2017 11:17:18 +0200

> On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote:
>> A fix for this is in Linus's tree and was submitted to -stable last
>> night:
> 
> What remains to be fixed though is that the gcc-7 testsuite
> *reproducibly* kills the kernel on sparc64 when building with more than
> around 20 jobs:

Well, I already have a release gcc bug to fix so pretty much I have no
time to look into bugs in unreleased versions of gcc sorry.

Re: sparc gcc 7.1 compile issue

[David Miller]

From: John Paul Adrian Glaubitz 
Date: Fri, 2 Jun 2017 11:17:18 +0200

> On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote:
>> A fix for this is in Linus's tree and was submitted to -stable last
>> night:
> 
> What remains to be fixed though is that the gcc-7 testsuite
> *reproducibly* kills the kernel on sparc64 when building with more than
> around 20 jobs:

Well, I already have a release gcc bug to fix so pretty much I have no
time to look into bugs in unreleased versions of gcc sorry.

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 11:13:20 +0200

> On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
>> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> > From: Corentin Labbe 
>> > Date: Wed, 31 May 2017 09:18:31 +0200
>> > 
>> > > This patch series add the driver for dwmac-sun8i which handle the 
>> > > Ethernet MAC
>> > > present on Allwinner H3/H5/A83T/A64 SoCs.
>> > 
>> > Series applied, but wow that's a lot of DT file changes :-(
>> 
>> The DT patches should not go through your tree, but arm-soc, so I
>> guess this is not an issue for you?
> 
> Ok, so I saw that you actually merged them. Can you revert or drop
> that merge for the DT part?
> 
> This will generate a lot of conflicts with our tree, and I'm not sure
> this would be efficient to make you take all the entirely unrelated to
> next patches.

Please tell me which specific changes to revert.

Thank you.

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 11:13:20 +0200

> On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
>> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> > From: Corentin Labbe 
>> > Date: Wed, 31 May 2017 09:18:31 +0200
>> > 
>> > > This patch series add the driver for dwmac-sun8i which handle the 
>> > > Ethernet MAC
>> > > present on Allwinner H3/H5/A83T/A64 SoCs.
>> > 
>> > Series applied, but wow that's a lot of DT file changes :-(
>> 
>> The DT patches should not go through your tree, but arm-soc, so I
>> guess this is not an issue for you?
> 
> Ok, so I saw that you actually merged them. Can you revert or drop
> that merge for the DT part?
> 
> This will generate a lot of conflicts with our tree, and I'm not sure
> this would be efficient to make you take all the entirely unrelated to
> next patches.

Please tell me which specific changes to revert.

Thank you.

Re: strange PAGE_ALLOC_COSTLY_ORDER usage in xgbe_map_rx_buffer

[Tom Lendacky]

On 5/31/2017 11:04 AM, Michal Hocko wrote:

Hi Tom,


Hi Michal,


I have stumbled over the following construct in xgbe_map_rx_buffer
order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0);
which looks quite suspicious. Why does it PAGE_ALLOC_COSTLY_ORDER - 1?
And why do you depend on PAGE_ALLOC_COSTLY_ORDER at all?



The driver tries to allocate a number of pages to be used as receive
buffers.  Based on what I could find in documentation, the value of
PAGE_ALLOC_COSTLY_ORDER is the point at which order allocations
(could) get expensive.  So I decrease by one the order requested. The
max_t test is just to insure that in case PAGE_ALLOC_COSTLY_ORDER ever
gets defined as 0, 0 would be used.

I believe there have been some enhancements relative to speed in
allocating 0-order pages recently that may make this unnecessary. I
haven't run any performance tests yet to determine if I can just go to
a 0-order allocation, though.

Thanks,
Tom


Thanks!

Re: strange PAGE_ALLOC_COSTLY_ORDER usage in xgbe_map_rx_buffer

[Tom Lendacky]

On 5/31/2017 11:04 AM, Michal Hocko wrote:

Hi Tom,


Hi Michal,


I have stumbled over the following construct in xgbe_map_rx_buffer
order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0);
which looks quite suspicious. Why does it PAGE_ALLOC_COSTLY_ORDER - 1?
And why do you depend on PAGE_ALLOC_COSTLY_ORDER at all?



The driver tries to allocate a number of pages to be used as receive
buffers.  Based on what I could find in documentation, the value of
PAGE_ALLOC_COSTLY_ORDER is the point at which order allocations
(could) get expensive.  So I decrease by one the order requested. The
max_t test is just to insure that in case PAGE_ALLOC_COSTLY_ORDER ever
gets defined as 0, 0 would be used.

I believe there have been some enhancements relative to speed in
allocating 0-order pages recently that may make this unnecessary. I
haven't run any performance tests yet to determine if I can just go to
a 0-order allocation, though.

Thanks,
Tom


Thanks!

Von Dr. Andrew Kitchen,

[Dr. Andrew Kitchen]

Von Dr. Andrew Kitchen,

 Ich erwarte, dass mein Brief Sie bei guter Gesundheit und Ihrer schönsten
Stimmung heute treffen wird. Mein Name ist Dr. Andrew Kitchen, UBS
Investment Bank London, Financial Officer und Chief Operating Officer bei
UBS Wealth Management UK, ich beschloss, eine vertrauliche Zusammenarbeit
mit Ihnen in der Ausführung des hier beschriebenen Deal zu suchen - für
unsere beiden gegenseitigen Nutzen und fordere Sie auf, es ein
Top-Geheimnis wegen der Natur dieser Transaktion zu halten. Während der
Auditierung von Bankkonten in unserer Bank entdeckte ich eine nicht
beanspruchte Geldsumme von (achtzehn Millionen britischen Pfund Sterling)
in einem Konto, das zu einem unserer späten ausländischen Kunden (Herr
Morgan Stanley) gehört, ein amerikanischer Geschäftsmann, der leider
Verlor sein Leben und seine Familie in einem Autounfall.

 Nachdem ich sein persönliches Profil in meiner Bankdatenbank durchgemacht
habe, entdeckte ich, dass er ohne irgendeinen spezifischen Erben für diese
Fonds starb. Ich freue mich gern, Ihnen die Zustimmung zu geben, Ihnen als
nächstes Verwandten / Erben des Verstorbenen zu präsentieren, damit die
Erlöse dieses Kontos, die an (achtzehn Millionen britisches Pfund
Sterling) geschätzt werden, Ihnen als Bond-fide Begünstigte freigegeben
werden Geteilt in Prozent Verhältnis 70% zu mir und 30% zu Ihnen jeweils.
Alles, was ich verlange, ist Ihre äußerste aufrichtige Zusammenarbeit;
Vertrauen und maximale Vertraulichkeit, um dieses Projekt erfolgreich zu
erreichen. Ich habe sorgfältig die Modalitäten für die Ausführung dieser
Transaktion unter einer legitimen Vereinbarung ausgearbeitet, um Sie vor
einer Verletzung des Gesetzes sowohl in Ihrem Land als auch hier in
England zu schützen, wenn der Fonds auf Ihr Bankkonto überwiesen wird.

 Ich wählte Sie wegen der geographischen Lage Ihres Landes und Ihrer
Adresse aus einem internationalen Firmenverzeichnis hier in der Londoner
Handelskammer. Der Hauptgrund, warum ich in diese Transaktion gehen
musste, ist, weil es keine moralische Rechtfertigung für die UBS Bank
gibt, diesen Fonds zu erben. Alles, was ich von Ihnen benötigte, ist Ihre
ehrlichste, aufrichtige, verständnisvolle und vertrauliche Zusammenarbeit.

Bei Rücksicht und Annahme dieses Angebots senden Sie mir bitte folgende
Informationen zu.

- Ihr vollständiger Name:
- Ihre Anschrift:
- Ihre direkte Mobilnummer:
- Ihr Beruf:
- Dein Geburtsdatum:
- Dein Geschlecht:

 Diese oben genannte Information wird es mir ermöglichen, Ihre Daten in
unsere Bankdatenbank einzufügen, um im Banksystem zu erscheinen, dass Sie
der benannte Nächste des Verwandten / Erben Begünstigten des Fonds sind,
und dann werde ich Ihre weitere Kommunikation mit der UBS Investment Bank
zur sofortigen Freigabe führen Und Übertragung des Fonds auf Ihr
designated Bankkonto, Ihre freundliche schnelle Antwort wird in hohem
Grade geschätzt, für mehr Details über dieses Geschäft Abkommen.

Vielen Dank in Anerkennung und Vorfreude auf Ihre dringende Antwort.

 Freundliche Grüße,

Dr. Andrew Kitchen,
Chief Operating Officer bei UBS Wealth Management UK.

Von Dr. Andrew Kitchen,

[Dr. Andrew Kitchen]

Von Dr. Andrew Kitchen,

 Ich erwarte, dass mein Brief Sie bei guter Gesundheit und Ihrer schönsten
Stimmung heute treffen wird. Mein Name ist Dr. Andrew Kitchen, UBS
Investment Bank London, Financial Officer und Chief Operating Officer bei
UBS Wealth Management UK, ich beschloss, eine vertrauliche Zusammenarbeit
mit Ihnen in der Ausführung des hier beschriebenen Deal zu suchen - für
unsere beiden gegenseitigen Nutzen und fordere Sie auf, es ein
Top-Geheimnis wegen der Natur dieser Transaktion zu halten. Während der
Auditierung von Bankkonten in unserer Bank entdeckte ich eine nicht
beanspruchte Geldsumme von (achtzehn Millionen britischen Pfund Sterling)
in einem Konto, das zu einem unserer späten ausländischen Kunden (Herr
Morgan Stanley) gehört, ein amerikanischer Geschäftsmann, der leider
Verlor sein Leben und seine Familie in einem Autounfall.

 Nachdem ich sein persönliches Profil in meiner Bankdatenbank durchgemacht
habe, entdeckte ich, dass er ohne irgendeinen spezifischen Erben für diese
Fonds starb. Ich freue mich gern, Ihnen die Zustimmung zu geben, Ihnen als
nächstes Verwandten / Erben des Verstorbenen zu präsentieren, damit die
Erlöse dieses Kontos, die an (achtzehn Millionen britisches Pfund
Sterling) geschätzt werden, Ihnen als Bond-fide Begünstigte freigegeben
werden Geteilt in Prozent Verhältnis 70% zu mir und 30% zu Ihnen jeweils.
Alles, was ich verlange, ist Ihre äußerste aufrichtige Zusammenarbeit;
Vertrauen und maximale Vertraulichkeit, um dieses Projekt erfolgreich zu
erreichen. Ich habe sorgfältig die Modalitäten für die Ausführung dieser
Transaktion unter einer legitimen Vereinbarung ausgearbeitet, um Sie vor
einer Verletzung des Gesetzes sowohl in Ihrem Land als auch hier in
England zu schützen, wenn der Fonds auf Ihr Bankkonto überwiesen wird.

 Ich wählte Sie wegen der geographischen Lage Ihres Landes und Ihrer
Adresse aus einem internationalen Firmenverzeichnis hier in der Londoner
Handelskammer. Der Hauptgrund, warum ich in diese Transaktion gehen
musste, ist, weil es keine moralische Rechtfertigung für die UBS Bank
gibt, diesen Fonds zu erben. Alles, was ich von Ihnen benötigte, ist Ihre
ehrlichste, aufrichtige, verständnisvolle und vertrauliche Zusammenarbeit.

Bei Rücksicht und Annahme dieses Angebots senden Sie mir bitte folgende
Informationen zu.

- Ihr vollständiger Name:
- Ihre Anschrift:
- Ihre direkte Mobilnummer:
- Ihr Beruf:
- Dein Geburtsdatum:
- Dein Geschlecht:

 Diese oben genannte Information wird es mir ermöglichen, Ihre Daten in
unsere Bankdatenbank einzufügen, um im Banksystem zu erscheinen, dass Sie
der benannte Nächste des Verwandten / Erben Begünstigten des Fonds sind,
und dann werde ich Ihre weitere Kommunikation mit der UBS Investment Bank
zur sofortigen Freigabe führen Und Übertragung des Fonds auf Ihr
designated Bankkonto, Ihre freundliche schnelle Antwort wird in hohem
Grade geschätzt, für mehr Details über dieses Geschäft Abkommen.

Vielen Dank in Anerkennung und Vorfreude auf Ihre dringende Antwort.

 Freundliche Grüße,

Dr. Andrew Kitchen,
Chief Operating Officer bei UBS Wealth Management UK.

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

[Arnd Bergmann]

On Fri, Jun 2, 2017 at 2:18 PM, Yan, Zheng  wrote:
> On Fri, Jun 2, 2017 at 7:33 PM, Arnd Bergmann  wrote:
>> On Fri, Jun 2, 2017 at 1:18 PM, Yan, Zheng  wrote:
>> What I meant is another related problem in ceph_mkdir() where the
>> i_ctime field of the parent inode is different between the persistent
>> representation in the mds and the in-memory representation.
>>
>
> I don't see any problem in mkdir case. Parent inode's i_ctime in mds is set to
> r_stamp. When client receives request reply, it set its in-memory inode's 
> ctime
> to the same time stamp.

Ok, I see it now, thanks for the clarification. Most other file systems do this
the other way round and update all fields in the in-memory inode structure
first and then write that to persistent storage, so I was getting confused about
the order of events here.

If I understand it all right, we have three different behaviors in ceph now,
though the differences are very minor and probably don't ever matter:

- in setattr(), we update ctime in the in-memory inode first and then send
  the same time to the mds, and expect to set it again when the reply comes.

- in ceph_write_iter write() and mmap/page_mkwrite(), we call
  file_update_time() to set i_mtime and i_ctime to the same
  timestamp first once a write is observed by the fs and then take
  two other timestamps that we send to the mds, and update the
  in-memory inode a second time when the reply comes. ctime
  is never older than mtime here, as far as I can tell, but it may
  be newer when the timer interrupt happens between taking the
  two stamps.

- in all other calls, we only update the inode (and/or parent inode)
  after the reply arrives.

   Arnd

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

[Arnd Bergmann]

On Fri, Jun 2, 2017 at 2:18 PM, Yan, Zheng  wrote:
> On Fri, Jun 2, 2017 at 7:33 PM, Arnd Bergmann  wrote:
>> On Fri, Jun 2, 2017 at 1:18 PM, Yan, Zheng  wrote:
>> What I meant is another related problem in ceph_mkdir() where the
>> i_ctime field of the parent inode is different between the persistent
>> representation in the mds and the in-memory representation.
>>
>
> I don't see any problem in mkdir case. Parent inode's i_ctime in mds is set to
> r_stamp. When client receives request reply, it set its in-memory inode's 
> ctime
> to the same time stamp.

Ok, I see it now, thanks for the clarification. Most other file systems do this
the other way round and update all fields in the in-memory inode structure
first and then write that to persistent storage, so I was getting confused about
the order of events here.

If I understand it all right, we have three different behaviors in ceph now,
though the differences are very minor and probably don't ever matter:

- in setattr(), we update ctime in the in-memory inode first and then send
  the same time to the mds, and expect to set it again when the reply comes.

- in ceph_write_iter write() and mmap/page_mkwrite(), we call
  file_update_time() to set i_mtime and i_ctime to the same
  timestamp first once a write is observed by the fs and then take
  two other timestamps that we send to the mds, and update the
  in-memory inode a second time when the reply comes. ctime
  is never older than mtime here, as far as I can tell, but it may
  be newer when the timer interrupt happens between taking the
  two stamps.

- in all other calls, we only update the inode (and/or parent inode)
  after the reply arrives.

   Arnd

Re: [PATCH V17 02/11] ras: acpi/apei: cper: add support for generic data v3 structure

[Will Deacon]

On Fri, May 19, 2017 at 02:32:04PM -0600, Tyler Baicar wrote:
> The ACPI 6.1 spec adds a new revision of the generic error data
> entry structure. Add support to handle the new structure as well
> as properly verify and iterate through the generic data entries.
> 
> Signed-off-by: Tyler Baicar 
> CC: Jonathan (Zhixiong) Zhang 
> ---
>  drivers/acpi/apei/ghes.c| 11 +--
>  drivers/firmware/efi/cper.c | 37 ++---
>  include/acpi/ghes.h | 36 
>  3 files changed, 63 insertions(+), 21 deletions(-)

Given that Boris and Rafael are ok with this series, it makes sense to
take this via arm64, but I need an ack from Ard or Matt on the EFI changes
in this patch and the subsequent one.

Will

[PATCH][V2] net: phy: marvell: make some functions static

[Colin King]

From: Colin Ian King 

functions m88e1510_get_temp_critical, m88e1510_set_temp_critical and
m88e1510_get_temp_alarm can be made static as they not need to be
in global scope.

Cleans up sparse warnings:
 "symbol 'm88e1510_get_temp_alarm' was not declared. Should it be static?"
 "symbol 'm88e1510_get_temp_critical' was not declared. Should it be
  static?"

Signed-off-by: Colin Ian King 
---
 drivers/net/phy/marvell.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 7c2cde45c262..7382b8fc77e2 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -1704,7 +1704,7 @@ static int m88e1510_get_temp(struct phy_device *phydev, 
long *temp)
return ret;
 }
 
-int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
+static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
 {
int oldpage;
int ret;
@@ -1735,7 +1735,7 @@ int m88e1510_get_temp_critical(struct phy_device *phydev, 
long *temp)
return ret;
 }
 
-int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
+static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
 {
int oldpage;
int ret;
@@ -1765,7 +1765,7 @@ int m88e1510_set_temp_critical(struct phy_device *phydev, 
long temp)
return ret;
 }
 
-int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
+static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
 {
int oldpage;
int ret;
-- 
2.11.0

Re: [PATCH V17 02/11] ras: acpi/apei: cper: add support for generic data v3 structure

[Will Deacon]

On Fri, May 19, 2017 at 02:32:04PM -0600, Tyler Baicar wrote:
> The ACPI 6.1 spec adds a new revision of the generic error data
> entry structure. Add support to handle the new structure as well
> as properly verify and iterate through the generic data entries.
> 
> Signed-off-by: Tyler Baicar 
> CC: Jonathan (Zhixiong) Zhang 
> ---
>  drivers/acpi/apei/ghes.c| 11 +--
>  drivers/firmware/efi/cper.c | 37 ++---
>  include/acpi/ghes.h | 36 
>  3 files changed, 63 insertions(+), 21 deletions(-)

Given that Boris and Rafael are ok with this series, it makes sense to
take this via arm64, but I need an ack from Ard or Matt on the EFI changes
in this patch and the subsequent one.

Will

[PATCH][V2] net: phy: marvell: make some functions static

[Colin King]

From: Colin Ian King 

functions m88e1510_get_temp_critical, m88e1510_set_temp_critical and
m88e1510_get_temp_alarm can be made static as they not need to be
in global scope.

Cleans up sparse warnings:
 "symbol 'm88e1510_get_temp_alarm' was not declared. Should it be static?"
 "symbol 'm88e1510_get_temp_critical' was not declared. Should it be
  static?"

Signed-off-by: Colin Ian King 
---
 drivers/net/phy/marvell.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 7c2cde45c262..7382b8fc77e2 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -1704,7 +1704,7 @@ static int m88e1510_get_temp(struct phy_device *phydev, 
long *temp)
return ret;
 }
 
-int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
+static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
 {
int oldpage;
int ret;
@@ -1735,7 +1735,7 @@ int m88e1510_get_temp_critical(struct phy_device *phydev, 
long *temp)
return ret;
 }
 
-int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
+static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
 {
int oldpage;
int ret;
@@ -1765,7 +1765,7 @@ int m88e1510_set_temp_critical(struct phy_device *phydev, 
long temp)
return ret;
 }
 
-int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
+static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
 {
int oldpage;
int ret;
-- 
2.11.0

[PATCH v3 08/27] thunderbolt: Introduce thunderbolt bus and connection manager

[Mika Westerberg]

Thunderbolt fabric consists of one or more switches. This fabric is
called domain and it is controlled by an entity called connection
manager. The connection manager can be either internal (driven by a
firmware running on the host controller) or external (software driver).
This driver currently implements support for the latter.

In order to manage switches and their properties more easily we model
this domain structure as a Linux bus. Each host controller adds a domain
device to this bus, and these devices are named as domainN where N
stands for index or id of the current domain.

We then abstract connection manager specific operations into a new
structure tb_cm_ops and convert the existing tb.c to fill those
accordingly. This makes it easier to add support for the internal
connection manager in subsequent patches.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/Makefile |   2 +-
 drivers/thunderbolt/domain.c | 229 +++
 drivers/thunderbolt/nhi.c|  31 --
 drivers/thunderbolt/tb.c | 156 --
 drivers/thunderbolt/tb.h |  70 +---
 drivers/thunderbolt/tunnel_pci.c |   9 +-
 6 files changed, 376 insertions(+), 121 deletions(-)
 create mode 100644 drivers/thunderbolt/domain.c

diff --git a/drivers/thunderbolt/Makefile b/drivers/thunderbolt/Makefile
index 5d1053cdfa54..e276a9a62261 100644
--- a/drivers/thunderbolt/Makefile
+++ b/drivers/thunderbolt/Makefile
@@ -1,3 +1,3 @@
 obj-${CONFIG_THUNDERBOLT} := thunderbolt.o
 thunderbolt-objs := nhi.o ctl.o tb.o switch.o cap.o path.o tunnel_pci.o 
eeprom.o
-
+thunderbolt-objs += domain.o
diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c
new file mode 100644
index ..e2f3777edee6
--- /dev/null
+++ b/drivers/thunderbolt/domain.c
@@ -0,0 +1,229 @@
+/*
+ * Thunderbolt bus support
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Author:  Mika Westerberg 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "tb.h"
+
+static DEFINE_IDA(tb_domain_ida);
+
+struct bus_type tb_bus_type = {
+   .name = "thunderbolt",
+};
+
+static void tb_domain_release(struct device *dev)
+{
+   struct tb *tb = container_of(dev, struct tb, dev);
+
+   tb_ctl_free(tb->ctl);
+   destroy_workqueue(tb->wq);
+   ida_simple_remove(_domain_ida, tb->index);
+   kfree(tb);
+}
+
+struct device_type tb_domain_type = {
+   .name = "thunderbolt_domain",
+   .release = tb_domain_release,
+};
+
+/**
+ * tb_domain_alloc() - Allocate a domain
+ * @nhi: Pointer to the host controller
+ * @privsize: Size of the connection manager private data
+ *
+ * Allocates and initializes a new Thunderbolt domain. Connection
+ * managers are expected to call this and then fill in @cm_ops
+ * accordingly.
+ *
+ * Call tb_domain_put() to release the domain before it has been added
+ * to the system.
+ *
+ * Return: allocated domain structure on %NULL in case of error
+ */
+struct tb *tb_domain_alloc(struct tb_nhi *nhi, size_t privsize)
+{
+   struct tb *tb;
+
+   /*
+* Make sure the structure sizes map with that the hardware
+* expects because bit-fields are being used.
+*/
+   BUILD_BUG_ON(sizeof(struct tb_regs_switch_header) != 5 * 4);
+   BUILD_BUG_ON(sizeof(struct tb_regs_port_header) != 8 * 4);
+   BUILD_BUG_ON(sizeof(struct tb_regs_hop) != 2 * 4);
+
+   tb = kzalloc(sizeof(*tb) + privsize, GFP_KERNEL);
+   if (!tb)
+   return NULL;
+
+   tb->nhi = nhi;
+   mutex_init(>lock);
+
+   tb->index = ida_simple_get(_domain_ida, 0, 0, GFP_KERNEL);
+   if (tb->index < 0)
+   goto err_free;
+
+   tb->wq = alloc_ordered_workqueue("thunderbolt%d", 0, tb->index);
+   if (!tb->wq)
+   goto err_remove_ida;
+
+   tb->dev.parent = >pdev->dev;
+   tb->dev.bus = _bus_type;
+   tb->dev.type = _domain_type;
+   dev_set_name(>dev, "domain%d", tb->index);
+   device_initialize(>dev);
+
+   return tb;
+
+err_remove_ida:
+   ida_simple_remove(_domain_ida, tb->index);
+err_free:
+   kfree(tb);
+
+   return NULL;
+}
+
+/**
+ * tb_domain_add() - Add domain to the system
+ * @tb: Domain to add
+ *
+ * Starts the domain and adds it to the system. Hotplugging devices will
+ * work after this has been returned successfully. In order to remove
+ * and release the domain after this function has been called, call
+ * tb_domain_remove().
+ *
+ * Return: %0 in case of success and negative errno in case of 

[PATCH v3 08/27] thunderbolt: Introduce thunderbolt bus and connection manager

[Mika Westerberg]

Thunderbolt fabric consists of one or more switches. This fabric is
called domain and it is controlled by an entity called connection
manager. The connection manager can be either internal (driven by a
firmware running on the host controller) or external (software driver).
This driver currently implements support for the latter.

In order to manage switches and their properties more easily we model
this domain structure as a Linux bus. Each host controller adds a domain
device to this bus, and these devices are named as domainN where N
stands for index or id of the current domain.

We then abstract connection manager specific operations into a new
structure tb_cm_ops and convert the existing tb.c to fill those
accordingly. This makes it easier to add support for the internal
connection manager in subsequent patches.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/Makefile |   2 +-
 drivers/thunderbolt/domain.c | 229 +++
 drivers/thunderbolt/nhi.c|  31 --
 drivers/thunderbolt/tb.c | 156 --
 drivers/thunderbolt/tb.h |  70 +---
 drivers/thunderbolt/tunnel_pci.c |   9 +-
 6 files changed, 376 insertions(+), 121 deletions(-)
 create mode 100644 drivers/thunderbolt/domain.c

diff --git a/drivers/thunderbolt/Makefile b/drivers/thunderbolt/Makefile
index 5d1053cdfa54..e276a9a62261 100644
--- a/drivers/thunderbolt/Makefile
+++ b/drivers/thunderbolt/Makefile
@@ -1,3 +1,3 @@
 obj-${CONFIG_THUNDERBOLT} := thunderbolt.o
 thunderbolt-objs := nhi.o ctl.o tb.o switch.o cap.o path.o tunnel_pci.o 
eeprom.o
-
+thunderbolt-objs += domain.o
diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c
new file mode 100644
index ..e2f3777edee6
--- /dev/null
+++ b/drivers/thunderbolt/domain.c
@@ -0,0 +1,229 @@
+/*
+ * Thunderbolt bus support
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Author:  Mika Westerberg 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "tb.h"
+
+static DEFINE_IDA(tb_domain_ida);
+
+struct bus_type tb_bus_type = {
+   .name = "thunderbolt",
+};
+
+static void tb_domain_release(struct device *dev)
+{
+   struct tb *tb = container_of(dev, struct tb, dev);
+
+   tb_ctl_free(tb->ctl);
+   destroy_workqueue(tb->wq);
+   ida_simple_remove(_domain_ida, tb->index);
+   kfree(tb);
+}
+
+struct device_type tb_domain_type = {
+   .name = "thunderbolt_domain",
+   .release = tb_domain_release,
+};
+
+/**
+ * tb_domain_alloc() - Allocate a domain
+ * @nhi: Pointer to the host controller
+ * @privsize: Size of the connection manager private data
+ *
+ * Allocates and initializes a new Thunderbolt domain. Connection
+ * managers are expected to call this and then fill in @cm_ops
+ * accordingly.
+ *
+ * Call tb_domain_put() to release the domain before it has been added
+ * to the system.
+ *
+ * Return: allocated domain structure on %NULL in case of error
+ */
+struct tb *tb_domain_alloc(struct tb_nhi *nhi, size_t privsize)
+{
+   struct tb *tb;
+
+   /*
+* Make sure the structure sizes map with that the hardware
+* expects because bit-fields are being used.
+*/
+   BUILD_BUG_ON(sizeof(struct tb_regs_switch_header) != 5 * 4);
+   BUILD_BUG_ON(sizeof(struct tb_regs_port_header) != 8 * 4);
+   BUILD_BUG_ON(sizeof(struct tb_regs_hop) != 2 * 4);
+
+   tb = kzalloc(sizeof(*tb) + privsize, GFP_KERNEL);
+   if (!tb)
+   return NULL;
+
+   tb->nhi = nhi;
+   mutex_init(>lock);
+
+   tb->index = ida_simple_get(_domain_ida, 0, 0, GFP_KERNEL);
+   if (tb->index < 0)
+   goto err_free;
+
+   tb->wq = alloc_ordered_workqueue("thunderbolt%d", 0, tb->index);
+   if (!tb->wq)
+   goto err_remove_ida;
+
+   tb->dev.parent = >pdev->dev;
+   tb->dev.bus = _bus_type;
+   tb->dev.type = _domain_type;
+   dev_set_name(>dev, "domain%d", tb->index);
+   device_initialize(>dev);
+
+   return tb;
+
+err_remove_ida:
+   ida_simple_remove(_domain_ida, tb->index);
+err_free:
+   kfree(tb);
+
+   return NULL;
+}
+
+/**
+ * tb_domain_add() - Add domain to the system
+ * @tb: Domain to add
+ *
+ * Starts the domain and adds it to the system. Hotplugging devices will
+ * work after this has been returned successfully. In order to remove
+ * and release the domain after this function has been called, call
+ * tb_domain_remove().
+ *
+ * Return: %0 in case of success and negative errno in case of error
+ */
+int tb_domain_add(struct tb *tb)
+{
+   int ret;
+
+   if (WARN_ON(!tb->cm_ops))
+   return -EINVAL;
+
+   

[PATCH v3 21/27] thunderbolt: Store Thunderbolt generation in the switch structure

[Mika Westerberg]

In some cases it is useful to know what is the Thunderbolt generation
the switch supports. This introduces a new field to struct switch that
stores the generation of the switch based on the device ID. Unknown
switches (there should be none) are assumed to be first generation to be
on the safe side.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/switch.c | 55 ++--
 drivers/thunderbolt/tb.h |  2 ++
 2 files changed, 40 insertions(+), 17 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 8006577590ed..56b99ad2099d 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -390,6 +390,42 @@ struct device_type tb_switch_type = {
.release = tb_switch_release,
 };
 
+static int tb_switch_get_generation(struct tb_switch *sw)
+{
+   switch (sw->config.device_id) {
+   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE:
+   case PCI_DEVICE_ID_INTEL_LIGHT_PEAK:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
+   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE:
+   return 1;
+
+   case PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
+   return 2;
+
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
+   return 3;
+
+   default:
+   /*
+* For unknown switches assume generation to be 1 to be
+* on the safe side.
+*/
+   tb_sw_warn(sw, "unsupported switch device id %#x\n",
+  sw->config.device_id);
+   return 1;
+   }
+}
+
 /**
  * tb_switch_alloc() - allocate a switch
  * @tb: Pointer to the owning domain
@@ -443,6 +479,8 @@ struct tb_switch *tb_switch_alloc(struct tb *tb, struct 
device *parent,
sw->ports[i].port = i;
}
 
+   sw->generation = tb_switch_get_generation(sw);
+
cap = tb_switch_find_vsec_cap(sw, TB_VSEC_CAP_PLUG_EVENTS);
if (cap < 0) {
tb_sw_warn(sw, "cannot find TB_VSEC_CAP_PLUG_EVENTS 
aborting\n");
@@ -491,23 +529,6 @@ int tb_switch_configure(struct tb_switch *sw)
tb_sw_warn(sw, "unknown switch vendor id %#x\n",
   sw->config.vendor_id);
 
-   switch (sw->config.device_id) {
-   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
-   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
-   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
-   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
-   break;
-
-   default:
-   tb_sw_warn(sw, "unsupported switch device id %#x\n",
-  sw->config.device_id);
-   }
-
sw->config.enabled = 1;
 
/* upload configuration */
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 0be989069941..b3cda7605619 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -25,6 +25,7 @@
  * @device: Device ID of the switch
  * @vendor_name: Name of the vendor (or %NULL if not known)
  * @device_name: Name of the device (or %NULL if not known)
+ * @generation: Switch Thunderbolt generation
  * @cap_plug_events: Offset to the plug events capability (%0 if not found)
  * @is_unplugged: The switch is going away
  * @drom: DROM of the switch (%NULL if not found)
@@ -40,6 +41,7 @@ struct tb_switch {
u16 device;
const char *vendor_name;
const char *device_name;
+   unsigned int generation;
int cap_plug_events;
bool is_unplugged;
u8 *drom;
-- 
2.11.0

[PATCH v3 21/27] thunderbolt: Store Thunderbolt generation in the switch structure

[Mika Westerberg]

In some cases it is useful to know what is the Thunderbolt generation
the switch supports. This introduces a new field to struct switch that
stores the generation of the switch based on the device ID. Unknown
switches (there should be none) are assumed to be first generation to be
on the safe side.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/switch.c | 55 ++--
 drivers/thunderbolt/tb.h |  2 ++
 2 files changed, 40 insertions(+), 17 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 8006577590ed..56b99ad2099d 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -390,6 +390,42 @@ struct device_type tb_switch_type = {
.release = tb_switch_release,
 };
 
+static int tb_switch_get_generation(struct tb_switch *sw)
+{
+   switch (sw->config.device_id) {
+   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE:
+   case PCI_DEVICE_ID_INTEL_LIGHT_PEAK:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
+   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE:
+   return 1;
+
+   case PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
+   return 2;
+
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
+   return 3;
+
+   default:
+   /*
+* For unknown switches assume generation to be 1 to be
+* on the safe side.
+*/
+   tb_sw_warn(sw, "unsupported switch device id %#x\n",
+  sw->config.device_id);
+   return 1;
+   }
+}
+
 /**
  * tb_switch_alloc() - allocate a switch
  * @tb: Pointer to the owning domain
@@ -443,6 +479,8 @@ struct tb_switch *tb_switch_alloc(struct tb *tb, struct 
device *parent,
sw->ports[i].port = i;
}
 
+   sw->generation = tb_switch_get_generation(sw);
+
cap = tb_switch_find_vsec_cap(sw, TB_VSEC_CAP_PLUG_EVENTS);
if (cap < 0) {
tb_sw_warn(sw, "cannot find TB_VSEC_CAP_PLUG_EVENTS 
aborting\n");
@@ -491,23 +529,6 @@ int tb_switch_configure(struct tb_switch *sw)
tb_sw_warn(sw, "unknown switch vendor id %#x\n",
   sw->config.vendor_id);
 
-   switch (sw->config.device_id) {
-   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
-   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
-   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
-   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
-   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
-   break;
-
-   default:
-   tb_sw_warn(sw, "unsupported switch device id %#x\n",
-  sw->config.device_id);
-   }
-
sw->config.enabled = 1;
 
/* upload configuration */
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 0be989069941..b3cda7605619 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -25,6 +25,7 @@
  * @device: Device ID of the switch
  * @vendor_name: Name of the vendor (or %NULL if not known)
  * @device_name: Name of the device (or %NULL if not known)
+ * @generation: Switch Thunderbolt generation
  * @cap_plug_events: Offset to the plug events capability (%0 if not found)
  * @is_unplugged: The switch is going away
  * @drom: DROM of the switch (%NULL if not found)
@@ -40,6 +41,7 @@ struct tb_switch {
u16 device;
const char *vendor_name;
const char *device_name;
+   unsigned int generation;
int cap_plug_events;
bool is_unplugged;
u8 *drom;
-- 
2.11.0

[PATCH v3 10/27] thunderbolt: Fail switch adding operation if reading DROM fails

[Mika Westerberg]

All non-root switches are expected to have DROM so if the operation
fails, it might be due the user unlugging the device. There is no point
continuing adding the switch further in that case. Just bail out.

For root switches (hosts) the DROM is either retrieved from a EFI
variable, NVM or hard-coded.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/switch.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 5cd854dedeea..0ce8b600a23f 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -535,8 +535,11 @@ int tb_switch_add(struct tb_switch *sw)
int i, ret;
 
/* read drom */
-   if (tb_drom_read(sw))
-   tb_sw_warn(sw, "tb_eeprom_read_rom failed, continuing\n");
+   ret = tb_drom_read(sw);
+   if (ret) {
+   tb_sw_warn(sw, "tb_eeprom_read_rom failed\n");
+   return ret;
+   }
tb_sw_info(sw, "uid: %#llx\n", sw->uid);
 
tb_switch_set_uuid(sw);
-- 
2.11.0

[PATCH v3 14/27] thunderbolt: Move control channel messages to tb_msgs.h

[Mika Westerberg]

We will be forwarding notifications received from the control channel to
the connection manager implementations. This way they can decide what to
do if anything when a notification is received.

To be able to use control channel messages from other files, move them
to tb_msgs.h.

No functional changes intended.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c |  76 -
 drivers/thunderbolt/ctl.h |  16 +--
 drivers/thunderbolt/tb_msgs.h | 108 ++
 3 files changed, 109 insertions(+), 91 deletions(-)
 create mode 100644 drivers/thunderbolt/tb_msgs.h

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index f8290a577b2b..24118c60b062 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -52,82 +52,6 @@ struct tb_ctl {
 #define tb_ctl_info(ctl, format, arg...) \
dev_info(&(ctl)->nhi->pdev->dev, format, ## arg)
 
-
-/* configuration packets definitions */
-
-enum tb_cfg_pkg_type {
-   TB_CFG_PKG_READ = 1,
-   TB_CFG_PKG_WRITE = 2,
-   TB_CFG_PKG_ERROR = 3,
-   TB_CFG_PKG_NOTIFY_ACK = 4,
-   TB_CFG_PKG_EVENT = 5,
-   TB_CFG_PKG_XDOMAIN_REQ = 6,
-   TB_CFG_PKG_XDOMAIN_RESP = 7,
-   TB_CFG_PKG_OVERRIDE = 8,
-   TB_CFG_PKG_RESET = 9,
-   TB_CFG_PKG_PREPARE_TO_SLEEP = 0xd,
-};
-
-/* common header */
-struct tb_cfg_header {
-   u32 route_hi:22;
-   u32 unknown:10; /* highest order bit is set on replies */
-   u32 route_lo;
-} __packed;
-
-/* additional header for read/write packets */
-struct tb_cfg_address {
-   u32 offset:13; /* in dwords */
-   u32 length:6; /* in dwords */
-   u32 port:6;
-   enum tb_cfg_space space:2;
-   u32 seq:2; /* sequence number  */
-   u32 zero:3;
-} __packed;
-
-/* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
-struct cfg_read_pkg {
-   struct tb_cfg_header header;
-   struct tb_cfg_address addr;
-} __packed;
-
-/* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
-struct cfg_write_pkg {
-   struct tb_cfg_header header;
-   struct tb_cfg_address addr;
-   u32 data[64]; /* maximum size, tb_cfg_address.length has 6 bits */
-} __packed;
-
-/* TB_CFG_PKG_ERROR */
-struct cfg_error_pkg {
-   struct tb_cfg_header header;
-   enum tb_cfg_error error:4;
-   u32 zero1:4;
-   u32 port:6;
-   u32 zero2:2; /* Both should be zero, still they are different fields. */
-   u32 zero3:16;
-} __packed;
-
-/* TB_CFG_PKG_EVENT */
-struct cfg_event_pkg {
-   struct tb_cfg_header header;
-   u32 port:6;
-   u32 zero:25;
-   bool unplug:1;
-} __packed;
-
-/* TB_CFG_PKG_RESET */
-struct cfg_reset_pkg {
-   struct tb_cfg_header header;
-} __packed;
-
-/* TB_CFG_PKG_PREPARE_TO_SLEEP */
-struct cfg_pts_pkg {
-   struct tb_cfg_header header;
-   u32 data;
-} __packed;
-
-
 /* utility functions */
 
 static u64 get_route(struct tb_cfg_header header)
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index 83ae54947082..610980e3232f 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -8,6 +8,7 @@
 #define _TB_CFG
 
 #include "nhi.h"
+#include "tb_msgs.h"
 
 /* control channel */
 struct tb_ctl;
@@ -23,21 +24,6 @@ void tb_ctl_free(struct tb_ctl *ctl);
 
 #define TB_CFG_DEFAULT_TIMEOUT 5000 /* msec */
 
-enum tb_cfg_space {
-   TB_CFG_HOPS = 0,
-   TB_CFG_PORT = 1,
-   TB_CFG_SWITCH = 2,
-   TB_CFG_COUNTERS = 3,
-};
-
-enum tb_cfg_error {
-   TB_CFG_ERROR_PORT_NOT_CONNECTED = 0,
-   TB_CFG_ERROR_INVALID_CONFIG_SPACE = 2,
-   TB_CFG_ERROR_NO_SUCH_PORT = 4,
-   TB_CFG_ERROR_ACK_PLUG_EVENT = 7, /* send as reply to TB_CFG_PKG_EVENT */
-   TB_CFG_ERROR_LOOP = 8,
-};
-
 struct tb_cfg_result {
u64 response_route;
u32 response_port; /*
diff --git a/drivers/thunderbolt/tb_msgs.h b/drivers/thunderbolt/tb_msgs.h
new file mode 100644
index ..761d56287149
--- /dev/null
+++ b/drivers/thunderbolt/tb_msgs.h
@@ -0,0 +1,108 @@
+/*
+ * Thunderbolt control channel messages
+ *
+ * Copyright (C) 2014 Andreas Noever 
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _TB_MSGS
+#define _TB_MSGS
+
+#include 
+
+enum tb_cfg_pkg_type {
+   TB_CFG_PKG_READ = 1,
+   TB_CFG_PKG_WRITE = 2,
+   TB_CFG_PKG_ERROR = 3,
+   TB_CFG_PKG_NOTIFY_ACK = 4,
+   TB_CFG_PKG_EVENT = 5,
+   TB_CFG_PKG_XDOMAIN_REQ = 6,
+   TB_CFG_PKG_XDOMAIN_RESP = 7,
+   TB_CFG_PKG_OVERRIDE = 8,
+   TB_CFG_PKG_RESET = 9,
+   

[PATCH v3 10/27] thunderbolt: Fail switch adding operation if reading DROM fails

[Mika Westerberg]

All non-root switches are expected to have DROM so if the operation
fails, it might be due the user unlugging the device. There is no point
continuing adding the switch further in that case. Just bail out.

For root switches (hosts) the DROM is either retrieved from a EFI
variable, NVM or hard-coded.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/switch.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 5cd854dedeea..0ce8b600a23f 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -535,8 +535,11 @@ int tb_switch_add(struct tb_switch *sw)
int i, ret;
 
/* read drom */
-   if (tb_drom_read(sw))
-   tb_sw_warn(sw, "tb_eeprom_read_rom failed, continuing\n");
+   ret = tb_drom_read(sw);
+   if (ret) {
+   tb_sw_warn(sw, "tb_eeprom_read_rom failed\n");
+   return ret;
+   }
tb_sw_info(sw, "uid: %#llx\n", sw->uid);
 
tb_switch_set_uuid(sw);
-- 
2.11.0

[PATCH v3 14/27] thunderbolt: Move control channel messages to tb_msgs.h

[Mika Westerberg]

We will be forwarding notifications received from the control channel to
the connection manager implementations. This way they can decide what to
do if anything when a notification is received.

To be able to use control channel messages from other files, move them
to tb_msgs.h.

No functional changes intended.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c |  76 -
 drivers/thunderbolt/ctl.h |  16 +--
 drivers/thunderbolt/tb_msgs.h | 108 ++
 3 files changed, 109 insertions(+), 91 deletions(-)
 create mode 100644 drivers/thunderbolt/tb_msgs.h

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index f8290a577b2b..24118c60b062 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -52,82 +52,6 @@ struct tb_ctl {
 #define tb_ctl_info(ctl, format, arg...) \
dev_info(&(ctl)->nhi->pdev->dev, format, ## arg)
 
-
-/* configuration packets definitions */
-
-enum tb_cfg_pkg_type {
-   TB_CFG_PKG_READ = 1,
-   TB_CFG_PKG_WRITE = 2,
-   TB_CFG_PKG_ERROR = 3,
-   TB_CFG_PKG_NOTIFY_ACK = 4,
-   TB_CFG_PKG_EVENT = 5,
-   TB_CFG_PKG_XDOMAIN_REQ = 6,
-   TB_CFG_PKG_XDOMAIN_RESP = 7,
-   TB_CFG_PKG_OVERRIDE = 8,
-   TB_CFG_PKG_RESET = 9,
-   TB_CFG_PKG_PREPARE_TO_SLEEP = 0xd,
-};
-
-/* common header */
-struct tb_cfg_header {
-   u32 route_hi:22;
-   u32 unknown:10; /* highest order bit is set on replies */
-   u32 route_lo;
-} __packed;
-
-/* additional header for read/write packets */
-struct tb_cfg_address {
-   u32 offset:13; /* in dwords */
-   u32 length:6; /* in dwords */
-   u32 port:6;
-   enum tb_cfg_space space:2;
-   u32 seq:2; /* sequence number  */
-   u32 zero:3;
-} __packed;
-
-/* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
-struct cfg_read_pkg {
-   struct tb_cfg_header header;
-   struct tb_cfg_address addr;
-} __packed;
-
-/* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
-struct cfg_write_pkg {
-   struct tb_cfg_header header;
-   struct tb_cfg_address addr;
-   u32 data[64]; /* maximum size, tb_cfg_address.length has 6 bits */
-} __packed;
-
-/* TB_CFG_PKG_ERROR */
-struct cfg_error_pkg {
-   struct tb_cfg_header header;
-   enum tb_cfg_error error:4;
-   u32 zero1:4;
-   u32 port:6;
-   u32 zero2:2; /* Both should be zero, still they are different fields. */
-   u32 zero3:16;
-} __packed;
-
-/* TB_CFG_PKG_EVENT */
-struct cfg_event_pkg {
-   struct tb_cfg_header header;
-   u32 port:6;
-   u32 zero:25;
-   bool unplug:1;
-} __packed;
-
-/* TB_CFG_PKG_RESET */
-struct cfg_reset_pkg {
-   struct tb_cfg_header header;
-} __packed;
-
-/* TB_CFG_PKG_PREPARE_TO_SLEEP */
-struct cfg_pts_pkg {
-   struct tb_cfg_header header;
-   u32 data;
-} __packed;
-
-
 /* utility functions */
 
 static u64 get_route(struct tb_cfg_header header)
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index 83ae54947082..610980e3232f 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -8,6 +8,7 @@
 #define _TB_CFG
 
 #include "nhi.h"
+#include "tb_msgs.h"
 
 /* control channel */
 struct tb_ctl;
@@ -23,21 +24,6 @@ void tb_ctl_free(struct tb_ctl *ctl);
 
 #define TB_CFG_DEFAULT_TIMEOUT 5000 /* msec */
 
-enum tb_cfg_space {
-   TB_CFG_HOPS = 0,
-   TB_CFG_PORT = 1,
-   TB_CFG_SWITCH = 2,
-   TB_CFG_COUNTERS = 3,
-};
-
-enum tb_cfg_error {
-   TB_CFG_ERROR_PORT_NOT_CONNECTED = 0,
-   TB_CFG_ERROR_INVALID_CONFIG_SPACE = 2,
-   TB_CFG_ERROR_NO_SUCH_PORT = 4,
-   TB_CFG_ERROR_ACK_PLUG_EVENT = 7, /* send as reply to TB_CFG_PKG_EVENT */
-   TB_CFG_ERROR_LOOP = 8,
-};
-
 struct tb_cfg_result {
u64 response_route;
u32 response_port; /*
diff --git a/drivers/thunderbolt/tb_msgs.h b/drivers/thunderbolt/tb_msgs.h
new file mode 100644
index ..761d56287149
--- /dev/null
+++ b/drivers/thunderbolt/tb_msgs.h
@@ -0,0 +1,108 @@
+/*
+ * Thunderbolt control channel messages
+ *
+ * Copyright (C) 2014 Andreas Noever 
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _TB_MSGS
+#define _TB_MSGS
+
+#include 
+
+enum tb_cfg_pkg_type {
+   TB_CFG_PKG_READ = 1,
+   TB_CFG_PKG_WRITE = 2,
+   TB_CFG_PKG_ERROR = 3,
+   TB_CFG_PKG_NOTIFY_ACK = 4,
+   TB_CFG_PKG_EVENT = 5,
+   TB_CFG_PKG_XDOMAIN_REQ = 6,
+   TB_CFG_PKG_XDOMAIN_RESP = 7,
+   TB_CFG_PKG_OVERRIDE = 8,
+   TB_CFG_PKG_RESET = 9,
+   TB_CFG_PKG_PREPARE_TO_SLEEP = 0xd,
+
+};
+
+enum tb_cfg_space {
+   TB_CFG_HOPS = 0,
+   TB_CFG_PORT = 1,
+   TB_CFG_SWITCH = 2,
+   

[PATCH v3 02/27] thunderbolt: No need to read UID of the root switch on resume

[Mika Westerberg]

The root switch is part of the host controller and cannot be physically
removed, so there is no point of reading UID again on resume in order to
check if the root switch is still the same.

Suggested-by: Andreas Noever 
Signed-off-by: Mika Westerberg 
---
 drivers/thunderbolt/switch.c | 29 ++---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index c6f30b1695a9..81f5164a6364 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -452,19 +452,26 @@ void tb_sw_set_unplugged(struct tb_switch *sw)
 int tb_switch_resume(struct tb_switch *sw)
 {
int i, err;
-   u64 uid;
tb_sw_info(sw, "resuming switch\n");
 
-   err = tb_drom_read_uid_only(sw, );
-   if (err) {
-   tb_sw_warn(sw, "uid read failed\n");
-   return err;
-   }
-   if (sw != sw->tb->root_switch && sw->uid != uid) {
-   tb_sw_info(sw,
-   "changed while suspended (uid %#llx -> %#llx)\n",
-   sw->uid, uid);
-   return -ENODEV;
+   /*
+* Check for UID of the connected switches except for root
+* switch which we assume cannot be removed.
+*/
+   if (tb_route(sw)) {
+   u64 uid;
+
+   err = tb_drom_read_uid_only(sw, );
+   if (err) {
+   tb_sw_warn(sw, "uid read failed\n");
+   return err;
+   }
+   if (sw->uid != uid) {
+   tb_sw_info(sw,
+   "changed while suspended (uid %#llx -> 
%#llx)\n",
+   sw->uid, uid);
+   return -ENODEV;
+   }
}
 
/* upload configuration */
-- 
2.11.0

[PATCH v3 09/27] thunderbolt: Convert switch to a device

[Mika Westerberg]

Thunderbolt domain consists of switches that are connected to each
other, forming a bus. This will convert each switch into a real Linux
device structure and adds them to the domain. The advantage here is
that we get all the goodies from the driver core, like reference
counting and sysfs hierarchy for free.

Also expose device identification information to the userspace via new
sysfs attributes.

In order to support internal connection manager (ICM) we separate switch
configuration into its own function (tb_switch_configure()) which is
only called by the existing native connection manager implementation
used on Macs.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |  22 ++
 drivers/thunderbolt/eeprom.c|   2 +
 drivers/thunderbolt/switch.c| 261 +++-
 drivers/thunderbolt/tb.c|  40 +++-
 drivers/thunderbolt/tb.h|  45 +++-
 5 files changed, 303 insertions(+), 67 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-thunderbolt

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
new file mode 100644
index ..9f1bd0086938
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -0,0 +1,22 @@
+What:  /sys/bus/thunderbolt/devices/.../device
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains id of this device extracted from
+   the device DROM.
+
+What:  /sys/bus/thunderbolt/devices/.../vendor
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains vendor id of this device extracted
+   from the device DROM.
+
+What:  /sys/bus/thunderbolt/devices/.../unique_id
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains unique_id string of this device.
+   This is either read from hardware registers (UUID on
+   newer hardware) or based on UID from the device DROM.
+   Can be used to uniquely identify particular device.
diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index eb2179c98b09..7e485e3ef27e 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -479,6 +479,8 @@ int tb_drom_read(struct tb_switch *sw)
goto err;
}
sw->uid = header->uid;
+   sw->vendor = header->vendor_id;
+   sw->device = header->model_id;
 
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
if (crc != header->data_crc32) {
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index c02079424d0e..5cd854dedeea 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -281,6 +281,9 @@ static int tb_plug_events_active(struct tb_switch *sw, bool 
active)
u32 data;
int res;
 
+   if (!sw->config.enabled)
+   return 0;
+
sw->config.plug_events_delay = 0xff;
res = tb_sw_write(sw, ((u32 *) >config) + 4, TB_CFG_SWITCH, 4, 1);
if (res)
@@ -307,36 +310,79 @@ static int tb_plug_events_active(struct tb_switch *sw, 
bool active)
   sw->cap_plug_events + 1, 1);
 }
 
+static ssize_t device_show(struct device *dev, struct device_attribute *attr,
+  char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
 
-/**
- * tb_switch_free() - free a tb_switch and all downstream switches
- */
-void tb_switch_free(struct tb_switch *sw)
+   return sprintf(buf, "%#x\n", sw->device);
+}
+static DEVICE_ATTR_RO(device);
+
+static ssize_t vendor_show(struct device *dev, struct device_attribute *attr,
+  char *buf)
 {
-   int i;
-   /* port 0 is the switch itself and never has a remote */
-   for (i = 1; i <= sw->config.max_port_number; i++) {
-   if (tb_is_upstream_port(>ports[i]))
-   continue;
-   if (sw->ports[i].remote)
-   tb_switch_free(sw->ports[i].remote->sw);
-   sw->ports[i].remote = NULL;
-   }
+   struct tb_switch *sw = tb_to_switch(dev);
 
-   if (!sw->is_unplugged)
-   tb_plug_events_active(sw, false);
+   return sprintf(buf, "%#x\n", sw->vendor);
+}
+static DEVICE_ATTR_RO(vendor);
+
+static ssize_t unique_id_show(struct device *dev, struct device_attribute 
*attr,
+ char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return sprintf(buf, 

[PATCH v3 02/27] thunderbolt: No need to read UID of the root switch on resume

[Mika Westerberg]

The root switch is part of the host controller and cannot be physically
removed, so there is no point of reading UID again on resume in order to
check if the root switch is still the same.

Suggested-by: Andreas Noever 
Signed-off-by: Mika Westerberg 
---
 drivers/thunderbolt/switch.c | 29 ++---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index c6f30b1695a9..81f5164a6364 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -452,19 +452,26 @@ void tb_sw_set_unplugged(struct tb_switch *sw)
 int tb_switch_resume(struct tb_switch *sw)
 {
int i, err;
-   u64 uid;
tb_sw_info(sw, "resuming switch\n");
 
-   err = tb_drom_read_uid_only(sw, );
-   if (err) {
-   tb_sw_warn(sw, "uid read failed\n");
-   return err;
-   }
-   if (sw != sw->tb->root_switch && sw->uid != uid) {
-   tb_sw_info(sw,
-   "changed while suspended (uid %#llx -> %#llx)\n",
-   sw->uid, uid);
-   return -ENODEV;
+   /*
+* Check for UID of the connected switches except for root
+* switch which we assume cannot be removed.
+*/
+   if (tb_route(sw)) {
+   u64 uid;
+
+   err = tb_drom_read_uid_only(sw, );
+   if (err) {
+   tb_sw_warn(sw, "uid read failed\n");
+   return err;
+   }
+   if (sw->uid != uid) {
+   tb_sw_info(sw,
+   "changed while suspended (uid %#llx -> 
%#llx)\n",
+   sw->uid, uid);
+   return -ENODEV;
+   }
}
 
/* upload configuration */
-- 
2.11.0

[PATCH v3 09/27] thunderbolt: Convert switch to a device

[Mika Westerberg]

Thunderbolt domain consists of switches that are connected to each
other, forming a bus. This will convert each switch into a real Linux
device structure and adds them to the domain. The advantage here is
that we get all the goodies from the driver core, like reference
counting and sysfs hierarchy for free.

Also expose device identification information to the userspace via new
sysfs attributes.

In order to support internal connection manager (ICM) we separate switch
configuration into its own function (tb_switch_configure()) which is
only called by the existing native connection manager implementation
used on Macs.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |  22 ++
 drivers/thunderbolt/eeprom.c|   2 +
 drivers/thunderbolt/switch.c| 261 +++-
 drivers/thunderbolt/tb.c|  40 +++-
 drivers/thunderbolt/tb.h|  45 +++-
 5 files changed, 303 insertions(+), 67 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-thunderbolt

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
new file mode 100644
index ..9f1bd0086938
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -0,0 +1,22 @@
+What:  /sys/bus/thunderbolt/devices/.../device
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains id of this device extracted from
+   the device DROM.
+
+What:  /sys/bus/thunderbolt/devices/.../vendor
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains vendor id of this device extracted
+   from the device DROM.
+
+What:  /sys/bus/thunderbolt/devices/.../unique_id
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains unique_id string of this device.
+   This is either read from hardware registers (UUID on
+   newer hardware) or based on UID from the device DROM.
+   Can be used to uniquely identify particular device.
diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index eb2179c98b09..7e485e3ef27e 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -479,6 +479,8 @@ int tb_drom_read(struct tb_switch *sw)
goto err;
}
sw->uid = header->uid;
+   sw->vendor = header->vendor_id;
+   sw->device = header->model_id;
 
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
if (crc != header->data_crc32) {
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index c02079424d0e..5cd854dedeea 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -281,6 +281,9 @@ static int tb_plug_events_active(struct tb_switch *sw, bool 
active)
u32 data;
int res;
 
+   if (!sw->config.enabled)
+   return 0;
+
sw->config.plug_events_delay = 0xff;
res = tb_sw_write(sw, ((u32 *) >config) + 4, TB_CFG_SWITCH, 4, 1);
if (res)
@@ -307,36 +310,79 @@ static int tb_plug_events_active(struct tb_switch *sw, 
bool active)
   sw->cap_plug_events + 1, 1);
 }
 
+static ssize_t device_show(struct device *dev, struct device_attribute *attr,
+  char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
 
-/**
- * tb_switch_free() - free a tb_switch and all downstream switches
- */
-void tb_switch_free(struct tb_switch *sw)
+   return sprintf(buf, "%#x\n", sw->device);
+}
+static DEVICE_ATTR_RO(device);
+
+static ssize_t vendor_show(struct device *dev, struct device_attribute *attr,
+  char *buf)
 {
-   int i;
-   /* port 0 is the switch itself and never has a remote */
-   for (i = 1; i <= sw->config.max_port_number; i++) {
-   if (tb_is_upstream_port(>ports[i]))
-   continue;
-   if (sw->ports[i].remote)
-   tb_switch_free(sw->ports[i].remote->sw);
-   sw->ports[i].remote = NULL;
-   }
+   struct tb_switch *sw = tb_to_switch(dev);
 
-   if (!sw->is_unplugged)
-   tb_plug_events_active(sw, false);
+   return sprintf(buf, "%#x\n", sw->vendor);
+}
+static DEVICE_ATTR_RO(vendor);
+
+static ssize_t unique_id_show(struct device *dev, struct device_attribute 
*attr,
+ char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return sprintf(buf, "%pUb\n", sw->uuid);
+}
+static DEVICE_ATTR_RO(unique_id);
+
+static struct attribute *switch_attrs[] = {
+   

[PATCH v3 11/27] thunderbolt: Do not fail if DROM data CRC32 is invalid

[Mika Westerberg]

There are devices out there where CRC32 of the DROM is not correct. One
reason for this is that the ICM firmware does not validate it and it
seems that neither does the Apple driver. To be able to support such
devices we continue parsing the DROM contents regardless of whether
CRC32 failed or not. We still keep the warning there.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 7e485e3ef27e..e2c1f8a45522 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -485,9 +485,8 @@ int tb_drom_read(struct tb_switch *sw)
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
if (crc != header->data_crc32) {
tb_sw_warn(sw,
-   "drom data crc32 mismatch (expected: %#x, got: %#x), 
aborting\n",
+   "drom data crc32 mismatch (expected: %#x, got: %#x), 
continuing\n",
header->data_crc32, crc);
-   goto err;
}
 
if (header->device_rom_revision > 2)
-- 
2.11.0

Re: [PATCH v3 00/19] Report power supply from hid-logitech-hidpp

[Dave Hansen]

On 06/02/2017 12:29 AM, Benjamin Tissoires wrote:
> On Jun 01 2017 or thereabouts, Bastien Nocera wrote:
>> On Thu, 2017-06-01 at 11:06 -0700, Dave Hansen wrote:
>>> On 03/27/2017 07:59 AM, Benjamin Tissoires wrote:
 this is finally a rework of the series that provides kernel
 power_supply
 for hidpp devices.

 This will allow upower to not handle those devices anymore and to
 have more
 immediate reportng of the device to the system.
>>> FWIW, I'm on Ubuntu 14.04, and upower *is* reporting my mouse battery
>>> as
>>> if it were a laptop battery.  It's mostly garbage, and always reports
>>> 0%, which makes upower always tell me my laptop is 2/3 charged (I
>>> have 2
>>> real batteries).
> Well, the exported battery might be sending levels instead of
> pourcentages. And upower needs to be upgraded to handle those :(

It sounds like there are a number of things here where newer kernels are
breaking older userspace.  It's also causing some very end-user visible
effects, like having folks' systems auto shut down because upower thinks
their batteries are dead.

Old versions of upower are obviously confused here.  It would be really
nice to ensure that newer kernels don't break it like this.

IOW, it would be really nice if this were treated like a regression,
because it's tantalizingly close.

Re: [PATCH] perf: fix perf test case 14 result reporting

[Arnaldo Carvalho de Melo]

Em Fri, Jun 02, 2017 at 11:09:36AM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu:
> > On 06/01/2017 11:04 PM, Jiri Olsa wrote:
> > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote:
> > >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu:
> > >>> Command perf test -v 14 (Setup struct perf_event_attr test)
> > >>> always reports success even if the test case fails.
> > >>> It works correctly if you also specify -F (for don't fork).
> > >>
> > >> Thanks for working on this, adding Jiri Olsa, that wrote this test
> > >> harness, so that he can check and provide his Acked-by or Reviewed-by,
> > >> Jiri?
> > >>
> > >> - Arnaldo
> > >>  
> > >>>root@s35lp76 perf]# ./perf test -v 14
> > >>>14: Setup struct perf_event_attr   :
> > >>>--- start ---
> > >>>running './tests/attr/test-record-no-delay'
> > >>>[ perf record: Woken up 1 times to write data ]
> > >>>[ perf record: Captured and wrote 0.002 MB /tmp/tmp4E1h7R/perf.data
> > >>>  (1 samples) ]
> > >>>expected task=0, got 1
> > >>>expected precise_ip=0, got 3
> > >>>expected wakeup_events=1, got 0
> > >>>FAILED './tests/attr/test-record-no-delay' - match failure
> > >>>test child finished with 0
> > >>> end 
> > >>>Setup struct perf_event_attr: Ok
> > >>>
> > >>> The reason for the wrong error reporting is the return value of the
> > >>> system() library call. It is called in run_dir() file tests/attr.c
> > >>> and returns the exit status, in above case 0xff00.
> > >>> This value is given as parameter to the exit() function which
> > >>> can only handle values 0-0xff.
> > >>> The child process terminates with exit value of 0 and the parent
> > >>> does not detect any error.
> > >>>
> > >>> This patch corrects the error reporting and prints the
> > >>> correct test result.
> > >>>
> > >>> Signed-off-by: Thomas Richter 
> > >>> Reviewed-by: Hendrik Brueckner 
> > >>> ---
> > >>>  tools/perf/tests/attr.c | 2 +-
> > >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/tools/perf/tests/attr.c b/tools/perf/tests/attr.c
> > >>> index 88dc51f..131b510 100644
> > >>> --- a/tools/perf/tests/attr.c
> > >>> +++ b/tools/perf/tests/attr.c
> > >>> @@ -150,7 +150,7 @@ static int run_dir(const char *d, const char *perf)
> > >>> snprintf(cmd, 3*PATH_MAX, PYTHON " %s/attr.py -d %s/attr/ -p %s 
> > >>> %.*s",
> > >>>  d, d, perf, vcnt, v);
> > >>>  
> > >>> -   return system(cmd);
> > >>> +   return system(cmd) ? TEST_FAIL : TEST_OK;
> > >>>  }
> > >>>  
> > >>>  int test__attr(int subtest __maybe_unused)
> > >>> -- 
> > >>> 2.9.3
> > > 
> > > seems ok, however "perf test attr" is broken ATM, since it wasn't updated
> > > for some time as it showed false 'Ok'
> > > 
> > > I started fixing it some time ago, but got distracted, if you are
> > > interested, you're welcome to pick up from my branch ;-)
> > > 
> > >   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git
> > >   perf/attr_test
> > > 
> > > thanks,
> > > jirka
> > > 
> > 
> > I have started work on perf tool very recently to get s390 support
> > working and up to date.
> > 
> > I downloaded your branch and discovered you have already fixed
> > another issue I run into this week. For example 
> > commit 070b9644981e ("perf tests attr: Do not store failed events")
> > 
> > I can certainly help you to get this test case operational again.
> > Maybe you need to pull some of your patches out of your backlog
> > and submit them the kernel to get to a common base to work on.
> > 
> > I suggest we should move the discussion to the linux-perf-users
> > mailing list.
> > 
> > Your thoughts?
> 
> If you have specific patches in Jiri's branch that you think are good to
> go, just point me to them and I'll cherry-pick them.
> 
> I'm looking now at the one you pointed out above (070b9644981e).

Just looked, but the cset comment should state what is the problem and
how it is solved, right now it has just a one line summary :-\

- Arnaldo

[PATCH v3 11/27] thunderbolt: Do not fail if DROM data CRC32 is invalid

[Mika Westerberg]

There are devices out there where CRC32 of the DROM is not correct. One
reason for this is that the ICM firmware does not validate it and it
seems that neither does the Apple driver. To be able to support such
devices we continue parsing the DROM contents regardless of whether
CRC32 failed or not. We still keep the warning there.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 7e485e3ef27e..e2c1f8a45522 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -485,9 +485,8 @@ int tb_drom_read(struct tb_switch *sw)
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
if (crc != header->data_crc32) {
tb_sw_warn(sw,
-   "drom data crc32 mismatch (expected: %#x, got: %#x), 
aborting\n",
+   "drom data crc32 mismatch (expected: %#x, got: %#x), 
continuing\n",
header->data_crc32, crc);
-   goto err;
}
 
if (header->device_rom_revision > 2)
-- 
2.11.0

Re: [PATCH v3 00/19] Report power supply from hid-logitech-hidpp

[Dave Hansen]

On 06/02/2017 12:29 AM, Benjamin Tissoires wrote:
> On Jun 01 2017 or thereabouts, Bastien Nocera wrote:
>> On Thu, 2017-06-01 at 11:06 -0700, Dave Hansen wrote:
>>> On 03/27/2017 07:59 AM, Benjamin Tissoires wrote:
 this is finally a rework of the series that provides kernel
 power_supply
 for hidpp devices.

 This will allow upower to not handle those devices anymore and to
 have more
 immediate reportng of the device to the system.
>>> FWIW, I'm on Ubuntu 14.04, and upower *is* reporting my mouse battery
>>> as
>>> if it were a laptop battery.  It's mostly garbage, and always reports
>>> 0%, which makes upower always tell me my laptop is 2/3 charged (I
>>> have 2
>>> real batteries).
> Well, the exported battery might be sending levels instead of
> pourcentages. And upower needs to be upgraded to handle those :(

It sounds like there are a number of things here where newer kernels are
breaking older userspace.  It's also causing some very end-user visible
effects, like having folks' systems auto shut down because upower thinks
their batteries are dead.

Old versions of upower are obviously confused here.  It would be really
nice to ensure that newer kernels don't break it like this.

IOW, it would be really nice if this were treated like a regression,
because it's tantalizingly close.

Re: [PATCH] perf: fix perf test case 14 result reporting

[Arnaldo Carvalho de Melo]

Em Fri, Jun 02, 2017 at 11:09:36AM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu:
> > On 06/01/2017 11:04 PM, Jiri Olsa wrote:
> > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote:
> > >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu:
> > >>> Command perf test -v 14 (Setup struct perf_event_attr test)
> > >>> always reports success even if the test case fails.
> > >>> It works correctly if you also specify -F (for don't fork).
> > >>
> > >> Thanks for working on this, adding Jiri Olsa, that wrote this test
> > >> harness, so that he can check and provide his Acked-by or Reviewed-by,
> > >> Jiri?
> > >>
> > >> - Arnaldo
> > >>  
> > >>>root@s35lp76 perf]# ./perf test -v 14
> > >>>14: Setup struct perf_event_attr   :
> > >>>--- start ---
> > >>>running './tests/attr/test-record-no-delay'
> > >>>[ perf record: Woken up 1 times to write data ]
> > >>>[ perf record: Captured and wrote 0.002 MB /tmp/tmp4E1h7R/perf.data
> > >>>  (1 samples) ]
> > >>>expected task=0, got 1
> > >>>expected precise_ip=0, got 3
> > >>>expected wakeup_events=1, got 0
> > >>>FAILED './tests/attr/test-record-no-delay' - match failure
> > >>>test child finished with 0
> > >>> end 
> > >>>Setup struct perf_event_attr: Ok
> > >>>
> > >>> The reason for the wrong error reporting is the return value of the
> > >>> system() library call. It is called in run_dir() file tests/attr.c
> > >>> and returns the exit status, in above case 0xff00.
> > >>> This value is given as parameter to the exit() function which
> > >>> can only handle values 0-0xff.
> > >>> The child process terminates with exit value of 0 and the parent
> > >>> does not detect any error.
> > >>>
> > >>> This patch corrects the error reporting and prints the
> > >>> correct test result.
> > >>>
> > >>> Signed-off-by: Thomas Richter 
> > >>> Reviewed-by: Hendrik Brueckner 
> > >>> ---
> > >>>  tools/perf/tests/attr.c | 2 +-
> > >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/tools/perf/tests/attr.c b/tools/perf/tests/attr.c
> > >>> index 88dc51f..131b510 100644
> > >>> --- a/tools/perf/tests/attr.c
> > >>> +++ b/tools/perf/tests/attr.c
> > >>> @@ -150,7 +150,7 @@ static int run_dir(const char *d, const char *perf)
> > >>> snprintf(cmd, 3*PATH_MAX, PYTHON " %s/attr.py -d %s/attr/ -p %s 
> > >>> %.*s",
> > >>>  d, d, perf, vcnt, v);
> > >>>  
> > >>> -   return system(cmd);
> > >>> +   return system(cmd) ? TEST_FAIL : TEST_OK;
> > >>>  }
> > >>>  
> > >>>  int test__attr(int subtest __maybe_unused)
> > >>> -- 
> > >>> 2.9.3
> > > 
> > > seems ok, however "perf test attr" is broken ATM, since it wasn't updated
> > > for some time as it showed false 'Ok'
> > > 
> > > I started fixing it some time ago, but got distracted, if you are
> > > interested, you're welcome to pick up from my branch ;-)
> > > 
> > >   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git
> > >   perf/attr_test
> > > 
> > > thanks,
> > > jirka
> > > 
> > 
> > I have started work on perf tool very recently to get s390 support
> > working and up to date.
> > 
> > I downloaded your branch and discovered you have already fixed
> > another issue I run into this week. For example 
> > commit 070b9644981e ("perf tests attr: Do not store failed events")
> > 
> > I can certainly help you to get this test case operational again.
> > Maybe you need to pull some of your patches out of your backlog
> > and submit them the kernel to get to a common base to work on.
> > 
> > I suggest we should move the discussion to the linux-perf-users
> > mailing list.
> > 
> > Your thoughts?
> 
> If you have specific patches in Jiri's branch that you think are good to
> go, just point me to them and I'll cherry-pick them.
> 
> I'm looking now at the one you pointed out above (070b9644981e).

Just looked, but the cset comment should state what is the problem and
how it is solved, right now it has just a one line summary :-\

- Arnaldo

Re: [PATCH v3 0/4] make some special clk as critical_clocks

[Heiko Stuebner]

Am Dienstag, 2. Mai 2017, 15:34:02 CEST schrieb Elaine Zhang:
> change in V3:
> reword the commit message,explain why the specific clocks are need to be 
> critical.
> 
> change in v2:
> fix up some clks which have their own driver, not need to set as critical 
> clocks
> 
> Elaine Zhang (4):
>   clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
>   clk: rockchip: rk3228: make noc and some special clk as
> critical_clocks
>   clk: rockchip: rk3288: make noc and some special clk as
> critical_clocks
>   clk: rockchip: rk3368: make some special clk as critical_clocks

applied all 4 for 4.13


Thanks
Heiko

Re: [PATCH v3 0/4] make some special clk as critical_clocks

[Heiko Stuebner]

Am Dienstag, 2. Mai 2017, 15:34:02 CEST schrieb Elaine Zhang:
> change in V3:
> reword the commit message,explain why the specific clocks are need to be 
> critical.
> 
> change in v2:
> fix up some clks which have their own driver, not need to set as critical 
> clocks
> 
> Elaine Zhang (4):
>   clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
>   clk: rockchip: rk3228: make noc and some special clk as
> critical_clocks
>   clk: rockchip: rk3288: make noc and some special clk as
> critical_clocks
>   clk: rockchip: rk3368: make some special clk as critical_clocks

applied all 4 for 4.13


Thanks
Heiko

Re: [PATCH 08/10] KVM: arm/arm64: vgic: Handle unshared mapped interrupts

[Marc Zyngier]

On 02/06/17 14:33, Christoffer Dall wrote:
> On Wed, May 24, 2017 at 10:13:21PM +0200, Eric Auger wrote:
>> Virtual interrupts directly mapped to physical interrupts require
>> some special care. Their pending and active state must be observed
>> at distributor level and not in the list register.
> 
> This is not entirely true.  There's a dependency, but there is also
> separate virtual vs. physical state, see below.

I think this stems for the usual confusion about the "pending and active
state" vs "pending and active states". Yes, the GIC spec is rubbish. Can
I state this again?

>>
>> Also a level sensitive interrupt's level is not toggled down by any
>> maintenance IRQ handler as the EOI is not trapped.
>>
>> This patch adds an host_irq field in vgic_irq struct to easily
>> get the irqchip state of the host irq. We also handle the
>> physical IRQ case in vgic_validate_injection and add helpers to
>> get the line level and active state.
>>
>> Signed-off-by: Eric Auger 
>> ---
>>  include/kvm/arm_vgic.h|  4 +++-
>>  virt/kvm/arm/arch_timer.c |  3 ++-
>>  virt/kvm/arm/vgic/vgic.c  | 44 ++--
>>  virt/kvm/arm/vgic/vgic.h  |  9 -
>>  4 files changed, 51 insertions(+), 9 deletions(-)
>>
>> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
>> index ef71858..695ebc7 100644
>> --- a/include/kvm/arm_vgic.h
>> +++ b/include/kvm/arm_vgic.h
>> @@ -112,6 +112,7 @@ struct vgic_irq {
>>  bool hw;/* Tied to HW IRQ */
>>  struct kref refcount;   /* Used for LPIs */
>>  u32 hwintid;/* HW INTID number */
>> +unsigned int host_irq;  /* linux irq corresponding to hwintid */
>>  union {
>>  u8 targets; /* GICv2 target VCPUs mask */
>>  u32 mpidr;  /* GICv3 target VCPU */
>> @@ -301,7 +302,8 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, 
>> unsigned int intid,
>>  bool level);
>>  int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int 
>> intid,
>> bool level);
>> -int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 
>> phys_irq);
>> +int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
>> +  u32 virt_irq, u32 phys_irq);
>>  int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
>>  bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
>>  
>> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
>> index 5976609..45f4779 100644
>> --- a/virt/kvm/arm/arch_timer.c
>> +++ b/virt/kvm/arm/arch_timer.c
>> @@ -651,7 +651,8 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
>>   * Tell the VGIC that the virtual interrupt is tied to a
>>   * physical interrupt. We do that once per VCPU.
>>   */
>> -ret = kvm_vgic_map_phys_irq(vcpu, vtimer->irq.irq, phys_irq);
>> +ret = kvm_vgic_map_phys_irq(vcpu, host_vtimer_irq,
>> +vtimer->irq.irq, phys_irq);
>>  if (ret)
>>  return ret;
>>  
>> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
>> index 83b24d2..aa0618c 100644
>> --- a/virt/kvm/arm/vgic/vgic.c
>> +++ b/virt/kvm/arm/vgic/vgic.c
>> @@ -137,6 +137,28 @@ void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq)
>>  kfree(irq);
>>  }
>>  
>> +bool irq_line_level(struct vgic_irq *irq)
>> +{
>> +bool line_level = irq->line_level;
>> +
>> +if (unlikely(is_unshared_mapped(irq)))
>> +WARN_ON(irq_get_irqchip_state(irq->host_irq,
>> +  IRQCHIP_STATE_PENDING,
>> +  _level));
>> +return line_level;
>> +}
> 
> This really looks fishy.  When do we need this exactly?
> 
> I feel like we should treat this more like everything else and set the
> line_level on the irq even for forwarded interrupts, and then you don't
> need changes to validate injection.
> 
> The challenge, then, is how to re-sample the line and lower the
> line_level field when necessary.  Can't we simply do this in
> vgic_fold_lr_state(), and if you have a forwarded interrupt which is
> level triggered and the level is high, then notify the one who injected
> this and tell it to adjust its line level (lower it if it changed).
> 
> That would follow our existing path very closely.
> 
> Am I missing something?

I don't think you are. I think Eric got confused because of the above.
But the flow is a bit a brainfsck :-(

- Physical interrupt fires, activated, injected in the vgic
- Injecting the interrupt has a very different flow from what we
currently have, and follow the same pattern as an Edge interrupt
(because the Pending state is kept at the physical distributor, so we
cannot preserve it in the emulation).
- Normal life cycle of the interrupt
- The fact that the Pending bit is kept at the 

Re: [PATCH 08/10] KVM: arm/arm64: vgic: Handle unshared mapped interrupts

[Marc Zyngier]

On 02/06/17 14:33, Christoffer Dall wrote:
> On Wed, May 24, 2017 at 10:13:21PM +0200, Eric Auger wrote:
>> Virtual interrupts directly mapped to physical interrupts require
>> some special care. Their pending and active state must be observed
>> at distributor level and not in the list register.
> 
> This is not entirely true.  There's a dependency, but there is also
> separate virtual vs. physical state, see below.

I think this stems for the usual confusion about the "pending and active
state" vs "pending and active states". Yes, the GIC spec is rubbish. Can
I state this again?

>>
>> Also a level sensitive interrupt's level is not toggled down by any
>> maintenance IRQ handler as the EOI is not trapped.
>>
>> This patch adds an host_irq field in vgic_irq struct to easily
>> get the irqchip state of the host irq. We also handle the
>> physical IRQ case in vgic_validate_injection and add helpers to
>> get the line level and active state.
>>
>> Signed-off-by: Eric Auger 
>> ---
>>  include/kvm/arm_vgic.h|  4 +++-
>>  virt/kvm/arm/arch_timer.c |  3 ++-
>>  virt/kvm/arm/vgic/vgic.c  | 44 ++--
>>  virt/kvm/arm/vgic/vgic.h  |  9 -
>>  4 files changed, 51 insertions(+), 9 deletions(-)
>>
>> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
>> index ef71858..695ebc7 100644
>> --- a/include/kvm/arm_vgic.h
>> +++ b/include/kvm/arm_vgic.h
>> @@ -112,6 +112,7 @@ struct vgic_irq {
>>  bool hw;/* Tied to HW IRQ */
>>  struct kref refcount;   /* Used for LPIs */
>>  u32 hwintid;/* HW INTID number */
>> +unsigned int host_irq;  /* linux irq corresponding to hwintid */
>>  union {
>>  u8 targets; /* GICv2 target VCPUs mask */
>>  u32 mpidr;  /* GICv3 target VCPU */
>> @@ -301,7 +302,8 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, 
>> unsigned int intid,
>>  bool level);
>>  int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int 
>> intid,
>> bool level);
>> -int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 
>> phys_irq);
>> +int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
>> +  u32 virt_irq, u32 phys_irq);
>>  int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
>>  bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
>>  
>> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
>> index 5976609..45f4779 100644
>> --- a/virt/kvm/arm/arch_timer.c
>> +++ b/virt/kvm/arm/arch_timer.c
>> @@ -651,7 +651,8 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
>>   * Tell the VGIC that the virtual interrupt is tied to a
>>   * physical interrupt. We do that once per VCPU.
>>   */
>> -ret = kvm_vgic_map_phys_irq(vcpu, vtimer->irq.irq, phys_irq);
>> +ret = kvm_vgic_map_phys_irq(vcpu, host_vtimer_irq,
>> +vtimer->irq.irq, phys_irq);
>>  if (ret)
>>  return ret;
>>  
>> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
>> index 83b24d2..aa0618c 100644
>> --- a/virt/kvm/arm/vgic/vgic.c
>> +++ b/virt/kvm/arm/vgic/vgic.c
>> @@ -137,6 +137,28 @@ void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq)
>>  kfree(irq);
>>  }
>>  
>> +bool irq_line_level(struct vgic_irq *irq)
>> +{
>> +bool line_level = irq->line_level;
>> +
>> +if (unlikely(is_unshared_mapped(irq)))
>> +WARN_ON(irq_get_irqchip_state(irq->host_irq,
>> +  IRQCHIP_STATE_PENDING,
>> +  _level));
>> +return line_level;
>> +}
> 
> This really looks fishy.  When do we need this exactly?
> 
> I feel like we should treat this more like everything else and set the
> line_level on the irq even for forwarded interrupts, and then you don't
> need changes to validate injection.
> 
> The challenge, then, is how to re-sample the line and lower the
> line_level field when necessary.  Can't we simply do this in
> vgic_fold_lr_state(), and if you have a forwarded interrupt which is
> level triggered and the level is high, then notify the one who injected
> this and tell it to adjust its line level (lower it if it changed).
> 
> That would follow our existing path very closely.
> 
> Am I missing something?

I don't think you are. I think Eric got confused because of the above.
But the flow is a bit a brainfsck :-(

- Physical interrupt fires, activated, injected in the vgic
- Injecting the interrupt has a very different flow from what we
currently have, and follow the same pattern as an Edge interrupt
(because the Pending state is kept at the physical distributor, so we
cannot preserve it in the emulation).
- Normal life cycle of the interrupt
- The fact that the Pending bit is kept at the distributor level ensures

[PATCH v3 13/27] thunderbolt: Read vendor and device name from DROM

[Mika Westerberg]

The device DROM contains name of the vendor and device among other
things. Extract this information and expose it to the userspace via two
new attributes.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt | 14 +++
 drivers/thunderbolt/eeprom.c| 32 +
 drivers/thunderbolt/switch.c| 22 +
 drivers/thunderbolt/tb.h|  4 
 4 files changed, 72 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 9f1bd0086938..29a516f53d2c 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -5,6 +5,13 @@ Contact:   thunderbolt-softw...@lists.01.org
 Description:   This attribute contains id of this device extracted from
the device DROM.
 
+What:  /sys/bus/thunderbolt/devices/.../device_name
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains name of this device extracted from
+   the device DROM.
+
 What:  /sys/bus/thunderbolt/devices/.../vendor
 Date:  Sep 2017
 KernelVersion: 4.13
@@ -12,6 +19,13 @@ Contact: thunderbolt-softw...@lists.01.org
 Description:   This attribute contains vendor id of this device extracted
from the device DROM.
 
+What:  /sys/bus/thunderbolt/devices/.../vendor_name
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains vendor name of this device extracted
+   from the device DROM.
+
 What:  /sys/bus/thunderbolt/devices/.../unique_id
 Date:  Sep 2017
 KernelVersion: 4.13
diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 5c7d80a109b1..d40a5f07fc4c 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -204,6 +204,11 @@ struct tb_drom_entry_header {
enum tb_drom_entry_type type:1;
 } __packed;
 
+struct tb_drom_entry_generic {
+   struct tb_drom_entry_header header;
+   u8 data[0];
+} __packed;
+
 struct tb_drom_entry_port {
/* BYTES 0-1 */
struct tb_drom_entry_header header;
@@ -295,6 +300,32 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
return 0;
 }
 
+static int tb_drom_parse_entry_generic(struct tb_switch *sw,
+   struct tb_drom_entry_header *header)
+{
+   const struct tb_drom_entry_generic *entry =
+   (const struct tb_drom_entry_generic *)header;
+
+   switch (header->index) {
+   case 1:
+   /* Length includes 2 bytes header so remove it before copy */
+   sw->vendor_name = kstrndup(entry->data,
+   header->len - sizeof(*header), GFP_KERNEL);
+   if (!sw->vendor_name)
+   return -ENOMEM;
+   break;
+
+   case 2:
+   sw->device_name = kstrndup(entry->data,
+   header->len - sizeof(*header), GFP_KERNEL);
+   if (!sw->device_name)
+   return -ENOMEM;
+   break;
+   }
+
+   return 0;
+}
+
 static int tb_drom_parse_entry_port(struct tb_switch *sw,
struct tb_drom_entry_header *header)
 {
@@ -350,6 +381,7 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
 
switch (entry->type) {
case TB_DROM_ENTRY_GENERIC:
+   res = tb_drom_parse_entry_generic(sw, entry);
break;
case TB_DROM_ENTRY_PORT:
res = tb_drom_parse_entry_port(sw, entry);
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 0ce8b600a23f..0a592ccb7923 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -319,6 +319,15 @@ static ssize_t device_show(struct device *dev, struct 
device_attribute *attr,
 }
 static DEVICE_ATTR_RO(device);
 
+static ssize_t
+device_name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return sprintf(buf, "%s\n", sw->device_name ? sw->device_name : "");
+}
+static DEVICE_ATTR_RO(device_name);
+
 static ssize_t vendor_show(struct device *dev, struct device_attribute *attr,
   char *buf)
 {
@@ -328,6 +337,15 @@ static ssize_t vendor_show(struct device *dev, struct 
device_attribute *attr,
 }
 static DEVICE_ATTR_RO(vendor);
 
+static ssize_t
+vendor_name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return 

Re: [PATCH] perf: fix perf test case 14 result reporting

[Arnaldo Carvalho de Melo]

Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu:
> On 06/01/2017 11:04 PM, Jiri Olsa wrote:
> > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote:
> >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu:
> >>> Command perf test -v 14 (Setup struct perf_event_attr test)
> >>> always reports success even if the test case fails.
> >>> It works correctly if you also specify -F (for don't fork).
> >>
> >> Thanks for working on this, adding Jiri Olsa, that wrote this test
> >> harness, so that he can check and provide his Acked-by or Reviewed-by,
> >> Jiri?
> >>
> >> - Arnaldo
> >>  
> >>>root@s35lp76 perf]# ./perf test -v 14
> >>>14: Setup struct perf_event_attr   :
> >>>--- start ---
> >>>running './tests/attr/test-record-no-delay'
> >>>[ perf record: Woken up 1 times to write data ]
> >>>[ perf record: Captured and wrote 0.002 MB /tmp/tmp4E1h7R/perf.data
> >>>  (1 samples) ]
> >>>expected task=0, got 1
> >>>expected precise_ip=0, got 3
> >>>expected wakeup_events=1, got 0
> >>>FAILED './tests/attr/test-record-no-delay' - match failure
> >>>test child finished with 0
> >>> end 
> >>>Setup struct perf_event_attr: Ok
> >>>
> >>> The reason for the wrong error reporting is the return value of the
> >>> system() library call. It is called in run_dir() file tests/attr.c
> >>> and returns the exit status, in above case 0xff00.
> >>> This value is given as parameter to the exit() function which
> >>> can only handle values 0-0xff.
> >>> The child process terminates with exit value of 0 and the parent
> >>> does not detect any error.
> >>>
> >>> This patch corrects the error reporting and prints the
> >>> correct test result.
> >>>
> >>> Signed-off-by: Thomas Richter 
> >>> Reviewed-by: Hendrik Brueckner 
> >>> ---
> >>>  tools/perf/tests/attr.c | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/tools/perf/tests/attr.c b/tools/perf/tests/attr.c
> >>> index 88dc51f..131b510 100644
> >>> --- a/tools/perf/tests/attr.c
> >>> +++ b/tools/perf/tests/attr.c
> >>> @@ -150,7 +150,7 @@ static int run_dir(const char *d, const char *perf)
> >>>   snprintf(cmd, 3*PATH_MAX, PYTHON " %s/attr.py -d %s/attr/ -p %s %.*s",
> >>>d, d, perf, vcnt, v);
> >>>  
> >>> - return system(cmd);
> >>> + return system(cmd) ? TEST_FAIL : TEST_OK;
> >>>  }
> >>>  
> >>>  int test__attr(int subtest __maybe_unused)
> >>> -- 
> >>> 2.9.3
> > 
> > seems ok, however "perf test attr" is broken ATM, since it wasn't updated
> > for some time as it showed false 'Ok'
> > 
> > I started fixing it some time ago, but got distracted, if you are
> > interested, you're welcome to pick up from my branch ;-)
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git
> >   perf/attr_test
> > 
> > thanks,
> > jirka
> > 
> 
> I have started work on perf tool very recently to get s390 support
> working and up to date.
> 
> I downloaded your branch and discovered you have already fixed
> another issue I run into this week. For example 
> commit 070b9644981e ("perf tests attr: Do not store failed events")
> 
> I can certainly help you to get this test case operational again.
> Maybe you need to pull some of your patches out of your backlog
> and submit them the kernel to get to a common base to work on.
> 
> I suggest we should move the discussion to the linux-perf-users
> mailing list.
> 
> Your thoughts?

If you have specific patches in Jiri's branch that you think are good to
go, just point me to them and I'll cherry-pick them.

I'm looking now at the one you pointed out above (070b9644981e).

Thanks,

- Arnaldo

[PATCH v3 13/27] thunderbolt: Read vendor and device name from DROM

[Mika Westerberg]

The device DROM contains name of the vendor and device among other
things. Extract this information and expose it to the userspace via two
new attributes.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt | 14 +++
 drivers/thunderbolt/eeprom.c| 32 +
 drivers/thunderbolt/switch.c| 22 +
 drivers/thunderbolt/tb.h|  4 
 4 files changed, 72 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 9f1bd0086938..29a516f53d2c 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -5,6 +5,13 @@ Contact:   thunderbolt-softw...@lists.01.org
 Description:   This attribute contains id of this device extracted from
the device DROM.
 
+What:  /sys/bus/thunderbolt/devices/.../device_name
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains name of this device extracted from
+   the device DROM.
+
 What:  /sys/bus/thunderbolt/devices/.../vendor
 Date:  Sep 2017
 KernelVersion: 4.13
@@ -12,6 +19,13 @@ Contact: thunderbolt-softw...@lists.01.org
 Description:   This attribute contains vendor id of this device extracted
from the device DROM.
 
+What:  /sys/bus/thunderbolt/devices/.../vendor_name
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute contains vendor name of this device extracted
+   from the device DROM.
+
 What:  /sys/bus/thunderbolt/devices/.../unique_id
 Date:  Sep 2017
 KernelVersion: 4.13
diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 5c7d80a109b1..d40a5f07fc4c 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -204,6 +204,11 @@ struct tb_drom_entry_header {
enum tb_drom_entry_type type:1;
 } __packed;
 
+struct tb_drom_entry_generic {
+   struct tb_drom_entry_header header;
+   u8 data[0];
+} __packed;
+
 struct tb_drom_entry_port {
/* BYTES 0-1 */
struct tb_drom_entry_header header;
@@ -295,6 +300,32 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
return 0;
 }
 
+static int tb_drom_parse_entry_generic(struct tb_switch *sw,
+   struct tb_drom_entry_header *header)
+{
+   const struct tb_drom_entry_generic *entry =
+   (const struct tb_drom_entry_generic *)header;
+
+   switch (header->index) {
+   case 1:
+   /* Length includes 2 bytes header so remove it before copy */
+   sw->vendor_name = kstrndup(entry->data,
+   header->len - sizeof(*header), GFP_KERNEL);
+   if (!sw->vendor_name)
+   return -ENOMEM;
+   break;
+
+   case 2:
+   sw->device_name = kstrndup(entry->data,
+   header->len - sizeof(*header), GFP_KERNEL);
+   if (!sw->device_name)
+   return -ENOMEM;
+   break;
+   }
+
+   return 0;
+}
+
 static int tb_drom_parse_entry_port(struct tb_switch *sw,
struct tb_drom_entry_header *header)
 {
@@ -350,6 +381,7 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
 
switch (entry->type) {
case TB_DROM_ENTRY_GENERIC:
+   res = tb_drom_parse_entry_generic(sw, entry);
break;
case TB_DROM_ENTRY_PORT:
res = tb_drom_parse_entry_port(sw, entry);
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 0ce8b600a23f..0a592ccb7923 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -319,6 +319,15 @@ static ssize_t device_show(struct device *dev, struct 
device_attribute *attr,
 }
 static DEVICE_ATTR_RO(device);
 
+static ssize_t
+device_name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return sprintf(buf, "%s\n", sw->device_name ? sw->device_name : "");
+}
+static DEVICE_ATTR_RO(device_name);
+
 static ssize_t vendor_show(struct device *dev, struct device_attribute *attr,
   char *buf)
 {
@@ -328,6 +337,15 @@ static ssize_t vendor_show(struct device *dev, struct 
device_attribute *attr,
 }
 static DEVICE_ATTR_RO(vendor);
 
+static ssize_t
+vendor_name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+   struct tb_switch *sw = tb_to_switch(dev);
+
+   return sprintf(buf, "%s\n", sw->vendor_name ? sw->vendor_name : "");
+}
+static 

Re: [PATCH] perf: fix perf test case 14 result reporting

[Arnaldo Carvalho de Melo]

Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu:
> On 06/01/2017 11:04 PM, Jiri Olsa wrote:
> > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote:
> >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu:
> >>> Command perf test -v 14 (Setup struct perf_event_attr test)
> >>> always reports success even if the test case fails.
> >>> It works correctly if you also specify -F (for don't fork).
> >>
> >> Thanks for working on this, adding Jiri Olsa, that wrote this test
> >> harness, so that he can check and provide his Acked-by or Reviewed-by,
> >> Jiri?
> >>
> >> - Arnaldo
> >>  
> >>>root@s35lp76 perf]# ./perf test -v 14
> >>>14: Setup struct perf_event_attr   :
> >>>--- start ---
> >>>running './tests/attr/test-record-no-delay'
> >>>[ perf record: Woken up 1 times to write data ]
> >>>[ perf record: Captured and wrote 0.002 MB /tmp/tmp4E1h7R/perf.data
> >>>  (1 samples) ]
> >>>expected task=0, got 1
> >>>expected precise_ip=0, got 3
> >>>expected wakeup_events=1, got 0
> >>>FAILED './tests/attr/test-record-no-delay' - match failure
> >>>test child finished with 0
> >>> end 
> >>>Setup struct perf_event_attr: Ok
> >>>
> >>> The reason for the wrong error reporting is the return value of the
> >>> system() library call. It is called in run_dir() file tests/attr.c
> >>> and returns the exit status, in above case 0xff00.
> >>> This value is given as parameter to the exit() function which
> >>> can only handle values 0-0xff.
> >>> The child process terminates with exit value of 0 and the parent
> >>> does not detect any error.
> >>>
> >>> This patch corrects the error reporting and prints the
> >>> correct test result.
> >>>
> >>> Signed-off-by: Thomas Richter 
> >>> Reviewed-by: Hendrik Brueckner 
> >>> ---
> >>>  tools/perf/tests/attr.c | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/tools/perf/tests/attr.c b/tools/perf/tests/attr.c
> >>> index 88dc51f..131b510 100644
> >>> --- a/tools/perf/tests/attr.c
> >>> +++ b/tools/perf/tests/attr.c
> >>> @@ -150,7 +150,7 @@ static int run_dir(const char *d, const char *perf)
> >>>   snprintf(cmd, 3*PATH_MAX, PYTHON " %s/attr.py -d %s/attr/ -p %s %.*s",
> >>>d, d, perf, vcnt, v);
> >>>  
> >>> - return system(cmd);
> >>> + return system(cmd) ? TEST_FAIL : TEST_OK;
> >>>  }
> >>>  
> >>>  int test__attr(int subtest __maybe_unused)
> >>> -- 
> >>> 2.9.3
> > 
> > seems ok, however "perf test attr" is broken ATM, since it wasn't updated
> > for some time as it showed false 'Ok'
> > 
> > I started fixing it some time ago, but got distracted, if you are
> > interested, you're welcome to pick up from my branch ;-)
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git
> >   perf/attr_test
> > 
> > thanks,
> > jirka
> > 
> 
> I have started work on perf tool very recently to get s390 support
> working and up to date.
> 
> I downloaded your branch and discovered you have already fixed
> another issue I run into this week. For example 
> commit 070b9644981e ("perf tests attr: Do not store failed events")
> 
> I can certainly help you to get this test case operational again.
> Maybe you need to pull some of your patches out of your backlog
> and submit them the kernel to get to a common base to work on.
> 
> I suggest we should move the discussion to the linux-perf-users
> mailing list.
> 
> Your thoughts?

If you have specific patches in Jiri's branch that you think are good to
go, just point me to them and I'll cherry-pick them.

I'm looking now at the one you pointed out above (070b9644981e).

Thanks,

- Arnaldo

[PATCH v3 23/27] thunderbolt: Do not touch the hardware if the NHI is gone on resume

[Mika Westerberg]

On PCs the NHI host controller is only present when there is a device
connected. When the last device is disconnected the host controller will
dissappear shortly (within 10s). Now if that happens when we are
suspended we should not try to touch the hardware anymore, so add a flag
for this and check it before we re-enable rings.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c | 12 
 drivers/thunderbolt/nhi.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index c358c074f925..14311535661d 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -403,6 +403,8 @@ void ring_start(struct tb_ring *ring)
 {
mutex_lock(>nhi->lock);
mutex_lock(>lock);
+   if (ring->nhi->going_away)
+   goto err;
if (ring->running) {
dev_WARN(>nhi->pdev->dev, "ring already started\n");
goto err;
@@ -449,6 +451,8 @@ void ring_stop(struct tb_ring *ring)
mutex_lock(>lock);
dev_info(>nhi->pdev->dev, "stopping %s %d\n",
 RING_TYPE(ring), ring->hop);
+   if (ring->nhi->going_away)
+   goto err;
if (!ring->running) {
dev_WARN(>nhi->pdev->dev, "%s %d already stopped\n",
 RING_TYPE(ring), ring->hop);
@@ -653,6 +657,14 @@ static int nhi_resume_noirq(struct device *dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct tb *tb = pci_get_drvdata(pdev);
 
+   /*
+* Check that the device is still there. It may be that the user
+* unplugged last device which causes the host controller to go
+* away on PCs.
+*/
+   if (!pci_device_is_present(pdev))
+   tb->nhi->going_away = true;
+
return tb_domain_resume_noirq(tb);
 }
 
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 446ff6dac91d..953864ae0ab3 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -20,6 +20,8 @@
  * @tx_rings: All Tx rings available on this host controller
  * @rx_rings: All Rx rings available on this host controller
  * @msix_ida: Used to allocate MSI-X vectors for rings
+ * @going_away: The host controller device is about to disappear so when
+ * this flag is set, avoid touching the hardware anymore.
  * @interrupt_work: Work scheduled to handle ring interrupt when no
  * MSI-X is used.
  * @hop_count: Number of rings (end point hops) supported by NHI.
@@ -31,6 +33,7 @@ struct tb_nhi {
struct tb_ring **tx_rings;
struct tb_ring **rx_rings;
struct ida msix_ida;
+   bool going_away;
struct work_struct interrupt_work;
u32 hop_count;
 };
-- 
2.11.0

[PATCH v3 23/27] thunderbolt: Do not touch the hardware if the NHI is gone on resume

[Mika Westerberg]

On PCs the NHI host controller is only present when there is a device
connected. When the last device is disconnected the host controller will
dissappear shortly (within 10s). Now if that happens when we are
suspended we should not try to touch the hardware anymore, so add a flag
for this and check it before we re-enable rings.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c | 12 
 drivers/thunderbolt/nhi.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index c358c074f925..14311535661d 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -403,6 +403,8 @@ void ring_start(struct tb_ring *ring)
 {
mutex_lock(>nhi->lock);
mutex_lock(>lock);
+   if (ring->nhi->going_away)
+   goto err;
if (ring->running) {
dev_WARN(>nhi->pdev->dev, "ring already started\n");
goto err;
@@ -449,6 +451,8 @@ void ring_stop(struct tb_ring *ring)
mutex_lock(>lock);
dev_info(>nhi->pdev->dev, "stopping %s %d\n",
 RING_TYPE(ring), ring->hop);
+   if (ring->nhi->going_away)
+   goto err;
if (!ring->running) {
dev_WARN(>nhi->pdev->dev, "%s %d already stopped\n",
 RING_TYPE(ring), ring->hop);
@@ -653,6 +657,14 @@ static int nhi_resume_noirq(struct device *dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct tb *tb = pci_get_drvdata(pdev);
 
+   /*
+* Check that the device is still there. It may be that the user
+* unplugged last device which causes the host controller to go
+* away on PCs.
+*/
+   if (!pci_device_is_present(pdev))
+   tb->nhi->going_away = true;
+
return tb_domain_resume_noirq(tb);
 }
 
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 446ff6dac91d..953864ae0ab3 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -20,6 +20,8 @@
  * @tx_rings: All Tx rings available on this host controller
  * @rx_rings: All Rx rings available on this host controller
  * @msix_ida: Used to allocate MSI-X vectors for rings
+ * @going_away: The host controller device is about to disappear so when
+ * this flag is set, avoid touching the hardware anymore.
  * @interrupt_work: Work scheduled to handle ring interrupt when no
  * MSI-X is used.
  * @hop_count: Number of rings (end point hops) supported by NHI.
@@ -31,6 +33,7 @@ struct tb_nhi {
struct tb_ring **tx_rings;
struct tb_ring **rx_rings;
struct ida msix_ida;
+   bool going_away;
struct work_struct interrupt_work;
u32 hop_count;
 };
-- 
2.11.0

[PATCH v3 27/27] MAINTAINERS: Add maintainers for Thunderbolt driver

[Mika Westerberg]

We will be helping Andreas to maintain the Thunderbolt driver.

Signed-off-by: Michael Jamet 
Signed-off-by: Yehezkel Bernat 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
---
 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 053c3bdd1fe5..f1504e283ae2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11328,6 +11328,9 @@ F:  Documentation/tee.txt
 
 THUNDERBOLT DRIVER
 M: Andreas Noever 
+M: Michael Jamet 
+M: Mika Westerberg 
+M: Yehezkel Bernat 
 S: Maintained
 F: drivers/thunderbolt/
 
-- 
2.11.0

[PATCH v3 03/27] thunderbolt: Do not try to read UID if DROM offset is read as 0

[Mika Westerberg]

At least Falcon Ridge when in host mode does not have any kind of DROM
available and reading DROM offset returns 0 for these. Do not try to
read DROM any further in that case.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 6392990c984d..e4e64b130514 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -276,6 +276,9 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
if (res)
return res;
 
+   if (drom_offset == 0)
+   return -ENODEV;
+
/* read uid */
res = tb_eeprom_read_n(sw, drom_offset, data, 9);
if (res)
-- 
2.11.0

[PATCH v3 27/27] MAINTAINERS: Add maintainers for Thunderbolt driver

[Mika Westerberg]

We will be helping Andreas to maintain the Thunderbolt driver.

Signed-off-by: Michael Jamet 
Signed-off-by: Yehezkel Bernat 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
---
 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 053c3bdd1fe5..f1504e283ae2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11328,6 +11328,9 @@ F:  Documentation/tee.txt
 
 THUNDERBOLT DRIVER
 M: Andreas Noever 
+M: Michael Jamet 
+M: Mika Westerberg 
+M: Yehezkel Bernat 
 S: Maintained
 F: drivers/thunderbolt/
 
-- 
2.11.0

[PATCH v3 03/27] thunderbolt: Do not try to read UID if DROM offset is read as 0

[Mika Westerberg]

At least Falcon Ridge when in host mode does not have any kind of DROM
available and reading DROM offset returns 0 for these. Do not try to
read DROM any further in that case.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index 6392990c984d..e4e64b130514 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -276,6 +276,9 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
if (res)
return res;
 
+   if (drom_offset == 0)
+   return -ENODEV;
+
/* read uid */
res = tb_eeprom_read_n(sw, drom_offset, data, 9);
if (res)
-- 
2.11.0

[PATCH v3 26/27] thunderbolt: Add documentation how Thunderbolt bus can be used

[Mika Westerberg]

Since there are no such tool yet that handles all the low-level details
of connecting devices and upgrading their firmware, add a small document
that shows how the Thunderbolt bus can be used directly from command
line.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 Documentation/admin-guide/index.rst   |   1 +
 Documentation/admin-guide/thunderbolt.rst | 199 ++
 2 files changed, 200 insertions(+)
 create mode 100644 Documentation/admin-guide/thunderbolt.rst

diff --git a/Documentation/admin-guide/index.rst 
b/Documentation/admin-guide/index.rst
index 8c60a8a32a1a..6d99a7ce6e21 100644
--- a/Documentation/admin-guide/index.rst
+++ b/Documentation/admin-guide/index.rst
@@ -61,6 +61,7 @@ configure specific aspects of kernel behavior to your liking.
java
ras
pm/index
+   thunderbolt
 
 .. only::  subproject and html
 
diff --git a/Documentation/admin-guide/thunderbolt.rst 
b/Documentation/admin-guide/thunderbolt.rst
new file mode 100644
index ..6a4cd1f159ca
--- /dev/null
+++ b/Documentation/admin-guide/thunderbolt.rst
@@ -0,0 +1,199 @@
+=
+ Thunderbolt
+=
+The interface presented here is not meant for end users. Instead there
+should be a userspace tool that handles all the low-level details, keeps
+database of the authorized devices and prompts user for new connections.
+
+More details about the sysfs interface for Thunderbolt devices can be
+found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
+
+Those users who just want to connect any device without any sort of
+manual work, can add following line to
+``/etc/udev/rules.d/99-local.rules``::
+
+  ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", 
ATTR{authorized}="1"
+
+This will authorize all devices automatically when they appear. However,
+keep in mind that this bypasses the security levels and makes the system
+vulnerable to DMA attacks.
+
+Security levels and how to use them
+---
+Starting from Intel Falcon Ridge Thunderbolt controller there are 4
+security levels available. The reason for these is the fact that the
+connected devices can be DMA masters and thus read contents of the host
+memory without CPU and OS knowing about it. There are ways to prevent
+this by setting up an IOMMU but it is not always available for various
+reasons.
+
+The security levels are as follows:
+
+  none
+All devices are automatically connected by the firmware. No user
+approval is needed. In BIOS settings this is typically called
+*Legacy mode*.
+
+  user
+User is asked whether the device is allowed to be connected.
+Based on the device identification information available through
+``/sys/bus/thunderbolt/devices``. user then can do the decision.
+In BIOS settings this is typically called *Unique ID*.
+
+  secure
+User is asked whether the device is allowed to be connected. In
+addition to UUID the device (if it supports secure connect) is sent
+a challenge that should match the expected one based on a random key
+written to ``key`` sysfs attribute. In BIOS settings this is
+typically called *One time saved key*.
+
+  dponly
+The firmware automatically creates tunnels for Display Port and
+USB. No PCIe tunneling is done. In BIOS settings this is
+typically called *Display Port Only*.
+
+The current security level can be read from
+``/sys/bus/thunderbolt/devices/domainX/security`` where ``domainX`` is
+the Thunderbolt domain the host controller manages. There is typically
+one domain per Thunderbolt host controller.
+
+If the security level reads as ``user`` or ``secure`` the connected
+device must be authorized by the user before PCIe tunnels are created
+(e.g the PCIe device appears).
+
+Each Thunderbolt device plugged in will appear in sysfs under
+``/sys/bus/thunderbolt/devices``. The device directory carries
+information that can be used to identify the particular device,
+including its name and UUID.
+
+Authorizing devices when security level is ``user`` or ``secure``
+-
+When a device is plugged in it will appear in sysfs as follows::
+
+  /sys/bus/thunderbolt/devices/0-1/authorized  - 0
+  /sys/bus/thunderbolt/devices/0-1/device  - 0x8004
+  /sys/bus/thunderbolt/devices/0-1/device_name - Thunderbolt to FireWire 
Adapter
+  /sys/bus/thunderbolt/devices/0-1/vendor  - 0x1
+  /sys/bus/thunderbolt/devices/0-1/vendor_name - Apple, Inc.
+  /sys/bus/thunderbolt/devices/0-1/unique_id   - 
e0376f00-0300-0100--
+
+The ``authorized`` attribute reads 0 which means no PCIe tunnels are
+created yet. The user can authorize the device by simply::
+
+  # echo 1 > /sys/bus/thunderbolt/devices/0-1/authorized
+

[PATCH v3 26/27] thunderbolt: Add documentation how Thunderbolt bus can be used

[Mika Westerberg]

Since there are no such tool yet that handles all the low-level details
of connecting devices and upgrading their firmware, add a small document
that shows how the Thunderbolt bus can be used directly from command
line.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 Documentation/admin-guide/index.rst   |   1 +
 Documentation/admin-guide/thunderbolt.rst | 199 ++
 2 files changed, 200 insertions(+)
 create mode 100644 Documentation/admin-guide/thunderbolt.rst

diff --git a/Documentation/admin-guide/index.rst 
b/Documentation/admin-guide/index.rst
index 8c60a8a32a1a..6d99a7ce6e21 100644
--- a/Documentation/admin-guide/index.rst
+++ b/Documentation/admin-guide/index.rst
@@ -61,6 +61,7 @@ configure specific aspects of kernel behavior to your liking.
java
ras
pm/index
+   thunderbolt
 
 .. only::  subproject and html
 
diff --git a/Documentation/admin-guide/thunderbolt.rst 
b/Documentation/admin-guide/thunderbolt.rst
new file mode 100644
index ..6a4cd1f159ca
--- /dev/null
+++ b/Documentation/admin-guide/thunderbolt.rst
@@ -0,0 +1,199 @@
+=
+ Thunderbolt
+=
+The interface presented here is not meant for end users. Instead there
+should be a userspace tool that handles all the low-level details, keeps
+database of the authorized devices and prompts user for new connections.
+
+More details about the sysfs interface for Thunderbolt devices can be
+found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
+
+Those users who just want to connect any device without any sort of
+manual work, can add following line to
+``/etc/udev/rules.d/99-local.rules``::
+
+  ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", 
ATTR{authorized}="1"
+
+This will authorize all devices automatically when they appear. However,
+keep in mind that this bypasses the security levels and makes the system
+vulnerable to DMA attacks.
+
+Security levels and how to use them
+---
+Starting from Intel Falcon Ridge Thunderbolt controller there are 4
+security levels available. The reason for these is the fact that the
+connected devices can be DMA masters and thus read contents of the host
+memory without CPU and OS knowing about it. There are ways to prevent
+this by setting up an IOMMU but it is not always available for various
+reasons.
+
+The security levels are as follows:
+
+  none
+All devices are automatically connected by the firmware. No user
+approval is needed. In BIOS settings this is typically called
+*Legacy mode*.
+
+  user
+User is asked whether the device is allowed to be connected.
+Based on the device identification information available through
+``/sys/bus/thunderbolt/devices``. user then can do the decision.
+In BIOS settings this is typically called *Unique ID*.
+
+  secure
+User is asked whether the device is allowed to be connected. In
+addition to UUID the device (if it supports secure connect) is sent
+a challenge that should match the expected one based on a random key
+written to ``key`` sysfs attribute. In BIOS settings this is
+typically called *One time saved key*.
+
+  dponly
+The firmware automatically creates tunnels for Display Port and
+USB. No PCIe tunneling is done. In BIOS settings this is
+typically called *Display Port Only*.
+
+The current security level can be read from
+``/sys/bus/thunderbolt/devices/domainX/security`` where ``domainX`` is
+the Thunderbolt domain the host controller manages. There is typically
+one domain per Thunderbolt host controller.
+
+If the security level reads as ``user`` or ``secure`` the connected
+device must be authorized by the user before PCIe tunnels are created
+(e.g the PCIe device appears).
+
+Each Thunderbolt device plugged in will appear in sysfs under
+``/sys/bus/thunderbolt/devices``. The device directory carries
+information that can be used to identify the particular device,
+including its name and UUID.
+
+Authorizing devices when security level is ``user`` or ``secure``
+-
+When a device is plugged in it will appear in sysfs as follows::
+
+  /sys/bus/thunderbolt/devices/0-1/authorized  - 0
+  /sys/bus/thunderbolt/devices/0-1/device  - 0x8004
+  /sys/bus/thunderbolt/devices/0-1/device_name - Thunderbolt to FireWire 
Adapter
+  /sys/bus/thunderbolt/devices/0-1/vendor  - 0x1
+  /sys/bus/thunderbolt/devices/0-1/vendor_name - Apple, Inc.
+  /sys/bus/thunderbolt/devices/0-1/unique_id   - 
e0376f00-0300-0100--
+
+The ``authorized`` attribute reads 0 which means no PCIe tunnels are
+created yet. The user can authorize the device by simply::
+
+  # echo 1 > /sys/bus/thunderbolt/devices/0-1/authorized
+
+This will create the PCIe tunnels and the device is now connected.
+
+If the device supports secure connect, and the 

[PATCH v3 19/27] thunderbolt: Add new Thunderbolt PCI IDs

[Mika Westerberg]

Add Intel Win Ridge (Thunderbolt 2) and Alpine Ridge (Thunderbolt 3)
controller PCI IDs to the list of supported devices.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c| 11 +++
 drivers/thunderbolt/nhi.h| 17 +
 drivers/thunderbolt/switch.c | 19 ++-
 3 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index c1113a3c4128..fa4c2745dba2 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -787,6 +787,17 @@ static struct pci_device_id nhi_ids[] = {
.device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
},
+
+   /* Thunderbolt 3 */
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
+
{ 0,}
 };
 
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 630f44140530..8bd9b4e5a0b1 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -143,4 +143,21 @@ static inline int ring_tx(struct tb_ring *ring, struct 
ring_frame *frame)
return __ring_enqueue(ring, frame);
 }
 
+/*
+ * PCI IDs used in this driver from Win Ridge forward. There is no
+ * need for the PCI quirk anymore as we will use ICM also on Apple
+ * hardware.
+ */
+#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI0x157d
+#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI0x15bf
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI  0x15d2
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE   0x15d3
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI  0x15d9
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE   0x15da
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI0x15dc
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI   0x15dd
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
+
 #endif
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 0a592ccb7923..8006577590ed 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -491,13 +491,22 @@ int tb_switch_configure(struct tb_switch *sw)
tb_sw_warn(sw, "unknown switch vendor id %#x\n",
   sw->config.vendor_id);
 
-   if (sw->config.device_id != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_PORT_RIDGE &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE 
&&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE)
+   switch (sw->config.device_id) {
+   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
+   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
+   break;
+
+   default:
tb_sw_warn(sw, "unsupported switch device id %#x\n",
   sw->config.device_id);
+   }
 
sw->config.enabled = 1;
 
-- 
2.11.0

[PATCH v3 19/27] thunderbolt: Add new Thunderbolt PCI IDs

[Mika Westerberg]

Add Intel Win Ridge (Thunderbolt 2) and Alpine Ridge (Thunderbolt 3)
controller PCI IDs to the list of supported devices.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c| 11 +++
 drivers/thunderbolt/nhi.h| 17 +
 drivers/thunderbolt/switch.c | 19 ++-
 3 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index c1113a3c4128..fa4c2745dba2 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -787,6 +787,17 @@ static struct pci_device_id nhi_ids[] = {
.device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
},
+
+   /* Thunderbolt 3 */
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
+   { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
+
{ 0,}
 };
 
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 630f44140530..8bd9b4e5a0b1 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -143,4 +143,21 @@ static inline int ring_tx(struct tb_ring *ring, struct 
ring_frame *frame)
return __ring_enqueue(ring, frame);
 }
 
+/*
+ * PCI IDs used in this driver from Win Ridge forward. There is no
+ * need for the PCI quirk anymore as we will use ICM also on Apple
+ * hardware.
+ */
+#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI0x157d
+#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI0x15bf
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI  0x15d2
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE   0x15d3
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI  0x15d9
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE   0x15da
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI0x15dc
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI   0x15dd
+#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
+
 #endif
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 0a592ccb7923..8006577590ed 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -491,13 +491,22 @@ int tb_switch_configure(struct tb_switch *sw)
tb_sw_warn(sw, "unknown switch vendor id %#x\n",
   sw->config.vendor_id);
 
-   if (sw->config.device_id != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_PORT_RIDGE &&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE 
&&
-   sw->config.device_id != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE)
+   switch (sw->config.device_id) {
+   case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
+   case PCI_DEVICE_ID_INTEL_PORT_RIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
+   case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
+   break;
+
+   default:
tb_sw_warn(sw, "unsupported switch device id %#x\n",
   sw->config.device_id);
+   }
 
sw->config.enabled = 1;
 
-- 
2.11.0

[PATCH v3 12/27] thunderbolt: Refactor and fix parsing of port drom entries

[Mika Westerberg]

From: Lukas Wunner 

Currently tb_drom_parse_entry() is only able to parse drom entries of
type TB_DROM_ENTRY_PORT. Rename it to tb_drom_parse_entry_port().
Fold tb_drom_parse_port_entry() into it.

Its return value is currently ignored. Evaluate it and abort parsing on
error.

Change tb_drom_parse_entries() to accommodate for parsing of other entry
types than TB_DROM_ENTRY_PORT.

Signed-off-by: Lukas Wunner 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index e2c1f8a45522..5c7d80a109b1 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -295,25 +295,13 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
return 0;
 }
 
-static void tb_drom_parse_port_entry(struct tb_port *port,
-   struct tb_drom_entry_port *entry)
-{
-   port->link_nr = entry->link_nr;
-   if (entry->has_dual_link_port)
-   port->dual_link_port =
-   >sw->ports[entry->dual_link_port_nr];
-}
-
-static int tb_drom_parse_entry(struct tb_switch *sw,
-   struct tb_drom_entry_header *header)
+static int tb_drom_parse_entry_port(struct tb_switch *sw,
+   struct tb_drom_entry_header *header)
 {
struct tb_port *port;
int res;
enum tb_port_type type;
 
-   if (header->type != TB_DROM_ENTRY_PORT)
-   return 0;
-
port = >ports[header->index];
port->disabled = header->port_disabled;
if (port->disabled)
@@ -332,7 +320,10 @@ static int tb_drom_parse_entry(struct tb_switch *sw,
header->len, sizeof(struct tb_drom_entry_port));
return -EIO;
}
-   tb_drom_parse_port_entry(port, entry);
+   port->link_nr = entry->link_nr;
+   if (entry->has_dual_link_port)
+   port->dual_link_port =
+   >sw->ports[entry->dual_link_port_nr];
}
return 0;
 }
@@ -347,6 +338,7 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
struct tb_drom_header *header = (void *) sw->drom;
u16 pos = sizeof(*header);
u16 drom_size = header->data_len + TB_DROM_DATA_START;
+   int res;
 
while (pos < drom_size) {
struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
@@ -356,7 +348,15 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
return -EIO;
}
 
-   tb_drom_parse_entry(sw, entry);
+   switch (entry->type) {
+   case TB_DROM_ENTRY_GENERIC:
+   break;
+   case TB_DROM_ENTRY_PORT:
+   res = tb_drom_parse_entry_port(sw, entry);
+   break;
+   }
+   if (res)
+   return res;
 
pos += entry->len;
}
-- 
2.11.0

[PATCH v3 12/27] thunderbolt: Refactor and fix parsing of port drom entries

[Mika Westerberg]

From: Lukas Wunner 

Currently tb_drom_parse_entry() is only able to parse drom entries of
type TB_DROM_ENTRY_PORT. Rename it to tb_drom_parse_entry_port().
Fold tb_drom_parse_port_entry() into it.

Its return value is currently ignored. Evaluate it and abort parsing on
error.

Change tb_drom_parse_entries() to accommodate for parsing of other entry
types than TB_DROM_ENTRY_PORT.

Signed-off-by: Lukas Wunner 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index e2c1f8a45522..5c7d80a109b1 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -295,25 +295,13 @@ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
return 0;
 }
 
-static void tb_drom_parse_port_entry(struct tb_port *port,
-   struct tb_drom_entry_port *entry)
-{
-   port->link_nr = entry->link_nr;
-   if (entry->has_dual_link_port)
-   port->dual_link_port =
-   >sw->ports[entry->dual_link_port_nr];
-}
-
-static int tb_drom_parse_entry(struct tb_switch *sw,
-   struct tb_drom_entry_header *header)
+static int tb_drom_parse_entry_port(struct tb_switch *sw,
+   struct tb_drom_entry_header *header)
 {
struct tb_port *port;
int res;
enum tb_port_type type;
 
-   if (header->type != TB_DROM_ENTRY_PORT)
-   return 0;
-
port = >ports[header->index];
port->disabled = header->port_disabled;
if (port->disabled)
@@ -332,7 +320,10 @@ static int tb_drom_parse_entry(struct tb_switch *sw,
header->len, sizeof(struct tb_drom_entry_port));
return -EIO;
}
-   tb_drom_parse_port_entry(port, entry);
+   port->link_nr = entry->link_nr;
+   if (entry->has_dual_link_port)
+   port->dual_link_port =
+   >sw->ports[entry->dual_link_port_nr];
}
return 0;
 }
@@ -347,6 +338,7 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
struct tb_drom_header *header = (void *) sw->drom;
u16 pos = sizeof(*header);
u16 drom_size = header->data_len + TB_DROM_DATA_START;
+   int res;
 
while (pos < drom_size) {
struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
@@ -356,7 +348,15 @@ static int tb_drom_parse_entries(struct tb_switch *sw)
return -EIO;
}
 
-   tb_drom_parse_entry(sw, entry);
+   switch (entry->type) {
+   case TB_DROM_ENTRY_GENERIC:
+   break;
+   case TB_DROM_ENTRY_PORT:
+   res = tb_drom_parse_entry_port(sw, entry);
+   break;
+   }
+   if (res)
+   return res;
 
pos += entry->len;
}
-- 
2.11.0

[PATCH v3 22/27] thunderbolt: Add support for DMA configuration based mailbox

[Mika Westerberg]

The DMA (NHI) port of a switch provides access to the NVM of the host
controller (and devices starting from Intel Alpine Ridge). The NVM
contains also more complete DROM for the root switch including vendor
and device identification strings.

This will look for the DMA port capability for each switch and if found
populates sw->dma_port. We then teach tb_drom_read() to read the DROM
information from NVM if available for the root switch.

The DMA port capability also supports upgrading the NVM for both host
controller and devices which will be added in subsequent patches.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/Makefile   |   2 +-
 drivers/thunderbolt/dma_port.c | 524 +
 drivers/thunderbolt/dma_port.h |  34 +++
 drivers/thunderbolt/eeprom.c   |  51 +++-
 drivers/thunderbolt/switch.c   |  30 +++
 drivers/thunderbolt/tb.h   |   5 +
 6 files changed, 644 insertions(+), 2 deletions(-)
 create mode 100644 drivers/thunderbolt/dma_port.c
 create mode 100644 drivers/thunderbolt/dma_port.h

diff --git a/drivers/thunderbolt/Makefile b/drivers/thunderbolt/Makefile
index e276a9a62261..9828e862dd35 100644
--- a/drivers/thunderbolt/Makefile
+++ b/drivers/thunderbolt/Makefile
@@ -1,3 +1,3 @@
 obj-${CONFIG_THUNDERBOLT} := thunderbolt.o
 thunderbolt-objs := nhi.o ctl.o tb.o switch.o cap.o path.o tunnel_pci.o 
eeprom.o
-thunderbolt-objs += domain.o
+thunderbolt-objs += domain.o dma_port.o
diff --git a/drivers/thunderbolt/dma_port.c b/drivers/thunderbolt/dma_port.c
new file mode 100644
index ..af6dde347bee
--- /dev/null
+++ b/drivers/thunderbolt/dma_port.c
@@ -0,0 +1,524 @@
+/*
+ * Thunderbolt DMA configuration based mailbox support
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Authors: Michael Jamet 
+ *  Mika Westerberg 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "dma_port.h"
+#include "tb_regs.h"
+
+#define DMA_PORT_CAP   0x3e
+
+#define MAIL_DATA  1
+#define MAIL_DATA_DWORDS   16
+
+#define MAIL_IN17
+#define MAIL_IN_CMD_SHIFT  28
+#define MAIL_IN_CMD_MASK   GENMASK(31, 28)
+#define MAIL_IN_CMD_FLASH_WRITE0x0
+#define MAIL_IN_CMD_FLASH_UPDATE_AUTH  0x1
+#define MAIL_IN_CMD_FLASH_READ 0x2
+#define MAIL_IN_CMD_POWER_CYCLE0x4
+#define MAIL_IN_DWORDS_SHIFT   24
+#define MAIL_IN_DWORDS_MASKGENMASK(27, 24)
+#define MAIL_IN_ADDRESS_SHIFT  2
+#define MAIL_IN_ADDRESS_MASK   GENMASK(23, 2)
+#define MAIL_IN_CSSBIT(1)
+#define MAIL_IN_OP_REQUEST BIT(0)
+
+#define MAIL_OUT   18
+#define MAIL_OUT_STATUS_RESPONSE   BIT(29)
+#define MAIL_OUT_STATUS_CMD_SHIFT  4
+#define MAIL_OUT_STATUS_CMD_MASK   GENMASK(7, 4)
+#define MAIL_OUT_STATUS_MASK   GENMASK(3, 0)
+#define MAIL_OUT_STATUS_COMPLETED  0
+#define MAIL_OUT_STATUS_ERR_AUTH   1
+#define MAIL_OUT_STATUS_ERR_ACCESS 2
+
+#define DMA_PORT_TIMEOUT   5000 /* ms */
+#define DMA_PORT_RETRIES   3
+
+/**
+ * struct tb_dma_port - DMA control port
+ * @sw: Switch the DMA port belongs to
+ * @port: Switch port number where DMA capability is found
+ * @base: Start offset of the mailbox registers
+ * @buf: Temporary buffer to store a single block
+ */
+struct tb_dma_port {
+   struct tb_switch *sw;
+   u8 port;
+   u32 base;
+   u8 *buf;
+};
+
+/*
+ * When the switch is in safe mode it supports very little functionality
+ * so we don't validate that much here.
+ */
+static bool dma_port_match(const struct tb_cfg_request *req,
+  const struct ctl_pkg *pkg)
+{
+   u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);
+
+   if (pkg->frame.eof == TB_CFG_PKG_ERROR)
+   return true;
+   if (pkg->frame.eof != req->response_type)
+   return false;
+   if (route != tb_cfg_get_route(req->request))
+   return false;
+   if (pkg->frame.size != req->response_size)
+   return false;
+
+   return true;
+}
+
+static bool dma_port_copy(struct tb_cfg_request *req, const struct ctl_pkg 
*pkg)
+{
+   memcpy(req->response, pkg->buffer, req->response_size);
+   return true;
+}
+
+static int dma_port_read(struct tb_ctl *ctl, void *buffer, u64 route,
+u32 port, u32 offset, u32 length, int 

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 08:37:52 +0200

> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> From: Corentin Labbe 
>> Date: Wed, 31 May 2017 09:18:31 +0200
>> 
>> > This patch series add the driver for dwmac-sun8i which handle the Ethernet 
>> > MAC
>> > present on Allwinner H3/H5/A83T/A64 SoCs.
>> 
>> Series applied, but wow that's a lot of DT file changes :-(
> 
> The DT patches should not go through your tree, but arm-soc, so I
> guess this is not an issue for you?

I already applied them, so if that is the intention, too late.

This needs to be explicitly stated in the header posting.  Otherwise
I assume the entire series is meant to go into my tree.

Also, saying "net-next" in the patch subjects means it's targetting my
tree.

[PATCH v3 22/27] thunderbolt: Add support for DMA configuration based mailbox

[Mika Westerberg]

The DMA (NHI) port of a switch provides access to the NVM of the host
controller (and devices starting from Intel Alpine Ridge). The NVM
contains also more complete DROM for the root switch including vendor
and device identification strings.

This will look for the DMA port capability for each switch and if found
populates sw->dma_port. We then teach tb_drom_read() to read the DROM
information from NVM if available for the root switch.

The DMA port capability also supports upgrading the NVM for both host
controller and devices which will be added in subsequent patches.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/Makefile   |   2 +-
 drivers/thunderbolt/dma_port.c | 524 +
 drivers/thunderbolt/dma_port.h |  34 +++
 drivers/thunderbolt/eeprom.c   |  51 +++-
 drivers/thunderbolt/switch.c   |  30 +++
 drivers/thunderbolt/tb.h   |   5 +
 6 files changed, 644 insertions(+), 2 deletions(-)
 create mode 100644 drivers/thunderbolt/dma_port.c
 create mode 100644 drivers/thunderbolt/dma_port.h

diff --git a/drivers/thunderbolt/Makefile b/drivers/thunderbolt/Makefile
index e276a9a62261..9828e862dd35 100644
--- a/drivers/thunderbolt/Makefile
+++ b/drivers/thunderbolt/Makefile
@@ -1,3 +1,3 @@
 obj-${CONFIG_THUNDERBOLT} := thunderbolt.o
 thunderbolt-objs := nhi.o ctl.o tb.o switch.o cap.o path.o tunnel_pci.o 
eeprom.o
-thunderbolt-objs += domain.o
+thunderbolt-objs += domain.o dma_port.o
diff --git a/drivers/thunderbolt/dma_port.c b/drivers/thunderbolt/dma_port.c
new file mode 100644
index ..af6dde347bee
--- /dev/null
+++ b/drivers/thunderbolt/dma_port.c
@@ -0,0 +1,524 @@
+/*
+ * Thunderbolt DMA configuration based mailbox support
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Authors: Michael Jamet 
+ *  Mika Westerberg 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+
+#include "dma_port.h"
+#include "tb_regs.h"
+
+#define DMA_PORT_CAP   0x3e
+
+#define MAIL_DATA  1
+#define MAIL_DATA_DWORDS   16
+
+#define MAIL_IN17
+#define MAIL_IN_CMD_SHIFT  28
+#define MAIL_IN_CMD_MASK   GENMASK(31, 28)
+#define MAIL_IN_CMD_FLASH_WRITE0x0
+#define MAIL_IN_CMD_FLASH_UPDATE_AUTH  0x1
+#define MAIL_IN_CMD_FLASH_READ 0x2
+#define MAIL_IN_CMD_POWER_CYCLE0x4
+#define MAIL_IN_DWORDS_SHIFT   24
+#define MAIL_IN_DWORDS_MASKGENMASK(27, 24)
+#define MAIL_IN_ADDRESS_SHIFT  2
+#define MAIL_IN_ADDRESS_MASK   GENMASK(23, 2)
+#define MAIL_IN_CSSBIT(1)
+#define MAIL_IN_OP_REQUEST BIT(0)
+
+#define MAIL_OUT   18
+#define MAIL_OUT_STATUS_RESPONSE   BIT(29)
+#define MAIL_OUT_STATUS_CMD_SHIFT  4
+#define MAIL_OUT_STATUS_CMD_MASK   GENMASK(7, 4)
+#define MAIL_OUT_STATUS_MASK   GENMASK(3, 0)
+#define MAIL_OUT_STATUS_COMPLETED  0
+#define MAIL_OUT_STATUS_ERR_AUTH   1
+#define MAIL_OUT_STATUS_ERR_ACCESS 2
+
+#define DMA_PORT_TIMEOUT   5000 /* ms */
+#define DMA_PORT_RETRIES   3
+
+/**
+ * struct tb_dma_port - DMA control port
+ * @sw: Switch the DMA port belongs to
+ * @port: Switch port number where DMA capability is found
+ * @base: Start offset of the mailbox registers
+ * @buf: Temporary buffer to store a single block
+ */
+struct tb_dma_port {
+   struct tb_switch *sw;
+   u8 port;
+   u32 base;
+   u8 *buf;
+};
+
+/*
+ * When the switch is in safe mode it supports very little functionality
+ * so we don't validate that much here.
+ */
+static bool dma_port_match(const struct tb_cfg_request *req,
+  const struct ctl_pkg *pkg)
+{
+   u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);
+
+   if (pkg->frame.eof == TB_CFG_PKG_ERROR)
+   return true;
+   if (pkg->frame.eof != req->response_type)
+   return false;
+   if (route != tb_cfg_get_route(req->request))
+   return false;
+   if (pkg->frame.size != req->response_size)
+   return false;
+
+   return true;
+}
+
+static bool dma_port_copy(struct tb_cfg_request *req, const struct ctl_pkg 
*pkg)
+{
+   memcpy(req->response, pkg->buffer, req->response_size);
+   return true;
+}
+
+static int dma_port_read(struct tb_ctl *ctl, void *buffer, u64 route,
+u32 port, u32 offset, u32 length, int timeout_msec)
+{
+   struct cfg_read_pkg request = {
+   .header = tb_cfg_make_header(route),
+   .addr = {
+   .seq = 1,
+

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 08:37:52 +0200

> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> From: Corentin Labbe 
>> Date: Wed, 31 May 2017 09:18:31 +0200
>> 
>> > This patch series add the driver for dwmac-sun8i which handle the Ethernet 
>> > MAC
>> > present on Allwinner H3/H5/A83T/A64 SoCs.
>> 
>> Series applied, but wow that's a lot of DT file changes :-(
> 
> The DT patches should not go through your tree, but arm-soc, so I
> guess this is not an issue for you?

I already applied them, so if that is the intention, too late.

This needs to be explicitly stated in the header posting.  Otherwise
I assume the entire series is meant to go into my tree.

Also, saying "net-next" in the patch subjects means it's targetting my
tree.

[PATCH v3 20/27] thunderbolt: Add support for NHI mailbox

[Mika Westerberg]

The host controller includes two sets of registers that are used to
communicate with the firmware. Add functions that can be used to access
these registers.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c  | 58 ++
 drivers/thunderbolt/nhi.h  | 16 
 drivers/thunderbolt/nhi_regs.h | 11 
 3 files changed, 85 insertions(+)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index fa4c2745dba2..c358c074f925 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "nhi.h"
 #include "nhi_regs.h"
@@ -28,6 +29,8 @@
 #define MSIX_MIN_VECS  6
 #define MSIX_MAX_VECS  16
 
+#define NHI_MAILBOX_TIMEOUT500 /* ms */
+
 static int ring_interrupt_index(struct tb_ring *ring)
 {
int bit = ring->hop;
@@ -525,6 +528,61 @@ void ring_free(struct tb_ring *ring)
kfree(ring);
 }
 
+/**
+ * nhi_mailbox_cmd() - Send a command through NHI mailbox
+ * @nhi: Pointer to the NHI structure
+ * @cmd: Command to send
+ * @data: Data to be send with the command
+ *
+ * Sends mailbox command to the firmware running on NHI. Returns %0 in
+ * case of success and negative errno in case of failure.
+ */
+int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
+{
+   ktime_t timeout;
+   u32 val;
+
+   iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
+
+   val = ioread32(nhi->iobase + REG_INMAIL_CMD);
+   val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
+   val |= REG_INMAIL_OP_REQUEST | cmd;
+   iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
+
+   timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
+   do {
+   val = ioread32(nhi->iobase + REG_INMAIL_CMD);
+   if (!(val & REG_INMAIL_OP_REQUEST))
+   break;
+   usleep_range(10, 20);
+   } while (ktime_before(ktime_get(), timeout));
+
+   if (val & REG_INMAIL_OP_REQUEST)
+   return -ETIMEDOUT;
+   if (val & REG_INMAIL_ERROR)
+   return -EIO;
+
+   return 0;
+}
+
+/**
+ * nhi_mailbox_mode() - Return current firmware operation mode
+ * @nhi: Pointer to the NHI structure
+ *
+ * The function reads current firmware operation mode using NHI mailbox
+ * registers and returns it to the caller.
+ */
+enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
+{
+   u32 val;
+
+   val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
+   val &= REG_OUTMAIL_CMD_OPMODE_MASK;
+   val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
+
+   return (enum nhi_fw_mode)val;
+}
+
 static void nhi_interrupt_work(struct work_struct *work)
 {
struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 8bd9b4e5a0b1..446ff6dac91d 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -143,6 +143,22 @@ static inline int ring_tx(struct tb_ring *ring, struct 
ring_frame *frame)
return __ring_enqueue(ring, frame);
 }
 
+enum nhi_fw_mode {
+   NHI_FW_SAFE_MODE,
+   NHI_FW_AUTH_MODE,
+   NHI_FW_EP_MODE,
+   NHI_FW_CM_MODE,
+};
+
+enum nhi_mailbox_cmd {
+   NHI_MAILBOX_SAVE_DEVS = 0x05,
+   NHI_MAILBOX_DRV_UNLOADS = 0x07,
+   NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
+};
+
+int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
+enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
+
 /*
  * PCI IDs used in this driver from Win Ridge forward. There is no
  * need for the PCI quirk anymore as we will use ICM also on Apple
diff --git a/drivers/thunderbolt/nhi_regs.h b/drivers/thunderbolt/nhi_regs.h
index 48b98d3c7e6a..322fe1fa3a3c 100644
--- a/drivers/thunderbolt/nhi_regs.h
+++ b/drivers/thunderbolt/nhi_regs.h
@@ -107,4 +107,15 @@ struct ring_desc {
 #define REG_DMA_MISC   0x39864
 #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
 
+#define REG_INMAIL_DATA0x39900
+
+#define REG_INMAIL_CMD 0x39904
+#define REG_INMAIL_CMD_MASKGENMASK(7, 0)
+#define REG_INMAIL_ERROR   BIT(30)
+#define REG_INMAIL_OP_REQUEST  BIT(31)
+
+#define REG_OUTMAIL_CMD0x3990c
+#define REG_OUTMAIL_CMD_OPMODE_SHIFT   8
+#define REG_OUTMAIL_CMD_OPMODE_MASKGENMASK(11, 8)
+
 #endif
-- 
2.11.0

[PATCH v3 17/27] thunderbolt: Let the connection manager handle all notifications

[Mika Westerberg]

Currently the control channel (ctl.c) handles the one supported
notification (PLUG_EVENT) and sends back ACK accordingly. However, we
are going to add support for the internal connection manager (ICM) that
needs to handle a different notifications. So instead of dealing
everything in the control channel, we change the callback to take an
arbitrary thunderbolt packet and convert the native connection manager
to handle the event itself.

In addition we only push replies we know of to the response FIFO.
Everything else is treated as notification (or request) and is expected
to be dealt by the connection manager implementation.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c| 86 ++--
 drivers/thunderbolt/ctl.h|  5 +--
 drivers/thunderbolt/domain.c | 15 +++-
 drivers/thunderbolt/tb.c | 30 
 drivers/thunderbolt/tb.h |  5 +--
 5 files changed, 103 insertions(+), 38 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index c6633da582b8..5417ed244edc 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -35,7 +35,7 @@ struct tb_ctl {
DECLARE_KFIFO(response_fifo, struct ctl_pkg*, 16);
struct completion response_ready;
 
-   hotplug_cb callback;
+   event_cb callback;
void *callback_data;
 };
 
@@ -52,6 +52,9 @@ struct tb_ctl {
 #define tb_ctl_info(ctl, format, arg...) \
dev_info(&(ctl)->nhi->pdev->dev, format, ## arg)
 
+#define tb_ctl_dbg(ctl, format, arg...) \
+   dev_dbg(&(ctl)->nhi->pdev->dev, format, ## arg)
+
 /* utility functions */
 
 static int check_header(struct ctl_pkg *pkg, u32 len, enum tb_cfg_pkg_type 
type,
@@ -272,24 +275,12 @@ static int tb_ctl_tx(struct tb_ctl *ctl, const void 
*data, size_t len,
 }
 
 /**
- * tb_ctl_handle_plug_event() - acknowledge a plug event, invoke ctl->callback
+ * tb_ctl_handle_event() - acknowledge a plug event, invoke ctl->callback
  */
-static void tb_ctl_handle_plug_event(struct tb_ctl *ctl,
-struct ctl_pkg *response)
+static void tb_ctl_handle_event(struct tb_ctl *ctl, enum tb_cfg_pkg_type type,
+   struct ctl_pkg *pkg, size_t size)
 {
-   struct cfg_event_pkg *pkg = response->buffer;
-   u64 route = tb_cfg_get_route(>header);
-
-   if (check_header(response, sizeof(*pkg), TB_CFG_PKG_EVENT, route)) {
-   tb_ctl_warn(ctl, "malformed TB_CFG_PKG_EVENT\n");
-   return;
-   }
-
-   if (tb_cfg_error(ctl, route, pkg->port, TB_CFG_ERROR_ACK_PLUG_EVENT))
-   tb_ctl_warn(ctl, "could not ack plug event on %llx:%x\n",
-   route, pkg->port);
-   WARN(pkg->zero, "pkg->zero is %#x\n", pkg->zero);
-   ctl->callback(ctl->callback_data, route, pkg->port, pkg->unplug);
+   ctl->callback(ctl->callback_data, type, pkg->buffer, size);
 }
 
 static void tb_ctl_rx_submit(struct ctl_pkg *pkg)
@@ -302,10 +293,29 @@ static void tb_ctl_rx_submit(struct ctl_pkg *pkg)
 */
 }
 
+static int tb_async_error(const struct ctl_pkg *pkg)
+{
+   const struct cfg_error_pkg *error = (const struct cfg_error_pkg *)pkg;
+
+   if (pkg->frame.eof != TB_CFG_PKG_ERROR)
+   return false;
+
+   switch (error->error) {
+   case TB_CFG_ERROR_LINK_ERROR:
+   case TB_CFG_ERROR_HEC_ERROR_DETECTED:
+   case TB_CFG_ERROR_FLOW_CONTROL_ERROR:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
 static void tb_ctl_rx_callback(struct tb_ring *ring, struct ring_frame *frame,
   bool canceled)
 {
struct ctl_pkg *pkg = container_of(frame, typeof(*pkg), frame);
+   __be32 crc32;
 
if (canceled)
return; /*
@@ -320,18 +330,42 @@ static void tb_ctl_rx_callback(struct tb_ring *ring, 
struct ring_frame *frame,
}
 
frame->size -= 4; /* remove checksum */
-   if (*(__be32 *) (pkg->buffer + frame->size)
-   != tb_crc(pkg->buffer, frame->size)) {
-   tb_ctl_err(pkg->ctl,
-  "RX: checksum mismatch, dropping packet\n");
-   goto rx;
-   }
+   crc32 = tb_crc(pkg->buffer, frame->size);
be32_to_cpu_array(pkg->buffer, pkg->buffer, frame->size / 4);
 
-   if (frame->eof == TB_CFG_PKG_EVENT) {
-   tb_ctl_handle_plug_event(pkg->ctl, pkg);
+   switch (frame->eof) {
+   case TB_CFG_PKG_READ:
+   case TB_CFG_PKG_WRITE:
+   case TB_CFG_PKG_ERROR:
+   case TB_CFG_PKG_OVERRIDE:
+   case TB_CFG_PKG_RESET:
+   if (*(__be32 *)(pkg->buffer + frame->size) != crc32) {
+   

[PATCH v3 17/27] thunderbolt: Let the connection manager handle all notifications

[Mika Westerberg]

Currently the control channel (ctl.c) handles the one supported
notification (PLUG_EVENT) and sends back ACK accordingly. However, we
are going to add support for the internal connection manager (ICM) that
needs to handle a different notifications. So instead of dealing
everything in the control channel, we change the callback to take an
arbitrary thunderbolt packet and convert the native connection manager
to handle the event itself.

In addition we only push replies we know of to the response FIFO.
Everything else is treated as notification (or request) and is expected
to be dealt by the connection manager implementation.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c| 86 ++--
 drivers/thunderbolt/ctl.h|  5 +--
 drivers/thunderbolt/domain.c | 15 +++-
 drivers/thunderbolt/tb.c | 30 
 drivers/thunderbolt/tb.h |  5 +--
 5 files changed, 103 insertions(+), 38 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index c6633da582b8..5417ed244edc 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -35,7 +35,7 @@ struct tb_ctl {
DECLARE_KFIFO(response_fifo, struct ctl_pkg*, 16);
struct completion response_ready;
 
-   hotplug_cb callback;
+   event_cb callback;
void *callback_data;
 };
 
@@ -52,6 +52,9 @@ struct tb_ctl {
 #define tb_ctl_info(ctl, format, arg...) \
dev_info(&(ctl)->nhi->pdev->dev, format, ## arg)
 
+#define tb_ctl_dbg(ctl, format, arg...) \
+   dev_dbg(&(ctl)->nhi->pdev->dev, format, ## arg)
+
 /* utility functions */
 
 static int check_header(struct ctl_pkg *pkg, u32 len, enum tb_cfg_pkg_type 
type,
@@ -272,24 +275,12 @@ static int tb_ctl_tx(struct tb_ctl *ctl, const void 
*data, size_t len,
 }
 
 /**
- * tb_ctl_handle_plug_event() - acknowledge a plug event, invoke ctl->callback
+ * tb_ctl_handle_event() - acknowledge a plug event, invoke ctl->callback
  */
-static void tb_ctl_handle_plug_event(struct tb_ctl *ctl,
-struct ctl_pkg *response)
+static void tb_ctl_handle_event(struct tb_ctl *ctl, enum tb_cfg_pkg_type type,
+   struct ctl_pkg *pkg, size_t size)
 {
-   struct cfg_event_pkg *pkg = response->buffer;
-   u64 route = tb_cfg_get_route(>header);
-
-   if (check_header(response, sizeof(*pkg), TB_CFG_PKG_EVENT, route)) {
-   tb_ctl_warn(ctl, "malformed TB_CFG_PKG_EVENT\n");
-   return;
-   }
-
-   if (tb_cfg_error(ctl, route, pkg->port, TB_CFG_ERROR_ACK_PLUG_EVENT))
-   tb_ctl_warn(ctl, "could not ack plug event on %llx:%x\n",
-   route, pkg->port);
-   WARN(pkg->zero, "pkg->zero is %#x\n", pkg->zero);
-   ctl->callback(ctl->callback_data, route, pkg->port, pkg->unplug);
+   ctl->callback(ctl->callback_data, type, pkg->buffer, size);
 }
 
 static void tb_ctl_rx_submit(struct ctl_pkg *pkg)
@@ -302,10 +293,29 @@ static void tb_ctl_rx_submit(struct ctl_pkg *pkg)
 */
 }
 
+static int tb_async_error(const struct ctl_pkg *pkg)
+{
+   const struct cfg_error_pkg *error = (const struct cfg_error_pkg *)pkg;
+
+   if (pkg->frame.eof != TB_CFG_PKG_ERROR)
+   return false;
+
+   switch (error->error) {
+   case TB_CFG_ERROR_LINK_ERROR:
+   case TB_CFG_ERROR_HEC_ERROR_DETECTED:
+   case TB_CFG_ERROR_FLOW_CONTROL_ERROR:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
 static void tb_ctl_rx_callback(struct tb_ring *ring, struct ring_frame *frame,
   bool canceled)
 {
struct ctl_pkg *pkg = container_of(frame, typeof(*pkg), frame);
+   __be32 crc32;
 
if (canceled)
return; /*
@@ -320,18 +330,42 @@ static void tb_ctl_rx_callback(struct tb_ring *ring, 
struct ring_frame *frame,
}
 
frame->size -= 4; /* remove checksum */
-   if (*(__be32 *) (pkg->buffer + frame->size)
-   != tb_crc(pkg->buffer, frame->size)) {
-   tb_ctl_err(pkg->ctl,
-  "RX: checksum mismatch, dropping packet\n");
-   goto rx;
-   }
+   crc32 = tb_crc(pkg->buffer, frame->size);
be32_to_cpu_array(pkg->buffer, pkg->buffer, frame->size / 4);
 
-   if (frame->eof == TB_CFG_PKG_EVENT) {
-   tb_ctl_handle_plug_event(pkg->ctl, pkg);
+   switch (frame->eof) {
+   case TB_CFG_PKG_READ:
+   case TB_CFG_PKG_WRITE:
+   case TB_CFG_PKG_ERROR:
+   case TB_CFG_PKG_OVERRIDE:
+   case TB_CFG_PKG_RESET:
+   if (*(__be32 *)(pkg->buffer + frame->size) != crc32) {
+   tb_ctl_err(pkg->ctl,
+  "RX: checksum mismatch, dropping packet\n");
+  

[PATCH v3 20/27] thunderbolt: Add support for NHI mailbox

[Mika Westerberg]

The host controller includes two sets of registers that are used to
communicate with the firmware. Add functions that can be used to access
these registers.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/nhi.c  | 58 ++
 drivers/thunderbolt/nhi.h  | 16 
 drivers/thunderbolt/nhi_regs.h | 11 
 3 files changed, 85 insertions(+)

diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index fa4c2745dba2..c358c074f925 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "nhi.h"
 #include "nhi_regs.h"
@@ -28,6 +29,8 @@
 #define MSIX_MIN_VECS  6
 #define MSIX_MAX_VECS  16
 
+#define NHI_MAILBOX_TIMEOUT500 /* ms */
+
 static int ring_interrupt_index(struct tb_ring *ring)
 {
int bit = ring->hop;
@@ -525,6 +528,61 @@ void ring_free(struct tb_ring *ring)
kfree(ring);
 }
 
+/**
+ * nhi_mailbox_cmd() - Send a command through NHI mailbox
+ * @nhi: Pointer to the NHI structure
+ * @cmd: Command to send
+ * @data: Data to be send with the command
+ *
+ * Sends mailbox command to the firmware running on NHI. Returns %0 in
+ * case of success and negative errno in case of failure.
+ */
+int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
+{
+   ktime_t timeout;
+   u32 val;
+
+   iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
+
+   val = ioread32(nhi->iobase + REG_INMAIL_CMD);
+   val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
+   val |= REG_INMAIL_OP_REQUEST | cmd;
+   iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
+
+   timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
+   do {
+   val = ioread32(nhi->iobase + REG_INMAIL_CMD);
+   if (!(val & REG_INMAIL_OP_REQUEST))
+   break;
+   usleep_range(10, 20);
+   } while (ktime_before(ktime_get(), timeout));
+
+   if (val & REG_INMAIL_OP_REQUEST)
+   return -ETIMEDOUT;
+   if (val & REG_INMAIL_ERROR)
+   return -EIO;
+
+   return 0;
+}
+
+/**
+ * nhi_mailbox_mode() - Return current firmware operation mode
+ * @nhi: Pointer to the NHI structure
+ *
+ * The function reads current firmware operation mode using NHI mailbox
+ * registers and returns it to the caller.
+ */
+enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
+{
+   u32 val;
+
+   val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
+   val &= REG_OUTMAIL_CMD_OPMODE_MASK;
+   val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
+
+   return (enum nhi_fw_mode)val;
+}
+
 static void nhi_interrupt_work(struct work_struct *work)
 {
struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h
index 8bd9b4e5a0b1..446ff6dac91d 100644
--- a/drivers/thunderbolt/nhi.h
+++ b/drivers/thunderbolt/nhi.h
@@ -143,6 +143,22 @@ static inline int ring_tx(struct tb_ring *ring, struct 
ring_frame *frame)
return __ring_enqueue(ring, frame);
 }
 
+enum nhi_fw_mode {
+   NHI_FW_SAFE_MODE,
+   NHI_FW_AUTH_MODE,
+   NHI_FW_EP_MODE,
+   NHI_FW_CM_MODE,
+};
+
+enum nhi_mailbox_cmd {
+   NHI_MAILBOX_SAVE_DEVS = 0x05,
+   NHI_MAILBOX_DRV_UNLOADS = 0x07,
+   NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
+};
+
+int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
+enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
+
 /*
  * PCI IDs used in this driver from Win Ridge forward. There is no
  * need for the PCI quirk anymore as we will use ICM also on Apple
diff --git a/drivers/thunderbolt/nhi_regs.h b/drivers/thunderbolt/nhi_regs.h
index 48b98d3c7e6a..322fe1fa3a3c 100644
--- a/drivers/thunderbolt/nhi_regs.h
+++ b/drivers/thunderbolt/nhi_regs.h
@@ -107,4 +107,15 @@ struct ring_desc {
 #define REG_DMA_MISC   0x39864
 #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
 
+#define REG_INMAIL_DATA0x39900
+
+#define REG_INMAIL_CMD 0x39904
+#define REG_INMAIL_CMD_MASKGENMASK(7, 0)
+#define REG_INMAIL_ERROR   BIT(30)
+#define REG_INMAIL_OP_REQUEST  BIT(31)
+
+#define REG_OUTMAIL_CMD0x3990c
+#define REG_OUTMAIL_CMD_OPMODE_SHIFT   8
+#define REG_OUTMAIL_CMD_OPMODE_MASKGENMASK(11, 8)
+
 #endif
-- 
2.11.0

[PATCH v3 01/27] thunderbolt: Use const buffer pointer in write operations

[Mika Westerberg]

These functions should not (and do not) modify the argument in any way
so make it const.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Greg Kroah-Hartman 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c | 8 
 drivers/thunderbolt/ctl.h | 4 ++--
 drivers/thunderbolt/tb.h  | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 1146ff4210a9..1031d97407a8 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -273,7 +273,7 @@ static void tb_cfg_print_error(struct tb_ctl *ctl,
}
 }
 
-static void cpu_to_be32_array(__be32 *dst, u32 *src, size_t len)
+static void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len)
 {
int i;
for (i = 0; i < len; i++)
@@ -333,7 +333,7 @@ static void tb_ctl_tx_callback(struct tb_ring *ring, struct 
ring_frame *frame,
  *
  * Return: Returns 0 on success or an error code on failure.
  */
-static int tb_ctl_tx(struct tb_ctl *ctl, void *data, size_t len,
+static int tb_ctl_tx(struct tb_ctl *ctl, const void *data, size_t len,
 enum tb_cfg_pkg_type type)
 {
int res;
@@ -650,7 +650,7 @@ struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, 
void *buffer,
  *
  * Offset and length are in dwords.
  */
-struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer,
+struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, const void *buffer,
u64 route, u32 port, enum tb_cfg_space space,
u32 offset, u32 length, int timeout_msec)
 {
@@ -695,7 +695,7 @@ int tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 
route, u32 port,
return res.err;
 }
 
-int tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
+int tb_cfg_write(struct tb_ctl *ctl, const void *buffer, u64 route, u32 port,
 enum tb_cfg_space space, u32 offset, u32 length)
 {
struct tb_cfg_result res = tb_cfg_write_raw(ctl, buffer, route, port,
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index ba87d6e731dd..83ae54947082 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -61,13 +61,13 @@ struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, 
void *buffer,
 u64 route, u32 port,
 enum tb_cfg_space space, u32 offset,
 u32 length, int timeout_msec);
-struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer,
+struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, const void *buffer,
  u64 route, u32 port,
  enum tb_cfg_space space, u32 offset,
  u32 length, int timeout_msec);
 int tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
enum tb_cfg_space space, u32 offset, u32 length);
-int tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
+int tb_cfg_write(struct tb_ctl *ctl, const void *buffer, u64 route, u32 port,
 enum tb_cfg_space space, u32 offset, u32 length);
 int tb_cfg_get_upstream_port(struct tb_ctl *ctl, u64 route);
 
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 61d57ba64035..ba2b85750335 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -173,7 +173,7 @@ static inline int tb_port_read(struct tb_port *port, void 
*buffer,
   length);
 }
 
-static inline int tb_port_write(struct tb_port *port, void *buffer,
+static inline int tb_port_write(struct tb_port *port, const void *buffer,
enum tb_cfg_space space, u32 offset, u32 length)
 {
return tb_cfg_write(port->sw->tb->ctl,
-- 
2.11.0

[PATCH v3 25/27] thunderbolt: Add support for host and device NVM firmware upgrade

[Mika Westerberg]

Starting from Intel Falcon Ridge the NVM firmware can be upgraded by
using DMA configuration based mailbox commands. If we detect that the
host or device (device support starts from Intel Alpine Ridge) has the
DMA configuration based mailbox we expose NVM information to the
userspace as two separate Linux NVMem devices: nvm_active and
nvm_non_active. The former is read-only portion of the active NVM which
firmware upgrade tools can be use to find out suitable NVM image if the
device identification strings are not enough.

The latter is write-only portion where the new NVM image is to be
written by the userspace. It is up to the userspace to find out right
NVM image (the kernel does very minimal validation). The ICM firmware
itself authenticates the new NVM firmware and fails the operation if it
is not what is expected.

We also expose two new sysfs files per each switch: nvm_version and
nvm_authenticate which can be used to read the active NVM version and
start the upgrade process.

We also introduce safe mode which is the mode a switch goes when it does
not have properly authenticated firmware. In this mode the switch only
accepts a couple of commands including flashing a new NVM firmware image
and triggering power cycle.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |  26 +
 drivers/thunderbolt/Kconfig |   1 +
 drivers/thunderbolt/domain.c|  18 +
 drivers/thunderbolt/icm.c   |  33 +-
 drivers/thunderbolt/nhi.h   |   1 +
 drivers/thunderbolt/switch.c| 603 +++-
 drivers/thunderbolt/tb.h|  40 +-
 7 files changed, 699 insertions(+), 23 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 05b7f9a6431f..2a98149943ea 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -82,3 +82,29 @@ Description: This attribute contains unique_id string of 
this device.
This is either read from hardware registers (UUID on
newer hardware) or based on UID from the device DROM.
Can be used to uniquely identify particular device.
+
+What:  /sys/bus/thunderbolt/devices/.../nvm_version
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   If the device has upgradeable firmware the version
+   number is available here. Format: %x.%x, major.minor.
+   If the device is in safe mode reading the file returns
+   -ENODATA instead as the NVM version is not available.
+
+What:  /sys/bus/thunderbolt/devices/.../nvm_authenticate
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   When new NVM image is written to the non-active NVM
+   area (through non_activeX NVMem device), the
+   authentication procedure is started by writing 1 to
+   this file. If everything goes well, the device is
+   restarted with the new NVM firmware. If the image
+   verification fails an error code is returned instead.
+
+   When read holds status of the last authentication
+   operation if an error occurred during the process. This
+   is directly the status value from the DMA configuration
+   based mailbox before the device is power cycled. Writing
+   0 here clears the status.
diff --git a/drivers/thunderbolt/Kconfig b/drivers/thunderbolt/Kconfig
index a9cc724985ad..f4869c38c7e4 100644
--- a/drivers/thunderbolt/Kconfig
+++ b/drivers/thunderbolt/Kconfig
@@ -6,6 +6,7 @@ menuconfig THUNDERBOLT
select CRC32
select CRYPTO
select CRYPTO_HASH
+   select NVMEM
help
  Thunderbolt Controller driver. This driver is required if you
  want to hotplug Thunderbolt devices on Apple hardware or on PCs
diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c
index bd491d483f7a..4544103b2cb2 100644
--- a/drivers/thunderbolt/domain.c
+++ b/drivers/thunderbolt/domain.c
@@ -425,6 +425,23 @@ int tb_domain_challenge_switch_key(struct tb *tb, struct 
tb_switch *sw)
return ret;
 }
 
+/**
+ * tb_domain_disconnect_pcie_paths() - Disconnect all PCIe paths
+ * @tb: Domain whose PCIe paths to disconnect
+ *
+ * This needs to be called in preparation for NVM upgrade of the host
+ * controller. Makes sure all PCIe paths are disconnected.
+ *
+ * Return %0 on success and negative errno in 

[PATCH v3 01/27] thunderbolt: Use const buffer pointer in write operations

[Mika Westerberg]

These functions should not (and do not) modify the argument in any way
so make it const.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Greg Kroah-Hartman 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c | 8 
 drivers/thunderbolt/ctl.h | 4 ++--
 drivers/thunderbolt/tb.h  | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 1146ff4210a9..1031d97407a8 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -273,7 +273,7 @@ static void tb_cfg_print_error(struct tb_ctl *ctl,
}
 }
 
-static void cpu_to_be32_array(__be32 *dst, u32 *src, size_t len)
+static void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len)
 {
int i;
for (i = 0; i < len; i++)
@@ -333,7 +333,7 @@ static void tb_ctl_tx_callback(struct tb_ring *ring, struct 
ring_frame *frame,
  *
  * Return: Returns 0 on success or an error code on failure.
  */
-static int tb_ctl_tx(struct tb_ctl *ctl, void *data, size_t len,
+static int tb_ctl_tx(struct tb_ctl *ctl, const void *data, size_t len,
 enum tb_cfg_pkg_type type)
 {
int res;
@@ -650,7 +650,7 @@ struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, 
void *buffer,
  *
  * Offset and length are in dwords.
  */
-struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer,
+struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, const void *buffer,
u64 route, u32 port, enum tb_cfg_space space,
u32 offset, u32 length, int timeout_msec)
 {
@@ -695,7 +695,7 @@ int tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 
route, u32 port,
return res.err;
 }
 
-int tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
+int tb_cfg_write(struct tb_ctl *ctl, const void *buffer, u64 route, u32 port,
 enum tb_cfg_space space, u32 offset, u32 length)
 {
struct tb_cfg_result res = tb_cfg_write_raw(ctl, buffer, route, port,
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index ba87d6e731dd..83ae54947082 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -61,13 +61,13 @@ struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, 
void *buffer,
 u64 route, u32 port,
 enum tb_cfg_space space, u32 offset,
 u32 length, int timeout_msec);
-struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer,
+struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, const void *buffer,
  u64 route, u32 port,
  enum tb_cfg_space space, u32 offset,
  u32 length, int timeout_msec);
 int tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
enum tb_cfg_space space, u32 offset, u32 length);
-int tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port,
+int tb_cfg_write(struct tb_ctl *ctl, const void *buffer, u64 route, u32 port,
 enum tb_cfg_space space, u32 offset, u32 length);
 int tb_cfg_get_upstream_port(struct tb_ctl *ctl, u64 route);
 
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 61d57ba64035..ba2b85750335 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -173,7 +173,7 @@ static inline int tb_port_read(struct tb_port *port, void 
*buffer,
   length);
 }
 
-static inline int tb_port_write(struct tb_port *port, void *buffer,
+static inline int tb_port_write(struct tb_port *port, const void *buffer,
enum tb_cfg_space space, u32 offset, u32 length)
 {
return tb_cfg_write(port->sw->tb->ctl,
-- 
2.11.0

[PATCH v3 25/27] thunderbolt: Add support for host and device NVM firmware upgrade

[Mika Westerberg]

Starting from Intel Falcon Ridge the NVM firmware can be upgraded by
using DMA configuration based mailbox commands. If we detect that the
host or device (device support starts from Intel Alpine Ridge) has the
DMA configuration based mailbox we expose NVM information to the
userspace as two separate Linux NVMem devices: nvm_active and
nvm_non_active. The former is read-only portion of the active NVM which
firmware upgrade tools can be use to find out suitable NVM image if the
device identification strings are not enough.

The latter is write-only portion where the new NVM image is to be
written by the userspace. It is up to the userspace to find out right
NVM image (the kernel does very minimal validation). The ICM firmware
itself authenticates the new NVM firmware and fails the operation if it
is not what is expected.

We also expose two new sysfs files per each switch: nvm_version and
nvm_authenticate which can be used to read the active NVM version and
start the upgrade process.

We also introduce safe mode which is the mode a switch goes when it does
not have properly authenticated firmware. In this mode the switch only
accepts a couple of commands including flashing a new NVM firmware image
and triggering power cycle.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |  26 +
 drivers/thunderbolt/Kconfig |   1 +
 drivers/thunderbolt/domain.c|  18 +
 drivers/thunderbolt/icm.c   |  33 +-
 drivers/thunderbolt/nhi.h   |   1 +
 drivers/thunderbolt/switch.c| 603 +++-
 drivers/thunderbolt/tb.h|  40 +-
 7 files changed, 699 insertions(+), 23 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 05b7f9a6431f..2a98149943ea 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -82,3 +82,29 @@ Description: This attribute contains unique_id string of 
this device.
This is either read from hardware registers (UUID on
newer hardware) or based on UID from the device DROM.
Can be used to uniquely identify particular device.
+
+What:  /sys/bus/thunderbolt/devices/.../nvm_version
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   If the device has upgradeable firmware the version
+   number is available here. Format: %x.%x, major.minor.
+   If the device is in safe mode reading the file returns
+   -ENODATA instead as the NVM version is not available.
+
+What:  /sys/bus/thunderbolt/devices/.../nvm_authenticate
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   When new NVM image is written to the non-active NVM
+   area (through non_activeX NVMem device), the
+   authentication procedure is started by writing 1 to
+   this file. If everything goes well, the device is
+   restarted with the new NVM firmware. If the image
+   verification fails an error code is returned instead.
+
+   When read holds status of the last authentication
+   operation if an error occurred during the process. This
+   is directly the status value from the DMA configuration
+   based mailbox before the device is power cycled. Writing
+   0 here clears the status.
diff --git a/drivers/thunderbolt/Kconfig b/drivers/thunderbolt/Kconfig
index a9cc724985ad..f4869c38c7e4 100644
--- a/drivers/thunderbolt/Kconfig
+++ b/drivers/thunderbolt/Kconfig
@@ -6,6 +6,7 @@ menuconfig THUNDERBOLT
select CRC32
select CRYPTO
select CRYPTO_HASH
+   select NVMEM
help
  Thunderbolt Controller driver. This driver is required if you
  want to hotplug Thunderbolt devices on Apple hardware or on PCs
diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c
index bd491d483f7a..4544103b2cb2 100644
--- a/drivers/thunderbolt/domain.c
+++ b/drivers/thunderbolt/domain.c
@@ -425,6 +425,23 @@ int tb_domain_challenge_switch_key(struct tb *tb, struct 
tb_switch *sw)
return ret;
 }
 
+/**
+ * tb_domain_disconnect_pcie_paths() - Disconnect all PCIe paths
+ * @tb: Domain whose PCIe paths to disconnect
+ *
+ * This needs to be called in preparation for NVM upgrade of the host
+ * controller. Makes sure all PCIe paths are disconnected.
+ *
+ * Return %0 on success and negative errno in case of error.
+ */
+int tb_domain_disconnect_pcie_paths(struct tb *tb)
+{
+   if (!tb->cm_ops->disconnect_pcie_paths)

[PATCH v3 04/27] thunderbolt: Do not warn about newer DROM versions

[Mika Westerberg]

DROM version 2 is compatible with the previous generation so no need to
warn about that.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index e4e64b130514..eb2179c98b09 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -488,7 +488,7 @@ int tb_drom_read(struct tb_switch *sw)
goto err;
}
 
-   if (header->device_rom_revision > 1)
+   if (header->device_rom_revision > 2)
tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
header->device_rom_revision);
 
-- 
2.11.0

[PATCH v3 06/27] thunderbolt: Rework capability handling

[Mika Westerberg]

Organization of the capabilities in switches and ports is not so random
after all. Rework the capability handling functionality so that it
follows how capabilities are organized and provide two new functions
(tb_switch_find_vsec_cap() and tb_port_find_cap()) which can be used to
extract capabilities for ports and switches. Then convert the current
users over these.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/cap.c| 169 +--
 drivers/thunderbolt/switch.c |   6 +-
 drivers/thunderbolt/tb.c |   8 +-
 drivers/thunderbolt/tb.h |   3 +-
 drivers/thunderbolt/tb_regs.h|  50 +---
 drivers/thunderbolt/tunnel_pci.c |   8 +-
 6 files changed, 142 insertions(+), 102 deletions(-)

diff --git a/drivers/thunderbolt/cap.c b/drivers/thunderbolt/cap.c
index a7b47e7cddbd..7260971acc4f 100644
--- a/drivers/thunderbolt/cap.c
+++ b/drivers/thunderbolt/cap.c
@@ -9,6 +9,8 @@
 
 #include "tb.h"
 
+#define CAP_OFFSET_MAX 0xff
+#define VSEC_CAP_OFFSET_MAX0x
 
 struct tb_cap_any {
union {
@@ -18,99 +20,110 @@ struct tb_cap_any {
};
 } __packed;
 
-static bool tb_cap_is_basic(struct tb_cap_any *cap)
-{
-   /* basic.cap is u8. This checks only the lower 8 bit of cap. */
-   return cap->basic.cap != 5;
-}
-
-static bool tb_cap_is_long(struct tb_cap_any *cap)
+/**
+ * tb_port_find_cap() - Find port capability
+ * @port: Port to find the capability for
+ * @cap: Capability to look
+ *
+ * Returns offset to start of capability or %-ENOENT if no such
+ * capability was found. Negative errno is returned if there was an
+ * error.
+ */
+int tb_port_find_cap(struct tb_port *port, enum tb_port_cap cap)
 {
-   return !tb_cap_is_basic(cap)
-  && cap->extended_short.next == 0
-  && cap->extended_short.length == 0;
-}
+   u32 offset;
 
-static enum tb_cap tb_cap(struct tb_cap_any *cap)
-{
-   if (tb_cap_is_basic(cap))
-   return cap->basic.cap;
+   /*
+* DP out adapters claim to implement TMU capability but in
+* reality they do not so we hard code the adapter specific
+* capability offset here.
+*/
+   if (port->config.type == TB_TYPE_DP_HDMI_OUT)
+   offset = 0x39;
else
-   /* extended_short/long have cap at the same offset. */
-   return cap->extended_short.cap;
+   offset = 0x1;
+
+   do {
+   struct tb_cap_any header;
+   int ret;
+
+   ret = tb_port_read(port, , TB_CFG_PORT, offset, 1);
+   if (ret)
+   return ret;
+
+   if (header.basic.cap == cap)
+   return offset;
+
+   offset = header.basic.next;
+   } while (offset);
+
+   return -ENOENT;
 }
 
-static u32 tb_cap_next(struct tb_cap_any *cap, u32 offset)
+static int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap)
 {
-   int next;
-   if (offset == 1) {
-   /*
-* The first pointer is part of the switch header and always
-* a simple pointer.
-*/
-   next = cap->basic.next;
-   } else {
-   /*
-* Somehow Intel decided to use 3 different types of capability
-* headers. It is not like anyone could have predicted that
-* single byte offsets are not enough...
-*/
-   if (tb_cap_is_basic(cap))
-   next = cap->basic.next;
-   else if (!tb_cap_is_long(cap))
-   next = cap->extended_short.next;
-   else
-   next = cap->extended_long.next;
+   int offset = sw->config.first_cap_offset;
+
+   while (offset > 0 && offset < CAP_OFFSET_MAX) {
+   struct tb_cap_any header;
+   int ret;
+
+   ret = tb_sw_read(sw, , TB_CFG_SWITCH, offset, 1);
+   if (ret)
+   return ret;
+
+   if (header.basic.cap == cap)
+   return offset;
+
+   offset = header.basic.next;
}
-   /*
-* "Hey, we could terminate some capability lists with a null offset
-*  and others with a pointer to the last element." - "Great idea!"
-*/
-   if (next == offset)
-   return 0;
-   return next;
+
+   return -ENOENT;
 }
 
 /**
- * tb_find_cap() - find a capability
+ * tb_switch_find_vsec_cap() - Find switch vendor specific capability
+ * @sw: Switch to find the capability for
+ * @vsec: Vendor specific capability to look
  *
- * Return: Returns a positive offset if the capability was found and 0 if not.
- * 

[PATCH v3 04/27] thunderbolt: Do not warn about newer DROM versions

[Mika Westerberg]

DROM version 2 is compatible with the previous generation so no need to
warn about that.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/eeprom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c
index e4e64b130514..eb2179c98b09 100644
--- a/drivers/thunderbolt/eeprom.c
+++ b/drivers/thunderbolt/eeprom.c
@@ -488,7 +488,7 @@ int tb_drom_read(struct tb_switch *sw)
goto err;
}
 
-   if (header->device_rom_revision > 1)
+   if (header->device_rom_revision > 2)
tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
header->device_rom_revision);
 
-- 
2.11.0

[PATCH v3 06/27] thunderbolt: Rework capability handling

[Mika Westerberg]

Organization of the capabilities in switches and ports is not so random
after all. Rework the capability handling functionality so that it
follows how capabilities are organized and provide two new functions
(tb_switch_find_vsec_cap() and tb_port_find_cap()) which can be used to
extract capabilities for ports and switches. Then convert the current
users over these.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/cap.c| 169 +--
 drivers/thunderbolt/switch.c |   6 +-
 drivers/thunderbolt/tb.c |   8 +-
 drivers/thunderbolt/tb.h |   3 +-
 drivers/thunderbolt/tb_regs.h|  50 +---
 drivers/thunderbolt/tunnel_pci.c |   8 +-
 6 files changed, 142 insertions(+), 102 deletions(-)

diff --git a/drivers/thunderbolt/cap.c b/drivers/thunderbolt/cap.c
index a7b47e7cddbd..7260971acc4f 100644
--- a/drivers/thunderbolt/cap.c
+++ b/drivers/thunderbolt/cap.c
@@ -9,6 +9,8 @@
 
 #include "tb.h"
 
+#define CAP_OFFSET_MAX 0xff
+#define VSEC_CAP_OFFSET_MAX0x
 
 struct tb_cap_any {
union {
@@ -18,99 +20,110 @@ struct tb_cap_any {
};
 } __packed;
 
-static bool tb_cap_is_basic(struct tb_cap_any *cap)
-{
-   /* basic.cap is u8. This checks only the lower 8 bit of cap. */
-   return cap->basic.cap != 5;
-}
-
-static bool tb_cap_is_long(struct tb_cap_any *cap)
+/**
+ * tb_port_find_cap() - Find port capability
+ * @port: Port to find the capability for
+ * @cap: Capability to look
+ *
+ * Returns offset to start of capability or %-ENOENT if no such
+ * capability was found. Negative errno is returned if there was an
+ * error.
+ */
+int tb_port_find_cap(struct tb_port *port, enum tb_port_cap cap)
 {
-   return !tb_cap_is_basic(cap)
-  && cap->extended_short.next == 0
-  && cap->extended_short.length == 0;
-}
+   u32 offset;
 
-static enum tb_cap tb_cap(struct tb_cap_any *cap)
-{
-   if (tb_cap_is_basic(cap))
-   return cap->basic.cap;
+   /*
+* DP out adapters claim to implement TMU capability but in
+* reality they do not so we hard code the adapter specific
+* capability offset here.
+*/
+   if (port->config.type == TB_TYPE_DP_HDMI_OUT)
+   offset = 0x39;
else
-   /* extended_short/long have cap at the same offset. */
-   return cap->extended_short.cap;
+   offset = 0x1;
+
+   do {
+   struct tb_cap_any header;
+   int ret;
+
+   ret = tb_port_read(port, , TB_CFG_PORT, offset, 1);
+   if (ret)
+   return ret;
+
+   if (header.basic.cap == cap)
+   return offset;
+
+   offset = header.basic.next;
+   } while (offset);
+
+   return -ENOENT;
 }
 
-static u32 tb_cap_next(struct tb_cap_any *cap, u32 offset)
+static int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap)
 {
-   int next;
-   if (offset == 1) {
-   /*
-* The first pointer is part of the switch header and always
-* a simple pointer.
-*/
-   next = cap->basic.next;
-   } else {
-   /*
-* Somehow Intel decided to use 3 different types of capability
-* headers. It is not like anyone could have predicted that
-* single byte offsets are not enough...
-*/
-   if (tb_cap_is_basic(cap))
-   next = cap->basic.next;
-   else if (!tb_cap_is_long(cap))
-   next = cap->extended_short.next;
-   else
-   next = cap->extended_long.next;
+   int offset = sw->config.first_cap_offset;
+
+   while (offset > 0 && offset < CAP_OFFSET_MAX) {
+   struct tb_cap_any header;
+   int ret;
+
+   ret = tb_sw_read(sw, , TB_CFG_SWITCH, offset, 1);
+   if (ret)
+   return ret;
+
+   if (header.basic.cap == cap)
+   return offset;
+
+   offset = header.basic.next;
}
-   /*
-* "Hey, we could terminate some capability lists with a null offset
-*  and others with a pointer to the last element." - "Great idea!"
-*/
-   if (next == offset)
-   return 0;
-   return next;
+
+   return -ENOENT;
 }
 
 /**
- * tb_find_cap() - find a capability
+ * tb_switch_find_vsec_cap() - Find switch vendor specific capability
+ * @sw: Switch to find the capability for
+ * @vsec: Vendor specific capability to look
  *
- * Return: Returns a positive offset if the capability was found and 0 if not.
- * Returns an error code on failure.
+ * Functions enumerates vendor specific (VSEC) capabilities of a switch
+ * and 

[PATCH v3 24/27] thunderbolt: Add support for Internal Connection Manager (ICM)

[Mika Westerberg]

Starting from Intel Falcon Ridge the internal connection manager running
on the Thunderbolt host controller has been supporting 4 security
levels. One reason for this is to prevent DMA attacks and only allow
connecting devices the user trusts.

The internal connection manager (ICM) is the preferred way of connecting
Thunderbolt devices over software only implementation typically used on
Macs. The driver communicates with ICM using special Thunderbolt ring 0
(control channel) messages. In order to handle these messages we add
support for the ICM messages to the control channel.

The security levels are as follows:

  none - No security, all tunnels are created automatically
  user - User needs to approve the device before tunnels are created
  secure - User need to approve the device before tunnels are created.
   The device is sent a challenge on future connects to be able
   to verify it is actually the approved device.
  dponly - Only Display Port and USB tunnels can be created and those
   are created automatically.

The security levels are typically configurable from the system BIOS and
by default it is set to "user" on many systems.

In this patch each Thunderbolt device will have either one or two new
sysfs attributes: authorized and key. The latter appears for devices
that support secure connect.

In order to identify the device the user can read identication
information, including UUID and name of the device from sysfs and based
on that make a decision to authorize the device. The device is
authorized by simply writing 1 to the "authorized" sysfs attribute. This
is following the USB bus device authorization mechanism. The secure
connect requires an additional challenge step (writing 2 to the
"authorized" attribute) in future connects when the key has already been
stored to the NVM of the device.

Non-ICM systems (before Alpine Ridge) continue to use the existing
functionality and the security level is set to none. For systems with
Alpine Ridge, even on Apple hardware, we will use ICM.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |   48 +
 drivers/thunderbolt/Kconfig |   12 +-
 drivers/thunderbolt/Makefile|2 +-
 drivers/thunderbolt/ctl.c   |2 +
 drivers/thunderbolt/domain.c|  195 +
 drivers/thunderbolt/icm.c   | 1058 +++
 drivers/thunderbolt/nhi.c   |   33 +-
 drivers/thunderbolt/nhi_regs.h  |7 +
 drivers/thunderbolt/switch.c|  222 +
 drivers/thunderbolt/tb.c|7 +
 drivers/thunderbolt/tb.h|   79 ++
 drivers/thunderbolt/tb_msgs.h   |  152 
 12 files changed, 1805 insertions(+), 12 deletions(-)
 create mode 100644 drivers/thunderbolt/icm.c

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 29a516f53d2c..05b7f9a6431f 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -1,3 +1,51 @@
+What: /sys/bus/thunderbolt/devices/.../domainX/security
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute holds current Thunderbolt security level
+   set by the system BIOS. Possible values are:
+
+   none: All devices are automatically authorized
+   user: Devices are only authorized based on writing
+ appropriate value to the authorized attribute
+   secure: Require devices that support secure connect at
+   minimum. User needs to authorize each device.
+   dponly: Automatically tunnel Display port (and USB). No
+   PCIe tunnels are created.
+
+What: /sys/bus/thunderbolt/devices/.../authorized
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute is used to authorize Thunderbolt devices
+   after they have been connected. If the device is not
+   authorized, no devices such as PCIe and Display port are
+   available to the system.
+
+   Contents of this attribute will be 0 when the device is not
+   yet authorized.
+
+   Possible values are supported:
+   1: The device will be authorized and connected
+
+   When key attribute contains 32 byte hex string the possible
+   values are:
+   1: The 32 byte hex 

[PATCH v3 24/27] thunderbolt: Add support for Internal Connection Manager (ICM)

[Mika Westerberg]

Starting from Intel Falcon Ridge the internal connection manager running
on the Thunderbolt host controller has been supporting 4 security
levels. One reason for this is to prevent DMA attacks and only allow
connecting devices the user trusts.

The internal connection manager (ICM) is the preferred way of connecting
Thunderbolt devices over software only implementation typically used on
Macs. The driver communicates with ICM using special Thunderbolt ring 0
(control channel) messages. In order to handle these messages we add
support for the ICM messages to the control channel.

The security levels are as follows:

  none - No security, all tunnels are created automatically
  user - User needs to approve the device before tunnels are created
  secure - User need to approve the device before tunnels are created.
   The device is sent a challenge on future connects to be able
   to verify it is actually the approved device.
  dponly - Only Display Port and USB tunnels can be created and those
   are created automatically.

The security levels are typically configurable from the system BIOS and
by default it is set to "user" on many systems.

In this patch each Thunderbolt device will have either one or two new
sysfs attributes: authorized and key. The latter appears for devices
that support secure connect.

In order to identify the device the user can read identication
information, including UUID and name of the device from sysfs and based
on that make a decision to authorize the device. The device is
authorized by simply writing 1 to the "authorized" sysfs attribute. This
is following the USB bus device authorization mechanism. The secure
connect requires an additional challenge step (writing 2 to the
"authorized" attribute) in future connects when the key has already been
stored to the NVM of the device.

Non-ICM systems (before Alpine Ridge) continue to use the existing
functionality and the security level is set to none. For systems with
Alpine Ridge, even on Apple hardware, we will use ICM.

This code is based on the work done by Amir Levy and Michael Jamet.

Signed-off-by: Michael Jamet 
Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Andy Shevchenko 
---
 Documentation/ABI/testing/sysfs-bus-thunderbolt |   48 +
 drivers/thunderbolt/Kconfig |   12 +-
 drivers/thunderbolt/Makefile|2 +-
 drivers/thunderbolt/ctl.c   |2 +
 drivers/thunderbolt/domain.c|  195 +
 drivers/thunderbolt/icm.c   | 1058 +++
 drivers/thunderbolt/nhi.c   |   33 +-
 drivers/thunderbolt/nhi_regs.h  |7 +
 drivers/thunderbolt/switch.c|  222 +
 drivers/thunderbolt/tb.c|7 +
 drivers/thunderbolt/tb.h|   79 ++
 drivers/thunderbolt/tb_msgs.h   |  152 
 12 files changed, 1805 insertions(+), 12 deletions(-)
 create mode 100644 drivers/thunderbolt/icm.c

diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt 
b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 29a516f53d2c..05b7f9a6431f 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -1,3 +1,51 @@
+What: /sys/bus/thunderbolt/devices/.../domainX/security
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute holds current Thunderbolt security level
+   set by the system BIOS. Possible values are:
+
+   none: All devices are automatically authorized
+   user: Devices are only authorized based on writing
+ appropriate value to the authorized attribute
+   secure: Require devices that support secure connect at
+   minimum. User needs to authorize each device.
+   dponly: Automatically tunnel Display port (and USB). No
+   PCIe tunnels are created.
+
+What: /sys/bus/thunderbolt/devices/.../authorized
+Date:  Sep 2017
+KernelVersion: 4.13
+Contact:   thunderbolt-softw...@lists.01.org
+Description:   This attribute is used to authorize Thunderbolt devices
+   after they have been connected. If the device is not
+   authorized, no devices such as PCIe and Display port are
+   available to the system.
+
+   Contents of this attribute will be 0 when the device is not
+   yet authorized.
+
+   Possible values are supported:
+   1: The device will be authorized and connected
+
+   When key attribute contains 32 byte hex string the possible
+   values are:
+   1: The 32 byte hex string is added to the device NVM and
+  the device is authorized.
+   2: Send a challenge 

[PATCH v3 07/27] thunderbolt: Allow passing NULL to tb_ctl_free()

[Mika Westerberg]

Following the usual pattern used in many places, we allow passing NULL
pointer to tb_ctl_free(). Then the user can call the function regardless
if it has allocated control channel or not making the code bit simpler.

Suggested-by: Andy Shevchenko 
Signed-off-by: Mika Westerberg 
---
 drivers/thunderbolt/ctl.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 889a32dd21e7..f8290a577b2b 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -520,6 +520,10 @@ struct tb_ctl *tb_ctl_alloc(struct tb_nhi *nhi, hotplug_cb 
cb, void *cb_data)
 void tb_ctl_free(struct tb_ctl *ctl)
 {
int i;
+
+   if (!ctl)
+   return;
+
if (ctl->rx)
ring_free(ctl->rx);
if (ctl->tx)
-- 
2.11.0

[PATCH v3 07/27] thunderbolt: Allow passing NULL to tb_ctl_free()

[Mika Westerberg]

Following the usual pattern used in many places, we allow passing NULL
pointer to tb_ctl_free(). Then the user can call the function regardless
if it has allocated control channel or not making the code bit simpler.

Suggested-by: Andy Shevchenko 
Signed-off-by: Mika Westerberg 
---
 drivers/thunderbolt/ctl.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 889a32dd21e7..f8290a577b2b 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -520,6 +520,10 @@ struct tb_ctl *tb_ctl_alloc(struct tb_nhi *nhi, hotplug_cb 
cb, void *cb_data)
 void tb_ctl_free(struct tb_ctl *ctl)
 {
int i;
+
+   if (!ctl)
+   return;
+
if (ctl->rx)
ring_free(ctl->rx);
if (ctl->tx)
-- 
2.11.0

[PATCH v3 15/27] thunderbolt: Expose get_route() to other files

[Mika Westerberg]

We are going to use it when we change the connection manager to handle
events itself. Also rename it to follow naming convention used in
functions exposed in ctl.h.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c | 19 +++
 drivers/thunderbolt/ctl.h |  4 
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 24118c60b062..8352ee8662aa 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -54,11 +54,6 @@ struct tb_ctl {
 
 /* utility functions */
 
-static u64 get_route(struct tb_cfg_header header)
-{
-   return (u64) header.route_hi << 32 | header.route_lo;
-}
-
 static struct tb_cfg_header make_header(u64 route)
 {
struct tb_cfg_header header = {
@@ -66,7 +61,7 @@ static struct tb_cfg_header make_header(u64 route)
.route_lo = route,
};
/* check for overflow, route_hi is not 32 bits! */
-   WARN_ON(get_route(header) != route);
+   WARN_ON(tb_cfg_get_route() != route);
return header;
 }
 
@@ -91,9 +86,9 @@ static int check_header(struct ctl_pkg *pkg, u32 len, enum 
tb_cfg_pkg_type type,
if (WARN(header->unknown != 1 << 9,
"header->unknown is %#x\n", header->unknown))
return -EIO;
-   if (WARN(route != get_route(*header),
+   if (WARN(route != tb_cfg_get_route(header),
"wrong route (expected %llx, got %llx)",
-   route, get_route(*header)))
+   route, tb_cfg_get_route(header)))
return -EIO;
return 0;
 }
@@ -126,10 +121,10 @@ static struct tb_cfg_result decode_error(struct ctl_pkg 
*response)
 {
struct cfg_error_pkg *pkg = response->buffer;
struct tb_cfg_result res = { 0 };
-   res.response_route = get_route(pkg->header);
+   res.response_route = tb_cfg_get_route(>header);
res.response_port = 0;
res.err = check_header(response, sizeof(*pkg), TB_CFG_PKG_ERROR,
-  get_route(pkg->header));
+  tb_cfg_get_route(>header));
if (res.err)
return res;
 
@@ -153,7 +148,7 @@ static struct tb_cfg_result parse_header(struct ctl_pkg 
*pkg, u32 len,
return decode_error(pkg);
 
res.response_port = 0; /* will be updated later for cfg_read/write */
-   res.response_route = get_route(*header);
+   res.response_route = tb_cfg_get_route(header);
res.err = check_header(pkg, len, type, route);
return res;
 }
@@ -294,7 +289,7 @@ static void tb_ctl_handle_plug_event(struct tb_ctl *ctl,
 struct ctl_pkg *response)
 {
struct cfg_event_pkg *pkg = response->buffer;
-   u64 route = get_route(pkg->header);
+   u64 route = tb_cfg_get_route(>header);
 
if (check_header(response, sizeof(*pkg), TB_CFG_PKG_EVENT, route)) {
tb_ctl_warn(ctl, "malformed TB_CFG_PKG_EVENT\n");
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index 610980e3232f..9812b1c86d4f 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -38,6 +38,10 @@ struct tb_cfg_result {
enum tb_cfg_error tb_error; /* valid if err == 1 */
 };
 
+static inline u64 tb_cfg_get_route(const struct tb_cfg_header *header)
+{
+   return (u64) header->route_hi << 32 | header->route_lo;
+}
 
 int tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port,
 enum tb_cfg_error error);
-- 
2.11.0

[PATCH v3 15/27] thunderbolt: Expose get_route() to other files

[Mika Westerberg]

We are going to use it when we change the connection manager to handle
events itself. Also rename it to follow naming convention used in
functions exposed in ctl.h.

Signed-off-by: Mika Westerberg 
Reviewed-by: Yehezkel Bernat 
Reviewed-by: Michael Jamet 
Reviewed-by: Andy Shevchenko 
---
 drivers/thunderbolt/ctl.c | 19 +++
 drivers/thunderbolt/ctl.h |  4 
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c
index 24118c60b062..8352ee8662aa 100644
--- a/drivers/thunderbolt/ctl.c
+++ b/drivers/thunderbolt/ctl.c
@@ -54,11 +54,6 @@ struct tb_ctl {
 
 /* utility functions */
 
-static u64 get_route(struct tb_cfg_header header)
-{
-   return (u64) header.route_hi << 32 | header.route_lo;
-}
-
 static struct tb_cfg_header make_header(u64 route)
 {
struct tb_cfg_header header = {
@@ -66,7 +61,7 @@ static struct tb_cfg_header make_header(u64 route)
.route_lo = route,
};
/* check for overflow, route_hi is not 32 bits! */
-   WARN_ON(get_route(header) != route);
+   WARN_ON(tb_cfg_get_route() != route);
return header;
 }
 
@@ -91,9 +86,9 @@ static int check_header(struct ctl_pkg *pkg, u32 len, enum 
tb_cfg_pkg_type type,
if (WARN(header->unknown != 1 << 9,
"header->unknown is %#x\n", header->unknown))
return -EIO;
-   if (WARN(route != get_route(*header),
+   if (WARN(route != tb_cfg_get_route(header),
"wrong route (expected %llx, got %llx)",
-   route, get_route(*header)))
+   route, tb_cfg_get_route(header)))
return -EIO;
return 0;
 }
@@ -126,10 +121,10 @@ static struct tb_cfg_result decode_error(struct ctl_pkg 
*response)
 {
struct cfg_error_pkg *pkg = response->buffer;
struct tb_cfg_result res = { 0 };
-   res.response_route = get_route(pkg->header);
+   res.response_route = tb_cfg_get_route(>header);
res.response_port = 0;
res.err = check_header(response, sizeof(*pkg), TB_CFG_PKG_ERROR,
-  get_route(pkg->header));
+  tb_cfg_get_route(>header));
if (res.err)
return res;
 
@@ -153,7 +148,7 @@ static struct tb_cfg_result parse_header(struct ctl_pkg 
*pkg, u32 len,
return decode_error(pkg);
 
res.response_port = 0; /* will be updated later for cfg_read/write */
-   res.response_route = get_route(*header);
+   res.response_route = tb_cfg_get_route(header);
res.err = check_header(pkg, len, type, route);
return res;
 }
@@ -294,7 +289,7 @@ static void tb_ctl_handle_plug_event(struct tb_ctl *ctl,
 struct ctl_pkg *response)
 {
struct cfg_event_pkg *pkg = response->buffer;
-   u64 route = get_route(pkg->header);
+   u64 route = tb_cfg_get_route(>header);
 
if (check_header(response, sizeof(*pkg), TB_CFG_PKG_EVENT, route)) {
tb_ctl_warn(ctl, "malformed TB_CFG_PKG_EVENT\n");
diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h
index 610980e3232f..9812b1c86d4f 100644
--- a/drivers/thunderbolt/ctl.h
+++ b/drivers/thunderbolt/ctl.h
@@ -38,6 +38,10 @@ struct tb_cfg_result {
enum tb_cfg_error tb_error; /* valid if err == 1 */
 };
 
+static inline u64 tb_cfg_get_route(const struct tb_cfg_header *header)
+{
+   return (u64) header->route_hi << 32 | header->route_lo;
+}
 
 int tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port,
 enum tb_cfg_error error);
-- 
2.11.0