Re: [PATCH 0/3] ANDROID: binder: reconcile with android common tree

[Martijn Coenen]

On Sat, Jul 29, 2017 at 1:22 AM, Greg KH  wrote:
> Ok, do some of these need to go to Linus now for 4.13-final and to the
> stable trees to match up with the 3 that are already proposed for the
> stable trees?  If so, which ones?

"fix proc->tsk check" is a fix for "c4ea41ba195d ("binder: use group
leader instead of open thread") which Todd sent to LKML just two weeks
ago; it should definitely go to 4.13-final if it still can, and
basically all the -stable kernels that patch ended up in (I think Todd
proposed back to 4.4).

The other two commits are related to the multiple domains /
scatter-gather patches that were upstreamed about 6 months ago (eg
7980240b6d63e); I saw those landed in 4.11-rc1 first.

Thanks,
Martijn

>
> thanks,
>
> greg k-h

Re: [PATCH] mm: don't zero ballooned pages

[Michal Hocko]

On Mon 31-07-17 12:13:33, Wei Wang wrote:
> Ballooned pages will be marked as MADV_DONTNEED by the hypervisor and
> shouldn't be given to the host ksmd to scan.

Could you point me where this MADV_DONTNEED is done, please?

> Therefore, it is not
> necessary to zero ballooned pages, which is very time consuming when
> the page amount is large. The ongoing fast balloon tests show that the
> time to balloon 7G pages is increased from ~491ms to 2.8 seconds with
> __GFP_ZERO added. So, this patch removes the flag.

Please make it obvious that this is a revert of bb01b64cfab7
("mm/balloon_compaction.c: enqueue zero page to balloon device").

> Signed-off-by: Wei Wang 
> ---
>  mm/balloon_compaction.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/mm/balloon_compaction.c b/mm/balloon_compaction.c
> index 9075aa5..b06d9fe 100644
> --- a/mm/balloon_compaction.c
> +++ b/mm/balloon_compaction.c
> @@ -24,7 +24,7 @@ struct page *balloon_page_enqueue(struct balloon_dev_info 
> *b_dev_info)
>  {
>   unsigned long flags;
>   struct page *page = alloc_page(balloon_mapping_gfp_mask() |
> - __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_ZERO);
> +__GFP_NOMEMALLOC | __GFP_NORETRY);
>   if (!page)
>   return NULL;
>  
> -- 
> 2.7.4
> 

-- 
Michal Hocko
SUSE Labs

[PATCH v3 2/5] [RESEND] [media]: rockchip/rga: v4l2 m2m support

[Jacob Chen]

Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness

The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the rendering pipeline.
 - copy
 - fast solid color fill
 - rotation
 - flip
 - alpha blending

The code in rga-hw.c is used to configure regs accroding to operations
The code in rga-buf.c is used to create (1-Level)mmu table for RGA

Signed-off-by: Jacob Chen 
---
 drivers/media/platform/Kconfig|  11 +
 drivers/media/platform/Makefile   |   2 +
 drivers/media/platform/rockchip-rga/Makefile  |   3 +
 drivers/media/platform/rockchip-rga/rga-buf.c | 141 
 drivers/media/platform/rockchip-rga/rga-hw.c  | 650 +
 drivers/media/platform/rockchip-rga/rga-hw.h  | 437 
 drivers/media/platform/rockchip-rga/rga.c | 987 ++
 drivers/media/platform/rockchip-rga/rga.h | 110 +++
 8 files changed, 2341 insertions(+)
 create mode 100644 drivers/media/platform/rockchip-rga/Makefile
 create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
 create mode 100644 drivers/media/platform/rockchip-rga/rga.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga.h

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index c9106e1..8199bcf 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -411,6 +411,17 @@ config VIDEO_RENESAS_VSP1
  To compile this driver as a module, choose M here: the module
  will be called vsp1.
 
+config VIDEO_ROCKCHIP_RGA
+   tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
+   depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select VIDEOBUF2_DMA_SG
+   select V4L2_MEM2MEM_DEV
+   default n
+   ---help---
+ This is a v4l2 driver for Rockchip SOC RGA2
+ 2d graphics accelerator.
+
 config VIDEO_TI_VPE
tristate "TI VPE (Video Processing Engine) driver"
depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 349ddf6..3bf096f 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1)  += rcar_fdp1.o
 obj-$(CONFIG_VIDEO_RENESAS_JPU)+= rcar_jpu.o
 obj-$(CONFIG_VIDEO_RENESAS_VSP1)   += vsp1/
 
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)   += rockchip-rga/
+
 obj-y  += omap/
 
 obj-$(CONFIG_VIDEO_AM437X_VPFE)+= am437x/
diff --git a/drivers/media/platform/rockchip-rga/Makefile 
b/drivers/media/platform/rockchip-rga/Makefile
new file mode 100644
index 000..92fe254
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/Makefile
@@ -0,0 +1,3 @@
+rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c 
b/drivers/media/platform/rockchip-rga/rga-buf.c
new file mode 100644
index 000..b4d28e3
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-buf.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rga-hw.h"
+#include "rga.h"
+
+static int
+rga_queue_setup(struct vb2_queue *vq,
+   unsigned int *nbuffers, unsigned int *nplanes,
+   unsigned int sizes[], struct device *alloc_devs[])
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vq);
+   struct rga_frame *f = rga_get_frame(ctx, vq->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   sizes[0] = f->size;
+   *nplanes = 1;
+
+   if (*nbuffers == 0)
+   *nbuffers = 1;
+
+   return 0;
+}
+
+static int rga_buf_prepare(struct vb2_buffer *vb)
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+   struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   vb2_set_plane_payload(vb, 0, f->size);
+
+   return 0;
+}
+
+static void rga_buf_queue(struct vb2_buffer *vb)
+{
+   struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+   st

[PATCH] infiniband: avoid overflow warning

[Arnd Bergmann]

A sockaddr_in structure on the stack getting passed into rdma_ip2gid
triggers this warning, since we memcpy into a larger sockaddr_in6
structure:

In function 'memcpy',
inlined from 'rdma_ip2gid' at include/rdma/ib_addr.h:175:3,
inlined from 'addr_event.isra.4.constprop' at 
drivers/infiniband/core/roce_gid_mgmt.c:693:2,
inlined from 'inetaddr_event' at 
drivers/infiniband/core/roce_gid_mgmt.c:716:9:
include/linux/string.h:305:4: error: call to '__read_overflow2' declared with 
attribute error: detected read beyond size of object passed as 2nd parameter

The warning seems appropriate here, but the code is also clearly
correct, so we really just want to shut up this instance of the
output.

The best way I found so far is to avoid the memcpy() call and instead
replace it with a struct assignment.

Fixes: 6974f0c4555e ("include/linux/string.h: add the option of fortified 
string.h functions")
Cc: Daniel Micay 
Cc: Kees Cook 
Signed-off-by: Arnd Bergmann 
---
 include/rdma/ib_addr.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h
index 7aca12188ef3..ec5008cf5d51 100644
--- a/include/rdma/ib_addr.h
+++ b/include/rdma/ib_addr.h
@@ -172,7 +172,8 @@ static inline int rdma_ip2gid(struct sockaddr *addr, union 
ib_gid *gid)
   (struct in6_addr *)gid);
break;
case AF_INET6:
-   memcpy(gid->raw, &((struct sockaddr_in6 *)addr)->sin6_addr, 16);
+   *(struct in6_addr *)&gid->raw =
+   ((struct sockaddr_in6 *)addr)->sin6_addr;
break;
default:
return -EINVAL;
-- 
2.9.0

Re: gigantic hugepages vs. movable zones

[Michal Hocko]

On Fri 28-07-17 13:48:28, Mike Kravetz wrote:
> On 07/26/2017 03:50 AM, Michal Hocko wrote:
> > Hi,
> > I've just noticed that alloc_gigantic_page ignores movability of the
> > gigantic page and it uses any existing zone. Considering that
> > hugepage_migration_supported only supports 2MB and pgd level hugepages
> > then 1GB pages are not migratable and as such allocating them from a
> > movable zone will break the basic expectation of this zone. Standard
> > hugetlb allocations try to avoid that by using htlb_alloc_mask and I
> > believe we should do the same for gigantic pages as well.
> > 
> > I suspect this behavior is not intentional. What do you think about the
> > following untested patch?
> > ---
> > From 542d32c1eca7dcf38afca1a91bca4a472f6e8651 Mon Sep 17 00:00:00 2001
> > From: Michal Hocko 
> > Date: Wed, 26 Jul 2017 12:43:43 +0200
> > Subject: [PATCH] mm, hugetlb: do not allocate non-migrateable gigantic pages
> >  from movable zones
> > 
> > alloc_gigantic_page doesn't consider movability of the gigantic hugetlb
> > when scanning eligible ranges for the allocation. As 1GB hugetlb pages
> > are not movable currently this can break the movable zone assumption
> > that all allocations are migrateable and as such break memory hotplug.
> > 
> > Reorganize the code and use the standard zonelist allocations scheme
> > that we use for standard hugetbl pages. htlb_alloc_mask will ensure that
> > only migratable hugetlb pages will ever see a movable zone.
> > 
> > Fixes: 944d9fec8d7a ("hugetlb: add support for gigantic page allocation at 
> > runtime")
> > Signed-off-by: Michal Hocko 
> 
> This seems reasonable to me, and I like the fact that the code is more
> like the default huge page case.  I don't see any issues with the code.
> I did some simple smoke testing of allocating 1G pages with the new code
> and ensuring they ended up as expected.
>
> Reviewed-by: Mike Kravetz 

Thanks a lot Mike! I will play with this some more today and tomorrow
and send the final patch later this week.
-- 
Michal Hocko
SUSE Labs

Re: [PATCH 2/2] mm: replace TIF_MEMDIE checks by tsk_is_oom_victim

[Michal Hocko]

On Sat 29-07-17 16:33:35, kbuild test robot wrote:
> Hi Michal,
> 
> [auto build test ERROR on cgroup/for-next]
> [also build test ERROR on v4.13-rc2 next-20170728]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Michal-Hocko/mm-oom-do-not-rely-on-TIF_MEMDIE-for-memory-reserves-access/20170728-101955
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git for-next
> config: i386-randconfig-c0-07291424 (attached as .config)
> compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=i386 
> 
> All errors (new ones prefixed by >>):
> 
>In file included from include/linux/ioport.h:12:0,
> from include/linux/device.h:16,
> from include/linux/node.h:17,
> from include/linux/cpu.h:16,
> from kernel/cgroup/cpuset.c:25:
>kernel/cgroup/cpuset.c: In function '__cpuset_node_allowed':
> >> include/linux/compiler.h:123:18: error: implicit declaration of function 
> >> 'tsk_is_oom_victim' [-Werror=implicit-function-declaration]

Thanks for the report. We need this
---
commit 638b5ab1ed275f23b52a71941b66c8966d332cd7
Author: Michal Hocko 
Date:   Mon Jul 31 08:45:53 2017 +0200

fold me

- fix implicit declaration of function 'tsk_is_oom_victim' reported by
  0day

Signed-off-by: Michal Hocko 

diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c
index 1cc53dff0d94..734ae4fa9775 100644
--- a/kernel/cgroup/cpuset.c
+++ b/kernel/cgroup/cpuset.c
@@ -56,6 +56,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
-- 
Michal Hocko
SUSE Labs

[PATCH 4/4] arm64: dts: msm8996: Add device node for qcom,dwc3

[Vivek Gautam]

Adding required device node for couple of DWC3 controllers
present on msm8996 chipset to enable High speed and Super
speed USB support.

Signed-off-by: Vivek Gautam 
---
 .../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi| 24 +
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi   | 34 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi  | 57 ++
 3 files changed, 115 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index b1142c45fdc9..8e379782597a 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -24,4 +24,28 @@
power-source = ; // 1.8V
};
};
+
+   usb3_vbus_det_gpio: pm8996_gpio22 {
+   pinconf {
+   pins = "gpio22";
+   function = PMIC_GPIO_FUNC_NORMAL;
+   input-enable;
+   bias-pull-down;
+   qcom,drive-strength = ;
+   power-source = ; // 1.8V
+   };
+   };
+};
+
+&pmi8994_gpios {
+   usb2_vbus_det_gpio: pmi8996_gpio6 {
+   pinconf {
+   pins = "gpio6";
+   function = PMIC_GPIO_FUNC_NORMAL;
+   input-enable;
+   bias-pull-down;
+   qcom,drive-strength = ;
+   power-source = ; // 1.8V
+   };
+   };
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index a493f797f9f1..271624f567be 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -13,6 +13,7 @@
 
 #include "msm8996.dtsi"
 #include "pm8994.dtsi"
+#include "pmi8994.dtsi"
 #include "apq8096-db820c-pins.dtsi"
 #include "apq8096-db820c-pmic-pins.dtsi"
 #include 
@@ -104,6 +105,39 @@
phy@7412000 {
status = "okay";
};
+
+   usb@6a0 {
+   status = "okay";
+
+   dwc3@6a0 {
+   extcon = <&usb3_id>;
+   dr_mode = "otg";
+   };
+   };
+
+   usb3_id: usb3-id {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&usb3_vbus_det_gpio>;
+   };
+
+   usb@760 {
+   status = "okay";
+
+   dwc3@760 {
+   extcon = <&usb2_id>;
+   dr_mode = "otg";
+   maximum-speed = "high-speed";
+   };
+   };
+
+   usb2_id: usb2-id {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&usb2_vbus_det_gpio>;
+   };
};
 
 
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 670af2b8d244..bfe7b9723247 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -767,6 +767,63 @@
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
};
+
+   usb2: usb@760 {
+   compatible = "qcom,dwc3";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
+   <&gcc GCC_USB20_MASTER_CLK>,
+   <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+   <&gcc GCC_USB20_SLEEP_CLK>,
+   <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+   assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+   assigned-clock-rates = <1920>, <6000>;
+
+   power-domains = <&gcc USB30_GDSC>;
+   status = "disabled";
+
+   dwc3@760 {
+   compatible = "snps,dwc3";
+   reg = <0x760 0xcc00>;
+   interrupts = <0 138 0>;
+   phys = <&hsusb_phy2>;
+   phy-names = "usb2-phy";
+   };
+   };
+
+   usb3: usb@6a0 {
+   compatible = "qc

[PATCH 0/4] arm64: dt: msm8996: Enable support for qmp and qusb2 phy, and USB

[Vivek Gautam]

Adding patches to enable qusb2 and qmp phy controller for PCIe and USB,
and to enable USB 2.0 and 3.0 support on msm8996 chipset.
Enabling the support for apq8096-db820c board.

Patch series dependencies:
1) Glink-rpm device tree support for 8996:
   https://www.spinics.net/lists/linux-arm-msm/msg29046.html
2) Dt binding fix for pipe clock source:
   a. https://patchwork.kernel.org/patch/9870865/
   b. https://patchwork.kernel.org/patch/9870871/
3) pmi8994 gpio support:
   https://lkml.org/lkml/2017/7/28/346

Tested the series on dragonboard db820c target.

Vivek Gautam (4):
  arm64: dts: msm8996: Add device node for qcom qusb2 phy
  arm64: dts: msm8996: Add device node for qcom qmp-phy for usb
  arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie
  arm64: dts: msm8996: Add device node for qcom,dwc3

 .../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi|  24 +++
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi   |  50 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi  | 203 +
 3 files changed, 277 insertions(+)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/4] arm64: dts: msm8996: Add device node for qcom qusb2 phy

[Vivek Gautam]

Adding device node for QUSB2 phy and the required infrastructure
to enable support for the same. This phy is used by dwc3 controller
present on msm8996.

Signed-off-by: Vivek Gautam 
---
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi |  8 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi| 51 
 2 files changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 5366708ee78f..4476e9238150 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -88,6 +88,14 @@
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
+
+   phy@7411000 {
+   status = "okay";
+   };
+
+   phy@7412000 {
+   status = "okay";
+   };
};
 
 
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index d6a30fe81b77..019ec9345dbc 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -621,6 +621,57 @@
   <96000>,
   <82500>;
};
+
+   qfprom@74000 {
+   compatible = "qcom,qfprom";
+   reg = <0x74000 0x8ff>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   qusb2p_hstx_trim: hstx_trim@24e {
+   reg = <0x24e 0x2>;
+   bits = <5 4>;
+   };
+
+   qusb2s_hstx_trim: hstx_trim@24f {
+   reg = <0x24f 0x1>;
+   bits = <1 4>;
+   };
+   };
+
+   hsusb_phy1: phy@7411000 {
+   compatible = "qcom,msm8996-qusb2-phy";
+   reg = <0x7411000 0x180>;
+   #phy-cells = <0>;
+
+   clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+   <&gcc GCC_RX1_USB2_CLKREF_CLK>;
+   clock-names = "cfg_ahb", "ref";
+
+   vdda-pll-supply = <&pm8994_l12>;
+   vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+   resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+   nvmem-cells = <&qusb2p_hstx_trim>;
+   status = "disabled";
+   };
+
+   hsusb_phy2: phy@7412000 {
+   compatible = "qcom,msm8996-qusb2-phy";
+   reg = <0x7412000 0x180>;
+   #phy-cells = <0>;
+
+   clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+   <&gcc GCC_RX2_USB2_CLKREF_CLK>;
+   clock-names = "cfg_ahb", "ref";
+
+   vdda-pll-supply = <&pm8994_l12>;
+   vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+   resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+   nvmem-cells = <&qusb2s_hstx_trim>;
+   status = "disabled";
+   };
};
 
adsp-pil {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 3/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie

[Vivek Gautam]

Add required device node for QMP phy based 3-lane PCIe phy
present on msm8996 chipset to enable support for the same.

Signed-off-by: Vivek Gautam 
---
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi |  4 ++
 arch/arm64/boot/dts/qcom/msm8996.dtsi| 62 
 2 files changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 2bab37594b5d..a493f797f9f1 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -89,6 +89,10 @@
status = "okay";
};
 
+   phy@34000 {
+   status = "okay";
+   };
+
phy@741 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0cdbdf49410..670af2b8d244 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -639,6 +639,68 @@
};
};
 
+   phy@34000 {
+   compatible = "qcom,msm8996-qmp-pcie-phy";
+   reg = <0x34000 0x488>;
+   #clock-cells = <1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+   <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+   <&gcc GCC_PCIE_CLKREF_CLK>;
+   clock-names = "aux", "cfg_ahb", "ref";
+
+   vdda-phy-supply = <&pm8994_l28>;
+   vdda-pll-supply = <&pm8994_l12>;
+
+   resets = <&gcc GCC_PCIE_PHY_BCR>,
+   <&gcc GCC_PCIE_PHY_COM_BCR>,
+   <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+   reset-names = "phy", "common", "cfg";
+   status = "disabled";
+
+   pciephy_0: lane@35000 {
+   reg = <0x035000 0x130>,
+   <0x035200 0x200>,
+   <0x035400 0x1dc>;
+   #phy-cells = <0>;
+
+   clock-output-names = "pcie_0_pipe_clk_src";
+   clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+   clock-names = "pipe0";
+   resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+   reset-names = "lane0";
+   };
+
+   pciephy_1: lane@36000 {
+   reg = <0x036000 0x130>,
+   <0x036200 0x200>,
+   <0x036400 0x1dc>;
+   #phy-cells = <0>;
+
+   clock-output-names = "pcie_1_pipe_clk_src";
+   clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+   clock-names = "pipe1";
+   resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+   reset-names = "lane1";
+   };
+
+   pciephy_2: lane@37000 {
+   reg = <0x037000 0x130>,
+   <0x037200 0x200>,
+   <0x037400 0x1dc>;
+   #phy-cells = <0>;
+
+   clock-output-names = "pcie_2_pipe_clk_src";
+   clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "pipe2";
+   resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+   reset-names = "lane2";
+   };
+   };
+
phy@741 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x741 0x1c4>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for usb

[Vivek Gautam]

Adding required device node for USB3 QMP phy present on
msm8996 chipset to enable support for the same. This phy
provides super speed usb functionality for dwc3 controller
on msm8996.

Signed-off-by: Vivek Gautam 
---
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi |  4 
 arch/arm64/boot/dts/qcom/msm8996.dtsi| 33 
 2 files changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 4476e9238150..2bab37594b5d 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -89,6 +89,10 @@
status = "okay";
};
 
+   phy@741 {
+   status = "okay";
+   };
+
phy@7411000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 019ec9345dbc..c0cdbdf49410 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -639,6 +639,39 @@
};
};
 
+   phy@741 {
+   compatible = "qcom,msm8996-qmp-usb3-phy";
+   reg = <0x741 0x1c4>;
+   #clock-cells = <1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+   <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+   <&gcc GCC_USB3_CLKREF_CLK>;
+   clock-names = "aux", "cfg_ahb", "ref";
+
+   vdda-phy-supply = <&pm8994_l28>;
+   vdda-pll-supply = <&pm8994_l12>;
+
+   resets = <&gcc GCC_USB3_PHY_BCR>,
+   <&gcc GCC_USB3PHY_PHY_BCR>;
+   reset-names = "phy", "common";
+   status = "disabled";
+
+   ssusb_phy_0: lane@7410200 {
+   reg = <0x7410200 0x200>,
+   <0x7410400 0x130>,
+   <0x7410600 0x1a8>;
+   #phy-cells = <0>;
+
+   clock-output-names = "usb3_phy_pipe_clk_src";
+   clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+   clock-names = "pipe0";
+   };
+   };
+
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 2/5] [media]: rockchip/rga: v4l2 m2m support

[Jacob Chen]

Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness

The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the rendering pipeline.
 - copy
 - fast solid color fill
 - rotation
 - flip
 - alpha blending

The code in rga-hw.c is used to configure regs accroding to operations
The code in rga-buf.c is used to create (1-Level)mmu table for RGA

Signed-off-by: Jacob Chen 
---
 drivers/media/platform/Kconfig|  11 +
 drivers/media/platform/Makefile   |   2 +
 drivers/media/platform/rockchip-rga/Makefile  |   3 +
 drivers/media/platform/rockchip-rga/rga-buf.c | 141 
 drivers/media/platform/rockchip-rga/rga-hw.c  | 650 +
 drivers/media/platform/rockchip-rga/rga-hw.h  | 437 
 drivers/media/platform/rockchip-rga/rga.c | 987 ++
 drivers/media/platform/rockchip-rga/rga.h | 110 +++
 8 files changed, 2341 insertions(+)
 create mode 100644 drivers/media/platform/rockchip-rga/Makefile
 create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
 create mode 100644 drivers/media/platform/rockchip-rga/rga.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga.h

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index c9106e1..8199bcf 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -411,6 +411,17 @@ config VIDEO_RENESAS_VSP1
  To compile this driver as a module, choose M here: the module
  will be called vsp1.
 
+config VIDEO_ROCKCHIP_RGA
+   tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
+   depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select VIDEOBUF2_DMA_SG
+   select V4L2_MEM2MEM_DEV
+   default n
+   ---help---
+ This is a v4l2 driver for Rockchip SOC RGA2
+ 2d graphics accelerator.
+
 config VIDEO_TI_VPE
tristate "TI VPE (Video Processing Engine) driver"
depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 349ddf6..3bf096f 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1)  += rcar_fdp1.o
 obj-$(CONFIG_VIDEO_RENESAS_JPU)+= rcar_jpu.o
 obj-$(CONFIG_VIDEO_RENESAS_VSP1)   += vsp1/
 
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)   += rockchip-rga/
+
 obj-y  += omap/
 
 obj-$(CONFIG_VIDEO_AM437X_VPFE)+= am437x/
diff --git a/drivers/media/platform/rockchip-rga/Makefile 
b/drivers/media/platform/rockchip-rga/Makefile
new file mode 100644
index 000..92fe254
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/Makefile
@@ -0,0 +1,3 @@
+rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c 
b/drivers/media/platform/rockchip-rga/rga-buf.c
new file mode 100644
index 000..b4d28e3
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-buf.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rga-hw.h"
+#include "rga.h"
+
+static int
+rga_queue_setup(struct vb2_queue *vq,
+   unsigned int *nbuffers, unsigned int *nplanes,
+   unsigned int sizes[], struct device *alloc_devs[])
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vq);
+   struct rga_frame *f = rga_get_frame(ctx, vq->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   sizes[0] = f->size;
+   *nplanes = 1;
+
+   if (*nbuffers == 0)
+   *nbuffers = 1;
+
+   return 0;
+}
+
+static int rga_buf_prepare(struct vb2_buffer *vb)
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+   struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   vb2_set_plane_payload(vb, 0, f->size);
+
+   return 0;
+}
+
+static void rga_buf_queue(struct vb2_buffer *vb)
+{
+   struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+   st

Re: [PATCH 4.4 66/90] powerpc/numa: Fix percpu allocations to be NUMA aware

[Michal Hocko]

On Fri 28-07-17 15:41:47, Greg KH wrote:
> On Fri, Jul 28, 2017 at 03:53:35PM +0200, Michal Hocko wrote:
> > JFYI. We have encountered a regression after applying this patch on a
> > large ppc machine. While the patch is the right thing to do it doesn't
> > work well with the current vmalloc area size on ppc and large machines
> > where NUMA nodes are very far from each other. Just for the reference
> > the boot fails on such a machine with bunch of warning preceeding it.
> > See http://lkml.kernel.org/r/20170724134240.gl25...@dhcp22.suse.cz
> > 
> > It seems the right thing to do is to enlarge the vmalloc space on ppc
> > but this is not the case in the upstream kernel yet AFAIK. It is also
> > questionable whether that is a stable material but I will decision on
> > you here.
> > 
> > We have reverted this patch from our 4.4 based kernel.
> 
> But all is fine on newer kernels?  That is odd.

Newer kernels do not have enlarged vmalloc space yet AFAIK so they won't
work properly eiter. This bug is quite rare though because you need a
specific HW configuration to trigger the issue - namely NUMA nodes have
to be far away from each other in the physical memory space.

> I'll be glad to drop it, but should it be dropped from all stable trees?

Yes from all stable backports.
-- 
Michal Hocko
SUSE Labs

Re: [PATCH] mmc: sdhci-of-at91: force card detect value for non removable devices

[Adrian Hunter]

On 26/07/17 17:02, Ludovic Desroches wrote:
> When the device is non removable, the card detect signal is often use

use -> used

> for another purpose i.e. muxed to another SoC peripheral or used as a
> GPIO. It could lead to wrong behaviors depending the defaut value of

defaut -> default

> this signal if not muxed to the SDHCI controller.
> 
> Fixes: bb5f8ea4d514 ("mmc: sdhci-of-at91: introduce driver for the Atmel 
> SDMMC")
> Signed-off-by: Ludovic Desroches 

Apart from spelling

Acked-by: Adrian Hunter 

> ---
>  drivers/mmc/host/sdhci-of-at91.c | 36 +++-
>  1 file changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-at91.c 
> b/drivers/mmc/host/sdhci-of-at91.c
> index 88e9b5f35a62..6a389f35396e 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -31,6 +31,7 @@
>  
>  #define SDMMC_MC1R   0x204
>  #define  SDMMC_MC1R_DDR  BIT(3)
> +#define  SDMMC_MC1R_FCD  BIT(7)
>  #define SDMMC_CACR   0x230
>  #define  SDMMC_CACR_CAPWREN  BIT(0)
>  #define  SDMMC_CACR_KEY  (0x46 << 8)
> @@ -44,6 +45,15 @@ struct sdhci_at91_priv {
>   bool restore_needed;
>  };
>  
> +static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
> +{
> + u8 mc1r;
> +
> + mc1r = readb(host->ioaddr + SDMMC_MC1R);
> + mc1r |= SDMMC_MC1R_FCD;
> + writeb(mc1r, host->ioaddr + SDMMC_MC1R);
> +}
> +
>  static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
>  {
>   u16 clk;
> @@ -111,10 +121,18 @@ void sdhci_at91_set_uhs_signaling(struct sdhci_host 
> *host, unsigned int timing)
>   sdhci_set_uhs_signaling(host, timing);
>  }
>  
> +static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
> +{
> + sdhci_reset(host, mask);
> +
> + if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
> + sdhci_at91_set_force_card_detect(host);
> +}
> +
>  static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
>   .set_clock  = sdhci_at91_set_clock,
>   .set_bus_width  = sdhci_set_bus_width,
> - .reset  = sdhci_reset,
> + .reset  = sdhci_at91_reset,
>   .set_uhs_signaling  = sdhci_at91_set_uhs_signaling,
>   .set_power  = sdhci_at91_set_power,
>  };
> @@ -369,6 +387,22 @@ static int sdhci_at91_probe(struct platform_device *pdev)
>   host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
>   }
>  
> + /*
> +  * If the device attached to the MMC bus is not removable, it is safer
> +  * to set the Force Card Detect bit. People often don't connect the
> +  * card detect signal and use this pin for another purpose. If the card
> +  * detect pin is not muxed to SDHCI controller, a default value is
> +  * used. This value can be different from a SoC revision to another
> +  * one. Problems come when this default value is not card present. To
> +  * avoid this case, if the device is non removable then the card
> +  * detection procedure using the SDMCC_CD signal is bypassed.
> +  * This bit is resetted when a software reset for all command is

resetted -> reset

> +  * performed so we need to implement our own reset function to set back
> +  * this bit.
> +  */
> + if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
> + sdhci_at91_set_force_card_detect(host);
> +
>   pm_runtime_put_autosuspend(&pdev->dev);
>  
>   return 0;
> 

Re: [PATCH] staging: ccree: Fix format/argument mismatches

[Gilad Ben-Yossef]

On Sun, Jul 30, 2017 at 7:45 PM, Joe Perches  wrote:
> By default, debug logging is disabled by CC_DEBUG not being defined.
>
> Convert SSI_LOG_DEBUG to use no_printk instead of an empty define
> to validate formats and arguments.
>
> Fix fallout.
>
> Miscellanea:
>
> o One of the conversions now uses %pR instead of multiple uses of %pad

This looks great (I didn't know about no_printk) but does not seem to
apply on top of
staging-next.


Thanks,
Gilad

>
> Signed-off-by: Joe Perches 
> ---
>  drivers/staging/ccree/ssi_aead.c|  8 
>  drivers/staging/ccree/ssi_buffer_mgr.c  | 29 +
>  drivers/staging/ccree/ssi_cipher.c  | 10 +-
>  drivers/staging/ccree/ssi_driver.c  |  5 ++---
>  drivers/staging/ccree/ssi_driver.h  |  2 +-
>  drivers/staging/ccree/ssi_hash.c| 32 
>  drivers/staging/ccree/ssi_request_mgr.c |  6 +++---
>  7 files changed, 44 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/staging/ccree/ssi_aead.c 
> b/drivers/staging/ccree/ssi_aead.c
> index ea29b8a1a71d..9376bf8b8c61 100644
> --- a/drivers/staging/ccree/ssi_aead.c
> +++ b/drivers/staging/ccree/ssi_aead.c
> @@ -103,7 +103,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
> if (ctx->enckey) {
> dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, 
> ctx->enckey_dma_addr);
> SSI_LOG_DEBUG("Freed enckey DMA buffer 
> enckey_dma_addr=%pad\n",
> - ctx->enckey_dma_addr);
> + &ctx->enckey_dma_addr);
> ctx->enckey_dma_addr = 0;
> ctx->enckey = NULL;
> }
> @@ -117,7 +117,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
>   xcbc->xcbc_keys_dma_addr);
> }
> SSI_LOG_DEBUG("Freed xcbc_keys DMA buffer 
> xcbc_keys_dma_addr=%pad\n",
> - xcbc->xcbc_keys_dma_addr);
> + &xcbc->xcbc_keys_dma_addr);
> xcbc->xcbc_keys_dma_addr = 0;
> xcbc->xcbc_keys = NULL;
> } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
> @@ -128,7 +128,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
>   hmac->ipad_opad,
>   hmac->ipad_opad_dma_addr);
> SSI_LOG_DEBUG("Freed ipad_opad DMA buffer 
> ipad_opad_dma_addr=%pad\n",
> - hmac->ipad_opad_dma_addr);
> + &hmac->ipad_opad_dma_addr);
> hmac->ipad_opad_dma_addr = 0;
> hmac->ipad_opad = NULL;
> }
> @@ -137,7 +137,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
>   hmac->padded_authkey,
>   hmac->padded_authkey_dma_addr);
> SSI_LOG_DEBUG("Freed padded_authkey DMA buffer 
> padded_authkey_dma_addr=%pad\n",
> - hmac->padded_authkey_dma_addr);
> + &hmac->padded_authkey_dma_addr);
> hmac->padded_authkey_dma_addr = 0;
> hmac->padded_authkey = NULL;
> }
> diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
> b/drivers/staging/ccree/ssi_buffer_mgr.c
> index 6579a54f9dc4..e13184d1d165 100644
> --- a/drivers/staging/ccree/ssi_buffer_mgr.c
> +++ b/drivers/staging/ccree/ssi_buffer_mgr.c
> @@ -14,6 +14,7 @@
>   * along with this program; if not, see .
>   */
>
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -33,14 +34,10 @@
>  #include "ssi_hash.h"
>  #include "ssi_aead.h"
>
> -#ifdef CC_DEBUG
>  #define GET_DMA_BUFFER_TYPE(buff_type) ( \
> ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \
> ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \
> ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID")
> -#else
> -#define GET_DMA_BUFFER_TYPE(buff_type)
> -#endif
>
>  enum dma_buffer_type {
> DMA_NULL_TYPE = -1,
> @@ -262,7 +259,7 @@ static int ssi_buffer_mgr_generate_mlli(
> SSI_LOG_DEBUG("MLLI params: "
>  "virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
>mlli_params->mlli_virt_addr,
> -  mlli_params->mlli_dma_addr,
> +  &mlli_params->mlli_dma_addr,
>mlli_params->mlli_len);
>
>  build_mlli_exit:
> @@ -278,7 +275,7 @@ static inline void ssi_buffer_mgr_add_buffer_entry(
>
> SSI_LOG_DEBUG("index=%u single_buff=%pad "
>  "buffer_len=0x%08X is_last=%d\n",
> -index, buffer_dma, buffer_len, is_last_entry);
> +index, &buffer_dma, buffer_len, is_last_entry);
> sgl_data->nents[index] = 1;
>  

[PATCH v6 0/7] Add support for IPQ8074 PCIe phy and controller

[Varadarajan Narayanan]

v6:
  Added 'Reviewed-by: Vivek Gautam ' and fixed
  white space issues as mentioned by Vivek.
phy: qcom-qmp: Fix phy pipe clock name
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074

v5:
  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Renamed phy_phy clock as common clock

  phy: qcom-qmp: Fix phy pipe clock name
Moved the DT get into the registering function

  phy: qcom-qmp: Add support for IPQ8074
Place the IPQ8074 related structs similar to existing SoC.
Renamed phy_phy clock as common clock
v4:
  phy: qcom-qmp: Fix phy pipe clock name
Based on Vivek's comments, return failure only for
PCI/USB type of phys.
Removed Ack.

  phy: qcom-qmp: Handle unavailable registers
Removed this patch.
Incorrectly used a block of code that is not applicable
to IPQ8074, hence had to avoid an "unavailable" register.
Since that is addressed using 'has_phy_com_ctrl' this
patch is not needed.

  phy: qcom-qmp: Add support for IPQ8074
Set 'has_phy_com_ctrl' to false
Remove ipq8074_pciephy_regs_layout

v3:
  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incoporate Stan's feedback:-
 - Add SoC Wrapper and Synopsys Core IP versions

v2:
  dt-bindings: phy: qmp: Add output-clock-names
Added Rob H's Ack

  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Removed example
Added IPQ8074 specific details

  phy: qcom-qmp: Fix phy pipe clock name
Added Vivek's Ack

  phy: qcom-qmp: Handle unavailable registers
No changes

  phy: qcom-qmp: Add support for IPQ8074
No changes

  PCI: dwc: qcom: Use block IP version for operations
Added new patch to use block IP version instead of v1, v2...

  dt-bindings: pci: qcom: Add support for IPQ8074
Removed example
Added IPQ8074 specific details

  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incorporated Bjorn's feedback:-
 - Removed reset names, helper function to assert/deassert, helper
   function to R/M/W register.
 - Renamed sys_noc clock as iface clock
 - Added deinit if phy power on fails

v1:
Add definitions required to enable QMP phy support for IPQ8074.

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.

Varadarajan Narayanan (7):
  dt-bindings: phy: qmp: Add output-clock-names
  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
  phy: qcom-qmp: Fix phy pipe clock name
  phy: qcom-qmp: Add support for IPQ8074
  PCI: dwc: qcom: Use block IP version for operations
  dt-bindings: pci: qcom: Add support for IPQ8074
  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

 .../devicetree/bindings/pci/qcom,pcie.txt  |  23 ++
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |  11 +
 drivers/pci/dwc/pcie-qcom.c| 378 +
 drivers/phy/qualcomm/phy-qcom-qmp.c| 147 +++-
 4 files changed, 485 insertions(+), 74 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v6 3/7] phy: qcom-qmp: Fix phy pipe clock name

[Varadarajan Narayanan]

Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.

Reviewed-by: Vivek Gautam 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 23 +++
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..3dd7891 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -925,29 +925,28 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
  *clk  |   +---+   |   +-+
  * +---+
  */
-static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 {
-   char name[24];
struct clk_fixed_rate *fixed;
struct clk_init_data init = { };
+   int ret;
 
-   switch (qmp->cfg->type) {
-   case PHY_TYPE_USB3:
-   snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src");
-   break;
-   case PHY_TYPE_PCIE:
-   snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id);
-   break;
-   default:
+   if ((qmp->cfg->type != PHY_TYPE_USB3) &&
+   (qmp->cfg->type != PHY_TYPE_PCIE)) {
/* not all phys register pipe clocks, so return success */
return 0;
}
 
+   ret = of_property_read_string(np, "clock-output-names", &init.name);
+   if (ret) {
+   dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
+   return ret;
+   }
+
fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return -ENOMEM;
 
-   init.name = name;
init.ops = &clk_fixed_rate_ops;
 
/* controllers using QMP phys use 125MHz pipe clock interface */
@@ -1122,7 +1121,7 @@ static int qcom_qmp_phy_probe(struct platform_device 
*pdev)
 * Register the pipe clock provided by phy.
 * See function description to see details of this pipe clock.
 */
-   ret = phy_pipe_clk_register(qmp, id);
+   ret = phy_pipe_clk_register(qmp, child);
if (ret) {
dev_err(qmp->dev,
"failed to register pipe clock source\n");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v6 4/7] phy: qcom-qmp: Add support for IPQ8074

[Varadarajan Narayanan]

Add definitions required to enable QMP phy support for IPQ8074.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 124 
 1 file changed, 124 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 3dd7891..0c6cb88 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -59,6 +59,7 @@
 #define QSERDES_COM_PLL_RCTRL_MODE10x088
 #define QSERDES_COM_PLL_CCTRL_MODE00x090
 #define QSERDES_COM_PLL_CCTRL_MODE10x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM0x0a8
 #define QSERDES_COM_SYSCLK_EN_SEL  0x0ac
 #define QSERDES_COM_RESETSM_CNTRL  0x0b4
 #define QSERDES_COM_RESTRIM_CTRL   0x0bc
@@ -143,6 +144,11 @@
 #define QPHY_LOCK_DETECT_CONFIG3   0x88
 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK   0xa0
 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB  0x1A8
+#define QPHY_OSC_DTCT_ACTIONS  0x1AC
+#define QPHY_RX_SIGDET_LVL 0x1D8
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB   0x1DC
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB   0x1E0
 
 /* QPHY_SW_RESET bit */
 #define SW_RESET   BIT(0)
@@ -382,6 +388,85 @@ enum qphy_reg_layout {
QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 };
 
+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+   QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+   QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+   QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAI

[PATCH RFC] vfio: Implement new Ioctl VFIO_IOMMU_GET_DIRTY_BITMAP

[Yulei Zhang]

This patch is to implement the new ioctl VFIO_IOMMU_GET_DIRTY_BITMAP
to fulfill the requirement for vfio-mdev device live migration, which
need copy the memory that has been pinned in iommu container to the
target VM for mdev device status restore.

Signed-off-by: Yulei Zhang 
---
 drivers/vfio/vfio_iommu_type1.c | 38 ++
 include/uapi/linux/vfio.h   | 14 ++
 2 files changed, 52 insertions(+)

diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 8549cb1..fab9e26 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -41,6 +41,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DRIVER_VERSION  "0.2"
 #define DRIVER_AUTHOR   "Alex Williamson "
@@ -1526,6 +1527,23 @@ static int vfio_domains_have_iommu_cache(struct 
vfio_iommu *iommu)
return ret;
 }
 
+static void vfio_dma_update_dirty_bitmap(struct vfio_iommu *iommu, u64 
start_addr,
+ u64 npage, void *bitmap)
+{
+   u64 iova = start_addr;
+   struct vfio_dma *dma;
+   int i;
+
+   for (i = 0; i < npage; i++) {
+   dma = vfio_find_dma(iommu, iova, PAGE_SIZE);
+   if (dma)
+   if (vfio_find_vpfn(dma, iova))
+   set_bit(i, bitmap);
+
+   iova += PAGE_SIZE;
+   }
+}
+
 static long vfio_iommu_type1_ioctl(void *iommu_data,
   unsigned int cmd, unsigned long arg)
 {
@@ -1596,6 +1614,26 @@ static long vfio_iommu_type1_ioctl(void *iommu_data,
 
return copy_to_user((void __user *)arg, &unmap, minsz) ?
-EFAULT : 0;
+   } else if (cmd == VFIO_IOMMU_GET_DIRTY_BITMAP) {
+   struct vfio_iommu_get_dirty_bitmap d;
+   unsigned long bitmap_sz;
+   unsigned *bitmap;
+
+   minsz = offsetofend(struct vfio_iommu_get_dirty_bitmap, 
page_nr);
+
+   if (copy_from_user(&d, (void __user *)arg, minsz))
+   return -EFAULT;
+
+   bitmap_sz = (BITS_TO_LONGS(d.page_nr) + 1) * sizeof(unsigned 
long);
+   bitmap = vzalloc(bitmap_sz);
+   vfio_dma_update_dirty_bitmap(iommu, d.start_addr, d.page_nr, 
bitmap);
+
+   if (copy_to_user((void __user*)arg + minsz, bitmap, bitmap_sz)) 
{
+   vfree(bitmap);
+   return -EFAULT;
+   }
+   vfree(bitmap);
+   return 0;
}
 
return -ENOTTY;
diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index 8424afb..ecf5c53 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -571,6 +571,20 @@ struct vfio_iommu_type1_dma_unmap {
 #define VFIO_IOMMU_ENABLE  _IO(VFIO_TYPE, VFIO_BASE + 15)
 #define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16)
 
+/**
+ * VFIO_IOMMU_GET_DIRTY_BITMAP - _IOW(VFIO_TYPE, VFIO_BASE + 17,
+ * struct vfio_iommu_get_dirty_bitmap)
+ *
+ * Return: 0 on success, -errno on failure.
+ */
+struct vfio_iommu_get_dirty_bitmap{
+   __u64  start_addr;
+   __u64  page_nr;
+   __u8   dirty_bitmap[];
+};
+
+#define VFIO_IOMMU_GET_DIRTY_BITMAP _IO(VFIO_TYPE, VFIO_BASE + 17)
+
 /*  Additional API for SPAPR TCE (Server POWERPC) IOMMU  */
 
 /*
-- 
2.7.4

[PATCH v6 5/7] PCI: dwc: qcom: Use block IP version for operations

[Varadarajan Narayanan]

Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.

Signed-off-by: Varadarajan Narayanan 
---
 drivers/pci/dwc/pcie-qcom.c | 133 +++-
 1 file changed, 71 insertions(+), 62 deletions(-)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index d15657d..6525f2f 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -61,7 +61,7 @@
 
 #define PERST_DELAY_US 1000
 
-struct qcom_pcie_resources_v0 {
+struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
@@ -75,7 +75,7 @@ struct qcom_pcie_resources_v0 {
struct regulator *vdda_refclk;
 };
 
-struct qcom_pcie_resources_v1 {
+struct qcom_pcie_resources_1_0_0 {
struct clk *iface;
struct clk *aux;
struct clk *master_bus;
@@ -84,7 +84,7 @@ struct qcom_pcie_resources_v1 {
struct regulator *vdda;
 };
 
-struct qcom_pcie_resources_v2 {
+struct qcom_pcie_resources_2_3_2 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -92,7 +92,7 @@ struct qcom_pcie_resources_v2 {
struct clk *pipe_clk;
 };
 
-struct qcom_pcie_resources_v3 {
+struct qcom_pcie_resources_2_4_0 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -111,10 +111,10 @@ struct qcom_pcie_resources_v3 {
 };
 
 union qcom_pcie_resources {
-   struct qcom_pcie_resources_v0 v0;
-   struct qcom_pcie_resources_v1 v1;
-   struct qcom_pcie_resources_v2 v2;
-   struct qcom_pcie_resources_v3 v3;
+   struct qcom_pcie_resources_1_0_0 v1_0_0;
+   struct qcom_pcie_resources_2_1_0 v2_1_0;
+   struct qcom_pcie_resources_2_3_2 v2_3_2;
+   struct qcom_pcie_resources_2_4_0 v2_4_0;
 };
 
 struct qcom_pcie;
@@ -172,7 +172,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
return dw_pcie_wait_for_link(pci);
 }
 
-static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
+static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
 {
u32 val;
 
@@ -182,9 +182,9 @@ static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie 
*pcie)
writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 }
 
-static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
 
@@ -232,9 +232,9 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie 
*pcie)
return PTR_ERR_OR_ZERO(res->phy_reset);
 }
 
-static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
@@ -249,9 +249,9 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
regulator_disable(res->vdda_refclk);
 }
 
-static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
u32 val;
@@ -367,9 +367,9 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
return ret;
 }
 
-static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
 
@@ -397,9 +397,9 @@ static int qcom_pcie_get_resources_v1(struct qcom_pcie 
*pcie)
return PTR_ERR_OR_ZERO(res->core);
 }
 
-static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 
reset_control_assert(res->core);
clk_disable_unprepare(res->slave_bus);
@@ -409,9 +409,9 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
regulator_disable(res->vdda);
 }
 
-static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struc

[PATCH v6 1/7] dt-bindings: phy: qmp: Add output-clock-names

[Varadarajan Narayanan]

The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.

Acked-by: Rob Herring 
Signed-off-by: Varadarajan Narayanan 
---
 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index e11c563..5d7a51f 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -60,6 +60,8 @@ Required properties for child node:
   one for each entry in clock-names.
  - clock-names: Must contain following for pcie and usb qmp phys:
 "pipe" for pipe clock specific to each lane.
+ - clock-output-names: Name of the phy clock that will be the parent for
+  the above pipe clock.
 
  - resets: a list of phandles and reset controller specifier pairs,
   one for each entry in reset-names.
@@ -96,6 +98,7 @@ Example:
 
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+   clock-output-names = "pcie_0_pipe_clk_src";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

linux-next: Tree for Jul 31

[Stephen Rothwell]

Hi all,

Changes since 20170728:

The rdma tree gained a build failure so I used the version from
next-20170728.

The drm tree gained a conflict against Linus' tree.

The rcu tree gained a conflict against the tip tree.

Non-merge commits (relative to Linus' tree): 3288
 3279 files changed, 115355 insertions(+), 54071 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig (with
CONFIG_BUILD_DOCSRC=n) for x86_64, a multi_v7_defconfig for arm and a
native build of tools/perf. After the final fixups (if any), I do an
x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And
finally, a simple boot test of the powerpc pseries_le_defconfig kernel
in qemu.

Below is a summary of the state of the merge.

I am currently merging 267 trees (counting Linus' and 41 trees of bug
fix patches pending for the current merge release).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (16f73eb02d7e Linux 4.13-rc3)
Merging fixes/master (b4b8cbf679c4 Cavium CNN55XX: fix broken default Kconfig 
entry)
Merging kbuild-current/fixes (ad8181060788 kconfig: fix sparse warnings in 
nconfig)
Merging arc-current/for-curr (37f1db0e85ff ARC: [plat-axs10x]: prepare dts 
files for enabling PAE40 on axs103)
Merging arm-current/fixes (ce184a0dee92 ARM: 8687/1: signal: Fix unparseable 
iwmmxt_sigframe in uc_regspace[])
Merging m68k-current/for-linus (204a2be30a7a m68k: Remove ptrace_signal_deliver)
Merging metag-fixes/fixes (b884a190afce metag/usercopy: Add missing fixups)
Merging powerpc-fixes/fixes (c9c98bc5cc2a powerpc/mm: Fix pmd/pte_devmap() on 
non-leaf entries)
Merging sparc/master (8cd3ec51c0c3 sbus: Convert to using %pOF instead of 
full_name)
Merging fscrypt-current/for-stable (42d97eb0ade3 fscrypt: fix renaming and 
linking special files)
Merging net/master (9975a54b3c9e bpf: fix bpf_prog_get_info_by_fd to dump 
correct xlated_prog_len)
Merging ipsec/master (e6194923237f esp: Fix memleaks on error paths.)
Merging netfilter/master (f7fb77fc1235 netfilter: nft_compat: check extension 
hook mask only if set)
Merging ipvs/master (3c5ab3f395d6 ipvs: SNAT packet replies only for NATed 
connections)
Merging wireless-drivers/master (5f5d03143de5 brcmfmac: fix memleak due to 
calling brcmf_sdiod_sgtable_alloc() twice)
Merging mac80211/master (d7f13f745036 cfg80211: Validate frequencies nested in 
NL80211_ATTR_SCAN_FREQUENCIES)
Merging sound-current/for-linus (ba92b1142879 ALSA: hda - Add mute led support 
for HP ProBook 440 G4)
Merging pci-current/for-linus (34d5ac2af644 PCI: rockchip: Check for 
pci_scan_root_bus_bridge() failure correctly)
Merging driver-core.current/driver-core-linus (5771a8c08880 Linux v4.13-rc1)
Merging tty.current/tty-linus (37ef38f3f838 tty: pl011: fix initialization 
order of QDF2400 E44)
Merging usb.current/usb-linus (45d73860530a usb: musb: fix tx fifo flush 
handling again)
Merging usb-gadget-fixes/fixes (520eccdfe187 Linux 4.13-rc2)
Merging usb-serial-fixes/usb-linus (9585e340db9f USB: serial: cp210x: add 
support for Qivicon USB ZigBee dongle)
Merging usb-chipidea-fixes/ci-for-usb-stable (cbb22ebcfb99 usb: chipidea: core: 
check before accessing ci_role in ci_role_show)
Merging phy/fixes (5771a8c08880 Linux v4.13-rc1)
Merging staging.current/staging-linus (cef988642cda staging: comedi: 
comedi_fops: do not call blocking ops when !TASK_RUNNING)
Merging char-misc.current/char-misc-linus (520eccdfe187 Linux 4.13-rc2)
Merging input-current/for-linus (293b915fd9be Input: trackpoint - assume 3 
buttons when buttons detection fails)
Merging crypto-current/master (41cdf7a45389 crypto: authencesn - Fix 
digest_null crash)
Merging ide/master (921edf312a6a ide: avoid warning for timings calculation)
Merging vfio-fixes/for-linus (bb67b496c338 in

[PATCH v6 7/7] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

[Varadarajan Narayanan]

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.

The core init is the similar to the existing SoC, however the
clocks and reset lines differ.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/pci/dwc/pcie-qcom.c | 245 
 1 file changed, 245 insertions(+)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 6525f2f..b2ea953 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -37,6 +37,20 @@
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL   0x00
+#define MST_WAKEUP_EN  BIT(13)
+#define SLV_WAKEUP_EN  BIT(12)
+#define MSTR_ACLK_CGC_DIS  BIT(10)
+#define SLV_ACLK_CGC_DIS   BIT(9)
+#define CORE_CLK_CGC_DIS   BIT(6)
+#define AUX_PWR_DETBIT(4)
+#define L23_CLK_RMV_DISBIT(2)
+#define L1_CLK_RMV_DIS BIT(1)
+
+#define PCIE20_COMMAND_STATUS  0x04
+#define CMD_BME_VAL0x4
+#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
+#define PCIE_CAP_CPL_TIMEOUT_DISABLE   0x10
+
 #define PCIE20_PARF_PHY_CTRL   0x40
 #define PCIE20_PARF_PHY_REFCLK 0x4C
 #define PCIE20_PARF_DBI_BASE_ADDR  0x168
@@ -58,9 +72,22 @@
 #define CFG_BRIDGE_SB_INIT BIT(0)
 
 #define PCIE20_CAP 0x70
+#define PCIE20_CAP_LINK_CAPABILITIES   (PCIE20_CAP + 0xC)
+#define PCIE20_CAP_LINK_1  (PCIE20_CAP + 0x14)
+#define PCIE_CAP_LINK1_VAL 0x2fd7f
+
+#define PCIE20_PARF_Q2A_FLUSH  0x1AC
+
+#define PCIE20_MISC_CONTROL_1_REG  0x8BC
+#define DBI_RO_WR_EN   1
 
 #define PERST_DELAY_US 1000
 
+#define AXI_CLK_RATE   2
+
+#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
+#define SLV_ADDR_SPACE_SZ   0x1000
+
 struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
@@ -110,11 +137,21 @@ struct qcom_pcie_resources_2_4_0 {
struct reset_control *phy_ahb_reset;
 };
 
+struct qcom_pcie_resources_2_3_3 {
+   struct clk *iface;
+   struct clk *axi_m_clk;
+   struct clk *axi_s_clk;
+   struct clk *ahb_clk;
+   struct clk *aux_clk;
+   struct reset_control *rst[7];
+};
+
 union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
struct qcom_pcie_resources_2_3_2 v2_3_2;
struct qcom_pcie_resources_2_4_0 v2_4_0;
+   struct qcom_pcie_resources_2_3_3 v2_3_3;
 };
 
 struct qcom_pcie;
@@ -884,6 +921,206 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
return ret;
 }
 
+static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+   struct dw_pcie *pci = pcie->pci;
+   struct device *dev = pci->dev;
+   int i;
+   const char *rst_names[] = {
+   "axi_m", "axi_s", "pipe",
+   "axi_m_sticky", "sticky",
+   "ahb", "sleep",
+   };
+
+   res->iface = devm_clk_get(dev, "iface");
+   if (IS_ERR(res->iface))
+   return PTR_ERR(res->iface);
+
+   res->axi_m_clk = devm_clk_get(dev, "axi_m");
+   if (IS_ERR(res->axi_m_clk))
+   return PTR_ERR(res->axi_m_clk);
+
+   res->axi_s_clk = devm_clk_get(dev, "axi_s");
+   if (IS_ERR(res->axi_s_clk))
+   return PTR_ERR(res->axi_s_clk);
+
+   res->ahb_clk = devm_clk_get(dev, "ahb");
+   if (IS_ERR(res->ahb_clk))
+   return PTR_ERR(res->ahb_clk);
+
+   res->aux_clk = devm_clk_get(dev, "aux");
+   if (IS_ERR(res->aux_clk))
+   return PTR_ERR(res->aux_clk);
+
+   for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
+   res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
+   if (IS_ERR(res->rst[i]))
+   return PTR_ERR(res->rst[i]);
+   }
+
+   return 0;
+}
+
+static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+
+   clk_disable_unprepare(res->iface);
+   clk_disable_unprepare(res->axi_m_clk);
+   clk_disable_unprepare(res->axi_s_clk);
+   clk_disable_unprepare(res->ahb_clk);
+   clk_disable_unprepare(res->aux_clk);
+}
+
+static int qcom_pcie_enable_resources_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom

[PATCH v6 6/7] dt-bindings: pci: qcom: Add support for IPQ8074

[Varadarajan Narayanan]

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.

Signed-off-by: Varadarajan Narayanan 
---
 .../devicetree/bindings/pci/qcom,pcie.txt  | 23 ++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt 
b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 9d418b7..b3e36ef 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+   - "qcom,pcie-ipq8074" for ipq8074
 
 - reg:
Usage: required
@@ -105,6 +106,16 @@
- "bus_master"  Master AXI clock
- "bus_slave"   Slave AXI clock
 
+- clock-names:
+   Usage: required for ipq8074
+   Value type: 
+   Definition: Should contain the following entries
+   - "iface"   PCIe to SysNOC BIU clock
+   - "axi_m"   AXI Master clock
+   - "axi_s"   AXI Slave clock
+   - "ahb" AHB clock
+   - "aux" Auxiliary clock
+
 - resets:
Usage: required
Value type: 
@@ -144,6 +155,18 @@
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
 
+- reset-names:
+   Usage: required for ipq8074
+   Value type: 
+   Definition: Should contain the following entries
+   - "pipe"PIPE reset
+   - "sleep"   Sleep reset
+   - "sticky"  Core Sticky reset
+   - "axi_m"   AXI Master reset
+   - "axi_s"   AXI Slave reset
+   - "ahb" AHB Reset
+   - "axi_m_sticky"AXI Master Sticky reset
+
 - power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v6 2/7] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074

[Varadarajan Narayanan]

IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.

Reviewed-by: Vivek Gautam 
Signed-off-by: Varadarajan Narayanan 
---
 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d7a51f..802af1b 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
 
 Required properties:
  - compatible: compatible list, contains:
+  "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
   "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
   "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
 
@@ -38,6 +39,8 @@ Required properties:
 "phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
 "phy", "common".
+   For "qcom,ipq8074-qmp-pcie-phy" must contain:
+"phy", "common".
 
  - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
  - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
  - clock-output-names: Name of the phy clock that will be the parent for
   the above pipe clock.
 
+   For "qcom,ipq8074-qmp-pcie-phy":
+   - "pcie20_phy0_pipe_clk"Pipe Clock parent
+   (or)
+ "pcie20_phy1_pipe_clk"
+
  - resets: a list of phandles and reset controller specifier pairs,
   one for each entry in reset-names.
  - reset-names: Must contain following for pcie qmp phys:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 5/5] ARC: DTS: Add device-tree for Anarion-based development board

[Vineet Gupta]

On 07/29/2017 03:37 AM, Alexandru Gagniuc wrote:

Signed-off-by: Alexandru Gagniuc 
---
  arch/arc/boot/dts/adaptrum_anarion.dtsi | 107 
  arch/arc/boot/dts/adaptrum_anarion_fpga.dts |  49 +
  2 files changed, 156 insertions(+)
  create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
  create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts


So you really need to upstream the fpga dts - if this just for initial bringup and 
you will eventually switch to silicon.
The reason I say is every additional file is a maintenance burden so better to 
avoid things which are only temporary.

But if you plan to support this config in long run I'm fine !

Looking further it seems first one is a "common" include style dts while fpga is 
for actual platform and the SoC one will follow once you get it running ?




diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi 
b/arch/arc/boot/dts/adaptrum_anarion.dtsi
new file mode 100644
index 000..f50958f
--- /dev/null
+++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc  for Adaptrum, Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
+
+#include "skeleton.dtsi"


Perhaps put a one liner that this is based on SNPS ARC700 cpu !


+
+/ {
+   compatible = "adaptrum,anarion";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   soc {
+   compatible = "simple-bus";
+   device_type = "soc";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   interrupt-parent = <&core_intc>;
+
+   core_intc: interrupt-controller {
+   compatible = "snps,arc700-intc";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   };
+
+   uart0: serial@f2202100 {
+   compatible = "ns16550";
+   reg = <0xf2202100 0x20>;
+   interrupts = <8>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clock-frequency = <19200>;
+   status = "disabled";
+   };
+
+   uart1: serial@f2202200 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0xf2202200 0x20>;
+   interrupts = <8>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clock-frequency = <19200>;
+   status = "disabled";
+   };
+
+   uart2: serial@f2202300 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0xf2202300 0x20>;
+   interrupts = <8>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clock-frequency = <19200>;
+   status = "disabled";
+   };
+
+   uart3: serial@f2202400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0xf2202400 0x20>;
+   interrupts = <8>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clock-frequency = <19200>;
+   status = "disabled";
+   };
+
+   qspi: qspi@f200f000 {
+   compatible = "adaptrum,anarion-qspi";
+   reg = <0xf200f000 0x1000>,
+ <0x2000 0x0800>;
+
+   interrupts = <10>;
+   status = "disabled";
+   };
+
+   gmac0: ethernet@f201 {
+   compatible = "snps,dwmac";
+   reg = <0xf201 0x4000>;
+
+   interrupt-parent = <&core_intc>;
+   interrupts = <20>;
+   interrupt-names = "macirq";
+
+   clocks = <&core_clk>;
+   clock-names = "stmmaceth";
+
+   snps,pbl = <32>;
+   status = "disabled";
+   };
+
+   gmac1: ethernet@f2014000 {
+   compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+   reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+   interrupt-parent = <&core_intc>;
+   interrupts = <21>;
+   interrupt-names = "macirq";
+
+   clocks = <&core_clk>;
+   clock-names = "stmmaceth";
+
+   snps,pbl = <32>;
+   status = "disabled";
+   };
+   };
+};
diff --git a/arch/arc/boot/dts/adaptrum_anarion_fpga.dts 
b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
new file mode 100644

Re: [PATCH v2 2/2] userfaultfd: selftest: Add tests for UFFD_FEATURE_SIGBUS feature

[Prakash Sangappa]

On 7/30/17 12:07 AM, Mike Rapoport wrote:

On Thu, Jul 27, 2017 at 10:18:40PM -0400, Prakash Sangappa wrote:

This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
accessing monitored area after signal delivery.

This patch also fixes a bug in uffd_poll_thread() where 'uffd'
is leaked.

Signed-off-by: Prakash Sangappa 
---
Change log

v2:
   - Added comments to explain the tests.
   - Fixed test to fail immediately if signal repeats.
   - Addressed other review comments.

v1: https://lkml.org/lkml/2017/7/26/101
---

Overall looks good to me, just small nitpick below.

[...]

for (nr = 0; nr < split_nr_pages; nr++) {
+   if (signal_test) {
+   if (sigsetjmp(*sigbuf, 1) != 0) {
+   if (nr == lastnr) {
+   sig_repeats++;

You can simply 'return 1' here, then sig_repeats variable can be dropped
and the return statement for signal_test can be simplified.


Ok, sent v3 patch with this change.

Thanks,
-Prakash.

[PATCH v3 2/2] userfaultfd: selftest: Add tests for UFFD_FEATURE_SIGBUS feature

[Prakash Sangappa]

This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
accessing monitored area after signal delivery.

This patch also fixes a bug in uffd_poll_thread() where 'uffd'
is leaked.

Signed-off-by: Prakash Sangappa 
---
Change log

v3:  Eliminated use of sig_repeat variable and simplified error return.

v2:
  - Added comments to explain the tests.
  - Fixed test to fail immediately if signal repeats.
  - Addressed other review comments.

v1: https://lkml.org/lkml/2017/7/26/101
---
 tools/testing/selftests/vm/userfaultfd.c |  127 +-
 1 files changed, 124 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/vm/userfaultfd.c 
b/tools/testing/selftests/vm/userfaultfd.c
index 1eae79a..52740ae 100644
--- a/tools/testing/selftests/vm/userfaultfd.c
+++ b/tools/testing/selftests/vm/userfaultfd.c
@@ -66,6 +66,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef __NR_userfaultfd
 
@@ -408,6 +409,7 @@ static int copy_page(int ufd, unsigned long offset)
userfaults++;
break;
case UFFD_EVENT_FORK:
+   close(uffd);
uffd = msg.arg.fork.ufd;
pollfd[0].fd = uffd;
break;
@@ -572,6 +574,17 @@ static int userfaultfd_open(int features)
return 0;
 }
 
+sigjmp_buf jbuf, *sigbuf;
+
+static void sighndl(int sig, siginfo_t *siginfo, void *ptr)
+{
+   if (sig == SIGBUS) {
+   if (sigbuf)
+   siglongjmp(*sigbuf, 1);
+   abort();
+   }
+}
+
 /*
  * For non-cooperative userfaultfd test we fork() a process that will
  * generate pagefaults, will mremap the area monitored by the
@@ -585,19 +598,59 @@ static int userfaultfd_open(int features)
  * The release of the pages currently generates event for shmem and
  * anonymous memory (UFFD_EVENT_REMOVE), hence it is not checked
  * for hugetlb.
+ * For signal test(UFFD_FEATURE_SIGBUS), signal_test = 1, we register
+ * monitored area, generate pagefaults and test that signal is delivered.
+ * Use UFFDIO_COPY to allocate missing page and retry. For signal_test = 2
+ * test robustness use case - we release monitored area, fork a process
+ * that will generate pagefaults and verify signal is generated.
+ * This also tests UFFD_FEATURE_EVENT_FORK event along with the signal
+ * feature. Using monitor thread, verify no userfault events are generated.
  */
-static int faulting_process(void)
+static int faulting_process(int signal_test)
 {
unsigned long nr;
unsigned long long count;
unsigned long split_nr_pages;
+   unsigned long lastnr;
+   struct sigaction act;
+   unsigned long signalled = 0;
 
if (test_type != TEST_HUGETLB)
split_nr_pages = (nr_pages + 1) / 2;
else
split_nr_pages = nr_pages;
 
+   if (signal_test) {
+   sigbuf = &jbuf;
+   memset(&act, 0, sizeof(act));
+   act.sa_sigaction = sighndl;
+   act.sa_flags = SA_SIGINFO;
+   if (sigaction(SIGBUS, &act, 0)) {
+   perror("sigaction");
+   return 1;
+   }
+   lastnr = (unsigned long)-1;
+   }
+
for (nr = 0; nr < split_nr_pages; nr++) {
+   if (signal_test) {
+   if (sigsetjmp(*sigbuf, 1) != 0) {
+   if (nr == lastnr) {
+   fprintf(stderr, "Signal repeated\n");
+   return 1;
+   }
+
+   lastnr = nr;
+   if (signal_test == 1) {
+   if (copy_page(uffd, nr * page_size))
+   signalled++;
+   } else {
+   signalled++;
+   continue;
+   }
+   }
+   }
+
count = *area_count(area_dst, nr);
if (count != count_verify[nr]) {
fprintf(stderr,
@@ -607,6 +660,9 @@ static int faulting_process(void)
}
}
 
+   if (signal_test)
+   return signalled != split_nr_pages;
+
if (test_type == TEST_HUGETLB)
return 0;
 
@@ -761,7 +817,7 @@ static int userfaultfd_events_test(void)
perror("fork"), exit(1);
 
if (!pid)
-   return faulting_process();
+   return faulting_process(0);
 
waitpid(pid, &err, 0);
if (err)
@@ -778,6 +834,70 @@ static int userfaultfd_events_test(void)
return userfaults != nr_pages;
 }
 
+static int userfaul

[PATCH 2/6] pinctrl: uniphier: fix pin_config_get() for input-enable

[Masahiro Yamada]

For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers.  So, the register offset must be
taken into account.  Otherwise, wrong input-enable status is displayed.

While we here, rename the macro because it is a base address.

Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new 
SoCs")
Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index c649e835bd54..f2f0f9dcfec3 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -32,7 +32,7 @@
 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
-#define UNIPHIER_PINCTRL_IECTRL0x1d00
+#define UNIPHIER_PINCTRL_IECTRL_BASE   0x1d00
 
 struct uniphier_pinctrl_priv {
struct pinctrl_desc pctldesc;
@@ -252,18 +252,21 @@ static int uniphier_conf_pin_input_enable_get(struct 
pinctrl_dev *pctldev,
 {
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
-   unsigned int val;
+   unsigned int reg, mask, val;
int ret;
 
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
/* This pin is always input-enabled. */
return 0;
 
-   ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
+   reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
+   mask = BIT(iectrl % 32);
+
+   ret = regmap_read(priv->regmap, reg, &val);
if (ret)
return ret;
 
-   return val & BIT(iectrl) ? 0 : -EINVAL;
+   return val & mask ? 0 : -EINVAL;
 }
 
 static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
@@ -456,7 +459,7 @@ static int uniphier_conf_pin_input_enable(struct 
pinctrl_dev *pctldev,
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
return enable ? 0 : -EINVAL;
 
-   reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
+   reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
mask = BIT(iectrl % 32);
 
return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
-- 
2.7.4

[PATCH 1/6] pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()

[Masahiro Yamada]

All UniPhier pinctrl drivers are built-in.  Exporting the symbol
is meaningless.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 30dec0ee7f35..c649e835bd54 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include 
 #include 
 #include 
 #include 
@@ -731,4 +730,3 @@ int uniphier_pinctrl_probe(struct platform_device *pdev,
 
return 0;
 }
-EXPORT_SYMBOL_GPL(uniphier_pinctrl_probe);
-- 
2.7.4

[PATCH 6/6] pinctrl: uniphier: add UniPhier PXs3 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PXs3 SoC.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/Kconfig |   4 +
 drivers/pinctrl/uniphier/Makefile|   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 989 +++
 3 files changed, 994 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index e5826eaa7170..9f2a1c666def 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -40,4 +40,8 @@ config PINCTRL_UNIPHIER_LD20
bool "UniPhier LD20 SoC pinctrl driver"
default ARM64
 
+config PINCTRL_UNIPHIER_PXS3
+   bool "UniPhier PXs3 SoC pinctrl driver"
+   default ARM64
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index 9f4bc8aa6f68..d592ff77d60f 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += 
pinctrl-uniphier-pxs2.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B)+= pinctrl-uniphier-ld6b.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD11)+= pinctrl-uniphier-ld11.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD20)+= pinctrl-uniphier-ld20.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3)+= pinctrl-uniphier-pxs3.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
new file mode 100644
index ..d9f166f0cc86
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -0,0 +1,989 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = {
+   UNIPHIER_PINCTRL_PIN(0, "LPST", UNIPHIER_PIN_IECTRL_EXIST,
+0, UNIPHIER_PIN_DRV_3BIT,
+0, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(1, "ED0", UNIPHIER_PIN_IECTRL_EXIST,
+1, UNIPHIER_PIN_DRV_3BIT,
+1, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(2, "ED1", UNIPHIER_PIN_IECTRL_EXIST,
+2, UNIPHIER_PIN_DRV_3BIT,
+2, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(3, "ED2", UNIPHIER_PIN_IECTRL_EXIST,
+3, UNIPHIER_PIN_DRV_3BIT,
+3, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(4, "ED3", UNIPHIER_PIN_IECTRL_EXIST,
+4, UNIPHIER_PIN_DRV_3BIT,
+4, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(5, "ED4", UNIPHIER_PIN_IECTRL_EXIST,
+5, UNIPHIER_PIN_DRV_3BIT,
+5, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(6, "ED5", UNIPHIER_PIN_IECTRL_EXIST,
+6, UNIPHIER_PIN_DRV_3BIT,
+6, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(7, "ED6", UNIPHIER_PIN_IECTRL_EXIST,
+7, UNIPHIER_PIN_DRV_3BIT,
+7, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(8, "ED7", UNIPHIER_PIN_IECTRL_EXIST,
+8, UNIPHIER_PIN_DRV_3BIT,
+8, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(9, "XERWE0", UNIPHIER_PIN_IECTRL_EXIST,
+9, UNIPHIER_PIN_DRV_3BIT,
+9, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(10, "XERWE1", UNIPHIER_PIN_IECTRL_EXIST,
+10, UNIPHIER_PIN_DRV_3BIT,
+10, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(11, "ERXW", UNIPHIER_PIN_IECTRL_EXIST,
+11, UNIPHIER_PIN_DRV_3BIT,
+11, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(12, "ES0", UNIPHIER_PIN_IECTRL_EXIST,
+12, UNIPHIER_PIN_DRV_3BIT,
+12, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(13, "ES1", UNIPHIER_PIN_IECTRL_EXIST,
+13, UNIPHIER_PIN_DRV_3BIT,
+13, UNIPHIER_PIN_PULL_DOWN),
+   UNIPHIER_PINCTRL_PIN(14, "ES2", UNIPHIER_PIN_IECTRL_EXIST,
+14, UNIPHIER_

[PATCH 5/6] pinctrl: uniphier: add suspend / resume support

[Masahiro Yamada]

Save registers lost in the sleep when suspending, and restore them
when resuming.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 178 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c  |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  |   2 +
 10 files changed, 188 insertions(+)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index b976e9109b1d..5d8c9efd8135 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -34,11 +35,19 @@
 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
 #define UNIPHIER_PINCTRL_IECTRL_BASE   0x1d00
 
+struct uniphier_pinctrl_reg_region {
+   struct list_head node;
+   unsigned int base;
+   unsigned int nregs;
+   u32 vals[0];
+};
+
 struct uniphier_pinctrl_priv {
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct regmap *regmap;
struct uniphier_pinctrl_socdata *socdata;
+   struct list_head reg_regions;
 };
 
 static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev)
@@ -688,12 +697,177 @@ static const struct pinmux_ops uniphier_pmxops = {
.strict = true,
 };
 
+#ifdef CONFIG_PM_SLEEP
+static int uniphier_pinctrl_suspend(struct device *dev)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev);
+   struct uniphier_pinctrl_reg_region *r;
+   int ret;
+
+   list_for_each_entry(r, &priv->reg_regions, node) {
+   ret = regmap_bulk_read(priv->regmap, r->base, r->vals,
+  r->nregs);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static int uniphier_pinctrl_resume(struct device *dev)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev);
+   struct uniphier_pinctrl_reg_region *r;
+   int ret;
+
+   list_for_each_entry(r, &priv->reg_regions, node) {
+   ret = regmap_bulk_write(priv->regmap, r->base, r->vals,
+   r->nregs);
+   if (ret)
+   return ret;
+   }
+
+   if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+   ret = regmap_write(priv->regmap,
+  UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static int uniphier_pinctrl_add_reg_region(struct device *dev,
+  struct uniphier_pinctrl_priv *priv,
+  unsigned int base,
+  unsigned int count,
+  unsigned int width)
+{
+   struct uniphier_pinctrl_reg_region *region;
+   unsigned int nregs;
+
+   if (!count)
+   return 0;
+
+   nregs = DIV_ROUND_UP(count * width, 32);
+
+   region = devm_kzalloc(dev,
+ sizeof(*region) + sizeof(region->vals[0]) * nregs,
+ GFP_KERNEL);
+   if (!region)
+   return -ENOMEM;
+
+   region->base = base;
+   region->nregs = nregs;
+
+   list_add_tail(®ion->node, &priv->reg_regions);
+
+   return 0;
+}
+#endif
+
+static int uniphier_pinctrl_pm_init(struct device *dev,
+   struct uniphier_pinctrl_priv *priv)
+{
+#ifdef CONFIG_PM_SLEEP
+   const struct uniphier_pinctrl_socdata *socdata = priv->socdata;
+   unsigned int num_drvctrl = 0;
+   unsigned int num_drv2ctrl = 0;
+   unsigned int num_drv3ctrl = 0;
+   unsigned int num_pupdctrl = 0;
+   unsigned int num_iectrl = 0;
+   unsigned int iectrl, drvctrl, pupdctrl;
+   enum uniphier_pin_drv_type drv_type;
+   enum uniphier_pin_pull_dir pull_dir;
+   int i, ret;
+
+   for (i = 0; i < socdata->npins; i++) {
+   void *drv_data = socdata->pins[i].drv_data;
+
+   drvctrl = uniphier_pin_get_drvctrl(drv_data);
+   drv_type = uniphier_pin_get_drv_type(drv_data);
+   pupdctrl = uniphier_pin_get_pupdctrl(drv_data);
+   pull_dir = uniphier_pin_get_pull_dir(drv_data);
+   iectrl = uniphier_pin_get_iectrl(drv_data);
+
+   switch (drv_type) {
+   case UNIPHIER_PIN

[PATCH 4/6] pinctrl: uniphier: omit redundant input enable bit information

[Masahiro Yamada]

For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit
number matches its pin number.  So, this is redundant information.
Instead, we just need a flag to know if the iectrl gating exists or not.

With this refactoring, 5 bits in pin data will be saved.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c |  45 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 284 +-
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 352 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  |   3 +-
 4 files changed, 345 insertions(+), 339 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 6de6fdca4e9c..b976e9109b1d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -138,10 +138,11 @@ static const struct pinctrl_ops uniphier_pctlops = {
 };
 
 static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
- const struct pin_desc *desc,
+ unsigned int pin,
  enum pin_config_param param)
 {
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+   const struct pin_desc *desc = pin_desc_get(pctldev, pin);
enum uniphier_pin_pull_dir pull_dir =
uniphier_pin_get_pull_dir(desc->drv_data);
unsigned int pupdctrl, reg, shift, val;
@@ -188,10 +189,10 @@ static int uniphier_conf_pin_bias_get(struct pinctrl_dev 
*pctldev,
 }
 
 static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
-  const struct pin_desc *desc,
-  u16 *strength)
+  unsigned int pin, u16 *strength)
 {
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+   const struct pin_desc *desc = pin_desc_get(pctldev, pin);
enum uniphier_pin_drv_type type =
uniphier_pin_get_drv_type(desc->drv_data);
const unsigned int strength_1bit[] = {4, 8};
@@ -248,9 +249,10 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev 
*pctldev,
 }
 
 static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
- const struct pin_desc *desc)
+ unsigned int pin)
 {
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+   const struct pin_desc *desc = pin_desc_get(pctldev, pin);
unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
unsigned int reg, mask, val;
int ret;
@@ -259,6 +261,9 @@ static int uniphier_conf_pin_input_enable_get(struct 
pinctrl_dev *pctldev,
/* This pin is always input-enabled. */
return 0;
 
+   if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
+   iectrl = pin;
+
reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
mask = BIT(iectrl % 32);
 
@@ -273,7 +278,6 @@ static int uniphier_conf_pin_config_get(struct pinctrl_dev 
*pctldev,
unsigned pin,
unsigned long *configs)
 {
-   const struct pin_desc *desc = pin_desc_get(pctldev, pin);
enum pin_config_param param = pinconf_to_config_param(*configs);
bool has_arg = false;
u16 arg;
@@ -283,14 +287,14 @@ static int uniphier_conf_pin_config_get(struct 
pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
-   ret = uniphier_conf_pin_bias_get(pctldev, desc, param);
+   ret = uniphier_conf_pin_bias_get(pctldev, pin, param);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
-   ret = uniphier_conf_pin_drive_get(pctldev, desc, &arg);
+   ret = uniphier_conf_pin_drive_get(pctldev, pin, &arg);
has_arg = true;
break;
case PIN_CONFIG_INPUT_ENABLE:
-   ret = uniphier_conf_pin_input_enable_get(pctldev, desc);
+   ret = uniphier_conf_pin_input_enable_get(pctldev, pin);
break;
default:
/* unsupported parameter */
@@ -305,10 +309,11 @@ static int uniphier_conf_pin_config_get(struct 
pinctrl_dev *pctldev,
 }
 
 static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
- const struct pin_desc *desc,
+ unsigned int pin,
  enum pin_config_param param, u32 arg)
 {
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+   const struct pin_desc *desc = pin_desc_get(pctldev, pin);
enum uniphie

[PATCH 0/6] pinctrl: uniphier: UniPhier pinctrl updates for v4.14

[Masahiro Yamada]

This series includes:
  - Clean up redundant pin data
  - Add simple suspend / resume support
  - Add a driver for a new SoC



Masahiro Yamada (6):
  pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()
  pinctrl: uniphier: fix pin_config_get() for input-enable
  pinctrl: uniphier: clean up GPIO port muxing
  pinctrl: uniphier: omit redundant input enable bit information
  pinctrl: uniphier: add suspend / resume support
  pinctrl: uniphier: add UniPhier PXs3 pinctrl driver

 drivers/pinctrl/uniphier/Kconfig |   4 +
 drivers/pinctrl/uniphier/Makefile|   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 277 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 660 ---
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 709 +---
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c  | 273 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 386 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 451 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 458 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 386 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 989 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 273 +--
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  |  40 +-
 13 files changed, 1809 insertions(+), 3098 deletions(-)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c

-- 
2.7.4

Re: Udpated sys_membarrier() speedup patch, FYI

[Avi Kivity]

On 07/28/2017 12:02 AM, Mathieu Desnoyers wrote:

- On Jul 27, 2017, at 4:58 PM, Mathieu Desnoyers 
mathieu.desnoy...@efficios.com wrote:


- On Jul 27, 2017, at 4:37 PM, Paul E. McKenney paul...@linux.vnet.ibm.com
wrote:


On Thu, Jul 27, 2017 at 11:04:13PM +0300, Avi Kivity wrote:

[...]

+
+   this_cpu = raw_smp_processor_id();
+   for_each_online_cpu(cpu) {
+   struct task_struct *p;
+
+   if (cpu == this_cpu)
+   continue;
+   rcu_read_lock();
+   p = task_rcu_dereference(&cpu_rq(cpu)->curr);
+   if (p && p->mm == current->mm)
+   __cpumask_set_cpu(cpu, tmpmask);

This gets you some false positives, if the CPU idled then mm will
not have changed.

Good point!  The battery-powered embedded guys would probably prefer
we not needlessly IPI idle CPUs.  We cannot rely on RCU's dyntick-idle
state in nohz_full cases.  Not sure if is_idle_task() can be used
safely, given things like play_idle().

Would changing the check in this loop to:

if (p && !is_idle_task(p) && p->mm == current->mm) {

work for you ?

Avi, is there an optimization that allows current->mm to be non-null
when the idle task is scheduled that I am missing ?

I would have expected current->mm to be always NULL for idle
tasks.




I remembered that current->mm does not change when switching to a kernel 
task, but my Kernlish is very rusty, or maybe it has changed.

Re: [PATCH 12/12] mmc: bcm2835: constify mmc_host_ops structures

[Stefan Wahren]

Am 29.07.2017 um 07:59 schrieb Julia Lawall:
> The mmc_host_ops structure is only stored in the ops field of an
> mmc_host structure, which is declared as const.  Thus the mmc_host_ops
> structure itself can be const.
>
> Done with the help of Coccinelle.
>
> // 
> @r disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct mmc_host_ops i@p = { ... };
>
> @ok1@
> struct mmc_host *mmc;
> identifier r.i;
> position p;
> @@
> mmc->ops = &i@p
>
> @bad@
> position p != {r.p,ok1.p};
> identifier r.i;
> struct mmc_host_ops e;
> @@
> e@i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r.i;
> @@
> static
> +const
>  struct mmc_host_ops i = { ... };
> // 
>
> Signed-off-by: Julia Lawall 

Acked-by: Stefan Wahren 

Re: [PATCH v5 3/7] phy: qcom-qmp: Fix phy pipe clock name

[Vivek Gautam]

Hi,


On 07/31/2017 11:09 AM, Varadarajan Narayanan wrote:

Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.

Signed-off-by: Varadarajan Narayanan 
---
  drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++--
  1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..464049c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -925,29 +925,28 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
   *clk  |   +---+   |   +-+
   * +---+
   */
-static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
  {
-   char name[24];
struct clk_fixed_rate *fixed;
struct clk_init_data init = { };
+   int ret;
  
-	switch (qmp->cfg->type) {

-   case PHY_TYPE_USB3:
-   snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src");
-   break;
-   case PHY_TYPE_PCIE:
-   snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id);
-   break;
-   default:
+   if ((qmp->cfg->type != PHY_TYPE_USB3) &&
+   (qmp->cfg->type != PHY_TYPE_PCIE)) {
/* not all phys register pipe clocks, so return success */
return 0;
}
  
+	ret = of_property_read_string(np, "clock-output-names", &init.name);

+   if (ret) {
+   dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
+   return ret;
+   }
+
fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return -ENOMEM;
  
-	init.name = name;

init.ops = &clk_fixed_rate_ops;
  
  	/* controllers using QMP phys use 125MHz pipe clock interface */

@@ -1110,6 +1109,7 @@ static int qcom_qmp_phy_probe(struct platform_device 
*pdev)
  
  	id = 0;

for_each_available_child_of_node(dev->of_node, child) {
+

Minor nits - this extra line not needed.


/* Create per-lane phy */
ret = qcom_qmp_phy_create(dev, child, id);
if (ret) {
@@ -1119,10 +1119,10 @@ static int qcom_qmp_phy_probe(struct platform_device 
*pdev)
}
  
  		/*

-* Register the pipe clock provided by phy.
-* See function description to see details of this pipe clock.
+* Register the pipe clock provided by phy. See function
+* description to see details of this pipe clock.


Is there some whitespace fixed here? Otherwise unnecessary hunk.

With these minor nits fixed,

Reviewed-by: Vivek Gautam 


 */
-   ret = phy_pipe_clk_register(qmp, id);
+   ret = phy_pipe_clk_register(qmp, child);
if (ret) {
dev_err(qmp->dev,
"failed to register pipe clock source\n");


--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 1/2] i2c: uniphier: add suspend / resume support

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Fix define but not used warning

 drivers/i2c/busses/i2c-uniphier.c | 40 ++-
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-uniphier.c 
b/drivers/i2c/busses/i2c-uniphier.c
index 777c0fe93653..bb181b088291 100644
--- a/drivers/i2c/busses/i2c-uniphier.c
+++ b/drivers/i2c/busses/i2c-uniphier.c
@@ -53,6 +53,7 @@ struct uniphier_i2c_priv {
void __iomem *membase;
struct clk *clk;
unsigned int busy_cnt;
+   unsigned int clk_cycle;
 };
 
 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
@@ -316,13 +317,13 @@ static struct i2c_bus_recovery_info 
uniphier_i2c_bus_recovery_info = {
.unprepare_recovery = uniphier_i2c_unprepare_recovery,
 };
 
-static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv,
-u32 bus_speed, unsigned long clk_rate)
+static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
 {
+   unsigned int cyc = priv->clk_cycle;
+
uniphier_i2c_reset(priv, true);
 
-   writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed),
-  priv->membase + UNIPHIER_I2C_CLK);
+   writel((cyc / 2 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
 
uniphier_i2c_reset(priv, false);
 }
@@ -376,6 +377,7 @@ static int uniphier_i2c_probe(struct platform_device *pdev)
goto disable_clk;
}
 
+   priv->clk_cycle = clk_rate / bus_speed;
init_completion(&priv->comp);
priv->adap.owner = THIS_MODULE;
priv->adap.algo = &uniphier_i2c_algo;
@@ -386,7 +388,7 @@ static int uniphier_i2c_probe(struct platform_device *pdev)
i2c_set_adapdata(&priv->adap, priv);
platform_set_drvdata(pdev, priv);
 
-   uniphier_i2c_hw_init(priv, bus_speed, clk_rate);
+   uniphier_i2c_hw_init(priv);
 
ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
   priv);
@@ -413,6 +415,33 @@ static int uniphier_i2c_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
+{
+   struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
+
+   clk_disable_unprepare(priv->clk);
+
+   return 0;
+}
+
+static int __maybe_unused uniphier_i2c_resume(struct device *dev)
+{
+   struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
+   int ret;
+
+   ret = clk_prepare_enable(priv->clk);
+   if (ret)
+   return ret;
+
+   uniphier_i2c_hw_init(priv);
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_i2c_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
+};
+
 static const struct of_device_id uniphier_i2c_match[] = {
{ .compatible = "socionext,uniphier-i2c" },
{ /* sentinel */ }
@@ -425,6 +454,7 @@ static struct platform_driver uniphier_i2c_drv = {
.driver = {
.name  = "uniphier-i2c",
.of_match_table = uniphier_i2c_match,
+   .pm = &uniphier_i2c_pm_ops,
},
 };
 module_platform_driver(uniphier_i2c_drv);
-- 
2.7.4

[PATCH v2 2/2] i2c: uniphier-f: add suspend / resume support

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Fix define but not used warning

 drivers/i2c/busses/i2c-uniphier-f.c | 46 +
 1 file changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-uniphier-f.c 
b/drivers/i2c/busses/i2c-uniphier-f.c
index beee31892295..9918bdd81619 100644
--- a/drivers/i2c/busses/i2c-uniphier-f.c
+++ b/drivers/i2c/busses/i2c-uniphier-f.c
@@ -97,6 +97,7 @@ struct uniphier_fi2c_priv {
int error;
unsigned int flags;
unsigned int busy_cnt;
+   unsigned int clk_cycle;
 };
 
 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
@@ -461,9 +462,9 @@ static struct i2c_bus_recovery_info 
uniphier_fi2c_bus_recovery_info = {
.unprepare_recovery = uniphier_fi2c_unprepare_recovery,
 };
 
-static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv,
- u32 bus_speed, unsigned long clk_rate)
+static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
 {
+   unsigned int cyc = priv->clk_cycle;
u32 tmp;
 
tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
@@ -472,12 +473,10 @@ static void uniphier_fi2c_hw_init(struct 
uniphier_fi2c_priv *priv,
 
uniphier_fi2c_reset(priv);
 
-   tmp = clk_rate / bus_speed;
-
-   writel(tmp, priv->membase + UNIPHIER_FI2C_CYC);
-   writel(tmp / 2, priv->membase + UNIPHIER_FI2C_LCTL);
-   writel(tmp / 2, priv->membase + UNIPHIER_FI2C_SSUT);
-   writel(tmp / 16, priv->membase + UNIPHIER_FI2C_DSUT);
+   writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
+   writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL);
+   writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
+   writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
 
uniphier_fi2c_prepare_operation(priv);
 }
@@ -531,6 +530,7 @@ static int uniphier_fi2c_probe(struct platform_device *pdev)
goto disable_clk;
}
 
+   priv->clk_cycle = clk_rate / bus_speed;
init_completion(&priv->comp);
priv->adap.owner = THIS_MODULE;
priv->adap.algo = &uniphier_fi2c_algo;
@@ -541,7 +541,7 @@ static int uniphier_fi2c_probe(struct platform_device *pdev)
i2c_set_adapdata(&priv->adap, priv);
platform_set_drvdata(pdev, priv);
 
-   uniphier_fi2c_hw_init(priv, bus_speed, clk_rate);
+   uniphier_fi2c_hw_init(priv);
 
ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
   pdev->name, priv);
@@ -568,6 +568,33 @@ static int uniphier_fi2c_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
+{
+   struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
+
+   clk_disable_unprepare(priv->clk);
+
+   return 0;
+}
+
+static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
+{
+   struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
+   int ret;
+
+   ret = clk_prepare_enable(priv->clk);
+   if (ret)
+   return ret;
+
+   uniphier_fi2c_hw_init(priv);
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
+};
+
 static const struct of_device_id uniphier_fi2c_match[] = {
{ .compatible = "socionext,uniphier-fi2c" },
{ /* sentinel */ }
@@ -580,6 +607,7 @@ static struct platform_driver uniphier_fi2c_drv = {
.driver = {
.name  = "uniphier-fi2c",
.of_match_table = uniphier_fi2c_match,
+   .pm = &uniphier_fi2c_pm_ops,
},
 };
 module_platform_driver(uniphier_fi2c_drv);
-- 
2.7.4

[PATCH v2] bus: uniphier-system-bus: set up registers when resuming

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Fix define but not used warning

 drivers/bus/uniphier-system-bus.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/bus/uniphier-system-bus.c 
b/drivers/bus/uniphier-system-bus.c
index 1e6e0269edcc..f76be6bd6eb3 100644
--- a/drivers/bus/uniphier-system-bus.c
+++ b/drivers/bus/uniphier-system-bus.c
@@ -256,10 +256,23 @@ static int uniphier_system_bus_probe(struct 
platform_device *pdev)
 
uniphier_system_bus_set_reg(priv);
 
+   platform_set_drvdata(pdev, priv);
+
/* Now, the bus is configured.  Populate platform_devices below it */
return of_platform_default_populate(dev->of_node, NULL, dev);
 }
 
+static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
+{
+   uniphier_system_bus_set_reg(dev_get_drvdata(dev));
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
+};
+
 static const struct of_device_id uniphier_system_bus_match[] = {
{ .compatible = "socionext,uniphier-system-bus" },
{ /* sentinel */ }
@@ -271,6 +284,7 @@ static struct platform_driver uniphier_system_bus_driver = {
.driver = {
.name   = "uniphier-system-bus",
.of_match_table = uniphier_system_bus_match,
+   .pm = &uniphier_system_bus_pm_ops,
},
 };
 module_platform_driver(uniphier_system_bus_driver);
-- 
2.7.4

Re: [PATCH v5 2/7] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074

[Vivek Gautam]

On 07/31/2017 11:09 AM, Varadarajan Narayanan wrote:

IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.

Signed-off-by: Varadarajan Narayanan 
---


Reviewed-by: Vivek Gautam 


  Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 
  1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d7a51f..802af1b 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  
  Required properties:

   - compatible: compatible list, contains:
+  "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
   "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
   "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
  
@@ -38,6 +39,8 @@ Required properties:

 "phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
 "phy", "common".
+   For "qcom,ipq8074-qmp-pcie-phy" must contain:
+"phy", "common".
  
   - vdda-phy-supply: Phandle to a regulator supply to PHY core block.

   - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
   - clock-output-names: Name of the phy clock that will be the parent for
   the above pipe clock.
  
+	For "qcom,ipq8074-qmp-pcie-phy":

+   - "pcie20_phy0_pipe_clk"  Pipe Clock parent
+   (or)
+ "pcie20_phy1_pipe_clk"
+
   - resets: a list of phandles and reset controller specifier pairs,
   one for each entry in reset-names.
   - reset-names: Must contain following for pcie qmp phys:


--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 4/4] ACPI / EC: Enable noirq stage GPE polling

[Lv Zheng]

This patch enables noirq stage GPE polling for the EC driver.

EC is a very special driver, required to work throughout the entire
suspend/resume process. Thus this patch enables IRQ polling for EC during
noirq stages to avoid all kinds of possible issues.

If this commit is bisected to be a regression culprit, please report this
to bugzilla.kernel.org for further investigation.

Signed-off-by: Lv Zheng 
---
 drivers/acpi/ec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index 5f951ba..f5d629b 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -164,7 +164,7 @@ module_param(ec_polling_guard, uint, 0644);
 MODULE_PARM_DESC(ec_polling_guard, "Guard time(us) between EC accesses in 
polling modes");
 
 static unsigned int ec_event_clearing __read_mostly = ACPI_EC_EVT_TIMING_QUERY;
-static unsigned int ec_gpe_polling __read_mostly = ACPI_EC_GPE_POLL_NONE;
+static unsigned int ec_gpe_polling __read_mostly = ACPI_EC_GPE_POLL_RESUME;
 
 /*
  * If the number of false interrupts per one transaction exceeds
-- 
2.7.4

[PATCH v2 3/4] ACPI / EC: Add support to handle EC events earlier

[Lv Zheng]

Now as GPE poller is implemented, EC driver is able to detect EC events
during suspend/resume noirq stages, we can try to move EC event handling
earlier without being worried about post-resume event stuck.

Signed-off-by: Lv Zheng 
---
 drivers/acpi/ec.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index f1cffd4..5f951ba 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -1004,7 +1004,9 @@ static void acpi_ec_start(struct acpi_ec *ec, bool 
resuming)
if (!resuming) {
acpi_ec_submit_request(ec);
ec_dbg_ref(ec, "Increase driver");
-   }
+   } else if (!ec_freeze_events &&
+  ec_gpe_polling == ACPI_EC_GPE_POLL_RESUME)
+   __acpi_ec_enable_event(ec);
ec_log_drv("EC started");
}
spin_unlock_irqrestore(&ec->lock, flags);
-- 
2.7.4

[PATCH v2 2/4] ACPI / EC: Add IRQ polling support for noirq stages

[Lv Zheng]

1. Problems:
EC IRQs contain transaction IRQs (OBF/IBF) and event IRQ (SCI_EVT).

Transactions are initiated by hosts. The earliest OSPMs execution of EC
transactions is from acpi_ec_transaction(), where the common EC IRQ
handling procedure - advance_transaction() - is initiated from the task
context.
Events are initiated by targets. The earliest OSPMs execution of EC events
is from acpi_ec_gpe_handler(), where the common EC IRQ handling procedure -
advance_transaction() - is initiated from the IRQ context.

1.1. Problem 1: Cannot detect EC event in noirq stages.
There is a noirq stage during system suspend/resume procedures. We can see
that during this stage, advance_transaction() which monitors SCI_EVT can
only be invoked from ec_poll().  Thus if there is no EC transaction
occurring in this stage, EC driver cannot detect SCI_EVT.

Note that in noirq stage if there is an EC transaction pending,
advance_transaction() invoked because of the EC transaction can also help
to detect SCI_EVT and initiate the handling of the EC events. That's why
real reports related to this problem are rare and unreproducible as whether
there is an EC transaction occurred after an undetectable EC events during
noirq stages is random.

1.2. Problem 2: Handling of EC events may stuck for some GPE chips.
Normally, when STS is set, GPE IRQs can be triggered by GPE chips when EN
bit is set. Thus it is ensured that handling of the EC events triggered in
suspend noirq stage is just deferred to resume stage and there won't be EC
event losts.

But there might be chips do not contain AND logic betwee STS and EN to
trigger GPE. In such worst case, EC events may risk lost, handling of the
lost EC events can only start when there is an EC transaction occurred.
Thus if there is no EC transaction, handling of EC events may "stuck"
after resume in such worst case.

2. Old assumption and solution:
Originally, as EC driver actually has never been fully able to handle EC
events during noirq stages, we assumed that detecting such events in noirq
stage is useless and implemented "ec_freeze_events" to stop handling
SCI_EVT earlier after suspend and re-start handling SCI_EVT after resume.
The EC event handling is namely "frozen" during suspend/resume and
"ec_freeze_events" controls the timing of the "freeze". If this could work,
we shouldn't be required to implement GPE polling in noirq stage.

Note that this solution cannot solve problem 2.

3. New fact and solution:
Recently, some bug reports (see Link #1) revealed that we shouldn't
"freeze" EC event handling too early during these system suspend/resume
procedures. Based on this fact, we should detect SCI_EVT during noirq
stage, this left us no other choice than implementing IRQ polling for
SCI_EVT in this stage.

This patch adds a timer to poll EC events timely (0.5s) during system
suspend/resume noirq stages. As the bug reports may not be root caused,
and most of the platforms may not require this, this patch prepares an
option to make this behavior configurable.

Note that this solution can also solve problem 2.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=196129 [#1]
Signed-off-by: Lv Zheng 
---
 drivers/acpi/ec.c   | 130 
 drivers/acpi/internal.h |   1 +
 2 files changed, 131 insertions(+)

diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index 54879c7..f1cffd4 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -40,6 +40,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "internal.h"
@@ -87,6 +88,31 @@
 #define ACPI_EC_EVT_TIMING_QUERY   0x01
 #define ACPI_EC_EVT_TIMING_EVENT   0x02
 
+/*
+ * There is a noirq stage during suspend/resume and EC firmware may
+ * require OS to handle EC events (SCI_EVT) during this stage.
+ * If there is no EC transactions during this stage, SCI_EVT cannot be
+ * detected. In order to still detect SCI_EVT, IRQ must be polled by the
+ * EC GPE poller. There are 3 configurable modes implemented for the EC
+ * GPE poller:
+ * NONE:Do not enable noirq stage GPE poller.
+ * SUSPEND: Enable GPE poller for suspend noirq stage.
+ *  This mode detects SCI_EVT in suspend noirq stage, making sure
+ *  that all pre-suspend firmware events are handled before
+ *  entering a low power state. Some buggy EC firmware may require
+ *  this, otherwise some unknown firmware issues can be seen on
+ *  such platforms:
+ *  Link: https://bugzilla.kernel.org/show_bug.cgi?id=196129
+ * RESUME:  Enable GPE poller for suspend/resume noirq stages.
+ *  This mode detects SCI_EVT in both suspend and resume noirq
+ *  stages, making sure that all post-resume firmware events are
+ *  handled as early as possible. This mode might be able to solve
+ *  some unknown driver timing issues.
+ */
+#define ACPI_EC_GPE_POLL_NONE  0x00
+#define ACPI_EC_GPE_POLL_SUSPEND   0x01
+#define ACPI_EC_GPE_POLL_RESUME 

[PATCH v2 1/4] ACPI / EC: Cleanup EC GPE mask flag

[Lv Zheng]

EC_FLAGS_COMMAND_STORM is actually used to mask GPE during IRQ processing.
This patch cleans it up using more readable flag/function names.

Signed-off-by: Lv Zheng 
---
 drivers/acpi/ec.c | 23 +++
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index ddb01e9..54879c7 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -112,8 +112,7 @@ enum {
EC_FLAGS_EVT_HANDLER_INSTALLED, /* _Qxx handlers installed */
EC_FLAGS_STARTED,   /* Driver is started */
EC_FLAGS_STOPPED,   /* Driver is stopped */
-   EC_FLAGS_COMMAND_STORM, /* GPE storms occurred to the
-* current command processing */
+   EC_FLAGS_GPE_MASKED,/* GPE masked */
 };
 
 #define ACPI_EC_COMMAND_POLL   0x01 /* Available for command byte */
@@ -421,19 +420,19 @@ static void acpi_ec_complete_request(struct acpi_ec *ec)
wake_up(&ec->wait);
 }
 
-static void acpi_ec_set_storm(struct acpi_ec *ec, u8 flag)
+static void acpi_ec_mask_gpe(struct acpi_ec *ec)
 {
-   if (!test_bit(flag, &ec->flags)) {
+   if (!test_bit(EC_FLAGS_GPE_MASKED, &ec->flags)) {
acpi_ec_disable_gpe(ec, false);
ec_dbg_drv("Polling enabled");
-   set_bit(flag, &ec->flags);
+   set_bit(EC_FLAGS_GPE_MASKED, &ec->flags);
}
 }
 
-static void acpi_ec_clear_storm(struct acpi_ec *ec, u8 flag)
+static void acpi_ec_unmask_gpe(struct acpi_ec *ec)
 {
-   if (test_bit(flag, &ec->flags)) {
-   clear_bit(flag, &ec->flags);
+   if (test_bit(EC_FLAGS_GPE_MASKED, &ec->flags)) {
+   clear_bit(EC_FLAGS_GPE_MASKED, &ec->flags);
acpi_ec_enable_gpe(ec, false);
ec_dbg_drv("Polling disabled");
}
@@ -460,7 +459,7 @@ static bool acpi_ec_submit_flushable_request(struct acpi_ec 
*ec)
 
 static void acpi_ec_submit_query(struct acpi_ec *ec)
 {
-   acpi_ec_set_storm(ec, EC_FLAGS_COMMAND_STORM);
+   acpi_ec_mask_gpe(ec);
if (!acpi_ec_event_enabled(ec))
return;
if (!test_and_set_bit(EC_FLAGS_QUERY_PENDING, &ec->flags)) {
@@ -476,7 +475,7 @@ static void acpi_ec_complete_query(struct acpi_ec *ec)
if (test_and_clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags))
ec_dbg_evt("Command(%s) unblocked",
   acpi_ec_cmd_string(ACPI_EC_COMMAND_QUERY));
-   acpi_ec_clear_storm(ec, EC_FLAGS_COMMAND_STORM);
+   acpi_ec_unmask_gpe(ec);
 }
 
 static inline void __acpi_ec_enable_event(struct acpi_ec *ec)
@@ -688,7 +687,7 @@ static void advance_transaction(struct acpi_ec *ec)
++t->irq_count;
/* Allow triggering on 0 threshold */
if (t->irq_count == ec_storm_threshold)
-   acpi_ec_set_storm(ec, EC_FLAGS_COMMAND_STORM);
+   acpi_ec_mask_gpe(ec);
}
}
 out:
@@ -786,7 +785,7 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec,
 
spin_lock_irqsave(&ec->lock, tmp);
if (t->irq_count == ec_storm_threshold)
-   acpi_ec_clear_storm(ec, EC_FLAGS_COMMAND_STORM);
+   acpi_ec_unmask_gpe(ec);
ec_dbg_req("Command(%s) stopped", acpi_ec_cmd_string(t->command));
ec->curr = NULL;
/* Disable GPE for command processing (IBF=0/OBF=1) */
-- 
2.7.4

[PATCH v2 0/4] ACPI / EC: Solve EC event handling issues

[Lv Zheng]

There is a known issue in EC event handling. This patchset tries to handle
noirq stage EC event polling to fix this known issue.

In the very early version, the EC event polling mechanism is implemented by
a kernel thread to poll EC events. Now the mechanism is implemented by a
timer ticked in noirq stage to poll EC GPEs. In this newest timer version,
timer running period is shortened and thus is safer for s2idle mode.

After adding such a mechanism, we can try to handle EC events earlier after
resume, this may be able to solve some driver order issues.

Lv Zheng (4):
  ACPI / EC: Cleanup EC GPE mask flag
  ACPI / EC: Add IRQ polling support for noirq stages
  ACPI / EC: Add support to handle EC events earlier
  ACPI / EC: Enable noirq stage GPE polling

 drivers/acpi/ec.c   | 157 
 drivers/acpi/internal.h |   1 +
 2 files changed, 145 insertions(+), 13 deletions(-)

-- 
2.7.4

Re: mailing list for the dma mapping code

[Marek Szyprowski]

Hi All,

On 2017-07-17 08:45, Christoph Hellwig wrote:

Hi all,

currently the dma-mapping code doesn't have a dedicated mailing list,
and thus posts get lots on linux-kernel.  I wonder if we should add
a new separate list for it, or if it makes sense to reuse the existing
iommu list given that there is a fair amount of overlap.


I don't think that having one more mailing list is really needed. IOMMU
ml is fine for me if its current users are not against using also for
generic DMA-mapping related talks.

Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH v5 7/7] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

[Varadarajan Narayanan]

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.

The core init is the similar to the existing SoC, however the
clocks and reset lines differ.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/pci/dwc/pcie-qcom.c | 245 
 1 file changed, 245 insertions(+)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 6525f2f..b2ea953 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -37,6 +37,20 @@
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL   0x00
+#define MST_WAKEUP_EN  BIT(13)
+#define SLV_WAKEUP_EN  BIT(12)
+#define MSTR_ACLK_CGC_DIS  BIT(10)
+#define SLV_ACLK_CGC_DIS   BIT(9)
+#define CORE_CLK_CGC_DIS   BIT(6)
+#define AUX_PWR_DETBIT(4)
+#define L23_CLK_RMV_DISBIT(2)
+#define L1_CLK_RMV_DIS BIT(1)
+
+#define PCIE20_COMMAND_STATUS  0x04
+#define CMD_BME_VAL0x4
+#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
+#define PCIE_CAP_CPL_TIMEOUT_DISABLE   0x10
+
 #define PCIE20_PARF_PHY_CTRL   0x40
 #define PCIE20_PARF_PHY_REFCLK 0x4C
 #define PCIE20_PARF_DBI_BASE_ADDR  0x168
@@ -58,9 +72,22 @@
 #define CFG_BRIDGE_SB_INIT BIT(0)
 
 #define PCIE20_CAP 0x70
+#define PCIE20_CAP_LINK_CAPABILITIES   (PCIE20_CAP + 0xC)
+#define PCIE20_CAP_LINK_1  (PCIE20_CAP + 0x14)
+#define PCIE_CAP_LINK1_VAL 0x2fd7f
+
+#define PCIE20_PARF_Q2A_FLUSH  0x1AC
+
+#define PCIE20_MISC_CONTROL_1_REG  0x8BC
+#define DBI_RO_WR_EN   1
 
 #define PERST_DELAY_US 1000
 
+#define AXI_CLK_RATE   2
+
+#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
+#define SLV_ADDR_SPACE_SZ   0x1000
+
 struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
@@ -110,11 +137,21 @@ struct qcom_pcie_resources_2_4_0 {
struct reset_control *phy_ahb_reset;
 };
 
+struct qcom_pcie_resources_2_3_3 {
+   struct clk *iface;
+   struct clk *axi_m_clk;
+   struct clk *axi_s_clk;
+   struct clk *ahb_clk;
+   struct clk *aux_clk;
+   struct reset_control *rst[7];
+};
+
 union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
struct qcom_pcie_resources_2_3_2 v2_3_2;
struct qcom_pcie_resources_2_4_0 v2_4_0;
+   struct qcom_pcie_resources_2_3_3 v2_3_3;
 };
 
 struct qcom_pcie;
@@ -884,6 +921,206 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
return ret;
 }
 
+static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+   struct dw_pcie *pci = pcie->pci;
+   struct device *dev = pci->dev;
+   int i;
+   const char *rst_names[] = {
+   "axi_m", "axi_s", "pipe",
+   "axi_m_sticky", "sticky",
+   "ahb", "sleep",
+   };
+
+   res->iface = devm_clk_get(dev, "iface");
+   if (IS_ERR(res->iface))
+   return PTR_ERR(res->iface);
+
+   res->axi_m_clk = devm_clk_get(dev, "axi_m");
+   if (IS_ERR(res->axi_m_clk))
+   return PTR_ERR(res->axi_m_clk);
+
+   res->axi_s_clk = devm_clk_get(dev, "axi_s");
+   if (IS_ERR(res->axi_s_clk))
+   return PTR_ERR(res->axi_s_clk);
+
+   res->ahb_clk = devm_clk_get(dev, "ahb");
+   if (IS_ERR(res->ahb_clk))
+   return PTR_ERR(res->ahb_clk);
+
+   res->aux_clk = devm_clk_get(dev, "aux");
+   if (IS_ERR(res->aux_clk))
+   return PTR_ERR(res->aux_clk);
+
+   for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
+   res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
+   if (IS_ERR(res->rst[i]))
+   return PTR_ERR(res->rst[i]);
+   }
+
+   return 0;
+}
+
+static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+
+   clk_disable_unprepare(res->iface);
+   clk_disable_unprepare(res->axi_m_clk);
+   clk_disable_unprepare(res->axi_s_clk);
+   clk_disable_unprepare(res->ahb_clk);
+   clk_disable_unprepare(res->aux_clk);
+}
+
+static int qcom_pcie_enable_resources_2_3_3(struct qcom_pcie *pcie)
+{
+   struct qcom

[PATCH v5 2/7] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074

[Varadarajan Narayanan]

IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.

Signed-off-by: Varadarajan Narayanan 
---
 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d7a51f..802af1b 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
 
 Required properties:
  - compatible: compatible list, contains:
+  "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
   "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
   "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
 
@@ -38,6 +39,8 @@ Required properties:
 "phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
 "phy", "common".
+   For "qcom,ipq8074-qmp-pcie-phy" must contain:
+"phy", "common".
 
  - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
  - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
  - clock-output-names: Name of the phy clock that will be the parent for
   the above pipe clock.
 
+   For "qcom,ipq8074-qmp-pcie-phy":
+   - "pcie20_phy0_pipe_clk"Pipe Clock parent
+   (or)
+ "pcie20_phy1_pipe_clk"
+
  - resets: a list of phandles and reset controller specifier pairs,
   one for each entry in reset-names.
  - reset-names: Must contain following for pcie qmp phys:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 4/7] phy: qcom-qmp: Add support for IPQ8074

[Varadarajan Narayanan]

Add definitions required to enable QMP phy support for IPQ8074.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 124 
 1 file changed, 124 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 464049c..136d236 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -59,6 +59,7 @@
 #define QSERDES_COM_PLL_RCTRL_MODE10x088
 #define QSERDES_COM_PLL_CCTRL_MODE00x090
 #define QSERDES_COM_PLL_CCTRL_MODE10x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM0x0a8
 #define QSERDES_COM_SYSCLK_EN_SEL  0x0ac
 #define QSERDES_COM_RESETSM_CNTRL  0x0b4
 #define QSERDES_COM_RESTRIM_CTRL   0x0bc
@@ -143,6 +144,11 @@
 #define QPHY_LOCK_DETECT_CONFIG3   0x88
 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK   0xa0
 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB  0x1A8
+#define QPHY_OSC_DTCT_ACTIONS  0x1AC
+#define QPHY_RX_SIGDET_LVL 0x1D8
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB   0x1DC
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB   0x1E0
 
 /* QPHY_SW_RESET bit */
 #define SW_RESET   BIT(0)
@@ -382,6 +388,85 @@ enum qphy_reg_layout {
QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 };
 
+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+   QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+   QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+   QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAI

[PATCH v5 6/7] dt-bindings: pci: qcom: Add support for IPQ8074

[Varadarajan Narayanan]

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.

Signed-off-by: Varadarajan Narayanan 
---
 .../devicetree/bindings/pci/qcom,pcie.txt  | 23 ++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt 
b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 9d418b7..b3e36ef 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+   - "qcom,pcie-ipq8074" for ipq8074
 
 - reg:
Usage: required
@@ -105,6 +106,16 @@
- "bus_master"  Master AXI clock
- "bus_slave"   Slave AXI clock
 
+- clock-names:
+   Usage: required for ipq8074
+   Value type: 
+   Definition: Should contain the following entries
+   - "iface"   PCIe to SysNOC BIU clock
+   - "axi_m"   AXI Master clock
+   - "axi_s"   AXI Slave clock
+   - "ahb" AHB clock
+   - "aux" Auxiliary clock
+
 - resets:
Usage: required
Value type: 
@@ -144,6 +155,18 @@
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
 
+- reset-names:
+   Usage: required for ipq8074
+   Value type: 
+   Definition: Should contain the following entries
+   - "pipe"PIPE reset
+   - "sleep"   Sleep reset
+   - "sticky"  Core Sticky reset
+   - "axi_m"   AXI Master reset
+   - "axi_s"   AXI Slave reset
+   - "ahb" AHB Reset
+   - "axi_m_sticky"AXI Master Sticky reset
+
 - power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 0/7] Add support for IPQ8074 PCIe phy and controller

[Varadarajan Narayanan]

v5:
  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Renamed phy_phy clock as common clock

  phy: qcom-qmp: Fix phy pipe clock name
Moved the DT get into the registering function

  phy: qcom-qmp: Add support for IPQ8074
Place the IPQ8074 related structs similar to existing SoC.
Renamed phy_phy clock as common clock
v4:
  phy: qcom-qmp: Fix phy pipe clock name
Based on Vivek's comments, return failure only for
PCI/USB type of phys.
Removed Ack.

  phy: qcom-qmp: Handle unavailable registers
Removed this patch.
Incorrectly used a block of code that is not applicable
to IPQ8074, hence had to avoid an "unavailable" register.
Since that is addressed using 'has_phy_com_ctrl' this
patch is not needed.

  phy: qcom-qmp: Add support for IPQ8074
Set 'has_phy_com_ctrl' to false
Remove ipq8074_pciephy_regs_layout

v3:
  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incoporate Stan's feedback:-
 - Add SoC Wrapper and Synopsys Core IP versions

v2:
  dt-bindings: phy: qmp: Add output-clock-names
Added Rob H's Ack

  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Removed example
Added IPQ8074 specific details

  phy: qcom-qmp: Fix phy pipe clock name
Added Vivek's Ack

  phy: qcom-qmp: Handle unavailable registers
No changes

  phy: qcom-qmp: Add support for IPQ8074
No changes

  PCI: dwc: qcom: Use block IP version for operations
Added new patch to use block IP version instead of v1, v2...

  dt-bindings: pci: qcom: Add support for IPQ8074
Removed example
Added IPQ8074 specific details

  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incorporated Bjorn's feedback:-
 - Removed reset names, helper function to assert/deassert, helper
   function to R/M/W register.
 - Renamed sys_noc clock as iface clock
 - Added deinit if phy power on fails

v1:
Add definitions required to enable QMP phy support for IPQ8074.

Add support for the IPQ8074 PCIe controller.  IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.

Varadarajan Narayanan (7):
  dt-bindings: phy: qmp: Add output-clock-names
  dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
  phy: qcom-qmp: Fix phy pipe clock name
  phy: qcom-qmp: Add support for IPQ8074
  PCI: dwc: qcom: Use block IP version for operations
  dt-bindings: pci: qcom: Add support for IPQ8074
  PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

 .../devicetree/bindings/pci/qcom,pcie.txt  |  23 ++
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |  11 +
 drivers/pci/dwc/pcie-qcom.c| 378 +
 drivers/phy/qualcomm/phy-qcom-qmp.c| 152 -
 4 files changed, 488 insertions(+), 76 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 3/7] phy: qcom-qmp: Fix phy pipe clock name

[Varadarajan Narayanan]

Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.

Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..464049c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -925,29 +925,28 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
  *clk  |   +---+   |   +-+
  * +---+
  */
-static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 {
-   char name[24];
struct clk_fixed_rate *fixed;
struct clk_init_data init = { };
+   int ret;
 
-   switch (qmp->cfg->type) {
-   case PHY_TYPE_USB3:
-   snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src");
-   break;
-   case PHY_TYPE_PCIE:
-   snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id);
-   break;
-   default:
+   if ((qmp->cfg->type != PHY_TYPE_USB3) &&
+   (qmp->cfg->type != PHY_TYPE_PCIE)) {
/* not all phys register pipe clocks, so return success */
return 0;
}
 
+   ret = of_property_read_string(np, "clock-output-names", &init.name);
+   if (ret) {
+   dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
+   return ret;
+   }
+
fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return -ENOMEM;
 
-   init.name = name;
init.ops = &clk_fixed_rate_ops;
 
/* controllers using QMP phys use 125MHz pipe clock interface */
@@ -1110,6 +1109,7 @@ static int qcom_qmp_phy_probe(struct platform_device 
*pdev)
 
id = 0;
for_each_available_child_of_node(dev->of_node, child) {
+
/* Create per-lane phy */
ret = qcom_qmp_phy_create(dev, child, id);
if (ret) {
@@ -1119,10 +1119,10 @@ static int qcom_qmp_phy_probe(struct platform_device 
*pdev)
}
 
/*
-* Register the pipe clock provided by phy.
-* See function description to see details of this pipe clock.
+* Register the pipe clock provided by phy. See function
+* description to see details of this pipe clock.
 */
-   ret = phy_pipe_clk_register(qmp, id);
+   ret = phy_pipe_clk_register(qmp, child);
if (ret) {
dev_err(qmp->dev,
"failed to register pipe clock source\n");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 1/7] dt-bindings: phy: qmp: Add output-clock-names

[Varadarajan Narayanan]

The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.

Acked-by: Rob Herring 
Signed-off-by: Varadarajan Narayanan 
---
 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index e11c563..5d7a51f 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -60,6 +60,8 @@ Required properties for child node:
   one for each entry in clock-names.
  - clock-names: Must contain following for pcie and usb qmp phys:
 "pipe" for pipe clock specific to each lane.
+ - clock-output-names: Name of the phy clock that will be the parent for
+  the above pipe clock.
 
  - resets: a list of phandles and reset controller specifier pairs,
   one for each entry in reset-names.
@@ -96,6 +98,7 @@ Example:
 
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+   clock-output-names = "pcie_0_pipe_clk_src";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 5/7] PCI: dwc: qcom: Use block IP version for operations

[Varadarajan Narayanan]

Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.

Signed-off-by: Varadarajan Narayanan 
---
 drivers/pci/dwc/pcie-qcom.c | 133 +++-
 1 file changed, 71 insertions(+), 62 deletions(-)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index d15657d..6525f2f 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -61,7 +61,7 @@
 
 #define PERST_DELAY_US 1000
 
-struct qcom_pcie_resources_v0 {
+struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
@@ -75,7 +75,7 @@ struct qcom_pcie_resources_v0 {
struct regulator *vdda_refclk;
 };
 
-struct qcom_pcie_resources_v1 {
+struct qcom_pcie_resources_1_0_0 {
struct clk *iface;
struct clk *aux;
struct clk *master_bus;
@@ -84,7 +84,7 @@ struct qcom_pcie_resources_v1 {
struct regulator *vdda;
 };
 
-struct qcom_pcie_resources_v2 {
+struct qcom_pcie_resources_2_3_2 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -92,7 +92,7 @@ struct qcom_pcie_resources_v2 {
struct clk *pipe_clk;
 };
 
-struct qcom_pcie_resources_v3 {
+struct qcom_pcie_resources_2_4_0 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -111,10 +111,10 @@ struct qcom_pcie_resources_v3 {
 };
 
 union qcom_pcie_resources {
-   struct qcom_pcie_resources_v0 v0;
-   struct qcom_pcie_resources_v1 v1;
-   struct qcom_pcie_resources_v2 v2;
-   struct qcom_pcie_resources_v3 v3;
+   struct qcom_pcie_resources_1_0_0 v1_0_0;
+   struct qcom_pcie_resources_2_1_0 v2_1_0;
+   struct qcom_pcie_resources_2_3_2 v2_3_2;
+   struct qcom_pcie_resources_2_4_0 v2_4_0;
 };
 
 struct qcom_pcie;
@@ -172,7 +172,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
return dw_pcie_wait_for_link(pci);
 }
 
-static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
+static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
 {
u32 val;
 
@@ -182,9 +182,9 @@ static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie 
*pcie)
writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 }
 
-static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
 
@@ -232,9 +232,9 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie 
*pcie)
return PTR_ERR_OR_ZERO(res->phy_reset);
 }
 
-static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
@@ -249,9 +249,9 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
regulator_disable(res->vdda_refclk);
 }
 
-static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+   struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
u32 val;
@@ -367,9 +367,9 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
return ret;
 }
 
-static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
 
@@ -397,9 +397,9 @@ static int qcom_pcie_get_resources_v1(struct qcom_pcie 
*pcie)
return PTR_ERR_OR_ZERO(res->core);
 }
 
-static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 
reset_control_assert(res->core);
clk_disable_unprepare(res->slave_bus);
@@ -409,9 +409,9 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
regulator_disable(res->vdda);
 }
 
-static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
 {
-   struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+   struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struc

Re: [PATCH 2/4] clk: sunxi-ng: multiplier: Fix fractional mode

[Chen-Yu Tsai]

On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
 wrote:
> Driver for multiplier clock is missing a call to
> ccu_frac_helper_enable() when fractional mode is selected.
>
> Add a call to ccu_frac_helper_enable().
>
> Fixes: d77e8135b340 ("clk: sunxi-ng: multiplier: Add fractional support")
> Signed-off-by: Jernej Skrabec 

Queued as a fix for 4.13.

ChenYu

Re: [PATCH] phy: qcom-qmp: Fix failure path in phy_init functions

[Vivek Gautam]

Hi Kishon,


On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
 wrote:
> Fixing the clk enable failure path in qcom_qmp_phy_init()
> and cleanup the reset control deassertion failure path in
> qcom_qmp_phy_com_init().
>
> Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
>
> Cc: Kishon Vijay Abraham I 
> Signed-off-by: Vivek Gautam 

This patch got missed. Can you please pull this in?

regards
Vivek

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.c | 15 ++-
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 78ca62897784..7b739571b301 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -654,8 +654,6 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
> if (ret) {
> dev_err(qmp->dev, "%s reset deassert failed\n",
> qmp->cfg->reset_list[i]);
> -   while (--i >= 0)
> -   reset_control_assert(qmp->resets[i]);
> goto err_rst;
> }
> }
> @@ -684,7 +682,7 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
> if (ret) {
> dev_err(qmp->dev,
> "phy common block init timed-out\n");
> -   goto err_com_init;
> +   goto err_rst;
> }
> }
>
> @@ -692,11 +690,11 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
>
> return 0;
>
> -err_com_init:
> +err_rst:
> while (--i >= 0)
> reset_control_assert(qmp->resets[i]);
> -err_rst:
> mutex_unlock(&qmp->phy_mutex);
> +
> return ret;
>  }
>
> @@ -749,14 +747,13 @@ static int qcom_qmp_phy_init(struct phy *phy)
> if (ret) {
> dev_err(qmp->dev, "failed to enable %s clk, err=%d\n",
> qmp->cfg->clk_list[i], ret);
> -   while (--i >= 0)
> -   clk_disable_unprepare(qmp->clks[i]);
> +   goto err_clk;
> }
> }
>
> ret = qcom_qmp_phy_com_init(qmp);
> if (ret)
> -   goto err_com_init;
> +   goto err_clk;
>
> if (cfg->has_lane_rst) {
> ret = reset_control_deassert(qphy->lane_rst);
> @@ -804,7 +801,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
> reset_control_assert(qphy->lane_rst);
>  err_lane_rst:
> qcom_qmp_phy_com_exit(qmp);
> -err_com_init:
> +err_clk:
> while (--i >= 0)
> clk_disable_unprepare(qmp->clks[i]);
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>



-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 3/3] ANDROID: binder: fix proc->tsk check.

[Amit Pundir]

On 28 July 2017 at 17:26, Martijn Coenen  wrote:
> Commit c4ea41ba195d ("binder: use group leader instead of open thread")'
> was incomplete and didn't update a check in binder_mmap(), causing all
> mmap() calls into the binder driver to fail.
>

Fixes Android WiFi/BT regression reported on 4.13-rc2.

Tested-by: Amit Pundir 

> Signed-off-by: Martijn Coenen 
> ---
>  drivers/android/binder.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/android/binder.c b/drivers/android/binder.c
> index f7665c31feca..831cdd7d197d 100644
> --- a/drivers/android/binder.c
> +++ b/drivers/android/binder.c
> @@ -3362,7 +3362,7 @@ static int binder_mmap(struct file *filp, struct 
> vm_area_struct *vma)
> const char *failure_string;
> struct binder_buffer *buffer;
>
> -   if (proc->tsk != current)
> +   if (proc->tsk != current->group_leader)
> return -EINVAL;
>
> if ((vma->vm_end - vma->vm_start) > SZ_4M)
> --
> 2.14.0.rc0.400.g1c36432dff-goog
>

Re: [PATCH 0/4] clk: sunxi-ng: Fix issues with fractional mode

[Chen-Yu Tsai]

Hi Jernej,

On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
 wrote:
> During development of H3 HDMI driver, I found some issues with
> setting video clock rate. It turned out that clock driver decided
> to use fractional mode and selected right frequency, but it didn't
> enable it. Additionally, fractional helpers don't wait on lock.

What kind of resolution were you testing to actually hit this?

AFAIK the fractional mode is either 297 or 270 MHz. Even Full HD
1080p60 dot clocks aren't that high. And the clk drivers should
try to request a matching parent clk rate. So the PLL wouldn't
go that high. Are you testing 4k @ 30fps?

As it stands, I don't think any of the existing display support
can go that high, so I think we're safe as far as old kernels
go, i.e. we don't need to Cc stable for these.

Regards
ChenYu

> Patch 1 adds a call to N-M clock driver which enables fractional mode.
> It also clears M factor before that as required by most SoCs.
>
> Patch 2 adds a call to N clock driver which enables fractional mode.
>
> Patch 3 makes fractional helpers less chatty.
>
> Patch 4 adds a wait for lock to fractional helpers.
>
> Jernej Skrabec (4):
>   clk: sunxi-ng: Fix fractional mode for N-M clocks
>   clk: sunxi-ng: multiplier: Fix fractional mode
>   clk: sunxi-ng: Make fractional helper less chatty
>   clk: sunxi-ng: Wait for lock when using fractional mode
>
>  drivers/clk/sunxi-ng/ccu_frac.c | 14 --
>  drivers/clk/sunxi-ng/ccu_frac.h |  2 +-
>  drivers/clk/sunxi-ng/ccu_mult.c | 10 +++---
>  drivers/clk/sunxi-ng/ccu_nm.c   | 19 ---
>  4 files changed, 32 insertions(+), 13 deletions(-)
>
> --
> 2.13.3
>

Re: [PATCH v2 1/3] media: V3s: Add support for Allwinner CSI.

[Baruch Siach]

Hi Yong,

On Mon, Jul 31, 2017 at 09:48:06AM +0800, Yong wrote:
> On Sun, 30 Jul 2017 09:08:01 +0300
> Baruch Siach  wrote:
> > On Fri, Jul 28, 2017 at 06:02:33PM +0200, Maxime Ripard wrote:
> > > On Thu, Jul 27, 2017 at 01:01:35PM +0800, Yong Deng wrote:
> > > > +   regmap_write(sdev->regmap, CSI_CH_F0_BUFA_REG,
> > > > +(bus_addr + sdev->planar_offset[0]) >> 2);
> > 
> > Why do you need the bit shift? Does that work for you?
> > 
> > The User Manuals of both the V3s and the and the A33 (AKA R16) state that 
> > the 
> > BUFA field size in this register is 31:00, that is 32bit. I have found no 
> > indication of this bit shift in the Olimex provided sunxi-vfe[1] driver. On 
> > the A33 I have found that only after removing the bit-shift, (some sort of) 
> > data started to appear in the buffer.
> > 
> > [1] 
> > https://github.com/hehopmajieh/a33_linux/tree/master/drivers/media/video/sunxi-vfe
> 
> The Users Manuals do not document this bit shift. You should see line 10 to
> 32 in 
> https://github.com/hehopmajieh/a33_linux/blob/master/drivers/media/video/sunxi-vfe/csi/csi_reg.c

Thanks. So for my reference, the SoCs that don't need bit shift are A31, A23, 
and A33. SoCs that need bit shift are A80, A83, H3, and V3s (AKA V30).

baruch

-- 
 http://baruch.siach.name/blog/  ~. .~   Tk Open Systems
=}ooO--U--Ooo{=
   - bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

[PATCH] bus: uniphier-system-bus: set up registers when resuming

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.

Signed-off-by: Masahiro Yamada 
---

 drivers/bus/uniphier-system-bus.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/bus/uniphier-system-bus.c 
b/drivers/bus/uniphier-system-bus.c
index 1e6e0269edcc..f9c334159e83 100644
--- a/drivers/bus/uniphier-system-bus.c
+++ b/drivers/bus/uniphier-system-bus.c
@@ -256,10 +256,23 @@ static int uniphier_system_bus_probe(struct 
platform_device *pdev)
 
uniphier_system_bus_set_reg(priv);
 
+   platform_set_drvdata(pdev, priv);
+
/* Now, the bus is configured.  Populate platform_devices below it */
return of_platform_default_populate(dev->of_node, NULL, dev);
 }
 
+static int uniphier_system_bus_resume(struct device *dev)
+{
+   uniphier_system_bus_set_reg(dev_get_drvdata(dev));
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
+};
+
 static const struct of_device_id uniphier_system_bus_match[] = {
{ .compatible = "socionext,uniphier-system-bus" },
{ /* sentinel */ }
@@ -271,6 +284,7 @@ static struct platform_driver uniphier_system_bus_driver = {
.driver = {
.name   = "uniphier-system-bus",
.of_match_table = uniphier_system_bus_match,
+   .pm = &uniphier_system_bus_pm_ops,
},
 };
 module_platform_driver(uniphier_system_bus_driver);
-- 
2.7.4

Re: [PATCH 4/4] clk: sunxi-ng: Wait for lock when using fractional mode

[Chen-Yu Tsai]

On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
 wrote:
> Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
> set before returning. Because of that, unstable clock may be used.
>
> Add a wait for lock in the helper function.
>
> Signed-off-by: Jernej Skrabec 

Can you provide a Fixes: tag?

Otherwise this looks good.

linux-next: build warnings after merge of the staging tree

[Stephen Rothwell]

Hi Greg,

After merging the staging tree, today's linux-next build (x86_64
allmodconfig) produced this warning:

drivers/staging/media/atomisp/i2c/imx/imx.c:1087:12: warning: 
'imx_vcm_power_up' defined but not used [-Wunused-function]
 static int imx_vcm_power_up(struct v4l2_subdev *sd)
^
drivers/staging/media/atomisp/i2c/imx/imx.c:1095:12: warning: 
'imx_vcm_power_down' defined but not used [-Wunused-function]
 static int imx_vcm_power_down(struct v4l2_subdev *sd)
^
drivers/staging/media/atomisp/i2c/imx/imx.c:1103:12: warning: 'imx_vcm_init' 
defined but not used [-Wunused-function]
 static int imx_vcm_init(struct v4l2_subdev *sd)
^
drivers/staging/media/atomisp/i2c/imx/imx.c::12: warning: 'imx_t_focus_vcm' 
defined but not used [-Wunused-function]
 static int imx_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
^

Introduced by commit

  9a5a6911aa3f ("staging: imx: fix non-static declarations")

-- 
Cheers,
Stephen Rothwell

Re: [PATCH V9 1/3] powernv: powercap: Add support for powercap framework

[Cyril Bur]

On Mon, 2017-07-31 at 07:54 +0530, Shilpasri G Bhat wrote:
> Adds a generic powercap framework to change the system powercap
> inband through OPAL-OCC command/response interface.
> 
> Signed-off-by: Shilpasri G Bhat 
> ---
> Changes from V8:
> - Use __pa() while passing pointer in opal call
> - Use mutex_lock_interruptible()
> - Fix error codes returned to user
> - Allocate and add sysfs attributes in a single loop
> 
>  arch/powerpc/include/asm/opal-api.h|   5 +-
>  arch/powerpc/include/asm/opal.h|   4 +
>  arch/powerpc/platforms/powernv/Makefile|   2 +-
>  arch/powerpc/platforms/powernv/opal-powercap.c | 243 
> +
>  arch/powerpc/platforms/powernv/opal-wrappers.S |   2 +
>  arch/powerpc/platforms/powernv/opal.c  |   4 +
>  6 files changed, 258 insertions(+), 2 deletions(-)
>  create mode 100644 arch/powerpc/platforms/powernv/opal-powercap.c
> 
> diff --git a/arch/powerpc/include/asm/opal-api.h 
> b/arch/powerpc/include/asm/opal-api.h
> index 3130a73..c3e0c4a 100644
> --- a/arch/powerpc/include/asm/opal-api.h
> +++ b/arch/powerpc/include/asm/opal-api.h
> @@ -42,6 +42,7 @@
>  #define OPAL_I2C_STOP_ERR-24
>  #define OPAL_XIVE_PROVISIONING   -31
>  #define OPAL_XIVE_FREE_ACTIVE-32
> +#define OPAL_TIMEOUT -33
>  
>  /* API Tokens (in r0) */
>  #define OPAL_INVALID_CALL   -1
> @@ -190,7 +191,9 @@
>  #define OPAL_NPU_INIT_CONTEXT146
>  #define OPAL_NPU_DESTROY_CONTEXT 147
>  #define OPAL_NPU_MAP_LPAR148
> -#define OPAL_LAST148
> +#define OPAL_GET_POWERCAP152
> +#define OPAL_SET_POWERCAP153
> +#define OPAL_LAST153
>  
>  /* Device tree flags */
>  
> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
> index 588fb1c..ec2087c 100644
> --- a/arch/powerpc/include/asm/opal.h
> +++ b/arch/powerpc/include/asm/opal.h
> @@ -267,6 +267,8 @@ int64_t opal_xive_set_vp_info(uint64_t vp,
>  int64_t opal_xive_free_irq(uint32_t girq);
>  int64_t opal_xive_sync(uint32_t type, uint32_t id);
>  int64_t opal_xive_dump(uint32_t type, uint32_t id);
> +int opal_get_powercap(u32 handle, int token, u32 *pcap);
> +int opal_set_powercap(u32 handle, int token, u32 pcap);
>  
>  /* Internal functions */
>  extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
> @@ -345,6 +347,8 @@ static inline int opal_get_async_rc(struct opal_msg msg)
>  
>  void opal_wake_poller(void);
>  
> +void opal_powercap_init(void);
> +
>  #endif /* __ASSEMBLY__ */
>  
>  #endif /* _ASM_POWERPC_OPAL_H */
> diff --git a/arch/powerpc/platforms/powernv/Makefile 
> b/arch/powerpc/platforms/powernv/Makefile
> index b5d98cb..e79f806 100644
> --- a/arch/powerpc/platforms/powernv/Makefile
> +++ b/arch/powerpc/platforms/powernv/Makefile
> @@ -2,7 +2,7 @@ obj-y += setup.o opal-wrappers.o opal.o 
> opal-async.o idle.o
>  obj-y+= opal-rtc.o opal-nvram.o opal-lpc.o 
> opal-flash.o
>  obj-y+= rng.o opal-elog.o opal-dump.o 
> opal-sysparam.o opal-sensor.o
>  obj-y+= opal-msglog.o opal-hmi.o opal-power.o 
> opal-irqchip.o
> -obj-y+= opal-kmsg.o
> +obj-y+= opal-kmsg.o opal-powercap.o
>  
>  obj-$(CONFIG_SMP)+= smp.o subcore.o subcore-asm.o
>  obj-$(CONFIG_PCI)+= pci.o pci-ioda.o npu-dma.o
> diff --git a/arch/powerpc/platforms/powernv/opal-powercap.c 
> b/arch/powerpc/platforms/powernv/opal-powercap.c
> new file mode 100644
> index 000..9be5093
> --- /dev/null
> +++ b/arch/powerpc/platforms/powernv/opal-powercap.c
> @@ -0,0 +1,243 @@
> +/*
> + * PowerNV OPAL Powercap interface
> + *
> + * Copyright 2017 IBM Corp.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#define pr_fmt(fmt) "opal-powercap: " fmt
> +
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +DEFINE_MUTEX(powercap_mutex);
> +
> +static struct kobject *powercap_kobj;
> +
> +struct powercap_attr {
> + u32 handle;
> + struct kobj_attribute attr;
> +};
> +
> +static struct pcap {
> + struct attribute_group pg;
> + struct powercap_attr *pattrs;
> +} *pcaps;
> +
> +static ssize_t powercap_show(struct kobject *kobj, struct kobj_attribute 
> *attr,
> +  char *buf)
> +{
> + struct powercap_attr *pcap_attr = container_of(attr,
> + struct powercap_attr, attr);
> + struct opal_msg msg;
> + u32 pcap;
> + int ret, token;
> +
> + token = opal_async_get_token_interruptible();
> + if (token < 0) {
> + pr_devel("Failed to get

Re: [PATCH 1/4] clk: sunxi-ng: Fix fractional mode for N-M clocks

[Chen-Yu Tsai]

On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
 wrote:
> N-M factor clock driver is missing a call to ccu_frac_helper_enable()
> when fractional mode is used. Additionally, most SoCs require that M
> factor must be set to 0 when fractional mode is used.
>
> Without this patch, clock keeps the old value and clk_set_rate() returns
> without error.
>
> Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
> CC: Maxime Ripard 
> Signed-off-by: Jernej Skrabec 

Queued as a fix for 4.13.

ChenYu

[PATCH 1/2] i2c: uniphier: add PM suspend / resume support

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/busses/i2c-uniphier.c | 40 ++-
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-uniphier.c 
b/drivers/i2c/busses/i2c-uniphier.c
index 777c0fe93653..f41a09d9927a 100644
--- a/drivers/i2c/busses/i2c-uniphier.c
+++ b/drivers/i2c/busses/i2c-uniphier.c
@@ -53,6 +53,7 @@ struct uniphier_i2c_priv {
void __iomem *membase;
struct clk *clk;
unsigned int busy_cnt;
+   unsigned int clk_cycle;
 };
 
 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
@@ -316,13 +317,13 @@ static struct i2c_bus_recovery_info 
uniphier_i2c_bus_recovery_info = {
.unprepare_recovery = uniphier_i2c_unprepare_recovery,
 };
 
-static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv,
-u32 bus_speed, unsigned long clk_rate)
+static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
 {
+   unsigned int cyc = priv->clk_cycle;
+
uniphier_i2c_reset(priv, true);
 
-   writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed),
-  priv->membase + UNIPHIER_I2C_CLK);
+   writel((cyc / 2 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
 
uniphier_i2c_reset(priv, false);
 }
@@ -376,6 +377,7 @@ static int uniphier_i2c_probe(struct platform_device *pdev)
goto disable_clk;
}
 
+   priv->clk_cycle = clk_rate / bus_speed;
init_completion(&priv->comp);
priv->adap.owner = THIS_MODULE;
priv->adap.algo = &uniphier_i2c_algo;
@@ -386,7 +388,7 @@ static int uniphier_i2c_probe(struct platform_device *pdev)
i2c_set_adapdata(&priv->adap, priv);
platform_set_drvdata(pdev, priv);
 
-   uniphier_i2c_hw_init(priv, bus_speed, clk_rate);
+   uniphier_i2c_hw_init(priv);
 
ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
   priv);
@@ -413,6 +415,33 @@ static int uniphier_i2c_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static int uniphier_i2c_suspend(struct device *dev)
+{
+   struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
+
+   clk_disable_unprepare(priv->clk);
+
+   return 0;
+}
+
+static int uniphier_i2c_resume(struct device *dev)
+{
+   struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
+   int ret;
+
+   ret = clk_prepare_enable(priv->clk);
+   if (ret)
+   return ret;
+
+   uniphier_i2c_hw_init(priv);
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_i2c_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
+};
+
 static const struct of_device_id uniphier_i2c_match[] = {
{ .compatible = "socionext,uniphier-i2c" },
{ /* sentinel */ }
@@ -425,6 +454,7 @@ static struct platform_driver uniphier_i2c_drv = {
.driver = {
.name  = "uniphier-i2c",
.of_match_table = uniphier_i2c_match,
+   .pm = &uniphier_i2c_pm_ops,
},
 };
 module_platform_driver(uniphier_i2c_drv);
-- 
2.7.4

[PATCH 2/2] i2c: uniphier-f: add PM suspend / resume support

[Masahiro Yamada]

When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.

Signed-off-by: Masahiro Yamada 
---

 drivers/i2c/busses/i2c-uniphier-f.c | 46 +
 1 file changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-uniphier-f.c 
b/drivers/i2c/busses/i2c-uniphier-f.c
index beee31892295..74cf0752bbd0 100644
--- a/drivers/i2c/busses/i2c-uniphier-f.c
+++ b/drivers/i2c/busses/i2c-uniphier-f.c
@@ -97,6 +97,7 @@ struct uniphier_fi2c_priv {
int error;
unsigned int flags;
unsigned int busy_cnt;
+   unsigned int clk_cycle;
 };
 
 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
@@ -461,9 +462,9 @@ static struct i2c_bus_recovery_info 
uniphier_fi2c_bus_recovery_info = {
.unprepare_recovery = uniphier_fi2c_unprepare_recovery,
 };
 
-static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv,
- u32 bus_speed, unsigned long clk_rate)
+static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
 {
+   unsigned int cyc = priv->clk_cycle;
u32 tmp;
 
tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
@@ -472,12 +473,10 @@ static void uniphier_fi2c_hw_init(struct 
uniphier_fi2c_priv *priv,
 
uniphier_fi2c_reset(priv);
 
-   tmp = clk_rate / bus_speed;
-
-   writel(tmp, priv->membase + UNIPHIER_FI2C_CYC);
-   writel(tmp / 2, priv->membase + UNIPHIER_FI2C_LCTL);
-   writel(tmp / 2, priv->membase + UNIPHIER_FI2C_SSUT);
-   writel(tmp / 16, priv->membase + UNIPHIER_FI2C_DSUT);
+   writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
+   writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL);
+   writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
+   writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
 
uniphier_fi2c_prepare_operation(priv);
 }
@@ -531,6 +530,7 @@ static int uniphier_fi2c_probe(struct platform_device *pdev)
goto disable_clk;
}
 
+   priv->clk_cycle = clk_rate / bus_speed;
init_completion(&priv->comp);
priv->adap.owner = THIS_MODULE;
priv->adap.algo = &uniphier_fi2c_algo;
@@ -541,7 +541,7 @@ static int uniphier_fi2c_probe(struct platform_device *pdev)
i2c_set_adapdata(&priv->adap, priv);
platform_set_drvdata(pdev, priv);
 
-   uniphier_fi2c_hw_init(priv, bus_speed, clk_rate);
+   uniphier_fi2c_hw_init(priv);
 
ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
   pdev->name, priv);
@@ -568,6 +568,33 @@ static int uniphier_fi2c_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static int uniphier_fi2c_suspend(struct device *dev)
+{
+   struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
+
+   clk_disable_unprepare(priv->clk);
+
+   return 0;
+}
+
+static int uniphier_fi2c_resume(struct device *dev)
+{
+   struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
+   int ret;
+
+   ret = clk_prepare_enable(priv->clk);
+   if (ret)
+   return ret;
+
+   uniphier_fi2c_hw_init(priv);
+
+   return 0;
+}
+
+static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
+};
+
 static const struct of_device_id uniphier_fi2c_match[] = {
{ .compatible = "socionext,uniphier-fi2c" },
{ /* sentinel */ }
@@ -580,6 +607,7 @@ static struct platform_driver uniphier_fi2c_drv = {
.driver = {
.name  = "uniphier-fi2c",
.of_match_table = uniphier_fi2c_match,
+   .pm = &uniphier_fi2c_pm_ops,
},
 };
 module_platform_driver(uniphier_fi2c_drv);
-- 
2.7.4

EXT4-fs (sdc1): Delayed block allocation failed ...

[Enrico Mioso]

Hello. I am getting a single error message, similar to what happens in

https://patchwork.kernel.org/patch/9460075/

EXT4-fs (sdc1): Delayed block allocation failed for inode 27155438 at logical 
offset 6561 with max blocks 6 with error 121
EXT4-fs (sdc1): This should not happen!! Data will be lost

The /dev/sdc device in question is a Samsung Portable Disk, my complete 
lsusb for this device follows.

Currently running kernel is 4.12.3-1-ARCH, 32-bit machine.

Thanks very much to all guys,

Enrico

---lsusb---
Bus 001 Device 008: ID 04e8:61b3 Samsung Electronics Co., Ltd 
Device Descriptor:

  bLength18
  bDescriptorType 1
  bcdUSB   2.10
  bDeviceClass0
  bDeviceSubClass 0
  bDeviceProtocol 0
  bMaxPacketSize064
  idVendor   0x04e8 Samsung Electronics Co., Ltd
  idProduct  0x61b3
  bcdDevice   13.06
  iManufacturer   1 Samsung M3 Portable
  iProduct2 Samsung M3 Portable
  iSerial 3 C0747E011D68
  bNumConfigurations  1
  Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength   85
bNumInterfaces  1
bConfigurationValue 1
iConfiguration  0
bmAttributes 0xc0
  Self Powered
MaxPower   30mA
Interface Descriptor:
  bLength 9
  bDescriptorType 4
  bInterfaceNumber0
  bAlternateSetting   0
  bNumEndpoints   2
  bInterfaceClass 8 Mass Storage
  bInterfaceSubClass  6 SCSI
  bInterfaceProtocol 80 Bulk-Only
  iInterface  0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81  EP 1 IN
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02  EP 2 OUT
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
Interface Descriptor:
  bLength 9
  bDescriptorType 4
  bInterfaceNumber0
  bAlternateSetting   1
  bNumEndpoints   4
  bInterfaceClass 8 Mass Storage
  bInterfaceSubClass  6 SCSI
  bInterfaceProtocol 98
  iInterface  0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01  EP 1 OUT
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
Command pipe (0x01)
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82  EP 2 IN
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
Status pipe (0x02)
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x83  EP 3 IN
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
Data-in pipe (0x03)
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x04  EP 4 OUT
bmAttributes2
  Transfer TypeBulk
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0200  1x 512 bytes
bInterval   0
Data-out pipe (0x04)
Binary Object Store Descriptor:
  bLength 5
  bDescriptorType15
  wTotalLength   22
  bNumDeviceCaps  2
  USB 2.0 Extension Device Capability:
bLength 7
bDescriptorType16
bDevCapabilityType  2
bmAttributes   0x0f0e
  BESL Link Power Management (LPM) Supported
BESL value 3840 us
  SuperSpeed USB Device Capability:
bLength10
bDescriptorType16
bDevCapabilityType  3
bmAttributes 0x00
wSpeedsSupported   0x000e
  Device can operate 

Re: [PATCH v3] vfio: platform: reset: Add Broadcom FlexRM reset module

[Anup Patel]

Hi Eric,

Thanks for the review comments...

On Sat, Jul 29, 2017 at 6:31 PM, Auger Eric  wrote:
> Hi Anup,
> On 20/07/2017 13:17, Anup Patel wrote:
>> This patch adds Broadcom FlexRM low-level reset for
>> VFIO platform.
>>
>> It will do the following:
>> 1. Disable/Deactivate each FlexRM ring
>> 2. Flush each FlexRM ring
>>
>> The cleanup sequence for FlexRM rings is adapted from
>> Broadcom FlexRM mailbox driver.
>>
>> Signed-off-by: Anup Patel 
>> Reviewed-by: Oza Oza 
>> Reviewed-by: Scott Branden 
>> ---
>>  drivers/vfio/platform/reset/Kconfig|  9 +++
>>  drivers/vfio/platform/reset/Makefile   |  1 +
>>  .../vfio/platform/reset/vfio_platform_bcmflexrm.c  | 93 
>> ++
>>  3 files changed, 103 insertions(+)
>>  create mode 100644 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
>>
>> diff --git a/drivers/vfio/platform/reset/Kconfig 
>> b/drivers/vfio/platform/reset/Kconfig
>> index 705..8d8d226 100644
>> --- a/drivers/vfio/platform/reset/Kconfig
>> +++ b/drivers/vfio/platform/reset/Kconfig
>> @@ -13,3 +13,12 @@ config VFIO_PLATFORM_AMDXGBE_RESET
>> Enables the VFIO platform driver to handle reset for AMD XGBE
>>
>> If you don't know what to do here, say N.
>> +
>> +config VFIO_PLATFORM_BCMFLEXRM_RESET
>> + tristate "VFIO support for Broadcom FlexRM reset"
>> + depends on VFIO_PLATFORM
>> + depends on ARCH_BCM_IPROC || COMPILE_TEST
> depends on VFIO_PLATFORM && (ARCH_BCM_IPROC || COMPILE_TEST)?

OK, I will update this.

>> + help
>> +   Enables the VFIO platform driver to handle reset for Broadcom FlexRM
>> +
>> +   If you don't know what to do here, say N.
>> diff --git a/drivers/vfio/platform/reset/Makefile 
>> b/drivers/vfio/platform/reset/Makefile
>> index 93f4e23..8d9874b 100644
>> --- a/drivers/vfio/platform/reset/Makefile
>> +++ b/drivers/vfio/platform/reset/Makefile
>> @@ -5,3 +5,4 @@ ccflags-y += -Idrivers/vfio/platform
>>
>>  obj-$(CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET) += 
>> vfio-platform-calxedaxgmac.o
>>  obj-$(CONFIG_VFIO_PLATFORM_AMDXGBE_RESET) += vfio-platform-amdxgbe.o
>> +obj-$(CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET) += vfio_platform_bcmflexrm.o
>> diff --git a/drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c 
>> b/drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
>> new file mode 100644
>> index 000..a198196
>> --- /dev/null
>> +++ b/drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
>> @@ -0,0 +1,93 @@
>> +/*
>> + * Copyright (C) 2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see .
>> + */
>> +
>> +/*
>> + * This driver provides reset support for Broadcom FlexRM ring manager
>> + * to VFIO platform.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "vfio_platform_private.h"
>> +
>> +/* FlexRM configuration */
>> +#define RING_REGS_SIZE   0x1
>> +#define RING_VER_MAGIC   0x76303031
>> +
>> +/* Per-Ring register offsets */
>> +#define RING_VER 0x000
>> +#define RING_CONTROL 0x034
>> +#define RING_FLUSH_DONE  0x038
>> +
>> +/* Register RING_CONTROL fields */
>> +#define CONTROL_FLUSH_SHIFT  5
>> +#define CONTROL_ACTIVE_SHIFT 4
> not used

OK, I will remove this.

>> +
>> +/* Register RING_FLUSH_DONE fields */
>> +#define FLUSH_DONE_MASK  0x1
>> +
>> +static void vfio_platform_bcmflexrm_shutdown(void __iomem *ring)
>> +{
>> + unsigned int timeout;
>> +
>> + /* Disable/inactivate ring */
>> + writel_relaxed(0x0, ring + RING_CONTROL);
>> +
>> + /* Flush ring with timeout of 1s */
>> + timeout = 1000;
>> + writel_relaxed(BIT(CONTROL_FLUSH_SHIFT), ring + RING_CONTROL);
>> + do {
>> + if (readl_relaxed(ring + RING_FLUSH_DONE) & FLUSH_DONE_MASK)
>> + break;
>> + mdelay(1);
>> + } while (timeout--);
>> +
>> + if (!timeout)
>> + pr_warn("VFIO FlexRM shutdown timedout\n");
> s/timedout/timeout

OK, will fix this.

>
> vfio_platform_bcmflexrm_shutdown may also return an error that would be
> propagated to the called:
> vfio_platform_release() would then emit a dev_warn + WARN_ON. your
> choice - I know thi

Re: FSGSBASE ABI considerations

[Linus Torvalds]

On Sun, Jul 30, 2017 at 8:05 PM, Andy Lutomirski  wrote:
>
> This means that, when gdb saves away a regset and reloads it using
> PTRACE_SETREGS or similar, the effect is to load gs_base and then load
> gs.  If gs != 0, this will blow away gs_base.  Without FSGSBASE, this
> doesn't matter so much.  With FSGSBASE, it means that using gdb to do,
> say, 'print func()' may corrupt gsbase.
>
> What, if anything, should we do about this?  One option would be to
> make gs_base be accurate all the time (it currently isn't) and teach
> PTRACE_SETREGS to restore in the opposite order despite the struct
> layout.

I do not think that ordering should ever matter. If it does, it means
that you've designed something. We already screwed that up with the
msr interface, can we try to not do it again?

Could we perhaps do something like:

 - every process starts out with CR4.FSGSBASE cleared

 - if we get an #UD due to the process using the {rd|wr}{gs|fs}base
instructions,  we enable FSGSBASE and mark the process as using those
instructions.

 - once a process is marked as FSGSBASE, the kernel prioritizes
FSGSBASE. We'll still save/restore the selector too, but every time we
restore the selector, we will first do a rd*base, and then do a
wr*base afterwards

IOW, the "selector" ends up being meaningless after people have used
fsgsbase. It is saved and restored as a _value_, but it has no effect
what-so-ever on the actual base pointer.

Yes, it's modal, but at least you don't end up in some situation where
it matters whether you write the selector first or not.

Hmm?

 Linus

[PATCH v2] soc: ti: knav: Add a NULL pointer check for kdev in knav_pool_create

[Keerthy]

knav_pool_create is an exported function. In the event of a call
before knav_queue_probe, we encounter a NULL pointer dereference
in the following line. Hence return -EPROBE_DEFER to the caller till
the kdev pointer is non-NULL.

Signed-off-by: Keerthy 
---

Changes in v2:

  * Fixed returning an int to returning pointer.

 drivers/soc/ti/knav_qmss_queue.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c
index 279e7c5..d91626b 100644
--- a/drivers/soc/ti/knav_qmss_queue.c
+++ b/drivers/soc/ti/knav_qmss_queue.c
@@ -745,6 +745,9 @@ void *knav_pool_create(const char *name,
bool slot_found;
int ret;
 
+   if (!kdev)
+   return ERR_PTR(-EPROBE_DEFER);
+
if (!kdev->dev)
return ERR_PTR(-ENODEV);
 
-- 
1.9.1

Re: [greybus-dev] [PATCH 10/11] greybus: usb: constify hc_driver structures

[Viresh Kumar]

On 28-07-17, 22:41, Julia Lawall wrote:
> The hc_driver structure is only passed as the first argument to
> usb_create_hcd, which is declared as const.  Thus the hc_driver structure
> itself can be const.
> 
> Done with the help of Coccinelle.
> 
> Signed-off-by: Julia Lawall 
> 
> ---
>  drivers/staging/greybus/usb.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/staging/greybus/usb.c b/drivers/staging/greybus/usb.c
> index ccadda0..f93a76d 100644
> --- a/drivers/staging/greybus/usb.c
> +++ b/drivers/staging/greybus/usb.c
> @@ -139,7 +139,7 @@ static int hub_control(struct usb_hcd *hcd, u16 typeReq, 
> u16 wValue, u16 wIndex,
>   return ret;
>  }
>  
> -static struct hc_driver usb_gb_hc_driver = {
> +static const struct hc_driver usb_gb_hc_driver = {
>   .description = "greybus-hcd",
>   .product_desc = "Greybus USB Host Controller",
>   .hcd_priv_size = sizeof(struct gb_usb_device),

Reviewed-by: Viresh Kumar 

-- 
viresh

[PATCH] mm: don't zero ballooned pages

[Wei Wang]

Ballooned pages will be marked as MADV_DONTNEED by the hypervisor and
shouldn't be given to the host ksmd to scan. Therefore, it is not
necessary to zero ballooned pages, which is very time consuming when
the page amount is large. The ongoing fast balloon tests show that the
time to balloon 7G pages is increased from ~491ms to 2.8 seconds with
__GFP_ZERO added. So, this patch removes the flag.

Signed-off-by: Wei Wang 
---
 mm/balloon_compaction.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mm/balloon_compaction.c b/mm/balloon_compaction.c
index 9075aa5..b06d9fe 100644
--- a/mm/balloon_compaction.c
+++ b/mm/balloon_compaction.c
@@ -24,7 +24,7 @@ struct page *balloon_page_enqueue(struct balloon_dev_info 
*b_dev_info)
 {
unsigned long flags;
struct page *page = alloc_page(balloon_mapping_gfp_mask() |
-   __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_ZERO);
+  __GFP_NOMEMALLOC | __GFP_NORETRY);
if (!page)
return NULL;
 
-- 
2.7.4

Re: [PATCH] mfd: lp87565: Convert to use devm_mfd_add_devices

[Keerthy]

On Sunday 30 July 2017 04:28 PM, Axel Lin wrote:
> This fixes missing mfd_remove_devices() call when unload the module.

Reviewed-by: Keerthy 

> 
> Signed-off-by: Axel Lin 
> ---
>  drivers/mfd/lp87565.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mfd/lp87565.c b/drivers/mfd/lp87565.c
> index 340ad0c..32d2a07 100644
> --- a/drivers/mfd/lp87565.c
> +++ b/drivers/mfd/lp87565.c
> @@ -73,10 +73,9 @@ static int lp87565_probe(struct i2c_client *client,
>  
>   i2c_set_clientdata(client, lp87565);
>  
> - ret = mfd_add_devices(lp87565->dev, PLATFORM_DEVID_AUTO, lp87565_cells,
> -   ARRAY_SIZE(lp87565_cells), NULL, 0, NULL);
> -
> - return ret;
> + return devm_mfd_add_devices(lp87565->dev, PLATFORM_DEVID_AUTO,
> + lp87565_cells, ARRAY_SIZE(lp87565_cells),
> + NULL, 0, NULL);
>  }
>  
>  static const struct i2c_device_id lp87565_id_table[] = {
> 

Re: [PATCH V8 1/6] PM / Domains: Add support to select performance-state of domains

[Viresh Kumar]

On 29-07-17, 10:24, Ulf Hansson wrote:
> Let's invent a new genpd flag, GENPD_FLAG_PERF_STATE!
> 
> The creator of the genpd then needs to set this before calling
> pm_genpd_init(). Similar as we are dealing with GENPD_FLAG_PM_CLK.
> 
> The requirement for GENPD_FLAG_PERF_STATES, is to have the
> ->get_performance_state() assigned. This shall be verified during
> pm_genpd_init().
> 
> The pm_genpd_has_performance_state() then only need to return true, in
> cases the device's genpd has GENPD_FLAG_PERF_STATE set - else false.
> 
> Regarding ->set_performance_state(), let's just make it optional - and
> when trying to set a new performance state, just walk the genpd
> hierarchy, from bottom to up, then invoke the callback when it's
> assigned.

Sounds good.

-- 
viresh

Re: [PATCH v3] cpuset: fix a deadlock due to incomplete patching of cpusets_enabled()

[Dima Zavin]

On Sun, Jul 30, 2017 at 9:01 PM, Dima Zavin  wrote:
> In codepaths that use the begin/retry interface for reading
> mems_allowed_seq with irqs disabled, there exists a race condition that
> stalls the patch process after only modifying a subset of the
> static_branch call sites.
>
> This problem manifested itself as a dead lock in the slub
> allocator, inside get_any_partial. The loop reads
> mems_allowed_seq value (via read_mems_allowed_begin),
> performs the defrag operation, and then verifies the consistency
> of mem_allowed via the read_mems_allowed_retry and the cookie
> returned by xxx_begin. The issue here is that both begin and retry
> first check if cpusets are enabled via cpusets_enabled() static branch.
> This branch can be rewritted dynamically (via cpuset_inc) if a new
> cpuset is created. The x86 jump label code fully synchronizes across
> all CPUs for every entry it rewrites. If it rewrites only one of the
> callsites (specifically the one in read_mems_allowed_retry) and then
> waits for the smp_call_function(do_sync_core) to complete while a CPU is
> inside the begin/retry section with IRQs off and the mems_allowed value
> is changed, we can hang. This is because begin() will always return 0
> (since it wasn't patched yet) while retry() will test the 0 against
> the actual value of the seq counter.
>
> The fix is to use two different static keys: one for begin
> (pre_enable_key) and one for retry (enable_key). In cpuset_inc(), we
> first bump the pre_enable key to ensure that cpuset_mems_allowed_begin()
> always return a valid seqcount if are enabling cpusets. Similarly,
> when disabling cpusets via cpuset_dec(), we first ensure that callers
> of cpuset_mems_allowed_retry() will start ignoring the seqcount
> value before we let cpuset_mems_allowed_begin() return 0.
>
> The relevant stack traces of the two stuck threads:
>
>   CPU: 1 PID: 1415 Comm: mkdir Tainted: G L  4.9.36-00104-g540c51286237 #4
>   Hardware name: Default string Default string/Hardware, BIOS 
> 4.29.1-20170526215256 05/26/2017
>   task: 8817f9c28000 task.stack: c9000ffa4000
>   RIP: smp_call_function_many+0x1f9/0x260
>   Call Trace:
> ? setup_data_read+0xa0/0xa0
> ? ___slab_alloc+0x28b/0x5a0
> smp_call_function+0x3b/0x70
> ? setup_data_read+0xa0/0xa0
> on_each_cpu+0x2f/0x90
> ? ___slab_alloc+0x28a/0x5a0
> ? ___slab_alloc+0x28b/0x5a0
> text_poke_bp+0x87/0xd0
> ? ___slab_alloc+0x28a/0x5a0
> arch_jump_label_transform+0x93/0x100
> __jump_label_update+0x77/0x90
> jump_label_update+0xaa/0xc0
> static_key_slow_inc+0x9e/0xb0
> cpuset_css_online+0x70/0x2e0
> online_css+0x2c/0xa0
> cgroup_apply_control_enable+0x27f/0x3d0
> cgroup_mkdir+0x2b7/0x420
> kernfs_iop_mkdir+0x5a/0x80
> vfs_mkdir+0xf6/0x1a0
> SyS_mkdir+0xb7/0xe0
> entry_SYSCALL_64_fastpath+0x18/0xad
>
>   ...
>
>   CPU: 2 PID: 1 Comm: init Tainted: G L  4.9.36-00104-g540c51286237 #4
>   Hardware name: Default string Default string/Hardware, BIOS 
> 4.29.1-20170526215256 05/26/2017
>   task: 8818087c task.stack: c903
>   RIP: int3+0x39/0x70
>   Call Trace:
> <#DB> ? ___slab_alloc+0x28b/0x5a0
>  ? copy_process.part.40+0xf7/0x1de0
> ? __slab_alloc.isra.80+0x54/0x90
> ? copy_process.part.40+0xf7/0x1de0
> ? copy_process.part.40+0xf7/0x1de0
> ? kmem_cache_alloc_node+0x8a/0x280
> ? copy_process.part.40+0xf7/0x1de0
> ? _do_fork+0xe7/0x6c0
> ? _raw_spin_unlock_irq+0x2d/0x60
> ? trace_hardirqs_on_caller+0x136/0x1d0
> ? entry_SYSCALL_64_fastpath+0x5/0xad
> ? do_syscall_64+0x27/0x350
> ? SyS_clone+0x19/0x20
> ? do_syscall_64+0x60/0x350
> ? entry_SYSCALL64_slow_path+0x25/0x25
>
> Reported-by: Cliff Spradlin 
> Signed-off-by: Dima Zavin 
> ---
>
> v3:
>  - Changed the implementation based on Peter Zijlstra's suggestion. Now
>using two keys for begin/retry instead of hacking the state into the
>cookie.
>  - Rebased and tested on top of v4.13-rc3.
>
> v4:

Doh, latest patch is v3, I obviously meant v2 here instead of v4. Sigh. Sorry.

--Dima

>  - Moved the cached cpusets_enabled() state into the cookie, turned
>the cookie into a struct and updated all the other call sites.
>  - Applied on top of v4.12 since one of the callers in page_alloc.c changed.
>Still only tested on v4.9.36 and compile tested against v4.12.
>
>  include/linux/cpuset.h | 19 +--
>  kernel/cgroup/cpuset.c |  1 +
>  2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
> index 119a3f9604b0..e5a684c04c70 100644
> --- a/include/linux/cpuset.h
> +++ b/include/linux/cpuset.h
> @@ -18,6 +18,19 @@
>
>  #ifdef CONFIG_CPUSETS
>
> +/*
> + * Static branch rewrites can happen in an arbitrary order for a given
> + * key. In code paths where we need to loop with read_mems_allowed_begin() 
> and
> + * read_mems_allowed_retry() to get a consistent view of mems_allowed, we 
>

[PATCH v3] cpuset: fix a deadlock due to incomplete patching of cpusets_enabled()

[Dima Zavin]

In codepaths that use the begin/retry interface for reading
mems_allowed_seq with irqs disabled, there exists a race condition that
stalls the patch process after only modifying a subset of the
static_branch call sites.

This problem manifested itself as a dead lock in the slub
allocator, inside get_any_partial. The loop reads
mems_allowed_seq value (via read_mems_allowed_begin),
performs the defrag operation, and then verifies the consistency
of mem_allowed via the read_mems_allowed_retry and the cookie
returned by xxx_begin. The issue here is that both begin and retry
first check if cpusets are enabled via cpusets_enabled() static branch.
This branch can be rewritted dynamically (via cpuset_inc) if a new
cpuset is created. The x86 jump label code fully synchronizes across
all CPUs for every entry it rewrites. If it rewrites only one of the
callsites (specifically the one in read_mems_allowed_retry) and then
waits for the smp_call_function(do_sync_core) to complete while a CPU is
inside the begin/retry section with IRQs off and the mems_allowed value
is changed, we can hang. This is because begin() will always return 0
(since it wasn't patched yet) while retry() will test the 0 against
the actual value of the seq counter.

The fix is to use two different static keys: one for begin
(pre_enable_key) and one for retry (enable_key). In cpuset_inc(), we
first bump the pre_enable key to ensure that cpuset_mems_allowed_begin()
always return a valid seqcount if are enabling cpusets. Similarly,
when disabling cpusets via cpuset_dec(), we first ensure that callers
of cpuset_mems_allowed_retry() will start ignoring the seqcount
value before we let cpuset_mems_allowed_begin() return 0.

The relevant stack traces of the two stuck threads:

  CPU: 1 PID: 1415 Comm: mkdir Tainted: G L  4.9.36-00104-g540c51286237 #4
  Hardware name: Default string Default string/Hardware, BIOS 
4.29.1-20170526215256 05/26/2017
  task: 8817f9c28000 task.stack: c9000ffa4000
  RIP: smp_call_function_many+0x1f9/0x260
  Call Trace:
? setup_data_read+0xa0/0xa0
? ___slab_alloc+0x28b/0x5a0
smp_call_function+0x3b/0x70
? setup_data_read+0xa0/0xa0
on_each_cpu+0x2f/0x90
? ___slab_alloc+0x28a/0x5a0
? ___slab_alloc+0x28b/0x5a0
text_poke_bp+0x87/0xd0
? ___slab_alloc+0x28a/0x5a0
arch_jump_label_transform+0x93/0x100
__jump_label_update+0x77/0x90
jump_label_update+0xaa/0xc0
static_key_slow_inc+0x9e/0xb0
cpuset_css_online+0x70/0x2e0
online_css+0x2c/0xa0
cgroup_apply_control_enable+0x27f/0x3d0
cgroup_mkdir+0x2b7/0x420
kernfs_iop_mkdir+0x5a/0x80
vfs_mkdir+0xf6/0x1a0
SyS_mkdir+0xb7/0xe0
entry_SYSCALL_64_fastpath+0x18/0xad

  ...

  CPU: 2 PID: 1 Comm: init Tainted: G L  4.9.36-00104-g540c51286237 #4
  Hardware name: Default string Default string/Hardware, BIOS 
4.29.1-20170526215256 05/26/2017
  task: 8818087c task.stack: c903
  RIP: int3+0x39/0x70
  Call Trace:
<#DB> ? ___slab_alloc+0x28b/0x5a0
 ? copy_process.part.40+0xf7/0x1de0
? __slab_alloc.isra.80+0x54/0x90
? copy_process.part.40+0xf7/0x1de0
? copy_process.part.40+0xf7/0x1de0
? kmem_cache_alloc_node+0x8a/0x280
? copy_process.part.40+0xf7/0x1de0
? _do_fork+0xe7/0x6c0
? _raw_spin_unlock_irq+0x2d/0x60
? trace_hardirqs_on_caller+0x136/0x1d0
? entry_SYSCALL_64_fastpath+0x5/0xad
? do_syscall_64+0x27/0x350
? SyS_clone+0x19/0x20
? do_syscall_64+0x60/0x350
? entry_SYSCALL64_slow_path+0x25/0x25

Reported-by: Cliff Spradlin 
Signed-off-by: Dima Zavin 
---

v3:
 - Changed the implementation based on Peter Zijlstra's suggestion. Now
   using two keys for begin/retry instead of hacking the state into the
   cookie.
 - Rebased and tested on top of v4.13-rc3.

v4:
 - Moved the cached cpusets_enabled() state into the cookie, turned
   the cookie into a struct and updated all the other call sites.
 - Applied on top of v4.12 since one of the callers in page_alloc.c changed.
   Still only tested on v4.9.36 and compile tested against v4.12.

 include/linux/cpuset.h | 19 +--
 kernel/cgroup/cpuset.c |  1 +
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index 119a3f9604b0..e5a684c04c70 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -18,6 +18,19 @@
 
 #ifdef CONFIG_CPUSETS
 
+/*
+ * Static branch rewrites can happen in an arbitrary order for a given
+ * key. In code paths where we need to loop with read_mems_allowed_begin() and
+ * read_mems_allowed_retry() to get a consistent view of mems_allowed, we need
+ * to ensure that begin() always gets rewritten before retry() in the
+ * disabled -> enabled transition. If not, then if local irqs are disabled
+ * around the loop, we can deadlock since retry() would always be
+ * comparing the latest value of the mems_allowed seqcount against 0 as
+ * begin() still would see cpusets_enabled() as false. The enabled -> 

Re: [PATCH V5 2/2] cpufreq: Process remote callbacks from any CPU if the platform permits

[Viresh Kumar]

On 28-07-17, 20:43, Joel Fernandes wrote:
> On Thu, Jul 27, 2017 at 11:46 PM, Viresh Kumar  
> wrote:
> > On many platforms, CPUs can do DVFS across cpufreq policies. i.e CPU
> > from policy-A can change frequency of CPUs belonging to policy-B.
> >
> > This is quite common in case of ARM platforms where we don't
> > configure any per-cpu register.
> >
> > Add a flag to identify such platforms and update
> > cpufreq_can_do_remote_dvfs() to allow remote callbacks if this flag is
> > set.
> >
> > Also enable the flag for cpufreq-dt driver which is used only on ARM
> > platforms currently.
> >
> > Signed-off-by: Viresh Kumar 
> > ---
> >  drivers/cpufreq/cpufreq-dt.c |  1 +
> >  include/linux/cpufreq.h  | 18 --
> >  2 files changed, 17 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
> > index fef3c2160691..d83ab94d041a 100644
> > --- a/drivers/cpufreq/cpufreq-dt.c
> > +++ b/drivers/cpufreq/cpufreq-dt.c
> > @@ -274,6 +274,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> > transition_latency = CPUFREQ_ETERNAL;
> >
> > policy->cpuinfo.transition_latency = transition_latency;
> > +   policy->dvfs_possible_from_any_cpu = true;
> >
> 
> Are there also ARM hardware that may not support it?

I don't think so. ARM never had any per-cpu register interface which may break
due to this.

> If yes, wouldn't
> a saner thing to do be to keep default as false and read the property
> from DT for hardware that does support it and then set to true?

I would do it if required, but for now I don't think there are any such users of
cpufreq-dt.

-- 
viresh

Re: [Eas-dev] [PATCH V3 1/3] sched: cpufreq: Allow remote cpufreq callbacks

[Viresh Kumar]

On 28-07-17, 14:05, Saravana Kannan wrote:
> 1. I'm not saying that. I'm saying assuming CPUs can change the freq only on
> behalf of all the CPUs in the same policy is wrong. Again, the scheduler or
> governor shouldn't even be making any of that assumption. That's a CPUfreq
> driver problem.
> 
> 2. No, that is not the basis of the entire cpufreq core design. None of the
> existing CPUfreq code has any assumptions that only CPUs in a policy can
> change their frequency. It doesn't break in any way in system where any CPU
> can change any other CPU's frequency -- all Qualcomm chips are like that.
> It's only the recent scheduler notifier changes that are adding this
> additional limitation and breaking stuff for systems where any CPU can
> change any other CPU's frequency.

Can you please have a look at V5 and see f the solution proposed there would be
fine ?

-- 
viresh

Re: [PATCH 0/6] Add DSP DT nodes on Keystone platforms

[santosh.shilim...@oracle.com]

On 7/28/17 4:19 PM, Suman Anna wrote:

Hi Santosh,

The following series adds the DT nodes for the DSP devices present
on the Keystone2 66AK2H/K, 66AK2L and 66AK2E SoCs. They are disabled
in the base dts files, and enabled in the corresponding board files
alongside an added common reserved CMA pool that is used by all the
DSP devices. The bindings and driver support were added to mainline
in 4.13-rc1, and this series adds the dt portions. Nodes are added
as per bindings in
Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt

Validation done on K2HK EVM, K2L EVM and K2E EVM. Supported features
include basic load/boot (tested with rpmsg_client_sample) and Error
Recovery (after reverting a patch merged in 4.13-rc1 that has caused
a kernel crash, see [1]). Functionality with CMA nodes from HighMem
require a patch in the virtio_rpmsg_bus core [2].


Applied !!

Regards,
Santosh

linux-next: manual merge of the rcu tree with the tip tree

[Stephen Rothwell]

Hi Paul,

Today's linux-next merge of the rcu tree got a conflict in:

  arch/x86/mm/tlb.c

between commit:

  94b1b03b519b ("x86/mm: Rework lazy TLB mode and TLB freshness tracking")

from the tip tree and commit:

  d7713e8f8b23 ("membarrier: Expedited private command")

from the rcu tree.

I fixed it up (the former removed the comment and the load_cr3(), so I
just dropped the commend change in the latter) and can carry the fix as
necessary. This is now fixed as far as linux-next is concerned, but any
non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.



-- 
Cheers,
Stephen Rothwell

[PATCH v7 1/3] mmc: dw_mmc-k3: add sd support for hi3660

[Li Wei]

Add sd card support for hi3660 soc

Signed-off-by: Li Wei 
Signed-off-by: Chen Jun 

Major changes in v3:
 - solve review comments from Heiner Kallweit.
   *use the GENMASK and FIELD_PREP macros replace the bit shift operation.
   *use usleep_range() replace udelay() and mdelay().

Major changes in v4:
 - solve review comments from Jaehoon Chung.
   *move common register for dwmmc controller to dwmmc header file.
   *modify definitions type of some register variables.
   *get rid of the magic numbers.

Major changes in v5:
 - further improve coding style.

Major changes in v6:
 - solve review comments for Jaehoon Chung.
   *modify dw_mci_hi3660_set_ios() to static.
   *fix the comment style.

Major changes in v7:
 - solve review comments for John Stultz.
   *remove reset code in dw_mmc-k3.c,use reset in core mmc.
---
 drivers/mmc/host/dw_mmc-k3.c | 311 +++
 drivers/mmc/host/dw_mmc.h|   2 +
 2 files changed, 313 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index e38fb0020bb1..efe18bf445ff 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -8,6 +8,8 @@
  * (at your option) any later version.
  */
 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -28,7 +30,38 @@
 #define AO_SCTRL_SEL18 BIT(10)
 #define AO_SCTRL_CTRL3 0x40C
 
+#define DWMMC_SDIO_ID 2
+
+#define SOC_SCTRL_SCPERCTRL5(0x314)
+#define SDCARD_IO_SEL18 BIT(2)
+
+#define SDCARD_RD_THRESHOLD  (512)
+
+#define GENCLK_DIV (7)
+
+#define GPIO_CLK_ENABLE   BIT(16)
+#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
+#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
+#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
+#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
+#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
+
+#define TIMING_MODE 3
+#define TIMING_CFG_NUM 10
+
+#define PULL_DOWN BIT(1)
+#define PULL_UP   BIT(0)
+
+#define NUM_PHASES (40)
+
+#define ENABLE_SHIFT_MIN_SMPL (4)
+#define ENABLE_SHIFT_MAX_SMPL (12)
+#define USE_DLY_MIN_SMPL (11)
+#define USE_DLY_MAX_SMPL (14)
+
 struct k3_priv {
+   int ctrl_id;
+   u32 cur_speed;
struct regmap   *reg;
 };
 
@@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
0
 };
 
+struct hs_timing {
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 smpl_phase_max;
+   u32 smpl_phase_min;
+};
+
+struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
+   { /* reserved */ },
+   { /* SD */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {6, 0,  4,  4,},  /* 1: MMC_HS */
+   {6, 0,  3,  3,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  2,  2,},  /* 4: SDR25 */
+   {4, 0, 11,  0,},  /* 5: SDR50 */
+   {6, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   },
+   { /* SDIO */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {0},  /* 1: MMC_HS */
+   {6, 0, 15, 15,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  0,  0,},  /* 4: SDR25 */
+   {4, 0, 12,  0,},  /* 5: SDR50 */
+   {5, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   }
+};
+
 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 {
int ret;
@@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
if (IS_ERR(priv->reg))
priv->reg = NULL;
 
+   priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
+   if (priv->ctrl_id < 0)
+   priv->ctrl_id = 0;
+
host->priv = priv;
return 0;
 }
@@ -144,7 +216,246 @@ static const struct dw_mci_drv_data hi6220_data = {
.execute_tuning = dw_mci_hi6220_execute_tuning,
 };
 
+static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
+int smpl_phase)
+{
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 use_smpl_dly = 0;
+   u32 enable_shift = 0;
+   u32 reg_value;
+   int ctrl_id;
+   struct k3_priv *priv;
+
+   priv = host->priv;
+   ctrl_id = priv->ctrl_id;
+
+   drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
+   smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
+   if (smpl_phase == -1)
+   smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
+hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
+
+   switch (timing) {
+   case MMC_TIMING_UHS_SDR104:
+   if (smpl_phase >= USE_DLY_MIN_SMPL &&

[PATCH v7 2/3] mmc: dw_mmc: move controller reset before driver init op

[Li Wei]

This commit modifies dw_mci_probe(), it moves reset assertion before
drv_data->init(host)

Some driver needs to access controller registers in its .init() ops. So,
in order to make such access safe, we should do controller reset before
.init() being called.

Signed-off-by: Wei Li 
Signed-off-by: Guodong Xu 
Signed-off-by: Chen Jun 
---
 drivers/mmc/host/dw_mmc.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a9dfb26972f2..f2fa928e1a12 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -3067,6 +3067,12 @@ int dw_mci_probe(struct dw_mci *host)
goto err_clk_ciu;
}
 
+   if (!IS_ERR(host->pdata->rstc)) {
+   reset_control_assert(host->pdata->rstc);
+   usleep_range(10, 50);
+   reset_control_deassert(host->pdata->rstc);
+   }
+
if (drv_data && drv_data->init) {
ret = drv_data->init(host);
if (ret) {
@@ -3076,12 +3082,6 @@ int dw_mci_probe(struct dw_mci *host)
}
}
 
-   if (!IS_ERR(host->pdata->rstc)) {
-   reset_control_assert(host->pdata->rstc);
-   usleep_range(10, 50);
-   reset_control_deassert(host->pdata->rstc);
-   }
-
setup_timer(&host->cmd11_timer,
dw_mci_cmd11_timer, (unsigned long)host);
 
-- 
2.11.0

Re: [PATCH v2 1/3] media: V3s: Add support for Allwinner CSI.

[Yong]

Hi,

On Fri, 28 Jul 2017 18:02:33 +0200
Maxime Ripard  wrote:

> Hi, 
> 
> Thanks for the second iteration!
> 
> On Thu, Jul 27, 2017 at 01:01:35PM +0800, Yong Deng wrote:
> > Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> > and CSI1 is used for parallel interface. This is not documented in
> > datasheet but by testing and guess.
> > 
> > This patch implement a v4l2 framework driver for it.
> > 
> > Currently, the driver only support the parallel interface. MIPI-CSI2,
> > ISP's support are not included in this patch.
> > 
> > Signed-off-by: Yong Deng 
> 
> There's a significant amount of checkpatch warnings (and quite
> important checks) in your driver. You should fix everything checkpatch
> --strict reports.

OK. I will check and fix.

> 
> > ---
> >  drivers/media/platform/Kconfig   |   1 +
> >  drivers/media/platform/Makefile  |   2 +
> >  drivers/media/platform/sun6i-csi/Kconfig |   9 +
> >  drivers/media/platform/sun6i-csi/Makefile|   3 +
> >  drivers/media/platform/sun6i-csi/sun6i_csi.c | 545 +++
> >  drivers/media/platform/sun6i-csi/sun6i_csi.h | 203 ++
> >  drivers/media/platform/sun6i-csi/sun6i_csi_v3s.c | 827 
> > +++
> >  drivers/media/platform/sun6i-csi/sun6i_csi_v3s.h | 206 ++
> >  drivers/media/platform/sun6i-csi/sun6i_video.c   | 663 ++
> >  drivers/media/platform/sun6i-csi/sun6i_video.h   |  61 ++
> >  10 files changed, 2520 insertions(+)
> >  create mode 100644 drivers/media/platform/sun6i-csi/Kconfig
> >  create mode 100644 drivers/media/platform/sun6i-csi/Makefile
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_csi.c
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_csi.h
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_csi_v3s.c
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_csi_v3s.h
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_video.c
> >  create mode 100644 drivers/media/platform/sun6i-csi/sun6i_video.h
> > 
> > diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> > index 0c741d1..8371a87 100644
> > --- a/drivers/media/platform/Kconfig
> > +++ b/drivers/media/platform/Kconfig
> > @@ -143,6 +143,7 @@ source "drivers/media/platform/am437x/Kconfig"
> >  source "drivers/media/platform/xilinx/Kconfig"
> >  source "drivers/media/platform/rcar-vin/Kconfig"
> >  source "drivers/media/platform/atmel/Kconfig"
> > +source "drivers/media/platform/sun6i-csi/Kconfig"
> 
> We're going to have several different drivers in v4l eventually, so I
> guess it would make sense to move to a directory of our own.

Like this?
drivers/media/platform/sunxi/sun6i-csi

> 
> > +   dev_dbg(csi->dev, "creating links for entity %s\n", local->name);
> > +
> > +   while (1) {
> > +   /* Get the next endpoint and parse its link. */
> > +   next = of_graph_get_next_endpoint(entity->node, ep);
> > +   if (next == NULL)
> > +   break;
> > +
> > +   of_node_put(ep);
> > +   ep = next;
> > +
> > +   dev_dbg(csi->dev, "processing endpoint %s\n", ep->full_name);
> > +
> > +   ret = v4l2_fwnode_parse_link(of_fwnode_handle(ep), &link);
> > +   if (ret < 0) {
> > +   dev_err(csi->dev, "failed to parse link for %s\n",
> > +   ep->full_name);
> > +   continue;
> > +   }
> > +
> > +   /* Skip sink ports, they will be processed from the other end of
> > +* the link.
> > +*/
> > +   if (link.local_port >= local->num_pads) {
> > +   dev_err(csi->dev, "invalid port number %u on %s\n",
> > +   link.local_port,
> > +   to_of_node(link.local_node)->full_name);
> > +   v4l2_fwnode_put_link(&link);
> > +   ret = -EINVAL;
> > +   break;
> > +   }
> > +
> > +   local_pad = &local->pads[link.local_port];
> > +
> > +   if (local_pad->flags & MEDIA_PAD_FL_SINK) {
> > +   dev_dbg(csi->dev, "skipping sink port %s:%u\n",
> > +   to_of_node(link.local_node)->full_name,
> > +   link.local_port);
> > +   v4l2_fwnode_put_link(&link);
> > +   continue;
> > +   }
> > +
> > +   /* Skip video node, they will be processed separately. */
> > +   if (link.remote_node == of_fwnode_handle(csi->dev->of_node)) {
> > +   dev_dbg(csi->dev, "skipping CSI port %s:%u\n",
> > +   to_of_node(link.local_node)->full_name,
> > +   link.local_port);
> > +   v4l2_fwnode_put_link(&link);
> > +   continue;
> > +   }
> > +
> > +   /* Find the remote entity. */
> > +   ent = sun6i_graph_find_ent

[PATCH v3 3/5] ARM: dts: rockchip: add RGA device node for RK3288

[Jacob Chen]

This patch add the RGA dt config of rk3288 SoC.

Signed-off-by: Jacob Chen 
Signed-off-by: Yakir Yang 
---
 arch/arm/boot/dts/rk3288.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 1efc2f2..cea41b7 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -945,6 +945,17 @@
status = "okay";
};
 
+   rga: rga@ff92 {
+   compatible = "rockchip,rk3288-rga";
+   reg = <0xff92 0x180>;
+   interrupts = ;
+   clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+   clock-names = "aclk", "hclk", "sclk";
+   power-domains = <&power RK3288_PD_VIO>;
+   resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru 
SRST_RGA_AHB>;
+   reset-names = "core", "axi", "ahb";
+   };
+
vopb: vop@ff93 {
compatible = "rockchip,rk3288-vop";
reg = <0xff93 0x19c>;
-- 
2.7.4

[PATCH v3 4/5] ARM: dts: rockchip: add RGA device node for RK3399

[Jacob Chen]

This patch add the RGA dt config of RK3399 SoC.

Signed-off-by: Jacob Chen 
Signed-off-by: Yakir Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8e6d1bd..0133a5f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1056,6 +1056,17 @@
status = "disabled";
};
 
+   rga: rga@ff68 {
+   compatible = "rockchip,rk3399-rga";
+   reg = <0x0 0xff68 0x0 0x1>;
+   interrupts = ;
+   clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+   clock-names = "aclk", "hclk", "sclk";
+   resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru 
SRST_H_RGA>;
+   reset-names = "core", "axi", "ahb";
+   power-domains = <&power RK3399_PD_RGA>;
+   };
+
efuse0: efuse@ff69 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff69 0x0 0x80>;
-- 
2.7.4

[PATCH v3 5/5] dt-bindings: Document the Rockchip RGA bindings

[Jacob Chen]

Add DT bindings documentation for Rockchip RGA

Signed-off-by: Jacob Chen 
Signed-off-by: Yakir Yang 
---
 .../devicetree/bindings/media/rockchip-rga.txt | 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.txt

diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.txt 
b/Documentation/devicetree/bindings/media/rockchip-rga.txt
new file mode 100644
index 000..fd5276a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/rockchip-rga.txt
@@ -0,0 +1,33 @@
+device-tree bindings for rockchip 2D raster graphic acceleration controller 
(RGA)
+
+RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
+graphics operations, such as point/line drawing, image scaling, rotation,
+BitBLT, alpha blending and image blur/sharpness.
+
+Required properties:
+- compatible: value should be one of the following
+   "rockchip,rk3288-rga";
+   "rockchip,rk3399-rga";
+
+- interrupts: RGA interrupt specifier.
+
+- clocks: phandle to RGA sclk/hclk/aclk clocks
+
+- clock-names: should be "aclk", "hclk" and "sclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: should be "core", "axi" and "ahb"
+
+Example:
+SoC-specific DT entry:
+   rga: rga@ff68 {
+   compatible = "rockchip,rk3399-rga";
+   reg = <0xff68 0x1>;
+   interrupts = ;
+   clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+   clock-names = "aclk", "hclk", "sclk";
+
+   resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru 
SRST_H_RGA>;
+   reset-names = "core, "axi", "ahb";
+   };
-- 
2.7.4

[PATCH v3 1/5] [media] v4l: add porter duff blend controls

[Jacob Chen]

At peresent, we don't have a control for Compositing and Blend.
All drivers are just doing copies while actually many hardwares
supports more functions.

So Adding V4L2 controls for Compositing and Blend, used for for
composting streams.

The values are based on porter duff operations.
Defined in below links.
https://developer.xamarin.com/api/type/Android.Graphics.PorterDuff+Mode/

Signed-off-by: Jacob Chen 
Suggested-by: Nicolas Dufresne 
---
 drivers/media/v4l2-core/v4l2-ctrls.c | 20 +++-
 include/uapi/linux/v4l2-controls.h   | 16 +++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c 
b/drivers/media/v4l2-core/v4l2-ctrls.c
index b9e08e3..561d7d5 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -478,7 +478,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
"Region Grid",
NULL,
};
-
+   static const char * const porter_duff_modes[] = {
+   "Source",
+   "Source Top",
+   "Source In",
+   "Source Out",
+   "Source Over",
+   "Destination",
+   "Destination Top",
+   "Destination In",
+   "Destination Out",
+   "Destination Over",
+   "Add",
+   "Clear",
+   NULL
+   };
 
switch (id) {
case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ:
@@ -564,6 +578,8 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
return vpx_golden_frame_sel;
case V4L2_CID_JPEG_CHROMA_SUBSAMPLING:
return jpeg_chroma_subsampling;
+   case V4L2_CID_PORTER_DUFF_MODE:
+   return porter_duff_modes;
case V4L2_CID_DV_TX_MODE:
return dv_tx_mode;
case V4L2_CID_DV_TX_RGB_RANGE:
@@ -886,6 +902,7 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_PIXEL_RATE:   return "Pixel Rate";
case V4L2_CID_TEST_PATTERN: return "Test Pattern";
case V4L2_CID_DEINTERLACING_MODE:   return "Deinterlacing Mode";
+   case V4L2_CID_PORTER_DUFF_MODE: return "PorterDuff Blend Modes";
 
/* DV controls */
/* Keep the order of the 'case's the same as in v4l2-controls.h! */
@@ -1060,6 +1077,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum 
v4l2_ctrl_type *type,
case V4L2_CID_DV_RX_IT_CONTENT_TYPE:
case V4L2_CID_TEST_PATTERN:
case V4L2_CID_DEINTERLACING_MODE:
+   case V4L2_CID_PORTER_DUFF_MODE:
case V4L2_CID_TUNE_DEEMPHASIS:
case V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL:
case V4L2_CID_DETECT_MD_MODE:
diff --git a/include/uapi/linux/v4l2-controls.h 
b/include/uapi/linux/v4l2-controls.h
index 0d2e1e0..9543b4b 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -893,7 +893,21 @@ enum v4l2_jpeg_chroma_subsampling {
 #define V4L2_CID_PIXEL_RATE(V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 2)
 #define V4L2_CID_TEST_PATTERN  (V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 3)
 #define V4L2_CID_DEINTERLACING_MODE(V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 4)
-
+#define V4L2_CID_PORTER_DUFF_MODE  (V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 5)
+enum v4l2_porter_duff_mode {
+   V4L2_PORTER_DUFF_SRC= 0,
+   V4L2_PORTER_DUFF_SRCATOP= 1,
+   V4L2_PORTER_DUFF_SRCIN  = 2,
+   V4L2_PORTER_DUFF_SRCOUT = 3,
+   V4L2_PORTER_DUFF_SRCOVER= 4,
+   V4L2_PORTER_DUFF_DST= 5,
+   V4L2_PORTER_DUFF_DSTATOP= 6,
+   V4L2_PORTER_DUFF_DSTIN  = 7,
+   V4L2_PORTER_DUFF_DSTOUT = 8,
+   V4L2_PORTER_DUFF_DSTOVER= 9,
+   V4L2_PORTER_DUFF_ADD= 10,
+   V4L2_PORTER_DUFF_CLEAR  = 11,
+};
 
 /*  DV-class control IDs defined by V4L2 */
 #define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900)
-- 
2.7.4

[PATCH v3 0/5] Add Rockchip RGA V4l2 support

[Jacob Chen]

This patch series add a v4l2 m2m drvier for rockchip RGA direct rendering based 
2d graphics acceleration module.

Before, my colleague yakir have write a drm RGA drvier and send it to the lists.
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-March/416769.html
I have been asked to find a userspace user("compositor") for it, but after some 
studys, my conclusion is that unlike exynos g2d,
rockchip rga are not suitable for compositor. Rockchip RGA have a limited MMU, 
which means it can only hold several buffers in the same time.
When it was used in compositor, it will waste a lot of time to 
import/export/flush buffer, resulting in a bad performance.

A few months ago, i saw a discussion in dri-de...@lists.freedesktop.org.
It remind that we could write a v4l2 m2m RGA driver, since we usually use RGA 
for streaming purpose.
https://patches.linaro.org/cover/97727/

I have test this driver with gstreamer v4l2transform plugin and it seems work 
well.

change in V3:
- rename the controls.
- add pm_runtime support.
- enable node by default.
- correct spelling in documents.

change in V2:
- generalize the controls.
- map buffers (10-50 us) in every cmd-run rather than in buffer-import to avoid 
get_free_pages failed on
actively used systems.
- remove status in dt-bindings examples.

Jacob Chen (5):
  [media] v4l: add blend modes controls
  [media]: rockchip/rga: v4l2 m2m support
  ARM: dts: rockchip: add RGA device node for RK3288
  ARM: dts: rockchip: add RGA device node for RK3399
  dt-bindings: Document the Rockchip RGA bindings

 .../devicetree/bindings/media/rockchip-rga.txt |  33 +
 arch/arm/boot/dts/rk3288.dtsi  |  11 +
 arch/arm64/boot/dts/rockchip/rk3399.dtsi   |  11 +
 drivers/media/platform/Kconfig |  11 +
 drivers/media/platform/Makefile|   2 +
 drivers/media/platform/rockchip-rga/Makefile   |   3 +
 drivers/media/platform/rockchip-rga/rga-buf.c  | 141 +++
 drivers/media/platform/rockchip-rga/rga-hw.c   | 650 ++
 drivers/media/platform/rockchip-rga/rga-hw.h   | 437 +
 drivers/media/platform/rockchip-rga/rga.c  | 987 +
 drivers/media/platform/rockchip-rga/rga.h  | 110 +++
 drivers/media/v4l2-core/v4l2-ctrls.c   |  20 +-
 include/uapi/linux/v4l2-controls.h |  16 +-
 13 files changed, 2430 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.txt
 create mode 100644 drivers/media/platform/rockchip-rga/Makefile
 create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
 create mode 100644 drivers/media/platform/rockchip-rga/rga.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga.h

-- 
2.7.4

[PATCH v3 2/5] [media]: rockchip/rga: v4l2 m2m support

[Jacob Chen]

Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness

The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the rendering pipeline.
 - copy
 - fast solid color fill
 - rotation
 - flip
 - alpha blending

The code in rga-hw.c is used to configure regs accroding to operations
The code in rga-buf.c is used to create (1-Level)mmu table for RGA
The tables is stored in a list, and be removed when buffer is cleanup

Signed-off-by: Jacob Chen 
---
 drivers/media/platform/Kconfig|  11 +
 drivers/media/platform/Makefile   |   2 +
 drivers/media/platform/rockchip-rga/Makefile  |   3 +
 drivers/media/platform/rockchip-rga/rga-buf.c | 141 
 drivers/media/platform/rockchip-rga/rga-hw.c  | 650 +
 drivers/media/platform/rockchip-rga/rga-hw.h  | 437 
 drivers/media/platform/rockchip-rga/rga.c | 987 ++
 drivers/media/platform/rockchip-rga/rga.h | 110 +++
 8 files changed, 2341 insertions(+)
 create mode 100644 drivers/media/platform/rockchip-rga/Makefile
 create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
 create mode 100644 drivers/media/platform/rockchip-rga/rga.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga.h

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index c9106e1..8199bcf 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -411,6 +411,17 @@ config VIDEO_RENESAS_VSP1
  To compile this driver as a module, choose M here: the module
  will be called vsp1.
 
+config VIDEO_ROCKCHIP_RGA
+   tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
+   depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select VIDEOBUF2_DMA_SG
+   select V4L2_MEM2MEM_DEV
+   default n
+   ---help---
+ This is a v4l2 driver for Rockchip SOC RGA2
+ 2d graphics accelerator.
+
 config VIDEO_TI_VPE
tristate "TI VPE (Video Processing Engine) driver"
depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 349ddf6..3bf096f 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1)  += rcar_fdp1.o
 obj-$(CONFIG_VIDEO_RENESAS_JPU)+= rcar_jpu.o
 obj-$(CONFIG_VIDEO_RENESAS_VSP1)   += vsp1/
 
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)   += rockchip-rga/
+
 obj-y  += omap/
 
 obj-$(CONFIG_VIDEO_AM437X_VPFE)+= am437x/
diff --git a/drivers/media/platform/rockchip-rga/Makefile 
b/drivers/media/platform/rockchip-rga/Makefile
new file mode 100644
index 000..92fe254
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/Makefile
@@ -0,0 +1,3 @@
+rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c 
b/drivers/media/platform/rockchip-rga/rga-buf.c
new file mode 100644
index 000..b4d28e3
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-buf.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rga-hw.h"
+#include "rga.h"
+
+static int
+rga_queue_setup(struct vb2_queue *vq,
+   unsigned int *nbuffers, unsigned int *nplanes,
+   unsigned int sizes[], struct device *alloc_devs[])
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vq);
+   struct rga_frame *f = rga_get_frame(ctx, vq->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   sizes[0] = f->size;
+   *nplanes = 1;
+
+   if (*nbuffers == 0)
+   *nbuffers = 1;
+
+   return 0;
+}
+
+static int rga_buf_prepare(struct vb2_buffer *vb)
+{
+   struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+   struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
+
+   if (IS_ERR(f))
+   return PTR_ERR(f);
+
+   vb2_set_plane_payload(vb, 0, f->size);
+
+   return 0;
+}
+
+static void rga_buf_queue(struct vb2_buffer *vb)
+{
+  

FSGSBASE ABI considerations

[Andy Lutomirski]

Hi all-

Chang wants to get the FSGSBASE patches in.  Here's a bit on a brain
dump on what I think the relevant considerations are and why I haven't
sent out my patches.

- Background -

Setting CR4.FSGSBASE has two major advantages and one major
disadvantage.  The major advantages are:

 - We can avoid some WRMSR instructions in the context switch path,
which makes a rather large difference.

 - User code can use the new RD/WR FS/GS BASE instructions.
Apparently some users really want this for, umm, userspace threading.
Think Java.

The major disadvantage is that user code can use the new instructions.
Now userspace is going to do totally stupid shite like writing some
nonzero value to GS and then doing WRGSBASE or like linking some
idiotic library that uses WRGSBASE into a perfectly innocent program
like dosemu2 and resulting in utterly nonsensical descriptor state.

In Windows, supposedly the scheduler reserves the right to do
arbitrarily awful things to you if you use WRFSBASE or WRGSBASE
inappropriately.  Andi took a similar approach in his original
FSGSBASE patches.  I think this is wrong and we need to have sensible,
documented, and tested behavior for what happens when you use the new
instructions.

For simplicity, the text below talks about WRGSBASE and ignores
WRFSBASE.  The ABI considerations are identical, even if the kernel
implementation details are different.

- Requirements -

In my book, there's only one sensible choice for what happens when you
are scheduled out and back in on a Linux system with FSGSBASE enabled:
all of your descriptors end up *exactly* the way they were when you
scheduled out.

ptrace users need to keep working.  It would be nice if existing gdb
versions continue to work right when user code uses WRGSBASE, but it
might be okay if a new ptrace interface is needed.  The existing
regset ABI is exactly backwards from what it needs to be to make this
easy.

- interaction with modify_ldt() -

The first sticking point we'll hit is modify_ldt() and, in particular,
what happens if you call modify_ldt() to change the base of a segment
that is ioaded into gs by another thread in the same mm.

Our current behavior here is nonsensical: on 32-bit kernels, FS would
be fully refreshed on other threads and GS might be depending on
compiler options.  On 64-bit kernels, neither FS nor GS is immediately
refreshed.  Historically, we didn't refresh anything reliably.  On the
bright side, this means that existing modify_ldt() users are (AFAIK)
tolerant of somewhat crazy behavior.

On an FSGSBASE-enabled system, I think we need to provide
deterministic, documented, tested behavior.  I can think of three
plausible choices:

1a. modify_ldt() immediately updates FSBASE and GSBASE all threads
that reference the modified selector.

1b. modify_ldt() immediatley updates FSBASE and GSBASE on all threads
that reference the LDT.

2. modify_ldt() leaves FSBASE and GSBASE alone on all threads.

(2) is trivial to implement, whereas (1a) and (1b) are a bit nasty to
implement when FSGSBASE is on.

The tricky bit is that 32-bit kernels can't do (2), so, if we want
modify_ldt() to behave the same on 32-bit and 64-bit kernels, we're
stuck with (1).  (I think we can implement (2) with acceptable
performance on 64-bit non-FSGSBASE kernels if we wanted to.)

Thoughts?

- Interaction with ptrace -

struct user_regs_struct looks like this:

...
unsigned long   fs_base;
unsigned long   gs_base;
unsigned long   ds;
unsigned long   es;
unsigned long   fs;
unsigned long   gs;
...

This means that, when gdb saves away a regset and reloads it using
PTRACE_SETREGS or similar, the effect is to load gs_base and then load
gs.  If gs != 0, this will blow away gs_base.  Without FSGSBASE, this
doesn't matter so much.  With FSGSBASE, it means that using gdb to do,
say, 'print func()' may corrupt gsbase.

What, if anything, should we do about this?  One option would be to
make gs_base be accurate all the time (it currently isn't) and teach
PTRACE_SETREGS to restore in the opposite order despite the struct
layout.

Thoughts?

Re: [PATCH v4 9/9] arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board

[Sean Wang]

On Thu, 2017-07-27 at 16:39 +0200, Matthias Brugger wrote:
> 
> On 05/25/2017 06:02 AM, sean.w...@mediatek.com wrote:
> > From: Sean Wang 
> > 
> > Add support for the Bananapi R2 (BPI-R2) development board from
> > BIPAI KEJI. Detailed hardware information for BPI-R2 which could be
> > found on http://www.banana-pi.org/r2.html
> > 
> > The patch currently only adds Mediatek GMAC, MT7530 Switch, the crypto
> > engine, USB, IR, I2S, I2C, UART, SPI, PWM, GPIO keys, GPIO LEDs and
> > PMIC LEDs. As to the other missing hardware and peripherals, they would
> > be added and integrated continuously.
> > 
> > Signed-off-by: Sean Wang 
> > Acked-by: Rob Herring 
> > ---
> >   Documentation/devicetree/bindings/arm/mediatek.txt |   2 +
> >   arch/arm/boot/dts/Makefile |   1 +
> >   arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts  | 440 
> > +
> >   3 files changed, 443 insertions(+)
> >   create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> > 
> [...]
> > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts 
> > b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> > new file mode 100644
> > index 000..72c7984
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> [...]
> > +
> > +ð {
> > +   status = "okay";
> > +   gmac0: mac@0 {
> > +   compatible = "mediatek,eth-mac";
> > +   reg = <0>;
> > +   phy-mode = "trgmii";
> > +   fixed-link {
> > +   speed = <1000>;
> > +   full-duplex;
> > +   pause;
> > +   };
> > +   };
> > +
> > +   mdio: mdio-bus {
> > +   switch@0 {
> > +   compatible = "mediatek,mt7530";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   reg = <0>;
> 
> What is this reg needed for? I can't find it neither in the code nor in the 
> bindings (mt7530 and general dsa bindings). Actually it throws a warning when 
> compiling:
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb: Warning (reg_format): "reg" 
> property in /ethernet@1b10/mdio-bus/switch@0 has invalid length (4 bytes) 
> (#address-cells == 2, #size-cells == 1)
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb: Warning 
> (avoid_default_addr_size): Relying on default #address-cells value for 
> /ethernet@1b10/mdio-bus/switch@0
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb: Warning 
> (avoid_default_addr_size): Relying on default #size-cells value for 
> /ethernet@1b10/mdio-bus/switch@0
> 
> Regards,
> Matthias
> 


Hi, Matthias

many thanks

It should be just my written mistakes. Recently I prepared the next
version including a few fixups and enhancements which also would include
the warning correction you reported here.

Sean 

> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH V9 3/3] powernv: Add support to clear sensor groups data

[Shilpasri G Bhat]

Adds support for clearing different sensor groups. OCC inband sensor
groups like CSM, Profiler, Job Scheduler can be cleared using this
driver. The min/max of all sensors belonging to these sensor groups
will be cleared.

Signed-off-by: Shilpasri G Bhat 
---
Changes from V8:
- Use mutex_lock_interruptible()
- Fix error codes returned to user

 arch/powerpc/include/asm/opal-api.h|   3 +-
 arch/powerpc/include/asm/opal.h|   2 +
 arch/powerpc/include/uapi/asm/opal-occ.h   |  23 +
 arch/powerpc/platforms/powernv/Makefile|   2 +-
 arch/powerpc/platforms/powernv/opal-occ.c  | 115 +
 arch/powerpc/platforms/powernv/opal-wrappers.S |   1 +
 arch/powerpc/platforms/powernv/opal.c  |   3 +
 7 files changed, 147 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/include/uapi/asm/opal-occ.h
 create mode 100644 arch/powerpc/platforms/powernv/opal-occ.c

diff --git a/arch/powerpc/include/asm/opal-api.h 
b/arch/powerpc/include/asm/opal-api.h
index 92e31fd..0841659 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -195,7 +195,8 @@
 #define OPAL_SET_POWERCAP  153
 #define OPAL_GET_POWER_SHIFT_RATIO 154
 #define OPAL_SET_POWER_SHIFT_RATIO 155
-#define OPAL_LAST  155
+#define OPAL_SENSOR_GROUPS_CLEAR   156
+#define OPAL_LAST  156
 
 /* Device tree flags */
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index b9ea77f..a716def 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -271,6 +271,7 @@ int64_t opal_xive_set_vp_info(uint64_t vp,
 int opal_set_powercap(u32 handle, int token, u32 pcap);
 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
+int opal_sensor_groups_clear(u32 group_hndl, int token);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
@@ -351,6 +352,7 @@ static inline int opal_get_async_rc(struct opal_msg msg)
 
 void opal_powercap_init(void);
 void opal_psr_init(void);
+int opal_sensor_groups_clear_history(u32 handle);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/include/uapi/asm/opal-occ.h 
b/arch/powerpc/include/uapi/asm/opal-occ.h
new file mode 100644
index 000..97c45e2
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/opal-occ.h
@@ -0,0 +1,23 @@
+/*
+ * OPAL OCC command interface
+ * Supported on POWERNV platform
+ *
+ * (C) Copyright IBM 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _UAPI_ASM_POWERPC_OPAL_OCC_H_
+#define _UAPI_ASM_POWERPC_OPAL_OCC_H_
+
+#define OPAL_OCC_IOCTL_CLEAR_SENSOR_GROUPS _IOR('o', 1, u32)
+
+#endif /* _UAPI_ASM_POWERPC_OPAL_OCC_H */
diff --git a/arch/powerpc/platforms/powernv/Makefile 
b/arch/powerpc/platforms/powernv/Makefile
index 9ed7d33..f193b33 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -2,7 +2,7 @@ obj-y   += setup.o opal-wrappers.o opal.o 
opal-async.o idle.o
 obj-y  += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
 obj-y  += rng.o opal-elog.o opal-dump.o opal-sysparam.o 
opal-sensor.o
 obj-y  += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o
-obj-y  += opal-kmsg.o opal-powercap.o opal-psr.o
+obj-y  += opal-kmsg.o opal-powercap.o opal-psr.o opal-occ.o
 
 obj-$(CONFIG_SMP)  += smp.o subcore.o subcore-asm.o
 obj-$(CONFIG_PCI)  += pci.o pci-ioda.o npu-dma.o
diff --git a/arch/powerpc/platforms/powernv/opal-occ.c 
b/arch/powerpc/platforms/powernv/opal-occ.c
new file mode 100644
index 000..f3ce880
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-occ.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright IBM Corporation 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "opal-occ: " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DEFINE_MU

[PATCH V9 2/3] powernv: Add support to set power-shifting-ratio

[Shilpasri G Bhat]

This patch adds support to set power-shifting-ratio which hints the
firmware how to distribute/throttle power between different entities
in a system (e.g CPU v/s GPU). This ratio is used by OCC for power
capping algorithm.

Signed-off-by: Shilpasri G Bhat 
---
Changes from V8:
- Use __pa() while passing pointer in opal call
- Use mutex_lock_interruptible()
- Fix error codes returned to user
- Allocate and add sysfs attributes in a single loop

 arch/powerpc/include/asm/opal-api.h|   4 +-
 arch/powerpc/include/asm/opal.h|   3 +
 arch/powerpc/platforms/powernv/Makefile|   2 +-
 arch/powerpc/platforms/powernv/opal-psr.c  | 173 +
 arch/powerpc/platforms/powernv/opal-wrappers.S |   2 +
 arch/powerpc/platforms/powernv/opal.c  |   3 +
 6 files changed, 185 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/platforms/powernv/opal-psr.c

diff --git a/arch/powerpc/include/asm/opal-api.h 
b/arch/powerpc/include/asm/opal-api.h
index c3e0c4a..92e31fd 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -193,7 +193,9 @@
 #define OPAL_NPU_MAP_LPAR  148
 #define OPAL_GET_POWERCAP  152
 #define OPAL_SET_POWERCAP  153
-#define OPAL_LAST  153
+#define OPAL_GET_POWER_SHIFT_RATIO 154
+#define OPAL_SET_POWER_SHIFT_RATIO 155
+#define OPAL_LAST  155
 
 /* Device tree flags */
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index ec2087c..b9ea77f 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -269,6 +269,8 @@ int64_t opal_xive_set_vp_info(uint64_t vp,
 int64_t opal_xive_dump(uint32_t type, uint32_t id);
 int opal_get_powercap(u32 handle, int token, u32 *pcap);
 int opal_set_powercap(u32 handle, int token, u32 pcap);
+int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
+int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
@@ -348,6 +350,7 @@ static inline int opal_get_async_rc(struct opal_msg msg)
 void opal_wake_poller(void);
 
 void opal_powercap_init(void);
+void opal_psr_init(void);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/platforms/powernv/Makefile 
b/arch/powerpc/platforms/powernv/Makefile
index e79f806..9ed7d33 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -2,7 +2,7 @@ obj-y   += setup.o opal-wrappers.o opal.o 
opal-async.o idle.o
 obj-y  += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
 obj-y  += rng.o opal-elog.o opal-dump.o opal-sysparam.o 
opal-sensor.o
 obj-y  += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o
-obj-y  += opal-kmsg.o opal-powercap.o
+obj-y  += opal-kmsg.o opal-powercap.o opal-psr.o
 
 obj-$(CONFIG_SMP)  += smp.o subcore.o subcore-asm.o
 obj-$(CONFIG_PCI)  += pci.o pci-ioda.o npu-dma.o
diff --git a/arch/powerpc/platforms/powernv/opal-psr.c 
b/arch/powerpc/platforms/powernv/opal-psr.c
new file mode 100644
index 000..e2cb335
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-psr.c
@@ -0,0 +1,173 @@
+/*
+ * PowerNV OPAL Power-Shift-Ratio interface
+ *
+ * Copyright 2017 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define pr_fmt(fmt) "opal-psr: " fmt
+
+#include 
+#include 
+#include 
+
+#include 
+
+DEFINE_MUTEX(psr_mutex);
+
+static struct kobject *psr_kobj;
+
+struct psr_attr {
+   u32 handle;
+   struct kobj_attribute attr;
+} *psr_attrs;
+
+static ssize_t psr_show(struct kobject *kobj, struct kobj_attribute *attr,
+   char *buf)
+{
+   struct psr_attr *psr_attr = container_of(attr, struct psr_attr, attr);
+   struct opal_msg msg;
+   int psr, ret, token;
+
+   token = opal_async_get_token_interruptible();
+   if (token < 0) {
+   pr_devel("Failed to get token\n");
+   return token;
+   }
+
+   ret = mutex_lock_interruptible(&psr_mutex);
+   if (ret)
+   return ret;
+
+   ret = opal_get_power_shift_ratio(psr_attr->handle, token,
+   (u32 *)__pa(&psr));
+   switch (ret) {
+   case OPAL_ASYNC_COMPLETION:
+   ret = opal_async_wait_response(token, &msg);
+   if (ret) {
+   pr_devel("Failed to wait for the async response\n");
+   ret = -EIO;
+   goto out;
+   }
+   ret = opal_error_

[PATCH V9 1/3] powernv: powercap: Add support for powercap framework

[Shilpasri G Bhat]

Adds a generic powercap framework to change the system powercap
inband through OPAL-OCC command/response interface.

Signed-off-by: Shilpasri G Bhat 
---
Changes from V8:
- Use __pa() while passing pointer in opal call
- Use mutex_lock_interruptible()
- Fix error codes returned to user
- Allocate and add sysfs attributes in a single loop

 arch/powerpc/include/asm/opal-api.h|   5 +-
 arch/powerpc/include/asm/opal.h|   4 +
 arch/powerpc/platforms/powernv/Makefile|   2 +-
 arch/powerpc/platforms/powernv/opal-powercap.c | 243 +
 arch/powerpc/platforms/powernv/opal-wrappers.S |   2 +
 arch/powerpc/platforms/powernv/opal.c  |   4 +
 6 files changed, 258 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/platforms/powernv/opal-powercap.c

diff --git a/arch/powerpc/include/asm/opal-api.h 
b/arch/powerpc/include/asm/opal-api.h
index 3130a73..c3e0c4a 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -42,6 +42,7 @@
 #define OPAL_I2C_STOP_ERR  -24
 #define OPAL_XIVE_PROVISIONING -31
 #define OPAL_XIVE_FREE_ACTIVE  -32
+#define OPAL_TIMEOUT   -33
 
 /* API Tokens (in r0) */
 #define OPAL_INVALID_CALL -1
@@ -190,7 +191,9 @@
 #define OPAL_NPU_INIT_CONTEXT  146
 #define OPAL_NPU_DESTROY_CONTEXT   147
 #define OPAL_NPU_MAP_LPAR  148
-#define OPAL_LAST  148
+#define OPAL_GET_POWERCAP  152
+#define OPAL_SET_POWERCAP  153
+#define OPAL_LAST  153
 
 /* Device tree flags */
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 588fb1c..ec2087c 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -267,6 +267,8 @@ int64_t opal_xive_set_vp_info(uint64_t vp,
 int64_t opal_xive_free_irq(uint32_t girq);
 int64_t opal_xive_sync(uint32_t type, uint32_t id);
 int64_t opal_xive_dump(uint32_t type, uint32_t id);
+int opal_get_powercap(u32 handle, int token, u32 *pcap);
+int opal_set_powercap(u32 handle, int token, u32 pcap);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
@@ -345,6 +347,8 @@ static inline int opal_get_async_rc(struct opal_msg msg)
 
 void opal_wake_poller(void);
 
+void opal_powercap_init(void);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_OPAL_H */
diff --git a/arch/powerpc/platforms/powernv/Makefile 
b/arch/powerpc/platforms/powernv/Makefile
index b5d98cb..e79f806 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -2,7 +2,7 @@ obj-y   += setup.o opal-wrappers.o opal.o 
opal-async.o idle.o
 obj-y  += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
 obj-y  += rng.o opal-elog.o opal-dump.o opal-sysparam.o 
opal-sensor.o
 obj-y  += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o
-obj-y  += opal-kmsg.o
+obj-y  += opal-kmsg.o opal-powercap.o
 
 obj-$(CONFIG_SMP)  += smp.o subcore.o subcore-asm.o
 obj-$(CONFIG_PCI)  += pci.o pci-ioda.o npu-dma.o
diff --git a/arch/powerpc/platforms/powernv/opal-powercap.c 
b/arch/powerpc/platforms/powernv/opal-powercap.c
new file mode 100644
index 000..9be5093
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-powercap.c
@@ -0,0 +1,243 @@
+/*
+ * PowerNV OPAL Powercap interface
+ *
+ * Copyright 2017 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define pr_fmt(fmt) "opal-powercap: " fmt
+
+#include 
+#include 
+#include 
+
+#include 
+
+DEFINE_MUTEX(powercap_mutex);
+
+static struct kobject *powercap_kobj;
+
+struct powercap_attr {
+   u32 handle;
+   struct kobj_attribute attr;
+};
+
+static struct pcap {
+   struct attribute_group pg;
+   struct powercap_attr *pattrs;
+} *pcaps;
+
+static ssize_t powercap_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+   struct powercap_attr *pcap_attr = container_of(attr,
+   struct powercap_attr, attr);
+   struct opal_msg msg;
+   u32 pcap;
+   int ret, token;
+
+   token = opal_async_get_token_interruptible();
+   if (token < 0) {
+   pr_devel("Failed to get token\n");
+   return token;
+   }
+
+   ret = mutex_lock_interruptible(&powercap_mutex);
+   if (ret)
+   return ret;
+
+   ret = opal_get_powercap(pcap_attr->handle, token, (u32 *)__pa(&pcap));
+   switch (ret) {
+   case OPAL_ASYNC_COMPLETION:
+   ret = opal_async_wait_res

Re: [PATCH v2 net-next 0/4] net: dsa: lan9303: Fix MDIO issues.

[David Miller]

From: Egil Hjelmeland 
Date: Sun, 30 Jul 2017 19:58:52 +0200

> This series fix the MDIO interface for the lan9303 DSA driver.
> Bugs found after testing on actual HW.
> 
> This series is extracted from the first patch of my first large
> series. Significant changes from that version are:
>  - use mdiobus_write_nested, mdiobus_read_nested.
>  - EXPORT lan9303_indirect_phy_ops
> 
> Unfortunately I do not have access to i2c based system for
> testing.
> 
> Changes from first version:
>  - Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL

Series applied, thanks.

[PATCH V9 0/3] powernv : Add support for OPAL-OCC command/response interface

[Shilpasri G Bhat]

In P9, OCC (On-Chip-Controller) supports shared memory based
commad-response interface. Within the shared memory there is an OPAL
command buffer and OCC response buffer that can be used to send
inband commands to OCC. The following commands are supported:

1) Set system powercap
2) Set CPU-GPU power shifting ratio
3) Clear min/max for OCC sensor groups

Shilpasri G Bhat (3):
  powernv: powercap: Add support for powercap framework
  powernv: Add support to set power-shifting-ratio
  powernv: Add support to clear sensor groups data

 arch/powerpc/include/asm/opal-api.h|   8 +-
 arch/powerpc/include/asm/opal.h|   9 +
 arch/powerpc/include/uapi/asm/opal-occ.h   |  23 +++
 arch/powerpc/platforms/powernv/Makefile|   2 +-
 arch/powerpc/platforms/powernv/opal-occ.c  | 115 
 arch/powerpc/platforms/powernv/opal-powercap.c | 243 +
 arch/powerpc/platforms/powernv/opal-psr.c  | 173 ++
 arch/powerpc/platforms/powernv/opal-wrappers.S |   5 +
 arch/powerpc/platforms/powernv/opal.c  |  10 +
 9 files changed, 586 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/include/uapi/asm/opal-occ.h
 create mode 100644 arch/powerpc/platforms/powernv/opal-occ.c
 create mode 100644 arch/powerpc/platforms/powernv/opal-powercap.c
 create mode 100644 arch/powerpc/platforms/powernv/opal-psr.c

-- 
1.8.3.1

linux-next: manual merge of the drm tree with Linus' tree

[Stephen Rothwell]

Hi Dave,

Today's linux-next merge of the drm tree got a conflict in:

  drivers/gpu/drm/nouveau/nv50_display.c

between commit:

  4a5431af19bc ("drm/nouveau/kms/nv50: update vblank state in response to 
modeset actions")

from Linus' tree and commit:

  ca814b25538a ("drm/vblank: Consistent drm_crtc_ prefix")

from the drm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/nouveau/nv50_display.c
index 2bc0dc985214,747c99c1e474..
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@@ -4080,8 -4068,7 +4081,8 @@@ nv50_disp_atomic_commit_tail(struct drm
if (crtc->state->event) {
unsigned long flags;
/* Get correct count/ts if racing with vblank irq */
 -  drm_crtc_accurate_vblank_count(crtc);
 +  if (crtc->state->active)
-   drm_accurate_vblank_count(crtc);
++  drm_crtc_accurate_vblank_count(crtc);
spin_lock_irqsave(&crtc->dev->event_lock, flags);
drm_crtc_send_vblank_event(crtc, crtc->state->event);
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);

Re: [PATCH v3 4/4] squashfs: Add zstd support

[Phillip Lougher]

On Mon, Jul 31, 2017 at 2:50 AM, Phillip Lougher
 wrote:
> On Thu, Jul 20, 2017 at 10:27 PM, Nick Terrell  wrote:
>> Add zstd compression and decompression support to SquashFS. zstd is a
>> great fit for SquashFS because it can compress at ratios approaching xz,
>> while decompressing twice as fast as zlib. For SquashFS in particular,
>> it can decompress as fast as lzo and lz4. It also has the flexibility
>> to turn down the compression ratio for faster compression times.
>
> Hi Nick,
>
> This patch (and none of the previous versions) is showing up on
> squashfs-de...@lists.sourceforge.net.  I also think you should have
> emailed me directly as a courtesy, as I'm the Squashfs author and
> maintainer.

OK, you're not subscribed to squashfs-devel    I have accepted
your previous posts, but, please subscribe.

Thanks

Phillip

>
>
>> | Method | Ratio | Compression MB/s | Decompression MB/s |
>> ||---|--||
>> | gzip   |  2.92 |   15 |128 |
>> | lzo|  2.64 |  9.5 |217 |
>> | lz4|  2.12 |   94 |218 |
>> | xz |  3.43 |  5.5 | 35 |
>> | xz 256 KB  |  3.53 |  5.4 | 40 |
>> | zstd 1 |  2.71 |   96 |210 |
>> | zstd 5 |  2.93 |   69 |198 |
>> | zstd 10|  3.01 |   41 |225 |
>> | zstd 15|  3.13 | 11.4 |224 |
>> | zstd 16 256 KB |  3.24 |  8.1 |210 |
>
>
> Those numbers look good to me.
>
>>
>> This patch was written by Sean Purcell , but I will be
>> taking over the submission process.
>>
>> [1] http://releases.ubuntu.com/16.10/
>> [2] 
>> https://github.com/facebook/zstd/blob/dev/contrib/linux-kernel/squashfs-benchmark.sh
>
> I can't find your patch that adds zstd to the user-land
> Squashfs-tools.  That would be handy to do any testing :-)
>
> Phillip
>
>>
>> zstd source repository: https://github.com/facebook/zstd
>>
>> Cc: Sean Purcell 
>> Signed-off-by: Nick Terrell 
>> ---
>>  fs/squashfs/Kconfig|  14 +
>>  fs/squashfs/Makefile   |   1 +
>>  fs/squashfs/decompressor.c |   7 +++
>>  fs/squashfs/decompressor.h |   4 ++
>>  fs/squashfs/squashfs_fs.h  |   1 +
>>  fs/squashfs/zstd_wrapper.c | 150 
>> +
>>  6 files changed, 177 insertions(+)
>>  create mode 100644 fs/squashfs/zstd_wrapper.c
>>
>> diff --git a/fs/squashfs/Kconfig b/fs/squashfs/Kconfig
>> index ffb093e..1adb334 100644
>> --- a/fs/squashfs/Kconfig
>> +++ b/fs/squashfs/Kconfig
>> @@ -165,6 +165,20 @@ config SQUASHFS_XZ
>>
>>   If unsure, say N.
>>
>> +config SQUASHFS_ZSTD
>> +   bool "Include support for ZSTD compressed file systems"
>> +   depends on SQUASHFS
>> +   select ZSTD_DECOMPRESS
>> +   help
>> + Saying Y here includes support for reading Squashfs file systems
>> + compressed with ZSTD compression.  ZSTD gives better compression 
>> than
>> + the default ZLIB compression, while using less CPU.
>> +
>> + ZSTD is not the standard compression used in Squashfs and so most
>> + file systems will be readable without selecting this option.
>> +
>> + If unsure, say N.
>> +
>>  config SQUASHFS_4K_DEVBLK_SIZE
>> bool "Use 4K device block size?"
>> depends on SQUASHFS
>> diff --git a/fs/squashfs/Makefile b/fs/squashfs/Makefile
>> index 246a6f3..6655631 100644
>> --- a/fs/squashfs/Makefile
>> +++ b/fs/squashfs/Makefile
>> @@ -15,3 +15,4 @@ squashfs-$(CONFIG_SQUASHFS_LZ4) += lz4_wrapper.o
>>  squashfs-$(CONFIG_SQUASHFS_LZO) += lzo_wrapper.o
>>  squashfs-$(CONFIG_SQUASHFS_XZ) += xz_wrapper.o
>>  squashfs-$(CONFIG_SQUASHFS_ZLIB) += zlib_wrapper.o
>> +squashfs-$(CONFIG_SQUASHFS_ZSTD) += zstd_wrapper.o
>> diff --git a/fs/squashfs/decompressor.c b/fs/squashfs/decompressor.c
>> index d2bc136..8366398 100644
>> --- a/fs/squashfs/decompressor.c
>> +++ b/fs/squashfs/decompressor.c
>> @@ -65,6 +65,12 @@ static const struct squashfs_decompressor 
>> squashfs_zlib_comp_ops = {
>>  };
>>  #endif
>>
>> +#ifndef CONFIG_SQUASHFS_ZSTD
>> +static const struct squashfs_decompressor squashfs_zstd_comp_ops = {
>> +   NULL, NULL, NULL, NULL, ZSTD_COMPRESSION, "zstd", 0
>> +};
>> +#endif
>> +
>>  static const struct squashfs_decompressor squashfs_unknown_comp_ops = {
>> NULL, NULL, NULL, NULL, 0, "unknown", 0
>>  };
>> @@ -75,6 +81,7 @@ static const struct squashfs_decompressor *decompressor[] 
>> = {
>> &squashfs_lzo_comp_ops,
>> &squashfs_xz_comp_ops,
>> &squashfs_lzma_unsupported_comp_ops,
>> +   &squashfs_zstd_comp_ops,
>> &squashfs_unknown_comp_ops
>>  };
>>
>> diff --git a/fs/squashfs/decompressor.h b/fs/squashfs/decompressor.h
>> index a25713c..0f5a8e4 100644
>> 

linux-next: build warning after merge of the crypto tree

[Stephen Rothwell]

Hi Herbert,

After merging the crypto tree, today's linux-next build (x86_64
allmodconfig) produced this warning:

drivers/crypto/ccp/ccp-ops.c: In function 'ccp_run_rsa_cmd':
drivers/crypto/ccp/ccp-ops.c:1856:3: warning: 'sb_count' may be used 
uninitialized in this function [-Wmaybe-uninitialized]
   cmd_q->ccp->vdata->perform->sbfree(cmd_q, op.sb_key, sb_count);
   ^

Maybe introduced by commit

  6ba46c7d4d7e ("crypto: ccp - Fix base RSA function for version 5 CCPs")

-- 
Cheers,
Stephen Rothwell