Re: [PATCH] fs: fix xattr permission checking error

[Theodore Ts'o]

On Sat, Oct 21, 2017 at 03:39:47PM +0200, Nicolas Belouin wrote:
> Fix an issue making trusted xattr world readable and other
> cap_sys_admin only
>

NACK.  It is *documented* that trusted xattrs are only supposed to be
readable by root.

- Ted

Re: [PATCH] fs: fix xattr permission checking error

[Theodore Ts'o]

On Sat, Oct 21, 2017 at 03:39:47PM +0200, Nicolas Belouin wrote:
> Fix an issue making trusted xattr world readable and other
> cap_sys_admin only
>

NACK.  It is *documented* that trusted xattrs are only supposed to be
readable by root.

- Ted

Re: [PATCH] fs: check for DAC_READ_SEARCH instead of SYS_ADMIN

[Theodore Ts'o]

On Sat, Oct 21, 2017 at 03:24:46PM +0200, Nicolas Belouin wrote:
> These checks are meant to prevent leaks or attacks via directory
> traversal, the use of CAP_SYS_ADMIN here is a misuse,
> CAP_DAC_READ_SEARCH being way more appropriate as a process
> with CAP_DAC_READ_SEARCH is entrusted with going trough all directories.
> CAP_SYS_ADMIN is not meant to flag such a process.
> 
> Signed-off-by: Nicolas Belouin 

No.  lookup_dcookie() is a horrid, horrid, hack which is
*spectacularly* dangerous.  We should not be trying to encourage its
use for anything beside its single legacy user, oprofile(8), for which
CAP_SYS_ADMIN is appropriate.

- Ted

Re: [PATCH] fs: check for DAC_READ_SEARCH instead of SYS_ADMIN

[Theodore Ts'o]

On Sat, Oct 21, 2017 at 03:24:46PM +0200, Nicolas Belouin wrote:
> These checks are meant to prevent leaks or attacks via directory
> traversal, the use of CAP_SYS_ADMIN here is a misuse,
> CAP_DAC_READ_SEARCH being way more appropriate as a process
> with CAP_DAC_READ_SEARCH is entrusted with going trough all directories.
> CAP_SYS_ADMIN is not meant to flag such a process.
> 
> Signed-off-by: Nicolas Belouin 

No.  lookup_dcookie() is a horrid, horrid, hack which is
*spectacularly* dangerous.  We should not be trying to encourage its
use for anything beside its single legacy user, oprofile(8), for which
CAP_SYS_ADMIN is appropriate.

- Ted

Re: [PATCH v1 1/3] virtio-balloon: replace the coarse-grained balloon_lock

[Tetsuo Handa]

Wei Wang wrote:
> The balloon_lock was used to synchronize the access demand to elements
> of struct virtio_balloon and its queue operations (please see commit
> e22504296d). This prevents the concurrent run of the leak_balloon and
> fill_balloon functions, thereby resulting in a deadlock issue on OOM:
> 
> fill_balloon: take balloon_lock and wait for OOM to get some memory;
> oom_notify: release some inflated memory via leak_balloon();
> leak_balloon: wait for balloon_lock to be released by fill_balloon.
> 
> This patch breaks the lock into two fine-grained inflate_lock and
> deflate_lock, and eliminates the unnecessary use of the shared data
> (i.e. vb->pnfs, vb->num_pfns). This enables leak_balloon and
> fill_balloon to run concurrently and solves the deadlock issue.
> 

> @@ -162,20 +160,20 @@ static unsigned fill_balloon(struct virtio_balloon *vb, 
> size_t num)
>   msleep(200);
>   break;
>   }
> - set_page_pfns(vb, vb->pfns + vb->num_pfns, page);
> - vb->num_pages += VIRTIO_BALLOON_PAGES_PER_PAGE;
> + set_page_pfns(vb, pfns + num_pfns, page);
>   if (!virtio_has_feature(vb->vdev,
>   VIRTIO_BALLOON_F_DEFLATE_ON_OOM))
>   adjust_managed_page_count(page, -1);
>   }
>  
> - num_allocated_pages = vb->num_pfns;
> + mutex_lock(>inflate_lock);
>   /* Did we get any? */
> - if (vb->num_pfns != 0)
> - tell_host(vb, vb->inflate_vq);
> - mutex_unlock(>balloon_lock);
> + if (num_pfns != 0)
> + tell_host(vb, vb->inflate_vq, pfns, num_pfns);
> + mutex_unlock(>inflate_lock);
> + atomic64_add(num_pfns, >num_pages);

Isn't this addition too late? If leak_balloon() is called due to
out_of_memory(), it will fail to find up to dated vb->num_pages value.

>  
> - return num_allocated_pages;
> + return num_pfns;
>  }
>  
>  static void release_pages_balloon(struct virtio_balloon *vb,
> @@ -194,38 +192,39 @@ static void release_pages_balloon(struct virtio_balloon 
> *vb,
>  
>  static unsigned leak_balloon(struct virtio_balloon *vb, size_t num)
>  {
> - unsigned num_freed_pages;
>   struct page *page;
>   struct balloon_dev_info *vb_dev_info = >vb_dev_info;
>   LIST_HEAD(pages);
> + unsigned int num_pfns;
> + __virtio32 pfns[VIRTIO_BALLOON_ARRAY_PFNS_MAX];

This array consumes 1024 bytes of kernel stack, doesn't it?
leak_balloon() might be called from out_of_memory() where kernel stack
is already largely consumed before entering __alloc_pages_nodemask().
For reducing possibility of stack overflow, since out_of_memory() is
serialized by oom_lock, I suggest using static (maybe kmalloc()ed as
vb->oom_pfns[VIRTIO_BALLOON_ARRAY_PFNS_MAX]) buffer when called from
out_of_memory().

>  
>   /* We can only do one array worth at a time. */
> - num = min(num, ARRAY_SIZE(vb->pfns));
> + num = min_t(size_t, num, VIRTIO_BALLOON_ARRAY_PFNS_MAX);
>  
> - mutex_lock(>balloon_lock);
>   /* We can't release more pages than taken */
> - num = min(num, (size_t)vb->num_pages);
> - for (vb->num_pfns = 0; vb->num_pfns < num;
> -  vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) {
> + num = min_t(size_t, num, atomic64_read(>num_pages));
> + for (num_pfns = 0; num_pfns < num;
> +  num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) {
>   page = balloon_page_dequeue(vb_dev_info);

If balloon_page_dequeue() can be concurrently called by both host's request
and guest's OOM event, is (!dequeued_page) test in balloon_page_dequeue() safe?
Is such concurrency needed?

>   if (!page)
>   break;
> - set_page_pfns(vb, vb->pfns + vb->num_pfns, page);
> + set_page_pfns(vb, pfns + num_pfns, page);
>   list_add(>lru, );
> - vb->num_pages -= VIRTIO_BALLOON_PAGES_PER_PAGE;
>   }
>  
> - num_freed_pages = vb->num_pfns;
>   /*
>* Note that if
>* virtio_has_feature(vdev, VIRTIO_BALLOON_F_MUST_TELL_HOST);
>* is true, we *have* to do it in this order
>*/
> - if (vb->num_pfns != 0)
> - tell_host(vb, vb->deflate_vq);
> + mutex_lock(>deflate_lock);
> + if (num_pfns != 0)
> + tell_host(vb, vb->deflate_vq, pfns, num_pfns);
> + mutex_unlock(>deflate_lock);
>   release_pages_balloon(vb, );
> - mutex_unlock(>balloon_lock);
> - return num_freed_pages;
> + atomic64_sub(num_pfns, >num_pages);

Isn't this subtraction too late?

> +
> + return num_pfns;
>  }
>  
>  static inline void update_stat(struct virtio_balloon *vb, int idx,

> @@ -465,6 +464,7 @@ static int virtballoon_migratepage(struct 
> balloon_dev_info *vb_dev_info,
>   struct virtio_balloon *vb = container_of(vb_dev_info,
>   struct virtio_balloon, vb_dev_info);
>   unsigned long flags;
> + __virtio32 

Re: [PATCH v1 1/3] virtio-balloon: replace the coarse-grained balloon_lock

[Tetsuo Handa]

Wei Wang wrote:
> The balloon_lock was used to synchronize the access demand to elements
> of struct virtio_balloon and its queue operations (please see commit
> e22504296d). This prevents the concurrent run of the leak_balloon and
> fill_balloon functions, thereby resulting in a deadlock issue on OOM:
> 
> fill_balloon: take balloon_lock and wait for OOM to get some memory;
> oom_notify: release some inflated memory via leak_balloon();
> leak_balloon: wait for balloon_lock to be released by fill_balloon.
> 
> This patch breaks the lock into two fine-grained inflate_lock and
> deflate_lock, and eliminates the unnecessary use of the shared data
> (i.e. vb->pnfs, vb->num_pfns). This enables leak_balloon and
> fill_balloon to run concurrently and solves the deadlock issue.
> 

> @@ -162,20 +160,20 @@ static unsigned fill_balloon(struct virtio_balloon *vb, 
> size_t num)
>   msleep(200);
>   break;
>   }
> - set_page_pfns(vb, vb->pfns + vb->num_pfns, page);
> - vb->num_pages += VIRTIO_BALLOON_PAGES_PER_PAGE;
> + set_page_pfns(vb, pfns + num_pfns, page);
>   if (!virtio_has_feature(vb->vdev,
>   VIRTIO_BALLOON_F_DEFLATE_ON_OOM))
>   adjust_managed_page_count(page, -1);
>   }
>  
> - num_allocated_pages = vb->num_pfns;
> + mutex_lock(>inflate_lock);
>   /* Did we get any? */
> - if (vb->num_pfns != 0)
> - tell_host(vb, vb->inflate_vq);
> - mutex_unlock(>balloon_lock);
> + if (num_pfns != 0)
> + tell_host(vb, vb->inflate_vq, pfns, num_pfns);
> + mutex_unlock(>inflate_lock);
> + atomic64_add(num_pfns, >num_pages);

Isn't this addition too late? If leak_balloon() is called due to
out_of_memory(), it will fail to find up to dated vb->num_pages value.

>  
> - return num_allocated_pages;
> + return num_pfns;
>  }
>  
>  static void release_pages_balloon(struct virtio_balloon *vb,
> @@ -194,38 +192,39 @@ static void release_pages_balloon(struct virtio_balloon 
> *vb,
>  
>  static unsigned leak_balloon(struct virtio_balloon *vb, size_t num)
>  {
> - unsigned num_freed_pages;
>   struct page *page;
>   struct balloon_dev_info *vb_dev_info = >vb_dev_info;
>   LIST_HEAD(pages);
> + unsigned int num_pfns;
> + __virtio32 pfns[VIRTIO_BALLOON_ARRAY_PFNS_MAX];

This array consumes 1024 bytes of kernel stack, doesn't it?
leak_balloon() might be called from out_of_memory() where kernel stack
is already largely consumed before entering __alloc_pages_nodemask().
For reducing possibility of stack overflow, since out_of_memory() is
serialized by oom_lock, I suggest using static (maybe kmalloc()ed as
vb->oom_pfns[VIRTIO_BALLOON_ARRAY_PFNS_MAX]) buffer when called from
out_of_memory().

>  
>   /* We can only do one array worth at a time. */
> - num = min(num, ARRAY_SIZE(vb->pfns));
> + num = min_t(size_t, num, VIRTIO_BALLOON_ARRAY_PFNS_MAX);
>  
> - mutex_lock(>balloon_lock);
>   /* We can't release more pages than taken */
> - num = min(num, (size_t)vb->num_pages);
> - for (vb->num_pfns = 0; vb->num_pfns < num;
> -  vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) {
> + num = min_t(size_t, num, atomic64_read(>num_pages));
> + for (num_pfns = 0; num_pfns < num;
> +  num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) {
>   page = balloon_page_dequeue(vb_dev_info);

If balloon_page_dequeue() can be concurrently called by both host's request
and guest's OOM event, is (!dequeued_page) test in balloon_page_dequeue() safe?
Is such concurrency needed?

>   if (!page)
>   break;
> - set_page_pfns(vb, vb->pfns + vb->num_pfns, page);
> + set_page_pfns(vb, pfns + num_pfns, page);
>   list_add(>lru, );
> - vb->num_pages -= VIRTIO_BALLOON_PAGES_PER_PAGE;
>   }
>  
> - num_freed_pages = vb->num_pfns;
>   /*
>* Note that if
>* virtio_has_feature(vdev, VIRTIO_BALLOON_F_MUST_TELL_HOST);
>* is true, we *have* to do it in this order
>*/
> - if (vb->num_pfns != 0)
> - tell_host(vb, vb->deflate_vq);
> + mutex_lock(>deflate_lock);
> + if (num_pfns != 0)
> + tell_host(vb, vb->deflate_vq, pfns, num_pfns);
> + mutex_unlock(>deflate_lock);
>   release_pages_balloon(vb, );
> - mutex_unlock(>balloon_lock);
> - return num_freed_pages;
> + atomic64_sub(num_pfns, >num_pages);

Isn't this subtraction too late?

> +
> + return num_pfns;
>  }
>  
>  static inline void update_stat(struct virtio_balloon *vb, int idx,

> @@ -465,6 +464,7 @@ static int virtballoon_migratepage(struct 
> balloon_dev_info *vb_dev_info,
>   struct virtio_balloon *vb = container_of(vb_dev_info,
>   struct virtio_balloon, vb_dev_info);
>   unsigned long flags;
> + __virtio32 

Re: [PATCH 2/2] soc: mediatek: pwrap: fix fatal compiler error

[Sean Wang]

On Sat, 2017-10-21 at 10:25 +0200, Matthias Brugger wrote:
> When adding the MT6380 compatible, the sentinel for of_device_id was
> deleted, which leades to the following compiler error:
> FATAL: drivers/soc/mediatek/mtk-pmic-wrap: struct of_device_id is not 
> terminated with a NULL entry!
> 
> Fix this by adding the sentinel again.
> 
> Signed-off-by: Matthias Brugger 
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c 
> b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 912edf93c192..e9e054a15b7d 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -1380,6 +1380,7 @@ static const struct of_device_id of_slave_match_tbl[] = 
> {
>   }, {
>   .compatible = "mediatek,mt6397",
>   .data = _mt6397,
> + }, {
>   /* sentinel */
>   }
>  };

Thanks for patching the mistaken edit I made.

Acked-by: Sean Wang 

Re: [PATCH 2/2] soc: mediatek: pwrap: fix fatal compiler error

[Sean Wang]

On Sat, 2017-10-21 at 10:25 +0200, Matthias Brugger wrote:
> When adding the MT6380 compatible, the sentinel for of_device_id was
> deleted, which leades to the following compiler error:
> FATAL: drivers/soc/mediatek/mtk-pmic-wrap: struct of_device_id is not 
> terminated with a NULL entry!
> 
> Fix this by adding the sentinel again.
> 
> Signed-off-by: Matthias Brugger 
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c 
> b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 912edf93c192..e9e054a15b7d 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -1380,6 +1380,7 @@ static const struct of_device_id of_slave_match_tbl[] = 
> {
>   }, {
>   .compatible = "mediatek,mt6397",
>   .data = _mt6397,
> + }, {
>   /* sentinel */
>   }
>  };

Thanks for patching the mistaken edit I made.

Acked-by: Sean Wang 

Re: [PATCH v1 2/3] virtio-balloon: deflate up to oom_pages on OOM

[Tetsuo Handa]

Michael S. Tsirkin wrote:
> On Fri, Oct 20, 2017 at 07:54:25PM +0800, Wei Wang wrote:
> > The current implementation only deflates 256 pages even when a user
> > specifies more than that via the oom_pages module param. This patch
> > enables the deflating of up to oom_pages pages if there are enough
> > inflated pages.
> 
> This seems reasonable. Does this by itself help?

At least

> > -   num_freed_pages = leak_balloon(vb, oom_pages);
> > +
> > +   /* Don't deflate more than the number of inflated pages */
> > +   while (npages && atomic64_read(>num_pages))
> > +   npages -= leak_balloon(vb, npages);

don't we need to abort if leak_balloon() returned 0 for some reason?

Re: [PATCH v1 2/3] virtio-balloon: deflate up to oom_pages on OOM

[Tetsuo Handa]

Michael S. Tsirkin wrote:
> On Fri, Oct 20, 2017 at 07:54:25PM +0800, Wei Wang wrote:
> > The current implementation only deflates 256 pages even when a user
> > specifies more than that via the oom_pages module param. This patch
> > enables the deflating of up to oom_pages pages if there are enough
> > inflated pages.
> 
> This seems reasonable. Does this by itself help?

At least

> > -   num_freed_pages = leak_balloon(vb, oom_pages);
> > +
> > +   /* Don't deflate more than the number of inflated pages */
> > +   while (npages && atomic64_read(>num_pages))
> > +   npages -= leak_balloon(vb, npages);

don't we need to abort if leak_balloon() returned 0 for some reason?

RE: [PATCH 02/15] drivers, net, ethernet: convert mtk_eth.dma_refcnt from atomic_t to refcount_t

[Sean Wang]

On Fri, 2017-10-20 at 10:37 +, Reshetova, Elena wrote:
> > On Fri, 2017-10-20 at 10:23 +0300, Elena Reshetova wrote:
> > > atomic_t variables are currently used to implement reference
> > > counters with the following properties:
> > >  - counter is initialized to 1 using atomic_set()
> > >  - a resource is freed upon counter reaching zero
> > >  - once counter reaches zero, its further
> > >increments aren't allowed
> > >  - counter schema uses basic atomic operations
> > >(set, inc, inc_not_zero, dec_and_test, etc.)
> > >
> > > Such atomic variables should be converted to a newly provided
> > > refcount_t type and API that prevents accidental counter overflows
> > > and underflows. This is important since overflows and underflows
> > > can lead to use-after-free situation and be exploitable.
> > >
> > > The variable mtk_eth.dma_refcnt is used as pure reference counter.
> > > Convert it to refcount_t and fix up the operations.
> > >
> > > Suggested-by: Kees Cook 
> > > Reviewed-by: David Windsor 
> > > Reviewed-by: Hans Liljestrand 
> > > Signed-off-by: Elena Reshetova 
> > > ---
> > >  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +---
> > >  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +++-
> > >  2 files changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > index 5e81a72..54adfd9 100644
> > > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > @@ -1817,7 +1817,7 @@ static int mtk_open(struct net_device *dev)
> > >   struct mtk_eth *eth = mac->hw;
> > >
> > >   /* we run 2 netdevs on the same dma ring so we only bring it up once
> > */
> > > - if (!atomic_read(>dma_refcnt)) {
> > > + if (!refcount_read(>dma_refcnt)) {
> > >   int err = mtk_start_dma(eth);
> > >
> > >   if (err)
> > > @@ -1827,8 +1827,10 @@ static int mtk_open(struct net_device *dev)
> > >   napi_enable(>rx_napi);
> > >   mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
> > >   mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
> > > + refcount_set(>dma_refcnt, 1);
> > 
> > the existing driver seems to have a missing initial atomic_set for the
> > eth->dma_refcnt.
> > 
> > >   }
> > > - atomic_inc(>dma_refcnt);
> > > + else
> > > + refcount_inc(>dma_refcnt);
> > >
> > 
> > how about add the initial refcount_set into probe handler, and keep
> > logic else unchanged ?
> 
> Sure, I guess you mean mtk_probe() function? I can move the refcount_set to 
> be there
> and remove this change. 
> 
> Should I resend the modified patch to you (maybe then two of the ethernet 
> patches)?
> 
> Best Regards,
> Elena.

The entire series has been applies to net-next, I think I can make the
follow-ups patches relative to your work. 

Sean

> > 
> > >   phy_start(dev->phydev);
> > >   netif_start_queue(dev);
> > > @@ -1868,7 +1870,7 @@ static int mtk_stop(struct net_device *dev)
> > >   phy_stop(dev->phydev);
> > >
> > >   /* only shutdown DMA if this is the last user */
> > > - if (!atomic_dec_and_test(>dma_refcnt))
> > > + if (!refcount_dec_and_test(>dma_refcnt))
> > >   return 0;
> > >
> > >   mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
> > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > index 3d3c24a..a3af466 100644
> > > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > @@ -15,6 +15,8 @@
> > >  #ifndef MTK_ETH_H
> > >  #define MTK_ETH_H
> > >
> > > +#include 
> > > +
> > >  #define MTK_QDMA_PAGE_SIZE   2048
> > >  #define  MTK_MAX_RX_LENGTH   1536
> > >  #define MTK_TX_DMA_BUF_LEN   0x3fff
> > > @@ -632,7 +634,7 @@ struct mtk_eth {
> > >   struct regmap   *pctl;
> > >   u32 chip_id;
> > >   boolhwlro;
> > > - atomic_tdma_refcnt;
> > > + refcount_t  dma_refcnt;
> > >   struct mtk_tx_ring  tx_ring;
> > >   struct mtk_rx_ring
> > rx_ring[MTK_MAX_RX_RING_NUM];
> > >   struct mtk_rx_ring  rx_ring_qdma;
> > 
> 

RE: [PATCH 02/15] drivers, net, ethernet: convert mtk_eth.dma_refcnt from atomic_t to refcount_t

[Sean Wang]

On Fri, 2017-10-20 at 10:37 +, Reshetova, Elena wrote:
> > On Fri, 2017-10-20 at 10:23 +0300, Elena Reshetova wrote:
> > > atomic_t variables are currently used to implement reference
> > > counters with the following properties:
> > >  - counter is initialized to 1 using atomic_set()
> > >  - a resource is freed upon counter reaching zero
> > >  - once counter reaches zero, its further
> > >increments aren't allowed
> > >  - counter schema uses basic atomic operations
> > >(set, inc, inc_not_zero, dec_and_test, etc.)
> > >
> > > Such atomic variables should be converted to a newly provided
> > > refcount_t type and API that prevents accidental counter overflows
> > > and underflows. This is important since overflows and underflows
> > > can lead to use-after-free situation and be exploitable.
> > >
> > > The variable mtk_eth.dma_refcnt is used as pure reference counter.
> > > Convert it to refcount_t and fix up the operations.
> > >
> > > Suggested-by: Kees Cook 
> > > Reviewed-by: David Windsor 
> > > Reviewed-by: Hans Liljestrand 
> > > Signed-off-by: Elena Reshetova 
> > > ---
> > >  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +---
> > >  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +++-
> > >  2 files changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > index 5e81a72..54adfd9 100644
> > > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> > > @@ -1817,7 +1817,7 @@ static int mtk_open(struct net_device *dev)
> > >   struct mtk_eth *eth = mac->hw;
> > >
> > >   /* we run 2 netdevs on the same dma ring so we only bring it up once
> > */
> > > - if (!atomic_read(>dma_refcnt)) {
> > > + if (!refcount_read(>dma_refcnt)) {
> > >   int err = mtk_start_dma(eth);
> > >
> > >   if (err)
> > > @@ -1827,8 +1827,10 @@ static int mtk_open(struct net_device *dev)
> > >   napi_enable(>rx_napi);
> > >   mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
> > >   mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
> > > + refcount_set(>dma_refcnt, 1);
> > 
> > the existing driver seems to have a missing initial atomic_set for the
> > eth->dma_refcnt.
> > 
> > >   }
> > > - atomic_inc(>dma_refcnt);
> > > + else
> > > + refcount_inc(>dma_refcnt);
> > >
> > 
> > how about add the initial refcount_set into probe handler, and keep
> > logic else unchanged ?
> 
> Sure, I guess you mean mtk_probe() function? I can move the refcount_set to 
> be there
> and remove this change. 
> 
> Should I resend the modified patch to you (maybe then two of the ethernet 
> patches)?
> 
> Best Regards,
> Elena.

The entire series has been applies to net-next, I think I can make the
follow-ups patches relative to your work. 

Sean

> > 
> > >   phy_start(dev->phydev);
> > >   netif_start_queue(dev);
> > > @@ -1868,7 +1870,7 @@ static int mtk_stop(struct net_device *dev)
> > >   phy_stop(dev->phydev);
> > >
> > >   /* only shutdown DMA if this is the last user */
> > > - if (!atomic_dec_and_test(>dma_refcnt))
> > > + if (!refcount_dec_and_test(>dma_refcnt))
> > >   return 0;
> > >
> > >   mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
> > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > index 3d3c24a..a3af466 100644
> > > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > @@ -15,6 +15,8 @@
> > >  #ifndef MTK_ETH_H
> > >  #define MTK_ETH_H
> > >
> > > +#include 
> > > +
> > >  #define MTK_QDMA_PAGE_SIZE   2048
> > >  #define  MTK_MAX_RX_LENGTH   1536
> > >  #define MTK_TX_DMA_BUF_LEN   0x3fff
> > > @@ -632,7 +634,7 @@ struct mtk_eth {
> > >   struct regmap   *pctl;
> > >   u32 chip_id;
> > >   boolhwlro;
> > > - atomic_tdma_refcnt;
> > > + refcount_t  dma_refcnt;
> > >   struct mtk_tx_ring  tx_ring;
> > >   struct mtk_rx_ring
> > rx_ring[MTK_MAX_RX_RING_NUM];
> > >   struct mtk_rx_ring  rx_ring_qdma;
> > 
> 

(*ABS*+0xbb29b267): multiple definition of `__crc___gcov_merge_add'

[kbuild test robot]

Hi Thomas,

FYI, the error/warning still remains.

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   0787643a5f6aad1f0cdeb305f7fe492b71943ea4
commit: d3488649dcd23b7a6e63895274ec69f80e92d4ed um: Fix CONFIG_GCOV for 
modules.
date:   5 weeks ago
config: um-allyesconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout d3488649dcd23b7a6e63895274ec69f80e92d4ed
# save the attached .config to linux build tree
make ARCH=um 

All errors (new ones prefixed by >>):

   kernel/gcov/base.o: In function `__crc___gcov_merge_add':
>> (*ABS*+0xbb29b267): multiple definition of `__crc___gcov_merge_add'
   kernel/gcov/base.o: In function `__crc___gcov_init':
>> (*ABS*+0xdceb3072): multiple definition of `__crc___gcov_init'

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

(*ABS*+0xbb29b267): multiple definition of `__crc___gcov_merge_add'

[kbuild test robot]

Hi Thomas,

FYI, the error/warning still remains.

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   0787643a5f6aad1f0cdeb305f7fe492b71943ea4
commit: d3488649dcd23b7a6e63895274ec69f80e92d4ed um: Fix CONFIG_GCOV for 
modules.
date:   5 weeks ago
config: um-allyesconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout d3488649dcd23b7a6e63895274ec69f80e92d4ed
# save the attached .config to linux build tree
make ARCH=um 

All errors (new ones prefixed by >>):

   kernel/gcov/base.o: In function `__crc___gcov_merge_add':
>> (*ABS*+0xbb29b267): multiple definition of `__crc___gcov_merge_add'
   kernel/gcov/base.o: In function `__crc___gcov_init':
>> (*ABS*+0xdceb3072): multiple definition of `__crc___gcov_init'

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH v2 7/9] usb: host: modify description for MTK xHCI config

[Chunfeng Yun]

Hi, Greg
On Tue, 2017-10-17 at 13:42 +0300, Mathias Nyman wrote:
> On 17.10.2017 13:20, Greg Kroah-Hartman wrote:
> > On Fri, Oct 13, 2017 at 01:32:14PM +0300, Mathias Nyman wrote:
> >> On 13.10.2017 11:26, Chunfeng Yun wrote:
> >>> Due to all MediaTek SoCs with xHCI host controller use this
> >>> driver, remove limitation for specific SoCs
> >>>
> >>> Signed-off-by: Chunfeng Yun 
> >>> ---
> >>
> >> xHCI parts of series look good to me, If Rob Herring agrees with the
> >> dt changes I can send it forward
> >
> > If you ack them, I can just take the whole series as-is.
> >
It would be great if you could take this series when you have time.

Thanks a lot

> 
> Acked-by: Mathias Nyman 
> 

Re: [PATCH v2 7/9] usb: host: modify description for MTK xHCI config

[Chunfeng Yun]

Hi, Greg
On Tue, 2017-10-17 at 13:42 +0300, Mathias Nyman wrote:
> On 17.10.2017 13:20, Greg Kroah-Hartman wrote:
> > On Fri, Oct 13, 2017 at 01:32:14PM +0300, Mathias Nyman wrote:
> >> On 13.10.2017 11:26, Chunfeng Yun wrote:
> >>> Due to all MediaTek SoCs with xHCI host controller use this
> >>> driver, remove limitation for specific SoCs
> >>>
> >>> Signed-off-by: Chunfeng Yun 
> >>> ---
> >>
> >> xHCI parts of series look good to me, If Rob Herring agrees with the
> >> dt changes I can send it forward
> >
> > If you ack them, I can just take the whole series as-is.
> >
It would be great if you could take this series when you have time.

Thanks a lot

> 
> Acked-by: Mathias Nyman 
> 

Re: [PATCH v1 2/3] virtio-balloon: deflate up to oom_pages on OOM

[Michael S. Tsirkin]

On Fri, Oct 20, 2017 at 07:54:25PM +0800, Wei Wang wrote:
> The current implementation only deflates 256 pages even when a user
> specifies more than that via the oom_pages module param. This patch
> enables the deflating of up to oom_pages pages if there are enough
> inflated pages.
> 
> Signed-off-by: Wei Wang 
> Cc: Michael S. Tsirkin 
> Cc: Michal Hocko 
> Cc: Tetsuo Handa 

This seems reasonable. Does this by itself help?


> ---
>  drivers/virtio/virtio_balloon.c | 14 +-
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c
> index 1ecd15a..ab55cf8 100644
> --- a/drivers/virtio/virtio_balloon.c
> +++ b/drivers/virtio/virtio_balloon.c
> @@ -43,8 +43,8 @@
>  #define OOM_VBALLOON_DEFAULT_PAGES 256
>  #define VIRTBALLOON_OOM_NOTIFY_PRIORITY 80
>  
> -static int oom_pages = OOM_VBALLOON_DEFAULT_PAGES;
> -module_param(oom_pages, int, S_IRUSR | S_IWUSR);
> +static unsigned int oom_pages = OOM_VBALLOON_DEFAULT_PAGES;
> +module_param(oom_pages, uint, 0600);
>  MODULE_PARM_DESC(oom_pages, "pages to free on OOM");
>  
>  #ifdef CONFIG_BALLOON_COMPACTION
> @@ -359,16 +359,20 @@ static int virtballoon_oom_notify(struct notifier_block 
> *self,
>  {
>   struct virtio_balloon *vb;
>   unsigned long *freed;
> - unsigned num_freed_pages;
> + unsigned int npages = oom_pages;
>  
>   vb = container_of(self, struct virtio_balloon, nb);
>   if (!virtio_has_feature(vb->vdev, VIRTIO_BALLOON_F_DEFLATE_ON_OOM))
>   return NOTIFY_OK;
>  
>   freed = parm;
> - num_freed_pages = leak_balloon(vb, oom_pages);
> +
> + /* Don't deflate more than the number of inflated pages */
> + while (npages && atomic64_read(>num_pages))
> + npages -= leak_balloon(vb, npages);
> +
>   update_balloon_size(vb);
> - *freed += num_freed_pages;
> + *freed += oom_pages - npages;
>  
>   return NOTIFY_OK;
>  }
> -- 
> 2.7.4

Re: [PATCH v1 2/3] virtio-balloon: deflate up to oom_pages on OOM

[Michael S. Tsirkin]

On Fri, Oct 20, 2017 at 07:54:25PM +0800, Wei Wang wrote:
> The current implementation only deflates 256 pages even when a user
> specifies more than that via the oom_pages module param. This patch
> enables the deflating of up to oom_pages pages if there are enough
> inflated pages.
> 
> Signed-off-by: Wei Wang 
> Cc: Michael S. Tsirkin 
> Cc: Michal Hocko 
> Cc: Tetsuo Handa 

This seems reasonable. Does this by itself help?


> ---
>  drivers/virtio/virtio_balloon.c | 14 +-
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c
> index 1ecd15a..ab55cf8 100644
> --- a/drivers/virtio/virtio_balloon.c
> +++ b/drivers/virtio/virtio_balloon.c
> @@ -43,8 +43,8 @@
>  #define OOM_VBALLOON_DEFAULT_PAGES 256
>  #define VIRTBALLOON_OOM_NOTIFY_PRIORITY 80
>  
> -static int oom_pages = OOM_VBALLOON_DEFAULT_PAGES;
> -module_param(oom_pages, int, S_IRUSR | S_IWUSR);
> +static unsigned int oom_pages = OOM_VBALLOON_DEFAULT_PAGES;
> +module_param(oom_pages, uint, 0600);
>  MODULE_PARM_DESC(oom_pages, "pages to free on OOM");
>  
>  #ifdef CONFIG_BALLOON_COMPACTION
> @@ -359,16 +359,20 @@ static int virtballoon_oom_notify(struct notifier_block 
> *self,
>  {
>   struct virtio_balloon *vb;
>   unsigned long *freed;
> - unsigned num_freed_pages;
> + unsigned int npages = oom_pages;
>  
>   vb = container_of(self, struct virtio_balloon, nb);
>   if (!virtio_has_feature(vb->vdev, VIRTIO_BALLOON_F_DEFLATE_ON_OOM))
>   return NOTIFY_OK;
>  
>   freed = parm;
> - num_freed_pages = leak_balloon(vb, oom_pages);
> +
> + /* Don't deflate more than the number of inflated pages */
> + while (npages && atomic64_read(>num_pages))
> + npages -= leak_balloon(vb, npages);
> +
>   update_balloon_size(vb);
> - *freed += num_freed_pages;
> + *freed += oom_pages - npages;
>  
>   return NOTIFY_OK;
>  }
> -- 
> 2.7.4

Re: [PATCH v1 0/3] Virtio-balloon Improvement

[Michael S. Tsirkin]

On Fri, Oct 20, 2017 at 07:54:23PM +0800, Wei Wang wrote:
> This patch series intends to summarize the recent contributions made by
> Michael S. Tsirkin, Tetsuo Handa, Michal Hocko etc. via reporting and
> discussing the related deadlock issues on the mailinglist. Please check
> each patch for details.
> 
> >From a high-level point of view, this patch series achieves:
> 1) eliminate the deadlock issue fundamentally caused by the inability
> to run leak_balloon and fill_balloon concurrently;

We need to think about this carefully. Is it an issue that
leak can now bypass fill? It seems that we can now
try to leak a page before fill was seen by host,
but I did not look into it deeply.

I really like my patch for this better at least for
current kernel. I agree we need to work more on 2+3.

> 2) enable OOM to release more than 256 inflated pages; and

Does just this help enough? How about my patch + 2?
Tetsuo, what do you think?

> 3) stop inflating when the guest is under severe memory pressure
> (i.e. OOM).

But when do we finally inflate?  Question is how does host know it needs
to resend an interrupt, and when should it do it?


> Here is an example of the benefit brought by this patch series:
> The guest sets virtio_balloon.oom_pages=10. When the host requests
> to inflate 7.9G of an 8G idle guest, the guest can still run normally
> since OOM can guarantee at least 10 pages (400MB) for the guest.
> Without the above patches, the guest will kill all the killable
> processes and fall into kernel panic finally.
> 
> Wei Wang (3):
>   virtio-balloon: replace the coarse-grained balloon_lock
>   virtio-balloon: deflate up to oom_pages on OOM
>   virtio-balloon: stop inflating when OOM occurs
> 
>  drivers/virtio/virtio_balloon.c | 149 
> 
>  1 file changed, 91 insertions(+), 58 deletions(-)
> 
> -- 
> 2.7.4

Re: [PATCH v1 0/3] Virtio-balloon Improvement

[Michael S. Tsirkin]

On Fri, Oct 20, 2017 at 07:54:23PM +0800, Wei Wang wrote:
> This patch series intends to summarize the recent contributions made by
> Michael S. Tsirkin, Tetsuo Handa, Michal Hocko etc. via reporting and
> discussing the related deadlock issues on the mailinglist. Please check
> each patch for details.
> 
> >From a high-level point of view, this patch series achieves:
> 1) eliminate the deadlock issue fundamentally caused by the inability
> to run leak_balloon and fill_balloon concurrently;

We need to think about this carefully. Is it an issue that
leak can now bypass fill? It seems that we can now
try to leak a page before fill was seen by host,
but I did not look into it deeply.

I really like my patch for this better at least for
current kernel. I agree we need to work more on 2+3.

> 2) enable OOM to release more than 256 inflated pages; and

Does just this help enough? How about my patch + 2?
Tetsuo, what do you think?

> 3) stop inflating when the guest is under severe memory pressure
> (i.e. OOM).

But when do we finally inflate?  Question is how does host know it needs
to resend an interrupt, and when should it do it?


> Here is an example of the benefit brought by this patch series:
> The guest sets virtio_balloon.oom_pages=10. When the host requests
> to inflate 7.9G of an 8G idle guest, the guest can still run normally
> since OOM can guarantee at least 10 pages (400MB) for the guest.
> Without the above patches, the guest will kill all the killable
> processes and fall into kernel panic finally.
> 
> Wei Wang (3):
>   virtio-balloon: replace the coarse-grained balloon_lock
>   virtio-balloon: deflate up to oom_pages on OOM
>   virtio-balloon: stop inflating when OOM occurs
> 
>  drivers/virtio/virtio_balloon.c | 149 
> 
>  1 file changed, 91 insertions(+), 58 deletions(-)
> 
> -- 
> 2.7.4

[PATCH v3 01/13] openrisc: use shadow registers to save regs on exception

[Stafford Horne]

From: Stefan Kristiansson 

Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.

This change is to use shadow registers for nested context.

Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.

Signed-off-by: Stefan Kristiansson 
Signed-off-by: Stafford Horne 
---

Changes since v2
 - None
Changes since v1
 - Added SMP checks in Kconfig

 arch/openrisc/Kconfig   | 11 ++
 arch/openrisc/kernel/head.S | 95 -
 2 files changed, 80 insertions(+), 26 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index a0f2e4a323c1..356dd67a86ea 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -124,6 +124,17 @@ config OPENRISC_NO_SPR_SR_DSX
  Say N here if you know that your OpenRISC processor has
  SPR_SR_DSX bit implemented. Say Y if you are unsure.
 
+config OPENRISC_HAVE_SHADOW_GPRS
+   bool "Support for shadow gpr files" if !SMP
+   default y if SMP
+   help
+ Say Y here if your OpenRISC processor features shadowed
+ register files. They will in such case be used as a
+ scratch reg storage on exception entry.
+
+ On SMP systems, this feature is mandatory.
+ On a unicore system it's safe to say N here if you are unsure.
+
 config CMDLINE
 string "Default kernel command string"
 default ""
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1e87913576e3..1e49895408f4 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -49,9 +49,31 @@
 
 /* [ tmp store locations ]=== */
 
+#define SPR_SHADOW_GPR(x)  ((x) + SPR_GPR_BASE + 32)
+
 /*
  * emergency_print temporary stores
  */
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
+#define EMERGENCY_PRINT_LOAD_GPR4  l.mfspr r4,r0,SPR_SHADOW_GPR(14)
+
+#define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
+#define EMERGENCY_PRINT_LOAD_GPR5  l.mfspr r5,r0,SPR_SHADOW_GPR(15)
+
+#define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
+#define EMERGENCY_PRINT_LOAD_GPR6  l.mfspr r6,r0,SPR_SHADOW_GPR(16)
+
+#define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
+#define EMERGENCY_PRINT_LOAD_GPR7  l.mfspr r7,r0,SPR_SHADOW_GPR(7)
+
+#define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
+#define EMERGENCY_PRINT_LOAD_GPR8  l.mfspr r8,r0,SPR_SHADOW_GPR(8)
+
+#define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
+#define EMERGENCY_PRINT_LOAD_GPR9  l.mfspr r9,r0,SPR_SHADOW_GPR(9)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EMERGENCY_PRINT_STORE_GPR4 l.sw0x20(r0),r4
 #define EMERGENCY_PRINT_LOAD_GPR4  l.lwz   r4,0x20(r0)
 
@@ -70,13 +92,28 @@
 #define EMERGENCY_PRINT_STORE_GPR9 l.sw0x34(r0),r9
 #define EMERGENCY_PRINT_LOAD_GPR9  l.lwz   r9,0x34(r0)
 
+#endif
 
 /*
  * TLB miss handlers temorary stores
  */
-#define EXCEPTION_STORE_GPR9   l.sw0x10(r0),r9
-#define EXCEPTION_LOAD_GPR9l.lwz   r9,0x10(r0)
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_STORE_GPR2   l.mtspr r0,r2,SPR_SHADOW_GPR(2)
+#define EXCEPTION_LOAD_GPR2l.mfspr r2,r0,SPR_SHADOW_GPR(2)
+
+#define EXCEPTION_STORE_GPR3   l.mtspr r0,r3,SPR_SHADOW_GPR(3)
+#define EXCEPTION_LOAD_GPR3l.mfspr r3,r0,SPR_SHADOW_GPR(3)
 
+#define EXCEPTION_STORE_GPR4   l.mtspr r0,r4,SPR_SHADOW_GPR(4)
+#define EXCEPTION_LOAD_GPR4l.mfspr r4,r0,SPR_SHADOW_GPR(4)
+
+#define EXCEPTION_STORE_GPR5   l.mtspr r0,r5,SPR_SHADOW_GPR(5)
+#define EXCEPTION_LOAD_GPR5l.mfspr r5,r0,SPR_SHADOW_GPR(5)
+
+#define EXCEPTION_STORE_GPR6   l.mtspr r0,r6,SPR_SHADOW_GPR(6)
+#define EXCEPTION_LOAD_GPR6l.mfspr r6,r0,SPR_SHADOW_GPR(6)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EXCEPTION_STORE_GPR2   l.sw0x64(r0),r2
 #define EXCEPTION_LOAD_GPR2l.lwz   r2,0x64(r0)
 
@@ -92,26 +129,32 @@
 #define EXCEPTION_STORE_GPR6   l.sw0x74(r0),r6
 #define EXCEPTION_LOAD_GPR6l.lwz   r6,0x74(r0)
 
+#endif
 
 /*
  * EXCEPTION_HANDLE temporary stores
  */
 
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_T_STORE_GPR30l.mtspr 
r0,r30,SPR_SHADOW_GPR(30)
+#define EXCEPTION_T_LOAD_GPR30(reg)l.mfspr reg,r0,SPR_SHADOW_GPR(30)
+
+#define EXCEPTION_T_STORE_GPR10l.mtspr 
r0,r10,SPR_SHADOW_GPR(10)
+#define EXCEPTION_T_LOAD_GPR10(reg)l.mfspr 

[PATCH v3 01/13] openrisc: use shadow registers to save regs on exception

[Stafford Horne]

From: Stefan Kristiansson 

Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.

This change is to use shadow registers for nested context.

Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.

Signed-off-by: Stefan Kristiansson 
Signed-off-by: Stafford Horne 
---

Changes since v2
 - None
Changes since v1
 - Added SMP checks in Kconfig

 arch/openrisc/Kconfig   | 11 ++
 arch/openrisc/kernel/head.S | 95 -
 2 files changed, 80 insertions(+), 26 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index a0f2e4a323c1..356dd67a86ea 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -124,6 +124,17 @@ config OPENRISC_NO_SPR_SR_DSX
  Say N here if you know that your OpenRISC processor has
  SPR_SR_DSX bit implemented. Say Y if you are unsure.
 
+config OPENRISC_HAVE_SHADOW_GPRS
+   bool "Support for shadow gpr files" if !SMP
+   default y if SMP
+   help
+ Say Y here if your OpenRISC processor features shadowed
+ register files. They will in such case be used as a
+ scratch reg storage on exception entry.
+
+ On SMP systems, this feature is mandatory.
+ On a unicore system it's safe to say N here if you are unsure.
+
 config CMDLINE
 string "Default kernel command string"
 default ""
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1e87913576e3..1e49895408f4 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -49,9 +49,31 @@
 
 /* [ tmp store locations ]=== */
 
+#define SPR_SHADOW_GPR(x)  ((x) + SPR_GPR_BASE + 32)
+
 /*
  * emergency_print temporary stores
  */
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
+#define EMERGENCY_PRINT_LOAD_GPR4  l.mfspr r4,r0,SPR_SHADOW_GPR(14)
+
+#define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
+#define EMERGENCY_PRINT_LOAD_GPR5  l.mfspr r5,r0,SPR_SHADOW_GPR(15)
+
+#define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
+#define EMERGENCY_PRINT_LOAD_GPR6  l.mfspr r6,r0,SPR_SHADOW_GPR(16)
+
+#define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
+#define EMERGENCY_PRINT_LOAD_GPR7  l.mfspr r7,r0,SPR_SHADOW_GPR(7)
+
+#define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
+#define EMERGENCY_PRINT_LOAD_GPR8  l.mfspr r8,r0,SPR_SHADOW_GPR(8)
+
+#define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
+#define EMERGENCY_PRINT_LOAD_GPR9  l.mfspr r9,r0,SPR_SHADOW_GPR(9)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EMERGENCY_PRINT_STORE_GPR4 l.sw0x20(r0),r4
 #define EMERGENCY_PRINT_LOAD_GPR4  l.lwz   r4,0x20(r0)
 
@@ -70,13 +92,28 @@
 #define EMERGENCY_PRINT_STORE_GPR9 l.sw0x34(r0),r9
 #define EMERGENCY_PRINT_LOAD_GPR9  l.lwz   r9,0x34(r0)
 
+#endif
 
 /*
  * TLB miss handlers temorary stores
  */
-#define EXCEPTION_STORE_GPR9   l.sw0x10(r0),r9
-#define EXCEPTION_LOAD_GPR9l.lwz   r9,0x10(r0)
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_STORE_GPR2   l.mtspr r0,r2,SPR_SHADOW_GPR(2)
+#define EXCEPTION_LOAD_GPR2l.mfspr r2,r0,SPR_SHADOW_GPR(2)
+
+#define EXCEPTION_STORE_GPR3   l.mtspr r0,r3,SPR_SHADOW_GPR(3)
+#define EXCEPTION_LOAD_GPR3l.mfspr r3,r0,SPR_SHADOW_GPR(3)
 
+#define EXCEPTION_STORE_GPR4   l.mtspr r0,r4,SPR_SHADOW_GPR(4)
+#define EXCEPTION_LOAD_GPR4l.mfspr r4,r0,SPR_SHADOW_GPR(4)
+
+#define EXCEPTION_STORE_GPR5   l.mtspr r0,r5,SPR_SHADOW_GPR(5)
+#define EXCEPTION_LOAD_GPR5l.mfspr r5,r0,SPR_SHADOW_GPR(5)
+
+#define EXCEPTION_STORE_GPR6   l.mtspr r0,r6,SPR_SHADOW_GPR(6)
+#define EXCEPTION_LOAD_GPR6l.mfspr r6,r0,SPR_SHADOW_GPR(6)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EXCEPTION_STORE_GPR2   l.sw0x64(r0),r2
 #define EXCEPTION_LOAD_GPR2l.lwz   r2,0x64(r0)
 
@@ -92,26 +129,32 @@
 #define EXCEPTION_STORE_GPR6   l.sw0x74(r0),r6
 #define EXCEPTION_LOAD_GPR6l.lwz   r6,0x74(r0)
 
+#endif
 
 /*
  * EXCEPTION_HANDLE temporary stores
  */
 
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_T_STORE_GPR30l.mtspr 
r0,r30,SPR_SHADOW_GPR(30)
+#define EXCEPTION_T_LOAD_GPR30(reg)l.mfspr reg,r0,SPR_SHADOW_GPR(30)
+
+#define EXCEPTION_T_STORE_GPR10l.mtspr 
r0,r10,SPR_SHADOW_GPR(10)
+#define EXCEPTION_T_LOAD_GPR10(reg)l.mfspr reg,r0,SPR_SHADOW_GPR(10)
+
+#define EXCEPTION_T_STORE_SP   l.mtspr 

[PATCH v3 13/13] openrisc: add tick timer multi-core sync logic

[Stafford Horne]

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu.  This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - change from timer-sync.h header to just time.h

 arch/openrisc/include/asm/time.h  |   8 +++
 arch/openrisc/kernel/Makefile |   2 +-
 arch/openrisc/kernel/smp.c|   3 +
 arch/openrisc/kernel/sync-timer.c | 120 ++
 arch/openrisc/kernel/time.c   |  15 -
 5 files changed, 145 insertions(+), 3 deletions(-)
 create mode 100644 arch/openrisc/kernel/sync-timer.c

diff --git a/arch/openrisc/include/asm/time.h b/arch/openrisc/include/asm/time.h
index fe83a34a7d68..313ee975774b 100644
--- a/arch/openrisc/include/asm/time.h
+++ b/arch/openrisc/include/asm/time.h
@@ -12,4 +12,12 @@
 
 extern void openrisc_clockevent_init(void);
 
+extern void openrisc_timer_set(unsigned long count);
+extern void openrisc_timer_set_next(unsigned long delta);
+
+#ifdef CONFIG_SMP
+extern void synchronise_count_master(int cpu);
+extern void synchronise_count_slave(int cpu);
+#endif
+
 #endif /* __ASM_OR1K_TIME_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index b4b51a07016a..9028e5a1fdd7 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -8,7 +8,7 @@ obj-y   := setup.o or32_ksyms.o process.o dma.o \
   traps.o time.o irq.o entry.o ptrace.o signal.o \
   sys_call_table.o unwinder.o
 
-obj-$(CONFIG_SMP)  += smp.o
+obj-$(CONFIG_SMP)  += smp.o sync-timer.o
 obj-$(CONFIG_STACKTRACE)   += stacktrace.o
 obj-$(CONFIG_MODULES)  += module.o
 obj-$(CONFIG_OF)   += prom.o
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 4763b8b9161e..4d80ce6fa045 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -100,6 +100,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
pr_crit("CPU%u: failed to start\n", cpu);
return -EIO;
}
+   synchronise_count_master(cpu);
 
return 0;
 }
@@ -129,6 +130,8 @@ asmlinkage __init void secondary_start_kernel(void)
set_cpu_online(cpu, true);
complete(_running);
 
+   synchronise_count_slave(cpu);
+
local_irq_enable();
 
preempt_disable();
diff --git a/arch/openrisc/kernel/sync-timer.c 
b/arch/openrisc/kernel/sync-timer.c
new file mode 100644
index ..ed8d835caca1
--- /dev/null
+++ b/arch/openrisc/kernel/sync-timer.c
@@ -0,0 +1,120 @@
+/*
+ * OR1K timer synchronisation
+ *
+ * Based on work from MIPS implementation.
+ *
+ * All CPUs will have their count registers synchronised to the CPU0 next time
+ * value. This can cause a small timewarp for CPU0. All other CPU's should
+ * not have done anything significant (but they may have had interrupts
+ * enabled briefly - prom_smp_finish() should not be responsible for enabling
+ * interrupts...)
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+static unsigned int initcount;
+static atomic_t count_count_start = ATOMIC_INIT(0);
+static atomic_t count_count_stop = ATOMIC_INIT(0);
+
+#define COUNTON 100
+#define NR_LOOPS 3
+
+void synchronise_count_master(int cpu)
+{
+   int i;
+   unsigned long flags;
+
+   pr_info("Synchronize counters for CPU %u: ", cpu);
+
+   local_irq_save(flags);
+
+   /*
+* We loop a few times to get a primed instruction cache,
+* then the last pass is more or less synchronised and
+* the master and slaves each set their cycle counters to a known
+* value all at once. This reduces the chance of having random offsets
+* between the processors, and guarantees that the maximum
+* delay between the cycle counters is never bigger than
+* the latency of information-passing (cachelines) between
+* two CPUs.
+*/
+
+   for (i = 0; i < NR_LOOPS; i++) {
+   /* slaves loop on '!= 2' */
+   while (atomic_read(_count_start) != 1)
+   mb();
+   atomic_set(_count_stop, 0);
+   smp_wmb();
+
+   /* Let the slave writes its count register */
+   atomic_inc(_count_start);
+
+   /* Count will be initialised to current timer */
+   if (i == 1)
+   initcount = get_cycles();
+
+   /*
+* Everyone initialises count in the last loop:
+*/
+   if (i == NR_LOOPS-1)
+   openrisc_timer_set(initcount);
+
+   /*
+  

[PATCH v3 13/13] openrisc: add tick timer multi-core sync logic

[Stafford Horne]

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu.  This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - change from timer-sync.h header to just time.h

 arch/openrisc/include/asm/time.h  |   8 +++
 arch/openrisc/kernel/Makefile |   2 +-
 arch/openrisc/kernel/smp.c|   3 +
 arch/openrisc/kernel/sync-timer.c | 120 ++
 arch/openrisc/kernel/time.c   |  15 -
 5 files changed, 145 insertions(+), 3 deletions(-)
 create mode 100644 arch/openrisc/kernel/sync-timer.c

diff --git a/arch/openrisc/include/asm/time.h b/arch/openrisc/include/asm/time.h
index fe83a34a7d68..313ee975774b 100644
--- a/arch/openrisc/include/asm/time.h
+++ b/arch/openrisc/include/asm/time.h
@@ -12,4 +12,12 @@
 
 extern void openrisc_clockevent_init(void);
 
+extern void openrisc_timer_set(unsigned long count);
+extern void openrisc_timer_set_next(unsigned long delta);
+
+#ifdef CONFIG_SMP
+extern void synchronise_count_master(int cpu);
+extern void synchronise_count_slave(int cpu);
+#endif
+
 #endif /* __ASM_OR1K_TIME_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index b4b51a07016a..9028e5a1fdd7 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -8,7 +8,7 @@ obj-y   := setup.o or32_ksyms.o process.o dma.o \
   traps.o time.o irq.o entry.o ptrace.o signal.o \
   sys_call_table.o unwinder.o
 
-obj-$(CONFIG_SMP)  += smp.o
+obj-$(CONFIG_SMP)  += smp.o sync-timer.o
 obj-$(CONFIG_STACKTRACE)   += stacktrace.o
 obj-$(CONFIG_MODULES)  += module.o
 obj-$(CONFIG_OF)   += prom.o
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 4763b8b9161e..4d80ce6fa045 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -100,6 +100,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
pr_crit("CPU%u: failed to start\n", cpu);
return -EIO;
}
+   synchronise_count_master(cpu);
 
return 0;
 }
@@ -129,6 +130,8 @@ asmlinkage __init void secondary_start_kernel(void)
set_cpu_online(cpu, true);
complete(_running);
 
+   synchronise_count_slave(cpu);
+
local_irq_enable();
 
preempt_disable();
diff --git a/arch/openrisc/kernel/sync-timer.c 
b/arch/openrisc/kernel/sync-timer.c
new file mode 100644
index ..ed8d835caca1
--- /dev/null
+++ b/arch/openrisc/kernel/sync-timer.c
@@ -0,0 +1,120 @@
+/*
+ * OR1K timer synchronisation
+ *
+ * Based on work from MIPS implementation.
+ *
+ * All CPUs will have their count registers synchronised to the CPU0 next time
+ * value. This can cause a small timewarp for CPU0. All other CPU's should
+ * not have done anything significant (but they may have had interrupts
+ * enabled briefly - prom_smp_finish() should not be responsible for enabling
+ * interrupts...)
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+static unsigned int initcount;
+static atomic_t count_count_start = ATOMIC_INIT(0);
+static atomic_t count_count_stop = ATOMIC_INIT(0);
+
+#define COUNTON 100
+#define NR_LOOPS 3
+
+void synchronise_count_master(int cpu)
+{
+   int i;
+   unsigned long flags;
+
+   pr_info("Synchronize counters for CPU %u: ", cpu);
+
+   local_irq_save(flags);
+
+   /*
+* We loop a few times to get a primed instruction cache,
+* then the last pass is more or less synchronised and
+* the master and slaves each set their cycle counters to a known
+* value all at once. This reduces the chance of having random offsets
+* between the processors, and guarantees that the maximum
+* delay between the cycle counters is never bigger than
+* the latency of information-passing (cachelines) between
+* two CPUs.
+*/
+
+   for (i = 0; i < NR_LOOPS; i++) {
+   /* slaves loop on '!= 2' */
+   while (atomic_read(_count_start) != 1)
+   mb();
+   atomic_set(_count_stop, 0);
+   smp_wmb();
+
+   /* Let the slave writes its count register */
+   atomic_inc(_count_start);
+
+   /* Count will be initialised to current timer */
+   if (i == 1)
+   initcount = get_cycles();
+
+   /*
+* Everyone initialises count in the last loop:
+*/
+   if (i == NR_LOOPS-1)
+   openrisc_timer_set(initcount);
+
+   /*
+* Wait 

[PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT

[Stafford Horne]

For lockdep support a reliable stack trace mechanism is needed.  This
patch adds support in OpenRISC for the stacktrace framework, implemented
by a simple unwinder api.  The unwinder api supports both framepointer
and basic stack tracing.

The unwinder is now used to replace the stack_dump() implementation as
well. The new traces are inline with other architectures trace format:

 Call trace:
 [] show_stack+0x3c/0x58
 [] dump_stack+0xa8/0xe4
 [] __cpu_up+0x64/0x130
 [] bringup_cpu+0x3c/0x178
 [] cpuhp_invoke_callback+0xa8/0x1fc
 [] cpuhp_up_callbacks+0x44/0x14c
 [] cpu_up+0x14c/0x1bc
 [] smp_init+0x104/0x15c
 [] ? kernel_init+0x0/0x140
 [] kernel_init_freeable+0xbc/0x25c
 [] ? kernel_init+0x0/0x140
 [] kernel_init+0x1c/0x140
 [] ? schedule_tail+0x18/0xa0
 [] ret_from_fork+0x1c/0x9c

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig|   4 ++
 arch/openrisc/include/asm/unwinder.h |  20 +++
 arch/openrisc/kernel/Makefile|   3 +-
 arch/openrisc/kernel/stacktrace.c|  86 
 arch/openrisc/kernel/traps.c |  54 +++---
 arch/openrisc/kernel/unwinder.c  | 105 +++
 6 files changed, 224 insertions(+), 48 deletions(-)
 create mode 100644 arch/openrisc/include/asm/unwinder.h
 create mode 100644 arch/openrisc/kernel/stacktrace.c
 create mode 100644 arch/openrisc/kernel/unwinder.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index bfff04ae7f7d..399f55e82dcb 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -33,6 +33,7 @@ config OPENRISC
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
+   select ARCH_WANT_FRAME_POINTERS
 
 config CPU_BIG_ENDIAN
def_bool y
@@ -60,6 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
 config GENERIC_CSUM
 def_bool y
 
+config STACKTRACE_SUPPORT
+   def_bool y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/include/asm/unwinder.h 
b/arch/openrisc/include/asm/unwinder.h
new file mode 100644
index ..165ec6f02ab8
--- /dev/null
+++ b/arch/openrisc/include/asm/unwinder.h
@@ -0,0 +1,20 @@
+/*
+ * OpenRISC unwinder.h
+ *
+ * Architecture API for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne 
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_UNWINDER_H
+#define __ASM_OPENRISC_UNWINDER_H
+
+void unwind_stack(void *data, unsigned long *stack,
+ void (*trace)(void *data, unsigned long addr,
+   int reliable));
+
+#endif /* __ASM_OPENRISC_UNWINDER_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 7d94643c878d..b4b51a07016a 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -6,9 +6,10 @@ extra-y:= head.o vmlinux.lds
 
 obj-y  := setup.o or32_ksyms.o process.o dma.o \
   traps.o time.o irq.o entry.o ptrace.o signal.o \
-  sys_call_table.o
+  sys_call_table.o unwinder.o
 
 obj-$(CONFIG_SMP)  += smp.o
+obj-$(CONFIG_STACKTRACE)   += stacktrace.o
 obj-$(CONFIG_MODULES)  += module.o
 obj-$(CONFIG_OF)   += prom.o
 
diff --git a/arch/openrisc/kernel/stacktrace.c 
b/arch/openrisc/kernel/stacktrace.c
new file mode 100644
index ..43f140a28bc7
--- /dev/null
+++ b/arch/openrisc/kernel/stacktrace.c
@@ -0,0 +1,86 @@
+/*
+ * Stack trace utility for OpenRISC
+ *
+ * Copyright (C) 2017 Stafford Horne 
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Losely based on work from sh and powerpc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+static void
+save_stack_address(void *data, unsigned long addr, int reliable)
+{
+   struct stack_trace *trace = data;
+
+   if (!reliable)
+   return;
+
+   if (trace->skip > 0) {
+   trace->skip--;
+   return;
+   }
+
+   if (trace->nr_entries < trace->max_entries)
+   trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+   unwind_stack(trace, (unsigned long *) , save_stack_address);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+static void
+save_stack_address_nosched(void *data, unsigned long addr, int reliable)
+{
+   struct stack_trace *trace = (struct stack_trace *)data;
+
+   if (!reliable)
+   return;
+
+   if (in_sched_functions(addr))
+   return;
+
+   if (trace->skip > 0) {
+ 

[PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing

[Stafford Horne]

Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig|  3 ++
 arch/openrisc/kernel/entry.S | 74 ++--
 2 files changed, 74 insertions(+), 3 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 399f55e82dcb..f8cfb3ba9e89 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -64,6 +64,9 @@ config GENERIC_CSUM
 config STACKTRACE_SUPPORT
def_bool y
 
+config LOCKDEP_SUPPORT
+   def_bool  y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 1b7160c79646..690d55272ba6 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -42,6 +42,61 @@
 
 /* =[ macros ]=== */
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+/*
+ * Trace irq on/off creating a stack frame.
+ */
+#define TRACE_IRQS_OP(trace_op)\
+   l.sw-8(r1),r2   /* store frame pointer */   ;\
+   l.sw-4(r1),r9   /* store return address */  ;\
+   l.addi  r2,r1,0 /* move sp to fp */ ;\
+   l.jal   trace_op;\
+l.addi r1,r1,-8;\
+   l.ori   r1,r2,0 /* restore sp */;\
+   l.lwz   r9,-4(r1)   /* restore return address */;\
+   l.lwz   r2,-8(r1)   /* restore fp */;\
+/*
+ * Trace irq on/off and save registers we need that would otherwise be
+ * clobbered.
+ */
+#define TRACE_IRQS_SAVE(t1,trace_op)   \
+   l.sw-12(r1),t1  /* save extra reg */;\
+   l.sw-8(r1),r2   /* store frame pointer */   ;\
+   l.sw-4(r1),r9   /* store return address */  ;\
+   l.addi  r2,r1,0 /* move sp to fp */ ;\
+   l.jal   trace_op;\
+l.addi r1,r1,-12   ;\
+   l.ori   r1,r2,0 /* restore sp */;\
+   l.lwz   r9,-4(r1)   /* restore return address */;\
+   l.lwz   r2,-8(r1)   /* restore fp */;\
+   l.lwz   t1,-12(r1)  /* restore extra reg */
+
+#define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
+#define TRACE_IRQS_ON  TRACE_IRQS_OP(trace_hardirqs_on)
+#define TRACE_IRQS_ON_SYSCALL  \
+   TRACE_IRQS_SAVE(r10,trace_hardirqs_on)  ;\
+   l.lwz   r3,PT_GPR3(r1)  ;\
+   l.lwz   r4,PT_GPR4(r1)  ;\
+   l.lwz   r5,PT_GPR5(r1)  ;\
+   l.lwz   r6,PT_GPR6(r1)  ;\
+   l.lwz   r7,PT_GPR7(r1)  ;\
+   l.lwz   r8,PT_GPR8(r1)  ;\
+   l.lwz   r11,PT_GPR11(r1)
+#define TRACE_IRQS_OFF_ENTRY   \
+   l.lwz   r5,PT_SR(r1);\
+   l.andi  r3,r5,(SPR_SR_IEE|SPR_SR_TEE)   ;\
+   l.sfeq  r5,r0   /* skip trace if irqs were already off */;\
+   l.bf1f  ;\
+l.nop  ;\
+   TRACE_IRQS_SAVE(r4,trace_hardirqs_off)  ;\
+1:
+#else
+#define TRACE_IRQS_OFF
+#define TRACE_IRQS_ON
+#define TRACE_IRQS_OFF_ENTRY
+#define TRACE_IRQS_ON_SYSCALL
+#endif
+
 /*
  * We need to disable interrupts at beginning of RESTORE_ALL
  * since interrupt might come in after we've loaded EPC return address
@@ -124,6 +179,7 @@ handler:
;\
/* r30 already save */  ;\
 /*l.swPT_GPR30(r1),r30*/   ;\
l.swPT_GPR31(r1),r31;\
+   TRACE_IRQS_OFF_ENTRY 

[PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators

[Stafford Horne]

From: Stefan Kristiansson 

Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP.  This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.

Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - Fix stdout-path

Changes since v1
 - Use openrisc, prefix for ompic
 - Add stdout-path
 - Remove @interrupt cells

 arch/openrisc/boot/dts/simple_smp.dts  | 63 
 arch/openrisc/configs/simple_smp_defconfig | 66 ++
 2 files changed, 129 insertions(+)
 create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
 create mode 100644 arch/openrisc/configs/simple_smp_defconfig

diff --git a/arch/openrisc/boot/dts/simple_smp.dts 
b/arch/openrisc/boot/dts/simple_smp.dts
new file mode 100644
index ..defbb92714ec
--- /dev/null
+++ b/arch/openrisc/boot/dts/simple_smp.dts
@@ -0,0 +1,63 @@
+/dts-v1/;
+/ {
+   compatible = "opencores,or1ksim";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   aliases {
+   uart0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "uart0:115200";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x0200>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <0>;
+   clock-frequency = <2000>;
+   };
+   cpu@1 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <1>;
+   clock-frequency = <2000>;
+   };
+   };
+
+   ompic: ompic@9800 {
+   compatible = "openrisc,ompic";
+   reg = <0x9800 16>;
+   interrupt-controller;
+   #interrupt-cells = <0>;
+   interrupts = <1>;
+   };
+
+   /*
+* OR1K PIC is built into CPU and accessed via special purpose
+* registers.  It is not addressable and, hence, has no 'reg'
+* property.
+*/
+   pic: pic {
+   compatible = "opencores,or1k-pic-level";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   serial0: serial@9000 {
+   compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+   reg = <0x9000 0x100>;
+   interrupts = <2>;
+   clock-frequency = <2000>;
+   };
+
+};
diff --git a/arch/openrisc/configs/simple_smp_defconfig 
b/arch/openrisc/configs/simple_smp_defconfig
new file mode 100644
index ..b6e3c7e158e7
--- /dev/null
+++ b/arch/openrisc/configs/simple_smp_defconfig
@@ -0,0 +1,66 @@
+CONFIG_CROSS_COMPILE="or1k-linux-"
+CONFIG_LOCALVERSION="-simple-smp"
+CONFIG_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_EPOLL is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+CONFIG_MODULES=y
+# CONFIG_BLOCK is not set
+CONFIG_OPENRISC_BUILTIN_DTB="simple_smp"
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_XZ_DEC=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_RCU_TRACE is not set
-- 
2.13.6

[PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT

[Stafford Horne]

For lockdep support a reliable stack trace mechanism is needed.  This
patch adds support in OpenRISC for the stacktrace framework, implemented
by a simple unwinder api.  The unwinder api supports both framepointer
and basic stack tracing.

The unwinder is now used to replace the stack_dump() implementation as
well. The new traces are inline with other architectures trace format:

 Call trace:
 [] show_stack+0x3c/0x58
 [] dump_stack+0xa8/0xe4
 [] __cpu_up+0x64/0x130
 [] bringup_cpu+0x3c/0x178
 [] cpuhp_invoke_callback+0xa8/0x1fc
 [] cpuhp_up_callbacks+0x44/0x14c
 [] cpu_up+0x14c/0x1bc
 [] smp_init+0x104/0x15c
 [] ? kernel_init+0x0/0x140
 [] kernel_init_freeable+0xbc/0x25c
 [] ? kernel_init+0x0/0x140
 [] kernel_init+0x1c/0x140
 [] ? schedule_tail+0x18/0xa0
 [] ret_from_fork+0x1c/0x9c

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig|   4 ++
 arch/openrisc/include/asm/unwinder.h |  20 +++
 arch/openrisc/kernel/Makefile|   3 +-
 arch/openrisc/kernel/stacktrace.c|  86 
 arch/openrisc/kernel/traps.c |  54 +++---
 arch/openrisc/kernel/unwinder.c  | 105 +++
 6 files changed, 224 insertions(+), 48 deletions(-)
 create mode 100644 arch/openrisc/include/asm/unwinder.h
 create mode 100644 arch/openrisc/kernel/stacktrace.c
 create mode 100644 arch/openrisc/kernel/unwinder.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index bfff04ae7f7d..399f55e82dcb 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -33,6 +33,7 @@ config OPENRISC
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
+   select ARCH_WANT_FRAME_POINTERS
 
 config CPU_BIG_ENDIAN
def_bool y
@@ -60,6 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
 config GENERIC_CSUM
 def_bool y
 
+config STACKTRACE_SUPPORT
+   def_bool y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/include/asm/unwinder.h 
b/arch/openrisc/include/asm/unwinder.h
new file mode 100644
index ..165ec6f02ab8
--- /dev/null
+++ b/arch/openrisc/include/asm/unwinder.h
@@ -0,0 +1,20 @@
+/*
+ * OpenRISC unwinder.h
+ *
+ * Architecture API for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne 
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_UNWINDER_H
+#define __ASM_OPENRISC_UNWINDER_H
+
+void unwind_stack(void *data, unsigned long *stack,
+ void (*trace)(void *data, unsigned long addr,
+   int reliable));
+
+#endif /* __ASM_OPENRISC_UNWINDER_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 7d94643c878d..b4b51a07016a 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -6,9 +6,10 @@ extra-y:= head.o vmlinux.lds
 
 obj-y  := setup.o or32_ksyms.o process.o dma.o \
   traps.o time.o irq.o entry.o ptrace.o signal.o \
-  sys_call_table.o
+  sys_call_table.o unwinder.o
 
 obj-$(CONFIG_SMP)  += smp.o
+obj-$(CONFIG_STACKTRACE)   += stacktrace.o
 obj-$(CONFIG_MODULES)  += module.o
 obj-$(CONFIG_OF)   += prom.o
 
diff --git a/arch/openrisc/kernel/stacktrace.c 
b/arch/openrisc/kernel/stacktrace.c
new file mode 100644
index ..43f140a28bc7
--- /dev/null
+++ b/arch/openrisc/kernel/stacktrace.c
@@ -0,0 +1,86 @@
+/*
+ * Stack trace utility for OpenRISC
+ *
+ * Copyright (C) 2017 Stafford Horne 
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Losely based on work from sh and powerpc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+static void
+save_stack_address(void *data, unsigned long addr, int reliable)
+{
+   struct stack_trace *trace = data;
+
+   if (!reliable)
+   return;
+
+   if (trace->skip > 0) {
+   trace->skip--;
+   return;
+   }
+
+   if (trace->nr_entries < trace->max_entries)
+   trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+   unwind_stack(trace, (unsigned long *) , save_stack_address);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+static void
+save_stack_address_nosched(void *data, unsigned long addr, int reliable)
+{
+   struct stack_trace *trace = (struct stack_trace *)data;
+
+   if (!reliable)
+   return;
+
+   if (in_sched_functions(addr))
+   return;
+
+   if (trace->skip > 0) {
+   trace->skip--;
+   return;

[PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing

[Stafford Horne]

Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig|  3 ++
 arch/openrisc/kernel/entry.S | 74 ++--
 2 files changed, 74 insertions(+), 3 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 399f55e82dcb..f8cfb3ba9e89 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -64,6 +64,9 @@ config GENERIC_CSUM
 config STACKTRACE_SUPPORT
def_bool y
 
+config LOCKDEP_SUPPORT
+   def_bool  y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 1b7160c79646..690d55272ba6 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -42,6 +42,61 @@
 
 /* =[ macros ]=== */
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+/*
+ * Trace irq on/off creating a stack frame.
+ */
+#define TRACE_IRQS_OP(trace_op)\
+   l.sw-8(r1),r2   /* store frame pointer */   ;\
+   l.sw-4(r1),r9   /* store return address */  ;\
+   l.addi  r2,r1,0 /* move sp to fp */ ;\
+   l.jal   trace_op;\
+l.addi r1,r1,-8;\
+   l.ori   r1,r2,0 /* restore sp */;\
+   l.lwz   r9,-4(r1)   /* restore return address */;\
+   l.lwz   r2,-8(r1)   /* restore fp */;\
+/*
+ * Trace irq on/off and save registers we need that would otherwise be
+ * clobbered.
+ */
+#define TRACE_IRQS_SAVE(t1,trace_op)   \
+   l.sw-12(r1),t1  /* save extra reg */;\
+   l.sw-8(r1),r2   /* store frame pointer */   ;\
+   l.sw-4(r1),r9   /* store return address */  ;\
+   l.addi  r2,r1,0 /* move sp to fp */ ;\
+   l.jal   trace_op;\
+l.addi r1,r1,-12   ;\
+   l.ori   r1,r2,0 /* restore sp */;\
+   l.lwz   r9,-4(r1)   /* restore return address */;\
+   l.lwz   r2,-8(r1)   /* restore fp */;\
+   l.lwz   t1,-12(r1)  /* restore extra reg */
+
+#define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
+#define TRACE_IRQS_ON  TRACE_IRQS_OP(trace_hardirqs_on)
+#define TRACE_IRQS_ON_SYSCALL  \
+   TRACE_IRQS_SAVE(r10,trace_hardirqs_on)  ;\
+   l.lwz   r3,PT_GPR3(r1)  ;\
+   l.lwz   r4,PT_GPR4(r1)  ;\
+   l.lwz   r5,PT_GPR5(r1)  ;\
+   l.lwz   r6,PT_GPR6(r1)  ;\
+   l.lwz   r7,PT_GPR7(r1)  ;\
+   l.lwz   r8,PT_GPR8(r1)  ;\
+   l.lwz   r11,PT_GPR11(r1)
+#define TRACE_IRQS_OFF_ENTRY   \
+   l.lwz   r5,PT_SR(r1);\
+   l.andi  r3,r5,(SPR_SR_IEE|SPR_SR_TEE)   ;\
+   l.sfeq  r5,r0   /* skip trace if irqs were already off */;\
+   l.bf1f  ;\
+l.nop  ;\
+   TRACE_IRQS_SAVE(r4,trace_hardirqs_off)  ;\
+1:
+#else
+#define TRACE_IRQS_OFF
+#define TRACE_IRQS_ON
+#define TRACE_IRQS_OFF_ENTRY
+#define TRACE_IRQS_ON_SYSCALL
+#endif
+
 /*
  * We need to disable interrupts at beginning of RESTORE_ALL
  * since interrupt might come in after we've loaded EPC return address
@@ -124,6 +179,7 @@ handler:
;\
/* r30 already save */  ;\
 /*l.swPT_GPR30(r1),r30*/   ;\
l.swPT_GPR31(r1),r31;\
+   TRACE_IRQS_OFF_ENTRY   

[PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators

[Stafford Horne]

From: Stefan Kristiansson 

Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP.  This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.

Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - Fix stdout-path

Changes since v1
 - Use openrisc, prefix for ompic
 - Add stdout-path
 - Remove @interrupt cells

 arch/openrisc/boot/dts/simple_smp.dts  | 63 
 arch/openrisc/configs/simple_smp_defconfig | 66 ++
 2 files changed, 129 insertions(+)
 create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
 create mode 100644 arch/openrisc/configs/simple_smp_defconfig

diff --git a/arch/openrisc/boot/dts/simple_smp.dts 
b/arch/openrisc/boot/dts/simple_smp.dts
new file mode 100644
index ..defbb92714ec
--- /dev/null
+++ b/arch/openrisc/boot/dts/simple_smp.dts
@@ -0,0 +1,63 @@
+/dts-v1/;
+/ {
+   compatible = "opencores,or1ksim";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   aliases {
+   uart0 = 
+   };
+
+   chosen {
+   bootargs = "earlycon";
+   stdout-path = "uart0:115200";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x0200>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <0>;
+   clock-frequency = <2000>;
+   };
+   cpu@1 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <1>;
+   clock-frequency = <2000>;
+   };
+   };
+
+   ompic: ompic@9800 {
+   compatible = "openrisc,ompic";
+   reg = <0x9800 16>;
+   interrupt-controller;
+   #interrupt-cells = <0>;
+   interrupts = <1>;
+   };
+
+   /*
+* OR1K PIC is built into CPU and accessed via special purpose
+* registers.  It is not addressable and, hence, has no 'reg'
+* property.
+*/
+   pic: pic {
+   compatible = "opencores,or1k-pic-level";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   serial0: serial@9000 {
+   compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+   reg = <0x9000 0x100>;
+   interrupts = <2>;
+   clock-frequency = <2000>;
+   };
+
+};
diff --git a/arch/openrisc/configs/simple_smp_defconfig 
b/arch/openrisc/configs/simple_smp_defconfig
new file mode 100644
index ..b6e3c7e158e7
--- /dev/null
+++ b/arch/openrisc/configs/simple_smp_defconfig
@@ -0,0 +1,66 @@
+CONFIG_CROSS_COMPILE="or1k-linux-"
+CONFIG_LOCALVERSION="-simple-smp"
+CONFIG_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_EPOLL is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+CONFIG_MODULES=y
+# CONFIG_BLOCK is not set
+CONFIG_OPENRISC_BUILTIN_DTB="simple_smp"
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_XZ_DEC=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_RCU_TRACE is not set
-- 
2.13.6

[PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing

[Stafford Horne]

From: Jan Henrik Weinstock 

On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock 
[sho...@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig  | 11 
 arch/openrisc/include/asm/Kbuild   |  1 -
 arch/openrisc/include/asm/cacheflush.h | 96 ++
 arch/openrisc/include/asm/pgtable.h| 16 +++---
 arch/openrisc/kernel/smp.c | 15 ++
 arch/openrisc/mm/Makefile  |  2 +-
 arch/openrisc/mm/cache.c   | 61 +
 7 files changed, 194 insertions(+), 8 deletions(-)
 create mode 100644 arch/openrisc/include/asm/cacheflush.h
 create mode 100644 arch/openrisc/mm/cache.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 2b3898ede888..bfff04ae7f7d 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -77,6 +77,17 @@ config OR1K_1200
 
 endchoice
 
+config DCACHE_WRITETHROUGH
+   bool "Have write through data caches"
+   default n
+   help
+ Select this if your implementation features write through data caches.
+ Selecting 'N' here will allow the kernel to force flushing of data
+ caches at relevant times. Most OpenRISC implementations support write-
+ through data caches.
+
+ If unsure say N here
+
 config OPENRISC_BUILTIN_DTB
 string "Builtin DTB"
 default ""
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5f066780d870..6eb16719549e 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,7 +1,6 @@
 generic-y += barrier.h
 generic-y += bug.h
 generic-y += bugs.h
-generic-y += cacheflush.h
 generic-y += checksum.h
 generic-y += clkdev.h
 generic-y += current.h
diff --git a/arch/openrisc/include/asm/cacheflush.h 
b/arch/openrisc/include/asm/cacheflush.h
new file mode 100644
index ..70f46fd7a074
--- /dev/null
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -0,0 +1,96 @@
+/*
+ * OpenRISC Linux
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others.  All original copyrights apply as per the original source
+ * declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) Jan Henrik Weinstock 
+ * et al.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_CACHEFLUSH_H
+#define __ASM_CACHEFLUSH_H
+
+#include 
+
+/*
+ * Helper function for flushing or invalidating entire pages from data
+ * and instruction caches. SMP needs a little extra work, since we need
+ * to flush the pages on all cpus.
+ */
+extern void local_dcache_page_flush(struct page *page);
+extern void local_icache_page_inv(struct page *page);
+
+/*
+ * Data cache flushing always happen on the local cpu. Instruction cache
+ * invalidations need to be broadcasted to all other cpu in the system in
+ * case of SMP configurations.
+ */
+#ifndef CONFIG_SMP
+#define dcache_page_flush(page)  local_dcache_page_flush(page)
+#define icache_page_inv(page)local_icache_page_inv(page)
+#else  /* CONFIG_SMP */
+#define dcache_page_flush(page)  local_dcache_page_flush(page)
+#define icache_page_inv(page)smp_icache_page_inv(page)
+extern void smp_icache_page_inv(struct page *page);
+#endif /* CONFIG_SMP */
+
+/*
+ * Synchronizes caches. Whenever a cpu writes executable code to memory, this
+ * should be called to make sure the processor sees the newly written code.
+ */
+static inline void sync_icache_dcache(struct page *page)
+{
+   if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
+   dcache_page_flush(page);
+   icache_page_inv(page);
+}
+
+/*
+ * Pages with this bit set need not be flushed/invalidated, since
+ * they have not changed since last flush. New pages start with
+ * PG_arch_1 not set and are therefore dirty by default.
+ */
+#define PG_dc_clean  PG_arch_1
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+static inline void flush_dcache_page(struct page *page)
+{
+   clear_bit(PG_dc_clean, >flags);
+}
+
+/*
+ * Other interfaces are not required since we do not have virtually
+ * indexed or tagged caches. So we can 

[PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks

[Stafford Horne]

During SMP testing we were getting the below warning after booting the
secondary cpu:

[0.06] BUG: scheduling while atomic: swapper/1/0/0x

This change follows similar patterns from other architectures to start
the schduler with preempt disabled.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/include/asm/thread_info.h | 2 +-
 arch/openrisc/kernel/smp.c  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/thread_info.h 
b/arch/openrisc/include/asm/thread_info.h
index 6e619a79a401..c229aa6bb502 100644
--- a/arch/openrisc/include/asm/thread_info.h
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -74,7 +74,7 @@ struct thread_info {
.task   = , \
.flags  = 0,\
.cpu= 0,\
-   .preempt_count  = 1,\
+   .preempt_count  = INIT_PREEMPT_COUNT,   \
.addr_limit = KERNEL_DS,\
.ksp= 0,\
 }
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index fd724123229a..154c94a0cfbc 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -128,6 +128,7 @@ asmlinkage __init void secondary_start_kernel(void)
 
local_irq_enable();
 
+   preempt_disable();
/*
 * OK, it's off to the idle thread for us
 */
-- 
2.13.6

[PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait

[Stafford Horne]

Currently we do a spin on secondary cpus when waiting to boot.  This
theoretically causes issues with power consumption and does cause issues
with qemu cycle burning (it starves cpu 0 from actually being able to
boot.)

This change puts each secondary cpu to sleep if they have a power
management unit, then signals them to wake via IPI when its time to boot.
If the cpus have no power management unit they will loop as before.

Note: The wakeup IPI requires a special interrupt handler as on secondary
cpu's the interrupt infrastructure is not yet established.  This
interrupt handler is set and reset by updating SPR_EVBAR.

Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - Check if power management exists before sleeping

 arch/openrisc/kernel/head.S | 51 +++--
 arch/openrisc/kernel/smp.c  |  5 +
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index a9972dc103f8..fb02b2a1d6f2 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -712,9 +712,45 @@ _flush_tlb:
 
 #ifdef CONFIG_SMP
 secondary_wait:
+   /* Doze the cpu until we are asked to run */
+   /* If we dont have power management skip doze */
+   l.mfspr r25,r0,SPR_UPR
+   l.andi  r25,r25,SPR_UPR_PMP
+   l.sfeq  r25,r0
+   l.bfsecondary_check_release
+l.nop
+
+   /* Setup special secondary exception handler */
+   LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
+   tophys(r25,r3)
+   l.mtspr r0,r25,SPR_EVBAR
+
+   /* Enable Interrupts */
+   l.mfspr r25,r0,SPR_SR
+   l.ori   r25,r25,SPR_SR_IEE
+   l.mtspr r0,r25,SPR_SR
+
+   /* Unmask interrupts interrupts */
+   l.mfspr r25,r0,SPR_PICMR
+   l.ori   r25,r25,0x
+   l.mtspr r0,r25,SPR_PICMR
+
+   /* Doze */
+   l.mfspr r25,r0,SPR_PMR
+   LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
+   l.orr25,r25,r3
+   l.mtspr r0,r25,SPR_PMR
+
+   /* Wakeup - Restore exception handler */
+   l.mtspr r0,r0,SPR_EVBAR
+
+secondary_check_release:
+   /*
+* Check if we actually got the release signal, if not go-back to
+* sleep.
+*/
l.mfspr r25,r0,SPR_COREID
-   l.movhi r3,hi(secondary_release)
-   l.ori   r3,r3,lo(secondary_release)
+   LOAD_SYMBOL_2_GPR(r3, secondary_release)
tophys(r4, r3)
l.lwz   r3,0(r4)
l.sfeq  r25,r3
@@ -1663,6 +1699,17 @@ ENTRY(_early_uart_init)
l.jrr9
l.nop
 
+   .align  0x1000
+   .global _secondary_evbar
+_secondary_evbar:
+
+   .space 0x800
+   /* Just disable interrupts and Return */
+   l.ori   r3,r0,SPR_SR_SM
+   l.mtspr r0,r3,SPR_ESR_BASE
+   l.rfe
+
+
.section .rodata
 _string_unhandled_exception:
.string "\n\rRunarunaround: Unhandled exception 0x\0"
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 154c94a0cfbc..685b4934fa39 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -26,6 +26,7 @@ unsigned long secondary_release = -1;
 struct thread_info *secondary_thread_info;
 
 enum ipi_msg_type {
+   IPI_WAKEUP,
IPI_RESCHEDULE,
IPI_CALL_FUNC,
IPI_CALL_FUNC_SINGLE,
@@ -42,6 +43,7 @@ static void boot_secondary(unsigned int cpu, struct 
task_struct *idle)
spin_lock(_lock);
 
secondary_release = cpu;
+   smp_cross_call(cpumask_of(cpu), IPI_WAKEUP);
 
/*
 * now the secondary core is starting up let it run its
@@ -140,6 +142,9 @@ void handle_IPI(unsigned int ipi_msg)
unsigned int cpu = smp_processor_id();
 
switch (ipi_msg) {
+   case IPI_WAKEUP:
+   break;
+
case IPI_RESCHEDULE:
scheduler_ipi();
break;
-- 
2.13.6

[PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing

[Stafford Horne]

From: Jan Henrik Weinstock 

On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock 
[sho...@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig  | 11 
 arch/openrisc/include/asm/Kbuild   |  1 -
 arch/openrisc/include/asm/cacheflush.h | 96 ++
 arch/openrisc/include/asm/pgtable.h| 16 +++---
 arch/openrisc/kernel/smp.c | 15 ++
 arch/openrisc/mm/Makefile  |  2 +-
 arch/openrisc/mm/cache.c   | 61 +
 7 files changed, 194 insertions(+), 8 deletions(-)
 create mode 100644 arch/openrisc/include/asm/cacheflush.h
 create mode 100644 arch/openrisc/mm/cache.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 2b3898ede888..bfff04ae7f7d 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -77,6 +77,17 @@ config OR1K_1200
 
 endchoice
 
+config DCACHE_WRITETHROUGH
+   bool "Have write through data caches"
+   default n
+   help
+ Select this if your implementation features write through data caches.
+ Selecting 'N' here will allow the kernel to force flushing of data
+ caches at relevant times. Most OpenRISC implementations support write-
+ through data caches.
+
+ If unsure say N here
+
 config OPENRISC_BUILTIN_DTB
 string "Builtin DTB"
 default ""
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5f066780d870..6eb16719549e 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,7 +1,6 @@
 generic-y += barrier.h
 generic-y += bug.h
 generic-y += bugs.h
-generic-y += cacheflush.h
 generic-y += checksum.h
 generic-y += clkdev.h
 generic-y += current.h
diff --git a/arch/openrisc/include/asm/cacheflush.h 
b/arch/openrisc/include/asm/cacheflush.h
new file mode 100644
index ..70f46fd7a074
--- /dev/null
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -0,0 +1,96 @@
+/*
+ * OpenRISC Linux
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others.  All original copyrights apply as per the original source
+ * declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) Jan Henrik Weinstock 
+ * et al.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_CACHEFLUSH_H
+#define __ASM_CACHEFLUSH_H
+
+#include 
+
+/*
+ * Helper function for flushing or invalidating entire pages from data
+ * and instruction caches. SMP needs a little extra work, since we need
+ * to flush the pages on all cpus.
+ */
+extern void local_dcache_page_flush(struct page *page);
+extern void local_icache_page_inv(struct page *page);
+
+/*
+ * Data cache flushing always happen on the local cpu. Instruction cache
+ * invalidations need to be broadcasted to all other cpu in the system in
+ * case of SMP configurations.
+ */
+#ifndef CONFIG_SMP
+#define dcache_page_flush(page)  local_dcache_page_flush(page)
+#define icache_page_inv(page)local_icache_page_inv(page)
+#else  /* CONFIG_SMP */
+#define dcache_page_flush(page)  local_dcache_page_flush(page)
+#define icache_page_inv(page)smp_icache_page_inv(page)
+extern void smp_icache_page_inv(struct page *page);
+#endif /* CONFIG_SMP */
+
+/*
+ * Synchronizes caches. Whenever a cpu writes executable code to memory, this
+ * should be called to make sure the processor sees the newly written code.
+ */
+static inline void sync_icache_dcache(struct page *page)
+{
+   if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
+   dcache_page_flush(page);
+   icache_page_inv(page);
+}
+
+/*
+ * Pages with this bit set need not be flushed/invalidated, since
+ * they have not changed since last flush. New pages start with
+ * PG_arch_1 not set and are therefore dirty by default.
+ */
+#define PG_dc_clean  PG_arch_1
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+static inline void flush_dcache_page(struct page *page)
+{
+   clear_bit(PG_dc_clean, >flags);
+}
+
+/*
+ * Other interfaces are not required since we do not have virtually
+ * indexed or tagged caches. So we can use the default here.
+ */
+#define flush_cache_all()  do { } while (0)
+#define 

[PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks

[Stafford Horne]

During SMP testing we were getting the below warning after booting the
secondary cpu:

[0.06] BUG: scheduling while atomic: swapper/1/0/0x

This change follows similar patterns from other architectures to start
the schduler with preempt disabled.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/include/asm/thread_info.h | 2 +-
 arch/openrisc/kernel/smp.c  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/thread_info.h 
b/arch/openrisc/include/asm/thread_info.h
index 6e619a79a401..c229aa6bb502 100644
--- a/arch/openrisc/include/asm/thread_info.h
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -74,7 +74,7 @@ struct thread_info {
.task   = , \
.flags  = 0,\
.cpu= 0,\
-   .preempt_count  = 1,\
+   .preempt_count  = INIT_PREEMPT_COUNT,   \
.addr_limit = KERNEL_DS,\
.ksp= 0,\
 }
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index fd724123229a..154c94a0cfbc 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -128,6 +128,7 @@ asmlinkage __init void secondary_start_kernel(void)
 
local_irq_enable();
 
+   preempt_disable();
/*
 * OK, it's off to the idle thread for us
 */
-- 
2.13.6

[PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait

[Stafford Horne]

Currently we do a spin on secondary cpus when waiting to boot.  This
theoretically causes issues with power consumption and does cause issues
with qemu cycle burning (it starves cpu 0 from actually being able to
boot.)

This change puts each secondary cpu to sleep if they have a power
management unit, then signals them to wake via IPI when its time to boot.
If the cpus have no power management unit they will loop as before.

Note: The wakeup IPI requires a special interrupt handler as on secondary
cpu's the interrupt infrastructure is not yet established.  This
interrupt handler is set and reset by updating SPR_EVBAR.

Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - Check if power management exists before sleeping

 arch/openrisc/kernel/head.S | 51 +++--
 arch/openrisc/kernel/smp.c  |  5 +
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index a9972dc103f8..fb02b2a1d6f2 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -712,9 +712,45 @@ _flush_tlb:
 
 #ifdef CONFIG_SMP
 secondary_wait:
+   /* Doze the cpu until we are asked to run */
+   /* If we dont have power management skip doze */
+   l.mfspr r25,r0,SPR_UPR
+   l.andi  r25,r25,SPR_UPR_PMP
+   l.sfeq  r25,r0
+   l.bfsecondary_check_release
+l.nop
+
+   /* Setup special secondary exception handler */
+   LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
+   tophys(r25,r3)
+   l.mtspr r0,r25,SPR_EVBAR
+
+   /* Enable Interrupts */
+   l.mfspr r25,r0,SPR_SR
+   l.ori   r25,r25,SPR_SR_IEE
+   l.mtspr r0,r25,SPR_SR
+
+   /* Unmask interrupts interrupts */
+   l.mfspr r25,r0,SPR_PICMR
+   l.ori   r25,r25,0x
+   l.mtspr r0,r25,SPR_PICMR
+
+   /* Doze */
+   l.mfspr r25,r0,SPR_PMR
+   LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
+   l.orr25,r25,r3
+   l.mtspr r0,r25,SPR_PMR
+
+   /* Wakeup - Restore exception handler */
+   l.mtspr r0,r0,SPR_EVBAR
+
+secondary_check_release:
+   /*
+* Check if we actually got the release signal, if not go-back to
+* sleep.
+*/
l.mfspr r25,r0,SPR_COREID
-   l.movhi r3,hi(secondary_release)
-   l.ori   r3,r3,lo(secondary_release)
+   LOAD_SYMBOL_2_GPR(r3, secondary_release)
tophys(r4, r3)
l.lwz   r3,0(r4)
l.sfeq  r25,r3
@@ -1663,6 +1699,17 @@ ENTRY(_early_uart_init)
l.jrr9
l.nop
 
+   .align  0x1000
+   .global _secondary_evbar
+_secondary_evbar:
+
+   .space 0x800
+   /* Just disable interrupts and Return */
+   l.ori   r3,r0,SPR_SR_SM
+   l.mtspr r0,r3,SPR_ESR_BASE
+   l.rfe
+
+
.section .rodata
 _string_unhandled_exception:
.string "\n\rRunarunaround: Unhandled exception 0x\0"
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 154c94a0cfbc..685b4934fa39 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -26,6 +26,7 @@ unsigned long secondary_release = -1;
 struct thread_info *secondary_thread_info;
 
 enum ipi_msg_type {
+   IPI_WAKEUP,
IPI_RESCHEDULE,
IPI_CALL_FUNC,
IPI_CALL_FUNC_SINGLE,
@@ -42,6 +43,7 @@ static void boot_secondary(unsigned int cpu, struct 
task_struct *idle)
spin_lock(_lock);
 
secondary_release = cpu;
+   smp_cross_call(cpumask_of(cpu), IPI_WAKEUP);
 
/*
 * now the secondary core is starting up let it run its
@@ -140,6 +142,9 @@ void handle_IPI(unsigned int ipi_msg)
unsigned int cpu = smp_processor_id();
 
switch (ipi_msg) {
+   case IPI_WAKEUP:
+   break;
+
case IPI_RESCHEDULE:
scheduler_ipi();
break;
-- 
2.13.6

[PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks

[Stafford Horne]

Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig  |  2 ++
 arch/openrisc/include/asm/Kbuild   |  4 
 arch/openrisc/include/asm/spinlock.h   | 12 +++-
 arch/openrisc/include/asm/spinlock_types.h |  7 +++
 4 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 356dd67a86ea..b49acda5e8f4 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
select OR1K_PIC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+   select ARCH_USE_QUEUED_SPINLOCKS
+   select ARCH_USE_QUEUED_RWLOCKS
 
 config CPU_BIG_ENDIAN
def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
 generic-y += pci.h
 generic-y += percpu.h
 generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h 
b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
 #ifndef __ASM_OPENRISC_SPINLOCK_H
 #define __ASM_OPENRISC_SPINLOCK_H
 
-#error "or32 doesn't do SMP yet"
+#include 
+
+#include 
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)  cpu_relax()
+#define arch_read_relax(lock)  cpu_relax()
+#define arch_write_relax(lock) cpu_relax()
+
 
 #endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h 
b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index ..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include 
+#include 
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
-- 
2.13.6

[PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support

[Stafford Horne]

OpenRISC only supports hardware instructions that perform 4 byte atomic
operations.  For enabling qrwlocks for upcoming SMP support 1 and 2 byte
implementations are needed.  To do this we leverage the 4 byte atomic
operations and shift/mask the 1 and 2 byte areas as needed.

This heavily borrows ideas and routines from sh and mips, which do
something similar.

Cc: Peter Zijlstra 
Signed-off-by: Stafford Horne 
---
 arch/openrisc/include/asm/cmpxchg.h | 147 
 1 file changed, 115 insertions(+), 32 deletions(-)

diff --git a/arch/openrisc/include/asm/cmpxchg.h 
b/arch/openrisc/include/asm/cmpxchg.h
index f0a5d8b844d6..d29f7db53906 100644
--- a/arch/openrisc/include/asm/cmpxchg.h
+++ b/arch/openrisc/include/asm/cmpxchg.h
@@ -1,32 +1,29 @@
 /*
+ * 1,2 and 4 byte cmpxchg and xchg implementations for OpenRISC.
+ *
  * Copyright (C) 2014 Stefan Kristiansson 
+ * Copyright (C) 2017 Stafford Horne 
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
+ *
+ * Note:
+ * The portable implementations of 1 and 2 byte xchg and cmpxchg using a 4
+ * byte cmpxchg is sourced heavily from the sh and mips implementations.
  */
 
 #ifndef __ASM_OPENRISC_CMPXCHG_H
 #define __ASM_OPENRISC_CMPXCHG_H
 
 #include  
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
+#include  
 
 #define __HAVE_ARCH_CMPXCHG 1
 
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+static inline unsigned long cmpxchg_u32(volatile void *ptr,
+   unsigned long old, unsigned long new)
 {
-   if (size != 4) {
-   __cmpxchg_called_with_bad_pointer();
-   return old;
-   }
-
__asm__ __volatile__(
"1: l.lwa %0, 0(%1) \n"
"   l.sfeq %0, %2   \n"
@@ -43,6 +40,97 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned 
long new, int size)
return old;
 }
 
+static inline unsigned long xchg_u32(volatile void *ptr,
+   unsigned long val)
+{
+   __asm__ __volatile__(
+   "1: l.lwa %0, 0(%1) \n"
+   "   l.swa 0(%1), %2 \n"
+   "   l.bnf 1b\n"
+   "l.nop  \n"
+   : "="(val)
+   : "r"(ptr), "r"(val)
+   : "cc", "memory");
+
+   return val;
+}
+
+static inline u32 cmpxchg_small(volatile void *ptr, u32 old, u32 new,
+   int size)
+{
+   int off = (unsigned long)ptr % sizeof(u32);
+   volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+   int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+   int bitoff = off * BITS_PER_BYTE;
+#endif
+   u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+   u32 load32, old32, new32;
+   u32 ret;
+
+   load32 = READ_ONCE(*p);
+
+   while (true) {
+   ret = (load32 & bitmask) >> bitoff;
+   if (old != ret)
+   return ret;
+
+   old32 = (load32 & ~bitmask) | (old << bitoff);
+   new32 = (load32 & ~bitmask) | (new << bitoff);
+
+   /* Do 32 bit cmpxchg */
+   load32 = cmpxchg_u32(p, old32, new32);
+   if (load32 == old32)
+   return old;
+   }
+}
+
+/* xchg */
+
+static inline u32 xchg_small(volatile void *ptr, u32 x, int size)
+{
+   int off = (unsigned long)ptr % sizeof(u32);
+   volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+   int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+   int bitoff = off * BITS_PER_BYTE;
+#endif
+   u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+   u32 oldv, newv;
+   u32 ret;
+
+   do {
+   oldv = READ_ONCE(*p);
+   ret = (oldv & bitmask) >> bitoff;
+   newv = (oldv & ~bitmask) | (x << bitoff);
+   } while (cmpxchg_u32(p, oldv, newv) != oldv);
+
+   return ret;
+}
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
+   __compiletime_error("Bad argument size for cmpxchg");
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+   unsigned long new, int size)
+{
+   switch (size) {
+   case 1:
+   case 2:
+   return cmpxchg_small(ptr, old, new, size);
+   case 4:
+   return cmpxchg_u32(ptr, old, new);
+   default:
+   return 

[PATCH v3 05/13] irqchip: add initial support for ompic

[Stafford Horne]

From: Stefan Kristiansson 

IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
proposed architecture specification:

  
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.

Cc: Marc Zyngier 
Cc: Rob Herring 
Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - Fixed some issues with missing static
 - Fixed spelling issue with multi-core
 - Added back #interrupt-cells

Changes since v1
 - Added openrisc, prefix
 - Clarified 8 bytes per cpu
 - Removed #interrupt-cells as this will not be an irq parent
 - Changed ops to be percpu
 - Added DTS and intialization failure validations


 .../interrupt-controller/openrisc,ompic.txt|  22 +++
 MAINTAINERS|   1 +
 arch/openrisc/Kconfig  |   1 +
 drivers/irqchip/Kconfig|   3 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-ompic.c| 205 +
 6 files changed, 233 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
 create mode 100644 drivers/irqchip/irq-ompic.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
new file mode 100644
index ..caec07cc7149
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
@@ -0,0 +1,22 @@
+Open Multi-Processor Interrupt Controller
+
+Required properties:
+
+- compatible : This should be "openrisc,ompic"
+- reg : Specifies base physical address and size of the register space. The
+  size is based on the number of cores the controller has been configured
+  to handle, this should be set to 8 bytes per cpu core.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : This should be set to 0 as this will not be an irq
+  parent.
+- interrupts : Specifies the interrupt line to which the ompic is wired.
+
+Example:
+
+ompic: interrupt-controller@9800 {
+   compatible = "openrisc,ompic";
+   reg = <0x9800 16>;
+   interrupt-controller;
+   #interrupt-cells = <0>;
+   interrupts = <1>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 2281af4b41b6..4d0255ce6e5f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10009,6 +10009,7 @@ L:  openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
 F: arch/openrisc/
+F: drivers/irqchip/irq-ompic.c
 
 OPENVSWITCH
 M: Pravin Shelar 
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index b49acda5e8f4..34eb4e90f56c 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -30,6 +30,7 @@ config OPENRISC
select NO_BOOTMEM
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
+   select OMPIC if SMP
 
 config CPU_BIG_ENDIAN
def_bool y
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9d8a1dd2e2c2..a2ca82f6c2dd 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -151,6 +151,9 @@ config CLPS711X_IRQCHIP
select SPARSE_IRQ
default y
 
+config OMPIC
+   bool
+
 config OR1K_PIC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 845abc107ad5..771f8e7f46f8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
 obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
+obj-$(CONFIG_OMPIC)+= irq-ompic.o
 obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
 obj-$(CONFIG_ORION_IRQCHIP)+= irq-orion.o
 obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
new file mode 100644
index ..1ade9bcab974
--- /dev/null
+++ b/drivers/irqchip/irq-ompic.c
@@ -0,0 +1,205 @@
+/*
+ * Open Multi-Processor Interrupt Controller driver
+ *
+ * Copyright (C) 2014 Stefan Kristiansson 

[PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support

[Stafford Horne]

OpenRISC only supports hardware instructions that perform 4 byte atomic
operations.  For enabling qrwlocks for upcoming SMP support 1 and 2 byte
implementations are needed.  To do this we leverage the 4 byte atomic
operations and shift/mask the 1 and 2 byte areas as needed.

This heavily borrows ideas and routines from sh and mips, which do
something similar.

Cc: Peter Zijlstra 
Signed-off-by: Stafford Horne 
---
 arch/openrisc/include/asm/cmpxchg.h | 147 
 1 file changed, 115 insertions(+), 32 deletions(-)

diff --git a/arch/openrisc/include/asm/cmpxchg.h 
b/arch/openrisc/include/asm/cmpxchg.h
index f0a5d8b844d6..d29f7db53906 100644
--- a/arch/openrisc/include/asm/cmpxchg.h
+++ b/arch/openrisc/include/asm/cmpxchg.h
@@ -1,32 +1,29 @@
 /*
+ * 1,2 and 4 byte cmpxchg and xchg implementations for OpenRISC.
+ *
  * Copyright (C) 2014 Stefan Kristiansson 
+ * Copyright (C) 2017 Stafford Horne 
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
+ *
+ * Note:
+ * The portable implementations of 1 and 2 byte xchg and cmpxchg using a 4
+ * byte cmpxchg is sourced heavily from the sh and mips implementations.
  */
 
 #ifndef __ASM_OPENRISC_CMPXCHG_H
 #define __ASM_OPENRISC_CMPXCHG_H
 
 #include  
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
+#include  
 
 #define __HAVE_ARCH_CMPXCHG 1
 
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+static inline unsigned long cmpxchg_u32(volatile void *ptr,
+   unsigned long old, unsigned long new)
 {
-   if (size != 4) {
-   __cmpxchg_called_with_bad_pointer();
-   return old;
-   }
-
__asm__ __volatile__(
"1: l.lwa %0, 0(%1) \n"
"   l.sfeq %0, %2   \n"
@@ -43,6 +40,97 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned 
long new, int size)
return old;
 }
 
+static inline unsigned long xchg_u32(volatile void *ptr,
+   unsigned long val)
+{
+   __asm__ __volatile__(
+   "1: l.lwa %0, 0(%1) \n"
+   "   l.swa 0(%1), %2 \n"
+   "   l.bnf 1b\n"
+   "l.nop  \n"
+   : "="(val)
+   : "r"(ptr), "r"(val)
+   : "cc", "memory");
+
+   return val;
+}
+
+static inline u32 cmpxchg_small(volatile void *ptr, u32 old, u32 new,
+   int size)
+{
+   int off = (unsigned long)ptr % sizeof(u32);
+   volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+   int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+   int bitoff = off * BITS_PER_BYTE;
+#endif
+   u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+   u32 load32, old32, new32;
+   u32 ret;
+
+   load32 = READ_ONCE(*p);
+
+   while (true) {
+   ret = (load32 & bitmask) >> bitoff;
+   if (old != ret)
+   return ret;
+
+   old32 = (load32 & ~bitmask) | (old << bitoff);
+   new32 = (load32 & ~bitmask) | (new << bitoff);
+
+   /* Do 32 bit cmpxchg */
+   load32 = cmpxchg_u32(p, old32, new32);
+   if (load32 == old32)
+   return old;
+   }
+}
+
+/* xchg */
+
+static inline u32 xchg_small(volatile void *ptr, u32 x, int size)
+{
+   int off = (unsigned long)ptr % sizeof(u32);
+   volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+   int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+   int bitoff = off * BITS_PER_BYTE;
+#endif
+   u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+   u32 oldv, newv;
+   u32 ret;
+
+   do {
+   oldv = READ_ONCE(*p);
+   ret = (oldv & bitmask) >> bitoff;
+   newv = (oldv & ~bitmask) | (x << bitoff);
+   } while (cmpxchg_u32(p, oldv, newv) != oldv);
+
+   return ret;
+}
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
+   __compiletime_error("Bad argument size for cmpxchg");
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+   unsigned long new, int size)
+{
+   switch (size) {
+   case 1:
+   case 2:
+   return cmpxchg_small(ptr, old, new, size);
+   case 4:
+   return cmpxchg_u32(ptr, old, new);
+   default:
+   return __cmpxchg_called_with_bad_pointer();
+   }
+}
+
 #define cmpxchg(ptr, o, n)

[PATCH v3 05/13] irqchip: add initial support for ompic

[Stafford Horne]

From: Stefan Kristiansson 

IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
proposed architecture specification:

  
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.

Cc: Marc Zyngier 
Cc: Rob Herring 
Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - Fixed some issues with missing static
 - Fixed spelling issue with multi-core
 - Added back #interrupt-cells

Changes since v1
 - Added openrisc, prefix
 - Clarified 8 bytes per cpu
 - Removed #interrupt-cells as this will not be an irq parent
 - Changed ops to be percpu
 - Added DTS and intialization failure validations


 .../interrupt-controller/openrisc,ompic.txt|  22 +++
 MAINTAINERS|   1 +
 arch/openrisc/Kconfig  |   1 +
 drivers/irqchip/Kconfig|   3 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-ompic.c| 205 +
 6 files changed, 233 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
 create mode 100644 drivers/irqchip/irq-ompic.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
new file mode 100644
index ..caec07cc7149
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
@@ -0,0 +1,22 @@
+Open Multi-Processor Interrupt Controller
+
+Required properties:
+
+- compatible : This should be "openrisc,ompic"
+- reg : Specifies base physical address and size of the register space. The
+  size is based on the number of cores the controller has been configured
+  to handle, this should be set to 8 bytes per cpu core.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : This should be set to 0 as this will not be an irq
+  parent.
+- interrupts : Specifies the interrupt line to which the ompic is wired.
+
+Example:
+
+ompic: interrupt-controller@9800 {
+   compatible = "openrisc,ompic";
+   reg = <0x9800 16>;
+   interrupt-controller;
+   #interrupt-cells = <0>;
+   interrupts = <1>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 2281af4b41b6..4d0255ce6e5f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10009,6 +10009,7 @@ L:  openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
 F: arch/openrisc/
+F: drivers/irqchip/irq-ompic.c
 
 OPENVSWITCH
 M: Pravin Shelar 
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index b49acda5e8f4..34eb4e90f56c 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -30,6 +30,7 @@ config OPENRISC
select NO_BOOTMEM
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
+   select OMPIC if SMP
 
 config CPU_BIG_ENDIAN
def_bool y
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9d8a1dd2e2c2..a2ca82f6c2dd 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -151,6 +151,9 @@ config CLPS711X_IRQCHIP
select SPARSE_IRQ
default y
 
+config OMPIC
+   bool
+
 config OR1K_PIC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 845abc107ad5..771f8e7f46f8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
 obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
+obj-$(CONFIG_OMPIC)+= irq-ompic.o
 obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
 obj-$(CONFIG_ORION_IRQCHIP)+= irq-orion.o
 obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
new file mode 100644
index ..1ade9bcab974
--- /dev/null
+++ b/drivers/irqchip/irq-ompic.c
@@ -0,0 +1,205 @@
+/*
+ * Open Multi-Processor Interrupt Controller driver
+ *
+ * Copyright (C) 2014 Stefan Kristiansson 
+ * Copyright (C) 2017 Stafford Horne 
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed 

[PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks

[Stafford Horne]

Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/Kconfig  |  2 ++
 arch/openrisc/include/asm/Kbuild   |  4 
 arch/openrisc/include/asm/spinlock.h   | 12 +++-
 arch/openrisc/include/asm/spinlock_types.h |  7 +++
 4 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 356dd67a86ea..b49acda5e8f4 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
select OR1K_PIC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+   select ARCH_USE_QUEUED_SPINLOCKS
+   select ARCH_USE_QUEUED_RWLOCKS
 
 config CPU_BIG_ENDIAN
def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
 generic-y += pci.h
 generic-y += percpu.h
 generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h 
b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
 #ifndef __ASM_OPENRISC_SPINLOCK_H
 #define __ASM_OPENRISC_SPINLOCK_H
 
-#error "or32 doesn't do SMP yet"
+#include 
+
+#include 
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)  cpu_relax()
+#define arch_read_relax(lock)  cpu_relax()
+#define arch_write_relax(lock) cpu_relax()
+
 
 #endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h 
b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index ..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include 
+#include 
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
-- 
2.13.6

[PATCH v3 06/13] openrisc: initial SMP support

[Stafford Horne]

From: Stefan Kristiansson 

This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few years back including:

 - New SPRS SPR_COREID SPR_NUMCORES
 - Shadow SPRs
 - Atomic Instructions
 - Cache Coherency
 - A wired in IPI controller

This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.

Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.

The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout.  The addition of the smp.c and changes in
time.c are the changes.  Some specific notes:

MM changes
--
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).

TLB Flush
-
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.

Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.

CPU INFO

This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu.  show_cpuinfo is also updated to reflect new version
information in later versions of the spec.

SMP API
---
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.

Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - Added time.h for timer initialization
 - Don't crash on boot if IPI initialization fails
 - Removed volatile on secondary_release flag (checkpatch report)
 - Change ipi variable name from ipi_msg from

 arch/openrisc/Kconfig   |  17 ++-
 arch/openrisc/include/asm/cpuinfo.h |   7 +-
 arch/openrisc/include/asm/mmu_context.h |   2 +-
 arch/openrisc/include/asm/pgtable.h |   2 +-
 arch/openrisc/include/asm/serial.h  |   2 +-
 arch/openrisc/include/asm/smp.h |  26 
 arch/openrisc/include/asm/spr_defs.h|  14 ++
 arch/openrisc/include/asm/time.h|  15 ++
 arch/openrisc/include/asm/tlbflush.h|  25 +++-
 arch/openrisc/kernel/Makefile   |   1 +
 arch/openrisc/kernel/dma.c  |  14 +-
 arch/openrisc/kernel/head.S |  97 -
 arch/openrisc/kernel/setup.c| 165 ++
 arch/openrisc/kernel/smp.c  | 235 
 arch/openrisc/kernel/time.c |  51 ---
 arch/openrisc/lib/delay.c   |   2 +-
 arch/openrisc/mm/fault.c|   4 +-
 arch/openrisc/mm/init.c |   2 +-
 arch/openrisc/mm/tlb.c  |  16 +--
 19 files changed, 584 insertions(+), 113 deletions(-)
 create mode 100644 arch/openrisc/include/asm/smp.h
 create mode 100644 arch/openrisc/include/asm/time.h
 create mode 100644 arch/openrisc/kernel/smp.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 34eb4e90f56c..2b3898ede888 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -21,8 +21,10 @@ config OPENRISC
select HAVE_UID16
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
+   select GENERIC_CLOCKEVENTS_BROADCAST
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
+   select GENERIC_SMP_IDLE_THREAD
select MODULES_USE_ELF_RELA
select HAVE_DEBUG_STACKOVERFLOW
select OR1K_PIC
@@ -107,8 +109,19 @@ config OPENRISC_HAVE_INST_DIV
 endmenu
 
 config NR_CPUS
-   int
-   default "1"
+   int "Maximum number of CPUs (2-32)"
+   range 2 32
+   depends on SMP
+   default "2"
+
+config SMP
+   bool "Symmetric Multi-Processing support"
+   help
+ This enables support for systems with more than one CPU. If you have
+ a system with only one CPU, say N. If you have a system with more
+ than one CPU, say Y.
+
+ If you don't know what to do here, say N.
 
 source kernel/Kconfig.hz
 source kernel/Kconfig.preempt
diff --git a/arch/openrisc/include/asm/cpuinfo.h 
b/arch/openrisc/include/asm/cpuinfo.h
index ec10679d6429..4ea0a33eba6c 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_OPENRISC_CPUINFO_H
 #define __ASM_OPENRISC_CPUINFO_H
 
-struct cpuinfo {
+struct cpuinfo_or1k {
u32 clock_frequency;
 
u32 icache_size;
@@ -29,8 +29,11 @@ 

[PATCH v3 06/13] openrisc: initial SMP support

[Stafford Horne]

From: Stefan Kristiansson 

This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few years back including:

 - New SPRS SPR_COREID SPR_NUMCORES
 - Shadow SPRs
 - Atomic Instructions
 - Cache Coherency
 - A wired in IPI controller

This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.

Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.

The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout.  The addition of the smp.c and changes in
time.c are the changes.  Some specific notes:

MM changes
--
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).

TLB Flush
-
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.

Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.

CPU INFO

This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu.  show_cpuinfo is also updated to reflect new version
information in later versions of the spec.

SMP API
---
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.

Signed-off-by: Stefan Kristiansson 
[sho...@gmail.com: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: Stafford Horne 
---

Changes since v2
 - none

Changes since v1
 - Added time.h for timer initialization
 - Don't crash on boot if IPI initialization fails
 - Removed volatile on secondary_release flag (checkpatch report)
 - Change ipi variable name from ipi_msg from

 arch/openrisc/Kconfig   |  17 ++-
 arch/openrisc/include/asm/cpuinfo.h |   7 +-
 arch/openrisc/include/asm/mmu_context.h |   2 +-
 arch/openrisc/include/asm/pgtable.h |   2 +-
 arch/openrisc/include/asm/serial.h  |   2 +-
 arch/openrisc/include/asm/smp.h |  26 
 arch/openrisc/include/asm/spr_defs.h|  14 ++
 arch/openrisc/include/asm/time.h|  15 ++
 arch/openrisc/include/asm/tlbflush.h|  25 +++-
 arch/openrisc/kernel/Makefile   |   1 +
 arch/openrisc/kernel/dma.c  |  14 +-
 arch/openrisc/kernel/head.S |  97 -
 arch/openrisc/kernel/setup.c| 165 ++
 arch/openrisc/kernel/smp.c  | 235 
 arch/openrisc/kernel/time.c |  51 ---
 arch/openrisc/lib/delay.c   |   2 +-
 arch/openrisc/mm/fault.c|   4 +-
 arch/openrisc/mm/init.c |   2 +-
 arch/openrisc/mm/tlb.c  |  16 +--
 19 files changed, 584 insertions(+), 113 deletions(-)
 create mode 100644 arch/openrisc/include/asm/smp.h
 create mode 100644 arch/openrisc/include/asm/time.h
 create mode 100644 arch/openrisc/kernel/smp.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 34eb4e90f56c..2b3898ede888 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -21,8 +21,10 @@ config OPENRISC
select HAVE_UID16
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
+   select GENERIC_CLOCKEVENTS_BROADCAST
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
+   select GENERIC_SMP_IDLE_THREAD
select MODULES_USE_ELF_RELA
select HAVE_DEBUG_STACKOVERFLOW
select OR1K_PIC
@@ -107,8 +109,19 @@ config OPENRISC_HAVE_INST_DIV
 endmenu
 
 config NR_CPUS
-   int
-   default "1"
+   int "Maximum number of CPUs (2-32)"
+   range 2 32
+   depends on SMP
+   default "2"
+
+config SMP
+   bool "Symmetric Multi-Processing support"
+   help
+ This enables support for systems with more than one CPU. If you have
+ a system with only one CPU, say N. If you have a system with more
+ than one CPU, say Y.
+
+ If you don't know what to do here, say N.
 
 source kernel/Kconfig.hz
 source kernel/Kconfig.preempt
diff --git a/arch/openrisc/include/asm/cpuinfo.h 
b/arch/openrisc/include/asm/cpuinfo.h
index ec10679d6429..4ea0a33eba6c 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_OPENRISC_CPUINFO_H
 #define __ASM_OPENRISC_CPUINFO_H
 
-struct cpuinfo {
+struct cpuinfo_or1k {
u32 clock_frequency;
 
u32 icache_size;
@@ -29,8 +29,11 @@ struct cpuinfo {
u32 dcache_size;
u32 dcache_block_size;
u32 

[PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list

[Stafford Horne]

Add OpenRISC.io to vendor prefixes.  This is reserved for softcores
developed by the OpenRISC community.  The OpenRISC community has
separated from OpenCores.org requiring a new prefix.

Reviewed-by: Andreas Färber 
Acked-by: Rob Herring 
Signed-off-by: Stafford Horne 
---

Changes since v2
 - None

Changes since v1
 - New patch

 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1ea1fd4232ab..1478aad87532 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -246,6 +246,7 @@ onion   Onion Corporation
 onnn   ON Semiconductor Corp.
 ontat  On Tat Industrial Company
 opencores  OpenCores.org
+openrisc   OpenRISC.io
 option Option NV
 ORCL   Oracle Corporation
 ortustech  Ortus Technology Co., Ltd.
-- 
2.13.6

[PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list

[Stafford Horne]

Add OpenRISC.io to vendor prefixes.  This is reserved for softcores
developed by the OpenRISC community.  The OpenRISC community has
separated from OpenCores.org requiring a new prefix.

Reviewed-by: Andreas Färber 
Acked-by: Rob Herring 
Signed-off-by: Stafford Horne 
---

Changes since v2
 - None

Changes since v1
 - New patch

 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1ea1fd4232ab..1478aad87532 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -246,6 +246,7 @@ onion   Onion Corporation
 onnn   ON Semiconductor Corp.
 ontat  On Tat Industrial Company
 opencores  OpenCores.org
+openrisc   OpenRISC.io
 option Option NV
 ORCL   Oracle Corporation
 ortustech  Ortus Technology Co., Ltd.
-- 
2.13.6

[PATCH v3 00/13] OpenRISC SMP Support

[Stafford Horne]

Hello Again,

(sorry for a bit of delay getting this version out, gdb and qemu patches
 have been keeping me busy)

This series adds SMP support for OpenRISC.  The OpenRISC multi-core
platform and SMP linux support is based on the work that Stefan
Kristiansson did around 2012 implemented in Verilog and run on FPGAs.  I
have been working to upstream this work. I have additionally tested this on
QEMU, which I patched for OpenRISC multi-core support, as well as FPGA.

I have documented the architecture in the OpenRISC 1.2 specification
proposal available here:
  
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

The QEMU patches are still under review but are available here for testers
and anyone interested:
  https://github.com/stffrdhrn/qemu.git openrisc-smp-v1

This series contains a bit of a mix of patches to get everything working.
 o First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get
   the architecture ready for SMP.
 o The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks"
   add the SMP locking infrastructure as needed.  Using the qspinlocks and
   qrwlocks as suggested by Peter Z while reviewing the original spinlocks
   implementation.
 o The "support for ompic" adds a new irqchip device which is used for IPI
   communication to support SMP.  (Perhaps this patch should go via another
   route but included here for completeness - confirmed this is ok)
 o The "initial SMP support" adds smp.c and makes changes to all of the
   necessary data-structures to be per-cpu.
 o The remaining patches are bug fixes and debug helpers which I wanted
   to keep separate from the "initial SMP support" in order to allow them
   to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic

--

Changes since v2
  - Dropped BIG_ENDIAN patch as its upstream already
  - Fix typos with multi-core throughout the series suggested by Rob
Herring.
  - Fix issues with static functions throughout the series suggested by
Marc Zyngier.
  - Suggestions on DT docs from Rob Herring:
> Fix 'interrupt-controller@9800' naming issue.
> Add back #interrupt-cells.

Changes since v1
  - refactor of timer headers to not require extern openrisc_timer_init()
in smp.c
  - check for power management unit when sleeping on secondary cpu wait
  - fixed cpuinfo to print online CPUs only
  - cleanups for the ompic suggested by Marc Zyngier and Mark Rutland
> don't say size is arbitrary, it's 8 bytes per CPU
> validate register size vs cpus
> add validations for all initialization failures
> use percpu for percpu ipi ops
> remove SMP and OF #ifdefs
> document details about OpenRISC implied barriers
> use vendor prefix openrisc,
> removed #interrupt-cells as this will not be a parent
> added some architecture documentation into the source
  - enforce shadow register usage for SMP as suggested by Geert
  - DTS updates suggested by Mark Rutland
> Add and use vendor prefix openrisc, for ompic
> Use stdout-path

-Stafford

Jan Henrik Weinstock (1):
  openrisc: add cacheflush support to fix icache aliasing

Stafford Horne (8):
  openrisc: add 1 and 2 byte cmpxchg support
  openrisc: use qspinlocks and qrwlocks
  dt-bindings: add openrisc to vendor prefixes list
  openrisc: fix initial preempt state for secondary cpu tasks
  openrisc: sleep instead of spin on secondary wait
  openrisc: support framepointers and STACKTRACE_SUPPORT
  openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
  openrisc: add tick timer multi-core sync logic

Stefan Kristiansson (4):
  openrisc: use shadow registers to save regs on exception
  irqchip: add initial support for ompic
  openrisc: initial SMP support
  openrisc: add simple_smp dts and defconfig for simulators

 .../interrupt-controller/openrisc,ompic.txt|  22 ++
 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 MAINTAINERS|   1 +
 arch/openrisc/Kconfig  |  49 +++-
 arch/openrisc/boot/dts/simple_smp.dts  |  63 +
 arch/openrisc/configs/simple_smp_defconfig |  66 ++
 arch/openrisc/include/asm/Kbuild   |   5 +-
 arch/openrisc/include/asm/cacheflush.h |  96 
 arch/openrisc/include/asm/cmpxchg.h| 147 +---
 arch/openrisc/include/asm/cpuinfo.h|   7 +-
 arch/openrisc/include/asm/mmu_context.h|   2 +-
 arch/openrisc/include/asm/pgtable.h|  18 +-
 arch/openrisc/include/asm/serial.h |   2 +-
 arch/openrisc/include/asm/smp.h|  26 +++
 

[PATCH v3 00/13] OpenRISC SMP Support

[Stafford Horne]

Hello Again,

(sorry for a bit of delay getting this version out, gdb and qemu patches
 have been keeping me busy)

This series adds SMP support for OpenRISC.  The OpenRISC multi-core
platform and SMP linux support is based on the work that Stefan
Kristiansson did around 2012 implemented in Verilog and run on FPGAs.  I
have been working to upstream this work. I have additionally tested this on
QEMU, which I patched for OpenRISC multi-core support, as well as FPGA.

I have documented the architecture in the OpenRISC 1.2 specification
proposal available here:
  
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

The QEMU patches are still under review but are available here for testers
and anyone interested:
  https://github.com/stffrdhrn/qemu.git openrisc-smp-v1

This series contains a bit of a mix of patches to get everything working.
 o First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get
   the architecture ready for SMP.
 o The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks"
   add the SMP locking infrastructure as needed.  Using the qspinlocks and
   qrwlocks as suggested by Peter Z while reviewing the original spinlocks
   implementation.
 o The "support for ompic" adds a new irqchip device which is used for IPI
   communication to support SMP.  (Perhaps this patch should go via another
   route but included here for completeness - confirmed this is ok)
 o The "initial SMP support" adds smp.c and makes changes to all of the
   necessary data-structures to be per-cpu.
 o The remaining patches are bug fixes and debug helpers which I wanted
   to keep separate from the "initial SMP support" in order to allow them
   to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic

--

Changes since v2
  - Dropped BIG_ENDIAN patch as its upstream already
  - Fix typos with multi-core throughout the series suggested by Rob
Herring.
  - Fix issues with static functions throughout the series suggested by
Marc Zyngier.
  - Suggestions on DT docs from Rob Herring:
> Fix 'interrupt-controller@9800' naming issue.
> Add back #interrupt-cells.

Changes since v1
  - refactor of timer headers to not require extern openrisc_timer_init()
in smp.c
  - check for power management unit when sleeping on secondary cpu wait
  - fixed cpuinfo to print online CPUs only
  - cleanups for the ompic suggested by Marc Zyngier and Mark Rutland
> don't say size is arbitrary, it's 8 bytes per CPU
> validate register size vs cpus
> add validations for all initialization failures
> use percpu for percpu ipi ops
> remove SMP and OF #ifdefs
> document details about OpenRISC implied barriers
> use vendor prefix openrisc,
> removed #interrupt-cells as this will not be a parent
> added some architecture documentation into the source
  - enforce shadow register usage for SMP as suggested by Geert
  - DTS updates suggested by Mark Rutland
> Add and use vendor prefix openrisc, for ompic
> Use stdout-path

-Stafford

Jan Henrik Weinstock (1):
  openrisc: add cacheflush support to fix icache aliasing

Stafford Horne (8):
  openrisc: add 1 and 2 byte cmpxchg support
  openrisc: use qspinlocks and qrwlocks
  dt-bindings: add openrisc to vendor prefixes list
  openrisc: fix initial preempt state for secondary cpu tasks
  openrisc: sleep instead of spin on secondary wait
  openrisc: support framepointers and STACKTRACE_SUPPORT
  openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
  openrisc: add tick timer multi-core sync logic

Stefan Kristiansson (4):
  openrisc: use shadow registers to save regs on exception
  irqchip: add initial support for ompic
  openrisc: initial SMP support
  openrisc: add simple_smp dts and defconfig for simulators

 .../interrupt-controller/openrisc,ompic.txt|  22 ++
 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 MAINTAINERS|   1 +
 arch/openrisc/Kconfig  |  49 +++-
 arch/openrisc/boot/dts/simple_smp.dts  |  63 +
 arch/openrisc/configs/simple_smp_defconfig |  66 ++
 arch/openrisc/include/asm/Kbuild   |   5 +-
 arch/openrisc/include/asm/cacheflush.h |  96 
 arch/openrisc/include/asm/cmpxchg.h| 147 +---
 arch/openrisc/include/asm/cpuinfo.h|   7 +-
 arch/openrisc/include/asm/mmu_context.h|   2 +-
 arch/openrisc/include/asm/pgtable.h|  18 +-
 arch/openrisc/include/asm/serial.h |   2 +-
 arch/openrisc/include/asm/smp.h|  26 +++
 

[PATCH] MAINTAINERS: Add OpenRISC pic maintainer

[Stafford Horne]

The OpenRISC team is the maintainer of the irqchip or1k-pic driver under
drivers/irqchip.

Signed-off-by: Stafford Horne 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2281af4b41b6..8ce029872089 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10009,6 +10009,7 @@ L:  openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
 F: arch/openrisc/
+F: drivers/irqchip/irq-or1k-*
 
 OPENVSWITCH
 M: Pravin Shelar 
-- 
2.13.6

[PATCH] MAINTAINERS: Add OpenRISC pic maintainer

[Stafford Horne]

The OpenRISC team is the maintainer of the irqchip or1k-pic driver under
drivers/irqchip.

Signed-off-by: Stafford Horne 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2281af4b41b6..8ce029872089 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10009,6 +10009,7 @@ L:  openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
 F: arch/openrisc/
+F: drivers/irqchip/irq-or1k-*
 
 OPENVSWITCH
 M: Pravin Shelar 
-- 
2.13.6

Re: [PATCH] cpu/hotplug: Reset node state after operation

[Paul E. McKenney]

On Sat, Oct 21, 2017 at 04:06:52PM +0200, Thomas Gleixner wrote:
> The recent rework of the cpu hotplug internals changed the usage of the per
> cpu state->node field, but missed to clean it up after usage.
> 
> So subsequent hotplug operations use the stale pointer from a previous
> operation and hand it into the callback functions. The callbacks then
> dereference a pointer which either belongs to a different facility or
> points to freed and potentially reused memory. In either case data
> corruption and crashes are the obvious consequence.
> 
> Reset the node and the last pointers in the per cpu state to NULL after the
> operation which set them has completed.
> 
> Fixes: 96abb968549c ("smp/hotplug: Allow external multi-instance rollback")
> Reported-by: Tvrtko Ursulin 
> Signed-off-by: Thomas Gleixner 

This does fine with rcutorture, though it does not fix the lost
(or egregiously delayed) timer problem that is still eluding me.
Nevertheless, for whatever it is worth:

Tested-by: Paul E. McKenney 

> ---
>  kernel/cpu.c |5 +
>  1 file changed, 5 insertions(+)
> 
> --- a/kernel/cpu.c
> +++ b/kernel/cpu.c
> @@ -632,6 +632,11 @@ cpuhp_invoke_ap_callback(int cpu, enum c
>   __cpuhp_kick_ap(st);
>   }
> 
> + /*
> +  * Clean up the leftovers so the next hotplug operation wont use stale
> +  * data.
> +  */
> + st->node = st->last = NULL;
>   return ret;
>  }
> 
> 

Re: [PATCH] cpu/hotplug: Reset node state after operation

[Paul E. McKenney]

On Sat, Oct 21, 2017 at 04:06:52PM +0200, Thomas Gleixner wrote:
> The recent rework of the cpu hotplug internals changed the usage of the per
> cpu state->node field, but missed to clean it up after usage.
> 
> So subsequent hotplug operations use the stale pointer from a previous
> operation and hand it into the callback functions. The callbacks then
> dereference a pointer which either belongs to a different facility or
> points to freed and potentially reused memory. In either case data
> corruption and crashes are the obvious consequence.
> 
> Reset the node and the last pointers in the per cpu state to NULL after the
> operation which set them has completed.
> 
> Fixes: 96abb968549c ("smp/hotplug: Allow external multi-instance rollback")
> Reported-by: Tvrtko Ursulin 
> Signed-off-by: Thomas Gleixner 

This does fine with rcutorture, though it does not fix the lost
(or egregiously delayed) timer problem that is still eluding me.
Nevertheless, for whatever it is worth:

Tested-by: Paul E. McKenney 

> ---
>  kernel/cpu.c |5 +
>  1 file changed, 5 insertions(+)
> 
> --- a/kernel/cpu.c
> +++ b/kernel/cpu.c
> @@ -632,6 +632,11 @@ cpuhp_invoke_ap_callback(int cpu, enum c
>   __cpuhp_kick_ap(st);
>   }
> 
> + /*
> +  * Clean up the leftovers so the next hotplug operation wont use stale
> +  * data.
> +  */
> + st->node = st->last = NULL;
>   return ret;
>  }
> 
> 

[PATCH 1/3] Documentation: Move OpenRISC docs out of arch/

[Stafford Horne]

The OpenRISC docs have traditionally been in arch/ but that does not
seem like the correct place to be.  Move them so they will be more
visible to others.  Also update MAINTAINERS to make sure we get
notifications of changes.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/README.openrisc => Documentation/openrisc/README | 0
 arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO | 0
 MAINTAINERS| 1 +
 3 files changed, 1 insertion(+)
 rename arch/openrisc/README.openrisc => Documentation/openrisc/README (100%)
 rename arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO (100%)

diff --git a/arch/openrisc/README.openrisc b/Documentation/openrisc/README
similarity index 100%
rename from arch/openrisc/README.openrisc
rename to Documentation/openrisc/README
diff --git a/arch/openrisc/TODO.openrisc b/Documentation/openrisc/TODO
similarity index 100%
rename from arch/openrisc/TODO.openrisc
rename to Documentation/openrisc/TODO
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ce029872089..a57d13cb414d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10008,6 +10008,7 @@ T:  git git://github.com/openrisc/linux.git
 L: openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
+F: Documentation/openrisc/
 F: arch/openrisc/
 F: drivers/irqchip/irq-or1k-*
 
-- 
2.13.6

[PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC

[Stafford Horne]

Add devicetree binding documentation for the OpenRISC platform
opencores,or1ksim.  This is the main OpenRISC reference platform
supporting multiple FPGA SoC's.

This format is based on some of the mips binding docs as we have
similar requirements.

Also, update maintainers so openrisc related binding changes are visible
to the openrisc team.

Suggested-by: Pavel Machek 
Signed-off-by: Stafford Horne 
---
 .../bindings/openrisc/opencores/or1ksim.txt| 39 ++
 MAINTAINERS|  1 +
 2 files changed, 40 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt

diff --git a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt 
b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
new file mode 100644
index ..4950c794ecbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
@@ -0,0 +1,39 @@
+OpenRISC Generic SoC
+
+
+Boards and FPGA SoC's which support the OpenRISC standard platform.  The
+platform essentially follows the conventions of the OpenRISC architecture
+specification, however some aspects, such as the boot protocol have been 
defined
+by the Linux port.
+
+Required properties
+---
+ - compatible: Must include "opencores,or1ksim"
+
+CPU nodes:
+--
+A "cpus" node is required.  Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required for at least CPU 0.  Since the topology may
+be probed via CPS, it is not necessary to specify secondary CPUs.  Required
+properties:
+ - compatible: Must be "opencores,or1200-rtlsvn481".
+ - reg: CPU number.
+ - clock-frequency: The CPU clock frequency in Hz.
+Example:
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <0>;
+   clock-frequency = <2000>;
+   };
+   };
+
+
+Boot protocol
+-
+The bootloader may pass the following arguments to the kernel:
+ - r3:  address of a flattened device-tree blob or 0x0.
diff --git a/MAINTAINERS b/MAINTAINERS
index a57d13cb414d..71e4f6762196 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10008,6 +10008,7 @@ T:  git git://github.com/openrisc/linux.git
 L: openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
+F; Documentation/devicetree/bindings/openrisc/
 F: Documentation/openrisc/
 F: arch/openrisc/
 F: drivers/irqchip/irq-or1k-*
-- 
2.13.6

[PATCH 1/3] Documentation: Move OpenRISC docs out of arch/

[Stafford Horne]

The OpenRISC docs have traditionally been in arch/ but that does not
seem like the correct place to be.  Move them so they will be more
visible to others.  Also update MAINTAINERS to make sure we get
notifications of changes.

Signed-off-by: Stafford Horne 
---
 arch/openrisc/README.openrisc => Documentation/openrisc/README | 0
 arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO | 0
 MAINTAINERS| 1 +
 3 files changed, 1 insertion(+)
 rename arch/openrisc/README.openrisc => Documentation/openrisc/README (100%)
 rename arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO (100%)

diff --git a/arch/openrisc/README.openrisc b/Documentation/openrisc/README
similarity index 100%
rename from arch/openrisc/README.openrisc
rename to Documentation/openrisc/README
diff --git a/arch/openrisc/TODO.openrisc b/Documentation/openrisc/TODO
similarity index 100%
rename from arch/openrisc/TODO.openrisc
rename to Documentation/openrisc/TODO
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ce029872089..a57d13cb414d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10008,6 +10008,7 @@ T:  git git://github.com/openrisc/linux.git
 L: openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
+F: Documentation/openrisc/
 F: arch/openrisc/
 F: drivers/irqchip/irq-or1k-*
 
-- 
2.13.6

[PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC

[Stafford Horne]

Add devicetree binding documentation for the OpenRISC platform
opencores,or1ksim.  This is the main OpenRISC reference platform
supporting multiple FPGA SoC's.

This format is based on some of the mips binding docs as we have
similar requirements.

Also, update maintainers so openrisc related binding changes are visible
to the openrisc team.

Suggested-by: Pavel Machek 
Signed-off-by: Stafford Horne 
---
 .../bindings/openrisc/opencores/or1ksim.txt| 39 ++
 MAINTAINERS|  1 +
 2 files changed, 40 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt

diff --git a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt 
b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
new file mode 100644
index ..4950c794ecbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
@@ -0,0 +1,39 @@
+OpenRISC Generic SoC
+
+
+Boards and FPGA SoC's which support the OpenRISC standard platform.  The
+platform essentially follows the conventions of the OpenRISC architecture
+specification, however some aspects, such as the boot protocol have been 
defined
+by the Linux port.
+
+Required properties
+---
+ - compatible: Must include "opencores,or1ksim"
+
+CPU nodes:
+--
+A "cpus" node is required.  Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required for at least CPU 0.  Since the topology may
+be probed via CPS, it is not necessary to specify secondary CPUs.  Required
+properties:
+ - compatible: Must be "opencores,or1200-rtlsvn481".
+ - reg: CPU number.
+ - clock-frequency: The CPU clock frequency in Hz.
+Example:
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   compatible = "opencores,or1200-rtlsvn481";
+   reg = <0>;
+   clock-frequency = <2000>;
+   };
+   };
+
+
+Boot protocol
+-
+The bootloader may pass the following arguments to the kernel:
+ - r3:  address of a flattened device-tree blob or 0x0.
diff --git a/MAINTAINERS b/MAINTAINERS
index a57d13cb414d..71e4f6762196 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10008,6 +10008,7 @@ T:  git git://github.com/openrisc/linux.git
 L: openr...@lists.librecores.org
 W: http://openrisc.io
 S: Maintained
+F; Documentation/devicetree/bindings/openrisc/
 F: Documentation/openrisc/
 F: arch/openrisc/
 F: drivers/irqchip/irq-or1k-*
-- 
2.13.6

[PATCH 2/3] Documentation: openrisc: Updates to README

[Stafford Horne]

Update the OpenRISC readme to provide some more up-to-date information
on how to get started with OpenRISC.  This includes:

 - remove references to southpole who no longer are consulting for
   OpenRISC (confirmed with Jonas)
 - suggested QEMU instead of the old or1ksim as QEMU is well supported
 - include instructions on how to get an FPGA board running

Suggested-by: Pavel Machek 
Signed-off-by: Stafford Horne 
---
 Documentation/openrisc/README | 65 +--
 1 file changed, 38 insertions(+), 27 deletions(-)

diff --git a/Documentation/openrisc/README b/Documentation/openrisc/README
index 072069ab5100..777a893d533d 100644
--- a/Documentation/openrisc/README
+++ b/Documentation/openrisc/README
@@ -7,13 +7,7 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 
family (or1k).
 For information about OpenRISC processors and ongoing development:
 
website http://openrisc.io
-
-For more information about Linux on OpenRISC, please contact South Pole AB.
-
-   email:  i...@southpole.se
-
-   website:http://southpole.se
-   http://southpoleconsulting.com
+   email   openr...@lists.librecores.org
 
 -
 
@@ -24,37 +18,54 @@ In order to build and run Linux for OpenRISC, you'll need 
at least a basic
 toolchain and, perhaps, the architectural simulator.  Steps to get these bits
 in place are outlined here.
 
-1)  The toolchain can be obtained from openrisc.io.  Instructions for building
-a toolchain can be found at:
+1) Toolchain
+
+Toolchain binaries can be obtained from openrisc.io or our github releases 
page.
+Instructions for building the different toolchains can be found on openrisc.io
+or Stafford's toolchain build and release scripts.
+
+   binarieshttps://github.com/openrisc/or1k-gcc/releases
+   toolchains  https://openrisc.io/software
+   buildinghttps://github.com/stffrdhrn/or1k-toolchain-build
 
-https://github.com/openrisc/tutorials
+2) Building
 
-2) or1ksim (optional)
+Build the Linux kernel as usual
 
-or1ksim is the architectural simulator which will allow you to actually run
-your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
+   make ARCH=openrisc defconfig
+   make ARCH=openrisc
 
-   git clone https://github.com/openrisc/or1ksim.git
+3) Running on FPGA (optional)
 
-   cd or1ksim
-   ./configure --prefix=$OPENRISC_PREFIX
-   make
-   make install
+The OpenRISC community typically uses FuseSoC to manage building and 
programming
+an SoC into an FPGA.  The below is an example of programming a De0 Nano
+development board with the OpenRISC SoC.  During the build FPGA RTL is code
+downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
+tools.  Binaries are loaded onto the board with openocd.
 
-3)  Linux kernel
+   git clone https://github.com/olofk/fusesoc
+   cd fusesoc
+   sudo pip install -e .
 
-Build the kernel as usual
+   fusesoc init
+   fusesoc build de0_nano
+   fusesoc pgm de0_nano
 
-   make ARCH=openrisc defconfig
-   make ARCH=openrisc
+   openocd -f interface/altera-usb-blaster.cfg \
+   -f board/or1k_generic.cfg
+
+   telnet localhost 
+   > init
+   > halt; load_image vmlinux ; reset
 
-4)  Run in architectural simulator
+4) Running on a Simulator (optional)
 
-Grab the or1ksim platform configuration file (from the or1ksim source) and
-together with your freshly built vmlinux, run your kernel with the following
-incantation:
+QEMU is a processor emulator which we recommend for simulating the OpenRISC
+platform.  Please follow the OpenRISC instructions on the QEMU website to get
+Linux running on QEMU.  You can build QEMU yourself, but your Linux 
distribution
+likely provides binary packages to support OpenRISC.
 
-   sim -f arch/openrisc/or1ksim.cfg vmlinux
+   qemu openrisc   https://wiki.qemu.org/Documentation/Platforms/OpenRISC
 
 -
 
-- 
2.13.6

[PATCH 0/3] OpenRISC doc updates

[Stafford Horne]

Hello,

This series moves OpenRISC documentation out of the arch/ folder and into the
Documentation folder.  I have also done some updates the README to bring to
better match the current state of OpenRISC.

Also, this adds documentation to the openrisc,or1ksim device tree binding which
was previously not documented.

Stafford Horne (3):
  Documentation: Move OpenRISC docs out of arch/
  Documentation: openrisc: Updates to README
  openrisc: dts: Add OpenRISC platform SoC

 .../bindings/openrisc/opencores/or1ksim.txt| 39 +
 .../openrisc/README| 65 +-
 .../TODO.openrisc => Documentation/openrisc/TODO   |  0
 MAINTAINERS|  2 +
 4 files changed, 79 insertions(+), 27 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
 rename arch/openrisc/README.openrisc => Documentation/openrisc/README (56%)
 rename arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO (100%)

-- 
2.13.6

[PATCH 2/3] Documentation: openrisc: Updates to README

[Stafford Horne]

Update the OpenRISC readme to provide some more up-to-date information
on how to get started with OpenRISC.  This includes:

 - remove references to southpole who no longer are consulting for
   OpenRISC (confirmed with Jonas)
 - suggested QEMU instead of the old or1ksim as QEMU is well supported
 - include instructions on how to get an FPGA board running

Suggested-by: Pavel Machek 
Signed-off-by: Stafford Horne 
---
 Documentation/openrisc/README | 65 +--
 1 file changed, 38 insertions(+), 27 deletions(-)

diff --git a/Documentation/openrisc/README b/Documentation/openrisc/README
index 072069ab5100..777a893d533d 100644
--- a/Documentation/openrisc/README
+++ b/Documentation/openrisc/README
@@ -7,13 +7,7 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 
family (or1k).
 For information about OpenRISC processors and ongoing development:
 
website http://openrisc.io
-
-For more information about Linux on OpenRISC, please contact South Pole AB.
-
-   email:  i...@southpole.se
-
-   website:http://southpole.se
-   http://southpoleconsulting.com
+   email   openr...@lists.librecores.org
 
 -
 
@@ -24,37 +18,54 @@ In order to build and run Linux for OpenRISC, you'll need 
at least a basic
 toolchain and, perhaps, the architectural simulator.  Steps to get these bits
 in place are outlined here.
 
-1)  The toolchain can be obtained from openrisc.io.  Instructions for building
-a toolchain can be found at:
+1) Toolchain
+
+Toolchain binaries can be obtained from openrisc.io or our github releases 
page.
+Instructions for building the different toolchains can be found on openrisc.io
+or Stafford's toolchain build and release scripts.
+
+   binarieshttps://github.com/openrisc/or1k-gcc/releases
+   toolchains  https://openrisc.io/software
+   buildinghttps://github.com/stffrdhrn/or1k-toolchain-build
 
-https://github.com/openrisc/tutorials
+2) Building
 
-2) or1ksim (optional)
+Build the Linux kernel as usual
 
-or1ksim is the architectural simulator which will allow you to actually run
-your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
+   make ARCH=openrisc defconfig
+   make ARCH=openrisc
 
-   git clone https://github.com/openrisc/or1ksim.git
+3) Running on FPGA (optional)
 
-   cd or1ksim
-   ./configure --prefix=$OPENRISC_PREFIX
-   make
-   make install
+The OpenRISC community typically uses FuseSoC to manage building and 
programming
+an SoC into an FPGA.  The below is an example of programming a De0 Nano
+development board with the OpenRISC SoC.  During the build FPGA RTL is code
+downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
+tools.  Binaries are loaded onto the board with openocd.
 
-3)  Linux kernel
+   git clone https://github.com/olofk/fusesoc
+   cd fusesoc
+   sudo pip install -e .
 
-Build the kernel as usual
+   fusesoc init
+   fusesoc build de0_nano
+   fusesoc pgm de0_nano
 
-   make ARCH=openrisc defconfig
-   make ARCH=openrisc
+   openocd -f interface/altera-usb-blaster.cfg \
+   -f board/or1k_generic.cfg
+
+   telnet localhost 
+   > init
+   > halt; load_image vmlinux ; reset
 
-4)  Run in architectural simulator
+4) Running on a Simulator (optional)
 
-Grab the or1ksim platform configuration file (from the or1ksim source) and
-together with your freshly built vmlinux, run your kernel with the following
-incantation:
+QEMU is a processor emulator which we recommend for simulating the OpenRISC
+platform.  Please follow the OpenRISC instructions on the QEMU website to get
+Linux running on QEMU.  You can build QEMU yourself, but your Linux 
distribution
+likely provides binary packages to support OpenRISC.
 
-   sim -f arch/openrisc/or1ksim.cfg vmlinux
+   qemu openrisc   https://wiki.qemu.org/Documentation/Platforms/OpenRISC
 
 -
 
-- 
2.13.6

[PATCH 0/3] OpenRISC doc updates

[Stafford Horne]

Hello,

This series moves OpenRISC documentation out of the arch/ folder and into the
Documentation folder.  I have also done some updates the README to bring to
better match the current state of OpenRISC.

Also, this adds documentation to the openrisc,or1ksim device tree binding which
was previously not documented.

Stafford Horne (3):
  Documentation: Move OpenRISC docs out of arch/
  Documentation: openrisc: Updates to README
  openrisc: dts: Add OpenRISC platform SoC

 .../bindings/openrisc/opencores/or1ksim.txt| 39 +
 .../openrisc/README| 65 +-
 .../TODO.openrisc => Documentation/openrisc/TODO   |  0
 MAINTAINERS|  2 +
 4 files changed, 79 insertions(+), 27 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
 rename arch/openrisc/README.openrisc => Documentation/openrisc/README (56%)
 rename arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO (100%)

-- 
2.13.6

[GIT] Networking

[David Miller]

A little more than usual this time around.  Been travelling, so that is
part of it.

Anyways, here are the highlights:

1) Deal with memcontrol races wrt. listener dismantle, from Eric
   Dumazet.

2) Handle page allocation failures properly in nfp driver, from
   Jaku Kicinski.

3) Fix memory leaks in macsec, from Sabrina Dubroca.

4) Fix crashes in pppol2tp_session_ioctl(), from Guillaume Nault.

5) Several fixes in bnxt_en driver, including preventing potential NVRAM
   parameter corruption from Michael Chan.

6) Fix for KRACK attacks in wireless, from Johannes Berg.

7) rtnetlink event generation fixes from Xin Long.

8) Deadlock in mlxsw driver, from Ido Schimmel.

9) Disallow arithmetic operations on context pointers in bpf, from
   Jakub Kicinski.

10) Missing sock_owned_by_user() check in sctp_icmp_redirect(), from
Xin Long.

11) Only TCP is supported for sockmap, make that explicit with a check,
from John Fastabend.

12) Fix IP options state races in DCCP and TCP, from Eric Dumazet.

13) Fix panic in packet_getsockopt(), also from Eric Dumazet.

14) Add missing locked in hv_sock layer, from Dexuan Cui.

15) Various aquantia bug fixes, including several statistics handling
cures.  From Igor Russkikh et al.

16) Fix arithmetic overflow in devmap code, from John Fastabend.

17) Fix busted socket memory accounting when we get a fault in the tcp
zero copy paths.  From Willem de Bruijn.

18) Don't leave opt->tot_len uninitialized in ipv6, from Eric Dumazet.

Please pull, thanks a lot!

The following changes since commit 529a86e063e9ff625c4ff247d8aa17d8072444fb:

  Merge branch 'ppc-bundle' (bundle from Michael Ellerman) (2017-10-09 19:08:32 
-0700)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git 

for you to fetch changes up to 8d5f4b07174976c55a5f5d696373c6826944:

  stmmac: Don't access tx_q->dirty_tx before netif_tx_lock (2017-10-22 03:24:43 
+0100)


Alexander Duyck (1):
  i40e: Fix memory leak related filter programming status

Arnd Bergmann (2):
  brcmsmac: make some local variables 'static const' to reduce stack size
  liquidio: fix timespec64_to_ns typo

Behan Webster (1):
  wimax/i2400m: Remove VLAIS

Bernd Edlinger (1):
  stmmac: Don't access tx_q->dirty_tx before netif_tx_lock

Chaya Rachel Ivgi (1):
  iwlwifi: nvm: set the correct offsets to 3168 series

Colin Ian King (1):
  can: bcm: check for null sk before deferencing it via the call to sock_net

Cong Wang (1):
  tun: call dev_get_valid_name() before register_netdevice()

Craig Gallek (1):
  soreuseport: fix initialization race

Daniel Borkmann (6):
  mm, percpu: add support for __GFP_NOWARN flag
  bpf: fix splat for illegal devmap percpu allocation
  bpf: do not test for PCPU_MIN_UNIT_SIZE before percpu allocations
  bpf: fix off by one for range markings with L{T, E} patterns
  bpf: fix pattern matches for direct packet access
  bpf: add test cases to bpf selftests to cover all access tests

Daniel Drake (1):
  r8169: only enable PCI wakeups when WOL is active

David Howells (1):
  rxrpc: Don't release call mutex on error pointer

David S. Miller (14):
  Merge branch '40GbE' of git://git.kernel.org/.../jkirsher/net-queue
  Merge branch 'nfp-fix-ethtool-stats-and-page-allocation'
  Merge tag 'wireless-drivers-for-davem-2017-10-13' of 
git://git.kernel.org/.../kvalo/wireless-drivers
  Merge branch 'bnxt_en-fixes'
  Merge branch 'rtnetlink-dev-notification-fixes'
  Merge tag 'mac80211-for-davem-2017-10-16' of 
git://git.kernel.org/.../jberg/mac80211
  Merge branch 'ena-fixes'
  Merge branch 'bpf-Fix-for-BPF-devmap-percpu-allocation-splat'
  Merge branch 'sockmap-fixes'
  Merge tag 'linux-can-fixes-for-4.14-20171019' of 
git://git.kernel.org/.../mkl/linux-can
  Merge branch 'aquantia-fixes'
  Merge branch 'bpf-range-marking-fixes'
  Merge branch 'mlxsw-fixes'
  Merge branch 'stmmac-hw-tstamp-fixes'

Dexuan Cui (1):
  hv_sock: add locking in the open/close/release code paths

Emiliano Ingrassia (1):
  net: stmmac: dwmac_lib: fix interchanged sleep/timeout values in DMA 
reset function

Eric Dumazet (7):
  net: memcontrol: defer call to mem_cgroup_sk_alloc()
  net: defer call to cgroup_sk_alloc()
  Revert "net: defer call to cgroup_sk_alloc()"
  net: call cgroup_sk_alloc() earlier in sk_clone_lock()
  tcp/dccp: fix ireq->opt races
  packet: avoid panic in packet_getsockopt()
  ipv6: flowlabel: do not leave opt->tot_len with garbage

Gavin Shan (3):
  net/ncsi: Disable HWA mode when no channels are found
  net/ncsi: Enforce failover on link monitor timeout
  net/ncsi: Fix length of GVI response packet

Geert Uytterhoeven (1):
  of_mdio: Fix broken PHY IRQ in case of probe deferral

Golan Ben Ami (1):
  iwlwifi: stop dbgc 

[GIT] Networking

[David Miller]

A little more than usual this time around.  Been travelling, so that is
part of it.

Anyways, here are the highlights:

1) Deal with memcontrol races wrt. listener dismantle, from Eric
   Dumazet.

2) Handle page allocation failures properly in nfp driver, from
   Jaku Kicinski.

3) Fix memory leaks in macsec, from Sabrina Dubroca.

4) Fix crashes in pppol2tp_session_ioctl(), from Guillaume Nault.

5) Several fixes in bnxt_en driver, including preventing potential NVRAM
   parameter corruption from Michael Chan.

6) Fix for KRACK attacks in wireless, from Johannes Berg.

7) rtnetlink event generation fixes from Xin Long.

8) Deadlock in mlxsw driver, from Ido Schimmel.

9) Disallow arithmetic operations on context pointers in bpf, from
   Jakub Kicinski.

10) Missing sock_owned_by_user() check in sctp_icmp_redirect(), from
Xin Long.

11) Only TCP is supported for sockmap, make that explicit with a check,
from John Fastabend.

12) Fix IP options state races in DCCP and TCP, from Eric Dumazet.

13) Fix panic in packet_getsockopt(), also from Eric Dumazet.

14) Add missing locked in hv_sock layer, from Dexuan Cui.

15) Various aquantia bug fixes, including several statistics handling
cures.  From Igor Russkikh et al.

16) Fix arithmetic overflow in devmap code, from John Fastabend.

17) Fix busted socket memory accounting when we get a fault in the tcp
zero copy paths.  From Willem de Bruijn.

18) Don't leave opt->tot_len uninitialized in ipv6, from Eric Dumazet.

Please pull, thanks a lot!

The following changes since commit 529a86e063e9ff625c4ff247d8aa17d8072444fb:

  Merge branch 'ppc-bundle' (bundle from Michael Ellerman) (2017-10-09 19:08:32 
-0700)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git 

for you to fetch changes up to 8d5f4b07174976c55a5f5d696373c6826944:

  stmmac: Don't access tx_q->dirty_tx before netif_tx_lock (2017-10-22 03:24:43 
+0100)


Alexander Duyck (1):
  i40e: Fix memory leak related filter programming status

Arnd Bergmann (2):
  brcmsmac: make some local variables 'static const' to reduce stack size
  liquidio: fix timespec64_to_ns typo

Behan Webster (1):
  wimax/i2400m: Remove VLAIS

Bernd Edlinger (1):
  stmmac: Don't access tx_q->dirty_tx before netif_tx_lock

Chaya Rachel Ivgi (1):
  iwlwifi: nvm: set the correct offsets to 3168 series

Colin Ian King (1):
  can: bcm: check for null sk before deferencing it via the call to sock_net

Cong Wang (1):
  tun: call dev_get_valid_name() before register_netdevice()

Craig Gallek (1):
  soreuseport: fix initialization race

Daniel Borkmann (6):
  mm, percpu: add support for __GFP_NOWARN flag
  bpf: fix splat for illegal devmap percpu allocation
  bpf: do not test for PCPU_MIN_UNIT_SIZE before percpu allocations
  bpf: fix off by one for range markings with L{T, E} patterns
  bpf: fix pattern matches for direct packet access
  bpf: add test cases to bpf selftests to cover all access tests

Daniel Drake (1):
  r8169: only enable PCI wakeups when WOL is active

David Howells (1):
  rxrpc: Don't release call mutex on error pointer

David S. Miller (14):
  Merge branch '40GbE' of git://git.kernel.org/.../jkirsher/net-queue
  Merge branch 'nfp-fix-ethtool-stats-and-page-allocation'
  Merge tag 'wireless-drivers-for-davem-2017-10-13' of 
git://git.kernel.org/.../kvalo/wireless-drivers
  Merge branch 'bnxt_en-fixes'
  Merge branch 'rtnetlink-dev-notification-fixes'
  Merge tag 'mac80211-for-davem-2017-10-16' of 
git://git.kernel.org/.../jberg/mac80211
  Merge branch 'ena-fixes'
  Merge branch 'bpf-Fix-for-BPF-devmap-percpu-allocation-splat'
  Merge branch 'sockmap-fixes'
  Merge tag 'linux-can-fixes-for-4.14-20171019' of 
git://git.kernel.org/.../mkl/linux-can
  Merge branch 'aquantia-fixes'
  Merge branch 'bpf-range-marking-fixes'
  Merge branch 'mlxsw-fixes'
  Merge branch 'stmmac-hw-tstamp-fixes'

Dexuan Cui (1):
  hv_sock: add locking in the open/close/release code paths

Emiliano Ingrassia (1):
  net: stmmac: dwmac_lib: fix interchanged sleep/timeout values in DMA 
reset function

Eric Dumazet (7):
  net: memcontrol: defer call to mem_cgroup_sk_alloc()
  net: defer call to cgroup_sk_alloc()
  Revert "net: defer call to cgroup_sk_alloc()"
  net: call cgroup_sk_alloc() earlier in sk_clone_lock()
  tcp/dccp: fix ireq->opt races
  packet: avoid panic in packet_getsockopt()
  ipv6: flowlabel: do not leave opt->tot_len with garbage

Gavin Shan (3):
  net/ncsi: Disable HWA mode when no channels are found
  net/ncsi: Enforce failover on link monitor timeout
  net/ncsi: Fix length of GVI response packet

Geert Uytterhoeven (1):
  of_mdio: Fix broken PHY IRQ in case of probe deferral

Golan Ben Ami (1):
  iwlwifi: stop dbgc 

Re: [GIT PULL] Documentation: Add a file explaining the requested Linux kernel license enforcement policy

[Bradley M. Kuhn]

> On Thu, Oct 19, 2017 at 06:28:12PM +0300, Pavel Nikulin wrote:
> Modification of GPL V2 terms are explicitly disallowed.

Greg KH replied at 03:29 (US/Eastern) on Friday:
>> Again, we are not modifying the license, so all should be fine

I agree with Greg; the Linux Kernel Enforcement Statement does not change
the license of Linux as a whole, and it does not modify the GPLv2.

Pavel Nikulin wrote at 11:28 (US/Eastern) on Thursday:
> Greg, are you trying to put a new addendum to the terms of GPL v2?
...
Pavel Nikulin wrote further at 15:16 (US/Eastern) today:
> If you say that your lawyers have comprehensively researched that,
> I can't say they did a good job. Almost every line sounds close to
> being a contractual agreement.
...
> And even this last phrase does not states explicitly that the nature of
> the document as non-legally binding.
...
> Moreover, you put "additional permissions under our license" wording
> there,

Certainly this issue is complicated.
https://sfconservancy.org/blog/2017/oct/20/additional-permissions/ might
help.  I decided yesterday to write a blog post digging deep into the weeds
on this, for those interested.
-- 
Bradley M. Kuhn
Distinguished Technologist of Software Freedom Conservancy

Become a Conservancy Supporter today: https://sfconservancy.org/supporter

Re: [GIT PULL] Documentation: Add a file explaining the requested Linux kernel license enforcement policy

[Bradley M. Kuhn]

> On Thu, Oct 19, 2017 at 06:28:12PM +0300, Pavel Nikulin wrote:
> Modification of GPL V2 terms are explicitly disallowed.

Greg KH replied at 03:29 (US/Eastern) on Friday:
>> Again, we are not modifying the license, so all should be fine

I agree with Greg; the Linux Kernel Enforcement Statement does not change
the license of Linux as a whole, and it does not modify the GPLv2.

Pavel Nikulin wrote at 11:28 (US/Eastern) on Thursday:
> Greg, are you trying to put a new addendum to the terms of GPL v2?
...
Pavel Nikulin wrote further at 15:16 (US/Eastern) today:
> If you say that your lawyers have comprehensively researched that,
> I can't say they did a good job. Almost every line sounds close to
> being a contractual agreement.
...
> And even this last phrase does not states explicitly that the nature of
> the document as non-legally binding.
...
> Moreover, you put "additional permissions under our license" wording
> there,

Certainly this issue is complicated.
https://sfconservancy.org/blog/2017/oct/20/additional-permissions/ might
help.  I decided yesterday to write a blog post digging deep into the weeds
on this, for those interested.
-- 
Bradley M. Kuhn
Distinguished Technologist of Software Freedom Conservancy

Become a Conservancy Supporter today: https://sfconservancy.org/supporter

Re: [PATCH] stmmac: Don't access tx_q->dirty_tx before netif_tx_lock

[David Miller]

From: Bernd Edlinger 
Date: Sat, 21 Oct 2017 06:51:30 +

> This is the possible reason for different hard to reproduce
> problems on my ARMv7-SMP test system.
> 
> The symptoms are in recent kernels imprecise external aborts,
> and in older kernels various kinds of network stalls and
> unexpected page allocation failures.
> 
> My testing indicates that the trouble started between v4.5 and v4.6
> and prevails up to v4.14.
> 
> Using the dirty_tx before acquiring the spin lock is clearly
> wrong and was first introduced with v4.6.
> 
> Fixes: e3ad57c96715 ("stmmac: review RX/TX ring management")
> 
> Signed-off-by: Bernd Edlinger 

Applied, thank you.

Re: [PATCH] stmmac: Don't access tx_q->dirty_tx before netif_tx_lock

[David Miller]

From: Bernd Edlinger 
Date: Sat, 21 Oct 2017 06:51:30 +

> This is the possible reason for different hard to reproduce
> problems on my ARMv7-SMP test system.
> 
> The symptoms are in recent kernels imprecise external aborts,
> and in older kernels various kinds of network stalls and
> unexpected page allocation failures.
> 
> My testing indicates that the trouble started between v4.5 and v4.6
> and prevails up to v4.14.
> 
> Using the dirty_tx before acquiring the spin lock is clearly
> wrong and was first introduced with v4.6.
> 
> Fixes: e3ad57c96715 ("stmmac: review RX/TX ring management")
> 
> Signed-off-by: Bernd Edlinger 

Applied, thank you.

[PATCH v2] openrisc: dts: or1ksim: Add stdout-path

[Stafford Horne]

During reviews of the OpenRISC SMP patch series it was suggested to add
stdout-path to the SMP dts file.  Add stdout-path to our other dts files
to be a good example.

Cc: Geert Uytterhoeven 
Signed-off-by: Stafford Horne 
---

Changes since v1
 - Complete rewrite with input from Geert

 arch/openrisc/boot/dts/or1ksim.dts | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/boot/dts/or1ksim.dts 
b/arch/openrisc/boot/dts/or1ksim.dts
index 5d4f9027afaf..8f41bd8c9f84 100644
--- a/arch/openrisc/boot/dts/or1ksim.dts
+++ b/arch/openrisc/boot/dts/or1ksim.dts
@@ -5,8 +5,13 @@
#size-cells = <1>;
interrupt-parent = <>;
 
+   aliases {
+   uart0 = 
+   };
+
chosen {
-   bootargs = "console=uart,mmio,0x9000,115200";
+   bootargs = "earlycon";
+   stdout-path = "uart0:115200";
};
 
memory@0 {
-- 
2.13.6

[PATCH v2] openrisc: dts: or1ksim: Add stdout-path

[Stafford Horne]

During reviews of the OpenRISC SMP patch series it was suggested to add
stdout-path to the SMP dts file.  Add stdout-path to our other dts files
to be a good example.

Cc: Geert Uytterhoeven 
Signed-off-by: Stafford Horne 
---

Changes since v1
 - Complete rewrite with input from Geert

 arch/openrisc/boot/dts/or1ksim.dts | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/boot/dts/or1ksim.dts 
b/arch/openrisc/boot/dts/or1ksim.dts
index 5d4f9027afaf..8f41bd8c9f84 100644
--- a/arch/openrisc/boot/dts/or1ksim.dts
+++ b/arch/openrisc/boot/dts/or1ksim.dts
@@ -5,8 +5,13 @@
#size-cells = <1>;
interrupt-parent = <>;
 
+   aliases {
+   uart0 = 
+   };
+
chosen {
-   bootargs = "console=uart,mmio,0x9000,115200";
+   bootargs = "earlycon";
+   stdout-path = "uart0:115200";
};
 
memory@0 {
-- 
2.13.6

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[David Miller]

From: Florian Fainelli 
Date: Sat, 21 Oct 2017 19:01:45 -0700

> Reviewed-by : Florian Fainelli 
> 
> I still can't make sure this is not a problem for multiple PHYs
> hanging off the same bus, but like anything else, we'll deal with
> problems later if they arise.

Thanks Florian.

Applied, thanks everyone.

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[David Miller]

From: Florian Fainelli 
Date: Sat, 21 Oct 2017 19:01:45 -0700

> Reviewed-by : Florian Fainelli 
> 
> I still can't make sure this is not a problem for multiple PHYs
> hanging off the same bus, but like anything else, we'll deal with
> problems later if they arise.

Thanks Florian.

Applied, thanks everyone.

Re: [PATCH] net: smc_close: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Sat, 21 Oct 2017 20:21:00 -0500

> 
> Quoting David Miller :
> 
>> From: "Gustavo A. R. Silva" 
>> Date: Thu, 19 Oct 2017 17:02:44 -0500
>>
>>> @@ -360,7 +360,8 @@ static void smc_close_passive_work(struct
>>> work_struct *work)
>>> case SMC_PEERCLOSEWAIT1:
>>> if (rxflags->peer_done_writing)
>>> sk->sk_state = SMC_PEERCLOSEWAIT2;
>>> -   /* fall through to check for closing */
>>> +   /* to check for closing */
>>> +   /* fall through */
>>
>> Gustavo please look at what you are doing to the code.
>>
>> This was a nice easy to read sentence in the comment, and now
>> you've chopped it up into two pieces and made it awkward and
>> more difficult to read.
> 
> You're right.
> 
> What about this instead:
> 
> /* fall through */
> /* to check for closing */

I'm surprised gcc cares if it's all on one line or not, actually.

Re: [PATCH] net: smc_close: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Sat, 21 Oct 2017 20:21:00 -0500

> 
> Quoting David Miller :
> 
>> From: "Gustavo A. R. Silva" 
>> Date: Thu, 19 Oct 2017 17:02:44 -0500
>>
>>> @@ -360,7 +360,8 @@ static void smc_close_passive_work(struct
>>> work_struct *work)
>>> case SMC_PEERCLOSEWAIT1:
>>> if (rxflags->peer_done_writing)
>>> sk->sk_state = SMC_PEERCLOSEWAIT2;
>>> -   /* fall through to check for closing */
>>> +   /* to check for closing */
>>> +   /* fall through */
>>
>> Gustavo please look at what you are doing to the code.
>>
>> This was a nice easy to read sentence in the comment, and now
>> you've chopped it up into two pieces and made it awkward and
>> more difficult to read.
> 
> You're right.
> 
> What about this instead:
> 
> /* fall through */
> /* to check for closing */

I'm surprised gcc cares if it's all on one line or not, actually.

Re: [PATCH] net: x25: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:37:52 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

Applied.

Re: [PATCH] net: x25: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:37:52 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

Applied.

Re: [PATCH] net: af_unix: mark expected switch fall-through

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:05:30 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

Applied.

Re: [PATCH] net: af_unix: mark expected switch fall-through

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:05:30 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

Applied.

Re: [PATCH] net: tipc: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:01:26 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

This doesn't apply to net-next.

Re: [PATCH] net: tipc: mark expected switch fall-throughs

[David Miller]

From: "Gustavo A. R. Silva" 
Date: Fri, 20 Oct 2017 12:01:26 -0500

> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva 

This doesn't apply to net-next.

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[Florian Fainelli]

On October 21, 2017 6:37:38 PM PDT, David Miller  wrote:
>
>Second ping, this patch needs a review ASAP.
>
>Geert's hard-resetting PHY changes depend upon this change.

Done, same concerns as before and we could all improve on trying to get this 
tested on a pure SW model (e.g QEMU) but there is only so little time... 
Regarding the other patch series it needs more love before it gets merged, so 
that hopefully lowers the criticality.

-- 
Florian

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[Florian Fainelli]

On October 21, 2017 6:37:38 PM PDT, David Miller  wrote:
>
>Second ping, this patch needs a review ASAP.
>
>Geert's hard-resetting PHY changes depend upon this change.

Done, same concerns as before and we could all improve on trying to get this 
tested on a pure SW model (e.g QEMU) but there is only so little time... 
Regarding the other patch series it needs more love before it gets merged, so 
that hopefully lowers the criticality.

-- 
Florian

Re: [PATCH net-next 0/3] net: stmmac: Fix HW timestamping

[David Miller]

From: Jose Abreu 
Date: Fri, 20 Oct 2017 14:37:33 +0100

> Three fixes for HW timestamping feature, all of them for RX side.

Series applied to 'net', thanks.

Re: [PATCH net-next 0/3] net: stmmac: Fix HW timestamping

[David Miller]

From: Jose Abreu 
Date: Fri, 20 Oct 2017 14:37:33 +0100

> Three fixes for HW timestamping feature, all of them for RX side.

Series applied to 'net', thanks.

Re: [PATCH net] rxrpc: Don't release call mutex on error pointer

[David Miller]

From: David Howells 
Date: Fri, 20 Oct 2017 17:01:22 +0100

> Don't release call mutex at the end of rxrpc_kernel_begin_call() if the
> call pointer actually holds an error value.
> 
> Fixes: 540b1c48c37a ("rxrpc: Fix deadlock between call creation and 
> sendmsg/recvmsg")
> Reported-by: Marc Dionne 
> Signed-off-by: David Howells 

Applied, thanks David.

Re: [PATCH net] rxrpc: Don't release call mutex on error pointer

[David Miller]

From: David Howells 
Date: Fri, 20 Oct 2017 17:01:22 +0100

> Don't release call mutex at the end of rxrpc_kernel_begin_call() if the
> call pointer actually holds an error value.
> 
> Fixes: 540b1c48c37a ("rxrpc: Fix deadlock between call creation and 
> sendmsg/recvmsg")
> Reported-by: Marc Dionne 
> Signed-off-by: David Howells 

Applied, thanks David.

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[Florian Fainelli]

On October 18, 2017 4:54:03 AM PDT, Geert Uytterhoeven 
 wrote:
>If an Ethernet PHY is initialized before the interrupt controller it is
>connected to, a message like the following is printed:
>
>irq: no irq domain found for /interrupt-controller@e61c !
>
>However, the actual error is ignored, leading to a non-functional
>(POLL)
>PHY interrupt later:
>
>Micrel KSZ8041RNLI ee70.ethernet-:01: attached PHY driver
>[Micrel KSZ8041RNLI] (mii_bus:phy_addr=ee70.ethernet-:01,
>irq=POLL)
>
>Depending on whether the PHY driver will fall back to polling, Ethernet
>may or may not work.
>
>To fix this:
>  1. Switch of_mdiobus_register_phy() from irq_of_parse_and_map() to
> of_irq_get().
> Unlike the former, the latter returns -EPROBE_DEFER if the
>interrupt controller is not yet available, so this condition can be
> detected.
> Other errors are handled the same as before, i.e. use the passed
> mdio->irq[addr] as interrupt.
>  2. Propagate and handle errors from of_mdiobus_register_phy() and
> of_mdiobus_register_device().
>
>Signed-off-by: Geert Uytterhoeven 

Reviewed-by : Florian Fainelli 

I still can't make sure this is not a problem for multiple PHYs hanging off the 
same bus, but like anything else, we'll deal with problems later if they arise.

>---
>Seen on e.g. r8a7791/koelsch when using the new CPG/MSSR clock driver,
>which will hit upstream in v4.15.  I assume it always happened on RZ/G1
>in mainline.
>
>The actual patch is unchanged since v1, sent on May 18.  Obviously I
>still cannot test it on a system with multiple PHYs, just like v1.
>
>How can we proceed?
>
>Note that if you are worried about the MDIO subsystem not handling
>(partial) teardown and reprobe correctly in the presence of multiple
>PHYs, that can already be triggered since commit a5597008dbc23087
>("phy:
>fixed_phy: Add gpio to determine link up/down."), which handles
>EPROBE_DEFER for GPIOs.
>
>Thanks!
>
>v2:
> - Update for non-functional interrupts being printed as "POLL" instead
>of "-1" since commit 5e369aefdce4818c ("net: stmmac: Delete dead
>code for MDIO registration").
>---
> drivers/of/of_mdio.c | 39 +++
> 1 file changed, 27 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
>index d94dd8b77abd5140..98258583abb0b405 100644
>--- a/drivers/of/of_mdio.c
>+++ b/drivers/of/of_mdio.c
>@@ -44,7 +44,7 @@ static int of_get_phy_id(struct device_node *device,
>u32 *phy_id)
>   return -EINVAL;
> }
> 
>-static void of_mdiobus_register_phy(struct mii_bus *mdio,
>+static int of_mdiobus_register_phy(struct mii_bus *mdio,
>   struct device_node *child, u32 addr)
> {
>   struct phy_device *phy;
>@@ -60,9 +60,13 @@ static void of_mdiobus_register_phy(struct mii_bus
>*mdio,
>   else
>   phy = get_phy_device(mdio, addr, is_c45);
>   if (IS_ERR(phy))
>-  return;
>+  return PTR_ERR(phy);
> 
>-  rc = irq_of_parse_and_map(child, 0);
>+  rc = of_irq_get(child, 0);
>+  if (rc == -EPROBE_DEFER) {
>+  phy_device_free(phy);
>+  return rc;
>+  }
>   if (rc > 0) {
>   phy->irq = rc;
>   mdio->irq[addr] = rc;
>@@ -84,22 +88,23 @@ static void of_mdiobus_register_phy(struct mii_bus
>*mdio,
>   if (rc) {
>   phy_device_free(phy);
>   of_node_put(child);
>-  return;
>+  return rc;
>   }
> 
>   dev_dbg(>dev, "registered phy %s at address %i\n",
>   child->name, addr);
>+  return 0;
> }
> 
>-static void of_mdiobus_register_device(struct mii_bus *mdio,
>- struct device_node *child, u32 addr)
>+static int of_mdiobus_register_device(struct mii_bus *mdio,
>+struct device_node *child, u32 addr)
> {
>   struct mdio_device *mdiodev;
>   int rc;
> 
>   mdiodev = mdio_device_create(mdio, addr);
>   if (IS_ERR(mdiodev))
>-  return;
>+  return PTR_ERR(mdiodev);
> 
>   /* Associate the OF node with the device structure so it
>* can be looked up later.
>@@ -112,11 +117,12 @@ static void of_mdiobus_register_device(struct
>mii_bus *mdio,
>   if (rc) {
>   mdio_device_free(mdiodev);
>   of_node_put(child);
>-  return;
>+  return rc;
>   }
> 
>   dev_dbg(>dev, "registered mdio device %s at address %i\n",
>   child->name, addr);
>+  return 0;
> }
> 
> /* The following is a list of PHY compatible strings which appear in
>@@ -219,9 +225,11 @@ int of_mdiobus_register(struct mii_bus *mdio,
>struct device_node *np)
>   }
> 
>   if (of_mdiobus_child_is_phy(child))
>-  of_mdiobus_register_phy(mdio, child, addr);
>+ 

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[Florian Fainelli]

On October 18, 2017 4:54:03 AM PDT, Geert Uytterhoeven 
 wrote:
>If an Ethernet PHY is initialized before the interrupt controller it is
>connected to, a message like the following is printed:
>
>irq: no irq domain found for /interrupt-controller@e61c !
>
>However, the actual error is ignored, leading to a non-functional
>(POLL)
>PHY interrupt later:
>
>Micrel KSZ8041RNLI ee70.ethernet-:01: attached PHY driver
>[Micrel KSZ8041RNLI] (mii_bus:phy_addr=ee70.ethernet-:01,
>irq=POLL)
>
>Depending on whether the PHY driver will fall back to polling, Ethernet
>may or may not work.
>
>To fix this:
>  1. Switch of_mdiobus_register_phy() from irq_of_parse_and_map() to
> of_irq_get().
> Unlike the former, the latter returns -EPROBE_DEFER if the
>interrupt controller is not yet available, so this condition can be
> detected.
> Other errors are handled the same as before, i.e. use the passed
> mdio->irq[addr] as interrupt.
>  2. Propagate and handle errors from of_mdiobus_register_phy() and
> of_mdiobus_register_device().
>
>Signed-off-by: Geert Uytterhoeven 

Reviewed-by : Florian Fainelli 

I still can't make sure this is not a problem for multiple PHYs hanging off the 
same bus, but like anything else, we'll deal with problems later if they arise.

>---
>Seen on e.g. r8a7791/koelsch when using the new CPG/MSSR clock driver,
>which will hit upstream in v4.15.  I assume it always happened on RZ/G1
>in mainline.
>
>The actual patch is unchanged since v1, sent on May 18.  Obviously I
>still cannot test it on a system with multiple PHYs, just like v1.
>
>How can we proceed?
>
>Note that if you are worried about the MDIO subsystem not handling
>(partial) teardown and reprobe correctly in the presence of multiple
>PHYs, that can already be triggered since commit a5597008dbc23087
>("phy:
>fixed_phy: Add gpio to determine link up/down."), which handles
>EPROBE_DEFER for GPIOs.
>
>Thanks!
>
>v2:
> - Update for non-functional interrupts being printed as "POLL" instead
>of "-1" since commit 5e369aefdce4818c ("net: stmmac: Delete dead
>code for MDIO registration").
>---
> drivers/of/of_mdio.c | 39 +++
> 1 file changed, 27 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
>index d94dd8b77abd5140..98258583abb0b405 100644
>--- a/drivers/of/of_mdio.c
>+++ b/drivers/of/of_mdio.c
>@@ -44,7 +44,7 @@ static int of_get_phy_id(struct device_node *device,
>u32 *phy_id)
>   return -EINVAL;
> }
> 
>-static void of_mdiobus_register_phy(struct mii_bus *mdio,
>+static int of_mdiobus_register_phy(struct mii_bus *mdio,
>   struct device_node *child, u32 addr)
> {
>   struct phy_device *phy;
>@@ -60,9 +60,13 @@ static void of_mdiobus_register_phy(struct mii_bus
>*mdio,
>   else
>   phy = get_phy_device(mdio, addr, is_c45);
>   if (IS_ERR(phy))
>-  return;
>+  return PTR_ERR(phy);
> 
>-  rc = irq_of_parse_and_map(child, 0);
>+  rc = of_irq_get(child, 0);
>+  if (rc == -EPROBE_DEFER) {
>+  phy_device_free(phy);
>+  return rc;
>+  }
>   if (rc > 0) {
>   phy->irq = rc;
>   mdio->irq[addr] = rc;
>@@ -84,22 +88,23 @@ static void of_mdiobus_register_phy(struct mii_bus
>*mdio,
>   if (rc) {
>   phy_device_free(phy);
>   of_node_put(child);
>-  return;
>+  return rc;
>   }
> 
>   dev_dbg(>dev, "registered phy %s at address %i\n",
>   child->name, addr);
>+  return 0;
> }
> 
>-static void of_mdiobus_register_device(struct mii_bus *mdio,
>- struct device_node *child, u32 addr)
>+static int of_mdiobus_register_device(struct mii_bus *mdio,
>+struct device_node *child, u32 addr)
> {
>   struct mdio_device *mdiodev;
>   int rc;
> 
>   mdiodev = mdio_device_create(mdio, addr);
>   if (IS_ERR(mdiodev))
>-  return;
>+  return PTR_ERR(mdiodev);
> 
>   /* Associate the OF node with the device structure so it
>* can be looked up later.
>@@ -112,11 +117,12 @@ static void of_mdiobus_register_device(struct
>mii_bus *mdio,
>   if (rc) {
>   mdio_device_free(mdiodev);
>   of_node_put(child);
>-  return;
>+  return rc;
>   }
> 
>   dev_dbg(>dev, "registered mdio device %s at address %i\n",
>   child->name, addr);
>+  return 0;
> }
> 
> /* The following is a list of PHY compatible strings which appear in
>@@ -219,9 +225,11 @@ int of_mdiobus_register(struct mii_bus *mdio,
>struct device_node *np)
>   }
> 
>   if (of_mdiobus_child_is_phy(child))
>-  of_mdiobus_register_phy(mdio, child, addr);
>+  rc = of_mdiobus_register_phy(mdio, child, addr);
> 

Re: v4.14-rc3/arm64 DABT exception in atomic_inc() / __skb_clone()

[Wei Wei]

I have uploaded the VM core dump [1]. And I don’t know if these logs are 
helpful in the case of 
failing to get the C reproducer currently.

[1] https://github.com/dotweiba/skb_clone_atomic_inc_bug/blob/master/vmcore.gz

2017/10/21 20:24:32 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': testing program (duration=24s, {Threaded:true Collide:true 
Repeat:true Procs:8 Sandb
ox:setuid Fault:false FaultCall:-1 FaultNth:0 EnableTun:true UseTmpDir:true 
HandleSegv:true WaitRepeat:true Debug:false Repro:true}): 
mmap-socket$inet_tcp-bind$inet-sendto$inet-se
ndto$inet-syz_emit_ethernet
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': program crashed: unable to handle kernel paging request in 
__skb_clone
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': extracting C reproducer
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': reproducing took 1h47m5.070207729s
2017/10/21 20:24:49 reproduction failed: no target compiler

Thanks,
Wei
> On 20 Oct 2017, at 11:39 AM, Willem de Bruijn 
>  wrote:
> 
> On Fri, Oct 20, 2017 at 11:14 AM, Dmitry Vyukov  wrote:
>> On Fri, Oct 20, 2017 at 4:40 PM, Wei Wei  wrote:
>>> Sadly, the syzkaller characterized it as a non-reproducible bug and there 
>>> were empty
>>> repro files. But if manually executing in VM like this “./syz-execprog 
>>> -executor=
>>> ./syz-executor -repeat=0 -procs=16 -cover=0 crash-log”, it crashed when 
>>> executing exactly
>>> program 1056 using log0 provided.
>>> 
>>> I failed to generate the C reproducer with syz-repro as it said “no target 
>>> compiler”
>>> in the final step. I would appreciate if you could give some hints.
>> 
>> syzkaller tries to use aarch64-linux-gnu-gcc when cross-compiling to arm64:
>> https://github.com/google/syzkaller/blob/master/sys/targets/targets.go#L62
>> Try to install g++-aarch64-linux-gnu.
>> Or how should it be done on your system?
> 
> A core dump would also be helpful to root around in and inspect
> what those registers point to. Thanks for posting the various reports
> on github, btw.

Re: v4.14-rc3/arm64 DABT exception in atomic_inc() / __skb_clone()

[Wei Wei]

I have uploaded the VM core dump [1]. And I don’t know if these logs are 
helpful in the case of 
failing to get the C reproducer currently.

[1] https://github.com/dotweiba/skb_clone_atomic_inc_bug/blob/master/vmcore.gz

2017/10/21 20:24:32 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': testing program (duration=24s, {Threaded:true Collide:true 
Repeat:true Procs:8 Sandb
ox:setuid Fault:false FaultCall:-1 FaultNth:0 EnableTun:true UseTmpDir:true 
HandleSegv:true WaitRepeat:true Debug:false Repro:true}): 
mmap-socket$inet_tcp-bind$inet-sendto$inet-se
ndto$inet-syz_emit_ethernet
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': program crashed: unable to handle kernel paging request in 
__skb_clone
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': extracting C reproducer
2017/10/21 20:24:49 reproducing crash 'unable to handle kernel paging request 
in __skb_clone': reproducing took 1h47m5.070207729s
2017/10/21 20:24:49 reproduction failed: no target compiler

Thanks,
Wei
> On 20 Oct 2017, at 11:39 AM, Willem de Bruijn 
>  wrote:
> 
> On Fri, Oct 20, 2017 at 11:14 AM, Dmitry Vyukov  wrote:
>> On Fri, Oct 20, 2017 at 4:40 PM, Wei Wei  wrote:
>>> Sadly, the syzkaller characterized it as a non-reproducible bug and there 
>>> were empty
>>> repro files. But if manually executing in VM like this “./syz-execprog 
>>> -executor=
>>> ./syz-executor -repeat=0 -procs=16 -cover=0 crash-log”, it crashed when 
>>> executing exactly
>>> program 1056 using log0 provided.
>>> 
>>> I failed to generate the C reproducer with syz-repro as it said “no target 
>>> compiler”
>>> in the final step. I would appreciate if you could give some hints.
>> 
>> syzkaller tries to use aarch64-linux-gnu-gcc when cross-compiling to arm64:
>> https://github.com/google/syzkaller/blob/master/sys/targets/targets.go#L62
>> Try to install g++-aarch64-linux-gnu.
>> Or how should it be done on your system?
> 
> A core dump would also be helpful to root around in and inspect
> what those registers point to. Thanks for posting the various reports
> on github, btw.

Re: [PATCH 2/3] watchdog: hpwdt: SMBIOS check

[Jerry Hoemann]

On Fri, Oct 20, 2017 at 07:37:21PM -0700, Guenter Roeck wrote:
> On 10/20/2017 03:54 PM, Jerry Hoemann wrote:
> > Correct test on SMBIOS table 219 Misc Features bits for UEFI supported.
> > 
> Please explain in more detail. There is no table 219 in the SMBIOS 
> specification.

Sorry, my patch documentation was imprecise, I should have stated Type 219 
record.

Type 219 is an HPE OEM SMBIOS extension whose contents are considered
confidential, so I'm not at liberty to go into details.  I will say
that Type 219 describes features of the iLO which hpwdt is implemented
against.


> There is table 9, BIOS Characteristics Extension Byte 2, which specifies bit 3
> as "UEFI Specification is supported.", but nothing that really maps to the
> other byte, and no "misc features". Maybe this is HP specific, but then we'll
> need to have much better explanation.

This patch is to correct commit cce78da766.

Our current servers do not support the CRU BIOS interfaces and we
need to avoid calling it.  Tom initially only checked that iCRU which
replaced CRU was supported.  But, later added code to extend to also
test whether UEFI was supported to anticipate a time when iCRU wasn't
supported either but where we still don't want to call back into CRU.

Tom's original change was implemented to an older definition of Type 219.
Unfortunately, the specification (and firmware) were modified to use a
different pair of bits to represent UEFI.  However, a corresponding change
to update Linux was missed.

The code is currently working today as the iCRU bit is correctly being
checked.  But as the purpose of cce78da766 is to protect the
code for a time when iCRU isn't true, we want to correct the
checking of the UEFI bit.


> 
> > Signed-off-by: Jerry Hoemann 
> > ---
> >   drivers/watchdog/hpwdt.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
> > index ef54b03..4c011e8 100644
> > --- a/drivers/watchdog/hpwdt.c
> > +++ b/drivers/watchdog/hpwdt.c
> > @@ -707,7 +707,7 @@ static void dmi_find_icru(const struct dmi_header *dm, 
> > void *dummy)
> > smbios_proliant_ptr = (struct smbios_proliant_info *) dm;
> > if (smbios_proliant_ptr->misc_features & 0x01)
> > is_icru = 1;
> > -   if (smbios_proliant_ptr->misc_features & 0x408)
> > +   if (smbios_proliant_ptr->misc_features & 0x1400)
> > is_uefi = 1;
> > }
> >   }
> > 
> Presumably patch 2/3 and 3/3 are bug fixs and should come first
> so they can be applied to stable releases.
> 

I can re-order the patches or delay the first patch if necessary.


Thanks
Jerry

-- 

-
Jerry Hoemann  Software Engineer   Hewlett Packard Enterprise
-

Re: [PATCH 2/3] watchdog: hpwdt: SMBIOS check

[Jerry Hoemann]

On Fri, Oct 20, 2017 at 07:37:21PM -0700, Guenter Roeck wrote:
> On 10/20/2017 03:54 PM, Jerry Hoemann wrote:
> > Correct test on SMBIOS table 219 Misc Features bits for UEFI supported.
> > 
> Please explain in more detail. There is no table 219 in the SMBIOS 
> specification.

Sorry, my patch documentation was imprecise, I should have stated Type 219 
record.

Type 219 is an HPE OEM SMBIOS extension whose contents are considered
confidential, so I'm not at liberty to go into details.  I will say
that Type 219 describes features of the iLO which hpwdt is implemented
against.


> There is table 9, BIOS Characteristics Extension Byte 2, which specifies bit 3
> as "UEFI Specification is supported.", but nothing that really maps to the
> other byte, and no "misc features". Maybe this is HP specific, but then we'll
> need to have much better explanation.

This patch is to correct commit cce78da766.

Our current servers do not support the CRU BIOS interfaces and we
need to avoid calling it.  Tom initially only checked that iCRU which
replaced CRU was supported.  But, later added code to extend to also
test whether UEFI was supported to anticipate a time when iCRU wasn't
supported either but where we still don't want to call back into CRU.

Tom's original change was implemented to an older definition of Type 219.
Unfortunately, the specification (and firmware) were modified to use a
different pair of bits to represent UEFI.  However, a corresponding change
to update Linux was missed.

The code is currently working today as the iCRU bit is correctly being
checked.  But as the purpose of cce78da766 is to protect the
code for a time when iCRU isn't true, we want to correct the
checking of the UEFI bit.


> 
> > Signed-off-by: Jerry Hoemann 
> > ---
> >   drivers/watchdog/hpwdt.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
> > index ef54b03..4c011e8 100644
> > --- a/drivers/watchdog/hpwdt.c
> > +++ b/drivers/watchdog/hpwdt.c
> > @@ -707,7 +707,7 @@ static void dmi_find_icru(const struct dmi_header *dm, 
> > void *dummy)
> > smbios_proliant_ptr = (struct smbios_proliant_info *) dm;
> > if (smbios_proliant_ptr->misc_features & 0x01)
> > is_icru = 1;
> > -   if (smbios_proliant_ptr->misc_features & 0x408)
> > +   if (smbios_proliant_ptr->misc_features & 0x1400)
> > is_uefi = 1;
> > }
> >   }
> > 
> Presumably patch 2/3 and 3/3 are bug fixs and should come first
> so they can be applied to stable releases.
> 

I can re-order the patches or delay the first patch if necessary.


Thanks
Jerry

-- 

-
Jerry Hoemann  Software Engineer   Hewlett Packard Enterprise
-

Re: [PATCH v3 net-next 0/2] net: dsa: lan9303: Add fdb/mdb methods

[David Miller]

From: Egil Hjelmeland 
Date: Fri, 20 Oct 2017 12:19:08 +0200

> This series add support for accessing and managing the lan9303 ALR 
> (Address Logic Resolution). 
> 
> The first patch add low level functions for accessing the ALR, along
> with port_fast_age and port_fdb_dump methods.
> 
> The second patch add functions for managing ALR entires, along with
> remaining fdb/mdb methods. 
> 
> Note that to complete STP support, a special ALR entry with the STP eth
> address must be added too. This must be addressed later.

Series applied, thank you.

Re: [PATCH 1/3] watchdog: hpwdt: add ioctl WDIOC_GETPRETIMEOUT

[Jerry Hoemann]

On Fri, Oct 20, 2017 at 07:25:20PM -0700, Guenter Roeck wrote:
> On 10/20/2017 03:54 PM, Jerry Hoemann wrote:
> > Add support for WDIOC_GETPRETIMEOUT ioctl so that user applications
> > can determine when the NMI should arrive.
> > 
> > Signed-off-by: Jerry Hoemann 
> > ---
> >   drivers/watchdog/hpwdt.c | 7 +++
> >   1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
> > index 67fbe35..ef54b03 100644
> > --- a/drivers/watchdog/hpwdt.c
> > +++ b/drivers/watchdog/hpwdt.c
> > @@ -50,6 +50,7 @@
> >   static bool nowayout = WATCHDOG_NOWAYOUT;
> >   static char expect_release;
> >   static unsigned long hpwdt_is_open;
> > +static const int pretimeout = 9;
> >   static void __iomem *pci_mem_addr;/* the PCI-memory 
> > address */
> >   static unsigned long __iomem *hpwdt_timer_reg;
> > @@ -622,6 +623,12 @@ static long hpwdt_ioctl(struct file *file, unsigned 
> > int cmd,
> > }
> > break;
> > +   case WDIOC_GETPRETIMEOUT:
> > +   ret = copy_to_user(argp, , sizeof(pretimeout));
> > +   if (ret)
> > +   ret = -EFAULT;
> > +   break;
> > +
> > case WDIOC_SETTIMEOUT:
> > ret = get_user(new_margin, p);
> > if (ret)
> > 
> 
> Can you please convert the driver to use the watchdog subsystem instead ?
> If there are still improvements needed afterwards, they can still be
> implemented, but we really should not make improvements which are
> already supported by the watchdog core.

I will look into converting the driver, but would like to get this
fix in independently.

SuSE brought https://bugzilla.novell.com/show_bug.cgi?id=1042933
to my attention earlier this summer.  The submitter was trying to
develop a watchdog test where the ping rate was set to be the
Timeout/2.

The test worked fine until (Timeout/2) < PreTimeout.  At this point
an NMI would be delivered to the system before the test could refresh
the timer.

I came to the view that a watchdog that implements a pre-timeout NMI
where the value of the pre-timeout is not known programmatically as having
a defect.

This problem has been around a long time and we could live with it, but
figured while I was in fixing other problems, I'd fix this one as well.

Thanks

-- 

-
Jerry Hoemann  Software Engineer   Hewlett Packard Enterprise
-

Re: [PATCH v3 net-next 0/2] net: dsa: lan9303: Add fdb/mdb methods

[David Miller]

From: Egil Hjelmeland 
Date: Fri, 20 Oct 2017 12:19:08 +0200

> This series add support for accessing and managing the lan9303 ALR 
> (Address Logic Resolution). 
> 
> The first patch add low level functions for accessing the ALR, along
> with port_fast_age and port_fdb_dump methods.
> 
> The second patch add functions for managing ALR entires, along with
> remaining fdb/mdb methods. 
> 
> Note that to complete STP support, a special ALR entry with the STP eth
> address must be added too. This must be addressed later.

Series applied, thank you.

Re: [PATCH 1/3] watchdog: hpwdt: add ioctl WDIOC_GETPRETIMEOUT

[Jerry Hoemann]

On Fri, Oct 20, 2017 at 07:25:20PM -0700, Guenter Roeck wrote:
> On 10/20/2017 03:54 PM, Jerry Hoemann wrote:
> > Add support for WDIOC_GETPRETIMEOUT ioctl so that user applications
> > can determine when the NMI should arrive.
> > 
> > Signed-off-by: Jerry Hoemann 
> > ---
> >   drivers/watchdog/hpwdt.c | 7 +++
> >   1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
> > index 67fbe35..ef54b03 100644
> > --- a/drivers/watchdog/hpwdt.c
> > +++ b/drivers/watchdog/hpwdt.c
> > @@ -50,6 +50,7 @@
> >   static bool nowayout = WATCHDOG_NOWAYOUT;
> >   static char expect_release;
> >   static unsigned long hpwdt_is_open;
> > +static const int pretimeout = 9;
> >   static void __iomem *pci_mem_addr;/* the PCI-memory 
> > address */
> >   static unsigned long __iomem *hpwdt_timer_reg;
> > @@ -622,6 +623,12 @@ static long hpwdt_ioctl(struct file *file, unsigned 
> > int cmd,
> > }
> > break;
> > +   case WDIOC_GETPRETIMEOUT:
> > +   ret = copy_to_user(argp, , sizeof(pretimeout));
> > +   if (ret)
> > +   ret = -EFAULT;
> > +   break;
> > +
> > case WDIOC_SETTIMEOUT:
> > ret = get_user(new_margin, p);
> > if (ret)
> > 
> 
> Can you please convert the driver to use the watchdog subsystem instead ?
> If there are still improvements needed afterwards, they can still be
> implemented, but we really should not make improvements which are
> already supported by the watchdog core.

I will look into converting the driver, but would like to get this
fix in independently.

SuSE brought https://bugzilla.novell.com/show_bug.cgi?id=1042933
to my attention earlier this summer.  The submitter was trying to
develop a watchdog test where the ping rate was set to be the
Timeout/2.

The test worked fine until (Timeout/2) < PreTimeout.  At this point
an NMI would be delivered to the system before the test could refresh
the timer.

I came to the view that a watchdog that implements a pre-timeout NMI
where the value of the pre-timeout is not known programmatically as having
a defect.

This problem has been around a long time and we could live with it, but
figured while I was in fixing other problems, I'd fix this one as well.

Thanks

-- 

-
Jerry Hoemann  Software Engineer   Hewlett Packard Enterprise
-

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[David Miller]

Second ping, this patch needs a review ASAP.

Geert's hard-resetting PHY changes depend upon this change.

Thank you.

Re: [PATCH v2] of_mdio: Fix broken PHY IRQ in case of probe deferral

[David Miller]

Second ping, this patch needs a review ASAP.

Geert's hard-resetting PHY changes depend upon this change.

Thank you.

[PATCH v2] net: smc_close: mark expected switch fall-through

[Gustavo A. R. Silva]

In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.

Notice that in this particular case I placed the "fall through" comment
on its own line, which is what GCC is expecting to find.

Signed-off-by: Gustavo A. R. Silva 
---
Changes in v2:
 Move the "fall through" comment on its own line
 above the rest of the sentence.

 net/smc/smc_close.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c
index f0d16fb..a6c6559 100644
--- a/net/smc/smc_close.c
+++ b/net/smc/smc_close.c
@@ -360,7 +360,8 @@ static void smc_close_passive_work(struct work_struct *work)
case SMC_PEERCLOSEWAIT1:
if (rxflags->peer_done_writing)
sk->sk_state = SMC_PEERCLOSEWAIT2;
-   /* fall through to check for closing */
+   /* fall through */
+   /* to check for closing */
case SMC_PEERCLOSEWAIT2:
case SMC_PEERFINCLOSEWAIT:
if (!smc_cdc_rxed_any_close(>conn))
-- 
2.7.4

[PATCH v2] net: smc_close: mark expected switch fall-through

[Gustavo A. R. Silva]

In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.

Notice that in this particular case I placed the "fall through" comment
on its own line, which is what GCC is expecting to find.

Signed-off-by: Gustavo A. R. Silva 
---
Changes in v2:
 Move the "fall through" comment on its own line
 above the rest of the sentence.

 net/smc/smc_close.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c
index f0d16fb..a6c6559 100644
--- a/net/smc/smc_close.c
+++ b/net/smc/smc_close.c
@@ -360,7 +360,8 @@ static void smc_close_passive_work(struct work_struct *work)
case SMC_PEERCLOSEWAIT1:
if (rxflags->peer_done_writing)
sk->sk_state = SMC_PEERCLOSEWAIT2;
-   /* fall through to check for closing */
+   /* fall through */
+   /* to check for closing */
case SMC_PEERCLOSEWAIT2:
case SMC_PEERFINCLOSEWAIT:
if (!smc_cdc_rxed_any_close(>conn))
-- 
2.7.4

Re: [PATCH 00/15] networking drivers refcount_t conversions

[David Miller]

From: Elena Reshetova 
Date: Fri, 20 Oct 2017 10:23:34 +0300

> Note: these are the last patches related to networking that perform
> conversion of refcounters from atomic_t to refcount_t.
> In contrast to the core network refcounter conversions that
> were merged earlier, these are much more straightforward ones.
> 
> This series, for various networking drivers, replaces atomic_t reference
> counters with the new refcount_t type and API (see include/linux/refcount.h).
> By doing this we prevent intentional or accidental
> underflows or overflows that can led to use-after-free vulnerabilities.
> 
> The patches are fully independent and can be cherry-picked separately.
> Patches are based on top of net-next.
> If there are no objections to the patches, please merge them via respective 
> trees

I've applied this entire series to net-next.  If there are any fixups or
follow-ups please send them as relative patches.

Thank you.

Re: [PATCH 00/15] networking drivers refcount_t conversions

[David Miller]

From: Elena Reshetova 
Date: Fri, 20 Oct 2017 10:23:34 +0300

> Note: these are the last patches related to networking that perform
> conversion of refcounters from atomic_t to refcount_t.
> In contrast to the core network refcounter conversions that
> were merged earlier, these are much more straightforward ones.
> 
> This series, for various networking drivers, replaces atomic_t reference
> counters with the new refcount_t type and API (see include/linux/refcount.h).
> By doing this we prevent intentional or accidental
> underflows or overflows that can led to use-after-free vulnerabilities.
> 
> The patches are fully independent and can be cherry-picked separately.
> Patches are based on top of net-next.
> If there are no objections to the patches, please merge them via respective 
> trees

I've applied this entire series to net-next.  If there are any fixups or
follow-ups please send them as relative patches.

Thank you.