Re: [PATCH 03/20] ARM: dts: aspeed-g4: Correct VUART IRQ number
On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley wrote: > This should have always been 8. > > Signed-off-by: Joel Stanley As this is a bugfix, should we backport it to stable kernels? When you fix a bug, I generally recommend including a 'Fixes' tag with the commit ID of the patch that introduced the problem, and either a 'Cc: sta...@vger.kernel.org' tag if you want it backported, or an explanation in the changelog why it should not get backported. This really helps Greg and the other stable maintainers trying to make a decision what to backport and what not. Arnd
[PATCH net-next v5 2/2] net: ethernet: socionext: add AVE ethernet driver
The UniPhier platform from Socionext provides the AVE ethernet controller that includes MAC and MDIO bus supporting RGMII/RMII modes. The controller is named AVE. Signed-off-by: Kunihiko Hayashi Signed-off-by: Jassi Brar Reviewed-by: Andrew Lunn --- drivers/net/ethernet/Kconfig |1 + drivers/net/ethernet/Makefile|1 + drivers/net/ethernet/socionext/Kconfig | 22 + drivers/net/ethernet/socionext/Makefile |5 + drivers/net/ethernet/socionext/sni_ave.c | 1744 ++ 5 files changed, 1773 insertions(+) create mode 100644 drivers/net/ethernet/socionext/Kconfig create mode 100644 drivers/net/ethernet/socionext/Makefile create mode 100644 drivers/net/ethernet/socionext/sni_ave.c diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index c604213..d50519e 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -170,6 +170,7 @@ source "drivers/net/ethernet/sis/Kconfig" source "drivers/net/ethernet/sfc/Kconfig" source "drivers/net/ethernet/sgi/Kconfig" source "drivers/net/ethernet/smsc/Kconfig" +source "drivers/net/ethernet/socionext/Kconfig" source "drivers/net/ethernet/stmicro/Kconfig" source "drivers/net/ethernet/sun/Kconfig" source "drivers/net/ethernet/tehuti/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 39f62733..6cf5ade 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_SFC) += sfc/ obj-$(CONFIG_SFC_FALCON) += sfc/falcon/ obj-$(CONFIG_NET_VENDOR_SGI) += sgi/ obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/ +obj-$(CONFIG_NET_VENDOR_SOCIONEXT) += socionext/ obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/ obj-$(CONFIG_NET_VENDOR_SUN) += sun/ obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/ diff --git a/drivers/net/ethernet/socionext/Kconfig b/drivers/net/ethernet/socionext/Kconfig new file mode 100644 index 000..3a1829e --- /dev/null +++ b/drivers/net/ethernet/socionext/Kconfig @@ -0,0 +1,22 @@ +config NET_VENDOR_SOCIONEXT + bool "Socionext ethernet drivers" + default y + ---help--- + Option to select ethernet drivers for Socionext platforms. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Socionext devices. If you say Y, you will be asked + for your specific card in the following questions. + +if NET_VENDOR_SOCIONEXT + +config SNI_AVE + tristate "Socionext AVE ethernet support" + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + select PHYLIB + ---help--- + Driver for gigabit ethernet MACs, called AVE, in the + Socionext UniPhier family. + +endif #NET_VENDOR_SOCIONEXT diff --git a/drivers/net/ethernet/socionext/Makefile b/drivers/net/ethernet/socionext/Makefile new file mode 100644 index 000..ab83df6 --- /dev/null +++ b/drivers/net/ethernet/socionext/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for all ethernet ip drivers on Socionext platforms +# +obj-$(CONFIG_SNI_AVE) += sni_ave.o diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c new file mode 100644 index 000..7b293c2 --- /dev/null +++ b/drivers/net/ethernet/socionext/sni_ave.c @@ -0,0 +1,1744 @@ +/** + * sni_ave.c - Socionext UniPhier AVE ethernet driver + * + * Copyright 2014 Panasonic Corporation + * Copyright 2015-2017 Socionext Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* General Register Group */ +#define AVE_IDR0x000 /* ID */ +#define AVE_VR 0x004 /* Version */ +#define AVE_GRR0x008 /* Global Reset */ +#define AVE_CFGR 0x00c /* Configuration */ + +/* Interrupt Register Group */ +#define AVE_GIMR 0x100 /* Global Interrupt Mask */ +#define AVE_GISR 0x104 /* Global Interrupt Status */ + +/* MAC Register Group */ +#define AVE_TXCR 0x200 /* TX Setup */ +#define AVE_RXCR 0x204 /* RX Setup */ +#define AVE_RXMAC1R0x208 /* MAC address (lower) */ +#define AVE_RXMAC2R0x20c /* MAC address (upper) */ +#define AVE_MDIOCTR0x214 /* MDIO Control */ +#define AVE_MDIOAR
Re: [PATCH v1 4/4] arm64: dts: mediatek: add mt2712 cpufreq related device nodes
On 08-12-17, 14:07, Andrew-sh Cheng wrote: > Add opp v2 information, > and also add clocks, regulators and opp information into cpu nodes > > Signed-off-by: Andrew-sh Cheng > --- > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 ++ > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 57 > + > 2 files changed, 84 insertions(+) Acked-by: Viresh Kumar -- viresh
[PATCH net-next v5 0/2] add UniPhier AVE ethernet support
This series adds support for Socionext AVE ethernet controller implemented
on UniPhier SoCs. This driver supports RGMII/RMII modes.
v4: https://www.spinics.net/lists/netdev/msg469294.html
The PHY patch included in v1 has already separated in:
http://www.spinics.net/lists/netdev/msg454595.html
Changes since v4:
- fix larger integer warning on AVE_PFMBYTE_MASK0
Changes since v3:
- remove checking dma address and use dma_set_mask() to restirct address
- replace ave_mdio_busywait() with read_poll_timeout()
- replace functions to access to registers with readl/writel() directly
- replace a function to access to macaddr with ave_hw_write_macaddr()
- change return value of ave_dma_map() to error value
- move mdiobus_unregister() from ave_remove() to ave_uninit()
- eliminate else block at the end of ave_dma_map()
- add mask definitions for packet filter
- sort bitmap definitions in descending order
- add error check to some functions
- rename and sort functions to clear sub-categories
- fix error value consistency
- remove unneeded initializers
- change type of constant arrays
Changes since v2:
- replace clk_get() with devm_clk_get()
- replace reset_control_get() with devm_reset_control_get_optional_shared()
- add error return when the error occurs on the above *_get functions
- sort soc data and compatible strings
- remove clearly obvious comments
- modify dt-bindings document consistent with these modifications
Changes since v1:
- add/remove devicetree properties and sub-node
- remove "internal-phy-interrupt" and "desc-bits" property
- add SoC data structures based on compatible strings
- add node operation to apply "mdio" sub-node
- add support for features
- add support for {get,set}_pauseparam and pause frame operations
- add support for ndo_get_stats64 instead of ndo_get_stats
- replace with desiable functions
- replace check for valid phy_mode with phy_interface{_mode}_is_rgmii()
- replace phy attach message with phy_attached_info()
- replace 32bit operation with {upper,lower}_32_bits() on ave_wdesc_addr()
- replace nway_reset and get_link with generic functions
- move operations to proper functions
- move phy_start_aneg() to ndo_open,
and remove unnecessary PHY interrupt operations
See http://www.spinics.net/lists/netdev/msg454590.html
- move irq initialization and descriptor memory allocation to ndo_open
- move initialization of reset and clock and mdiobus to ndo_init
- fix skbuffer operations
- fix skb alignment operations and add Rx buffer adjustment for descriptor
See http://www.spinics.net/lists/netdev/msg456014.html
- add error returns when dma_map_single() failed
- clean up code structures
- clean up wait-loop and wake-queue conditions
- add ave_wdesc_addr() and offset definitions
- add ave_macaddr_init() to clean up mac-address operation
- fix checking whether Tx entry is not enough
- fix supported features of phydev
- add necessary free/disable operations
- add phydev check on ave_{get,set}_wol()
- remove netif_carrier functions, phydev initializer, and Tx budget check
- change obsolate codes
- replace ndev->{base_addr,irq} with the members of ave_private
- rename goto labels and mask definitions, and remove unused codes
Kunihiko Hayashi (2):
dt-bindings: net: add DT bindings for Socionext UniPhier AVE
net: ethernet: socionext: add AVE ethernet driver
.../bindings/net/socionext,uniphier-ave4.txt | 48 +
drivers/net/ethernet/Kconfig |1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/socionext/Kconfig | 22 +
drivers/net/ethernet/socionext/Makefile|5 +
drivers/net/ethernet/socionext/sni_ave.c | 1744
6 files changed, 1821 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
create mode 100644 drivers/net/ethernet/socionext/Kconfig
create mode 100644 drivers/net/ethernet/socionext/Makefile
create mode 100644 drivers/net/ethernet/socionext/sni_ave.c
--
2.7.4
[PATCH net-next v5 1/2] dt-bindings: net: add DT bindings for Socionext UniPhier AVE
DT bindings for the AVE ethernet controller found on Socionext's
UniPhier platforms.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Acked-by: Rob Herring
---
.../bindings/net/socionext,uniphier-ave4.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
new file mode 100644
index 000..4700377
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
@@ -0,0 +1,48 @@
+* Socionext AVE ethernet controller
+
+This describes the devicetree bindings for AVE ethernet controller
+implemented on Socionext UniPhier SoCs.
+
+Required properties:
+ - compatible: Should be
+ - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
+ - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
+ - "socionext,uniphier-ld11-ave4" : for LD11 SoC
+ - "socionext,uniphier-ld20-ave4" : for LD20 SoC
+ - reg: Address where registers are mapped and size of region.
+ - interrupts: Should contain the MAC interrupt.
+ - phy-mode: See ethernet.txt in the same directory. Allow to choose
+ "rgmii", "rmii", or "mii" according to the PHY.
+ - phy-handle: Should point to the external phy device.
+ See ethernet.txt file in the same directory.
+ - clocks: A phandle to the clock for the MAC.
+
+Optional properties:
+ - resets: A phandle to the reset control for the MAC
+ - local-mac-address: See ethernet.txt in the same directory.
+
+Required subnode:
+ - mdio: Device tree subnode with the following required properties:
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+ - reg: phy ID number, usually a small integer.
+
+Example:
+
+ ether: ethernet@6500 {
+ compatible = "socionext,uniphier-ld20-ave4";
+ reg = <0x6500 0x8500>;
+ interrupts = <0 66 4>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ local-mac-address = [00 00 00 00 00 00];
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+ };
+ };
--
2.7.4
Re: [PATCH v1 3/4] arm64: dts: mediatek: add mt8173 cpufreq related device nodes
On 08-12-17, 14:07, Andrew-sh Cheng wrote: > Add opp v2 information, > and also add clocks, regulators and opp information into cpu nodes > > Signed-off-by: Andrew-sh Cheng > --- > arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++ > arch/arm64/boot/dts/mediatek/mt8173.dtsi| 90 > + > 2 files changed, 108 insertions(+) Acked-by: Viresh Kumar -- viresh
Re: [PATCH 02/20] dt-bindings: gpio: Add ASPEED constants
On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley wrote: > These are used to by the device tree to map pin numbers to constants > required by the GPIO bindings. > + > +#define ASPEED_GPIO_PORT_A 0 > +#define ASPEED_GPIO_PORT_B 1 > +#define ASPEED_GPIO_PORT_C 2 > +#define ASPEED_GPIO_PORT_D 3 > +#define ASPEED_GPIO_PORT_E 4 > +#define ASPEED_GPIO_PORT_F 5 > +#define ASPEED_GPIO_PORT_G 6 > +#define ASPEED_GPIO_PORT_H 7 > +#define ASPEED_GPIO_PORT_I 8 > +#define ASPEED_GPIO_PORT_J 9 > +#define ASPEED_GPIO_PORT_K 10 > +#define ASPEED_GPIO_PORT_L 11 > +#define ASPEED_GPIO_PORT_M 12 > +#define ASPEED_GPIO_PORT_N 13 > +#define ASPEED_GPIO_PORT_O 14 > +#define ASPEED_GPIO_PORT_P 15 > +#define ASPEED_GPIO_PORT_Q 16 > +#define ASPEED_GPIO_PORT_R 17 > +#define ASPEED_GPIO_PORT_S 18 > +#define ASPEED_GPIO_PORT_T 19 > +#define ASPEED_GPIO_PORT_U 20 > +#define ASPEED_GPIO_PORT_V 21 > +#define ASPEED_GPIO_PORT_W 22 > +#define ASPEED_GPIO_PORT_X 23 > +#define ASPEED_GPIO_PORT_Y 24 > +#define ASPEED_GPIO_PORT_Z 25 > +#define ASPEED_GPIO_PORT_AA 26 > +#define ASPEED_GPIO_PORT_AB 27 > +#define ASPEED_GPIO_PORT_AC 28 This looks like a 1:1 mapping, wouldn't it be easier to just describe it in the binding document? Arnd
Re: [PATCH v1 2/4] cpufreq: mediatek: Add mediatek related projects into blacklist
On 08-12-17, 14:07, Andrew-sh Cheng wrote:
> mediatek projects will use mediate-cpufreq.c as cpufreq driver,
> instead of using cpufreq_dt.c
> Add mediatek related projects into cpufreq-dt blacklist
>
> Signed-off-by: Andrew-sh Cheng
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> b/drivers/cpufreq/cpufreq-dt-platdev.c
> index ecc56e2..3b585e4 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -108,6 +108,14 @@ static const struct of_device_id blacklist[] __initconst
> = {
>
> { .compatible = "marvell,armadaxp", },
>
> + { .compatible = "mediatek,mt2701", },
> + { .compatible = "mediatek,mt2712", },
> + { .compatible = "mediatek,mt7622", },
> + { .compatible = "mediatek,mt7623", },
> + { .compatible = "mediatek,mt817x", },
> + { .compatible = "mediatek,mt8173", },
> + { .compatible = "mediatek,mt8176", },
> +
> { .compatible = "nvidia,tegra124", },
>
> { .compatible = "st,stih407", },
Acked-by: Viresh Kumar
--
viresh
Re: [PATCH v1 1/4] cpufreq: mediatek: add mt2712 into compatible list
On 08-12-17, 14:07, Andrew-sh Cheng wrote:
> Support mt2712 in mediatek-cpufreq.c
>
> Signed-off-by: Andrew-sh Cheng
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> b/drivers/cpufreq/mediatek-cpufreq.c
> index 18c4bd9..62aec5c 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -574,6 +574,7 @@ static struct platform_driver mtk_cpufreq_platdrv = {
> /* List of machines supported by this driver */
> static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
> { .compatible = "mediatek,mt2701", },
> + { .compatible = "mediatek,mt2712", },
> { .compatible = "mediatek,mt7622", },
> { .compatible = "mediatek,mt7623", },
> { .compatible = "mediatek,mt817x", },
Acked-by: Viresh Kumar
--
viresh
Re: [PATCH 01/20] dt-bindings: clock: Add ASPEED constants
On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley wrote: > +#define ASPEED_NUM_CLKS35 Why is this part of the ABI? What if they ever come out with a new chip that needs one more clock and you can't change it? Arnd
[PATCH 4/4] arm: dts: sun8i: a83t: Set timer node to use phy timer
By default, virtual timers are used. These timers need an offset
that must be set by firmware, for example. In case of SMP support,
after a reset, this offset is in "unknown" state and produced
a hang of the kernel.
Use "arm,cpu-registers-not-fw-configured" property allows to use
physical timers instead of virtual ones.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 3e2aad537972..0fe4b9e5dee1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -121,6 +121,7 @@
,
,
;
+ arm,cpu-registers-not-fw-configured;
};
clocks {
--
2.11.0
[PATCH 2/4] arm: dts: sun8i: a83t: Add registers needed for MCPM
Add 3 registers needed for MCPM (ie SMP): prcm, cpucfg and r_cpucfg.
prcm and cpucfg are identical with sun9i-a80. The only difference
is the r_cpucfg that does not exist on sun9i.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a384b766f3dc..eeb2e7d0d6dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -323,6 +323,16 @@
#reset-cells = <1>;
};
+ cpucfg@0170 {
+ compatible = "allwinner,sun9i-a80-cpucfg";
+ reg = <0x0170 0x100>;
+ };
+
+ r_cpucfg@1f01c00 {
+ compatible = "allwinner,sun8i-a83t-r-cpucfg";
+ reg = <0x1f01c00 0x100>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
@@ -493,6 +503,11 @@
interrupts = ;
};
+ prcm@1f01400 {
+ compatible = "allwinner,sun9i-a80-prcm";
+ reg = <0x1f01400 0x200>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
--
2.11.0
[PATCH 3/4] arm: dts: sun8i: a83t: Add CCI-400 node
Add CCI-400 node and control-port on CPUs needed by MCPM (ie SMP).
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index eeb2e7d0d6dc..3e2aad537972 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -62,48 +62,56 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
+ cci-control-port = <&cci_control0>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
+ cci-control-port = <&cci_control0>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
+ cci-control-port = <&cci_control0>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
+ cci-control-port = <&cci_control0>;
};
cpu@100 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0x100>;
+ cci-control-port = <&cci_control1>;
};
cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0x101>;
+ cci-control-port = <&cci_control1>;
};
cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0x102>;
+ cci-control-port = <&cci_control1>;
};
cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0x103>;
+ cci-control-port = <&cci_control1>;
};
};
@@ -314,6 +322,39 @@
status = "disabled";
};
+ cci: cci@179 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0179 0x1000>;
+ ranges = <0x0 0x0179 0x1>;
+
+ cci_control0: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ };
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c2 0x400>;
--
2.11.0
[PATCH 1/4] ARM: sunxi: mcpm: Add support for A83T
Add the support for A83T.
A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-sunxi/Kconfig | 1 +
arch/arm/mach-sunxi/mcpm.c | 90 ++---
2 files changed, 86 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 177380548d99..ae7b57fbd7ac 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -42,6 +42,7 @@ config MACH_SUN8I
default ARCH_SUNXI
select ARM_GIC
select MFD_SUN6I_PRCM
+ imply MCPM
config MACH_SUN9I
bool "Allwinner (sun9i) SoCs support"
diff --git a/arch/arm/mach-sunxi/mcpm.c b/arch/arm/mach-sunxi/mcpm.c
index 4b6e1d6ae379..fc8a28dcb576 100644
--- a/arch/arm/mach-sunxi/mcpm.c
+++ b/arch/arm/mach-sunxi/mcpm.c
@@ -43,17 +43,25 @@
#define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
#define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
#define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
#define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
#define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
#define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
#define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+/* The power off register for clusters are different from SUN9I and SUN8I */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4)
#define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
#define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
#define PRCM_CPU_SOFT_ENTRY_REG0x164
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
static void __iomem *cpucfg_base;
+static void __iomem *r_cpucfg_base;
static void __iomem *prcm_base;
static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
@@ -101,6 +109,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+ if (r_cpucfg_base) {
+ /* assert cpu power-on reset */
+ reg = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+ reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+ writel(reg, r_cpucfg_base +
+ R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+ udelay(10);
+ }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!(of_machine_is_compatible("allwinner,sun9i-a80") &&
cluster == SUN9I_A80_A15_CLUSTER)) {
@@ -126,17 +144,37 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
+ /* Handle A83T bit swap */
+ if (of_machine_is_compatible("allwinner,sun8i-a83t")) {
+ if (cpu == 0)
+ cpu = 4;
+ }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
+ if (of_machine_is_compatible("allwinner,sun8i-a83t")) {
+ if (cpu == 4)
+ cpu = 0;
+ }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+ if (r_cpucfg_base) {
+ reg = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+ reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+ writel(reg, r_cpucfg_base +
+ R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+ udelay(10);
+ }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -160,6 +198,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;
+ /* For A83T, assert cluster cores resets */
+ if (of_machine_is_compatible("allwinner,sun8i-a83t")) {
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset*/
+
[PATCH 0/4] Sunxi: Add SMP support on A83T
Hello everyone, This series adds SMP support for Allwinner Sun8i-a83t with MCPM (Multi-Cluster Power Management). Series information: - Based on last linux-next (next-20171211) - Had dependencies on Chen Yu's patch that add MCPM support: https://patchwork.kernel.org/patch/6402801/ Patch 01: Convert the mcpm driver (initially for A80) to be able to use it for A83T. This SoC has a bit flip that needs to be handled. Patch 02: Add registers nodes (prcm, cpucfg and r_cpucfg) needed for MCPM. Patch 03: Add CCI-400 node for a83t. Patch 04: Fix the use of virtual timers that hangs the kernel in case of SMP support. If you have any remarks/questions, let me know. Thank you in advance, Mylène Mylène Josserand (4): ARM: sunxi: mcpm: Add support for A83T arm: dts: sun8i: a83t: Add registers needed for MCPM arm: dts: sun8i: a83t: Add CCI-400 node arm: dts: sun8i: a83t: Set timer node to use phy timer arch/arm/boot/dts/sun8i-a83t.dtsi | 57 + arch/arm/mach-sunxi/Kconfig | 1 + arch/arm/mach-sunxi/mcpm.c| 90 --- 3 files changed, 143 insertions(+), 5 deletions(-) -- 2.11.0
Re: [PATCH 1/1] futex: futex_wake_op, fix sign_extend32 sign bits
On 12/10/2017, 09:50 PM, Linus Torvalds wrote: > On Thu, Nov 30, 2017 at 6:35 AM, Jiri Slaby wrote: >> sign_extend32 counts the sign bit parameter from 0, not from 1. So we >> have to use "11" for 12th bit, not "12". > > This interface is crap. It really doesn't make much sense. I wonder > how many people have gotten this wrong, but it's hard to tell. I tend to agree, because it really surprised me. So at that time I searched for most (all?) uses of the interface, checked them and all of them *seem* to be fine. > I'm applying this directly to my tree since I didn't see anybody else > react to it, but the whole pattern worries me. > > Also, clearly nobody actually uses the odder corners of futex ops > anyway. Maybe we should deprecate them entirely? > > Jiri, did you notice by testing, or what? I noticed it by coincidence while fixing the strace build test failures -- e78c38f6bdd9 (futex: futex_wake_op, do not fail on invalid op). I compiled a bit modified futex_atomic_op_inuser in userspace to test the conversion and the added check and it did not work. And yes, somebody (tglx?) noted already that this interface is old and perhaps unused. thanks, -- js suse labs
Re: [PATCH v2] usb: host: Implement workaround for Erratum A-009611
On Mon, Dec 11, 2017 at 03:15:37AM +, Yinbo Zhu wrote: > > > -Original Message- > From: Felipe Balbi [mailto:felipe.ba...@linux.intel.com] > Sent: Friday, December 08, 2017 6:44 PM > To: Greg Kroah-Hartman ; Yinbo Zhu > > Cc: Mathias Nyman ; open list:DESIGNWARE USB3 DRD IP > DRIVER ; open list:DESIGNWARE USB3 DRD IP DRIVER > ; open list ; > Xiaobo Xie ; Jerry Huang ; Ran Wang > > Subject: Re: [PATCH v2] usb: host: Implement workaround for Erratum A-009611 > > > >Hi, > > >Greg Kroah-Hartman writes: > > On Fri, Dec 08, 2017 at 05:49:41PM +0800, yinbo@nxp.com wrote: > >> From: "yinbo.zhu" > >> > >> Description: This is a occasional problem where the software > > > > No need for a "Description:" word. That's just assumed here, right? > > I will remove "Description:" thanks. > >> issues an End Transfer command while a USB transfer is in progress, > >> resulting in the TxFIFO being flushed when the lower layer is > >> waiting for data,causing the super speed (SS) transmit to get blocked. > >> If the End Transfer command is issued on an IN endpoint to flush out > >> the pending transfers when the same IN endpoint is doing transfers on > >> the USB, then depending upon the timing of the End Transfer (and the > >> resulting internal FIFO flush),the lower layer (U3PTL/U3MAC) could > >> get stuck waiting for data indefinitely. This blocks the transmission > >> path on the SS, and no DP/ACK/ERDY/DEVNOTIF packets can be sent from > >> the device. > >> Impact: If this issue happens and the transmission gets blocked, then > >> the USB host aborts and resets/re-enumerates the device. > >> This unblocks the transmitt engine and the device functions normally. > >> > >> Workaround: Software must wait for all existing TRBs to complete > >> before issuing End transfer command. > >> > >> Configs Affected: > >> LS1088-48A-R1.0, LS2081A-R1.1, LS2088-48A-R1.0, LS2088-48A-R1.1, > >> LX2160-2120-2080A-R1. > > > > What are these Configs? That doesn't seem to match up with anything > > that is in the kernel tree that I can see. > > These configs is soc information, I don't enable it on these platform dts. > Although the erratum issue can't be reproduced. I do not understand what this means, please explain it a bit better. thanks, greg k-h
Re: [PATCH v2] usb: host: Implement workaround for Erratum A-007463
On Mon, Dec 11, 2017 at 02:26:02AM +, Yinbo Zhu wrote: > > > -Original Message- > From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org] > Sent: Friday, December 08, 2017 6:18 PM > To: Yinbo Zhu > Cc: Felipe Balbi ; Mathias Nyman ; > open list:DESIGNWARE USB3 DRD IP DRIVER ; open > list:DESIGNWARE USB3 DRD IP DRIVER ; open list > ; Xiaobo Xie ; Jerry Huang > ; Ran Wang > Subject: Re: [PATCH v2] usb: host: Implement workaround for Erratum A-007463 > > On Fri, Dec 08, 2017 at 05:49:40PM +0800, yinbo@nxp.com wrote: > > From: "yinbo.zhu" > > >I need a "real name" here, I doubt you sign documents as: > > "yinbo.zhu" > >right? :) > > >Also, you sent 3 patches, yet no way to know what order to apply them in. > >Please fix that up by sending a >patch series, properly numbered. > > >thanks, > > >greg k-h > > Hi Greg Kroah-Hartman, > > "Yinbo.zhu" is my email address prefix,and it is automatically generated > through the git command. Then this means you have not correctly configured git, please fix that :) > You can follow the order of patch A-007463 A-009611 A-009668 to apply it. That's not how we number patches in the kernel, please do so in the normal way. See the mailing lists for lots of examples. The kernel documentation also describes the correct format for this. thanks, greg k-h
Re: [PATCH] mm: Release a semaphore in 'get_vaddr_frames()'
Le 10/12/2017 à 10:45, Michal Hocko a écrit :
On Sat 09-12-17 08:09:41, Christophe JAILLET wrote:
A semaphore is acquired before this check, so we must release it before
leaving.
Fixes: b7f0554a56f2 ("mm: fail get_vaddr_frames() for filesystem-dax mappings")
Signed-off-by: Christophe JAILLET
---
-- Untested --
The wording of the commit entry and log description could be improved
but I didn't find something better.
The changelog is ok imo.
---
mm/frame_vector.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/mm/frame_vector.c b/mm/frame_vector.c
index 297c7238f7d4..e0c5e659fa82 100644
--- a/mm/frame_vector.c
+++ b/mm/frame_vector.c
@@ -62,8 +62,10 @@ int get_vaddr_frames(unsigned long start, unsigned int
nr_frames,
* get_user_pages_longterm() and disallow it for filesystem-dax
* mappings.
*/
- if (vma_is_fsdax(vma))
+ if (vma_is_fsdax(vma)) {
+ up_read(&mm->mmap_sem);
return -EOPNOTSUPP;
+ }
Is there any reason to do a different error handling than other error
paths? Namely not going without goto out?
You are right, I misread the code after out:.
I thought it would override the returned value, but I was wrong.
'goto out' is definitively better, IMHO. I'll propose a v2.
CJ
[PATCH] e1000e: Fix e1000_check_for_copper_link_ich8lan return value.
e1000e_check_for_copper_link() and e1000_check_for_copper_link_ich8lan()
are the two functions that may be assigned to mac.ops.check_for_link when
phy.media_type == e1000_media_type_copper. Commit 19110cfbb34d ("e1000e:
Separate signaling for link check/link up") changed the meaning of the
return value of check_for_link for copper media but only adjusted the first
function. This patch adjusts the second function likewise.
Reported-by: Christian Hesse
Reported-by: Gabriel C
Link: https://bugzilla.kernel.org/show_bug.cgi?id=198047
Fixes: 19110cfbb34d ("e1000e: Separate signaling for link check/link up")
Tested-by: Christian Hesse
Signed-off-by: Benjamin Poirier
---
drivers/net/ethernet/intel/e1000e/ich8lan.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c
b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index d6d4ed7acf03..31277d3bb7dc 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1367,6 +1367,9 @@ static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw,
bool force)
* Checks to see of the link status of the hardware has changed. If a
* change in link status has been detected, then we read the PHY registers
* to get the current speed/duplex if link exists.
+ *
+ * Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link
+ * up).
**/
static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
{
@@ -1382,7 +1385,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct
e1000_hw *hw)
* Change or Rx Sequence Error interrupt.
*/
if (!mac->get_link_status)
- return 0;
+ return 1;
/* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
@@ -1613,10 +1616,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct
e1000_hw *hw)
* different link partner.
*/
ret_val = e1000e_config_fc_after_link_up(hw);
- if (ret_val)
+ if (ret_val) {
e_dbg("Error configuring flow control\n");
+ return ret_val;
+ }
- return ret_val;
+ return 1;
}
static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
--
2.15.1
Crypto Fixes for 4.15
Hi Linus: This push fixes the following issues: - Buffer overread in RSA. - Potential use after free in algif_aead. - Error path null pointer dereference in af_alg. - Forbid combinations such as hmac(hmac(sha3)) which may crash. - Crash in salsa20 due to incorrect API usage. Please pull from git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git linus Eric Biggers (5): crypto: rsa - fix buffer overread when stripping leading zeroes crypto: algif_aead - fix reference counting of null skcipher crypto: af_alg - fix NULL pointer dereference in crypto: hmac - require that the underlying hash algorithm is unkeyed crypto: salsa20 - fix blkcipher_walk API usage arch/x86/crypto/salsa20_glue.c |7 --- crypto/af_alg.c| 13 +++-- crypto/algif_aead.c|2 +- crypto/hmac.c |6 +- crypto/rsa_helper.c|2 +- crypto/salsa20_generic.c |7 --- crypto/shash.c |5 +++-- include/crypto/internal/hash.h |8 8 files changed, 25 insertions(+), 25 deletions(-) Thanks, -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH 3/5] arm: dts: sun8i: a83t: a711: Enable I2C0
Hi,
On Fri, Dec 08, 2017 at 10:54:17PM +0100, Mylène Josserand wrote:
> The A711 has a touchscreen connected by I2C0.
> Enable only I2C0 node for the moment.
>
> Signed-off-by: Mylène Josserand
> ---
> arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> index a021ee6da396..84cca1a48cea 100644
> --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> @@ -105,6 +105,13 @@
> status = "okay";
> };
>
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
If there's only one set of pins, maybe we should force that muxing in
the DTSI?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 5/5] arm: dts: sun8i: a83t: a711: Add touchscreen node
Hi,
On Fri, Dec 08, 2017 at 10:54:19PM +0100, Mylène Josserand wrote:
> Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
> It is connected via I2C0 so add his node in i2c0's node.
>
> The reset line is PD5, the interrupt line is PL7 and the power
> supply is the ldo_io0 regulator.
>
> Signed-off-by: Mylène Josserand
> ---
> arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> index 84cca1a48cea..738359917a34 100644
> --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
> @@ -110,6 +110,17 @@
> pinctrl-0 = <&i2c0_pins>;
> clock-frequency = <40>;
> status = "okay";
> +
> + polytouch: edt-ft5x06@38 {
You're not using that label anywhere, so you can drop it, and the node
name must be the class of the device.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 1/5] arm: dts: sun8i: a83t: Add I2C0 node
Hi,
On Fri, Dec 08, 2017 at 10:54:15PM +0100, Mylène Josserand wrote:
> Add I2C0 node for A83T.
>
> Signed-off-by: Mylène Josserand
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
> b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 19acae1b4089..848cf3f19962 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -177,6 +177,17 @@
> #dma-cells = <1>;
> };
>
> + i2c0: i2c@01c2ac00 {
Drop the leading 0, it generates a warning in dtc.
> + compatible = "allwinner,sun6i-a31-i2c";
Can you add a SoC-specific compatible there please?
> + reg = <0x01c2ac00 0x400>;
And you should order your nodes by physical address.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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RE: [PATCH v2 1/5] dt-bindings: rtc: add bindings for i.MX53 SRTC
>From: Rob Herring [mailto:r...@kernel.org]
>Sent: Mittwoch, 6. Dezember 2017 22:55
>On Tue, Dec 05, 2017 at 03:06:42PM +0100, linux-kernel-...@beckhoff.com
>wrote:
>> From: Patrick Bruenn
>>
>> +++ b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
>> @@ -0,0 +1,17 @@
>> +* i.MX53 Real Time Clock controller
>> +
>> +Required properties:
>> +- compatible: should be: "fsl,imx53-rtc"
>> +- reg: physical base address of the controller and length of memory
>mapped
>> + region.
>> +- clocks: should contain the phandle for the rtc clock
>
>Shouldn't there be more than 1 here. From what I remember, the ipg clock
>and the 32k clock?
Yes, you are right. But if I am reading the original Freescale driver and the
reference manual correctly, the second clock is always active.
Section "72.3.1.1 Clocks" from the reference manual [1] reads:
"SRTC runs on two clock sources, high frequency peripherals clock and low
frequency
timers clock. The high frequency peripheral IP clock is used by the SRTC
peripheral bus
interface, control and status registers. The low frequency 32.768 kHz clock is
the
always-active clock used by the SRTC timers..."
That's why I would only include one clock . Should I change this?
>
>> +- interrupts: rtc alarm interrupt
>> +
>> +Example:
>> +
>> +srtc@53fa4000 {
>
>rtc@...
>
The rtc for which this series adds support is embedded within a function block
called
"Secure Real Time Clock". This driver doesn't utilize all of the hardware
features by
now. But maybe someone else wants to extend the functionalities, later.
For that possibility I wanted to name the node "srtc". Should I still change
this?
I believe you have a much better understanding of what should be done here. I
don't
want to argue with you, just thought you might not had that information. So if
I am
wrong just tell me and I will change it without further "complaining".
Thank you for taking the time,
Patrick
[1] https://cache.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf
---
Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans Beckhoff
Registered office: Verl, Germany | Register court: Guetersloh HRA 7075
Re: [PATCH 1/4] fs/notify: fdinfo can report unsupported file handles.
On Mon, Dec 11, 2017 at 8:41 AM, Amir Goldstein wrote: > On Mon, Dec 11, 2017 at 8:04 AM, NeilBrown wrote: >> If a filesystem does not set sb->s_export_op, then it >> does not support filehandles and export_fs_encode_fh() >> and exportfs_encode_inode_fh() should not be called. >> They will use export_encode_fh() is which is a default >> that uses inode number generation number, but in general >> they may not be stable. >> >> So change exportfs_encode_inode_fh() to return FILEID_INVALID >> if called on an unsupported Filesystem. Currently only >> notify/fdinfo can do that. >> > > I wish you would leave this check to the caller, maybe add a helper > exportfs_can_decode_fh() for callers to use. > > Although there are no current uses for it in-tree, there is value in > being able to encode a unique file handle even when it cannot be > decoded back to an open file. > > I am using this property in my fanotify super block watch patches, > where the object identifier on the event is an encoded file handle > of the object, which delegates tracking filesystem objects to > userspace and prevents fanotify from keeping elevated refcounts > on inodes and dentries. > > There are quite a few userspace tools out there that are checking > that st_ino hasn't changed on a file between non atomic operations. > Those tools (or others) could benefit from a unique file handle if > we ever decide to provide a relaxed version of name_to_handle_at(). > And this change need a clause about not breaking userspace. Pavel, Will this break any version of criu in the wild? Amir.
Re: [PATCH v4 0/4] Teach phylib hard-resetting devices
On Mon, Dec 04, 2017 at 11:34:48AM +0100, Geert Uytterhoeven wrote: > Hi David, Andrew, Florian, Simon, Magnus, > > This patch series adds optional PHY reset support to phylib. > > The first two patches are destined for David's net-next tree. They add > core PHY reset code, and update a driver that currently uses its own > reset code. > > The last two patches are destined for Simon's renesas tree. They add > properties to describe the EthernetAVB PHY reset topology to the common > Salvator-X/XS and ULCB DTS files, which solves two issues: > 1. On Salvator-XS, the enable pin of the regulator providing PHY power > is connected to PRESETn, and PSCI powers down the SoC during system > suspend. Hence a PHY reset is needed to restore network > functionality after system resume. > 2. Linux should not rely on the boot loader having reset the PHY, but > should reset the PHY during driver probe. Thanks, I have applied patches 3/4 and 4/4 for v4.16.
Re: [PATCH PTI v2 0/6] Clean up pgd handling and fix VSYSCALL and LDT
On Sun, Dec 10, 2017 at 10:47 PM, Andy Lutomirski wrote:
> I'm getting reasonably happy with this. It still needs more testing,
> but I want to get it out there.
>
> The main things that need testing are the 5-level case for the both
> vsyscalls and the LDT. I'm getting a double-fault in ldt_gdt_64,
> but I haven't checked whether it's a bug in this series, and it
> kind of looks like it isn't. I'll figure it out in the morning.
> The docs also want updating for the 5 level case.
>
The actual failure looks a lot like the ESPFIX stacks aren't mapped in
the usermode tables, which reinforces my old belief that this bit of
code is bogus:
/*
* Just copy the top-level PGD that is mapping the espfix area to
* ensure it is mapped into the user page tables.
*
* For 5-level paging, the espfix pgd was populated when
* pti_init() pre-populated all the pgd entries. The above
* p4d_alloc() would never do anything and the p4d_populate() would
* be done to a p4d already mapped in the userspace pgd.
*/
#ifdef CONFIG_PAGE_TABLE_ISOLATION
if (CONFIG_PGTABLE_LEVELS <= 4) {
set_pgd(kernel_to_user_pgdp(pgd),
__pgd(_KERNPG_TABLE | (p4d_pfn(*p4d) << PAGE_SHIFT)));
}
#endif
Of course, the comment is even more wrong with this series applied,
but I think it's been wrong all along.
I'll fix it in the morning if no one beats me to it.
(Hint: this can be tested in QEMU with -machine accel=tcg -cpu qemu64,+la57)
> Changes from v1:
> - vsyscalls actually work.
> - Added the "Warn and fail" patch to prevent the testing goof I had on v1.
> - Lots of cleanups
>
> Andy Lutomirski (6):
> x86/pti: Vastly simplify pgd synchronization
> Revert "x86/mm/pti: Disable native VSYSCALL"
> x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy
> x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode
> x86/pti: Map the vsyscall page if needed
> x86/pti: Put the LDT in its own PGD if PTI is on
>
> Documentation/x86/x86_64/mm.txt | 11 ++-
> arch/x86/Kconfig| 8 --
> arch/x86/entry/vsyscall/vsyscall_64.c | 37 -
> arch/x86/include/asm/mmu_context.h | 33 +++-
> arch/x86/include/asm/pgtable.h | 6 +-
> arch/x86/include/asm/pgtable_64.h | 77 --
> arch/x86/include/asm/pgtable_64_types.h | 2 +
> arch/x86/include/asm/processor.h| 23 --
> arch/x86/include/asm/vsyscall.h | 1 +
> arch/x86/kernel/ldt.c | 138
> +---
> arch/x86/mm/pti.c | 115 --
> 11 files changed, 331 insertions(+), 120 deletions(-)
>
> --
> 2.13.6
>
[PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Also move the clock info to the board.dts instead in the soc.dtsi.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..718bbebff107 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
&uart_AO {
status = "okay";
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6fe5ee0c144e..f5b496bfd4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
/ {
compatible = "amlogic,meson-axg";
@@ -200,8 +201,6 @@
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = ;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
@@ -209,8 +208,6 @@
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = ;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
--
2.15.1
[PATCH v6 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Qiufang Dai
Try to add Hiubus DT info, and also enable clock DT info
for the Amlogic's Meson-AXG SoC.
Acked-by: Rob Herring
Signed-off-by: Qiufang Dai
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b932a784b02a..6fe5ee0c144e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -148,6 +148,20 @@
#address-cells = <0>;
};
+ hiubus: bus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x1c00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,axg-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x320>;
+ };
+ };
+
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu",
"amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
--
2.15.1
[PATCH v6 3/6] clk: meson-axg: add clock controller drivers
From: Qiufang Dai
Add clock controller drivers for Amlogic Meson-AXG SoC.
Acked-by: Neil Armstrong
Signed-off-by: Qiufang Dai
Signed-off-by: Yixun Lan
---
arch/arm64/Kconfig.platforms | 1 +
drivers/clk/meson/Kconfig| 8 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/axg.c | 944 +++
drivers/clk/meson/axg.h | 126 ++
5 files changed, 1080 insertions(+)
create mode 100644 drivers/clk/meson/axg.c
create mode 100644 drivers/clk/meson/axg.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2401373565ff..fbedbd8f619a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -105,6 +105,7 @@ config ARCH_MESON
select PINCTRL_MESON
select COMMON_CLK_AMLOGIC
select COMMON_CLK_GXBB
+ select COMMON_CLK_AXG
select MESON_IRQ_GPIO
help
This enables support for the Amlogic S905 SoCs.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d2d0174a6eca..7694302c70a4 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
help
Support for the clock controller on AmLogic S905 devices, aka gxbb.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_AXG
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ help
+ Support for the clock controller on AmLogic A113D devices, aka axg.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index b139d41b25da..3c03ce583798 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o
gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
new file mode 100644
index ..cba75409f929
--- /dev/null
+++ b/drivers/clk/meson/axg.c
@@ -0,0 +1,944 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Qiufang Dai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "axg.h"
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static const struct pll_rate_table sys_pll_rate_table[] = {
+ PLL_RATE(2400, 56, 1, 2),
+ PLL_RATE(4800, 64, 1, 2),
+ PLL_RATE(7200, 72, 1, 2),
+ PLL_RATE(9600, 64, 1, 2),
+ PLL_RATE(12000, 80, 1, 2),
+ PLL_RATE(14400, 96, 1, 2),
+ PLL_RATE(16800, 56, 1, 1),
+ PLL_RATE(19200, 64, 1, 1),
+ PLL_RATE(21600, 72, 1, 1),
+ PLL_RATE(24000, 80, 1, 1),
+ PLL_RATE(26400, 88, 1, 1),
+ PLL_RATE(28800, 96, 1, 1),
+ PLL_RATE(31200, 52, 1, 2),
+ PLL_RATE(33600, 56, 1, 2),
+ PLL_RATE(36000, 60, 1, 2),
+ PLL_RATE(38400, 64, 1, 2),
+ PLL_RATE(40800, 68, 1, 2),
+ PLL_RATE(43200, 72, 1, 2),
+ PLL_RATE(45600, 76, 1, 2),
+ PLL_RATE(48000, 80, 1, 2),
+ PLL_RATE(50400, 84, 1, 2),
+ PLL_RATE(52800, 88, 1, 2),
+ PLL_RATE(55200, 92, 1, 2),
+ PLL_RATE(57600, 96, 1, 2),
+ PLL_RATE(6, 50, 1, 1),
+ PLL_RATE(62400, 52, 1, 1),
+ PLL_RATE(64800, 54, 1, 1),
+ PLL_RATE(67200, 56, 1, 1),
+ PLL_RATE(69600, 58, 1, 1),
+ PLL_RATE(72000, 60, 1, 1),
+ PLL_RATE(74400, 62, 1, 1),
+ PLL_RATE(76800, 64, 1, 1),
+ PLL_RATE(79200, 66, 1, 1),
+ PLL_RATE(81600, 68, 1, 1),
+ PLL_RATE(84000, 70, 1, 1),
+ PLL_RATE(86400, 72, 1, 1),
+ PLL_RATE(88800, 74, 1, 1),
+ PLL_RATE(91200, 76, 1, 1),
+ PLL_RATE(93600, 78, 1, 1),
+ PLL_RATE(96000, 80, 1, 1),
+ PLL_RATE(98400, 82, 1, 1),
+ PLL_RATE(100800, 84, 1, 1),
+ PLL_RATE(103200, 86, 1, 1),
+ PLL_RATE(105600, 88, 1, 1),
+ PLL_RATE(108000, 90, 1, 1),
+ PLL_RATE(110400, 92, 1, 1),
+ PLL_RATE(112800, 94, 1, 1),
+ PLL_RATE(115200, 96, 1, 1),
+ PLL_RATE(117600, 98, 1, 1),
+ PLL_RATE(12, 50, 1, 0),
+ PLL_RATE(122400, 51, 1, 0),
+ PLL_RATE(124800, 52, 1, 0),
+ PLL_RATE(127200, 53, 1, 0),
+ PLL_RATE(129600, 54, 1, 0),
+ PLL_RATE(132000, 55, 1, 0),
+ PLL_RATE(134400, 56, 1, 0),
+ PLL_RATE(136800, 57, 1, 0),
+ PLL_RATE(139200, 58, 1, 0),
+ PLL_RATE(1416
[PATCH v6 4/6] clk: meson: make the spinlock naming more specific
Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.
Suggested-by: Stephen Boyd
Signed-off-by: Yixun Lan
---
this patch try to address the issue which bring up by Stephen at [1]
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html
---
drivers/clk/meson/axg.c | 34 +++---
drivers/clk/meson/clkc.h| 2 +-
drivers/clk/meson/gxbb.c| 112 ++--
drivers/clk/meson/meson8b.c | 24 +-
4 files changed, 86 insertions(+), 86 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index cba75409f929..8d8758089472 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -19,7 +19,7 @@
#include "clkc.h"
#include "axg.h"
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_rate_table sys_pll_rate_table[] = {
PLL_RATE(2400, 56, 1, 2),
@@ -129,7 +129,7 @@ static struct meson_clk_pll axg_fixed_pll = {
.shift = 16,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -157,7 +157,7 @@ static struct meson_clk_pll axg_sys_pll = {
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = &meson_clk_pll_ro_ops,
@@ -291,7 +291,7 @@ static struct meson_clk_pll axg_gp0_pll = {
},
.rate_table = axg_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = &meson_clk_pll_ops,
@@ -383,7 +383,7 @@ static struct meson_clk_mpll axg_mpll0 = {
.shift = 25,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &meson_clk_mpll_ops,
@@ -413,7 +413,7 @@ static struct meson_clk_mpll axg_mpll1 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &meson_clk_mpll_ops,
@@ -443,7 +443,7 @@ static struct meson_clk_mpll axg_mpll2 = {
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &meson_clk_mpll_ops,
@@ -473,7 +473,7 @@ static struct meson_clk_mpll axg_mpll3 = {
.shift = 0,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll3",
.ops = &meson_clk_mpll_ops,
@@ -499,7 +499,7 @@ static struct clk_mux axg_mpeg_clk_sel = {
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = &clk_mux_ro_ops,
@@ -518,7 +518,7 @@ static struct clk_divider axg_mpeg_clk_div = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = &clk_divider_ops,
@@ -531,7 +531,7 @@ static struct clk_divider axg_mpeg_clk_div = {
static struct clk_gate axg_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
@@ -557,7 +557,7 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = &clk_mux_ops,
@@ -571,7 +571,7 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div",
@@ -585,7 +585,7 @@
[PATCH v6 1/6] dt-bindings: clock: add compatible variant for the Meson-AXG
Update the documentation to support clock driver for the Amlogic's Meson-AXG SoC. Acked-by: Rob Herring Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index 924040769186..e2b377ed6f91 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -5,8 +5,11 @@ controllers within the SoC. Required Properties: -- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC, - or "amlogic,gxl-clkc" for GXL and GXM SoC. +- compatible: should be: + "amlogic,gxbb-clkc" for GXBB SoC, + "amlogic,gxl-clkc" for GXL and GXM SoC, + "amlogic,axg-clkc" for AXG SoC. + - reg: physical base address of the clock controller and length of memory mapped region. -- 2.15.1
[PATCH v6 2/6] clk: meson-axg: add clocks dt-bindings required header
From: Qiufang Dai Add the required header for the clocks ID dt-bindings exported from various subsystem in the Meson-AXG SoC. Acked-by: Rob Herring Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- include/dt-bindings/clock/axg-clkc.h | 71 1 file changed, 71 insertions(+) create mode 100644 include/dt-bindings/clock/axg-clkc.h diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h new file mode 100644 index ..941ac70e7f30 --- /dev/null +++ b/include/dt-bindings/clock/axg-clkc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-AXG clock tree IDs + * + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AXG_CLKC_H +#define __AXG_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_AUDIO_LOCKER 16 +#define CLKID_MIPI_DSI_HOST17 +#define CLKID_ISA 18 +#define CLKID_PL30119 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC0 21 +#define CLKID_I2C 22 +#define CLKID_RNG0 23 +#define CLKID_UART024 +#define CLKID_MIPI_DSI_PHY 25 +#define CLKID_SPICC1 26 +#define CLKID_PCIE_A 27 +#define CLKID_PCIE_B 28 +#define CLKID_HIU_IFACE29 +#define CLKID_ASSIST_MISC 30 +#define CLKID_SD_EMMC_B31 +#define CLKID_SD_EMMC_C32 +#define CLKID_DMA 33 +#define CLKID_SPI 34 +#define CLKID_AUDIO35 +#define CLKID_ETH 36 +#define CLKID_UART137 +#define CLKID_G2D 38 +#define CLKID_USB0 39 +#define CLKID_USB1 40 +#define CLKID_RESET41 +#define CLKID_USB 42 +#define CLKID_AHB_ARB0 43 +#define CLKID_EFUSE44 +#define CLKID_BOOT_ROM 45 +#define CLKID_AHB_DATA_BUS 46 +#define CLKID_AHB_CTRL_BUS 47 +#define CLKID_USB1_DDR_BRIDGE 48 +#define CLKID_USB0_DDR_BRIDGE 49 +#define CLKID_MMC_PCLK 50 +#define CLKID_VPU_INTR 51 +#define CLKID_SEC_AHB_AHB3_BRIDGE 52 +#define CLKID_GIC 53 +#define CLKID_AO_MEDIA_CPU 54 +#define CLKID_AO_AHB_SRAM 55 +#define CLKID_AO_AHB_BUS 56 +#define CLKID_AO_IFACE 57 +#define CLKID_AO_I2C 58 +#define CLKID_SD_EMMC_B_CLK0 59 +#define CLKID_SD_EMMC_C_CLK0 60 + +#endif /* __AXG_CLKC_H */ -- 2.15.1
[PATCH PTI v2 0/6] Clean up pgd handling and fix VSYSCALL and LDT
I'm getting reasonably happy with this. It still needs more testing, but I want to get it out there. The main things that need testing are the 5-level case for the both vsyscalls and the LDT. I'm getting a double-fault in ldt_gdt_64, but I haven't checked whether it's a bug in this series, and it kind of looks like it isn't. I'll figure it out in the morning. The docs also want updating for the 5 level case. Changes from v1: - vsyscalls actually work. - Added the "Warn and fail" patch to prevent the testing goof I had on v1. - Lots of cleanups Andy Lutomirski (6): x86/pti: Vastly simplify pgd synchronization Revert "x86/mm/pti: Disable native VSYSCALL" x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode x86/pti: Map the vsyscall page if needed x86/pti: Put the LDT in its own PGD if PTI is on Documentation/x86/x86_64/mm.txt | 11 ++- arch/x86/Kconfig| 8 -- arch/x86/entry/vsyscall/vsyscall_64.c | 37 - arch/x86/include/asm/mmu_context.h | 33 +++- arch/x86/include/asm/pgtable.h | 6 +- arch/x86/include/asm/pgtable_64.h | 77 -- arch/x86/include/asm/pgtable_64_types.h | 2 + arch/x86/include/asm/processor.h| 23 -- arch/x86/include/asm/vsyscall.h | 1 + arch/x86/kernel/ldt.c | 138 +--- arch/x86/mm/pti.c | 115 -- 11 files changed, 331 insertions(+), 120 deletions(-) -- 2.13.6
[PATCH PTI v2 4/6] x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode
If something goes wrong with pagetable setup, vsyscall=native will
accidentally fall back to emulation. Make it warn and fail so that
we notice.
Signed-off-by: Andy Lutomirski
---
arch/x86/entry/vsyscall/vsyscall_64.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c
b/arch/x86/entry/vsyscall/vsyscall_64.c
index bc88a0540347..a06f2ae09ad6 100644
--- a/arch/x86/entry/vsyscall/vsyscall_64.c
+++ b/arch/x86/entry/vsyscall/vsyscall_64.c
@@ -138,6 +138,10 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long
address)
WARN_ON_ONCE(address != regs->ip);
+ /* This should be unreachable in NATIVE mode. */
+ if (WARN_ON(vsyscall_mode == NATIVE))
+ return false;
+
if (vsyscall_mode == NONE) {
warn_bad_vsyscall(KERN_INFO, regs,
"vsyscall attempted with vsyscall=none");
--
2.13.6
[PATCH PTI v2 1/6] x86/pti: Vastly simplify pgd synchronization
Back when we would dynamically add mappings to the usermode tables,
we needed to preallocate all the high top-level entries in the
usermode tables. We don't need this in recent versions of PTI, so
get rid of preallocation.
With preallocation gone, the comments in pti_set_user_pgd() make
even less sense. Rearrange the function to make it entirely obvious
what it does and does not do. FWIW, I haven't even tried to wrap my
head around the old logic, since it seemed to be somewhere between
incomprehensible and wrong.
I admit that a bit of the earlier complexity was based on my
suggestions. Mea culpa.
Signed-off-by: Andy Lutomirski
---
arch/x86/include/asm/pgtable_64.h | 74 +++
arch/x86/mm/pti.c | 52 ++-
2 files changed, 39 insertions(+), 87 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_64.h
b/arch/x86/include/asm/pgtable_64.h
index f5adf92091c6..be8d086de927 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -195,14 +195,6 @@ static inline bool pgdp_maps_userspace(void *__ptr)
}
/*
- * Does this PGD allow access from userspace?
- */
-static inline bool pgd_userspace_access(pgd_t pgd)
-{
- return pgd.pgd & _PAGE_USER;
-}
-
-/*
* Take a PGD location (pgdp) and a pgd value that needs to be set there.
* Populates the user and returns the resulting PGD that must be set in
* the kernel copy of the page tables.
@@ -213,50 +205,42 @@ static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t
pgd)
if (!static_cpu_has_bug(X86_BUG_CPU_SECURE_MODE_PTI))
return pgd;
- if (pgd_userspace_access(pgd)) {
- if (pgdp_maps_userspace(pgdp)) {
- /*
-* The user page tables get the full PGD,
-* accessible from userspace:
-*/
- kernel_to_user_pgdp(pgdp)->pgd = pgd.pgd;
- /*
-* For the copy of the pgd that the kernel uses,
-* make it unusable to userspace. This ensures on
-* in case that a return to userspace with the
-* kernel CR3 value, userspace will crash instead
-* of running.
-*
-* Note: NX might be not available or disabled.
-*/
- if (__supported_pte_mask & _PAGE_NX)
- pgd.pgd |= _PAGE_NX;
- }
- } else if (pgd_userspace_access(*pgdp)) {
+ if (pgdp_maps_userspace(pgdp)) {
/*
-* We are clearing a _PAGE_USER PGD for which we presumably
-* populated the user PGD. We must now clear the user PGD
-* entry.
+* The user page tables get the full PGD,
+* accessible from userspace:
*/
- if (pgdp_maps_userspace(pgdp)) {
- kernel_to_user_pgdp(pgdp)->pgd = pgd.pgd;
- } else {
- /*
-* Attempted to clear a _PAGE_USER PGD which is in
-* the kernel portion of the address space. PGDs
-* are pre-populated and we never clear them.
-*/
- WARN_ON_ONCE(1);
- }
+ kernel_to_user_pgdp(pgdp)->pgd = pgd.pgd;
+
+ /*
+* If this is normal user memory, make it NX in the kernel
+* pagetables so that, if we somehow screw up and return to
+* usermode with the kernel CR3 loaded, we'll get a page
+* fault instead of allowing user code to execute with
+* the wrong CR3.
+*
+* As exceptions, we don't set NX if:
+* - this is EFI or similar, the kernel may execute from it
+* - we don't have NX support
+* - we're clearing the PGD (i.e. pgd.pgd == 0).
+*/
+ if ((pgd.pgd & _PAGE_USER) && (__supported_pte_mask & _PAGE_NX))
+ pgd.pgd |= _PAGE_NX;
} else {
/*
-* _PAGE_USER was not set in either the PGD being set or
-* cleared. All kernel PGDs should be pre-populated so
-* this should never happen after boot.
+* Changes to the high (kernel) portion of the kernelmode
+* page tables are not automatically propagated to the
+* usermode tables.
+*
+* Users should keep in mind that, unlike the kernelmode
+* tables, there is no vmalloc_fault equivalent for the
+* usermode tables. Top-level entries added to init_mm's
+* usermode pgd after boot
[PATCH v6 0/6] add clk controller driver for Meson-AXG SoC
Add driver for the clk controller which found in Meson AXG SoC Note, we deliberately create a seperate source file for the Meson AXG series, instead of sharing code with previous GXBB/GXL - the file axg.c It would help us maintaining the code more easily. Changes since v5 [5]: - add Rob's Ack for patch 2, add Neil's Ack for patch 3 - include spinlock' name change patch, patch 4 - include uart_ao clock DTS patch Changes since v4 [4]: - use devm_ioremap instead of devm_ioremap_resource - rename DT node using generic name 'bus' Changes since v3 [3]: - separate dt-bindings header file - adjust license note as standard way - replace of_iomap with platform/devm API - add Rob's Ack to Patch 1,4 Changes since v2 [2]: - drop register offset calculation - update dt-bindings for new compatible variant Changes since v1 [1]: - rework register definion, use '(offset << 2)' to better match the description from data sheet - drop "#include dt-bindings/clock/gxbb-aoclkc.h" from dts - rebase code to v4.15-rc1 [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005655.html http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005656.html http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005657.html http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005658.html http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005659.html [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005522.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005525.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005526.html [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005487.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005488.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005489.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005490.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005468.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005469.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005470.html [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005239.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005240.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005241.html Qiufang Dai (3): clk: meson-axg: add clocks dt-bindings required header clk: meson-axg: add clock controller drivers arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan (3): dt-bindings: clock: add compatible variant for the Meson-AXG clk: meson: make the spinlock naming more specific arm64: dts: meson-axg: switch uart_ao clock to CLK81 .../bindings/clock/amlogic,gxbb-clkc.txt | 7 +- arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 19 +- drivers/clk/meson/Kconfig | 8 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/axg.c| 944 + drivers/clk/meson/axg.h| 126 +++ drivers/clk/meson/clkc.h | 2 +- drivers/clk/meson/gxbb.c | 112 +-- drivers/clk/meson/meson8b.c| 24 +- include/dt-bindings/clock/axg-clkc.h | 71 ++ 12 files changed, 1242 insertions(+), 75 deletions(-) create mode 100644 drivers/clk/meson/axg.c create mode 100644 drivers/clk/meson/axg.h create mode 100644 include/dt-bindings/clock/axg-clkc.h -- 2.15.1
[PATCH PTI v2 2/6] Revert "x86/mm/pti: Disable native VSYSCALL"
This reverts commit 6a7b4041b853ecc653e2c1dda5b736ab5fd29357. With the PGD-propagation logic simplified, there's no need for this. --- arch/x86/Kconfig | 8 1 file changed, 8 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 411838058194..babb1e53b0a6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2233,9 +2233,6 @@ choice config LEGACY_VSYSCALL_NATIVE bool "Native" - # The VSYSCALL page comes from the kernel page tables - # and is not available when PAGE_TABLE_ISOLATION is enabled. - depends on !PAGE_TABLE_ISOLATION help Actual executable code is located in the fixed vsyscall address mapping, implementing time() efficiently. Since @@ -2253,11 +2250,6 @@ choice exploits. This configuration is recommended when userspace still uses the vsyscall area. - When PAGE_TABLE_ISOLATION is enabled, the vsyscall area will become - unreadable. This emulation option still works, but PAGE_TABLE_ISOLATION - will make it harder to do things like trace code using the - emulation. - config LEGACY_VSYSCALL_NONE bool "None" help -- 2.13.6
[PATCH PTI v2 5/6] x86/pti: Map the vsyscall page if needed
Make VSYSCALLs work fully in PTI mode.
Signed-off-by: Andy Lutomirski
---
arch/x86/entry/vsyscall/vsyscall_64.c | 6 ++--
arch/x86/include/asm/pgtable.h| 6 +++-
arch/x86/include/asm/pgtable_64.h | 9 +++--
arch/x86/include/asm/vsyscall.h | 1 +
arch/x86/mm/pti.c | 63 +++
5 files changed, 78 insertions(+), 7 deletions(-)
diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c
b/arch/x86/entry/vsyscall/vsyscall_64.c
index a06f2ae09ad6..e4a6fe8354f0 100644
--- a/arch/x86/entry/vsyscall/vsyscall_64.c
+++ b/arch/x86/entry/vsyscall/vsyscall_64.c
@@ -343,14 +343,14 @@ int in_gate_area_no_mm(unsigned long addr)
* vsyscalls but leave the page not present. If so, we skip calling
* this.
*/
-static void __init set_vsyscall_pgtable_user_bits(void)
+void __init set_vsyscall_pgtable_user_bits(pgd_t *root)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
- pgd = pgd_offset_k(VSYSCALL_ADDR);
+ pgd = pgd_offset_pgd(root, VSYSCALL_ADDR);
pgd->pgd |= _PAGE_USER;
p4d = p4d_offset(pgd, VSYSCALL_ADDR);
#if CONFIG_PGTABLE_LEVELS >= 5
@@ -372,7 +372,7 @@ void __init map_vsyscall(void)
vsyscall_mode == NATIVE
? PAGE_KERNEL_VSYSCALL
: PAGE_KERNEL_VVAR);
- set_vsyscall_pgtable_user_bits();
+ set_vsyscall_pgtable_user_bits(swapper_pg_dir);
}
BUILD_BUG_ON((unsigned long)__fix_to_virt(VSYSCALL_PAGE) !=
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 83c0c77e7365..a8a8fc15ca16 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -920,7 +920,11 @@ static inline int pgd_none(pgd_t pgd)
* pgd_offset() returns a (pgd_t *)
* pgd_index() is used get the offset into the pgd page's array of pgd_t's;
*/
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
+#define pgd_offset_pgd(pgd, address) (pgd + pgd_index((address)))
+/*
+ * a shortcut to get a pgd_t in a given mm
+ */
+#define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
/*
* a shortcut which implies the use of the kernel's pgd, instead
* of a process's
diff --git a/arch/x86/include/asm/pgtable_64.h
b/arch/x86/include/asm/pgtable_64.h
index be8d086de927..a2fb3f8bc985 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -220,11 +220,14 @@ static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t
pgd)
* the wrong CR3.
*
* As exceptions, we don't set NX if:
-* - this is EFI or similar, the kernel may execute from it
+* - _PAGE_USER is not set. This could be an executable
+* EFI runtime mapping or something similar, and the kernel
+* may execute from it
* - we don't have NX support
-* - we're clearing the PGD (i.e. pgd.pgd == 0).
+* - we're clearing the PGD (i.e. the new pgd is not present).
*/
- if ((pgd.pgd & _PAGE_USER) && (__supported_pte_mask & _PAGE_NX))
+ if ((pgd.pgd & (_PAGE_USER|_PAGE_PRESENT)) ==
(_PAGE_USER|_PAGE_PRESENT) &&
+ (__supported_pte_mask & _PAGE_NX))
pgd.pgd |= _PAGE_NX;
} else {
/*
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index d9a7c659009c..b986b2ca688a 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -7,6 +7,7 @@
#ifdef CONFIG_X86_VSYSCALL_EMULATION
extern void map_vsyscall(void);
+extern void set_vsyscall_pgtable_user_bits(pgd_t *root);
/*
* Called on instruction fetch fault in vsyscall page.
diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
index f48645d2f3fd..a9c53d21f0a8 100644
--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -38,6 +38,7 @@
#include
#include
+#include
#include
#include
#include
@@ -133,6 +134,48 @@ static pmd_t *pti_user_pagetable_walk_pmd(unsigned long
address)
return pmd_offset(pud, address);
}
+/*
+ * Walk the shadow copy of the page tables (optionally) trying to allocate
+ * page table pages on the way down. Does not support large pages.
+ *
+ * Note: this is only used when mapping *new* kernel data into the
+ * user/shadow page tables. It is never used for userspace data.
+ *
+ * Returns a pointer to a PTE on success, or NULL on failure.
+ */
+static pte_t *pti_user_pagetable_walk_pte(unsigned long address)
+{
+ gfp_t gfp = (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
+ pmd_t *pmd = pti_user_pagetable_walk_pmd(address);
+ pte_t *pte;
+
+ /* We can't do anything sensible if we hit a large mapping. */
+ if (pmd_large(*pmd)) {
+ WARN_ON(1);
+ return NULL;
+ }
+
+ if
Re: [PATCH 2/4] fs/notify: don't put file handle buffer on stack.
On Mon, Dec 11, 2017 at 8:04 AM, NeilBrown wrote: > A file handle buffer is not tiny, and could need to be larger in future, > so it isn't safe to allocate one on the stack. Instead, we need to > kmalloc(). > > There is no way to return an error status from a ->show_fdinfo() > function, so if the kmalloc fails, we silently exclude the filehandle > from the output. As it is at the end of line, this shouldn't > upset parsing too much. I think that is a bold assumption to make about parsers ;) Anyway, the second reasoning is stronger, so may as well drop this one. There is probably a single userspace user for this which is CRIU, for which this fdinfo file handle was added, so you could possibly say that this change does not upset this user (?). > In any case, it can only fail when the > process is being killed by the OOM killer, so the file will never > be parsed anyway. > > Signed-off-by: NeilBrown
[PATCH PTI v2 6/6] x86/pti: Put the LDT in its own PGD if PTI is on
With PTI on, we need the LDT to be in the usermode tables somewhere,
and the LDT is per-mm.
tglx had a hack to have a per-cpu LDT and context switch it, but it
was probably insanely slow due to the required TLB flushes.
Instead, take advantage of the fact that we have an address space
hole that gives us a completely unused pgd and make that pgd be
per-mm. We can put the LDT in it.
This has a down side: the LDT isn't (currently) randomized, and an
attack that can write the LDT is instant root due to call gates
(thanks, AMD, for leaving call gates in AMD64 but designing them
wrong so they're only useful for exploits). We could mitigate this
by making the LDT read-only or randomizing it, either of which is
strightforward on top of this patch.
XXX: The 5-level case needs testing and docs updates
Signed-off-by: Andy Lutomirski
---
Documentation/x86/x86_64/mm.txt | 11 ++-
arch/x86/include/asm/mmu_context.h | 33 +++-
arch/x86/include/asm/pgtable_64_types.h | 2 +
arch/x86/include/asm/processor.h| 23 --
arch/x86/kernel/ldt.c | 138 +---
5 files changed, 184 insertions(+), 23 deletions(-)
diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt
index 2d7d6590ade8..bfa44e1cb293 100644
--- a/Documentation/x86/x86_64/mm.txt
+++ b/Documentation/x86/x86_64/mm.txt
@@ -12,13 +12,15 @@ ea00 - eaff (=40 bits) virtual
memory map (1TB)
... unused hole ...
ec00 - fbff (=44 bits) kasan shadow memory (16TB)
... unused hole ...
+fe80 - feff (=39 bits) LDT range
ff00 - ff7f (=39 bits) %esp fixup stacks
... unused hole ...
ffef - fffe (=64 GB) EFI region mapping space
... unused hole ...
8000 - 9fff (=512 MB) kernel text mapping, from phys 0
-a000 - ff5f (=1526 MB) module mapping space (variable)
-ff60 - ffdf (=8 MB) vsyscalls
+a000 - [fixmap start] (~1526 MB) module mapping space (variable)
+[fixmap start] - ff5f kernel-internal fixmap range
+ff60 - ff600fff (=4 kB) legacy vsyscall ABI
ffe0 - (=2 MB) unused hole
Virtual memory map with 5 level page tables:
@@ -39,8 +41,9 @@ ff00 - ff7f (=39 bits) %esp fixup
stacks
ffef - fffe (=64 GB) EFI region mapping space
... unused hole ...
8000 - 9fff (=512 MB) kernel text mapping, from phys 0
-a000 - ff5f (=1526 MB) module mapping space
-ff60 - ffdf (=8 MB) vsyscalls
+a000 - [fixmap start] (~1526 MB) module mapping space
+[fixmap start] - ff5f kernel-internal fixmap range
+ff60 - ff600fff (=4 kB) legacy vsyscall ABI
ffe0 - (=2 MB) unused hole
Architecture defines a 64-bit virtual address. Implementations can support
diff --git a/arch/x86/include/asm/mmu_context.h
b/arch/x86/include/asm/mmu_context.h
index 5e1a1ecb65c6..eb87bbeddacc 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -52,13 +52,29 @@ struct ldt_struct {
*/
struct desc_struct *entries;
unsigned int nr_entries;
+
+ /*
+* If PTI is in use, then the entries array is not mapped while we're
+* in user mode. The whole array will be aliased at the addressed
+* given by ldt_slot_va(slot).
+*/
+ int slot;
};
+/* This is a multiple of PAGE_SIZE. */
+#define LDT_SLOT_STRIDE (LDT_ENTRIES * LDT_ENTRY_SIZE)
+
+static void *ldt_slot_va(int slot)
+{
+ return (void *)(LDT_BASE_ADDR + LDT_SLOT_STRIDE * slot);
+}
+
/*
* Used for LDT copy/destruction.
*/
int init_new_context_ldt(struct task_struct *tsk, struct mm_struct *mm);
void destroy_context_ldt(struct mm_struct *mm);
+void ldt_arch_exit_mmap(struct mm_struct *mm);
#else /* CONFIG_MODIFY_LDT_SYSCALL */
static inline int init_new_context_ldt(struct task_struct *tsk,
struct mm_struct *mm)
@@ -90,10 +106,20 @@ static inline void load_mm_ldt(struct mm_struct *mm)
* that we can see.
*/
- if (unlikely(ldt))
- set_ldt(ldt->entries, ldt->nr_entries);
- else
+ if (unlikely(ldt)) {
+ if (static_cpu_has_bug(X86_BUG_CPU_SECURE_MODE_PTI)) {
+ if (WARN_ON_ONCE((unsigned long)ldt->slot > 1)) {
+ clear_LDT();
+ return;
+ }
+
+ set_ldt(ldt_slot_va(ldt->slot), ldt->nr_entries);
+ } else {
+ set_ldt(ldt->entries, ldt->nr_entries);
+ }
+ } else {
clear_LDT();
+ }
#else
clear_LDT
[PATCH PTI v2 3/6] x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy
The kernel is very erratic as to which pagetables have _PAGE_USER
set. The vsyscall page gets lucky: it seems that all of the
relevant pagetables are among the apparently arbitrary ones that set
_PAGE_USER. Rather than relying on chance, just explicitly set
_PAGE_USER.
This will let us clean up pagetable setup to stop setting
_PAGE_USER. The added code can also be reused by pagetable
isolation to manage the _PAGE_USER bit in the usermode tables.
Signed-off-by: Andy Lutomirski
---
arch/x86/entry/vsyscall/vsyscall_64.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c
b/arch/x86/entry/vsyscall/vsyscall_64.c
index f279ba2643dc..bc88a0540347 100644
--- a/arch/x86/entry/vsyscall/vsyscall_64.c
+++ b/arch/x86/entry/vsyscall/vsyscall_64.c
@@ -329,16 +329,47 @@ int in_gate_area_no_mm(unsigned long addr)
return vsyscall_mode != NONE && (addr & PAGE_MASK) == VSYSCALL_ADDR;
}
+/*
+ * The VSYSCALL page is the only user-accessible page in the kernel address
+ * range. Normally, the kernel page tables can have _PAGE_USER clear, but
+ * the tables covering VSYSCALL_ADDR need _PAGE_USER set if vsyscalls
+ * are enabled.
+ *
+ * Some day we may create a "minimal" vsyscall mode in which we emulate
+ * vsyscalls but leave the page not present. If so, we skip calling
+ * this.
+ */
+static void __init set_vsyscall_pgtable_user_bits(void)
+{
+ pgd_t *pgd;
+ p4d_t *p4d;
+ pud_t *pud;
+ pmd_t *pmd;
+
+ pgd = pgd_offset_k(VSYSCALL_ADDR);
+ pgd->pgd |= _PAGE_USER;
+ p4d = p4d_offset(pgd, VSYSCALL_ADDR);
+#if CONFIG_PGTABLE_LEVELS >= 5
+ p4d->p4d |= _PAGE_USER;
+#endif
+ pud = pud_offset(p4d, VSYSCALL_ADDR);
+ pud->pud |= _PAGE_USER;
+ pmd = pmd_offset(pud, VSYSCALL_ADDR);
+ pmd->pmd |= _PAGE_USER;
+}
+
void __init map_vsyscall(void)
{
extern char __vsyscall_page;
unsigned long physaddr_vsyscall = __pa_symbol(&__vsyscall_page);
- if (vsyscall_mode != NONE)
+ if (vsyscall_mode != NONE) {
__set_fixmap(VSYSCALL_PAGE, physaddr_vsyscall,
vsyscall_mode == NATIVE
? PAGE_KERNEL_VSYSCALL
: PAGE_KERNEL_VVAR);
+ set_vsyscall_pgtable_user_bits();
+ }
BUILD_BUG_ON((unsigned long)__fix_to_virt(VSYSCALL_PAGE) !=
(unsigned long)VSYSCALL_ADDR);
--
2.13.6
Re: [RFC][PATCH] apparent big-endian bugs in dwc-xlgmac
On 2017/12/11 13:38, Al Viro wrote:
> On Mon, Dec 11, 2017 at 05:05:20AM +, Al Viro wrote:
>
>> What for? Sure, this variant will work, but why bother with
>> a = le32_to_cpu(b);
>> (cpu_to_le32(a) & ) |
>> and how is that better than
>> (b & ...) | ...
>>
>> IDGI... Mind you, I'm not sure if there is any point keeping _var in that
>> thing,
>> seeing that we use var only once - might be better off with
>> ((var) & ~cpu_to_le32(GENMASK(_pos + _len - 1, _pos))) |\
>> cpu_to_le32(_val); \
> FWIW, seeing how many drivers end up open-coding that, I'm rather tempted to
> add to linux/bitops.h or linux/byteorder/generic.h the following:
>
> static inline __le16 le16_replace_bits(__le16 old, u16 v, int bit, int size)
> {
> __le16 mask = cpu_to_le16(GENMASK(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_le16(v << bit) & mask);
> }
>
> static inline __le32 le32_replace_bits(__le32 old, u32 v, int bit, int size)
> {
> __le32 mask = cpu_to_le32(GENMASK(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_le32(v << bit) & mask);
> }
>
> static inline __le64 le64_replace_bits(__le64 old, u64 v, int bit, int size)
> {
> __le64 mask = cpu_to_le64(GENMASK_ULL(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_le64(v << bit) & mask);
> }
>
> static inline __be16 be16_replace_bits(__be16 old, u16 v, int bit, int size)
> {
> __be16 mask = cpu_to_be16(GENMASK(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_be16(v << bit) & mask);
> }
>
> static inline __be32 be32_replace_bits(__be32 old, u32 v, int bit, int size)
> {
> __be32 mask = cpu_to_be32(GENMASK(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_be32(v << bit) & mask);
> }
>
> static inline __be64 be64_replace_bits(__be64 old, u64 v, int bit, int size)
> {
> __be64 mask = cpu_to_be64(GENMASK_ULL(bit + size - 1, bit));
> return (old & ~mask) | (cpu_to_be64(v << bit) & mask);
> }
>
> static inline u16 le16_get_bits(__le16 v, int bit, int size)
> {
> return (le16_to_cpu(v) >> bit) & (BIT(size) - 1);
> }
>
> static inline u32 le32_get_bits(__le32 v, int bit, int size)
> {
> return (le32_to_cpu(v) >> bit) & (BIT(size) - 1);
> }
>
> static inline u64 le64_get_bits(__le64 v, int bit, int size)
> {
> return (le64_to_cpu(v) >> bit) & (BIT_ULL(size) - 1);
> }
>
> static inline u16 be16_get_bits(__be16 v, int bit, int size)
> {
> return (be16_to_cpu(v) >> bit) & (BIT(size) - 1);
> }
>
> static inline u32 be32_get_bits(__be32 v, int bit, int size)
> {
> return (be32_to_cpu(v) >> bit) & (BIT(size) - 1);
> }
>
> static inline u64 be64_get_bits(__be64 v, int bit, int size)
> {
> return (be64_to_cpu(v) >> bit) & (BIT_ULL(size) - 1);
> }
>
> and let drivers use those...
Sounds good. As a driver developer, I'm happy to see this.
Re: [PATCH 1/4] fs/notify: fdinfo can report unsupported file handles.
On Mon, Dec 11, 2017 at 8:04 AM, NeilBrown wrote: > If a filesystem does not set sb->s_export_op, then it > does not support filehandles and export_fs_encode_fh() > and exportfs_encode_inode_fh() should not be called. > They will use export_encode_fh() is which is a default > that uses inode number generation number, but in general > they may not be stable. > > So change exportfs_encode_inode_fh() to return FILEID_INVALID > if called on an unsupported Filesystem. Currently only > notify/fdinfo can do that. > I wish you would leave this check to the caller, maybe add a helper exportfs_can_decode_fh() for callers to use. Although there are no current uses for it in-tree, there is value in being able to encode a unique file handle even when it cannot be decoded back to an open file. I am using this property in my fanotify super block watch patches, where the object identifier on the event is an encoded file handle of the object, which delegates tracking filesystem objects to userspace and prevents fanotify from keeping elevated refcounts on inodes and dentries. There are quite a few userspace tools out there that are checking that st_ino hasn't changed on a file between non atomic operations. Those tools (or others) could benefit from a unique file handle if we ever decide to provide a relaxed version of name_to_handle_at(). Cheers, Amir.
Re: [PATCH v18 10/10] virtio-balloon: don't report free pages when page poisoning is enabled
On 12/01/2017 11:49 PM, Michael S. Tsirkin wrote:
On Wed, Nov 29, 2017 at 09:55:26PM +0800, Wei Wang wrote:
The guest free pages should not be discarded by the live migration thread
when page poisoning is enabled with PAGE_POISONING_NO_SANITY=n, because
skipping the transfer of such poisoned free pages will trigger false
positive when new pages are allocated and checked on the destination.
This patch skips the reporting of free pages in the above case.
Reported-by: Michael S. Tsirkin
Signed-off-by: Wei Wang
Cc: Michal Hocko
---
drivers/virtio/virtio_balloon.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c
index 035bd3a..6ac4cff 100644
--- a/drivers/virtio/virtio_balloon.c
+++ b/drivers/virtio/virtio_balloon.c
@@ -652,7 +652,9 @@ static void report_free_page(struct work_struct *work)
/* Start by sending the obtained cmd id to the host with an outbuf */
send_one_desc(vb, vb->free_page_vq, virt_to_phys(&vb->start_cmd_id),
sizeof(uint32_t), false, true, false);
- walk_free_mem_block(vb, 0, &virtio_balloon_send_free_pages);
+ if (!(page_poisoning_enabled() &&
+ !IS_ENABLED(CONFIG_PAGE_POISONING_NO_SANITY)))
+ walk_free_mem_block(vb, 0, &virtio_balloon_send_free_pages);
/*
* End by sending the stop id to the host with an outbuf. Use the
* non-batching mode here to trigger a kick after adding the stop id.
PAGE_POISONING_ZERO is actually OK.
But I really would prefer it that we still send pages to host,
otherwise debugging becomes much harder.
And it does not have to be completely useless, even though
you can not discard them as they would be zero-filled then.
How about a config field telling host what should be there in the free
pages? This way even though host can not discard them, host can send
them out without reading them, still a win.
Since this poison value comes with the free page reporting feature, how
about sending the poison value via the free_page_vq, along with the cmd
id in the outbuf? That is, use the following interface:
struct virtio_balloon_free_page_vq_hdr {
bool page_poisoning;
__virtio32 poison_value;
__virtio32 cmd_id;
}
We need "bool page_poisoning" because "poison_value=0" doesn't tell
whether page poising is in use by the guest. PAGE_POISONING_ZERO sets
"page_poisoning=true, poisoning_value=0", and the host will send the
0-filled pages to the destination (if not sending 0-filled pages, the
destination host would offer non-zero pages to the guest)
The host can discard free pages only when "page_poisoning=false".
Best,
Wei
Re: [PATCH 1/4] fs/notify: fdinfo can report unsupported file handles.
On Mon, Dec 11, 2017 at 05:04:05PM +1100, NeilBrown wrote:
> @@ -385,7 +385,9 @@ int exportfs_encode_inode_fh(struct inode *inode, struct
> fid *fid,
> {
> const struct export_operations *nop = inode->i_sb->s_export_op;
>
> - if (nop && nop->encode_fh)
> + if (nop)
> + return FILEID_INVALID;
> + if (nop->encode_fh)
> return nop->encode_fh(inode, fid->raw, max_len, parent);
This might as well have been
if (nop)
return FILEID_INVALID;
BUG();
Have you ever tested that?
Re: [PATCH 00/13] Updates for QCOM Alpha PLL
On 2017-12-09 05:46, Stephen Boyd wrote:
On 12/08, Abhishek Sahu wrote:
On 2017-12-07 11:53, Stephen Boyd wrote:
>On 09/28, Abhishek Sahu wrote:
>>This patch series does the miscellaneous changes in QCOM Alpha PLL
>>operation and structure to support other types of Alpha PLL’s.
>>
>>1. It adds the pll_type which will be used for determining all
>> the properties of Alpha PLL.
>>2. It adds the support for Brammo and Huayra PLL’s for which
>> the support is not available in existing alpha PLL code.
>>3. There won’t be any change in existing users of Alpha PLL’s
>> since all the newly added code will be under flag for the default
>> PLL operations.
>>
>
>Ok. I took a long look at this today. I rewrote a bunch of stuff.
Thanks Stephen for reviewing the changes and making the code
cleaner. I checked all the code changes and everything looks
good. It will work for all of our requirement. I will check
with other PLL users also once and then update the patch
series with all your suggested code changes after complete
testing.
Ok. Please don't resend. I've pushed out the branch to clk-next,
and it can be adjusted if needed, or dropped and rewritten if
something is totally busted.
Thanks Stephen for your great help and support.
It seems, we are getting the error in the following error with these
patches because of missing EXPORT_SYMBOL_GPL for
clk_alpha_pll_regs and clk_hw_is_enabled.
ERROR: "clk_alpha_pll_regs" [drivers/clk/qcom/mmcc-msm8996.ko]
undefined!
ERROR: "clk_hw_is_enabled" [drivers/clk/qcom/clk-qcom.ko] undefined!
Caused by commits
d1506b749e92 ("clk: qcom: support for alpha pll properties")
e66a4d6d0081 ("clk: qcom: support for dynamic updating the PLL")
301803e6013b ("clk: qcom: support Huayra type Alpha PLL")
[PATCH 1/4] fs/notify: fdinfo can report unsupported file handles.
If a filesystem does not set sb->s_export_op, then it
does not support filehandles and export_fs_encode_fh()
and exportfs_encode_inode_fh() should not be called.
They will use export_encode_fh() is which is a default
that uses inode number generation number, but in general
they may not be stable.
So change exportfs_encode_inode_fh() to return FILEID_INVALID
if called on an unsupported Filesystem. Currently only
notify/fdinfo can do that.
Also remove the WARNing from fdinfo when exportfs_encode_inode_fh()
returns FILEID_INVALID, as that is no an erroneous condition.
Signed-off-by: NeilBrown
---
fs/exportfs/expfs.c |4 +++-
fs/notify/fdinfo.c |4 +---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/fs/exportfs/expfs.c b/fs/exportfs/expfs.c
index 329a5d103846..f5b27dd843a1 100644
--- a/fs/exportfs/expfs.c
+++ b/fs/exportfs/expfs.c
@@ -385,7 +385,9 @@ int exportfs_encode_inode_fh(struct inode *inode, struct
fid *fid,
{
const struct export_operations *nop = inode->i_sb->s_export_op;
- if (nop && nop->encode_fh)
+ if (nop)
+ return FILEID_INVALID;
+ if (nop->encode_fh)
return nop->encode_fh(inode, fid->raw, max_len, parent);
return export_encode_fh(inode, fid, max_len, parent);
diff --git a/fs/notify/fdinfo.c b/fs/notify/fdinfo.c
index d478629c728b..d1135ed61229 100644
--- a/fs/notify/fdinfo.c
+++ b/fs/notify/fdinfo.c
@@ -50,10 +50,8 @@ static void show_mark_fhandle(struct seq_file *m, struct
inode *inode)
size = f.handle.handle_bytes >> 2;
ret = exportfs_encode_inode_fh(inode, (struct fid *)f.handle.f_handle,
&size, 0);
- if ((ret == FILEID_INVALID) || (ret < 0)) {
- WARN_ONCE(1, "Can't encode file handler for inotify: %d\n",
ret);
+ if ((ret == FILEID_INVALID) || (ret < 0))
return;
- }
f.handle.handle_type = ret;
f.handle.handle_bytes = size * sizeof(u32);
[PATCH 2/4] fs/notify: don't put file handle buffer on stack.
A file handle buffer is not tiny, and could need to be larger in future,
so it isn't safe to allocate one on the stack. Instead, we need to
kmalloc().
There is no way to return an error status from a ->show_fdinfo()
function, so if the kmalloc fails, we silently exclude the filehandle
from the output. As it is at the end of line, this shouldn't
upset parsing too much. In any case, it can only fail when the
process is being killed by the OOM killer, so the file will never
be parsed anyway.
Signed-off-by: NeilBrown
---
fs/notify/fdinfo.c | 47 +--
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/fs/notify/fdinfo.c b/fs/notify/fdinfo.c
index d1135ed61229..7347f295bc0f 100644
--- a/fs/notify/fdinfo.c
+++ b/fs/notify/fdinfo.c
@@ -23,54 +23,56 @@
static void show_fdinfo(struct seq_file *m, struct file *f,
void (*show)(struct seq_file *m,
-struct fsnotify_mark *mark))
+struct fsnotify_mark *mark,
+struct fid *fh))
{
struct fsnotify_group *group = f->private_data;
struct fsnotify_mark *mark;
+ struct fid *fh = kmalloc(MAX_HANDLE_SZ, GFP_KERNEL);
mutex_lock(&group->mark_mutex);
list_for_each_entry(mark, &group->marks_list, g_list) {
- show(m, mark);
+ show(m, mark, fh);
if (seq_has_overflowed(m))
break;
}
mutex_unlock(&group->mark_mutex);
+ kfree(fh);
}
#if defined(CONFIG_EXPORTFS)
-static void show_mark_fhandle(struct seq_file *m, struct inode *inode)
+static void show_mark_fhandle(struct seq_file *m, struct inode *inode,
+ struct fid *fhbuf)
{
- struct {
- struct file_handle handle;
- u8 pad[MAX_HANDLE_SZ];
- } f;
int size, ret, i;
+ unsigned char *bytes;
- f.handle.handle_bytes = sizeof(f.pad);
- size = f.handle.handle_bytes >> 2;
+ if (!fhbuf)
+ return;
+ size = MAX_HANDLE_SZ >> 2;
- ret = exportfs_encode_inode_fh(inode, (struct fid *)f.handle.f_handle,
&size, 0);
+ ret = exportfs_encode_inode_fh(inode, fhbuf, &size, 0);
if ((ret == FILEID_INVALID) || (ret < 0))
return;
- f.handle.handle_type = ret;
- f.handle.handle_bytes = size * sizeof(u32);
-
- seq_printf(m, "fhandle-bytes:%x fhandle-type:%x f_handle:",
- f.handle.handle_bytes, f.handle.handle_type);
+ seq_printf(m, "fhandle-bytes:%zx fhandle-type:%x f_handle:",
+ size * sizeof(u32), ret);
- for (i = 0; i < f.handle.handle_bytes; i++)
- seq_printf(m, "%02x", (int)f.handle.f_handle[i]);
+ bytes = (unsigned char *)(fhbuf->raw);
+ for (i = 0; i < size * sizeof(u32); i++)
+ seq_printf(m, "%02x", bytes[i]);
}
#else
-static void show_mark_fhandle(struct seq_file *m, struct inode *inode)
+static void show_mark_fhandle(struct seq_file *m, struct inode *inode,
+ struct fid *fhbuf)
{
}
#endif
#ifdef CONFIG_INOTIFY_USER
-static void inotify_fdinfo(struct seq_file *m, struct fsnotify_mark *mark)
+static void inotify_fdinfo(struct seq_file *m, struct fsnotify_mark *mark,
+ struct fid *fhbuf)
{
struct inotify_inode_mark *inode_mark;
struct inode *inode;
@@ -91,7 +93,7 @@ static void inotify_fdinfo(struct seq_file *m, struct
fsnotify_mark *mark)
seq_printf(m, "inotify wd:%x ino:%lx sdev:%x mask:%x
ignored_mask:%x ",
inode_mark->wd, inode->i_ino, inode->i_sb->s_dev,
mask, mark->ignored_mask);
- show_mark_fhandle(m, inode);
+ show_mark_fhandle(m, inode, fhbuf);
seq_putc(m, '\n');
iput(inode);
}
@@ -106,7 +108,8 @@ void inotify_show_fdinfo(struct seq_file *m, struct file *f)
#ifdef CONFIG_FANOTIFY
-static void fanotify_fdinfo(struct seq_file *m, struct fsnotify_mark *mark)
+static void fanotify_fdinfo(struct seq_file *m, struct fsnotify_mark *mark,
+ struct fid *fhbuf)
{
unsigned int mflags = 0;
struct inode *inode;
@@ -121,7 +124,7 @@ static void fanotify_fdinfo(struct seq_file *m, struct
fsnotify_mark *mark)
seq_printf(m, "fanotify ino:%lx sdev:%x mflags:%x mask:%x
ignored_mask:%x ",
inode->i_ino, inode->i_sb->s_dev,
mflags, mark->mask, mark->ignored_mask);
- show_mark_fhandle(m, inode);
+ show_mark_fhandle(m, inode, fhbuf);
seq_putc(m, '\n');
iput(inode);
} else if (mark->connector->flags & FSNOTIFY_OBJ_TYPE_VFSMOUNT) {
[PATCH 0/4] VFS: fix assorted issues with name_to_handle conversions.
This series of patches is the result of discussion following the previous patch which increases MAX_HANDLE_SZ. Thanks, NeilBrown --- NeilBrown (4): fs/notify: fdinfo can report unsupported file handles. fs/notify: don't put file handle buffer on stack. NFS: allow name_to_handle_at() to work for Amazon EFS. fhandle: Improve error responses in name_to_handle_at() fs/exportfs/expfs.c |4 +++- fs/fhandle.c | 16 +- fs/nfs/export.c |2 ++ fs/notify/fdinfo.c | 51 +++--- include/linux/exportfs.h | 10 +++-- 5 files changed, 49 insertions(+), 34 deletions(-) -- Signature
[PATCH 4/4] fhandle: Improve error responses in name_to_handle_at()
1/ Always return the mnt_id, even if some other error occurs. It can be useful without the file handle. An application can initialise the memory to, e.g. -1 and if there is some other value after name_to_handle_at() returns, then it is a valid mnt_id. If the value is unchanged, then the kernel does not have this patch. 2/ Don't return -EINVAL if the requested handle_bytes is larger than MAX_HANDLE_SZ. There is no need for an error and it causes unnecessary behavior change in the kernel ever needs to increase MAX_HANDLE_SZ. Simple limit handle_bytes to MAX_HANDLE_SZ silently. Signed-off-by: NeilBrown --- fs/fhandle.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/fs/fhandle.c b/fs/fhandle.c index 0ace128f5d23..04afffaeb742 100644 --- a/fs/fhandle.c +++ b/fs/fhandle.c @@ -23,9 +23,16 @@ static long do_sys_name_to_handle(struct path *path, int handle_dwords, handle_bytes; struct file_handle *handle = NULL; + /* +* Always return the mnt_id, it might be useful even +* without the file handle +*/ + if (copy_to_user(mnt_id, &real_mount(path->mnt)->mnt_id, +sizeof(*mnt_id))) + return -EFAULT; /* * We need to make sure whether the file system -* support decoding of the file handle +* supports decoding of the file handle. */ if (!path->dentry->d_sb->s_export_op || !path->dentry->d_sb->s_export_op->fh_to_dentry) @@ -35,7 +42,7 @@ static long do_sys_name_to_handle(struct path *path, return -EFAULT; if (f_handle.handle_bytes > MAX_HANDLE_SZ) - return -EINVAL; + f_handle.handle_bytes = MAX_HANDLE_SZ; handle = kmalloc(sizeof(struct file_handle) + f_handle.handle_bytes, GFP_KERNEL); @@ -68,10 +75,7 @@ static long do_sys_name_to_handle(struct path *path, retval = -EOVERFLOW; } else retval = 0; - /* copy the mount id */ - if (copy_to_user(mnt_id, &real_mount(path->mnt)->mnt_id, -sizeof(*mnt_id)) || - copy_to_user(ufh, handle, + if (copy_to_user(ufh, handle, sizeof(struct file_handle) + handle_bytes)) retval = -EFAULT; kfree(handle);
[PATCH 3/4] NFS: allow name_to_handle_at() to work for Amazon EFS.
Amazon EFS provides an NFSv4.1 filesystem which appears to use
(close to) full length (128 byte) file handles.
This causes the handle reported by name_to_handle_at() to exceed
MAX_HANDLE_SZ, resulting in
EOVERFLOW if 128 bytes were requested, or
EINVAL if the size reported by the previous call was requested.
To fix this, increase MAX_HANDLE_SIZE a little, and add a BUILD_BUG
so that this sort of inconsistent error reporting won't happen again.
Link: https://github.com/systemd/systemd/issues/7082#issuecomment-347380436
Signed-off-by: NeilBrown
---
fs/nfs/export.c |2 ++
include/linux/exportfs.h | 10 --
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/fs/nfs/export.c b/fs/nfs/export.c
index 83fd09fc8f77..23b2fc3ab2bb 100644
--- a/fs/nfs/export.c
+++ b/fs/nfs/export.c
@@ -39,6 +39,8 @@ nfs_encode_fh(struct inode *inode, __u32 *p, int *max_len,
struct inode *parent)
size_t fh_size = offsetof(struct nfs_fh, data) + server_fh->size;
int len = EMBED_FH_OFF + XDR_QUADLEN(fh_size);
+ BUILD_BUG_ON_MSG(EMBED_FH_OFF + NFS_MAXFHSIZE > MAX_HANDLE_SZ,
+ "MAX_HANDLE_SZ is too small");
dprintk("%s: max fh len %d inode %p parent %p",
__func__, *max_len, inode, parent);
diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h
index 0d3037419bc7..71eb9c2cc2fb 100644
--- a/include/linux/exportfs.h
+++ b/include/linux/exportfs.h
@@ -11,8 +11,14 @@ struct iomap;
struct super_block;
struct vfsmount;
-/* limit the handle size to NFSv4 handle size now */
-#define MAX_HANDLE_SZ 128
+/* Must be larger than NFSv4 file handle.
+ * overlayfs doesn't want this too close to 255.
+ * NOTE: This value MUST NOT be exported to user-space.
+ * Applications must only ever see MAX_HANDLE_SZ == 128.
+ * If they try a larger number on older kernels, they
+ * will get -EINVAL which will be confusing.
+ */
+#define MAX_HANDLE_SZ 200
/*
* The fileid_type identifies how the file within the filesystem is encoded.
Re: linux-next: build warning after merge of the device-mapper tree
Hi Mike, On Mon, 11 Dec 2017 00:24:36 -0500 Mike Snitzer wrote: > > I worked all weekend on DM code and compiled dm.c probably 30 times, > pretty bizarre that the RHEL7 gcc compiler isn't spewing anything about > this. That is weird. > Anyway, I just fixed it via rebase (new commit is > 6fb0326f0a19dd855bfd748481fd32035770376e). Excellent, thanks. -- Cheers, Stephen Rothwell
Re: [RFC][PATCH] apparent big-endian bugs in dwc-xlgmac
On Mon, Dec 11, 2017 at 05:05:20AM +, Al Viro wrote:
> What for? Sure, this variant will work, but why bother with
> a = le32_to_cpu(b);
> (cpu_to_le32(a) & ) |
> and how is that better than
> (b & ...) | ...
>
> IDGI... Mind you, I'm not sure if there is any point keeping _var in that
> thing,
> seeing that we use var only once - might be better off with
> ((var) & ~cpu_to_le32(GENMASK(_pos + _len - 1, _pos))) |\
> cpu_to_le32(_val); \
FWIW, seeing how many drivers end up open-coding that, I'm rather tempted to
add to linux/bitops.h or linux/byteorder/generic.h the following:
static inline __le16 le16_replace_bits(__le16 old, u16 v, int bit, int size)
{
__le16 mask = cpu_to_le16(GENMASK(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_le16(v << bit) & mask);
}
static inline __le32 le32_replace_bits(__le32 old, u32 v, int bit, int size)
{
__le32 mask = cpu_to_le32(GENMASK(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_le32(v << bit) & mask);
}
static inline __le64 le64_replace_bits(__le64 old, u64 v, int bit, int size)
{
__le64 mask = cpu_to_le64(GENMASK_ULL(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_le64(v << bit) & mask);
}
static inline __be16 be16_replace_bits(__be16 old, u16 v, int bit, int size)
{
__be16 mask = cpu_to_be16(GENMASK(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_be16(v << bit) & mask);
}
static inline __be32 be32_replace_bits(__be32 old, u32 v, int bit, int size)
{
__be32 mask = cpu_to_be32(GENMASK(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_be32(v << bit) & mask);
}
static inline __be64 be64_replace_bits(__be64 old, u64 v, int bit, int size)
{
__be64 mask = cpu_to_be64(GENMASK_ULL(bit + size - 1, bit));
return (old & ~mask) | (cpu_to_be64(v << bit) & mask);
}
static inline u16 le16_get_bits(__le16 v, int bit, int size)
{
return (le16_to_cpu(v) >> bit) & (BIT(size) - 1);
}
static inline u32 le32_get_bits(__le32 v, int bit, int size)
{
return (le32_to_cpu(v) >> bit) & (BIT(size) - 1);
}
static inline u64 le64_get_bits(__le64 v, int bit, int size)
{
return (le64_to_cpu(v) >> bit) & (BIT_ULL(size) - 1);
}
static inline u16 be16_get_bits(__be16 v, int bit, int size)
{
return (be16_to_cpu(v) >> bit) & (BIT(size) - 1);
}
static inline u32 be32_get_bits(__be32 v, int bit, int size)
{
return (be32_to_cpu(v) >> bit) & (BIT(size) - 1);
}
static inline u64 be64_get_bits(__be64 v, int bit, int size)
{
return (be64_to_cpu(v) >> bit) & (BIT_ULL(size) - 1);
}
and let drivers use those...
Re: [PATCH] KVM: VMX: drop I/O permission bitmaps
On 2017/12/09 01:31, Jim Mattson wrote:
On Fri, Dec 8, 2017 at 2:22 AM, Quan Xu wrote:
From: Quan Xu
Since KVM removes the only I/O port 0x80 bypass on Intel hosts,
clear CPU_BASED_USE_IO_BITMAPS and set CPU_BASED_UNCOND_IO_EXITING
bit. Then these I/O permission bitmaps are not used at all, so
drop I/O permission bitmaps.
Signed-off-by: Jim Mattson
Signed-off-by: Radim Krčmář
Signed-off-by: Quan Xu
---
arch/x86/kvm/vmx.c | 17 +
1 files changed, 1 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2fd9a8c..3e4f760 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -771,8 +771,6 @@ enum segment_cache_field {
FIELD(HOST_FS_SELECTOR, host_fs_selector),
FIELD(HOST_GS_SELECTOR, host_gs_selector),
FIELD(HOST_TR_SELECTOR, host_tr_selector),
- FIELD64(IO_BITMAP_A, io_bitmap_a),
- FIELD64(IO_BITMAP_B, io_bitmap_b),
These two lines should stay.
Jim, could you explain why these two lines should stay?
IIUC, the main concern is from nested virtualization, which still uses
io_bitmap_a/io_bitmap_b..
if so, we really need to further clean up these code, as
CPU_BASED_USE_IO_BITMAPS is clear, and CPU_BASED_UNCOND_IO_EXITING is set for
both L0/L2. after new patches which I mentioned
in this thread.
right?
Alibaba Cloud
Quan
linux-next: Tree for Dec 11
Hi all, Changes since 20171208: The clk tree gained build failures so I used the version from next-20171208. The v4l-dvb-next tree gained conflicts against the vfs tree. The akpm-current tree gained a build failure for which I added a fix patch. The akpm tree lost a patch that turned up elsewhere. Non-merge commits (relative to Linus' tree): 3585 4000 files changed, 125336 insertions(+), 123397 deletions(-) I have created today's linux-next tree at git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git (patches at http://www.kernel.org/pub/linux/kernel/next/ ). If you are tracking the linux-next tree using git, you should not use "git pull" to do so as that will try to merge the new linux-next release with the old one. You should use "git fetch" and checkout or reset to the new master. You can see which trees have been included by looking in the Next/Trees file in the source. There are also quilt-import.log and merge.log files in the Next directory. Between each merge, the tree was built with a ppc64_defconfig for powerpc, an allmodconfig for x86_64, a multi_v7_defconfig for arm and a native build of tools/perf. After the final fixups (if any), I do an x86_64 modules_install followed by builds for x86_64 allnoconfig, powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And finally, a simple boot test of the powerpc pseries_le_defconfig kernel in qemu (with and without kvm enabled). Below is a summary of the state of the merge. I am currently merging 251 trees (counting Linus' and 43 trees of bug fix patches pending for the current merge release). Stats about the size of the tree over time can be seen at http://neuling.org/linux-next-size.html . Status of my local build tests will be at http://kisskb.ellerman.id.au/linux-next . If maintainers want to give advice about cross compilers/configs that work, we are always open to add more builds. Thanks to Randy Dunlap for doing many randconfig builds. And to Paul Gortmaker for triage and bug fixes. -- Cheers, Stephen Rothwell $ git checkout master $ git reset --hard stable Merging origin/master (98087c05b9fc hpfs: don't bother with the i_version counter or f_version) Merging fixes/master (820bf5c419e4 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi) Merging kbuild-current/fixes (cfe17c9bbe6a kbuild: move cc-option and cc-disable-warning after incl. arch Makefile) Merging arc-current/for-curr (60e134d94018 ARC: provide for gcc "isolate path" induced generated abort calls) Merging arm-current/fixes (3aaf33bebda8 ARM: avoid faulting on qemu) Merging m68k-current/for-linus (5e387199c17c m68k/defconfig: Update defconfigs for v4.14-rc7) Merging metag-fixes/fixes (b884a190afce metag/usercopy: Add missing fixups) Merging powerpc-fixes/fixes (d81041820873 powerpc/xmon: Don't print hashed pointers in xmon) Merging sparc/master (a0908a1b7d68 Merge branch 'akpm' (patches from Andrew)) Merging fscrypt-current/for-stable (42d97eb0ade3 fscrypt: fix renaming and linking special files) Merging net/master (f335195adf04 kmemcheck: rip it out for real) Merging bpf/master (195bd525d5f6 Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf) Merging ipsec/master (75bf50f4aaa1 xfrm: fix xfrm_do_migrate() with AEAD e.g(AES-GCM)) Merging netfilter/master (96307a0a75d8 netfilter: ipt_CLUSTERIP: fix clusterip_net_exit build regression) Merging ipvs/master (f7fb77fc1235 netfilter: nft_compat: check extension hook mask only if set) Merging wireless-drivers/master (a41886f56b7b Merge tag 'iwlwifi-for-kalle-2017-12-05' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-fixes) Merging mac80211/master (156324d6e92c mac80211: fix locking in ieee80211_sta_tear_down_BA_sessions) Merging sound-current/for-linus (2b4584d00a6b ALSA: hda - Add vendor id for Cannonlake HDMI codec) Merging pci-current/for-linus (a19e2696135e x86/PCI: Only enable a 64bit BAR on single-socket AMD Family 15h) Merging driver-core.current/driver-core-linus (0946b2fb38fd firmware: cleanup FIRMWARE_IN_KERNEL message) Merging tty.current/tty-linus (c8ec2041f549 MIPS: Add custom serial.h with BASE_BAUD override for generic kernel) Merging usb.current/usb-linus (72b663a99c07 usb: xhci: fix TDS for MTK xHCI1.1) Merging usb-gadget-fixes/fixes (a3acc696085e usb: f_fs: Force Reserved1=1 in OS_DESC_EXT_COMPAT) Merging usb-serial-fixes/usb-linus (762ff4678e89 USB: serial: usb_debug: add new USB device id) Merging usb-chipidea-fixes/ci-for-usb-stable (cbb22ebcfb99 usb: chipidea: core: check before accessing ci_role in ci_role_show) Merging phy/fixes (521e84ab2507 phy: rcar-gen3-usb2: select USB_COMMON) Merging staging.current/staging-linus (202fc673c626 staging: pi433: Fixes issue with bit shift in rf69_get_modulation) Merging char-misc.current/char-misc-linus (66bc5df31110 M
Re: [PATCH -mm] mm, swap: Fix race between swapoff and some swap operations
Andrew Morton writes: > On Fri, 08 Dec 2017 16:41:38 +0800 "Huang\, Ying" > wrote: > >> > Why do we need srcu here? Is it enough with rcu like below? >> > >> > It might have a bug/room to be optimized about performance/naming. >> > I just wanted to show my intention. >> >> Yes. rcu should work too. But if we use rcu, it may need to be called >> several times to make sure the swap device under us doesn't go away, for >> example, when checking si->max in __swp_swapcount() and >> add_swap_count_continuation(). And I found we need rcu to protect swap >> cache radix tree array too. So I think it may be better to use one >> calling to srcu_read_lock/unlock() instead of multiple callings to >> rcu_read_lock/unlock(). > > Or use stop_machine() ;) It's very crude but it sure is simple. Does > anyone have a swapoff-intensive workload? Sorry, I don't know how to solve the problem with stop_machine(). The problem we try to resolved is that, we have a swap entry, but that swap entry can become invalid because of swappoff between we check it and we use it. So we need to prevent swapoff to be run between checking and using. I don't know how to use stop_machine() in swapoff to wait for all users of swap entry to finish. Anyone can help me on this? Best Regards, Huang, Ying
Re: linux-next: build warning after merge of the device-mapper tree
On Sun, Dec 10 2017 at 9:05pm -0500,
Stephen Rothwell wrote:
> Hi all,
>
> After merging the device-mapper tree, today's linux-next build (powerp
> ppc64_defconfig) produced this warning:
>
> drivers/md/dm.c: In function '__send_changing_extent_only':
> drivers/md/dm.c:1365:45: warning: 'ti' may be used uninitialized in this
> function [-Wmaybe-uninitialized]
> num_bios = get_num_bios ? get_num_bios(ti) : 0;
> ^
>
> Introduced by commit
>
> aecefd4919de ("dm: fix __send_changing_extent_only() to send first bio and
> chain remainder")
>
> This looks particularly bad :-(
I worked all weekend on DM code and compiled dm.c probably 30 times,
pretty bizarre that the RHEL7 gcc compiler isn't spewing anything about
this.
Anyway, I just fixed it via rebase (new commit is
6fb0326f0a19dd855bfd748481fd32035770376e).
Thanks,
Mike
Re: [v2 PATCH] cpufreq: powernv: Correctly parse the sign of pstates on POWER8 vs POWER9
Hi Balbir,
On Fri, Dec 08, 2017 at 02:44:40PM +1100, Balbir Singh wrote:
> On Thu, Dec 7, 2017 at 4:59 PM, Gautham R. Shenoy
> wrote:
> > From: "Gautham R. Shenoy"
> >
> > On POWERNV platform, Pstates are 8-bit values. On POWER8 they are
> > negatively numbered while on POWER9 they are positively
> > numbered. Thus, on POWER9, the maximum number of pstates could be as
> > high as 256.
> >
> > The current code interprets pstates as a signed 8-bit value. This
> > causes a problem on POWER9 platforms which have more than 128 pstates.
> > On such systems, on a CPU that is in a lower pstate whose number is
> > greater than 128, querying the current pstate returns a "pstate X is
> > out of bound" error message and the current pstate is reported as the
> > nominal pstate.
> >
> > This patch fixes the aforementioned issue by correctly differentiating
> > the sign whenever a pstate value read, depending on whether the
> > pstates are positively numbered or negatively numbered.
>
> Yikes! Is there no better way of fixing this?
There is. In fact, I am working on cleaning up the whole thing to make
it not depend on the sign until it is really needed (and that is to
check whether the pstate that we read from the PMSR is within bounds)
Besides, currently the kernel code assumes a few things that the
device-tree doesn't guarantee, such as the continguity of pstates.
>
> >
> > Fixes: commit 09ca4c9b5958 ("cpufreq: powernv: Replacing pstate_id with
> > frequency table index")
> > Cc: #v4.8
> > Signed-off-by: Gautham R. Shenoy
> > Tested-and-reviewed-by: Shilpasri G Bhat
> > Acked-by: Viresh Kumar
> > ---
> > drivers/cpufreq/powernv-cpufreq.c | 43
> > ++-
> > 1 file changed, 33 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/cpufreq/powernv-cpufreq.c
> > b/drivers/cpufreq/powernv-cpufreq.c
> > index b6d7c4c..bb7586e 100644
> > --- a/drivers/cpufreq/powernv-cpufreq.c
> > +++ b/drivers/cpufreq/powernv-cpufreq.c
> > @@ -41,11 +41,14 @@
> > #define POWERNV_MAX_PSTATES256
> > #define PMSR_PSAFE_ENABLE (1UL << 30)
> > #define PMSR_SPR_EM_DISABLE(1UL << 31)
> > -#define PMSR_MAX(x)((x >> 32) & 0xFF)
> > +#define EXTRACT_BYTE(x, shift) (((x) >> shift) & 0xFF)
> > +#define MAX_SHIFT 32
> > #define LPSTATE_SHIFT 48
> > #define GPSTATE_SHIFT 56
> > -#define GET_LPSTATE(x) (((x) >> LPSTATE_SHIFT) & 0xFF)
> > -#define GET_GPSTATE(x) (((x) >> GPSTATE_SHIFT) & 0xFF)
> > +#define GET_PMSR_MAX(x)EXTRACT_BYTE(x, MAX_SHIFT)
> > +#define GET_LPSTATE(x) EXTRACT_BYTE(x, LPSTATE_SHIFT)
> > +#define GET_GPSTATE(x) EXTRACT_BYTE(x, GPSTATE_SHIFT)
> > +
>
> Can you hide all of this in pstate_to_idx(), do the casting inside? I
> was reviewing this
> code earlier before being distracted with something else, this did
> come across as
> strange and I was looking at using abs values to simplify the code,
> but I did not get
> to it.
>
> Balbir Singh.
>
Re: [PATCH] KVM: VMX: drop I/O permission bitmaps
On 2017/12/09 00:18, David Hildenbrand wrote:
On 08.12.2017 11:22, Quan Xu wrote:
From: Quan Xu
Since KVM removes the only I/O port 0x80 bypass on Intel hosts,
clear CPU_BASED_USE_IO_BITMAPS and set CPU_BASED_UNCOND_IO_EXITING
bit. Then these I/O permission bitmaps are not used at all, so
drop I/O permission bitmaps.
Signed-off-by: Jim Mattson
Signed-off-by: Radim Krčmář
Signed-off-by: Quan Xu
---
arch/x86/kvm/vmx.c | 17 +
1 files changed, 1 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2fd9a8c..3e4f760 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -771,8 +771,6 @@ enum segment_cache_field {
FIELD(HOST_FS_SELECTOR, host_fs_selector),
FIELD(HOST_GS_SELECTOR, host_gs_selector),
FIELD(HOST_TR_SELECTOR, host_tr_selector),
- FIELD64(IO_BITMAP_A, io_bitmap_a),
- FIELD64(IO_BITMAP_B, io_bitmap_b),
FIELD64(MSR_BITMAP, msr_bitmap),
FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
@@ -943,8 +941,6 @@ static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12,
static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
enum {
- VMX_IO_BITMAP_A,
- VMX_IO_BITMAP_B,
VMX_MSR_BITMAP_LEGACY,
VMX_MSR_BITMAP_LONGMODE,
VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
@@ -958,8 +954,6 @@ enum {
static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
-#define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
-#define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
#define vmx_msr_bitmap_legacy
(vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
#define vmx_msr_bitmap_longmode
(vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
#define vmx_msr_bitmap_legacy_x2apic_apicv
(vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
@@ -3632,7 +3626,7 @@ static __init int setup_vmcs_config(struct vmcs_config
*vmcs_conf)
#endif
CPU_BASED_CR3_LOAD_EXITING |
CPU_BASED_CR3_STORE_EXITING |
- CPU_BASED_USE_IO_BITMAPS |
+ CPU_BASED_UNCOND_IO_EXITING |
CPU_BASED_MOV_DR_EXITING |
CPU_BASED_USE_TSC_OFFSETING |
CPU_BASED_INVLPG_EXITING |
@@ -5445,10 +5439,6 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
#endif
int i;
- /* I/O */
- vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
- vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
-
if (enable_shadow_vmcs) {
vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
@@ -6751,14 +6741,9 @@ static __init int hardware_setup(void)
goto out;
}
- vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
- memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
-
- memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
-
memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
Looks good to me.
David, thanks for your review.
We could now also drop
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index a5d2856eb28b..732e93332f4c 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -10639,7 +10639,6 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu,
struct vmcs12 *vmcs12,
* Rather, exit every time.
*/
exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
- exec_control |= CPU_BASED_UNCOND_IO_EXITING;
vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
As this will be implicitly set by vmx_exec_control()
good catch.
yes, L0 merge vmcs01 with vmcsl2 to create vmcs02 and run L2.
however as this code is related to nested virtualization, I better
introduce it in another new patch
with "KVM: NVMX" prefix subject after this patch is applied.
furthermore, I think I could drop these tow lines in another new patch:
- exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
- exec_control |= CPU_BASED_UNCOND_IO_EXITING;
as the CPU_BASED_USE_IO_BITMAPS is clear after this patch.
Quan
[PATCH 20/20] ARM: dts: aspeed-plametto: Add flash layout
The OpenBMC flash layout is used by Palmetto systems. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index a8f0c046e83e..cc18137386f2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -34,6 +34,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; +#include "openbmc-flash-layout.dtsi" }; }; -- 2.14.1
[PATCH 19/20] ARM: dts: aspeed-romulus: Update Romulus system
- Fix incorrect RAM size
- Remove alias; these are now specified in the dtsi
- Add newly upstreamed devices
- Include OpenBMC flash layout
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 155 +--
1 file changed, 149 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 8067793129ea..bfdf643584df 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
@@ -7,17 +7,13 @@
model = "Romulus BMC";
compatible = "ibm,romulus-bmc", "aspeed,ast2500";
- aliases {
- serial4 = &uart5;
- };
-
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
- reg = <0x8000 0x4000>;
+ reg = <0x8000 0x2000>;
};
reserved-memory {
@@ -29,6 +25,73 @@
no-map;
reg = <0xbf00 0x0100>; /* 16M */
};
+
+ flash_memory: region@9800 {
+ no-map;
+ reg = <0x9800 0x0400>; /* 64M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
};
};
@@ -38,6 +101,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+#include "openbmc-flash-layout.dtsi"
};
};
@@ -53,6 +117,12 @@
};
};
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
&uart1 {
/* Rear RS-232 connector */
status = "okay";
@@ -81,6 +151,10 @@
pinctrl-0 = <&pinctrl_rmii1_default>;
};
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -133,8 +207,77 @@
&i2c12 {
status = "okay";
+
+ max31785@52 {
+ compatible = "maxim,max31785";
+ reg = <0x52>;
+ };
+};
+
+&gpio {
+ nic_func_mode0 {
+ gpio-hog;
+ gpios = ;
+ output-low;
+ line-name = "nic_func_mode0";
+ };
+ nic_func_mode1 {
+ gpio-hog;
+ gpios = ;
+ output-low;
+ line-name = "nic_func_mode1";
+ };
};
&vuart {
status = "okay";
};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan@2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan@3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan@4 {
+
[PATCH 18/20] ARM: dts: aspeed: Add Qanta Q71L BMC machine
From: Rick Altherr
The Qanta Q71L BMC is an ASPEED ast2400 based BMC that is part of a
Qanta x86 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Peter Hanson
Signed-off-by: Andrew Jeffery
Signed-off-by: Patrick Venture
Signed-off-by: Rick Altherr
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++
2 files changed, 460 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 48c55f307aa9..5ab5d9169511 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1106,5 +1106,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-witherspoon.dtb \
- aspeed-bmc-opp-zaius.dtb
+ aspeed-bmc-opp-zaius.dtb \
+ aspeed-bmc-quanta-q71l.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
new file mode 100644
index ..2f40bab63149
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+
+/ {
+ model = "Quanta Q71L BMC";
+ compatible = "quanta,q71l-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x4000 0x800>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@4780 {
+ no-map;
+ reg = <0x4780 0x0080>; /* 8MB */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 11>;
+ };
+
+ i2c1mux: i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
+ i2c-parent = <&i2c1>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
+ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* temp2 inlet */
+ tmp75@4c {
+ compatible = "ti,tmp75";
+ reg = <0x4c>;
+ };
+
+ /* temp3 */
+ tmp75@4e {
+ compatible = "ti,tmp75";
+ reg = <0x4e>;
+ };
+
+ /* temp1 */
+ tmp75@4f {
+ compatible = "ti,tmp75";
+ reg = <0x4f>;
+ };
+
+ /* Baseboard FRU */
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ /* FP FRU */
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* 0: PCIe Slot 2,
+*Slot 3,
+*Slot 6,
+*Slo
[PATCH 16/20] ARM: dts: aspeed: Add Witherspoon BMC machine
The Witherspoon BMC is an ASPEED ast2500 based BMC that is part of an
OpenPower Power9 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Brandon Wyman
Signed-off-by: Matt Spinler
Signed-off-by: Brad Bishop
Signed-off-by: Edward A. James
Signed-off-by: Cédric Le Goater
Signed-off-by: Andrew Jeffery
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 547 +++
2 files changed, 550 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d1e9d37bf3a..15a9207319c1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1104,5 +1104,7 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-romulus.dtb
+ aspeed-bmc-opp-romulus.dtb \
+ aspeed-bmc-opp-witherspoon.dtb
+
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
new file mode 100644
index ..9a0937512e5b
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include
+
+/ {
+ model = "Witherspoon BMC";
+ compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x8000 0x2000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@9800 {
+ no-map;
+ reg = <0x9800 0x0400>; /* 64M */
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fan0 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ front-fault {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
+ };
+
+ front-power {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ front-id {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rear-fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-id {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-power {
+ gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ power-button {
+
[PATCH 13/20] ARM: dts: aspeed: Update license headers
In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier
to files with no license") these files had the GPL-2.0 licence added
automatically. Update them to be GPL 2.0+ in line with other IBM kernel
contributions.
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 602bc10fdaf4..3e6f38e5d5d0 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index c786bc2f2919..a8f0c046e83e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g4.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2d7ac577d6b5..9c175832babc 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include
#include
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 030a760696fd..360329eab7c3 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include
#include
--
2.14.1
[PATCH 17/20] ARM: dts: aspeed: Add Ingrasys Zaius BMC machine
From: Xo Wang
Zaius is a POWER9 platform announced at OpenPOWER Summit 2016. This adds
basic DTS support for its AST2500 BMC.
This adds the device tree description for most upstream components. It
is a squashed commit of all of the patches from the OpenBMC kernel tree.
Signed-off-by: Xo Wang
Signed-off-by: Patrick Venture
Signed-off-by: Robert Lippert
Signed-off-by: Peter Hanson
Signed-off-by: Jeremy Kerr
Signed-off-by: Cédric Le Goater
Signed-off-by: Rick Altherr
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 427 +
2 files changed, 429 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 15a9207319c1..48c55f307aa9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1105,6 +1105,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
- aspeed-bmc-opp-witherspoon.dtb
-
+ aspeed-bmc-opp-witherspoon.dtb \
+ aspeed-bmc-opp-zaius.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
new file mode 100644
index ..90d77012495d
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include
+
+/ {
+ model = "Zaius BMC";
+ compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x8000 0x4000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@9800 {
+ no-map;
+ reg = <0x9800 0x0400>; /* 64M */
+ };
+ };
+
+ onewire0 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire1 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire2 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire3 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys_boot_status {
+ label = "System boot status";
+ gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ attention {
+ label = "Attention";
+ gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ plt_fault {
+ label = "Platform fault";
+ gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ hdd_fault {
+ label = "Onboard drive fault";
+ gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+ <&adc 13>, <&adc 14>, <&adc 15>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+
[PATCH 15/20] ARM: dts: aspeed: Sort ASPEED entries in makefile
In preperation for adding more boards. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..5d1e9d37bf3a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1101,7 +1101,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb -dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ - aspeed-bmc-opp-romulus.dtb \ - aspeed-ast2500-evb.dtb +dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-ast2500-evb.dtb \ + aspeed-bmc-opp-palmetto.dtb \ + aspeed-bmc-opp-romulus.dtb endif -- 2.14.1
[PATCH 14/20] ARM: dts: Add OpenBMC flash layout
This is a layout used by OpenBMC systems. It describes the fixed flash
layout of a 32MB mtd device.
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 +
1 file changed, 32 insertions(+)
create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi
b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
new file mode 100644
index ..63ad8db7a431
--- /dev/null
+++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x6>;
+ label = "u-boot";
+ };
+
+ u-boot-env@6 {
+ reg = <0x6 0x2>;
+ label = "u-boot-env";
+ };
+
+ kernel@8 {
+ reg = <0x8 0x44>;
+ label = "kernel";
+ };
+
+ rofs@0c {
+ reg = <0x4c 0x174>;
+ label = "rofs";
+ };
+
+ rwfs@1c0 {
+ reg = <0x1c0 0x40>;
+ label = "rwfs";
+ };
+};
--
2.14.1
[PATCH 11/20] ARM: dts: aspeed: Add LPC Snoop device
LPC snoop hardware on the ASPEED BMC, used for monitoring
host I/O port activity.
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index f6fee40c04c0..b3580f37f507 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -236,6 +236,13 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible =
"aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
lhc: lhc@20 {
compatible =
"aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 96a9d2fe3f0d..50766f0629f8 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -287,6 +287,12 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible =
"aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
lhc: lhc@20 {
compatible =
"aspeed,ast2500-lhc";
--
2.14.1
[PATCH 12/20] ARM: dts: aspeed: Remove skeleton.dtsi
We don't require it for any of the ASPEED systems. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 - arch/arm/boot/dts/aspeed-g5.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b3580f37f507..2d7ac577d6b5 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" #include #include diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 50766f0629f8..030a760696fd 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" #include #include -- 2.14.1
[PATCH 10/20] ARM: dts: aspeed: Add PWM and tachometer node
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 9 +
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index fa52a01f50b5..f6fee40c04c0 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -189,6 +189,15 @@
clocks = <&syscon ASPEED_CLK_APB>;
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2400-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2400-vuart";
reg = <0x1e787000 0x40>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5e6db2aa5c23..96a9d2fe3f0d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -239,6 +239,15 @@
status = "disabled";
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
--
2.14.1
[PATCH 08/20] ARM: dts: aspeed: Add flash controller clocks
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2e3666d4fbeb..afac0ca0cb10 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -56,6 +56,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -71,6 +72,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 24bb2d16b900..f3689caf6fe2 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -56,6 +56,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -81,6 +82,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@@ -100,6 +102,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
--
2.14.1
[PATCH 09/20] ARM: dts: aspeed: Add clock phandle to GPIO
This enables a feature where the driver can debounce inputs. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index afac0ca0cb10..fa52a01f50b5 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -144,6 +144,7 @@ reg = <0x1e78 0x1000>; interrupts = <20>; gpio-ranges = <&pinctrl 0 0 220>; + clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f3689caf6fe2..5e6db2aa5c23 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -187,6 +187,7 @@ reg = <0x1e78 0x1000>; interrupts = <20>; gpio-ranges = <&pinctrl 0 0 220>; + clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; }; -- 2.14.1
[PATCH 07/20] ARM: dts: aspeed: Add watchdog clocks
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index cf407b4db630..2e3666d4fbeb 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -177,11 +177,13 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785020 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
vuart: serial@1e787000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index ab26156d6822..24bb2d16b900 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -219,16 +219,19 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt3: watchdog@1e785040 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785040 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
};
--
2.14.1
[PATCH 05/20] ARM: dts: aspeed: Add proper clock references
The existing device trees use fixed-clocks in order to boot without a
clk driver. The newly added clk driver provides proper clock support,
including gating, so we move the device trees over to properly request
clocks.
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 100 +++--
arch/arm/boot/dts/aspeed-g5.dtsi | 104 +++
2 files changed, 81 insertions(+), 123 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b6d01523555a..c87883a7f250 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include
#include
/ {
@@ -107,47 +108,12 @@
ranges;
syscon: syscon@1e6e2000 {
- compatible = "aspeed,g4-scu", "syscon",
"simple-mfd";
+ compatible = "aspeed,ast2400-scu", "syscon",
"simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
-
-clk_clkin: clk_clkin {
-#clock-cells = <0>;
-compatible = "fixed-clock";
-clock-frequency = <4800>;
-};
-
-clk_hpll: clk_hpll@70 {
-#clock-cells = <0>;
-compatible = "aspeed,g4-hpll-clock",
"fixed-clock";
-reg = <0x70>;
-clocks = <&clk_clkin>;
-clock-frequency = <38400>;
-};
-
-clk_ahb: clk_ahb@70 {
-#clock-cells = <0>;
-compatible = "aspeed,g4-ahb-clock",
"fixed-clock";
-reg = <0x70>;
-clocks = <&clk_hpll>;
-clock-frequency = <19200>;
-};
-
-clk_apb: clk_apb@8 {
-#clock-cells = <0>;
-compatible = "aspeed,g4-apb-clock",
"fixed-clock";
-reg = <0x08>;
-clocks = <&clk_hpll>;
-clock-frequency = <4800>;
-};
-
-clk_uart: clk_uart@2c{
-#clock-cells = <0>;
-compatible = "aspeed,g4-uart-clock",
"fixed-clock";
-reg = <0x2c>;
-clock-frequency = <2400>;
-};
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g4-pinctrl";
@@ -157,7 +123,7 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2400-adc";
reg = <0x1e6e9000 0xb0>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
#io-channel-cells = <1>;
status = "disabled";
};
@@ -182,7 +148,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@@ -191,7 +157,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@@ -201,7 +167,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
- clocks = <&clk_uart>;
+
[PATCH 06/20] ARM: dts: aspeed: Add MAC clocks
Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++ arch/arm/boot/dts/aspeed-g5.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index c87883a7f250..cf407b4db630 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -91,6 +91,7 @@ compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e66 0x180>; interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; status = "disabled"; }; @@ -98,6 +99,7 @@ compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e68 0x180>; interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 90bc09d93ea6..ab26156d6822 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -125,6 +125,7 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e66 0x180>; interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; status = "disabled"; }; @@ -132,6 +133,7 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e68 0x180>; interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; }; -- 2.14.1
[PATCH 04/20] ARM: dts: aspeed: Add LPC and child devices
From: Andrew Jeffery
Ensure the ordering is correct and add all of the children in the SoC
device trees for the ast2400 and ast2500.
Signed-off-by: Andrew Jeffery
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++
arch/arm/boot/dts/aspeed-g5.dtsi | 27 +--
2 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9ebf90f34709..b6d01523555a 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -226,6 +226,41 @@
status = "disabled";
};
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2400-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2400-lpc-host",
"simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible =
"aspeed,ast2400-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+ lhc: lhc@20 {
+ compatible =
"aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+ };
+ };
+
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 1f9d28313f82..7861631940fe 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -266,6 +266,16 @@
status = "disabled";
};
+ vuart: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
@@ -289,6 +299,13 @@
reg-io-width = <4>;
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible =
"aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+
lhc: lhc@20 {
compatible =
"aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
@@ -296,16 +313,6 @@
};
};
- vuart: serial@1e787000 {
- compatible = "aspeed,ast2500-vuart";
- reg = <0x1e787000 0x40>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
-
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
--
2.14.1
[PATCH 03/20] ARM: dts: aspeed-g4: Correct VUART IRQ number
This should have always been 8. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 100d092e6c07..9ebf90f34709 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -220,7 +220,7 @@ compatible = "aspeed,ast2400-vuart"; reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <10>; + interrupts = <8>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; -- 2.14.1
[PATCH 01/20] dt-bindings: clock: Add ASPEED constants
These will be merged as part of the clock driver. This commit is included so the tree will build without the clock series being applied. Signed-off-by: Joel Stanley --- include/dt-bindings/clock/aspeed-clock.h | 54 1 file changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/aspeed-clock.h diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index ..fe46ab69da5c --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK16 +#define ASPEED_CLK_GATE_MAC1CLK17 +#define ASPEED_CLK_GATE_MAC2CLK18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART27 +#define ASPEED_CLK_SDIO28 +#define ASPEED_CLK_ECLK29 +#define ASPEED_CLK_ECLK_MUX30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK33 +#define ASPEED_CLK_MPLL34 + +#define ASPEED_NUM_CLKS35 + +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + +#endif -- 2.14.1
[PATCH 02/20] dt-bindings: gpio: Add ASPEED constants
These are used to by the device tree to map pin numbers to constants
required by the GPIO bindings.
Signed-off-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
3 files changed, 51 insertions(+)
create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 45d815a86d42..100d092e6c07 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include
/ {
model = "Aspeed BMC";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5c4ecdba3a6b..1f9d28313f82 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include
/ {
model = "Aspeed BMC";
diff --git a/include/dt-bindings/gpio/aspeed-gpio.h
b/include/dt-bindings/gpio/aspeed-gpio.h
new file mode 100644
index ..56fc4889b2c4
--- /dev/null
+++ b/include/dt-bindings/gpio/aspeed-gpio.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for binding aspeed,*-gpio.
+ *
+ * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+
+#include
+
+#define ASPEED_GPIO_PORT_A 0
+#define ASPEED_GPIO_PORT_B 1
+#define ASPEED_GPIO_PORT_C 2
+#define ASPEED_GPIO_PORT_D 3
+#define ASPEED_GPIO_PORT_E 4
+#define ASPEED_GPIO_PORT_F 5
+#define ASPEED_GPIO_PORT_G 6
+#define ASPEED_GPIO_PORT_H 7
+#define ASPEED_GPIO_PORT_I 8
+#define ASPEED_GPIO_PORT_J 9
+#define ASPEED_GPIO_PORT_K 10
+#define ASPEED_GPIO_PORT_L 11
+#define ASPEED_GPIO_PORT_M 12
+#define ASPEED_GPIO_PORT_N 13
+#define ASPEED_GPIO_PORT_O 14
+#define ASPEED_GPIO_PORT_P 15
+#define ASPEED_GPIO_PORT_Q 16
+#define ASPEED_GPIO_PORT_R 17
+#define ASPEED_GPIO_PORT_S 18
+#define ASPEED_GPIO_PORT_T 19
+#define ASPEED_GPIO_PORT_U 20
+#define ASPEED_GPIO_PORT_V 21
+#define ASPEED_GPIO_PORT_W 22
+#define ASPEED_GPIO_PORT_X 23
+#define ASPEED_GPIO_PORT_Y 24
+#define ASPEED_GPIO_PORT_Z 25
+#define ASPEED_GPIO_PORT_AA 26
+#define ASPEED_GPIO_PORT_AB 27
+#define ASPEED_GPIO_PORT_AC 28
+
+#define ASPEED_GPIO(port, offset) \
+ ((ASPEED_GPIO_PORT_##port * 8) + offset)
+
+#endif
--
2.14.1
[PATCH 00/20] ARM: dts: aspeed: updates and new machines
This series of device tree patches for the ASPEED BMC machines moves all systems to use the soon to be merged clk driver, and updates machines to use all of the drivers we have upstream. In addition it adds three new OpenBMC systems that have been developed in the OpenBMC kernel tree over the past year: two Power9 OpenPower systems, and a port by Google to a Quanta x86 server. I have boot tested these on Romulus and Palmetto, as well as boot tested all device trees in Qemu. Please review the boards you are familiar with. I will merge these in to the ASPEED ARM SoC tree for inclusion in 4.16. Andrew Jeffery (1): ARM: dts: aspeed: Add LPC and child devices Joel Stanley (17): dt-bindings: clock: Add ASPEED constants dt-bindings: gpio: Add ASPEED constants ARM: dts: aspeed-g4: Correct VUART IRQ number ARM: dts: aspeed: Add proper clock references ARM: dts: aspeed: Add MAC clocks ARM: dts: aspeed: Add watchdog clocks ARM: dts: aspeed: Add flash controller clocks ARM: dts: aspeed: Add clock phandle to GPIO ARM: dts: aspeed: Add PWM and tachometer node ARM: dts: aspeed: Add LPC Snoop device ARM: dts: aspeed: Remove skeleton.dtsi ARM: dts: aspeed: Update license headers ARM: dts: Add OpenBMC flash layout ARM: dts: aspeed: Sort ASPEED entries in makefile ARM: dts: aspeed: Add Witherspoon BMC machine ARM: dts: aspeed-romulus: Update Romulus system ARM: dts: aspeed-plametto: Add flash layout Rick Altherr (1): ARM: dts: aspeed: Add Qanta Q71L BMC machine Xo Wang (1): ARM: dts: aspeed: Add Ingrasys Zaius BMC machine arch/arm/boot/dts/Makefile | 8 +- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts| 3 +- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 155 ++- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 547 +++ arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 427 ++ arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++ arch/arm/boot/dts/aspeed-g4.dtsi | 164 --- arch/arm/boot/dts/aspeed-g5.dtsi | 155 --- arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 ++ include/dt-bindings/clock/aspeed-clock.h | 54 +++ include/dt-bindings/gpio/aspeed-gpio.h | 49 ++ 12 files changed, 1908 insertions(+), 146 deletions(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi create mode 100644 include/dt-bindings/clock/aspeed-clock.h create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h -- 2.14.1
linux-next: build failure after merge of the akpm-current tree
Hi Andrew,
After merging the akpm-current tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
In file included from include/linux/hugetlb.h:451:0,
from arch/powerpc/mm/hugetlbpage.c:14:
arch/powerpc/include/asm/hugetlb.h:125:26: error: redefinition of
'vma_mmu_pagesize'
#define vma_mmu_pagesize vma_mmu_pagesize
^
arch/powerpc/mm/hugetlbpage.c:563:15: note: in expansion of macro
'vma_mmu_pagesize'
unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
^
In file included from arch/powerpc/mm/hugetlbpage.c:14:0:
include/linux/hugetlb.h:274:29: note: previous definition of 'vma_mmu_pagesize'
was here
static inline unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
^
Caused by commit
ac9284a6b670 ("mm, hugetlbfs: introduce ->pagesize() to vm_operations_struct")
I have added the following fix patch for today:
From: Stephen Rothwell
Date: Mon, 11 Dec 2017 15:51:41 +1100
Subject: [PATCH] mm, hugetlbfs: move testing of vma_mmu_pagesize to after
inclusion of asm/hugetlb.h
Signed-off-by: Stephen Rothwell
---
arch/powerpc/include/asm/hugetlb.h | 1 +
include/linux/hugetlb.h| 26 +-
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/hugetlb.h
b/arch/powerpc/include/asm/hugetlb.h
index 14c9d44f355b..3cc6ca1bdaf2 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -123,6 +123,7 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
unsigned long addr,
* to override the version in mm/hugetlb.c
*/
#define vma_mmu_pagesize vma_mmu_pagesize
+unsigned long vma_mmu_pagesize(struct vm_area_struct *vma);
/*
* If the arch doesn't supply something else, assume that hugepage
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index c354befab724..b0f1f6768336 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -264,19 +264,6 @@ static inline unsigned long vma_kernel_pagesize(struct
vm_area_struct *vma)
return PAGE_SIZE;
}
-/*
- * Return the page size being used by the MMU to back a VMA. In the majority
- * of cases, the page size used by the kernel matches the MMU size. On
- * architectures where it differs, an architecture-specific version of this
- * function is required.
- */
-#ifndef vma_mmu_pagesize
-static inline unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
-{
- return vma_kernel_pagesize(vma);
-}
-#endif
-
#ifdef CONFIG_HUGETLBFS
struct hugetlbfs_sb_info {
longmax_inodes; /* inodes allowed */
@@ -615,6 +602,19 @@ static inline void set_huge_swap_pte_at(struct mm_struct
*mm, unsigned long addr
}
#endif /* CONFIG_HUGETLB_PAGE */
+/*
+ * Return the page size being used by the MMU to back a VMA. In the majority
+ * of cases, the page size used by the kernel matches the MMU size. On
+ * architectures where it differs, an architecture-specific version of this
+ * function is required.
+ */
+#ifndef vma_mmu_pagesize
+static inline unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
+{
+ return vma_kernel_pagesize(vma);
+}
+#endif
+
static inline spinlock_t *huge_pte_lock(struct hstate *h,
struct mm_struct *mm, pte_t *pte)
{
--
2.15.0
--
Cheers,
Stephen Rothwell
Re: [PATCH 4/4] PCI: dwc: pci-dra7xx: Fix legacy IRQ handling
On Saturday 09 December 2017 12:05 AM, Lorenzo Pieralisi wrote: > On Fri, Dec 01, 2017 at 11:43:11AM +0530, Vignesh R wrote: >> Legacy INTD IRQ handling is broken on dra7xx due to fact that driver >> uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size >> 4 which is numbered 0-3. Therefore when INTD IRQ line is used with >> pci-dra7xx driver following warning is seen: >> >>WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:342 >> irq_domain_associate+0x12c/0x1c4 >>error: hwirq 0x4 is too large for dummy >> >> Fix this by using pci_irqd_intx_xlate() helper to translate the INTx 1-4 >> range into the 0-3 as done in other PCIe drivers. >> >> Also, iterate over all the INTx bits and call their respective IRQ >> handlers before clearing the status register. > > It seems to me that you are fixing two bugs with one patch and therefore > I would ask you to split it in two or explain to me why we should > consider lumping them together. > Ok, I will split the patch into two in v2. -- Regards Vignesh
Re: linux-next: build warnings after merge of the scsi tree
Hi all,
On Wed, 6 Dec 2017 13:31:49 +1100 Stephen Rothwell
wrote:
>
> After merging the scsi tree, today's linux-next build (x86_64
> allmodconfig) produced these warnings:
>
> drivers/scsi/bfa/bfad_bsg.c: In function 'bfad_im_bsg_vendor_request':
> drivers/scsi/bfa/bfad_bsg.c:3137:35: warning: initialization makes pointer
> from integer without a cast [-Wint-conversion]
> struct bfad_im_port_s *im_port = shost->hostdata[0];
>^
> drivers/scsi/bfa/bfad_bsg.c: In function 'bfad_im_bsg_els_ct_request':
> drivers/scsi/bfa/bfad_bsg.c:3353:35: warning: initialization makes pointer
> from integer without a cast [-Wint-conversion]
> struct bfad_im_port_s *im_port = shost->hostdata[0];
>^
>
> Introduced by commit
>
> 45349821ab3a ("scsi: bfa: fix access to bfad_im_port_s")
I am still getting these ...
--
Cheers,
Stephen Rothwell
Re: [PATCH v4 72/73] xfs: Convert mru cache to XArray
On Mon, Dec 11, 2017 at 10:57:45AM +1100, Dave Chinner wrote:
> i.e. the fact the cmpxchg failed may not have anything to do with a
> race condtion - it failed because the slot wasn't empty like we
> expected it to be. There can be any number of reasons the slot isn't
> empty - the API should not "document" that the reason the insert
> failed was a race condition. It should document the case that we
> "couldn't insert because there was an existing entry in the slot".
> Let the surrounding code document the reason why that might have
> happened - it's not for the API to assume reasons for failure.
>
> i.e. this API and potential internal implementation makes much
> more sense:
>
> int
> xa_store_iff_empty(...)
> {
> curr = xa_cmpxchg(&pag->pag_ici_xa, agino, NULL, ip, GFP_NOFS);
> if (!curr)
> return 0; /* success! */
> if (!IS_ERR(curr))
> return -EEXIST; /* failed - slot not empty */
> return PTR_ERR(curr); /* failed - XA internal issue */
> }
>
> as it replaces the existing preload and insert code in the XFS code
> paths whilst letting us handle and document the "insert failed
> because slot not empty" case however we want. It implies nothing
> about *why* the slot wasn't empty, just that we couldn't do the
> insert because it wasn't empty.
Yeah, OK. So, over the top of the recent changes I'm looking at this:
I'm not in love with xa_store_empty() as a name. I almost want
xa_store_weak(), but after my MAP_FIXED_WEAK proposed name got shot
down, I'm leery of it. "empty" is at least a concept we already have
in the API with the comment for xa_init() talking about an empty array
and xa_empty(). I also considered xa_store_null and xa_overwrite_null
and xa_replace_null(). Naming remains hard.
diff --git a/fs/xfs/xfs_icache.c b/fs/xfs/xfs_icache.c
index 941f38bb94a4..586b43836905 100644
--- a/fs/xfs/xfs_icache.c
+++ b/fs/xfs/xfs_icache.c
@@ -451,7 +451,7 @@ xfs_iget_cache_miss(
int flags,
int lock_flags)
{
- struct xfs_inode*ip, *curr;
+ struct xfs_inode*ip;
int error;
xfs_agino_t agino = XFS_INO_TO_AGINO(mp, ino);
int iflags;
@@ -498,8 +498,7 @@ xfs_iget_cache_miss(
xfs_iflags_set(ip, iflags);
/* insert the new inode */
- curr = xa_cmpxchg(&pag->pag_ici_xa, agino, NULL, ip, GFP_NOFS);
- error = __xa_race(curr, -EAGAIN);
+ error = xa_store_empty(&pag->pag_ici_xa, agino, ip, GFP_NOFS, -EAGAIN);
if (error)
goto out_unlock;
diff --git a/include/linux/xarray.h b/include/linux/xarray.h
index 5792b6dbb040..cc7cc5253a67 100644
--- a/include/linux/xarray.h
+++ b/include/linux/xarray.h
@@ -271,43 +271,30 @@ static inline int xa_err(void *entry)
}
/**
- * __xa_race() - Turn a cmpxchg result into an errno.
- * @entry: Result from calling an XArray function.
- * @errno: Error number to return if we lost the race.
+ * xa_store_empty() - Store this entry in the XArray unless another entry is
+ * already present.
+ * @xa: XArray.
+ * @index: Index into array.
+ * @entry: New entry.
+ * @gfp: Memory allocation flags.
+ * @rc: Number to return if another entry was present.
*
- * Like xa_race(), but returns the error number of your choice. Calling
- * __xa_race(entry, 0) has the same result (but is less efficient) as
- * calling xa_err().
+ * Like xa_store(), but will fail and return the supplied error number if
+ * the existing entry at @index is not %NULL.
*
* Return: A negative errno or 0.
*/
-static inline int __xa_race(void *entry, int errno)
+static inline int xa_store_empty(struct xarray *xa, unsigned long index,
+ void *entry, gfp_t gfp, int errno)
{
- if (!entry)
+ void *curr = xa_cmpxchg(xa, index, NULL, entry, gfp);
+ if (!curr)
return 0;
- if (xa_is_err(entry))
- return (long)entry >> 2;
+ if (xa_is_err(curr))
+ return xa_err(curr);
return errno;
}
-/**
- * xa_race() - Turn a cmpxchg result into an errno.
- * @entry: Result from calling an XArray function.
- *
- * It is common to use xa_cmpxchg() to ensure that only one thread assigns
- * a value to an index. Pass the result from xa_cmpxchg() to xa_race() to
- * get an errno back. This function also handles any other error which
- * may have been returned by xa_cmpxchg() such as ENOMEM.
- *
- * If you don't care that you lost the race, you can use xa_err() instead.
- *
- * Return: A negative errno or 0.
- */
-static inline int xa_race(void *entry)
-{
- return __xa_race(entry, -EEXIST);
-}
-
/* Everything below here is the Advanced API. Proceed with caution. */
#define xa_trylock(xa) spin_trylock(&(xa)->xa_lock)
diff --git a/mm/backing-dev.c b/mm/backing-dev.c
index 85d1bc963ab6..87ed55af823e 100644
--- a/mm/backing-dev.c
+++ b
Re: [PATCH 27/45] net: remove duplicate includes
From: Pravin Shedge Date: Sun, 10 Dec 2017 23:30:21 +0530 > On Thu, Dec 7, 2017 at 2:28 AM, David Miller wrote: >> From: Pravin Shedge >> Date: Wed, 6 Dec 2017 23:02:58 +0530 >> >>> These duplicate includes have been found with scripts/checkincludes.pl but >>> they have been removed manually to avoid removing false positives. >>> >>> Signed-off-by: Pravin Shedge >> >> Networking patches need to be sent to net...@vger.kernel.org >> >> Thank you. > > -- Adding net...@vger.kernel.org for reviewing networking patches. Doesn't work like that. You have to post the actual patch freshly to the netdev mailing list so that it gets properly queued in patchwork and can be reviewed. You can't just add netdev to the CC: in a reply to my email, that doesn't do any good at all.
Re: [PATCH] ptp: make PTP a menuconfig to ease disabling it all
On Sat, Dec 09, 2017 at 04:07:15PM +0100, Vincent Legoll wrote: > No need to get into the submenu to disable all PTP-related > config entries. > > This makes it easier to disable all PTP config options > without entering the submenu. It will also enable one > to see that en/dis-abled state from the outside menu. > > This is only intended to change menuconfig UI, not change > the config dependencies. NAK, you are introducing a new config option for no good reason. Sorry, Richard
Re: [PATCH] dmaengine: jz4740: disable/unprepare clk if probe fails
On Wed, Dec 06, 2017 at 02:28:27PM +0100, Tobias Jordan wrote: > in error path of jz4740_dma_probe(), call clk_disable_unprepare() to clean > up. > > Found by Linux Driver Verification project (linuxtesting.org). Applied, thanks -- ~Vinod
Re: [PATCH] dmaengine: timb_dma: fix spelling mistake: "Couldnt" -> "Couldn't"
On Fri, Dec 01, 2017 at 09:25:28AM +, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake in dev_err error message text. Applied, thanks -- ~Vinod
RE: [PATCH v2] usb: host: Implement workaround for Erratum A-009611
-Original Message- From: Felipe Balbi [mailto:felipe.ba...@linux.intel.com] Sent: Friday, December 08, 2017 6:44 PM To: Greg Kroah-Hartman ; Yinbo Zhu Cc: Mathias Nyman ; open list:DESIGNWARE USB3 DRD IP DRIVER ; open list:DESIGNWARE USB3 DRD IP DRIVER ; open list ; Xiaobo Xie ; Jerry Huang ; Ran Wang Subject: Re: [PATCH v2] usb: host: Implement workaround for Erratum A-009611 >Hi, >Greg Kroah-Hartman writes: > On Fri, Dec 08, 2017 at 05:49:41PM +0800, yinbo@nxp.com wrote: >> From: "yinbo.zhu" >> >> Description: This is a occasional problem where the software > > No need for a "Description:" word. That's just assumed here, right? I will remove "Description:" thanks. >> issues an End Transfer command while a USB transfer is in progress, >> resulting in the TxFIFO being flushed when the lower layer is >> waiting for data,causing the super speed (SS) transmit to get blocked. >> If the End Transfer command is issued on an IN endpoint to flush out >> the pending transfers when the same IN endpoint is doing transfers on >> the USB, then depending upon the timing of the End Transfer (and the >> resulting internal FIFO flush),the lower layer (U3PTL/U3MAC) could >> get stuck waiting for data indefinitely. This blocks the transmission >> path on the SS, and no DP/ACK/ERDY/DEVNOTIF packets can be sent from >> the device. >> Impact: If this issue happens and the transmission gets blocked, then >> the USB host aborts and resets/re-enumerates the device. >> This unblocks the transmitt engine and the device functions normally. >> >> Workaround: Software must wait for all existing TRBs to complete >> before issuing End transfer command. >> >> Configs Affected: >> LS1088-48A-R1.0, LS2081A-R1.1, LS2088-48A-R1.0, LS2088-48A-R1.1, >> LX2160-2120-2080A-R1. > > What are these Configs? That doesn't seem to match up with anything > that is in the kernel tree that I can see. These configs is soc information, I don't enable it on these platform dts. Although the erratum issue can't be reproduced. >> >> Signed-off-by: yinbo.zhu >> --- >> drivers/usb/dwc3/core.c | 3 +++ >> drivers/usb/dwc3/core.h | 3 +++ >> drivers/usb/dwc3/host.c | 3 +++ >> drivers/usb/host/xhci-plat.c | 4 >> drivers/usb/host/xhci.c | 24 ++-- >> drivers/usb/host/xhci.h | 1 + >> 6 files changed, 32 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index >> 5cb3f6795b0b..071e7cea8cbb 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -1106,6 +1106,9 @@ static void dwc3_get_properties(struct dwc3 >> *dwc) >> >> dwc->quirk_reverse_in_out = device_property_read_bool(dev, >> "snps,quirk_reverse_in_out"); >This was generated on vendor tree. This quirk doesn't exist in dwc3. Also, >update your tree and review MAINTAINERS file. It has been almost 2 years >since I left TI :-) >-- >Balbi Hi Balbi, The quirk that I had add it in dwc3. Your meaning is that I can't use quirk to enable or disable the erratum, isn't it? The tree is git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git, I had updated it. Thanks. Yinbo
Re: Linux 4.15-rc3 (uml + bpf_perf_event.h)
On 12/10/2017 06:08 PM, Linus Torvalds wrote: > Another week, another rc. > um (uml) won't build on i386 or x86_64: CC init/main.o In file included from ../include/linux/perf_event.h:18:0, from ../include/linux/trace_events.h:10, from ../include/trace/syscall.h:7, from ../include/linux/syscalls.h:82, from ../init/main.c:20: ../include/uapi/linux/bpf_perf_event.h:11:32: fatal error: asm/bpf_perf_event.h: No such file or directory #include ^ compilation terminated. ../scripts/Makefile.build:310: recipe for target 'init/main.o' failed Should that be ? -- ~Randy
Re: [PATCH][next] scsi: arcmsr: remove redundant check for secs < 0
Colin,
You are right. That's checking is redundant. secs is never be negative.
Thanks for your correction and patch.
Regards,
Ching
2017-12-09 8:34 GMT+08:00 Colin King :
> From: Colin Ian King
>
> The check for secs being less than zero is redundant for two reasons.
> Firstly, secs is unsigned so the check is always going to be false.
> Secondly, if secs was signed the proceeding calculation of secs is
> never going to be negative. Hence we can remove this redundant check
> and day and secs re-adjustment.
>
> Detected by static analysis with smatch:
> arcmsr_set_iop_datetime() warn: unsigned 'secs' is never less than zero.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/scsi/arcmsr/arcmsr_hba.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/scsi/arcmsr/arcmsr_hba.c
> b/drivers/scsi/arcmsr/arcmsr_hba.c
> index 0707a60bf5c0..e4258b69f4be 100644
> --- a/drivers/scsi/arcmsr/arcmsr_hba.c
> +++ b/drivers/scsi/arcmsr/arcmsr_hba.c
> @@ -3679,10 +3679,6 @@ static void arcmsr_set_iop_datetime(struct timer_list
> *t)
> secs = (u32)(tv.tv_sec - (sys_tz.tz_minuteswest * 60));
> days = secs / 86400;
> secs = secs - 86400 * days;
> - if (secs < 0) {
> - days = days - 1;
> - secs = secs + 86400;
> - }
> j = days / 146097;
> i = days - 146097 * j;
> a = i + 719468;
> --
> 2.14.1
>
RE: [PATCH v2] usb: host: Implement workaround for Erratum A-007463
-Original Message- From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org] Sent: Friday, December 08, 2017 6:18 PM To: Yinbo Zhu Cc: Felipe Balbi ; Mathias Nyman ; open list:DESIGNWARE USB3 DRD IP DRIVER ; open list:DESIGNWARE USB3 DRD IP DRIVER ; open list ; Xiaobo Xie ; Jerry Huang ; Ran Wang Subject: Re: [PATCH v2] usb: host: Implement workaround for Erratum A-007463 On Fri, Dec 08, 2017 at 05:49:40PM +0800, yinbo@nxp.com wrote: > From: "yinbo.zhu" >I need a "real name" here, I doubt you sign documents as: > "yinbo.zhu" >right? :) >Also, you sent 3 patches, yet no way to know what order to apply them in. >Please fix that up by sending a >patch series, properly numbered. >thanks, >greg k-h Hi Greg Kroah-Hartman, "Yinbo.zhu" is my email address prefix,and it is automatically generated through the git command. You can follow the order of patch A-007463 A-009611 A-009668 to apply it. Thanks Yinbo.
Re: [PATCH net-next] libbpf: add function to setup XDP
On 2017/12/09 23:43, Eric Leblond wrote:
> Most of the code is taken from set_link_xdp_fd() in bpf_load.c and
> slightly modified to be library compliant.
>
> Signed-off-by: Eric Leblond
...
> +int bpf_set_link_xdp_fd(int ifindex, int fd, __u32 flags)
...
> + for (nh = (struct nlmsghdr *)buf; NLMSG_OK(nh, len);
> + nh = NLMSG_NEXT(nh, len)) {
> + if (nh->nlmsg_pid != getpid()) {
Generally nlmsg_pid should not be compared with process id.
See man netlink and
https://github.com/iovisor/bcc/pull/1275/commits/69ce96a54c55960c8de3392061254c97b6306a6d
> + ret = -LIBBPF_ERRNO__WRNGPID;
> + goto cleanup;
> + }
--
Toshiaki Makita
Re: [PATCH v2 00/18] arm64: Unmap the kernel whilst running in userspace (KAISER)
Hi Will, I tested v2 patch series on Centriq2400 server platform successfully, no regression so far. And also we applied internal patches on top of the branch "kpti" and verified kaiser feature. Tested-by: Shanker Donthineni -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v4] mmap.2: MAP_FIXED updated documentation
On 12/10/2017 02:31 AM, Michal Hocko wrote: > On Tue 05-12-17 19:14:34, john.hubb...@gmail.com wrote: >> From: John Hubbard >> >> Previously, MAP_FIXED was "discouraged", due to portability >> issues with the fixed address. In fact, there are other, more >> serious issues. Also, alignment requirements were a bit vague. >> So: >> >> -- Expand the documentation to discuss the hazards in >>enough detail to allow avoiding them. >> >> -- Mention the upcoming MAP_FIXED_SAFE flag. >> >> -- Enhance the alignment requirement slightly. >> >> Some of the wording is lifted from Matthew Wilcox's review >> (the "Portability issues" section). The alignment requirements >> section uses Cyril Hrubis' wording, with light editing applied. >> >> Suggested-by: Matthew Wilcox >> Suggested-by: Cyril Hrubis >> Signed-off-by: John Hubbard > > Would you mind if I take this patch and resubmit it along with my > MAP_FIXED_SAFE (or whatever name I will end up with) next week? > > Acked-by: Michal Hocko Sure, that works for me. A tiny complication: I see that Michael Kerrisk has already applied the much smaller v2 of this patch (the one that "no longer discourages" the option, but that's all), as: ffa518803e14 mmap.2: MAP_FIXED is no longer discouraged so this one here will need to be adjusted slightly to merge gracefully. Let me know if you want me to respin, or if you want to handle the merge. thanks, -- John Hubbard NVIDIA
Re: [PATCH] checkpatch: don't require octal permissions for "0"
On Sun, 2017-12-10 at 15:04 +0100, Bartosz Golaszewski wrote:
> If the permission value is 0, don't raise the NON_OCTAL_PERMISSIONS
> error. There's no possibility of an error if there are no permissions.
>
> Suggested-by: Andy Shevchenko
> Signed-off-by: Bartosz Golaszewski
> ---
> scripts/checkpatch.pl | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> index 6b130a4116fa..ea98e298d3ac 100755
> --- a/scripts/checkpatch.pl
> +++ b/scripts/checkpatch.pl
> @@ -6321,7 +6321,7 @@ sub process {
> if ($stat =~ /$test/) {
> my $val = $1;
> $val = $6 if ($skip_args ne "");
> - if (($val =~ /^$Int$/ && $val !~
> /^$Octal$/) ||
> + if (($val ne "0" && $val =~ /^$Int$/ &&
> $val !~ /^$Octal$/) ||
> ($val =~ /^$Octal$/ && length($val)
> ne 4)) {
> ERROR("NON_OCTAL_PERMISSIONS",
> "Use 4 digit octal (0777)
> not decimal permissions\n" . "$here\n" . $stat_real);
perhaps
---
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 6b130a4116fa..950bbc0e6e3f 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -6321,7 +6321,8 @@ sub process {
if ($stat =~ /$test/) {
my $val = $1;
$val = $6 if ($skip_args ne "");
- if (($val =~ /^$Int$/ && $val !~
/^$Octal$/) ||
+ if ($func !~ /^module_param/ &&
+ ($val =~ /^$Int$/ && $val !~
/^$Octal$/) ||
($val =~ /^$Octal$/ && length($val)
ne 4)) {
ERROR("NON_OCTAL_PERMISSIONS",
"Use 4 digit octal (0777)
not decimal permissions\n" . "$here\n" . $stat_real);
Linux 4.15-rc3
Another week, another rc.
I'm not thrilled about how big the early 4.15 rc's are, but rc3 is
often the biggest rc because it's still fairly early in the
calming-down period, and yet people have had some time to start
finding problems. That said, this rc3 is big even by rc3 standards.
Not good.
Most of the changes by far are drivers (with a big chunk of it being
just syntactic changes for some doc warnings) with some perf tooling
updates also being noticeable. But there are changes all over: core
kernel and networking, kvm, arch updates and Documentation.
Anyway, I sincerely hope that things are really starting to calm down now.
Also, there's a known issue with x86 32-bit suspend/resume that I just
didn't get a good patch for in time for this rc. Soon.
Shortlog appended.
Linus
---
Aaro Koskinen (1):
staging: octeon-usb: use __delay() instead of cvmx_wait()
Adam Ford (2):
ARM: dts: logicpd-som-lv: Fix gpmc addresses for NAND and enet
ARM: dts: logicpd-somlv: Fix wl127x pinmux
Adrian Hunter (1):
perf intel-pt: Bring instruction decoder files into line with the kernel
Al Viro (3):
fix kcm_clone()
socketpair(): allocate descriptors first
make sock_alloc_file() do sock_release() on failures
Alex Bennée (5):
KVM: arm/arm64: debug: Introduce helper for single-step
kvm: arm64: handle single-stepping trapped instructions
kvm: arm64: handle single-step of userspace mmio instructions
kvm: arm64: handle single-step during SError exceptions
kvm: arm64: handle single-step of hyp emulated mmio instructions
Alex Deucher (2):
drm/amdgpu: add license to Makefiles
drm/amdgpu: add license to files where it was missing
Andi Kleen (1):
perf record: Fix -c/-F options for cpu event aliases
Andre Przywara (4):
KVM: arm/arm64: VGIC: extend !vgic_is_initialized guard
pinctrl: sunxi: Fix A80 interrupt pin bank
pinctrl: sunxi: Fix A64 UART mux value
pinctrl: sunxi: Disable strict mode for H5 driver
Andrei Vagin (1):
perf trace: Fix an exit code of trace__symbols_init
Andrew Honig (1):
KVM: VMX: remove I/O port 0x80 bypass on Intel hosts
Andrew Jones (1):
KVM: arm/arm64: kvm_arch_destroy_vm cleanups
Andrew Lunn (2):
net: dsa: mv88e6xxx: Fix interrupt masking on removal
net: dsa: mv88e6xxx: Unregister MDIO bus on error path
Andy Lutomirski (1):
x86/power: Fix some ordering bugs in __restore_processor_context()
Andy Shevchenko (3):
pinctrl: denverton: Fix UART2 RTS pin mode
iio: proximity: sx9500: Assign interrupt from GpioIo()
brcmfmac: Avoid build error with make W=1
Angelo Dureghello (1):
m68k/defconfig: fix stmark2 broken local compilation
Antoine Tenart (1):
net: mvpp2: fix the RSS table entry offset
Ard Biesheuvel (1):
kvm: arm: don't treat unavailable HYP mode as an error
Arend Van Spriel (1):
brcmfmac: change driver unbind order of the sdio function devices
Arnaldo Carvalho de Melo (16):
perf evlist: Set the correct idx when adding dummy events
perf record: Generate PERF_RECORD_{MMAP,COMM,EXEC} with --delay
perf evsel: Fix up leftover perf_evsel_stat usage via evsel->priv
perf script: Fix --per-event-dump for auxtrace synth evsels
perf machine: Guard against NULL in machine__exit()
perf evlist: Add helper to check if attr.exclude_kernel is set
in all evsels
perf report: Ignore kptr_restrict when not sampling the kernel
perf record: Ignore kptr_restrict when not sampling the kernel
perf top: Ignore kptr_restrict when not sampling the kernel
tools headers: Synchronize kernel ABI headers wrt SPDX tags
tools headers: Synchronize perf_event.h header
tools headers uapi: Synchronize drm/drm.h
tools headers: Synchronize drm/i915_drm.h
tools headers: Synchronize KVM arch ABI headers
tools headers: Synchronize prctl.h ABI header
tools headers: Syncronize mman.h ABI header
Arnaud Patard (1):
meson-gx-socinfo: Fix package id parsing
Arnd Bergmann (7):
ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssr
debugfs: fix debugfs_real_fops() build error
media: et8ek8: select V4L2_FWNODE
iio: stm32: fix adc/trigger link error
s390/dasd: remove 'struct timespec' usage
x86/vdso: Change time() prototype to match __vdso_time()
ARM: omap2: hide omap3_save_secure_ram on non-OMAP3 builds
Arvind Yadav (1):
bus: arm-ccn: constify attribute_group structures.
Bart Van Assche (1):
usb: gadget: allow to enable legacy drivers without USB_ETH
Bert Kenward (1):
sfc: pass valid pointers from efx_enqueue_unwind
Bjørn Mork (1):
usbnet: fix alignment for frames with no ethernet header
Boris Brezillon (1):
drm/vc4: Fix false positive WARN() backtrace on refcount_inc() usage
Branislav Radocaj (1):
net: ethernet: arc: fix error handling in emac_rockchip_probe
Br
Re: [PATCH] TC: Delete an error message for a failed memory allocation in tc_bus_add_devices()
On Sun, 2017-12-10 at 21:41 +, Maciej W. Rozycki wrote: > On Sun, 10 Dec 2017, SF Markus Elfring wrote: > > > Omit an extra message for a memory allocation failure in this function. > > > > This issue was detected by using the Coccinelle software. > > And the problem here is? Markus' terrible commit messages. Generically, any OOM via a malloc like call has a dump_stack() which shows a stack trace unless __GFP_NOWARN is used. So this message is generally unnecessary as the dump_stack() will show the tc_bus_add_devices function name and (now hashed) value of the function address. What will be different is the particular slot # of the tc_dev will no longer be shown. Really though, if there's an OOM on the init, there are larger problems and the system will be unusable.
