Re: [PATCH] MIPS: Loongson64: Drop 32-bit support for Loongson 2E/2F devices

[James Hogan]

On Tue, Dec 26, 2017 at 12:21:38PM +0800, Jiaxun Yang wrote:
> Make loongson64 a pure 64-bit mach.

Please expand to provide some rationale behind the change. Was 32-bit
support broken at runtime, or broken at build time, or are we simply no
longer interested in supporting it?

Cheers
James

> 
> Signed-off-by: Jiaxun Yang 
> ---
>  arch/mips/loongson64/Kconfig | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
> index 0d249fc3cfe9..a7d9a9241ac4 100644
> --- a/arch/mips/loongson64/Kconfig
> +++ b/arch/mips/loongson64/Kconfig
> @@ -17,7 +17,6 @@ config LEMOTE_FULOONG2E
>   select I8259
>   select ISA
>   select IRQ_MIPS_CPU
> - select SYS_SUPPORTS_32BIT_KERNEL
>   select SYS_SUPPORTS_64BIT_KERNEL
>   select SYS_SUPPORTS_LITTLE_ENDIAN
>   select SYS_SUPPORTS_HIGHMEM
> @@ -49,7 +48,6 @@ config LEMOTE_MACH2F
>   select ISA
>   select SYS_HAS_CPU_LOONGSON2F
>   select SYS_HAS_EARLY_PRINTK
> - select SYS_SUPPORTS_32BIT_KERNEL
>   select SYS_SUPPORTS_64BIT_KERNEL
>   select SYS_SUPPORTS_HIGHMEM
>   select SYS_SUPPORTS_LITTLE_ENDIAN
> -- 
> 2.15.1
> 


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Re: [PATCH 3/3] pinctrl: rockchip: Fix a typo in four comment lines

[Linus Walleij]

On Sat, Dec 23, 2017 at 10:42 PM, SF Markus Elfring
 wrote:

> From: Markus Elfring 
> Date: Sat, 23 Dec 2017 22:22:54 +0100
>
> Adjust words in these descriptions.
>
> Signed-off-by: Markus Elfring 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH 2/3] pinctrl: rockchip: Improve a size determination in rockchip_pinctrl_probe()

[Linus Walleij]

On Sat, Dec 23, 2017 at 10:40 PM, SF Markus Elfring
 wrote:

> From: Markus Elfring 
> Date: Sat, 23 Dec 2017 22:07:30 +0100
>
> Replace the specification of a data structure by a pointer dereference
> as the parameter for the operator "sizeof" to make the corresponding size
> determination a bit safer according to the Linux coding style convention.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH 1/3] pinctrl: rockchip: Delete error messages for a failed memory allocation in two functions

[Linus Walleij]

On Sat, Dec 23, 2017 at 10:38 PM, SF Markus Elfring
 wrote:

> From: Markus Elfring 
> Date: Sat, 23 Dec 2017 22:02:47 +0100
>
> Omit extra messages for a memory allocation failure in these functions.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH] pinctrl: palmas: Delete an error message for a failed memory allocation in palmas_pinctrl_probe()

[Linus Walleij]

On Sat, Dec 23, 2017 at 9:30 PM, SF Markus Elfring
 wrote:

> From: Markus Elfring 
> Date: Sat, 23 Dec 2017 21:16:42 +0100
>
> Omit an extra message for a memory allocation failure in this function.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH] pinctrl: at91: Delete an error message for a failed memory allocation in at91_pinctrl_mux_mask()

[Linus Walleij]

On Sat, Dec 23, 2017 at 8:55 PM, SF Markus Elfring
 wrote:

> From: Markus Elfring 
> Date: Sat, 23 Dec 2017 20:44:27 +0100
>
> Omit an extra message for a memory allocation failure in this function.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH v3 18/27] pinctrl: replace devm_ioremap_nocache with devm_ioremap

[Linus Walleij]

On Sat, Dec 23, 2017 at 12:00 PM, Yisheng Xie  wrote:

> Default ioremap is ioremap_nocache, so devm_ioremap has the same
> function with devm_ioremap_nocache, which can just be killed to
> save the size of devres.o
>
> This patch is to use use devm_ioremap instead of devm_ioremap_nocache,
> which should not have any function change but prepare for killing
> devm_ioremap_nocache.
>
> Cc: Linus Walleij 
> Cc: linux-g...@vger.kernel.org
> Signed-off-by: Yisheng Xie 

Patch applied.

Yours,
Linus Walleij

Re: [PATCH v3 06/27] gpio: replace devm_ioremap_nocache with devm_ioremap

[Linus Walleij]

On Sat, Dec 23, 2017 at 11:58 AM, Yisheng Xie  wrote:

> Default ioremap is ioremap_nocache, so devm_ioremap has the same
> function with devm_ioremap_nocache, which can just be killed to
> save the size of devres.o
>
> This patch is to use use devm_ioremap instead of devm_ioremap_nocache,
> which should not have any function change but prepare for killing
> devm_ioremap_nocache.
>
> Cc: Linus Walleij 
> Cc: linux-g...@vger.kernel.org
> Signed-off-by: Yisheng Xie 

Patch applied.

Yours,
Linus Walleij

[PATCH v5 00/39] Andes(nds32) Linux Kernel Port

[Greentime Hu]

This is the 5th version patchset to add the Linux kernel port for Andes(nds32)
processors. Almost all of the feedbacks from v4 patchseries has been addressed.
Thanks to everyone who provided feedback on the previous version.


This patchset adds core architecture support to Linux for Andestech's
N13, N15, D15, N10, D10 processor cores.

Based on the 16/32-bit AndeStar RISC-like architecture, we designed the
configurable AndesCore series of embedded processor families. AndesCores
range from highly performance-efficient small-footprint cores for
microcontrollers and deeply-embedded applications to 1GHz+ cores running
Linux, covering general-purpose N-series cores for a wide range of computing
need, DSP-capable D-series cores for digital signal control,
instruction-extensible E-series cores for application-specific acceleration,
and secure S-series cores for best protection of the most valuable.

The patches are based on v4.14-rc8, and can also be found in the
following git tree:
  https://github.com/andestech/linux.git nds32-4.14-rc8-v5

The build script and toolchain repositories are able to be found here:
  https://github.com/andestech/build_script.git

Freely available instruction set and architecture overview documents can
be found on the following page:
  http://www.andestech.com/product.php?cls=9


Vincent Ren-Wei Chen and I will maintain this port. Thanks to everyone who
helped us and contributed to it. :) Any feedback is welcome.

Changes in v5:
 - Remove __NR__llseek  and sys_mmap()
 - Add a comment to explain that we don't have clocksource cycle counter in the 
CPU
 - Add volatile in iounmap()
 - Fix typo Featuretures to Features
 - Replace CPU_CACHE_NONALIASING with !CPU_CACHE_ALIASING
 - Fix a endian bug when we try to get val = of_get_property(cpu, 
"clock-frequency", NULL)
 - Add screen_info to fix the building error when CONFIG_ VGA_CONSOLE is enabled
 - Remove unnecessary msync()
 - Add depends on !64BIT || BROKEN for faraday Kconfig because the descriptor 
only supports 32bit
 - Add atl2c binding document
 - Remove unnecessary include headers
 - Fix a vector table bug. It placed wrong vector handlers for 2 exceptions.
 - Fix a vdso bug. It may encounter TLB multi-hit exception because we 
accidently set it as a global page.
 - Add proper isb and barrier after some cache operations
 - Fix a bug in system call restart flow. $r0 ~ $r5 does not be recovered 
before restarting system call
 - Fix the build errors for OpenRISC and SPARC because io.h changed.
 - Update ae3xx.dts to support atl2c.

Changes in v4:
 - Add atcpit100 timer driver due to it include vdso implementations and sent
   them together with nds32 may help reviewer to review.
 - Update ae3xx.dts for atcpit100 clock setting and remove vdso settings.
 - To get cycle counter register by timer driver instead of dts.
 - Use "depends on NDS32 || COMPILE_TEST" in atcpit100 driver because it is 
needed for nds32 vdso
 - Update defconfig becasue kconfig rename from CONFIG_CLKSRC_ATCPIT100 to 
CONFIG_TIMER_ATCPIT100
 - Remove ag101p.dts because we are not yet ready for ag101p platform.
 - Update copyright style to SPDX-License-Identifier
 - Include  instead of 
 - Add local_irq_save()/local_irq_restore() to protect SR_TLB_VPN in 
update_mmu_cache().
 - Update cpu_dcache_inval_all implementation to make sure all level cache are 
writeback.

Changes in v3:
 - Use arch's io.h instead of generic one
 - Add andestech-boards binding document
 - Update nds32/cpus.txt binding document
 - Remove atcpit100 timer drivers
 - Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
 - make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
 - Add cpu type to select HWZOL/CPU_CACHE_ALIASING
 - Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
 - Remove bootarg from device tree script
 - Update ag101p.dts and ae3xx.dts for correct board name.
 - Clear and simplify defconfig
 - Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of 
__raw_readl/__raw_writel for endian save
 - Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use 
the generic ones
 - Refine devicetree.c
 - Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
 - Refine irqchip/irq-ativic32.c implementations
 - Add COMPILE_TEST in drivers/net/ethernet/faraday/Kconfig
 - Refine cache operations
 - Add CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
 - Fix ZERO_PAGE define
 - Remove SA_RESTORER
 - Remove uapi/asm/signal.h
 - Redefine user_pt_regs
 - Remove spinlock.h
 - Remove __ARCH_WANT_RENAMEAT and __ARCH_WANT_SYSCALL_OFF_T from unistd.h
 - Remove set_fs(USER_DS) because flush_old_exec() will do this setting
 - Replace in_atomic() with faulthandler_disabled()
 - Add barrier.h
 - Select COMMON_CLK
 - Add clk_pll in dts
 - Add of_clk_init() in arch/nds32/kernel/time.c

Changes in v2:
 - Set GENERIC_CALIBRATE_DELAY default n
 - Add earlycon support
 - Remove earlyprintk
 - Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
 - Refine unalignment access exception handler
 -

[PATCH v5 01/39] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

From: Greentime Hu 

It allows some architectures to use this generic macro instead of
defining theirs.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Acked-by: Arnd Bergmann 
---
 include/asm-generic/io.h |   18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3..7c6a39e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, 
size_t size,
 }
 #endif
 
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
 #ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
 #define ioremap_nocache ioremap_nocache
 static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
 {
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, 
size_t size)
 }
 #endif
 
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
 #ifdef CONFIG_HAS_IOPORT_MAP
 #ifndef CONFIG_GENERIC_IOMAP
 #ifndef ioport_map
-- 
1.7.9.5

[PATCH v5 05/39] nds32: Assembly macros and definitions

[Greentime Hu]

From: Greentime Hu 

This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/assembler.h |   39 ++
 arch/nds32/include/asm/bitfield.h  |  963 
 arch/nds32/include/asm/nds32.h |   83 
 arch/nds32/kernel/asm-offsets.c|   28 ++
 4 files changed, 1113 insertions(+)
 create mode 100644 arch/nds32/include/asm/assembler.h
 create mode 100644 arch/nds32/include/asm/bitfield.h
 create mode 100644 arch/nds32/include/asm/nds32.h
 create mode 100644 arch/nds32/kernel/asm-offsets.c

diff --git a/arch/nds32/include/asm/assembler.h 
b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 000..c385578
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+   setgie.d
+   dsb
+.endm
+
+.macro gie_enable
+   setgie.e
+   dsb
+.endm
+
+.macro gie_save oldpsw
+   mfsr \oldpsw, $ir0
+   setgie.d
+dsb
+.endm
+
+.macro gie_restore oldpsw
+   andi \oldpsw, \oldpsw, #0x1
+   beqz \oldpsw, 7001f
+   setgie.e
+   dsb
+7001:
+.endm
+
+
+#define USER(insn,  reg, addr, opr)\
+:  insn  reg, addr, opr;   \
+   .section __ex_table,"a";\
+   .align 3;   \
+   .long   b, 9001f;   \
+   .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h 
b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 000..c73f71d
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/**
+ * cr0: CPU_VER (CPU Version Register)
+ */
+#define CPU_VER_offCFGID   0   /* Minor configuration */
+#define CPU_VER_offREV 16  /* Revision of the CPU version */
+#define CPU_VER_offCPUID   24  /* Major CPU versions */
+
+#define CPU_VER_mskCFGID   ( 0x  << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF  << CPU_VER_offREV )
+#define CPU_VER_mskCPUID   ( 0xFF  << CPU_VER_offCPUID )
+
+/**
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ */
+#define ICM_CFG_offISET0   /* I-cache sets (# of cache 
lines) per way */
+#define ICM_CFG_offIWAY3   /* I-cache ways */
+#define ICM_CFG_offISZ 6   /* I-cache line size */
+#define ICM_CFG_offILCK9   /* I-cache locking support */
+#define ICM_CFG_offILMB10  /* On-chip ILM banks */
+#define ICM_CFG_offBSAV13  /* ILM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET( 0x7  << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY( 0x7  << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7  << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK( 0x1  << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB( 0x7  << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV( 0x3  << ICM_CFG_offBSAV )
+
+/**
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ */
+#define DCM_CFG_offDSET0   /* D-cache sets (# of cache 
lines) per way */
+#define DCM_CFG_offDWAY3   /* D-cache ways */
+#define DCM_CFG_offDSZ 6   /* D-cache line size */
+#define DCM_CFG_offDLCK9   /* D-cache locking support */
+#define DCM_CFG_offDLMB10  /* On-chip DLM banks */
+#define DCM_CFG_offBSAV13  /* DLM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET( 0x7  << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY( 0x7  << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7  << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK( 0x1  << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB( 0x7  << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV( 0x3  << DCM_CFG_offBSAV )
+
+/**
+ * cr3: MMU_CFG (MMU Configuration Register)
+ *

[PATCH v5 06/39] nds32: Kernel booting and initialization

[Greentime Hu]

From: Greentime Hu 

This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/kernel/head.S  |  188 ++
 arch/nds32/kernel/setup.c |  387 +
 2 files changed, 575 insertions(+)
 create mode 100644 arch/nds32/kernel/head.S
 create mode 100644 arch/nds32/kernel/setup.c

diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 000..71f57bd
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+   .globl  swapper_pg_dir
+   .equswapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+   .section ".head.text", "ax"
+   .type   _stext, %function
+ENTRY(_stext)
+   setgie.d! Disable interrupt
+   isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+   mfsr$r0, $mr8
+   li  $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+   and $r0, $r0, $r1
+   mtsr$r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+   andi$r0,$r2,#0x3
+   li  $r10, 0
+   bne $r0, $r10, _nodtb
+   lwi $r0, [$r2]
+   li  $r1, OF_DT_MAGIC
+   bne $r0, $r1, _nodtb
+   move$r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+   sethi   $r4, hi20(swapper_pg_dir)
+   li  $p0, (PAGE_OFFSET - PHYS_OFFSET)
+   sub $r4, $r4, $p0
+   tlbop   FlushAll! invalidate TLB\n"
+   isb
+   mtsr$r4, $L1_PPTB   ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+   mfsr$r3, $MMU_CTL
+   li  $r0, #~MMU_CTL_mskNTC0
+   and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0))
+#else
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+   li  $r0, #MMU_CTL_UNA
+   or  $r3, $r3, $r0
+#endif
+   mtsr$r3, $MMU_CTL
+   isb
+
+/* set page size and size of kernel image */
+mfsr$r0, $MMU_CFG
+srli$r3, $r0, MMU_CFG_offfEPSZ
+zeb $r3, $r3
+bnez$r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+li  $r5, #SZ_4K ! Use 4KB page size
+#else
+li  $r5, #SZ_8K ! Use 8KB page size
+li  $r3, #1
+#endif
+mtsr$r3, $TLB_MISC
+b   _image_size_check
+
+_extra_page_size_support:! Use epzs pages size
+clz $r6, $r3
+subri   $r2, $r6, #31
+li  $r3, #1
+sll $r3, $r3, $r2
+/* MMU_CFG.EPSZ value -> meaning */
+mul $r5, $r3, $r3
+slli$r5, $r5, #14
+/* MMU_CFG.EPSZ  -> TLB_MISC.ACC_PSZ */
+addi$r3, $r2, #0x2
+mtsr$r3, $TLB_MISC
+
+_image_size_check:
+/* calculate the image maximum size accepted by TLB config */
+andi$r6, $r0, MMU_CFG_mskTBW
+andi$r0, $r0, MMU_CFG_mskTBS
+srli$r6, $r6, MMU_CFG_offTBW
+srli$r0, $r0, MMU_CFG_offTBS
+/*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+li  $r2, 't'
+beqz$r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+addi$r0, $r0, #0x2   ! MMU_CFG.TBS value -> meaning
+sll $r0, $r6, $r0! entries = k-way * n-set
+mul $r6, $r0, $r5! max size = entries * page size
+/* check kernel image size */
+la  $r3, (_end - PAGE_OFFSET)
+li  $r2, 's'
+bgt $r3, $r6, __error
+
+   li  $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+li  $r3, PAGE_OFFSET
+add $r6, $r6, $r3
+
+_tlb:
+   mtsr$r3, $TLB_VPN
+   dsb
+   tlbop   $r2, RWR
+   isb
+   add $r3, $r3, $r5
+   add $r2, $r2, $r5
+   bgt $r6, $r3, _tlb
+   mfsr$r3, $TLB_MISC  ! setup access page size
+   li  $r2, #~0xf
+   and $r3, $r3, $r2
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+  

[PATCH v5 03/39] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

From: Greentime Hu 

It will be built failed if commit id: d25ea659 is selected. This patch
can fix this build error.

Signed-off-by: Greentime Hu 
---
 arch/sparc/include/asm/io_32.h |5 -
 arch/sparc/kernel/ioport.c |4 ++--
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89..df2dc17 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem 
*dst,
  * Bus number may be embedded in the higher bits of the physical address.
  * This is why we have no bus number argument to ioremap().
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y)   ioremap((X),(Y))
-#define ioremap_wc(X,Y)ioremap((X),(Y))
-#define ioremap_wt(X,Y)ioremap((X),(Y))
 void iounmap(volatile void __iomem *addr);
-
 /* Create a virtual mapping cookie for an IO port range */
 void __iomem *ioport_map(unsigned long port, unsigned int nr);
 void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80..3bcef9c 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
  *
  * Bus type is always zero on IIep.
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
char name[14];
 
sprintf(name, "phys_%08x", (u32)offset);
-   return _sparc_alloc_io(0, offset, size, name);
+   return _sparc_alloc_io(0, (unsigned long)offset, size, name);
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
1.7.9.5

[PATCH v5 08/39] nds32: MMU definitions

[Greentime Hu]

From: Greentime Hu 

This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It
also includes the 4KB/8KB page size configurations and pte operations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/fixmap.h   |   29 +++
 arch/nds32/include/asm/highmem.h  |   65 ++
 arch/nds32/include/asm/memory.h   |  105 ++
 arch/nds32/include/asm/mmu.h  |   12 ++
 arch/nds32/include/asm/page.h |   67 ++
 arch/nds32/include/asm/pgalloc.h  |   96 +
 arch/nds32/include/asm/pgtable.h  |  409 +
 arch/nds32/include/asm/shmparam.h |   19 ++
 8 files changed, 802 insertions(+)
 create mode 100644 arch/nds32/include/asm/fixmap.h
 create mode 100644 arch/nds32/include/asm/highmem.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/mmu.h
 create mode 100644 arch/nds32/include/asm/page.h
 create mode 100644 arch/nds32/include/asm/pgalloc.h
 create mode 100644 arch/nds32/include/asm/pgtable.h
 create mode 100644 arch/nds32/include/asm/shmparam.h

diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index 000..0e60e15
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include 
+#include 
+#endif
+
+enum fixed_addresses {
+   FIX_HOLE,
+   FIX_KMAP_RESERVED,
+   FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+   FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+   FIX_EARLYCON_MEM_BASE,
+   __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE   ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START  (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include 
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
new file mode 100644
index 000..425d546
--- /dev/null
+++ b/arch/nds32/include/asm/highmem.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * Ordering is (from lower to higher memory addresses):
+ *
+ * high_memory
+ * Persistent kmap area
+ * PKMAP_BASE
+ * fixed_addresses
+ * FIXADDR_START
+ * FIXADDR_TOP
+ * Vmalloc area
+ * VMALLOC_START
+ * VMALLOC_END
+ */
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
+#define LAST_PKMAP PTRS_PER_PTE
+#define LAST_PKMAP_MASK(LAST_PKMAP - 1)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define kmap_prot  PAGE_KERNEL
+
+static inline void flush_cache_kmaps(void)
+{
+   cpu_dcache_wbinval_all();
+}
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void kmap_init(void);
+
+/*
+ * The following functions are already defined by 
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page);
+extern void __kunmap_atomic(void *kvaddr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 000..60efc72
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include 
+#include 
+
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus  __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt  __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE  ((CONFIG_PAGE_OFFSET) - (SZ_32M))
+#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_32M)
+#define PAGE

[PATCH v5 12/39] nds32: Process management

[Greentime Hu]

From: Greentime Hu 

This patch includes copy_thread(), start_thread() implementation and cpu_context
structure definition. nds32 uses $r25 to get current task_struct.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/current.h |   12 ++
 arch/nds32/include/asm/processor.h   |  102 +
 arch/nds32/include/asm/thread_info.h |   78 +
 arch/nds32/kernel/process.c  |  204 ++
 4 files changed, 396 insertions(+)
 create mode 100644 arch/nds32/include/asm/current.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/thread_info.h
 create mode 100644 arch/nds32/kernel/process.c

diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h
new file mode 100644
index 000..b4dcd22
--- /dev/null
+++ b/arch/nds32/include/asm/current.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_CURRENT_H
+#define _ASM_NDS32_CURRENT_H
+
+#ifndef __ASSEMBLY__
+register struct task_struct *current asm("$r25");
+#endif /* __ASSEMBLY__ */
+#define tsk $r25
+
+#endif /* _ASM_NDS32_CURRENT_H */
diff --git a/arch/nds32/include/asm/processor.h 
b/arch/nds32/include/asm/processor.h
new file mode 100644
index 000..cad9b8c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PROCESSOR_H
+#define __ASM_NDS32_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include 
+#include 
+#include 
+
+#define KERNEL_STACK_SIZE  PAGE_SIZE
+#define STACK_TOP  TASK_SIZE
+#define STACK_TOP_MAX   TASK_SIZE
+
+struct cpu_context {
+   unsigned long r6;
+   unsigned long r7;
+   unsigned long r8;
+   unsigned long r9;
+   unsigned long r10;
+   unsigned long r11;
+   unsigned long r12;
+   unsigned long r13;
+   unsigned long r14;
+   unsigned long fp;
+   unsigned long pc;
+   unsigned long sp;
+};
+
+struct thread_struct {
+   struct cpu_context cpu_context; /* cpu context */
+   /* fault info */
+   unsigned long address;
+   unsigned long trap_no;
+   unsigned long error_code;
+};
+
+#define INIT_THREAD  { }
+
+#ifdef __NDS32_EB__
+#define PSW_DE PSW_mskBE
+#else
+#define PSW_DE 0x0
+#endif
+
+#ifdef CONFIG_WBNA
+#define PSW_valWBNAPSW_mskWBNA
+#else
+#define PSW_valWBNA0x0
+#endif
+
+#ifdef CONFIG_HWZOL
+#definePSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT 
| PSW_mskIT | PSW_DE | PSW_mskGIE)
+#else
+#definePSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT 
| PSW_DE | PSW_mskGIE)
+#endif
+
+#define start_thread(regs,pc,stack)\
+({ \
+   memzero(regs, sizeof(struct pt_regs));  \
+   regs->ipsw = PSW_valINIT;   \
+   regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE 
| PSW_SYSTEM | PSW_INTL_1); \
+   regs->ipc = pc; \
+   regs->sp = stack;   \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)   do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()barrier()
+
+#define task_pt_regs(task) \
+   ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+   - 8) - 1)
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk)  instruction_pointer(task_pt_regs(tsk))
+#define KSTK_ESP(tsk)  user_stack_pointer(task_pt_regs(tsk))
+
+#endif
+
+#endif /* __ASM_NDS32_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/thread_info.h 
b/arch/nds32/include/asm/thread_info.h
new file mode 100644
index 000..818e769
--- /dev/null
+++ b/arch/nds32/include/asm/thread_info.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_THREAD_INFO_H
+#define __ASM_NDS32_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define THREAD_SIZE_ORDER  (1)
+#define THREAD_SIZE(PAGE_SIZE << THREAD_SIZE_ORDER)
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+#include 
+#include 
+
+typedef unsigned long mm_segment_t;
+
+/*
+ * low level task data that entry.S needs immediate access to.
+ * __switch_to() assumes cpu_context follows immediately after cpu_domain.
+ *

Re: [RFC PATCH 1/4] rtc: Introduce one interface to save the RTC hardware time range

[Baolin Wang]

Hi Alexandre,

On 2 January 2018 at 15:47, Alexandre Belloni
 wrote:
> Hi Baolin,
>
> Could you have a look at
> https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git/commit/?h=rtc-ranges
>
> My approach has multiple advantages as it works for 64-bit counters and
> the range can be updated at runtime.

Ah, I missed your approach. I will look at it. Thanks.

-- 
Baolin.wang
Best Regards

[PATCH v5 14/39] nds32: Atomic operations

[Greentime Hu]

From: Greentime Hu 

This patch includes the atomic and futex operations. Many atomic operations use
the load-lock word(llw) and store-condition word(scw) operations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/barrier.h |   15 ++
 arch/nds32/include/asm/futex.h   |  103 ++
 2 files changed, 118 insertions(+)
 create mode 100644 arch/nds32/include/asm/barrier.h
 create mode 100644 arch/nds32/include/asm/futex.h

diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h
new file mode 100644
index 000..faafc37
--- /dev/null
+++ b/arch/nds32/include/asm/barrier.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASM_BARRIER_H
+#define __NDS32_ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+#define mb()   asm volatile("msync all":::"memory")
+#define rmb()  asm volatile("msync all":::"memory")
+#define wmb()  asm volatile("msync store":::"memory")
+#include 
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __NDS32_ASM_BARRIER_H */
diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h
new file mode 100644
index 000..eab5e84
--- /dev/null
+++ b/arch/nds32/include/asm/futex.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_FUTEX_H__
+#define __NDS32_FUTEX_H__
+
+#include 
+#include 
+#include 
+
+#define __futex_atomic_ex_table(err_reg)   \
+   "   .pushsection __ex_table,\"a\"\n"\
+   "   .align  3\n"\
+   "   .long   1b, 4f\n"   \
+   "   .long   2b, 4f\n"   \
+   "   .popsection\n"  \
+   "   .pushsection .fixup,\"ax\"\n"   \
+   "4: move%0, " err_reg "\n"  \
+   "   j   3b\n"   \
+   "   .popsection"
+
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)\
+   smp_mb();   \
+   asm volatile(   \
+   "   movi$ta, #0\n"  \
+   "1: llw %1, [%2+$ta]\n" \
+   "   " insn "\n" \
+   "2: scw %0, [%2+$ta]\n" \
+   "   beqz%0, 1b\n"   \
+   "   movi%0, #0\n"   \
+   "3:\n"  \
+   __futex_atomic_ex_table("%4")   \
+   : "=&r" (ret), "=&r" (oldval)   \
+   : "r" (uaddr), "r" (oparg), "i" (-EFAULT)   \
+   : "cc", "memory")
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr,
+ u32 oldval, u32 newval)
+{
+   int ret = 0;
+   u32 val, tmp, flags;
+
+   if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+   return -EFAULT;
+
+   smp_mb();
+   asm volatile ("   movi$ta, #0\n"
+ "1: llw %1, [%6 + $ta]\n"
+ "   sub %3, %1, %4\n"
+ "   cmovz   %2, %5, %3\n"
+ "   cmovn   %2, %1, %3\n"
+ "2: scw %2, [%6 + $ta]\n"
+ "   beqz%2, 1b\n"
+ "3:\n   " __futex_atomic_ex_table("%7")
+ :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags)
+ :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT)
+ :"$ta", "memory");
+   smp_mb();
+
+   *uval = val;
+   return ret;
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+   int oldval = 0, ret;
+
+
+   pagefault_disable();
+   switch (op) {
+   case FUTEX_OP_SET:
+   __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_ADD:
+   __futex_atomic_op("add  %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_OR:
+   __futex_atomic_op("or   %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_ANDN:
+   __futex_atomic_op("and  %0, %1, %3", ret, oldval, tmp, uaddr,
+ ~oparg);
+   break;
+   case FUTEX_OP_XOR:
+   __futex_atomic_op("xor  %0, %1, %3", ret, oldval, tmp, uaddr,
+  

[PATCH v5 17/39] nds32: ELF definitions

[Greentime Hu]

From: Greentime Hu 

This patch adds definitions for the ELF format, relocation types, vdso
locations and EXEC_PAGESIZE.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/elf.h |  179 ++
 arch/nds32/include/uapi/asm/auxvec.h |   12 +++
 arch/nds32/include/uapi/asm/param.h  |   11 +++
 3 files changed, 202 insertions(+)
 create mode 100644 arch/nds32/include/asm/elf.h
 create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
 create mode 100644 arch/nds32/include/uapi/asm/param.h

diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h
new file mode 100644
index 000..99203f1
--- /dev/null
+++ b/arch/nds32/include/asm/elf.h
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_ELF_H
+#define __ASMNDS32_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include 
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+extern unsigned int elf_hwcap;
+
+#define EM_NDS32   167
+
+#define R_NDS32_NONE   0
+#define R_NDS32_16_RELA19
+#define R_NDS32_32_RELA20
+#define R_NDS32_9_PCREL_RELA   22
+#define R_NDS32_15_PCREL_RELA  23
+#define R_NDS32_17_PCREL_RELA  24
+#define R_NDS32_25_PCREL_RELA  25
+#define R_NDS32_HI20_RELA  26
+#define R_NDS32_LO12S3_RELA27
+#define R_NDS32_LO12S2_RELA28
+#define R_NDS32_LO12S1_RELA29
+#define R_NDS32_LO12S0_RELA30
+#define R_NDS32_SDA15S3_RELA   31
+#define R_NDS32_SDA15S2_RELA   32
+#define R_NDS32_SDA15S1_RELA   33
+#define R_NDS32_SDA15S0_RELA   34
+#define R_NDS32_GOT20  37
+#define R_NDS32_25_PLTREL  38
+#define R_NDS32_COPY   39
+#define R_NDS32_GLOB_DAT   40
+#define R_NDS32_JMP_SLOT   41
+#define R_NDS32_RELATIVE   42
+#define R_NDS32_GOTOFF 43
+#define R_NDS32_GOTPC2044
+#define R_NDS32_GOT_HI20   45
+#define R_NDS32_GOT_LO12   46
+#define R_NDS32_GOTPC_HI20 47
+#define R_NDS32_GOTPC_LO12 48
+#define R_NDS32_GOTOFF_HI2049
+#define R_NDS32_GOTOFF_LO1250
+#define R_NDS32_INSN16 51
+#define R_NDS32_LABEL  52
+#define R_NDS32_LONGCALL1  53
+#define R_NDS32_LONGCALL2  54
+#define R_NDS32_LONGCALL3  55
+#define R_NDS32_LONGJUMP1  56
+#define R_NDS32_LONGJUMP2  57
+#define R_NDS32_LONGJUMP3  58
+#define R_NDS32_LOADSTORE  59
+#define R_NDS32_9_FIXED_RELA   60
+#define R_NDS32_15_FIXED_RELA  61
+#define R_NDS32_17_FIXED_RELA  62
+#define R_NDS32_25_FIXED_RELA  63
+#define R_NDS32_PLTREL_HI2064
+#define R_NDS32_PLTREL_LO1265
+#define R_NDS32_PLT_GOTREL_HI2066
+#define R_NDS32_PLT_GOTREL_LO1267
+#define R_NDS32_LO12S0_ORI_RELA72
+#define R_NDS32_DWARF2_OP1_RELA77
+#define R_NDS32_DWARF2_OP2_RELA78
+#define R_NDS32_DWARF2_LEB_RELA79
+#define R_NDS32_WORD_9_PCREL_RELA  94
+#define R_NDS32_LONGCALL4  107
+#define R_NDS32_RELA_NOP_MIX   192
+#define R_NDS32_RELA_NOP_MAX   255
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page is totally unused, we just cover the entire
+   range.  All of the addresses are rounded in such a way that an integral
+   number of pages is written.
+   STACK: We need the stack information in order to get a meaning

[PATCH v5 16/39] nds32: DMA mapping API

[Greentime Hu]

From: Greentime Hu 

This patch adds support for the DMA mapping API. It uses dma_map_ops for
flexibility.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/dma-mapping.h |   14 ++
 arch/nds32/kernel/dma.c  |  459 ++
 2 files changed, 473 insertions(+)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
 create mode 100644 arch/nds32/kernel/dma.c

diff --git a/arch/nds32/include/asm/dma-mapping.h 
b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index 000..2dd47d24
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef ASMNDS32_DMA_MAPPING_H
+#define ASMNDS32_DMA_MAPPING_H
+
+extern struct dma_map_ops nds32_dma_ops;
+
+static inline struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+   return &nds32_dma_ops;
+}
+
+#endif
diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c
new file mode 100644
index 000..9bd1dc7
--- /dev/null
+++ b/arch/nds32/kernel/dma.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * This is the page table (2MB) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte;
+static DEFINE_RAW_SPINLOCK(consistent_lock);
+
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ *  struct vm_struct {
+ *struct vm_region region;
+ *unsigned longflags;
+ *struct page  **pages;
+ *unsigned int nr_pages;
+ *unsigned longphys_addr;
+ *  };
+ *
+ * get_vm_area() would then call vm_region_alloc with an appropriate
+ * struct vm_region head (eg):
+ *
+ *  struct vm_region vmalloc_head = {
+ * .vm_list= LIST_HEAD_INIT(vmalloc_head.vm_list),
+ * .vm_start   = VMALLOC_START,
+ * .vm_end = VMALLOC_END,
+ *  };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vm_region_alloc().
+ */
+struct arch_vm_region {
+   struct list_head vm_list;
+   unsigned long vm_start;
+   unsigned long vm_end;
+   struct page *vm_pages;
+};
+
+static struct arch_vm_region consistent_head = {
+   .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
+   .vm_start = CONSISTENT_BASE,
+   .vm_end = CONSISTENT_END,
+};
+
+static struct arch_vm_region *vm_region_alloc(struct arch_vm_region *head,
+ size_t size, int gfp)
+{
+   unsigned long addr = head->vm_start, end = head->vm_end - size;
+   unsigned long flags;
+   struct arch_vm_region *c, *new;
+
+   new = kmalloc(sizeof(struct arch_vm_region), gfp);
+   if (!new)
+   goto out;
+
+   raw_spin_lock_irqsave(&consistent_lock, flags);
+
+   list_for_each_entry(c, &head->vm_list, vm_list) {
+   if ((addr + size) < addr)
+   goto nospc;
+   if ((addr + size) <= c->vm_start)
+   goto found;
+   addr = c->vm_end;
+   if (addr > end)
+   goto nospc;
+   }
+
+found:
+   /*
+* Insert this entry _before_ the one we found.
+*/
+   list_add_tail(&new->vm_list, &c->vm_list);
+   new->vm_start = addr;
+   new->vm_end = addr + size;
+
+   raw_spin_unlock_irqrestore(&consistent_lock, flags);
+   return new;
+
+nospc:
+   raw_spin_unlock_irqrestore(&consistent_lock, flags);
+   kfree(new);
+out:
+   return NULL;
+}
+
+static struct arch_vm_region *vm_region_find(struct arch_vm_region *head,
+unsigned long addr)
+{
+   struct arch_vm_region *c;
+
+   list_for_each_entry(c, &head->vm_list, vm_list) {
+   if (c->vm_start == addr)
+   goto out;
+   }
+   c = NULL;
+out:
+   return c;
+}
+
+/* FIXME: attrs is not used. */
+static void *nds32_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t * handle, gfp_t gfp,
+ unsigned long attrs)
+{
+   struct page *page;
+   struct arch_vm_region *c;
+   unsigned long order;
+   u64 mask = ~0ULL, limit;
+   pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
+
+   if (!consistent_pte) {
+   pr_err("%s: not initialized\n", __func__);
+   dump_stack();
+

Re: [PATCH -next] xen/pvcalls: use GFP_ATOMIC under spin lock

[Juergen Gross]

On 28/12/17 04:46, Wei Yongjun wrote:
> A spin lock is taken here so we should use GFP_ATOMIC.
> 
> Fixes: 9774c6cca266 ("xen/pvcalls: implement accept command")
> Signed-off-by: Wei Yongjun 

Reviewed-by: Juergen Gross 


Juergen

[PATCH v5 19/39] nds32: VDSO support

[Greentime Hu]

From: Greentime Hu 

This patch adds VDSO support. The VDSO code is currently used for
sys_rt_sigreturn() and optimised gettimeofday() (using the SoC timer counter).

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/vdso.h  |   24 +++
 arch/nds32/include/asm/vdso_datapage.h |   36 
 arch/nds32/include/asm/vdso_timer_info.h   |   14 ++
 arch/nds32/kernel/vdso.c   |  230 +++
 arch/nds32/kernel/vdso/Makefile|   82 +
 arch/nds32/kernel/vdso/datapage.S  |   21 +++
 arch/nds32/kernel/vdso/gen_vdso_offsets.sh |   15 ++
 arch/nds32/kernel/vdso/gettimeofday.c  |  271 
 arch/nds32/kernel/vdso/note.S  |   11 ++
 arch/nds32/kernel/vdso/sigreturn.S |   19 ++
 arch/nds32/kernel/vdso/vdso.S  |   18 ++
 arch/nds32/kernel/vdso/vdso.lds.S  |   76 
 12 files changed, 817 insertions(+)
 create mode 100644 arch/nds32/include/asm/vdso.h
 create mode 100644 arch/nds32/include/asm/vdso_datapage.h
 create mode 100644 arch/nds32/include/asm/vdso_timer_info.h
 create mode 100644 arch/nds32/kernel/vdso.c
 create mode 100644 arch/nds32/kernel/vdso/Makefile
 create mode 100644 arch/nds32/kernel/vdso/datapage.S
 create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh
 create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c
 create mode 100644 arch/nds32/kernel/vdso/note.S
 create mode 100644 arch/nds32/kernel/vdso/sigreturn.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S

diff --git a/arch/nds32/include/asm/vdso.h b/arch/nds32/include/asm/vdso.h
new file mode 100644
index 000..af2c6af
--- /dev/null
+++ b/arch/nds32/include/asm/vdso.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include 
+
+#define VDSO_SYMBOL(base, name)
   \
+({\
+   (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \
+})
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/nds32/include/asm/vdso_datapage.h 
b/arch/nds32/include/asm/vdso_datapage.h
new file mode 100644
index 000..79db5a1
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_datapage.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+#ifndef __ASM_VDSO_DATAPAGE_H
+#define __ASM_VDSO_DATAPAGE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct vdso_data {
+   bool cycle_count_down;  /* timer cyclye counter is decrease with time */
+   u32 cycle_count_offset; /* offset of timer cycle counter register */
+   u32 seq_count;  /* sequence count - odd during updates */
+   u32 xtime_coarse_sec;   /* coarse time */
+   u32 xtime_coarse_nsec;
+
+   u32 wtm_clock_sec;  /* wall to monotonic offset */
+   u32 wtm_clock_nsec;
+   u32 xtime_clock_sec;/* CLOCK_REALTIME - seconds */
+   u32 cs_mult;/* clocksource multiplier */
+   u32 cs_shift;   /* Cycle to nanosecond divisor (power of two) */
+
+   u64 cs_cycle_last;  /* last cycle value */
+   u64 cs_mask;/* clocksource mask */
+
+   u64 xtime_clock_nsec;   /* CLOCK_REALTIME sub-ns base */
+   u32 tz_minuteswest; /* timezone info for gettimeofday(2) */
+   u32 tz_dsttime;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_DATAPAGE_H */
diff --git a/arch/nds32/include/asm/vdso_timer_info.h 
b/arch/nds32/include/asm/vdso_timer_info.h
new file mode 100644
index 000..50ba117
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_timer_info.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+extern struct timer_info_t timer_info;
+#define EMPTY_VALUE ~(0UL)
+#define EMPTY_TIMER_MAPPING EMPTY_VALUE
+#define EMPTY_REG_OFFSET EMPTY_VALUE
+
+struct timer_info_t
+{
+   bool cycle_count_down;
+   unsigned long mapping_base;
+   unsigned long cycle_count_reg_offset;
+};
diff --git a/arch/nds32/kernel/vdso.c b/arch/nds32/kernel/vdso.c
new file mode 100644
index 000..f1198d7
--- /dev/null
+++ b/arch/nds32/kernel/vdso.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+extern struct cache_info L1_cache_info[2];
+extern char vdso_start, vdso

[PATCH v5 21/39] nds32: Library functions

[Greentime Hu]

From: Greentime Hu 

This patch add support for various library functions.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/string.h  |   17 +++
 arch/nds32/include/asm/swab.h|   35 +
 arch/nds32/include/asm/uaccess.h |  283 ++
 arch/nds32/kernel/nds32_ksyms.c  |   31 +
 arch/nds32/lib/Makefile  |3 +
 arch/nds32/lib/clear_user.S  |   42 ++
 arch/nds32/lib/copy_from_user.S  |   45 ++
 arch/nds32/lib/copy_template.S   |   70 ++
 arch/nds32/lib/copy_to_user.S|   45 ++
 arch/nds32/lib/memcpy.S  |   30 
 arch/nds32/lib/memmove.S |   70 ++
 arch/nds32/lib/memset.S  |   33 +
 arch/nds32/lib/memzero.S |   18 +++
 13 files changed, 722 insertions(+)
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/swab.h
 create mode 100644 arch/nds32/include/asm/uaccess.h
 create mode 100644 arch/nds32/kernel/nds32_ksyms.c
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/clear_user.S
 create mode 100644 arch/nds32/lib/copy_from_user.S
 create mode 100644 arch/nds32/lib/copy_template.S
 create mode 100644 arch/nds32/lib/copy_to_user.S
 create mode 100644 arch/nds32/lib/memcpy.S
 create mode 100644 arch/nds32/lib/memmove.S
 create mode 100644 arch/nds32/lib/memset.S
 create mode 100644 arch/nds32/lib/memzero.S

diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 000..179272c
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_STRING_H
+#define __ASM_NDS32_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+extern void *memzero(void *ptr, __kernel_size_t n);
+#endif
diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h
new file mode 100644
index 000..e01a755
--- /dev/null
+++ b/arch/nds32/include/asm/swab.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_SWAB_H__
+#define __NDS32_SWAB_H__
+
+#include 
+#include 
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+   __asm__("wsbh   %0, %0\n\t" /* word swap byte within halfword */
+   "rotri  %0, %0, #16\n"
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+   __asm__("wsbh   %0, %0\n"   /* word swap byte within halfword */
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+#define __arch_swab32(x) ___arch__swab32(x)
+#define __arch_swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __NDS32_SWAB_H__ */
diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h
new file mode 100644
index 000..18a009f
--- /dev/null
+++ b/arch/nds32/include/asm/uaccess.h
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMANDES_UACCESS_H
+#define _ASMANDES_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VERIFY_READ0
+#define VERIFY_WRITE   1
+
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+   unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#define KERNEL_DS  ((mm_segment_t) { ~0UL })
+#define USER_DS((mm_segment_t) {TASK_SIZE - 1})
+
+#define get_ds()   (KERNEL_DS)
+#define get_fs()   (current_thread_info()->addr_limit)
+#define user_addr_max  get_fs
+
+static inline void set_fs(mm_segment_t fs)
+{
+   current_thread_info()->addr_limit = fs;
+}
+
+#define segment_eq(a, b)((a) == (b))
+
+#define __range_ok(addr, size) (size <= get_fs() && addr <= (get_fs() -size))
+
+#define access_ok(type, addr, size

[PATCH v5 23/39] nds32: L2 cache support

[Greentime Hu]

From: Greentime Hu 

This patch adds L2 cache support.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/l2_cache.h |  137 +
 arch/nds32/kernel/atl2c.c |   64 +
 2 files changed, 201 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000..37dd5ef
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include 
+#include 
+#include 
+
+#define L2C_R_REG(offset)   readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value)writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY()\
+do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & 
L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+   return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsigned long L2_CACHE_WAY(void)
+{
+   return 1 +
+   ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+L2_CA_CONF_offL2WAY);
+}
+
+static inline unsigned long L2_CACHE_LINE_SIZE(void)
+{
+
+

[PATCH v5 25/39] nds32: Generic timers support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for timer.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Linus Walleij 
---
 arch/nds32/kernel/time.c |   11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/nds32/kernel/time.c

diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c
new file mode 100644
index 000..ac9d78c
--- /dev/null
+++ b/arch/nds32/kernel/time.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+void __init time_init(void)
+{
+   of_clk_init(NULL);
+   timer_probe();
+}
-- 
1.7.9.5

[PATCH v5 27/39] nds32: Miscellaneous header files

[Greentime Hu]

From: Greentime Hu 

This patch introduces some miscellaneous header files.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/delay.h  |   39 +++
 arch/nds32/include/asm/linkage.h|   11 +
 arch/nds32/include/uapi/asm/byteorder.h |   13 +++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/nds32/include/asm/delay.h
 create mode 100644 arch/nds32/include/asm/linkage.h
 create mode 100644 arch/nds32/include/uapi/asm/byteorder.h

diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h
new file mode 100644
index 000..519ba97
--- /dev/null
+++ b/arch/nds32/include/asm/delay.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_DELAY_H__
+#define __NDS32_DELAY_H__
+
+#include 
+
+/* There is no clocksource cycle counter in the CPU. */
+static inline void __delay(unsigned long loops)
+{
+   __asm__ __volatile__(".align 2\n"
+"1:\n"
+"\taddi\t%0, %0, -1\n"
+"\tbgtz\t%0, 1b\n"
+:"=r"(loops)
+:"0"(loops));
+}
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+   usecs *= (unsigned long)(((0x8000ULL / (50 / HZ)) +
+ 0x8000ULL) >> 32);
+   usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
+   __delay(usecs);
+}
+
+#define udelay(usecs) __udelay((usecs), loops_per_jiffy)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS  1
+#elif HZ <= 200
+#define MAX_UDELAY_MS  5
+#else
+#define MAX_UDELAY_MS  (1000 / HZ)
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index 000..e708c8b
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 2
+#define __ALIGN_STR ".align 2"
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/byteorder.h 
b/arch/nds32/include/uapi/asm/byteorder.h
new file mode 100644
index 000..a23f6f3a
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/byteorder.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BYTEORDER_H__
+#define __NDS32_BYTEORDER_H__
+
+#ifdef __NDS32_EB__
+#include 
+#else
+#include 
+#endif
+
+#endif /* __NDS32_BYTEORDER_H__ */
-- 
1.7.9.5

[PATCH v5 26/39] nds32: Device tree support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for device tree.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/boot/dts/Makefile  |8 +
 arch/nds32/boot/dts/ae3xx.dts |   73 +
 arch/nds32/kernel/devtree.c   |   19 +++
 3 files changed, 100 insertions(+)
 create mode 100644 arch/nds32/boot/dts/Makefile
 create mode 100644 arch/nds32/boot/dts/ae3xx.dts
 create mode 100644 arch/nds32/kernel/devtree.c

diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index 000..d31faa8
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index 000..6b23d60
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,73 @@
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <&intc>;
+
+   chosen {
+   stdout-path = &serial0;
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x4000>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0>;
+   clock-frequency = <6000>;
+   next-level-cache = <&L2>;
+   };
+   };
+
+   L2: l2-cache@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
+   apb: clk@0 {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <3000>;
+   };
+
+
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   serial0: serial@f030 {
+   compatible = "andestech,uart16550", "ns16550a";
+   reg = <0xf030 0x1000>;
+   interrupts = <8>;
+   clock-frequency = <14745600>;
+   reg-shift = <2>;
+   reg-offset = <32>;
+   no-loopback-test = <1>;
+   };
+
+   timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <&apb>;
+   clock-names = "PCLK";
+   };
+
+   mac0: mac@e010 {
+   compatible = "andestech,atmac100";
+   reg = <0xe010 0x1000>;
+   interrupts = <18>;
+   };
+
+};
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index 000..bdce0fe
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+void __init early_init_devtree(void *params)
+{
+   if (!params || !early_init_dt_scan(params)) {
+   pr_crit("\n"
+   "Error: invalid device tree blob at (virtual address 
0x%p)\n"
+   "\nPlease check your bootloader.", params);
+
+   BUG_ON(1);
+   }
+
+   dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
-- 
1.7.9.5

[PATCH v5 30/39] MAINTAINERS: Add nds32

[Greentime Hu]

From: Greentime Hu 

Signed-off-by: Greentime Hu 
---
 MAINTAINERS |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f4e462..20284c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -857,6 +857,17 @@ X: drivers/iio/*/adjd*
 F: drivers/staging/iio/*/ad*
 F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
 
+ANDES ARCHITECTURE
+M: Greentime Hu 
+M: Vincent Chen 
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32
+F: 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32
+K: nds32
+N: nds32
+
 ANDROID CONFIG FRAGMENTS
 M: Rob Herring 
 S: Supported
-- 
1.7.9.5

[PATCH v5 31/39] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 CPU binding documents.

Signed-off-by: Vincent Chen 
Signed-off-by: Rick Chen 
Signed-off-by: Zong Li 
Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/nds32/cpus.txt |   37 ++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt

diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index 000..9a52937
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,37 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: should be one of:
+   "andestech,n13"
+   "andestech,n15"
+   "andestech,d15"
+   "andestech,n10"
+   "andestech,d10"
+   "andestech,nds32v3"
+   - device_type
+   Usage: required
+   Value type: 
+   Definition: must be "cpu"
+   - reg: Contains CPU index.
+   - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+   cpus {
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0x0>;
+   clock-frequency = <6000>
+   };
+   };
+};
-- 
1.7.9.5

[PATCH v5 32/39] dt-bindings: nds32 L2 cache controller Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu 
---
 Documentation/devicetree/bindings/nds32/atl2c.txt |   29 +
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt 
b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000..db9f7ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,29 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: "andestech,atl2c"
+   - reg : Physical base address and size of cache controller's memory 
mapped
+   - cache-unified : Specifies the cache is a unified cache.
+   - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+   L2: l2-cache@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
-- 
1.7.9.5

Re: [linux-sunxi] [PATCH v4 1/6] ARM: sunxi: h3/h5: add simplefb nodes

[Jernej Škrabec]

Hi,

Dne torek, 02. januar 2018 ob 09:14:37 CET je Icenowy Zheng napisal(a):
> 在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道：
> 
> > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng  wrote:
> > > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> > > 
> > > Add simplefb nodes for these outputs.
> > > 
> > > Signed-off-by: Icenowy Zheng 
> > > ---
> > > Changes in v4:
> > > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
> > > 
> > >   clocks that are needed to display framebuffer to the monitor.
> > 
> > Looks good. I assume you've tested this? It does continue to work
> > with the bus and DDC clocks disabled, right?
> 
> Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model
> A".

I think DDC clock is misnamed and according to DW HDMI binding should be named 
ISFR (clock for special function registers). I did few test tests when writing 
U-Boot driver and it has to be enabled all the time for driver to work 
correctly. I did few additional tests few days back - if only DDC clock is 
enabled and PLL video/HDMI clock disabled, DW HDMI registers are accessible.

I guess DDC clock in your case is not needed because controller is already 
configured correctly.

Best regards,
Jernej

Re: [linux-sunxi] [PATCH v4 5/6] arm64: allwinner: a64: add simplefb for A64 SoC

[Chen-Yu Tsai]

On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng  wrote:
> The A64 SoC features two display pipelines, one has a LCD output, the
> other has a HDMI output.
>
> Add support for simplefb for these pipelines on A64 SoC.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v4:
> - Dropped extra clocks.
> - Added labels to the SimpleFB device tree nodes as boards may have
>   extra regulator for display pipeline.
>
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index fb8ea7c414e1..d803c115d362 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -42,9 +42,11 @@
>   * OTHER DEALINGS IN THE SOFTWARE.
>   */
>
> +#include 
>  #include 
>  #include 
>  #include 
> +#include 

Nit: This isn't used anywhere. Please add it when DE2 DRM support is added.

ChenYu

[PATCH v5 33/39] dt-bindings: nds32 SoC Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 SoC(AE3XX and AG101P) binding documents.

Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/nds32/andestech-boards |   40 
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards

diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards 
b/Documentation/devicetree/bindings/nds32/andestech-boards
new file mode 100644
index 000..f5d7569
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <&intc>;
+};
+
+Andestech(nds32) AG101P Platform
+-
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+   compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ag101p";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <&intc>;
+};
-- 
1.7.9.5

[PATCH v5 36/39] net: faraday add nds32 support.

[Greentime Hu]

From: Greentime Hu 

This patch is used to support nds32 architecture to use these faraday
mac IP.

Signed-off-by: Greentime Hu 
---
 drivers/net/ethernet/faraday/Kconfig |8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/faraday/Kconfig 
b/drivers/net/ethernet/faraday/Kconfig
index 040c7f1..0fb8df6 100644
--- a/drivers/net/ethernet/faraday/Kconfig
+++ b/drivers/net/ethernet/faraday/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_FARADAY
bool "Faraday devices"
default y
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,7 +18,8 @@ if NET_VENDOR_FARADAY
 
 config FTMAC100
tristate "Faraday FTMAC100 10/100 Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select MII
---help---
  This driver supports the FTMAC100 10/100 Ethernet controller
@@ -27,7 +28,8 @@ config FTMAC100
 
 config FTGMAC100
tristate "Faraday FTGMAC100 Gigabit Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select PHYLIB
---help---
  This driver supports the FTGMAC100 Gigabit Ethernet controller
-- 
1.7.9.5

[PATCH v5 37/39] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

From: Rick Chen 

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Linus Walleij 
---
 drivers/clocksource/Kconfig   |7 +
 drivers/clocksource/Makefile  |1 +
 drivers/clocksource/timer-atcpit100.c |  255 +
 3 files changed, 263 insertions(+)
 create mode 100644 drivers/clocksource/timer-atcpit100.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cc60620..5bdf92c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -615,4 +615,11 @@ config CLKSRC_ST_LPC
  Enable this option to use the Low Power controller timer
  as clocksource.
 
+config TIMER_ATCPIT100
+   bool "Clocksource for AE3XX platform"
+   depends on NDS32 || COMPILE_TEST
+   depends on HAS_IOMEM
+   help
+ This option enables support for the Andestech AE3XX platform timers.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..74efe5f 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
 obj-$(CONFIG_H8300_TPU)+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_TIMER_ATCPIT100)  += timer-atcpit100.o
diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
new file mode 100644
index 000..0077fdb
--- /dev/null
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -0,0 +1,255 @@
+/*
+ *  Andestech ATCPIT100 Timer Device Driver Implementation
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "timer-of.h"
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c, i)((1name, timer_of_rate(&to), 300, 32,
+   clocksource_mmio_readl_down);
+
+   if (ret) {
+   pr_err("Failed to register clocksource\n");
+   return ret;
+   }
+
+ 

[PATCH v5 38/39] clocksource/drivers/atcpit100: VDSO support

[Greentime Hu]

From: Rick Chen 

VDSO needs real-time cycle count to ensure the time accuracy.
Unlike others, nds32 architecture does not define clock source,
hence VDSO needs atcpit100 offering real-time cycle count
to derive the correct time.

Signed-off-by: Vincent Chen 
Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
---
 drivers/clocksource/timer-atcpit100.c |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
index 0077fdb..9b2b628 100644
--- a/drivers/clocksource/timer-atcpit100.c
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -29,6 +29,9 @@
 #include 
 #include 
 #include "timer-of.h"
+#ifdef CONFIG_NDS32
+#include 
+#endif
 
 /*
  * Definition of register offsets
@@ -211,6 +214,17 @@ static u64 notrace atcpit100_timer_sched_read(void)
return ~readl(timer_of_base(&to) + CH1_CNT);
 }
 
+#ifdef CONFIG_NDS32
+static void fill_vdso_need_info(struct device_node *node)
+{
+   struct resource timer_res;
+   of_address_to_resource(node, 0, &timer_res);
+   timer_info.mapping_base = (unsigned long)timer_res.start;
+   timer_info.cycle_count_down = true;
+   timer_info.cycle_count_reg_offset = CH1_CNT;
+}
+#endif
+
 static int __init atcpit100_timer_init(struct device_node *node)
 {
int ret;
@@ -249,6 +263,10 @@ static int __init atcpit100_timer_init(struct device_node 
*node)
val = readl(base + INT_EN);
writel(val | CH0INT0EN, base + INT_EN);
 
+#ifdef CONFIG_NDS32
+   fill_vdso_need_info(node);
+#endif
+
return ret;
 }
 
-- 
1.7.9.5

[PATCH v5 39/39] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Greentime Hu]

From: Rick Chen 

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Acked-by: Rob Herring 
---
 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt

diff --git 
a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt 
b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 000..4c9ea59
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clocks   : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names  : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <&apb>;
+   clock-names = "PCLK";
+};
-- 
1.7.9.5

[PATCH v5 35/39] irqchip: Andestech Internal Vector Interrupt Controller driver

[Greentime Hu]

From: Greentime Hu 

This patch adds the Andestech Internal Vector Interrupt Controller
driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
http://www.andestech.com/product.php?cls=9

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Marc Zyngier 
---
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-ativic32.c |  107 
 2 files changed, 108 insertions(+)
 create mode 100644 drivers/irqchip/irq-ativic32.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b842dfd..201ca9f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o 
irq-aspeed-i2c-ic.o
 obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
 obj-$(CONFIG_QCOM_IRQ_COMBINER)+= qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)   += irq-uniphier-aidet.o
+obj-$(CONFIG_NDS32)+= irq-ativic32.o
diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c
new file mode 100644
index 000..f69a858
--- /dev/null
+++ b/drivers/irqchip/irq-ativic32.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void ativic32_ack_irq(struct irq_data *data)
+{
+   __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
+}
+
+static void ativic32_mask_irq(struct irq_data *data)
+{
+   unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
+   __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), 
NDS32_SR_INT_MASK2);
+}
+
+static void ativic32_unmask_irq(struct irq_data *data)
+{
+   unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
+   __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
+}
+
+static struct irq_chip ativic32_chip = {
+   .name = "ativic32",
+   .irq_ack = ativic32_ack_irq,
+   .irq_mask = ativic32_mask_irq,
+   .irq_unmask = ativic32_unmask_irq,
+};
+
+static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
+
+static struct irq_domain *root_domain;
+static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
+ irq_hw_number_t hw)
+{
+
+   unsigned long int_trigger_type;
+   u32 type;
+   struct irq_data *irq_data;
+   int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
+   irq_data = irq_get_irq_data(virq);
+   if (!irq_data)
+   return -EINVAL;
+
+   if (int_trigger_type & (BIT(hw))) {
+   irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
+   type = IRQ_TYPE_EDGE_RISING;
+   } else {
+   irq_set_chip_and_handler(virq, &ativic32_chip, 
handle_level_irq);
+   type = IRQ_TYPE_LEVEL_HIGH;
+   }
+
+   irqd_set_trigger_type(irq_data, type);
+   return 0;
+}
+
+static struct irq_domain_ops ativic32_ops = {
+   .map = ativic32_irq_domain_map,
+   .xlate = irq_domain_xlate_onecell
+};
+
+static irq_hw_number_t get_intr_src(void)
+{
+   return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> 
ITYPE_offVECTOR)
+   - NDS32_VECTOR_offINTERRUPT;
+}
+
+asmlinkage void asm_do_IRQ(struct pt_regs *regs)
+{
+   irq_hw_number_t hwirq = get_intr_src();
+   handle_domain_irq(root_domain, hwirq, regs);
+}
+
+int __init ativic32_init_irq(struct device_node *node, struct device_node 
*parent)
+{
+   unsigned long int_vec_base, nivic, nr_ints;
+
+   if (WARN(parent, "non-root ativic32 are not supported"))
+   return -EINVAL;
+
+   int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
+
+   if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
+   panic("Unable to use atcivic32 for this cpu.\n");
+
+   nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
+   if (nivic >= ARRAY_SIZE(nivic_map))
+   panic("The number of input for ativic32 is not supported.\n");
+
+   nr_ints = nivic_map[nivic];
+
+   root_domain = irq_domain_add_linear(node, nr_ints,
+   &ativic32_ops, NULL);
+
+   if (!root_domain)
+   panic("%s: unable to create IRQ domain\n", node->full_name);
+
+   return 0;
+}
+IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);
-- 
1.7.9.5

[PATCH v5 34/39] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller

[Greentime Hu]

From: Greentime Hu 

This patch adds an irqchip driver document for the Andestech Internal Vector
Interrupt Controller.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 .../interrupt-controller/andestech,ativic32.txt|   19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index 000..f4b4193
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain  "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
-- 
1.7.9.5

[PATCH v5 29/39] nds32: Build infrastructure

[Greentime Hu]

From: Greentime Hu 

This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building
an nds32 kernel.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/Kconfig |  108 
 arch/nds32/Kconfig.cpu |  161 
 arch/nds32/Makefile|   66 +++
 arch/nds32/boot/Makefile   |   15 
 arch/nds32/include/asm/Kbuild  |   54 
 arch/nds32/include/uapi/asm/Kbuild |   28 +++
 arch/nds32/kernel/Makefile |   23 ++
 arch/nds32/kernel/vmlinux.lds.S|   57 +
 arch/nds32/mm/Makefile |7 ++
 9 files changed, 519 insertions(+)
 create mode 100644 arch/nds32/Kconfig
 create mode 100644 arch/nds32/Kconfig.cpu
 create mode 100644 arch/nds32/Makefile
 create mode 100644 arch/nds32/boot/Makefile
 create mode 100644 arch/nds32/include/asm/Kbuild
 create mode 100644 arch/nds32/include/uapi/asm/Kbuild
 create mode 100644 arch/nds32/kernel/Makefile
 create mode 100644 arch/nds32/kernel/vmlinux.lds.S
 create mode 100644 arch/nds32/mm/Makefile

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index 000..c83506e
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,108 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+def_bool y
+   select ARCH_HAS_RAW_COPY_USER
+   select ARCH_WANT_FRAME_POINTERS if FTRACE
+   select ARCH_WANT_IPC_PARSE_VERSION
+   select CLKSRC_MMIO
+   select CLONE_BACKWARDS
+   select COMMON_CLK
+   select TIMER_OF
+   select FRAME_POINTER
+   select GENERIC_ATOMIC64
+   select GENERIC_CPU_DEVICES
+   select GENERIC_CLOCKEVENTS
+   select GENERIC_IRQ_CHIP
+   select GENERIC_IRQ_PROBE
+   select GENERIC_IRQ_SHOW
+   select GENERIC_STRNCPY_FROM_USER
+   select GENERIC_STRNLEN_USER
+   select GENERIC_TIME_VSYSCALL
+   select HANDLE_DOMAIN_IRQ
+   select HAVE_ARCH_TRACEHOOK
+   select HAVE_DEBUG_KMEMLEAK
+   select HAVE_MEMBLOCK
+   select HAVE_REGS_AND_STACK_ACCESS_API
+   select IRQ_DOMAIN
+   select LOCKDEP_SUPPORT
+   select MODULES_USE_ELF_RELA
+   select OF
+   select OF_EARLY_FLATTREE
+   select NO_BOOTMEM
+   select NO_IOPORT_MAP
+   select RTC_LIB
+   select THREAD_INFO_IN_TASK
+   help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+   def_bool n
+
+config GENERIC_CSUM
+def_bool y
+
+config GENERIC_HWEIGHT
+def_bool y
+
+config GENERIC_LOCKBREAK
+def_bool y
+   depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+   def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+   def_bool y
+
+config STACKTRACE_SUPPORT
+def_bool y
+
+config FIX_EARLYCON_MEM
+   def_bool y
+
+config PGTABLE_LEVELS
+   default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+   int
+   default 1
+
+config MMU
+def_bool y
+
+config NDS32_BUILTIN_DTB
+string "Builtin DTB"
+default ""
+   help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index 000..43e2f3f
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,161 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+   bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+   bool "hardware zero overhead loop support"
+   depends on CPU_D10 || CPU_D15
+   default n
+   help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+   bool "Aliasing cache"
+   depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+   default y
+   help
+ If this CPU is using VIPT data cache and its cache way size is larger
+ than page size, say Y. If it is using PIPT data cache, say N.
+
+ If unsure, say Y.
+
+choice
+   prompt "CPU type"
+   default CPU_V3
+config CPU_N15
+   bool "AndesCore N15"
+config CPU_N13
+   bool "And

[PATCH v5 20/39] nds32: Signal handling support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for signal handling.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/uapi/asm/sigcontext.h |   60 ++
 arch/nds32/kernel/signal.c   |  337 ++
 2 files changed, 397 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
 create mode 100644 arch/nds32/kernel/signal.c

diff --git a/arch/nds32/include/uapi/asm/sigcontext.h 
b/arch/nds32/include/uapi/asm/sigcontext.h
new file mode 100644
index 000..00567b2
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/sigcontext.h
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SIGCONTEXT_H
+#define _ASMNDS32_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.  Note: only add new entries
+ * to the end of the structure.
+ */
+
+struct zol_struct {
+   unsigned long nds32_lc; /* $LC */
+   unsigned long nds32_le; /* $LE */
+   unsigned long nds32_lb; /* $LB */
+};
+
+struct sigcontext {
+   unsigned long trap_no;
+   unsigned long error_code;
+   unsigned long oldmask;
+   unsigned long nds32_r0;
+   unsigned long nds32_r1;
+   unsigned long nds32_r2;
+   unsigned long nds32_r3;
+   unsigned long nds32_r4;
+   unsigned long nds32_r5;
+   unsigned long nds32_r6;
+   unsigned long nds32_r7;
+   unsigned long nds32_r8;
+   unsigned long nds32_r9;
+   unsigned long nds32_r10;
+   unsigned long nds32_r11;
+   unsigned long nds32_r12;
+   unsigned long nds32_r13;
+   unsigned long nds32_r14;
+   unsigned long nds32_r15;
+   unsigned long nds32_r16;
+   unsigned long nds32_r17;
+   unsigned long nds32_r18;
+   unsigned long nds32_r19;
+   unsigned long nds32_r20;
+   unsigned long nds32_r21;
+   unsigned long nds32_r22;
+   unsigned long nds32_r23;
+   unsigned long nds32_r24;
+   unsigned long nds32_r25;
+   unsigned long nds32_fp; /* $r28 */
+   unsigned long nds32_gp; /* $r29 */
+   unsigned long nds32_lp; /* $r30 */
+   unsigned long nds32_sp; /* $r31 */
+   unsigned long nds32_ipc;
+   unsigned long fault_address;
+   unsigned long used_math_flag;
+   /* FPU Registers */
+   struct zol_struct zol;
+};
+
+#endif
diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c
new file mode 100644
index 000..b6313dd
--- /dev/null
+++ b/arch/nds32/kernel/signal.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+struct rt_sigframe {
+   struct siginfo info;
+   struct ucontext uc;
+};
+
+static int restore_sigframe(struct pt_regs *regs,
+   struct rt_sigframe __user * sf)
+{
+   sigset_t set;
+   int err;
+
+   err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
+   if (err == 0) {
+   set_current_blocked(&set);
+   }
+
+   __get_user_error(regs->uregs[0], &sf->uc.uc_mcontext.nds32_r0, err);
+   __get_user_error(regs->uregs[1], &sf->uc.uc_mcontext.nds32_r1, err);
+   __get_user_error(regs->uregs[2], &sf->uc.uc_mcontext.nds32_r2, err);
+   __get_user_error(regs->uregs[3], &sf->uc.uc_mcontext.nds32_r3, err);
+   __get_user_error(regs->uregs[4], &sf->uc.uc_mcontext.nds32_r4, err);
+   __get_user_error(regs->uregs[5], &sf->uc.uc_mcontext.nds32_r5, err);
+   __get_user_error(regs->uregs[6], &sf->uc.uc_mcontext.nds32_r6, err);
+   __get_user_error(regs->uregs[7], &sf->uc.uc_mcontext.nds32_r7, err);
+   __get_user_error(regs->uregs[8], &sf->uc.uc_mcontext.nds32_r8, err);
+   __get_user_error(regs->uregs[9], &sf->uc.uc_mcontext.nds32_r9, err);
+   __get_user_error(regs->uregs[10], &sf->uc.uc_mcontext.nds32_r10, err);
+   __get_user_error(regs->uregs[11], &sf->uc.uc_mcontext.nds32_r11, err);
+   __get_user_error(regs->uregs[12], &sf->uc.uc_mcontext.nds32_r12, err);
+   __get_user_error(regs->uregs[13], &sf->uc.uc_mcontext.nds32_r13, err);
+   __get_user_error(regs->uregs[14], &sf->uc.uc_mcontext.nds32_r14, err);
+   __get_user_error(regs->uregs[15], &sf->uc.uc_mcontext.nds32_r15, err);
+   __get_user_error(regs->uregs[16], &sf->uc.uc_mcontext.nds32_r16, err);
+   __get_user_error(regs->uregs[17], &sf->uc.uc_mcontext.nds32_r17, err);
+   __get_user_error(regs->uregs[18], &sf->uc.uc_mcontext.nds32_r18, err);
+   __get_user_error(regs->uregs[19], &sf->uc.uc_mcontext.nds32_r19, err);
+   __get_user_error(regs->uregs[20], &sf->uc.uc_mcontext.nds32_r20, err);
+   __get_user_error(regs->uregs[21], &sf->uc.uc_mcontext.nds32_r21, err);
+   __get_user_error(regs->

[PATCH v5 22/39] nds32: Debugging support

[Greentime Hu]

From: Greentime Hu 

This patch adds ptrace support.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/uapi/asm/ptrace.h |   25 +++
 arch/nds32/kernel/ptrace.c   |  311 ++
 2 files changed, 336 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ptrace.c

diff --git a/arch/nds32/include/uapi/asm/ptrace.h 
b/arch/nds32/include/uapi/asm/ptrace.h
new file mode 100644
index 000..358c99e
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/ptrace.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __UAPI_ASM_NDS32_PTRACE_H
+#define __UAPI_ASM_NDS32_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose register.
+ */
+struct user_pt_regs {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+   long lb;
+   long le;
+   long lc;
+   long syscallno;
+};
+#endif
+#endif
diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c
new file mode 100644
index 000..0e18564
--- /dev/null
+++ b/arch/nds32/kernel/ptrace.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+enum nds32_regset {
+   REGSET_GPR,
+};
+
+static int gpr_get(struct task_struct *target,
+  const struct user_regset *regset,
+  unsigned int pos, unsigned int count,
+  void *kbuf, void __user * ubuf)
+{
+   struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs;
+   return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset 
*regset,
+  unsigned int pos, unsigned int count,
+  const void *kbuf, const void __user * ubuf)
+{
+   int err;
+   struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
+
+   err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
+   if (err)
+   return err;
+
+   task_pt_regs(target)->user_regs = newregs;
+   return 0;
+}
+
+static const struct user_regset nds32_regsets[] = {
+   [REGSET_GPR] = {
+   .core_note_type = NT_PRSTATUS,
+   .n = sizeof(struct user_pt_regs) / sizeof(u32),
+   .size = sizeof(u32),
+   .align = sizeof(u32),
+   .get = gpr_get,
+   .set = gpr_set}
+};
+
+static const struct user_regset_view nds32_user_view = {
+   .name = "nds32",.e_machine = EM_NDS32,
+   .regsets = nds32_regsets,.n = ARRAY_SIZE(nds32_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+   return &nds32_user_view;
+}
+
+/* get_user_reg()
+ *
+ * This routine will get a word off of the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline unsigned int get_user_reg(struct task_struct *task, int offset)
+{
+   return task_pt_regs(task)->uregs[offset];
+}
+
+/* put_user_reg()
+ *
+ * this routine will put a word on the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline int put_user_reg(struct task_struct *task, int offset, long data)
+{
+   struct pt_regs newregs, *regs = task_pt_regs(task);
+   int ret = -EINVAL;
+
+   newregs = *regs;
+   newregs.uregs[offset] = data;
+
+   if (valid_user_regs(&newregs)) {
+   regs->uregs[offset] = data;
+   ret = 0;
+   }
+
+   return ret;
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure the single step bit is not set.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+   user_disable_single_step(child);
+}
+
+static void fill_sigtrap_info(struct task_struct *tsk,
+ struct pt_regs *regs,
+ int error_code, int si_code, struct siginfo *info)
+{
+   tsk->thread.trap_no = ENTRY_DEBUG_RELATED;
+   tsk->thread.error_code = error_code;
+
+   memset(info, 0, sizeof(*info));
+   info->si_signo = SIGTRAP;
+   info->si_code = si_code;
+   info->si_addr = (void __user *)instruction_pointer(regs);
+}
+
+void user_single_step_siginfo(struct task_struct *tsk,
+ struct pt_regs *regs, struct siginfo *info)
+{
+   fill_sigtrap_info(tsk, regs, 0, TRAP_BRKPT, info);
+}
+
+/*
+ * Handle 

[PATCH v5 28/39] nds32: defconfig

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 defconfig.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/configs/defconfig |  108 ++
 1 file changed, 108 insertions(+)
 create mode 100644 arch/nds32/configs/defconfig

diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig
new file mode 100644
index 000..4d79d2db
--- /dev/null
+++ b/arch/nds32/configs/defconfig
@@ -0,0 +1,108 @@
+CONFIG_CROSS_COMPILE="nds32le-linux-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CACHE_L2 is not set
+CONFIG_VMSPLIT_3G_OPT=y
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_FTMAC100=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_TIMER_ATCPIT100=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_READABLE_ASM=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+# CONFIG_CRYPTO_HW is not set
-- 
1.7.9.5

[PATCH v5 18/39] nds32: System calls handling

[Greentime Hu]

From: Greentime Hu 

This patch adds support for system calls.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/syscall.h |  188 ++
 arch/nds32/include/asm/syscalls.h|   13 +++
 arch/nds32/include/asm/unistd.h  |6 ++
 arch/nds32/include/uapi/asm/unistd.h |   11 ++
 arch/nds32/kernel/ex-scall.S |  106 +++
 arch/nds32/kernel/sys_nds32.c|   50 +
 arch/nds32/kernel/syscall_table.c|   17 +++
 7 files changed, 391 insertions(+)
 create mode 100644 arch/nds32/include/asm/syscall.h
 create mode 100644 arch/nds32/include/asm/syscalls.h
 create mode 100644 arch/nds32/include/asm/unistd.h
 create mode 100644 arch/nds32/include/uapi/asm/unistd.h
 create mode 100644 arch/nds32/kernel/ex-scall.S
 create mode 100644 arch/nds32/kernel/sys_nds32.c
 create mode 100644 arch/nds32/kernel/syscall_table.c

diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h
new file mode 100644
index 000..f7e5e86
--- /dev/null
+++ b/arch/nds32/include/asm/syscall.h
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2008-2009 Red Hat, Inc.  All rights reserved.
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_SYSCALL_H
+#define _ASM_NDS32_SYSCALL_H   1
+
+#include 
+struct task_struct;
+struct pt_regs;
+
+/**
+ * syscall_get_nr - find what system call a task is executing
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * If @task is executing a system call or is at system call
+ * tracing about to attempt one, returns the system call number.
+ * If @task is not executing a system call, i.e. it's blocked
+ * inside the kernel for a fault or signal, returns -1.
+ *
+ * Note this returns int even on 64-bit machines.  Only 32 bits of
+ * system call number can be meaningful.  If the actual arch value
+ * is 64 bits, this truncates to 32 bits so 0x means -1.
+ *
+ * It's only valid to call this when @task is known to be blocked.
+ */
+int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->syscallno;
+}
+
+/**
+ * syscall_rollback - roll back registers after an aborted system call
+ * @task:  task of interest, must be in system call exit tracing
+ * @regs:  task_pt_regs() of @task
+ *
+ * It's only valid to call this when @task is stopped for system
+ * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT),
+ * after tracehook_report_syscall_entry() returned nonzero to prevent
+ * the system call from taking place.
+ *
+ * This rolls back the register state in @regs so it's as if the
+ * system call instruction was a no-op.  The registers containing
+ * the system call number and arguments are as they were before the
+ * system call instruction.  This may not be the same as what the
+ * register state looked like at system call entry tracing.
+ */
+void syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+   regs->uregs[0] = regs->orig_r0;
+}
+
+/**
+ * syscall_get_error - check result of traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns 0 if the system call succeeded, or -ERRORCODE if it failed.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+   unsigned long error = regs->uregs[0];
+   return IS_ERR_VALUE(error) ? error : 0;
+}
+
+/**
+ * syscall_get_return_value - get the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns the return value of the successful system call.
+ * This value is meaningless if syscall_get_error() returned nonzero.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->uregs[0];
+}
+
+/**
+ * syscall_set_return_value - change the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ * @error: negative error code, or zero to indicate success
+ * @val:   user return value if @error is zero
+ *
+ * This changes the results of the system call that user mode will see.
+ * If @error is zero, the user sees a successful system call with a
+ * return value of @val.  If @error is nonzero, it's a negated errno
+ * code; the user sees a failed system call with this errno code.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+void syscall_set_return_value(

[PATCH v5 24/39] nds32: Loadable modules

[Greentime Hu]

From: Greentime Hu 

This patch adds support for loadable modules.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/module.h |   11 ++
 arch/nds32/kernel/module.c  |  286 +++
 2 files changed, 297 insertions(+)
 create mode 100644 arch/nds32/include/asm/module.h
 create mode 100644 arch/nds32/kernel/module.c

diff --git a/arch/nds32/include/asm/module.h b/arch/nds32/include/asm/module.h
new file mode 100644
index 000..16cf9c7
--- /dev/null
+++ b/arch/nds32/include/asm/module.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_MODULE_H
+#define _ASM_NDS32_MODULE_H
+
+#include 
+
+#define MODULE_ARCH_VERMAGIC   "NDS32v3"
+
+#endif /* _ASM_NDS32_MODULE_H */
diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
new file mode 100644
index 000..714a6d6
--- /dev/null
+++ b/arch/nds32/kernel/module.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+#include 
+
+void *module_alloc(unsigned long size)
+{
+   return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+   GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+   __builtin_return_address(0));
+}
+
+void module_free(struct module *module, void *region)
+{
+   vfree(region);
+}
+
+int module_frob_arch_sections(Elf_Ehdr * hdr,
+ Elf_Shdr * sechdrs,
+ char *secstrings, struct module *mod)
+{
+   return 0;
+}
+
+void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"2:\n"
+"\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"2:\n"
+"\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+static inline int exceed_limit(int offset, unsigned int val_mask,
+  struct module *module, Elf32_Rela * rel,
+  unsigned int relindex, unsigned int reloc_order)
+{
+   int abs_off = offset < 0 ? ~offset : offset;
+
+   if (abs_off & (~val_mask)) {
+   pr_err("\n%s: relocation type %d out of range.\n"
+  "please rebuild the kernel module with gcc option 
\"-Wa,-mno-small-text\".\n",
+  module->name, ELF32_R_TYPE(rel->r_info));
+   pr_err("section %d reloc %d offset 0x%x relative 0x%x.\n",
+  relindex, reloc_order, rel->r_offset, offset);
+   return true;
+   }
+   return false;
+}
+
+#ifdef __NDS32_EL__
+#define NEED_SWAP 1
+#else
+#define NEED_SWAP 0
+#endif
+
+int
+apply_relocate_add(Elf32_Shdr * sechdrs, const char *strtab,
+  unsigned int symindex, unsigned int relindex,
+  struct module *module)
+{
+   Elf32_Shdr *symsec = sechdrs + symindex;

[PATCH v5 13/39] nds32: IRQ handling

[Greentime Hu]

From: Greentime Hu 

This patch includes irq related functions and irqchip_init().

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/irqflags.h |   36 
 arch/nds32/kernel/irq.c   |9 +
 2 files changed, 45 insertions(+)
 create mode 100644 arch/nds32/include/asm/irqflags.h
 create mode 100644 arch/nds32/kernel/irq.c

diff --git a/arch/nds32/include/asm/irqflags.h 
b/arch/nds32/include/asm/irqflags.h
new file mode 100644
index 000..2bfd00f
--- /dev/null
+++ b/arch/nds32/include/asm/irqflags.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+#define arch_local_irq_disable()   \
+   GIE_DISABLE();
+
+#define arch_local_irq_enable()\
+   GIE_ENABLE();
+static inline unsigned long arch_local_irq_save(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   GIE_DISABLE();
+   return flags;
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+   if(flags)
+   GIE_ENABLE();
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+   return !flags;
+}
diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c
new file mode 100644
index 000..6ff5a67
--- /dev/null
+++ b/arch/nds32/kernel/irq.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+
+void __init init_IRQ(void)
+{
+   irqchip_init();
+}
-- 
1.7.9.5

[PATCH v5 15/39] nds32: Device specific operations

[Greentime Hu]

From: Greentime Hu 

This patch introduces ioremap implementations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/io.h |   83 +++
 arch/nds32/mm/ioremap.c |   62 
 2 files changed, 145 insertions(+)
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/mm/ioremap.c

diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 000..966e71b
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_IO_H
+#define __ASM_NDS32_IO_H
+
+extern void iounmap(volatile void __iomem *addr);
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+   asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+   asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+   asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+   u8 val;
+
+   asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+   u16 val;
+
+   asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+   u32 val;
+
+   asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __iormb()   rmb()
+#define __iowmb()   wmb()
+
+#define mmiowb()__asm__ __volatile__ ("msync all" : : : "memory");
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+
+#define readb_relaxed(c)   ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)   ({ u16 __v = le16_to_cpu((__force 
__le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c)   ({ u32 __v = le32_to_cpu((__force 
__le32)__raw_readl(c)); __v; })
+#define writeb_relaxed(v,c)((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c)((void)__raw_writew((__force 
u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c)((void)__raw_writel((__force 
u32)cpu_to_le32(v),(c)))
+
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
+#define readb(c)   ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)   ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)   ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c)({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c)({ __iowmb(); writel_relaxed((v),(c)); })
+#include 
+#endif /* __ASM_NDS32_IO_H */
diff --git a/arch/nds32/mm/ioremap.c b/arch/nds32/mm/ioremap.c
new file mode 100644
index 000..690140b
--- /dev/null
+++ b/arch/nds32/mm/ioremap.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+ void *caller)
+{
+   struct vm_struct *area;
+   unsigned long addr, offset, last_addr;
+   pgprot_t prot;
+
+   /* Don't allow wraparound or zero size */
+   last_addr = phys_addr + size - 1;
+   if (!size || last_addr < phys_addr)
+   return NULL;
+
+   /*
+* Mappings have to be page-aligned
+*/
+   offset = phys_addr & ~PAGE_MASK;
+   phys_addr &= PAGE_MASK;
+   size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+   /*
+* Ok, go for it..
+*/
+   area = get_vm_area_caller(size, VM_IOREMAP, caller);
+   if (!area)
+   return NULL;
+
+   area->phys_addr = phys_addr;
+   addr = (unsigned long)area->addr;
+   prot = __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D |
+   _PAGE_G | _PAGE_C_DEV);
+   if (ioremap_page_range(addr, addr + size, phys_addr, prot)) {
+   vunmap((void *)addr);
+   return NULL;
+   }
+   return (__force void __iomem *)(offset + (char *)addr);
+
+}
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size)
+{
+   return __ioremap_caller(phys_addr, size,
+ 

[PATCH v5 04/39] earlycon: add reg-offset to physical address before mapping

[Greentime Hu]

From: Greentime Hu 

It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called

Signed-off-by: Greentime Hu 
---
 drivers/tty/serial/earlycon.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 98928f0..17dba0a 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id 
*match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
-   port->membase = earlycon_map(port->mapbase, SZ_4K);
 
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+   port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
-- 
1.7.9.5

[PATCH v5 11/39] nds32: Cache and TLB routines

[Greentime Hu]

From: Greentime Hu 

This patch contains cache and TLB maintenance functions.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/cache.h |   12 +
 arch/nds32/include/asm/cache_info.h|   13 +
 arch/nds32/include/asm/cacheflush.h|   44 +++
 arch/nds32/include/asm/mmu_context.h   |   68 
 arch/nds32/include/asm/proc-fns.h  |   44 +++
 arch/nds32/include/asm/tlb.h   |   28 ++
 arch/nds32/include/asm/tlbflush.h  |   47 +++
 arch/nds32/include/uapi/asm/cachectl.h |   14 +
 arch/nds32/kernel/cacheinfo.c  |   49 +++
 arch/nds32/mm/cacheflush.c |  322 +++
 arch/nds32/mm/proc.c   |  533 
 arch/nds32/mm/tlb.c|   50 +++
 12 files changed, 1224 insertions(+)
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/cache_info.h
 create mode 100644 arch/nds32/include/asm/cacheflush.h
 create mode 100644 arch/nds32/include/asm/mmu_context.h
 create mode 100644 arch/nds32/include/asm/proc-fns.h
 create mode 100644 arch/nds32/include/asm/tlb.h
 create mode 100644 arch/nds32/include/asm/tlbflush.h
 create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
 create mode 100644 arch/nds32/kernel/cacheinfo.c
 create mode 100644 arch/nds32/mm/cacheflush.c
 create mode 100644 arch/nds32/mm/proc.c
 create mode 100644 arch/nds32/mm/tlb.c

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 000..347db48
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHE_H__
+#define __NDS32_CACHE_H__
+
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+
+#define ARCH_DMA_MINALIGN   L1_CACHE_BYTES
+
+#endif /* __NDS32_CACHE_H__ */
diff --git a/arch/nds32/include/asm/cache_info.h 
b/arch/nds32/include/asm/cache_info.h
new file mode 100644
index 000..38ec458
--- /dev/null
+++ b/arch/nds32/include/asm/cache_info.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+struct cache_info {
+   unsigned char ways;
+   unsigned char line_size;
+   unsigned short sets;
+   unsigned short size;
+#if defined(CONFIG_CPU_CACHE_ALIASING)
+   unsigned short aliasing_num;
+   unsigned int aliasing_mask;
+#endif
+};
diff --git a/arch/nds32/include/asm/cacheflush.h 
b/arch/nds32/include/asm/cacheflush.h
new file mode 100644
index 000..7b9b20a
--- /dev/null
+++ b/arch/nds32/include/asm/cacheflush.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHEFLUSH_H__
+#define __NDS32_CACHEFLUSH_H__
+
+#include 
+
+#define PG_dcache_dirty PG_arch_1
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+void flush_cache_mm(struct mm_struct *mm);
+void flush_cache_dup_mm(struct mm_struct *mm);
+void flush_cache_range(struct vm_area_struct *vma,
+  unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn);
+void flush_cache_kmaps(void);
+void flush_cache_vmap(unsigned long start, unsigned long end);
+void flush_cache_vunmap(unsigned long start, unsigned long end);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+void flush_dcache_page(struct page *page);
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+  unsigned long vaddr, void *dst, void *src, int len);
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+unsigned long vaddr, void *dst, void *src, int len);
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+void flush_anon_page(struct vm_area_struct *vma,
+struct page *page, unsigned long vaddr);
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+void flush_kernel_dcache_page(struct page *page);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_dcache_mmap_lock(mapping)   spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) 
spin_unlock_irq(&(mapping)->tree_lock)
+
+#else
+#include 
+#endif
+
+#endif /* __NDS32_CACHEFLUSH_H__ */
diff --git a/arch/nds32/include/asm/mmu_context.h 
b/arch/nds32/include/asm/mmu_context.h
new file mode 100644
index 000..fd7d13c
--- /dev/null
+++ b/arch/nds32/include/asm/mmu_context.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MMU_CONTEXT_H
+#define __ASM_NDS32_MMU_CONTEXT_H
+
+#include 
+#include 
+#include 
+#include 
+
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+   mm->context.id = 0;
+   return 0;
+}
+
+#define destroy_con

[PATCH v5 07/39] nds32: Exception handling

[Greentime Hu]

From: Greentime Hu 

This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/ptrace.h |   66 +
 arch/nds32/kernel/ex-entry.S|  157 ++
 arch/nds32/kernel/ex-exit.S |  193 +
 arch/nds32/kernel/stacktrace.c  |   47 +++
 arch/nds32/kernel/traps.c   |  428 +++
 arch/nds32/mm/alignment.c   |  609 +++
 6 files changed, 1500 insertions(+)
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ex-entry.S
 create mode 100644 arch/nds32/kernel/ex-exit.S
 create mode 100644 arch/nds32/kernel/stacktrace.c
 create mode 100644 arch/nds32/kernel/traps.c
 create mode 100644 arch/nds32/mm/alignment.c

diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 000..db7856c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS   14
+#define PTRACE_SETFPREGS   15
+
+#include 
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+   union {
+   struct user_pt_regs user_regs;
+   struct {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+#if defined(CONFIG_HWZOL)
+   long lb;
+   long le;
+   long lc;
+#else
+   long dummy[3];
+#endif
+   long syscallno;
+   };
+   };
+   long orig_r0;
+   long ir0;
+   long ipsw;
+   long pipsw;
+   long pipc;
+   long pp0;
+   long pp1;
+   long fucop_ctl;
+   long osp;
+};
+
+#include 
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+int error_code, int si_code);
+
+#define arch_has_single_step() (1)
+#define user_mode(regs)(((regs)->ipsw & PSW_mskPOM) == 
0)
+#define interrupts_enabled(regs)   (!!((regs)->ipsw & PSW_mskGIE))
+#define valid_user_regs(regs)  (user_mode(regs) && 
interrupts_enabled(regs))
+#define regs_return_value(regs)((regs)->uregs[0])
+#define instruction_pointer(regs)  ((regs)->ipc)
+#define user_stack_pointer(regs)((regs)->sp)
+#define profile_pc(regs)   instruction_pointer(regs)
+
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 000..a72e83d
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_HWZOL
+   .macro push_zol
+   mfusr   $r14, $LB
+   mfusr   $r15, $LE
+   mfusr   $r16, $LC
+   .endm
+#endif
+
+   .macro  save_user_regs
+
+   smw.adm $sp, [$sp], $sp, #0x1
+   /* move $SP to the bottom of pt_regs */
+   addi$sp, $sp, -OSP_OFFSET
+
+   /* push $r0 ~ $r25 */
+   smw.bim $r0, [$sp], $r25
+   /* push $fp, $gp, $lp */
+   smw.bim $sp, [$sp], $sp, #0xe
+
+   mfsr$r12, $SP_USR
+   mfsr$r13, $IPC
+#ifdef CONFIG_HWZOL
+   push_zol
+#endif
+   movi$r17, -1
+   move$r18, $r0
+   mfsr$r19, $PSW
+   mfsr$r20, $IPSW
+   mfsr$r21, $P_IPSW
+   mfsr$r22, $P_IPC
+   mfsr$r23, $P_P0
+   mfsr$r24, $P_P1
+   smw.bim $r12, [$sp], $r24, #0
+   addi$sp, $sp, -FUCOP_CTL_OFFSET
+
+   /* Initialize kernel space $fp */
+   andi$p0, $r20, #PSW_mskPOM
+   movi$p1, #0x0
+   cmovz   $fp, $p1, $p0
+
+   andi$r16, $r19, #PSW_mskINTL
+   slti$r17, $r16, #4
+   bnez$r17, 1f
+   addi$r17, $r19, #-2
+   mtsr$r17, $PSW
+   isb
+1:
+   /* If it was superuser mode, we don't need to update $r25 */
+   bnez$p0, 2f
+   la  $p0, __entry_task
+   lw  $r25, [$p0]
+2:
+   .endm
+
+   .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+   .long   unhandled_exceptions!Reset/NMI
+   .long   unhandled_exceptions!TLB fill
+   .long   do_page_fault   !PTE not present
+   .long   do_dispatch_tlb_misc!TLB misc
+   .long   unhandled_exceptions!TLB VLPT
+  

[PATCH v5 09/39] nds32: MMU initialization

[Greentime Hu]

From: Greentime Hu 

This patch includes memory initializations and highmem supporting.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/mm/highmem.c  |   79 +
 arch/nds32/mm/init.c |  277 ++
 arch/nds32/mm/mm-nds32.c |   90 +++
 3 files changed, 446 insertions(+)
 create mode 100644 arch/nds32/mm/highmem.c
 create mode 100644 arch/nds32/mm/init.c
 create mode 100644 arch/nds32/mm/mm-nds32.c

diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
new file mode 100644
index 000..e17cb8a
--- /dev/null
+++ b/arch/nds32/mm/highmem.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void *kmap(struct page *page)
+{
+   unsigned long vaddr;
+   might_sleep();
+   if (!PageHighMem(page))
+   return page_address(page);
+   vaddr = (unsigned long)kmap_high(page);
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap);
+
+void kunmap(struct page *page)
+{
+   BUG_ON(in_interrupt());
+   if (!PageHighMem(page))
+   return;
+   kunmap_high(page);
+}
+
+EXPORT_SYMBOL(kunmap);
+
+void *kmap_atomic(struct page *page)
+{
+   unsigned int idx;
+   unsigned long vaddr, pte;
+   int type;
+   pte_t *ptep;
+
+   preempt_disable();
+   pagefault_disable();
+   if (!PageHighMem(page))
+   return page_address(page);
+
+   type = kmap_atomic_idx_push();
+
+   idx = type + KM_TYPE_NR * smp_processor_id();
+   vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+   pte = (page_to_pfn(page) << PAGE_SHIFT) | (PAGE_KERNEL);
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, pte);
+
+   __nds32__tlbop_inv(vaddr);
+   __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN);
+   __nds32__tlbop_rwr(pte);
+   __nds32__isb();
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap_atomic);
+
+void __kunmap_atomic(void *kvaddr)
+{
+   if (kvaddr >= (void *)FIXADDR_START) {
+   unsigned long vaddr = (unsigned long)kvaddr;
+   pte_t *ptep;
+   kmap_atomic_idx_pop();
+   __nds32__tlbop_inv(vaddr);
+   __nds32__isb();
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, 0);
+   }
+   pagefault_enable();
+   preempt_enable();
+}
+
+EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/nds32/mm/init.c b/arch/nds32/mm/init.c
new file mode 100644
index 000..93ee016
--- /dev/null
+++ b/arch/nds32/mm/init.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 1995-2005 Russell King
+// Copyright (C) 2012 ARM Ltd.
+// Copyright (C) 2013-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+DEFINE_SPINLOCK(anon_alias_lock);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern unsigned long phys_initrd_start;
+extern unsigned long phys_initrd_size;
+
+/*
+ * empty_zero_page is a special page that is used for
+ * zero-initialized data and COW.
+ */
+struct page *empty_zero_page;
+
+static void __init zone_sizes_init(void)
+{
+   unsigned long zones_size[MAX_NR_ZONES];
+
+   /* Clear the zone sizes */
+   memset(zones_size, 0, sizeof(zones_size));
+
+   zones_size[ZONE_NORMAL] = max_low_pfn;
+#ifdef CONFIG_HIGHMEM
+   zones_size[ZONE_HIGHMEM] = max_pfn;
+#endif
+   free_area_init(zones_size);
+
+}
+
+/*
+ * Map all physical memory under high_memory into kernel's address space.
+ *
+ * This is explicitly coded for two-level page tables, so if you need
+ * something else then this needs to change.
+ */
+static void __init map_ram(void)
+{
+   unsigned long v, p, e;
+   pgd_t *pge;
+   pud_t *pue;
+   pmd_t *pme;
+   pte_t *pte;
+   /* These mark extents of read-only kernel pages...
+* ...from vmlinux.lds.S
+*/
+
+   p = (u32) memblock_start_of_DRAM() & PAGE_MASK;
+   e = min((u32) memblock_end_of_DRAM(), (u32) __pa(high_memory));
+
+   v = (u32) __va(p);
+   pge = pgd_offset_k(v);
+
+   while (p < e) {
+   int j;
+   pue = pud_offset(pge, v);
+   pme = pmd_offset(pue, v);
+
+   if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
+   panic("%s: Kernel hardcoded for "
+ "two-level page tables", __func__);
+   }
+
+   /* Alloc one page for holding PTE's... */
+   pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+   memset(pte, 0, PAGE_SIZE);
+   set_pmd(pme, __pmd(__pa(pte) + _PAGE_KERNEL_TABLE));

[PATCH v5 02/39] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.

[Greentime Hu]

From: Greentime Hu 

It will be built failed if commit id: d25ea659 is selected. This patch can fix 
this
build error.

Signed-off-by: Greentime Hu 
---
 arch/openrisc/include/asm/io.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c69139..6709b28 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
 #define PIO_OFFSET 0
 #define PIO_MASK   0
 
+#define ioremap_nocache ioremap_nocache
 #include 
 #include 
 
 extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
 
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
return __ioremap(offset, size, PAGE_KERNEL);
 }
-- 
1.7.9.5

Re: [PATCH] x86: xen: remove the use of VLAIS

[Juergen Gross]

On 24/12/17 19:02, Nick Desaulniers wrote:
> Variable Length Arrays In Structs (VLAIS) is not supported by Clang, and
> frowned upon by others.
> 
> https://lkml.org/lkml/2013/9/23/500
> 
> Here, the VLAIS was used because the size of the bitmap returned from
> xen_mc_entry() depended on possibly (based on kernel configuration)
> runtime sized data. Rather than declaring args as a VLAIS then calling
> sizeof on *args, we can define the variable length array (mask) to be a
> pointer, and calculate the appropriate sizeof args manually. Further, we
> can get rid of the #ifdef's and rely on num_possible_cpus() (thanks to a
> helpful checkpatch warning from an earlier version of this patch).

Using a pointer for mask seems to be wrong, as it is never initialized.

Why don't you just use:

DECLARE_BITMAP(mask, NR_CPUS);

and drop the #ifdef, while keeping the manual length calculation?


Juergen

> 
> Signed-off-by: Nick Desaulniers 
> ---
>  arch/x86/xen/mmu_pv.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
> index 4d62c07..966976c 100644
> --- a/arch/x86/xen/mmu_pv.c
> +++ b/arch/x86/xen/mmu_pv.c
> @@ -1325,20 +1325,18 @@ static void xen_flush_tlb_others(const struct cpumask 
> *cpus,
>  {
>   struct {
>   struct mmuext_op op;
> -#ifdef CONFIG_SMP
> - DECLARE_BITMAP(mask, num_processors);
> -#else
> - DECLARE_BITMAP(mask, NR_CPUS);
> -#endif
> + unsigned long *mask;
>   } *args;
>   struct multicall_space mcs;
> + const size_t mc_entry_size = sizeof(args->op) +
> + sizeof(*args->mask) * BITS_TO_LONGS(num_possible_cpus());
>  
>   trace_xen_mmu_flush_tlb_others(cpus, info->mm, info->start, info->end);
>  
>   if (cpumask_empty(cpus))
>   return; /* nothing to do */
>  
> - mcs = xen_mc_entry(sizeof(*args));
> + mcs = xen_mc_entry(mc_entry_size);
>   args = mcs.args;
>   args->op.arg2.vcpumask = to_cpumask(args->mask);
>  
> 

[GIT PULL] phy: for 4.16

[Kishon Vijay Abraham I]

Hi Greg,

Please find the pull request for 4.16 merge window below.

It includes a fix in exynos5-usbdrd to enumerate SuperSpeed devices on
Odroid XU3 and includes fixes/cleanups in Broadcom and Mediatek PHYs.
Please see the tag message for the complete list of changes.

Consider merging it for the next merge window and let me know if I
have to make any changes.

Thanks
Kishon

The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git 
tags/phy-for-4.16

for you to fetch changes up to e4b227c1ca70ae779c39e5284742555b9e1cdf9f:

  phy: phy-mtk-tphy: use of_device_get_match_data() (2017-12-29 13:00:35 +0530)


phy: for 4.16

 *) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3
 *) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working
 *) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled
to save power
 *) Fix in Broadcom USB PHY to prevent abort in DRD mode
 *) Fix in Broadcom USB PHY to use the correct dt properties
 *) Fix in Mediatek PHY to detect device connection
 *) Make getting resource optional for Mediatek V1 TPHY
 *) Cleanup in Mediatek PHY

Signed-off-by: Kishon Vijay Abraham I 


Al Cooper (4):
  phy: phy-brcm-usb: Fix two DT properties to match bindings doc
  phy: phy-brcm-usb-init: Some Low Speed keyboards fail on 7271
  phy: phy-brcm-usb-init: Power down USB 3.0 PHY when XHCI disabled
  phy: phy-brcm-usb-init: DRD mode can cause crash on startup

Chunfeng Yun (3):
  phy: phy-mtk-tphy: use auto instead of force to bypass utmi signals
  phy: phy-mtk-tphy: make shared banks optional for V1 TPHY
  phy: phy-mtk-tphy: use of_device_get_match_data()

Vivek Gautam (1):
  phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800

 drivers/phy/broadcom/phy-brcm-usb-init.c |  22 ++--
 drivers/phy/broadcom/phy-brcm-usb.c  |   4 +-
 drivers/phy/mediatek/phy-mtk-tphy.c  |  35 +++---
 drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++
 drivers/usb/dwc3/core.c  |   2 +
 5 files changed, 212 insertions(+), 34 deletions(-)

-- 
2.11.0

Re: [linux-sunxi] [PATCH v4 1/6] ARM: sunxi: h3/h5: add simplefb nodes

[Icenowy Zheng]

在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道：
> On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng  wrote:
> > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> > 
> > Add simplefb nodes for these outputs.
> > 
> > Signed-off-by: Icenowy Zheng 
> > ---
> > Changes in v4:
> > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
> > 
> >   clocks that are needed to display framebuffer to the monitor.
> 
> Looks good. I assume you've tested this? It does continue to work
> with the bus and DDC clocks disabled, right?

Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model 
A".

> 
> Thanks
> ChenYu

[PATCH] xen/input: do not advertise multi-touch pressure support

[Oleksandr Andrushchenko]

From: Oleksandr Andrushchenko 

Some user-space applications expect multi-touch pressure
on contact to be reported if it is advertised in device
properties. Otherwise, such applications may treat reports
not as actual touches, but hovering. Currently this is
only advertised, but not reported.
Fix this by not advertising that ABS_MT_PRESSURE is supported.

Signed-off-by: Oleksandr Andrushchenko 
Signed-off-by: Andrii Chepurnyi 
---
 drivers/input/misc/xen-kbdfront.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/input/misc/xen-kbdfront.c 
b/drivers/input/misc/xen-kbdfront.c
index 6bf56bb5f8d9..d91f3b1c5375 100644
--- a/drivers/input/misc/xen-kbdfront.c
+++ b/drivers/input/misc/xen-kbdfront.c
@@ -326,8 +326,6 @@ static int xenkbd_probe(struct xenbus_device *dev,
 0, width, 0, 0);
input_set_abs_params(mtouch, ABS_MT_POSITION_Y,
 0, height, 0, 0);
-   input_set_abs_params(mtouch, ABS_MT_PRESSURE,
-0, 255, 0, 0);
 
ret = input_mt_init_slots(mtouch, num_cont, INPUT_MT_DIRECT);
if (ret) {
-- 
2.7.4

Re: [linux-sunxi] [PATCH v4 1/6] ARM: sunxi: h3/h5: add simplefb nodes

[Chen-Yu Tsai]

On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng  wrote:
> The H3/H5 SoCs have a HDMI output and a TV Composite output.
>
> Add simplefb nodes for these outputs.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v4:
> - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
>   clocks that are needed to display framebuffer to the monitor.

Looks good. I assume you've tested this? It does continue to work
with the bus and DDC clocks disabled, right?

Thanks
ChenYu

Re: [linux-sunxi] [PATCH v4 3/6] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

[Chen-Yu Tsai]

On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng  wrote:
> Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v4:
> - Use a struct to maintain both ccu desc and quirks as Chen-Yu Tsai
>   suggested.

This made the patch slightly messy. Could you split it into two patches?
The first just adds the struct (without the sram_needed field) and migrates
everything to that. This patch should mention it is preperation for the
next patch, which adds the a field to the struct (otherwise it makes no
sense and just looks like churn.) The second patch will add the .sram_needed
field and support for the A64 DE2 CCU.


Thanks
ChenYu

[RFC PATCH v2] pciehp: fix a race between pciehp and removing operations by sysfs

[Xiongfeng Wang]

From: Xiongfeng Wang 

When I run a stress test about pcie hotplug and removing operations by
sysfs, I got a hange task, and the following call trace is printed.

 INFO: task kworker/0:2:4413 blocked for more than 120 seconds.
   Tainted: PW  O4.12.0-rc1 #1
 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
 kworker/0:2 D0  4413  2 0x
 Workqueue: pciehp-0 pciehp_power_thread
 Call trace:
 [] __switch_to+0x94/0xa8
 [] __schedule+0x1b0/0x708
 [] schedule+0x40/0xa4
 [] schedule_preempt_disabled+0x28/0x40
 [] __mutex_lock.isra.8+0x148/0x50c
 [] __mutex_lock_slowpath+0x24/0x30
 [] mutex_lock+0x48/0x54
 [] pci_lock_rescan_remove+0x20/0x28
 [] pciehp_unconfigure_device+0x54/0x1cc
 [] pciehp_disable_slot+0x4c/0xbc
 [] pciehp_power_thread+0xa0/0xb8
 [] process_one_work+0x13c/0x3f8
 [] worker_thread+0x60/0x3e4
 [] kthread+0x10c/0x138
 [] ret_from_fork+0x10/0x50
 INFO: task bash:31732 blocked for more than 120 seconds.
   Tainted: PW  O4.12.0-rc1 #1
 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
 bashD0 31732  1 0x0009
 Call trace:
 [] __switch_to+0x94/0xa8
 [] __schedule+0x1b0/0x708
 [] schedule+0x40/0xa4
 [] schedule_timeout+0x1a0/0x340
 [] wait_for_common+0x108/0x1bc
 [] wait_for_completion+0x28/0x34
 [] flush_workqueue+0x130/0x488
 [] drain_workqueue+0xc4/0x164
 [] destroy_workqueue+0x28/0x1f4
 [] pciehp_release_ctrl+0x34/0xe0
 [] pciehp_remove+0x30/0x3c
 [] pcie_port_remove_service+0x3c/0x54
 [] device_release_driver_internal+0x150/0x1d0
 [] device_release_driver+0x28/0x34
 [] bus_remove_device+0xe0/0x11c
 [] device_del+0x200/0x304
 [] device_unregister+0x20/0x38
 [] remove_iter+0x44/0x54
 [] device_for_each_child+0x4c/0x90
 [] pcie_port_device_remove+0x2c/0x48
 [] pcie_portdrv_remove+0x60/0x6c
 [] pci_device_remove+0x48/0x110
 [] device_release_driver_internal+0x150/0x1d0
 [] device_release_driver+0x28/0x34
 [] pci_stop_bus_device+0x9c/0xac
 [] pci_stop_and_remove_bus_device_locked+0x24/0x3c
 [] remove_store+0x74/0x80
 [] dev_attr_store+0x44/0x5c
 [] sysfs_kf_write+0x5c/0x74
 [] kernfs_fop_write+0xcc/0x1dc
 [] __vfs_write+0x48/0x13c
 [] vfs_write+0xa8/0x198
 [] SyS_write+0x54/0xb0
 [] el0_svc_naked+0x24/0x28

There is a race condition between these two kinds of operations.
When the Attention button on a PCIE slot is pressed, 5 seconds later,
pciehp_power_thread() will be scheduled on slot->wq. This function will
call pciehp_unconfigure_device(), which will try to get a global mutex
lock 'pci_rescan_remove_lock'.

At the same time, we remove the pcie port by sysfs, which results in
pci_stop_and_remove_bus_device_locked() called. This function will get
the global mutex lock 'pci_rescan_remove_lock', and then release the
struct 'ctrl', which will wait until the work_struct on slot->wq is
finished.

If pci_stop_and_remove_bus_device_locked() got the mutex lock, and
before it drains workqueue slot->wq, pciehp_power_thread() is scheduled
on slot->wq and tries to get the mutex lock but failed, so it will just
wait. Then pci_stop_and_remove_bus_device_locked() tries to drain workqueue
slot->wq and wait until work struct 'pciehp_power_thread()' is finished.
Then a hung_task occurs.

So this two kinds of operation, removing through attention buttion and
removing through /sys/devices/pci***/remove, should not be excuted at the
same time. This patch add a global variable to mark that one of these
operations is under processing. When this variable is set,  if another
operation is requested, it will be rejected.

At first, I want to add a flag for each pci slot to record whether a
removing operation is under processing. When a bridge is being removed,
the flags of all the slots below the bridge need to be checked. But it
is hard for us to guarantee the atomic access. So I just use a global
flag.

This workaround method uses a global flag, which is not good for the code
framework and can't fix the race condition fully. But I can't figure out
a better way. I think we may need to reconstruct the code framework a lot
to fix this issue nicely. There are so many work struct created. Before
that, maybe we can use this patch as a temporary fix.

Signed-off-by: Xiongfeng Wang 
---
 drivers/pci/hotplug/pciehp_ctrl.c |  7 +++
 drivers/pci/hotplug/pciehp_hpc.c  | 12 +++-
 drivers/pci/pci-sysfs.c   | 11 +--
 drivers/pci/remove.c  |  6 ++
 include/linux/pci.h   |  3 +++
 5 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/hotplug/pciehp_ctrl.c 
b/drivers/pci/hotplug/pciehp_ctrl.c
index 83f3d4a..5680439 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -44,6 +44,7 @@ void pciehp_queue_interrupt_event(struct slot *p_slot, u32 
event_type)
info = kmalloc(sizeof(*info), GFP_ATOMIC);
if (!info) {
ctrl_err(p_slot->ctrl, "dropped event %d (ENOMEM)\n", 
event_type);
+

[PATCH 3/3] nvme-pci: add nvme_pci_post_init

[Jianchao Wang]

No functional change. Add new interface nvme_pci_post_init to get
in the nvme sepcific initialization work after identify.

Signed-off-by: Jianchao Wang 
---
 drivers/nvme/host/pci.c | 58 +
 1 file changed, 34 insertions(+), 24 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 1a63835..c390cf1 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2295,11 +2295,41 @@ static int nvme_pci_pre_init(struct nvme_dev *dev)
return nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
 }
 
+/* Include initialization work after identify
+ */
+static int nvme_pci_post_init(struct nvme_dev *dev)
+{
+   int ret;
+   bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
+
+   if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
+   if (!dev->ctrl.opal_dev)
+   dev->ctrl.opal_dev =
+   init_opal_dev(&dev->ctrl, &nvme_sec_submit);
+   else if (was_suspend)
+   opal_unlock_from_suspend(dev->ctrl.opal_dev);
+   } else {
+   free_opal_dev(dev->ctrl.opal_dev);
+   dev->ctrl.opal_dev = NULL;
+   }
+
+   if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
+   if(nvme_dbbuf_dma_alloc(dev))
+   dev_warn(dev->dev,
+"unable to allocate dma for dbbuf\n");
+   }
+
+   if (dev->ctrl.hmpre) {
+   ret = nvme_setup_host_mem(dev);
+   return ret >= 0 ? 0 : ret;
+   }
+
+   return 0;
+}
 static void nvme_reset_work(struct work_struct *work)
 {
struct nvme_dev *dev =
container_of(work, struct nvme_dev, ctrl.reset_work);
-   bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
int result = -ENODEV;
 
if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
@@ -2333,29 +2363,9 @@ static void nvme_reset_work(struct work_struct *work)
if (result)
goto out;
 
-   if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
-   if (!dev->ctrl.opal_dev)
-   dev->ctrl.opal_dev =
-   init_opal_dev(&dev->ctrl, &nvme_sec_submit);
-   else if (was_suspend)
-   opal_unlock_from_suspend(dev->ctrl.opal_dev);
-   } else {
-   free_opal_dev(dev->ctrl.opal_dev);
-   dev->ctrl.opal_dev = NULL;
-   }
-
-   if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
-   result = nvme_dbbuf_dma_alloc(dev);
-   if (result)
-   dev_warn(dev->dev,
-"unable to allocate dma for dbbuf\n");
-   }
-
-   if (dev->ctrl.hmpre) {
-   result = nvme_setup_host_mem(dev);
-   if (result < 0)
-   goto out;
-   }
+   result = nvme_pci_post_init(dev);
+   if (result)
+   goto out;
 
result = nvme_setup_io_queues(dev);
if (result)
-- 
2.7.4

[PATCHSET] nvme-pci: sort out nvme initialization procedure in nvme_rest_work

[Jianchao Wang]

Hello

This patchset is to sort out the nvme initialization procedure in
nvme_reset_work. There is no functional changes in it. Add two new
helper interfaces nvme_pci_pre_init and nvme_pci_post_init to package
the nvme specific initialization work before configuring adminq and
after getting identify information. Then nvme_pci_enable, 
nvme_pci_configure_admin_queue and nvme_reset_work could be clearer.
Change functions' name, nvme_pci_configure_admin_queue and
nvme_alloc_admin_tags to  nvme_pci_setup_adminq and
nvme_pci_start_adminq to make it more readable.

Jianchao Wang (3)
0001-nvme-pci-add-nvme_pci_pre_init.patch
0002-nvme-pci-change-the-name-of-functions-corresponding-.patch
0003-nvme-pci-add-nvme_pci_post_init.patch

 drivers/nvme/host/pci.c | 211 ++--
 1 file changed, 115 insertions(+), 96 deletions(-)

Thanks
Jianchao