Re: [PATCH v8 20/22] KVM: s390: Handling of Cypto control block in VSIE
On 09/08/2018 08:20, Janosch Frank wrote:
On 08.08.2018 16:44, Tony Krowiak wrote:
From: Pierre Morel
+#define ECA_APIE 0x0008
That shouldn't be necessary, it's defined in kvm_host.h which vsie.c
includes. Or is it not?
This was forgotten here for a long long time!
You are right I remove it.
+static int shadow_crycb(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
+{
+ struct kvm_s390_sie_block *scb_s = &vsie_page->scb_s;
+ struct kvm_s390_sie_block *scb_o = vsie_page->scb_o;
+ const uint32_t crycbd_o = READ_ONCE(scb_o->crycbd);
+ const u32 crycb_addr = crycbd_o & 0x7ff8U;
+ int g2_fmt = vcpu->arch.sie_block->crycbd & CRYCB_FORMAT_MASK;
+ int g3_fmt = crycbd_o & CRYCB_FORMAT_MASK;
+ int g2_apie, g2_msa3, g3_apie, g3_msa3;
+ int size, ret;
+
+ /* crycb should not cross a page boundary */
+ size = (g3_fmt == CRYCB_FORMAT2) ? 0x100 : 0x80;
+ if ((crycb_addr & PAGE_MASK) != ((crycb_addr + size) & PAGE_MASK))
+ return set_validity_icpt(scb_s, 0x003CU);
+
+ g2_apie = vcpu->arch.sie_block->eca & ECA_APIE;
+ g3_apie = scb_o->eca & g2_apie;
+
+ g2_msa3 = test_kvm_facility(vcpu->kvm, 76);
+ g3_msa3 = (g3_fmt != CRYCB_FORMAT0) & g2_msa3;
+
+ scb_s->crycbd = 0;
+ /* If no AP instructions and no keys we just set crycbd to 0 */
+ if (!(g3_apie || g3_msa3))
+ return 0;
+
+ if (!crycb_addr)
+ return set_validity_icpt(scb_s, 0x0039U);
+
+ if (g3_apie) {
+ ret = copy_apcb(vcpu, vsie_page, g2_fmt, g3_fmt);
+ if (ret)
+ goto out;
s/goto out;/return ret;/
better
Thanks
Pierre
--
Pierre Morel
Linux/KVM/QEMU in Böblingen - Germany
Re: [PATCH v5 5/5] Auto-detect whether a FPU exists
On Thu, Aug 09, 2018 at 12:02:58AM -0700, Christoph Hellwig wrote: > On Thu, Aug 09, 2018 at 02:43:36PM +0800, Alan Kao wrote: > > It does look a little bit weird. Should I send a v6 for this? > > Yes, please resend the series or just this patch. > > I think the hswap.h definition should go away and we should just > keep the switch_to.h one, even if that means including the header > in another C file. > It turns out that only cpufeature.c and switch_to.h are affected by hwcap.h. As switch_to.h already had extern has_fpu declaration, the one in hwcap.h is redundant and can be removed safely. I will resend just this patch, and mark it as v6.
Re: FUSE: write operations trigger balance_dirty_pages when using writeback cache
Thank you for the prompt reply. I tried this config, but still can get balance_dirty_pages triggered. [root@A01-R20-I31-77-8S5FKM2 example]# stat -c %d /mnt/fuse/ 42 [root@A01-R20-I31-77-8S5FKM2 example]# echo 20 > /sys/devices/virtual/bdi/0:`stat -c %d /mnt/fuse/`/max_ratio [root@A01-R20-I31-77-8S5FKM2 example]# cat /sys/devices/virtual/bdi/0\:42/max_ratio 20 [root@A01-R20-I31-77-8S5FKM2 example]# dd if=/dev/zero of=/mnt/fuse/tmp/test001 bs=4k count=2 ... dd-633 [001] 273499.083059: balance_dirty_pages: bdi 0:42: limit=3180556 setpoint=2782501 dirty=310 bdi_setpoint=0 bdi_dirty=13 dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 pause=14 period=14 think=1 cgroup_ino=1 dd-633 [001] 273499.098089: balance_dirty_pages: bdi 0:42: limit=3180556 setpoint=2782501 dirty=311 bdi_setpoint=0 bdi_dirty=14 dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 pause=15 period=15 think=1 cgroup_ino=1 dd-633 [001] 273499.114082: balance_dirty_pages: bdi 0:42: limit=3180556 setpoint=2782501 dirty=312 bdi_setpoint=0 bdi_dirty=15 dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 pause=16 period=16 think=1 cgroup_ino=1 ... Regards, Shuoran -邮件原件- 发件人: Miklos Szeredi [mailto:mik...@szeredi.hu] 发送时间: 2018年8月9日 15:14 收件人: 刘硕然 抄送: linux-fsde...@vger.kernel.org; linux-kernel@vger.kernel.org 主题: Re: FUSE: write operations trigger balance_dirty_pages when using writeback cache On Thu, Aug 9, 2018 at 5:37 AM, 刘硕然 wrote: > Dear Miklos, > > Recently I've been testing FUSE and libfuse example passthrough_ll with > writeback cache on, and found out that the performance drops significantly > compared to that in local filesystem. As I can see from trace, > balance_dirty_pages is triggered very frequently even if there not enough > pages that shall be sent to libfuse. I'm not sure if this is a known fact or > the FUSE writeback feature requires some specific configurations. Trace log > is attached. > > dd-19067 [001] 195295.568097: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=32 > dirty_ratelimit=32 task_ratelimit=0 dirtied=32 dirtied_pause=32 paused=0 > pause=33 period=33 think=0 cgroup_ino=1 > dd-19067 [001] 195295.602029: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=33 > dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 > pause=34 period=34 think=1 cgroup_ino=1 > dd-19067 [001] 195295.637026: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=34 > dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 > pause=35 period=35 think=1 cgroup_ino=1 > > BTW, I'm using Linux kernel 4.17.12 and libfuse 3.2.5. Look forward to > hearing from you. Thanks in advance. Try echo 20 > /sys/devices/virtual/bdi/0:`stat -c %d /mnt/fuse/`/max_ratio where you replace /mnt/fuse with your mountpoint. Thanks, Miklos
Re: [PATCH RFC 1/2] KVM: s390: vsie: simulate VCPU SIE entry/exit
On 07.08.2018 14:51, David Hildenbrand wrote:
> VCPU requests and VCPU blocking right now don't take care of the vSIE
> (as it was not necessary until now). But we want to have VCPU requests
> that will also be handled before running the vSIE again.
>
> So let's simulate a SIE entry when entering the vSIE loop and check
> for PROG_ flags. The existing infrastructure (e.g. exit_sie()) will then
> detect that the SIE (in form of the vSIE execution loop) is running and
> properly kick the vSIE CPU, resulting in it leaving the vSIE loop and
> therefore the vSIE interception handler, allowing it to handle VCPU
> requests.
>
> E.g. if we want to modify the crycb of the VCPU and make sure that any
> masks also get applied to the VSIE crycb shadow (which uses masks from the
> VCPU crycb), we will need a way to hinder the vSIE from running and make
> sure to process the updated crycb before reentering the vSIE again.
>
> Signed-off-by: David Hildenbrand
> ---
> arch/s390/kvm/kvm-s390.c | 9 -
> arch/s390/kvm/kvm-s390.h | 1 +
> arch/s390/kvm/vsie.c | 20 ++--
> 3 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
> index 91ad4a9425c0..c87734a31fdb 100644
> --- a/arch/s390/kvm/kvm-s390.c
> +++ b/arch/s390/kvm/kvm-s390.c
> @@ -2766,18 +2766,25 @@ static void kvm_s390_vcpu_request(struct kvm_vcpu
> *vcpu)
> exit_sie(vcpu);
> }
>
> +bool kvm_s390_vcpu_sie_inhibited(struct kvm_vcpu *vcpu)
> +{
> + return atomic_read(&vcpu->arch.sie_block->prog20) &
> +(PROG_BLOCK_SIE | PROG_REQUEST);
> +}
> +
> static void kvm_s390_vcpu_request_handled(struct kvm_vcpu *vcpu)
> {
> atomic_andnot(PROG_REQUEST, &vcpu->arch.sie_block->prog20);
> }
>
> /*
> - * Kick a guest cpu out of SIE and wait until SIE is not running.
> + * Kick a guest cpu out of (v)SIE and wait until (v)SIE is not running.
> * If the CPU is not running (e.g. waiting as idle) the function will
> * return immediately. */
> void exit_sie(struct kvm_vcpu *vcpu)
> {
> kvm_s390_set_cpuflags(vcpu, CPUSTAT_STOP_INT);
> + kvm_s390_vsie_kick(vcpu);
> while (vcpu->arch.sie_block->prog0c & PROG_IN_SIE)
> cpu_relax();
> }
> diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
> index 981e3ba97461..1f6e36cdce0d 100644
> --- a/arch/s390/kvm/kvm-s390.h
> +++ b/arch/s390/kvm/kvm-s390.h
> @@ -290,6 +290,7 @@ void kvm_s390_vcpu_start(struct kvm_vcpu *vcpu);
> void kvm_s390_vcpu_stop(struct kvm_vcpu *vcpu);
> void kvm_s390_vcpu_block(struct kvm_vcpu *vcpu);
> void kvm_s390_vcpu_unblock(struct kvm_vcpu *vcpu);
> +bool kvm_s390_vcpu_sie_inhibited(struct kvm_vcpu *vcpu);
> void exit_sie(struct kvm_vcpu *vcpu);
> void kvm_s390_sync_request(int req, struct kvm_vcpu *vcpu);
> int kvm_s390_vcpu_setup_cmma(struct kvm_vcpu *vcpu);
> diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c
> index 63844b95c22c..faac06886f77 100644
> --- a/arch/s390/kvm/vsie.c
> +++ b/arch/s390/kvm/vsie.c
> @@ -989,6 +989,17 @@ static int vsie_run(struct kvm_vcpu *vcpu, struct
> vsie_page *vsie_page)
> struct kvm_s390_sie_block *scb_s = &vsie_page->scb_s;
> int rc = 0;
>
> + /*
> + * Simulate a SIE entry of the VCPU (see sie64a), so VCPU blocking
> + * and VCPU requests can hinder the whole vSIE loop from running
> + * and lead to an immediate exit. We do it at this point (not
> + * earlier), so kvm_s390_vsie_kick() works correctly already.
> + */
> + vcpu->arch.sie_block->prog0c |= PROG_IN_SIE;
> + barrier();
> + if (kvm_s390_vcpu_sie_inhibited(vcpu))
> + return 0;
> +
> while (1) {
> rc = acquire_gmap_shadow(vcpu, vsie_page);
> if (!rc)
> @@ -1004,10 +1015,14 @@ static int vsie_run(struct kvm_vcpu *vcpu, struct
> vsie_page *vsie_page)
> if (rc == -EAGAIN)
> rc = 0;
> if (rc || scb_s->icptcode || signal_pending(current) ||
> - kvm_s390_vcpu_has_irq(vcpu, 0))
> + kvm_s390_vcpu_has_irq(vcpu, 0) ||
> + kvm_s390_vcpu_sie_inhibited(vcpu))
> break;
> }
>
> + barrier();
> + vcpu->arch.sie_block->prog0c &= ~PROG_IN_SIE;
> +
I am thinking about moving this down to the actual sie64 call. We
eventually take locks and even call into MM code (to resolve faults)
inside do_vsie_run(). I think this extra overhead can be avoided (where
any caller - e.g. on prefix unmaps has to wait).
--
Thanks,
David / dhildenb
Re: [PATCH 0/2] fs/lock: show locks info owned by dead/invisible processes
Hi,
Looks like this missed v4.18 ?
Thanks,
Murphy
On Fri, Jun 8, 2018 at 10:27 PM, Konstantin Khorenko
wrote:
> The behavior has been changed after 9d5b86ac13c5 ("fs/locks: Remove fl_nspid
> and use fs-specific l_pid for remote locks")
> and now /proc/$PID/fdinfo/$FD does not show the info about the lock
> * if the flock owner process is dead and its pid has been already freed
> or
> * if the lock owner is not visible in current pidns.
>
> CRIU uses this interface to store locks info during dump and thus can break
> on v4.13 and newer.
>
> So let's show info about locks anyway in described cases (like it was before
> 9d5b86ac13c5), but show pid number saved in file_lock struct if we are in
> init_pid_ns (patch 1) or just zero otherwise (patch 2) like we do with SID.
>
> Reproducer:
> process A process A1 process A2
> fork()->
> exit() open()
> flock()
> fork()->
> exit() sleep()
>
> Before the patch:
>
> (root@vz7)/: cat /proc/${PID_A2}/fdinfo/3
> pos:4
> flags: 0212
> mnt_id: 257
> lock: (root@vz7)/:
>
> After the patch:
> ===
> (root@vz7)/:cat /proc/${PID_A2}/fdinfo/3
> pos:4
> flags: 0212
> mnt_id: 295
> lock: 1: FLOCK ADVISORY WRITE ${PID_A1} b6:f8a61:529946 0 EOF
>
> ===
> # cat flock1.c
>
> #include
> #include
> #include
> #include
> #include
> #include
> #include
>
> int main(void)
> {
> int fd;
> int err;
> pid_t child_pid;
>
> child_pid = fork();
> if (child_pid == -1)
> perror("fork failed");
> if (child_pid) {
> exit(0);
> }
>
> fd = open("/tmp/a", O_CREAT | O_RDWR);
> if (fd == -1)
> perror("Failed to open the file");
>
> err = flock(fd, LOCK_EX);
> if (err == -1)
> perror("flock failed");
>
> child_pid = fork();
> if (child_pid == -1)
> perror("fork failed");
> if (child_pid)
> exit(0);
>
> sleep(1);
>
> return 0;
> }
>
> Konstantin Khorenko (2):
> fs/lock: skip lock owner pid translation in case we are in init_pid_ns
> fs/lock: show locks taken by processes from another pidns
>
> fs/locks.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> --
> 2.15.1
>
Re: FUSE: write operations trigger balance_dirty_pages when using writeback cache
On Thu, Aug 9, 2018 at 5:37 AM, 刘硕然 wrote: > Dear Miklos, > > Recently I've been testing FUSE and libfuse example passthrough_ll with > writeback cache on, and found out that the performance drops significantly > compared to that in local filesystem. As I can see from trace, > balance_dirty_pages is triggered very frequently even if there not enough > pages that shall be sent to libfuse. I'm not sure if this is a known fact or > the FUSE writeback feature requires some specific configurations. Trace log > is attached. > > dd-19067 [001] 195295.568097: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=32 > dirty_ratelimit=32 task_ratelimit=0 dirtied=32 dirtied_pause=32 paused=0 > pause=33 period=33 think=0 cgroup_ino=1 > dd-19067 [001] 195295.602029: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=33 > dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 > pause=34 period=34 think=1 cgroup_ino=1 > dd-19067 [001] 195295.637026: balance_dirty_pages: bdi 0:42: > limit=3180390 setpoint=2782421 dirty=5 bdi_setpoint=0 bdi_dirty=34 > dirty_ratelimit=32 task_ratelimit=0 dirtied=1 dirtied_pause=0 paused=0 > pause=35 period=35 think=1 cgroup_ino=1 > > BTW, I'm using Linux kernel 4.17.12 and libfuse 3.2.5. Look forward to > hearing from you. Thanks in advance. Try echo 20 > /sys/devices/virtual/bdi/0:`stat -c %d /mnt/fuse/`/max_ratio where you replace /mnt/fuse with your mountpoint. Thanks, Miklos
Re: [PATCH RFC v2 02/10] mm: Make shrink_slab() lockless
On Wed 08-08-18 16:20:54, Kirill Tkhai wrote: > [Added two more places needed srcu_dereference(). All ->shrinker_map > dereferences must be under SRCU, and this v2 adds missed in previous] > > The patch makes shrinker list and shrinker_idr SRCU-safe > for readers. This requires synchronize_srcu() on finalize > stage unregistering stage, which waits till all parallel > shrink_slab() are finished > > Note, that patch removes rwsem_is_contended() checks from > the code, and this does not result in delays during > registration, since there is no waiting at all. Unregistration > case may be optimized by splitting unregister_shrinker() > in tho stages, and this is made in next patches. > > Also, keep in mind, that in case of SRCU is not allowed > to make unconditional (which is done in previous patch), > it is possible to use percpu_rw_semaphore instead of it. > percpu_down_read() will be used in shrink_slab_memcg() > and in shrink_slab(), and consecutive calls > > percpu_down_write(percpu_rwsem); > percpu_up_write(percpu_rwsem); > > will be used instead of synchronize_srcu(). An obvious question. Why didn't you go that way? What are pros/cons of both approaches? -- Michal Hocko SUSE Labs
[PATCH v4 3/3] clk: meson: add sub MMC clock controller driver
The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.
Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 10 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/mmc-clkc.c | 275 +++
3 files changed, 286 insertions(+)
create mode 100644 drivers/clk/meson/mmc-clkc.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..8b8ccbcfed1d 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
+config COMMON_CLK_MMC_MESON
+ tristate "Meson MMC Sub Clock Controller Driver"
+ depends on COMMON_CLK_AMLOGIC
+ select MFD_SYSCON
+ select REGMAP
+ help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 39ce5661b654..31c16d524a4b 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..6aa055f7e62c
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX 0
+
+#define SD_EMMC_CLOCK 0
+#define CLK_DIV_MASK GENMASK(5, 0)
+#define CLK_SRC_MASK GENMASK(7, 6)
+#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define CLK_TX_PHASE_MASKGENMASK(11, 10)
+#define CLK_RX_PHASE_MASKGENMASK(13, 12)
+#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define CLK_V2_ALWAYS_ON BIT(24)
+
+#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define CLK_V3_ALWAYS_ON BIT(28)
+
+#define CLK_DELAY_STEP_PS200
+#define CLK_PHASE_STEP 30
+#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS 5
+
+struct mmc_clkc_data {
+ struct meson_clk_phase_delay_data tx;
+ struct meson_clk_phase_delay_data rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+ .offset = SD_EMMC_CLOCK,
+ .mask = 0x3,
+ .shift = 6,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+ .offset = SD_EMMC_CLOCK,
+ .shift = 0,
+ .width = 6,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_delay_data mmc_clkc_core_phase_delay = {
+ .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+ {
+ .phase_mask = CLK_TX_PHASE_MASK,
+ .delay_mask = CLK_V2_TX_DELAY_MASK,
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ {
+ .phase_mask = CLK_RX_PHASE_MASK,
+ .delay_mask = CLK_V2_RX_DELAY_MASK,
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+ {
+ .phase_mask = CLK_TX_PHASE_MASK,
+ .delay_mask = CLK_V3_TX_DELAY_MASK,
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ {
+ .phase_mask = CLK_RX_PHASE_MASK,
+ .delay_mask = CLK_V3_RX_DELAY_MA
[PATCH v4 2/3] clk: meson: add DT documentation for emmc clock controller
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
---
.../bindings/clock/amlogic,mmc-clkc.txt | 31 +++
include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++
2 files changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index ..9e6d34389be8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,31 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+ "amlogic,gx-mmc-clkc"
+ "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+ - "clkin0", "clkin1"
+
+Parent node should have the following properties :
+- compatible: "amlogic,axg-mmc-clkc", "syscon".
+- reg: base address and size of the MMC control register space.
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x4>;
+ #clock-cells = <1>;
+
+ clock-names = "clkin0", "clkin1";
+ clocks = <&clkc CLKID_SD_MMC_C_CLK0>,
+<&clkc CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index ..162b94949119
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV 1
+#define CLKID_MMC_PHASE_CORE 2
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
--
2.17.1
[PATCH v4 1/3] clk: meson: add emmc sub clock phase delay driver
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-phase-delay.c | 96 +
drivers/clk/meson/clkc.h| 13
3 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/clk-phase-delay.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..39ce5661b654 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,7 +2,7 @@
# Makefile for Meson specific clk
#
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
clk-phase-delay.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/clk-phase-delay.c
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index ..6f226814cfec
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ */
+
+#include
+#include "clkc.h"
+
+#define SD_EMMC_CLOCK 0
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph =
+ meson_clk_get_phase_delay_data(clk);
+ unsigned int phase_num = 1 << hweight_long(ph->phase_mask);
+ unsigned long period_ps, p, d;
+ int degrees;
+ u32 val;
+
+ regmap_read(clk->map, SD_EMMC_CLOCK, &val);
+ p = (val & ph->phase_mask) >> __ffs(ph->phase_mask);
+ degrees = p * 360 / phase_num;
+
+ if (ph->delay_mask) {
+ period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+ d = (val & ph->delay_mask) >> __ffs(ph->delay_mask);
+ degrees += d * ph->delay_step_ps * 360 / period_ps;
+ degrees %= 360;
+ }
+
+ return degrees;
+}
+
+static void meson_clk_apply_phase_delay(struct clk_regmap *clk,
+ unsigned int phase,
+ unsigned int delay)
+{
+ struct meson_clk_phase_delay_data *ph = clk->data;
+ u32 val;
+
+ regmap_read(clk->map, SD_EMMC_CLOCK, &val);
+
+ val &= ~ph->phase_mask;
+ val |= phase << __ffs(ph->phase_mask);
+
+ if (ph->delay_mask) {
+ val &= ~ph->delay_mask;
+ val |= delay << __ffs(ph->delay_mask);
+ }
+
+ regmap_write(clk->map, SD_EMMC_CLOCK, val);
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph =
+ meson_clk_get_phase_delay_data(clk);
+ unsigned int phase_num = 1 << hweight_long(ph->phase_mask);
+ unsigned long period_ps, d = 0, r;
+ u64 p;
+
+ p = degrees % 360;
+
+ if (!ph->delay_mask) {
+ p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
+ } else {
+ period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+
+ /* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+ r = do_div(p, 360 / phase_num);
+ d = DIV_ROUND_CLOSEST(r * period_ps,
+ 360 * ph->delay_step_ps);
+ d = min(d, ph->delay_mask >> __ffs(ph->delay_mask));
+ }
+
+ meson_clk_apply_phase_delay(clk, p, d);
+ return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+ .get_phase = meson_clk_phase_delay_get_phase,
+ .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 24cec16b6038..499834dd34f2 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -113,6 +113,18 @@ struct clk_regmap _name = {
\
}, \
};
+struct meson_clk_phase_delay_data {
+ unsigned long phase_mask;
+ unsigned long delay_mask;
+ unsigned intdelay_step_ps;
+};
+
+static inline struct meson_clk_phase_delay_data *
+meson_clk_get_phase_delay_data(struct clk_regmap *clk)
+{
+ return (st
[PATCH v4 0/3] clk: meson: add a sub EMMC clock controller support
This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../bindings/clock/amlogic,mmc-clkc.txt | 31 ++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile| 3 +- drivers/clk/meson/clk-phase-delay.c | 96 ++ drivers/clk/meson/clkc.h | 13 + drivers/clk/meson/mmc-clkc.c | 275 ++ include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 7 files changed, 444 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 2.17.1
[PATCH v2] dmaengine: sprd: Support DMA link-list mode
From: Eric Long
The Spreadtrum DMA can support the link-list transaction mode, which means
DMA controller can do transaction one by one automatically once we linked
these transaction by link-list register.
Signed-off-by: Eric Long
Signed-off-by: Baolin Wang
---
Changes since v1:
- Remove sprd_dma_fill_chn_desc() function.
- Remove the redundant validation of 'sglen' in sprd_dma_fill_linklist_desc().
- Add some comments make code more clear.
- Fix the typos.
---
drivers/dma/sprd-dma.c | 81 ++
include/linux/dma/sprd-dma.h | 69 +++
2 files changed, 143 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c
index 55df0d4..38d4e4f 100644
--- a/drivers/dma/sprd-dma.c
+++ b/drivers/dma/sprd-dma.c
@@ -68,6 +68,7 @@
/* SPRD_DMA_CHN_CFG register definition */
#define SPRD_DMA_CHN_ENBIT(0)
+#define SPRD_DMA_LINKLIST_EN BIT(4)
#define SPRD_DMA_WAIT_BDONE_OFFSET 24
#define SPRD_DMA_DONOT_WAIT_BDONE 1
@@ -103,7 +104,7 @@
#define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)
#define SPRD_DMA_FIX_SEL_OFFSET21
#define SPRD_DMA_FIX_EN_OFFSET 20
-#define SPRD_DMA_LLIST_END_OFFSET 19
+#define SPRD_DMA_LLIST_END BIT(19)
#define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)
/* SPRD_DMA_CHN_BLK_LEN register definition */
@@ -164,6 +165,7 @@ struct sprd_dma_desc {
struct sprd_dma_chn {
struct virt_dma_chanvc;
void __iomem*chn_base;
+ struct sprd_dma_linklistlinklist;
struct dma_slave_config slave_cfg;
u32 chn_num;
u32 dev_id;
@@ -582,7 +584,8 @@ static int sprd_dma_get_step(enum dma_slave_buswidth
buswidth)
}
static int sprd_dma_fill_desc(struct dma_chan *chan,
- struct sprd_dma_desc *sdesc,
+ struct sprd_dma_chn_hw *hw,
+ unsigned int sglen, int sg_index,
dma_addr_t src, dma_addr_t dst, u32 len,
enum dma_transfer_direction dir,
unsigned long flags,
@@ -590,7 +593,6 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
{
struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
- struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
u32 int_mode = flags & SPRD_DMA_INT_MASK;
int src_datawidth, dst_datawidth, src_step, dst_step;
@@ -670,12 +672,52 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) <<
SPRD_DMA_SRC_TRSF_STEP_OFFSET;
hw->trsf_step = temp;
+ /* link-list configuration */
+ if (schan->linklist.phy_addr) {
+ if (sg_index == sglen - 1)
+ hw->frg_len |= SPRD_DMA_LLIST_END;
+
+ hw->cfg |= SPRD_DMA_LINKLIST_EN;
+
+ /* link-list index */
+ temp = (sg_index + 1) % sglen;
+ /* Next link-list configuration's physical address offset */
+ temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR;
+ /*
+* Set the link-list pointer point to next link-list
+* configuration's physical address.
+*/
+ hw->llist_ptr = schan->linklist.phy_addr + temp;
+ } else {
+ hw->llist_ptr = 0;
+ }
+
hw->frg_step = 0;
hw->src_blk_step = 0;
hw->des_blk_step = 0;
return 0;
}
+static int sprd_dma_fill_linklist_desc(struct dma_chan *chan,
+ unsigned int sglen, int sg_index,
+ dma_addr_t src, dma_addr_t dst, u32 len,
+ enum dma_transfer_direction dir,
+ unsigned long flags,
+ struct dma_slave_config *slave_cfg)
+{
+ struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
+ struct sprd_dma_chn_hw *hw;
+
+ if (!schan->linklist.virt_addr)
+ return -EINVAL;
+
+ hw = (struct sprd_dma_chn_hw *)(schan->linklist.virt_addr +
+ sg_index * sizeof(*hw));
+
+ return sprd_dma_fill_desc(chan, hw, sglen, sg_index, src, dst, len,
+ dir, flags, slave_cfg);
+}
+
static struct dma_async_tx_descriptor *
sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t
src,
size_t len, unsigned long flags)
@@ -744,10 +786,20 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
u32 len = 0;
int ret, i;
- /* TODO: now we only support one sg for each DM
Re: [PATCH 2/3] microblaze: Added system call table generation support
On 9.8.2018 07:27, Firoz Khan wrote: > The system call tables are in different format in all > architecture and it will be difficult to manually add or > modify the system calls in the respective files. To make > it easy by keeping a script and which'll generate the > header file and syscall table file so this change will > unify them across all architectures. > > The system call table generation script is added in > syscalls directory which contain the script to generate > both uapi header file system call table generation file > and syscall.tbl file which'll be the input for the scripts. > > syscall.tbl contains the list of available system calls > along with system call number and corresponding entry point. > Add a new system call in this architecture will be possible > by adding new entry in the syscall.tbl file. > > Adding a new table entry consisting of: > - System call number. > - ABI. > - System call name. > - Entry point name. > > syscallhdr.sh and syscalltbl.sh will generate uapi header- > unistd.h and syscall_table.h files respectively. File > syscall_table.h is included by syscall.S - the real system > call table. Both .sh files will parse the content syscall.tbl > to generate the header and table files. > > ARM, s390 and x86 architecuture does have the similar support. > I leverage their implementation to come up with a generic > solution. And this is the ground work for y2038 issue. We need > to change 52 system call implementation and this work will > reduce the effort by simply modify 52 entries in syscall.tbl. > > Signed-off-by: Firoz Khan > --- > arch/microblaze/kernel/syscalls/Makefile | 37 +++ > arch/microblaze/kernel/syscalls/syscall.tbl | 404 > ++ > arch/microblaze/kernel/syscalls/syscallhdr.sh | 33 +++ > arch/microblaze/kernel/syscalls/syscalltbl.sh | 28 ++ > 4 files changed, 502 insertions(+) > create mode 100644 arch/microblaze/kernel/syscalls/Makefile > create mode 100644 arch/microblaze/kernel/syscalls/syscall.tbl > create mode 100644 arch/microblaze/kernel/syscalls/syscallhdr.sh it is interesting that arm and x86 scripts and they are "almost" the same. Is there any plan to put these script to generic location instead of keeping the same copy in architecture? fileguard name contains hardcoded macro prefix where in arm there is uapi detection. The same should be done architecture and sholdn't matter if you define macro with or without value. > create mode 100644 arch/microblaze/kernel/syscalls/syscalltbl.sh > > diff --git a/arch/microblaze/kernel/syscalls/Makefile > b/arch/microblaze/kernel/syscalls/Makefile > new file mode 100644 > index 000..7624044 > --- /dev/null > +++ b/arch/microblaze/kernel/syscalls/Makefile > @@ -0,0 +1,37 @@ > +# SPDX-License-Identifier: GPL-2.0 > +out := arch/$(SRCARCH)/include/generated/asm > +uapi := arch/$(SRCARCH)/include/generated/uapi/asm > + > +_dummy := $(shell [ -d '$(uapi)' ] || mkdir -p '$(uapi)') \ > + $(shell [ -d '$(out)' ] || mkdir -p '$(out)') > + > +syscall := $(srctree)/$(src)/syscall.tbl > + > +syshdr := $(srctree)/$(src)/syscallhdr.sh > +systbl := $(srctree)/$(src)/syscalltbl.sh > + > +quiet_cmd_syshdr = SYSHDR $@ > + cmd_syshdr = $(CONFIG_SHELL) '$(syshdr)' '$<' '$@' \ > +'$(syshdr_abi_$(basetarget))' \ > +'$(syshdr_pfx_$(basetarget))' \ > +'$(syshdr_offset_$(basetarget))' > + > +quiet_cmd_systbl = SYSTBL $@ > + cmd_systbl = $(CONFIG_SHELL) '$(systbl)' '$<' '$@' \ > +'$(systbl_abi_$(basetarget))' > + > +$(uapi)/unistd_32.h: $(syscall) $(syshdr) > + $(call if_changed,syshdr) > + > +$(out)/syscall_table.h: $(syscall) $(systbl) > + $(call if_changed,systbl) > + > +uapisyshdr-y += unistd_32.h > +syshdr-y += syscall_table.h > + > +targets += $(uapisyshdr-y) $(syshdr-y) > + > +PHONY += all > +all: $(addprefix $(uapi)/,$(uapisyshdr-y)) > +all: $(addprefix $(out)/,$(syshdr-y)) > + @: > diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl > b/arch/microblaze/kernel/syscalls/syscall.tbl > new file mode 100644 > index 000..219d940 > --- /dev/null > +++ b/arch/microblaze/kernel/syscalls/syscall.tbl > @@ -0,0 +1,404 @@ > +# > +# Linux system call numbers and entry vectors > +# > +# The format is: > +# > +# > +# The abi is always common for this file. > +# > +0 common restart_syscall sys_restart_syscall > +1 common exitsys_exit > +2 common forksys_fork > +3 common readsys_read Arm(and partially s390) are using tabs for indentation. Any reason not to use it here too? Thanks, Michal
Re: [PATCH v5 5/5] Auto-detect whether a FPU exists
On Thu, Aug 09, 2018 at 02:43:36PM +0800, Alan Kao wrote: > It does look a little bit weird. Should I send a v6 for this? Yes, please resend the series or just this patch. I think the hswap.h definition should go away and we should just keep the switch_to.h one, even if that means including the header in another C file.
