[PATCH v2] vfio/pci: Mask buggy SR-IOV VF INTx support
The SR-IOV spec requires that VFs must report zero for the INTx pin
register as VFs are precluded from INTx support. It's much easier for
the host kernel to understand whether a device is a VF and therefore
whether a non-zero pin register value is bogus than it is to do the
same in userspace. Override the INTx count for such devices and
virtualize the pin register to provide a consistent view of the device
to the user.
As this is clearly a spec violation, warn about it to support hardware
validation, but also provide a known whitelist as it doesn't do much
good to continue complaining if the hardware vendor doesn't plan to
fix it.
Known devices with this issue: 8086:270c
Signed-off-by: Alex Williamson
---
v2:
Moved the warning to vfio_config_init(), so it triggers on device open and
no longer depends on the user looking at the number of INTx IRQs available.
Also changed from dev_warn_once() to pci_warn() as this new location seems
sufficiently low frequency to nag repeatedly. Please test. Thanks,
Alex
drivers/vfio/pci/vfio_pci.c|8 ++--
drivers/vfio/pci/vfio_pci_config.c | 27 +++
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c
index cddb453a1ba5..50cdedfca9fe 100644
--- a/drivers/vfio/pci/vfio_pci.c
+++ b/drivers/vfio/pci/vfio_pci.c
@@ -434,10 +434,14 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device
*vdev, int irq_type)
{
if (irq_type == VFIO_PCI_INTX_IRQ_INDEX) {
u8 pin;
+
+ if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) ||
+ vdev->nointx || vdev->pdev->is_virtfn)
+ return 0;
+
pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin);
- if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && !vdev->nointx && pin)
- return 1;
+ return pin ? 1 : 0;
} else if (irq_type == VFIO_PCI_MSI_IRQ_INDEX) {
u8 pos;
u16 flags;
diff --git a/drivers/vfio/pci/vfio_pci_config.c
b/drivers/vfio/pci/vfio_pci_config.c
index 62023b4a373b..423ea1f98441 100644
--- a/drivers/vfio/pci/vfio_pci_config.c
+++ b/drivers/vfio/pci/vfio_pci_config.c
@@ -1611,6 +1611,15 @@ static int vfio_ecap_init(struct vfio_pci_device *vdev)
return 0;
}
+/*
+ * Nag about hardware bugs, hopefully to have vendors fix them, but at least
+ * to collect a list of dependencies for the VF INTx pin quirk below.
+ */
+static const struct pci_device_id known_bogus_vf_intx_pin[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
+ {}
+};
+
/*
* For each device we allocate a pci_config_map that indicates the
* capability occupying each dword and thus the struct perm_bits we
@@ -1676,6 +1685,24 @@ int vfio_config_init(struct vfio_pci_device *vdev)
if (pdev->is_virtfn) {
*(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
+
+ /*
+* Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
+* does not apply to VFs and VFs must implement this register
+* as read-only with value zero. Userspace is not readily able
+* to identify whether a device is a VF and thus that the pin
+* definition on the device is bogus should it violate this
+* requirement. We already virtualize the pin register for
+* other purposes, so we simply need to replace the bogus value
+* and consider VFs when we determine INTx IRQ count.
+*/
+ if (vconfig[PCI_INTERRUPT_PIN] &&
+ !pci_match_id(known_bogus_vf_intx_pin, pdev))
+ pci_warn(pdev,
+"Hardware bug: VF reports bogus INTx pin %d\n",
+vconfig[PCI_INTERRUPT_PIN]);
+
+ vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
}
if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
[PATCHv2 0/7] mm: faster get user pages
Changes since v1: Fixed shift size for following huge PMD on powerpc Updated change log with addition justification details Keith Busch (7): mm/gup_benchmark: Time put_page mm/gup_benchmark: Add additional pinning methods tools/gup_benchmark: Fix 'write' flag usage tools/gup_benchmark: Allow user specified file tools/gup_benchmark: Add parameter for hugetlb mm/gup: Combine parameters into struct mm/gup: Cache dev_pagemap while pinning pages include/linux/huge_mm.h| 12 +- include/linux/hugetlb.h| 2 +- include/linux/mm.h | 27 ++- mm/gup.c | 279 ++--- mm/gup_benchmark.c | 36 +++- mm/huge_memory.c | 67 --- mm/nommu.c | 6 +- tools/testing/selftests/vm/gup_benchmark.c | 40 - 8 files changed, 262 insertions(+), 207 deletions(-) -- 2.14.4
[PATCHv2 4/7] tools/gup_benchmark: Allow user specified file
The gup benchmark by default maps anonymous memory. This patch allows a
user to specify a file to map, providing a means to test various
file backings, like device and filesystem DAX.
Cc: Kirill Shutemov
Cc: Dave Hansen
Cc: Dan Williams
Signed-off-by: Keith Busch
---
tools/testing/selftests/vm/gup_benchmark.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tools/testing/selftests/vm/gup_benchmark.c
b/tools/testing/selftests/vm/gup_benchmark.c
index b2082df8beb4..f2c99e2436f8 100644
--- a/tools/testing/selftests/vm/gup_benchmark.c
+++ b/tools/testing/selftests/vm/gup_benchmark.c
@@ -33,9 +33,12 @@ int main(int argc, char **argv)
unsigned long size = 128 * MB;
int i, fd, opt, nr_pages = 1, thp = -1, repeats = 1, write = 0;
int cmd = GUP_FAST_BENCHMARK;
+ int file_map = -1;
+ int flags = MAP_ANONYMOUS | MAP_PRIVATE;
+ char *file = NULL;
char *p;
- while ((opt = getopt(argc, argv, "m:r:n:tTLU")) != -1) {
+ while ((opt = getopt(argc, argv, "m:r:n:f:tTLU")) != -1) {
switch (opt) {
case 'm':
size = atoi(optarg) * MB;
@@ -61,11 +64,22 @@ int main(int argc, char **argv)
case 'w':
write = 1;
break;
+ case 'f':
+ file = optarg;
+ flags &= ~(MAP_PRIVATE | MAP_ANONYMOUS);
+ flags |= MAP_SHARED;
+ break;
default:
return -1;
}
}
+ if (file) {
+ file_map = open(file, O_RDWR|O_CREAT);
+ if (file_map < 0)
+ perror("open"), exit(file_map);
+ }
+
gup.nr_pages_per_call = nr_pages;
gup.flags = write;
@@ -73,8 +87,7 @@ int main(int argc, char **argv)
if (fd == -1)
perror("open"), exit(1);
- p = mmap(NULL, size, PROT_READ | PROT_WRITE,
- MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+ p = mmap(NULL, size, PROT_READ | PROT_WRITE, flags, file_map, 0);
if (p == MAP_FAILED)
perror("mmap"), exit(1);
gup.addr = (unsigned long)p;
--
2.14.4
[PATCHv2 7/7] mm/gup: Cache dev_pagemap while pinning pages
Pinning pages from ZONE_DEVICE memory needs to check the backing device's
live-ness, which is tracked in the device's dev_pagemap metadata. This
metadata is stored in a radix tree and looking it up adds measurable
software overhead.
This patch avoids repeating this relatively costly operation when
dev_pagemap is used by caching the last dev_pagemap while getting user
pages. The gup_benchmark reports this reduces the time to get user pages
to as low as 1/3 of the previous time.
Cc: Kirill Shutemov
Cc: Dave Hansen
Cc: Dan Williams
Signed-off-by: Keith Busch
---
include/linux/mm.h | 8 +++-
mm/gup.c | 41 -
mm/huge_memory.c | 35 +++
3 files changed, 46 insertions(+), 38 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index f1fd241c9071..d688e18a19c4 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -380,6 +380,7 @@ struct vm_fault {
struct follow_page_context {
struct vm_area_struct *vma;
+ struct dev_pagemap *pgmap;
unsigned long address;
unsigned int page_mask;
unsigned int flags;
@@ -2546,14 +2547,19 @@ struct page *follow_page_mask(struct
follow_page_context *ctx);
static inline struct page *follow_page(struct vm_area_struct *vma,
unsigned long address, unsigned int foll_flags)
{
+ struct page *page;
struct follow_page_context ctx = {
.vma = vma,
+ .pgmap = NULL,
.address = address,
.page_mask = 0,
.flags = foll_flags,
};
- return follow_page_mask(&ctx);
+ page = follow_page_mask(&ctx);
+ if (ctx.pgmap)
+ put_dev_pagemap(ctx.pgmap);
+ return page;
}
#define FOLL_WRITE 0x01/* check pte is writable */
diff --git a/mm/gup.c b/mm/gup.c
index 4c4da54f8dbe..c98ea05eaa59 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -72,7 +72,6 @@ static inline bool can_follow_write_pte(pte_t pte, unsigned
int flags)
static struct page *follow_page_pte(struct follow_page_context *ctx, pmd_t
*pmd)
{
struct mm_struct *mm = ctx->vma->vm_mm;
- struct dev_pagemap *pgmap = NULL;
struct page *page;
spinlock_t *ptl;
pte_t *ptep, pte;
@@ -114,8 +113,8 @@ static struct page *follow_page_pte(struct
follow_page_context *ctx, pmd_t *pmd)
* Only return device mapping pages in the FOLL_GET case since
* they are only valid while holding the pgmap reference.
*/
- pgmap = get_dev_pagemap(pte_pfn(pte), NULL);
- if (pgmap)
+ ctx->pgmap = get_dev_pagemap(pte_pfn(pte), ctx->pgmap);
+ if (ctx->pgmap)
page = pte_page(pte);
else
goto no_page;
@@ -154,9 +153,9 @@ static struct page *follow_page_pte(struct
follow_page_context *ctx, pmd_t *pmd)
get_page(page);
/* drop the pgmap reference now that we hold the page */
- if (pgmap) {
- put_dev_pagemap(pgmap);
- pgmap = NULL;
+ if (ctx->pgmap) {
+ put_dev_pagemap(ctx->pgmap);
+ ctx->pgmap = NULL;
}
}
if (ctx->flags & FOLL_TOUCH) {
@@ -645,7 +644,7 @@ static long __get_user_pages(struct task_struct *tsk,
struct mm_struct *mm,
unsigned int gup_flags, struct page **pages,
struct vm_area_struct **vmas, int *nonblocking)
{
- long i = 0;
+ long ret = 0, i = 0;
struct vm_area_struct *vma = NULL;
struct follow_page_context ctx = {};
@@ -681,8 +680,10 @@ static long __get_user_pages(struct task_struct *tsk,
struct mm_struct *mm,
goto next_page;
}
- if (!vma || check_vma_flags(vma, gup_flags))
- return i ? : -EFAULT;
+ if (!vma || check_vma_flags(vma, gup_flags)) {
+ ret = -EFAULT;
+ goto out;
+ }
if (is_vm_hugetlb_page(vma)) {
i = follow_hugetlb_page(mm, vma, pages, vmas,
&start, &nr_pages, i,
@@ -697,23 +698,25 @@ static long __get_user_pages(struct task_struct *tsk,
struct mm_struct *mm,
* If we have a pending SIGKILL, don't keep faulting pages and
* potentially allocating memory.
*/
- if (unlikely(fatal_signal_pending(current)))
- return i ? i : -ERESTARTSYS;
+ if (unlikely(fatal_signal_pending(current))) {
+ ret = -ERESTARTSYS;
+ goto out;
+ }
cond_res
[PATCHv2 1/7] mm/gup_benchmark: Time put_page
We'd like to measure time to unpin user pages, so this adds a second
benchmark timer on put_page, separate from get_page.
Adding the field will breaks this ioctl ABI, but should be okay since
this an in-tree kernel selftest.
Cc: Kirill Shutemov
Cc: Dave Hansen
Cc: Dan Williams
Signed-off-by: Keith Busch
---
mm/gup_benchmark.c | 8 ++--
tools/testing/selftests/vm/gup_benchmark.c | 6 --
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/mm/gup_benchmark.c b/mm/gup_benchmark.c
index 6a473709e9b6..76cd35e477af 100644
--- a/mm/gup_benchmark.c
+++ b/mm/gup_benchmark.c
@@ -8,7 +8,8 @@
#define GUP_FAST_BENCHMARK _IOWR('g', 1, struct gup_benchmark)
struct gup_benchmark {
- __u64 delta_usec;
+ __u64 get_delta_usec;
+ __u64 put_delta_usec;
__u64 addr;
__u64 size;
__u32 nr_pages_per_call;
@@ -47,14 +48,17 @@ static int __gup_benchmark_ioctl(unsigned int cmd,
}
end_time = ktime_get();
- gup->delta_usec = ktime_us_delta(end_time, start_time);
+ gup->get_delta_usec = ktime_us_delta(end_time, start_time);
gup->size = addr - gup->addr;
+ start_time = ktime_get();
for (i = 0; i < nr_pages; i++) {
if (!pages[i])
break;
put_page(pages[i]);
}
+ end_time = ktime_get();
+ gup->put_delta_usec = ktime_us_delta(end_time, start_time);
kvfree(pages);
return 0;
diff --git a/tools/testing/selftests/vm/gup_benchmark.c
b/tools/testing/selftests/vm/gup_benchmark.c
index 36df55132036..bdcb97acd0ac 100644
--- a/tools/testing/selftests/vm/gup_benchmark.c
+++ b/tools/testing/selftests/vm/gup_benchmark.c
@@ -17,7 +17,8 @@
#define GUP_FAST_BENCHMARK _IOWR('g', 1, struct gup_benchmark)
struct gup_benchmark {
- __u64 delta_usec;
+ __u64 get_delta_usec;
+ __u64 put_delta_usec;
__u64 addr;
__u64 size;
__u32 nr_pages_per_call;
@@ -81,7 +82,8 @@ int main(int argc, char **argv)
if (ioctl(fd, GUP_FAST_BENCHMARK, &gup))
perror("ioctl"), exit(1);
- printf("Time: %lld us", gup.delta_usec);
+ printf("Time: get:%lld put:%lld us", gup.get_delta_usec,
+ gup.put_delta_usec);
if (gup.size != size)
printf(", truncated (size: %lld)", gup.size);
printf("\n");
--
2.14.4
[PATCHv2 3/7] tools/gup_benchmark: Fix 'write' flag usage
If the '-w' parameter was provided, the benchmark would exit due to a mssing 'break'. Cc: Kirill Shutemov Cc: Dave Hansen Cc: Dan Williams Signed-off-by: Keith Busch --- tools/testing/selftests/vm/gup_benchmark.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/vm/gup_benchmark.c b/tools/testing/selftests/vm/gup_benchmark.c index c2f785ded9b9..b2082df8beb4 100644 --- a/tools/testing/selftests/vm/gup_benchmark.c +++ b/tools/testing/selftests/vm/gup_benchmark.c @@ -60,6 +60,7 @@ int main(int argc, char **argv) break; case 'w': write = 1; + break; default: return -1; } -- 2.14.4
[PATCHv2 6/7] mm/gup: Combine parameters into struct
This will make it easier to add new parameters that we may wish to
thread through these function calls.
Cc: Kirill Shutemov
Cc: Dave Hansen
Cc: Dan Williams
Signed-off-by: Keith Busch
---
include/linux/huge_mm.h | 12 +--
include/linux/hugetlb.h | 2 +-
include/linux/mm.h | 21 -
mm/gup.c| 238 +++-
mm/huge_memory.c| 32 +++
mm/nommu.c | 6 +-
6 files changed, 151 insertions(+), 160 deletions(-)
diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
index 99c19b06d9a4..7d22e2c7f154 100644
--- a/include/linux/huge_mm.h
+++ b/include/linux/huge_mm.h
@@ -212,10 +212,8 @@ static inline int hpage_nr_pages(struct page *page)
return 1;
}
-struct page *follow_devmap_pmd(struct vm_area_struct *vma, unsigned long addr,
- pmd_t *pmd, int flags);
-struct page *follow_devmap_pud(struct vm_area_struct *vma, unsigned long addr,
- pud_t *pud, int flags);
+struct page *follow_devmap_pmd(struct follow_page_context *ctx, pmd_t *pmd);
+struct page *follow_devmap_pud(struct follow_page_context *ctx, pud_t *pud);
extern vm_fault_t do_huge_pmd_numa_page(struct vm_fault *vmf, pmd_t orig_pmd);
@@ -343,14 +341,12 @@ static inline void mm_put_huge_zero_page(struct mm_struct
*mm)
return;
}
-static inline struct page *follow_devmap_pmd(struct vm_area_struct *vma,
- unsigned long addr, pmd_t *pmd, int flags)
+static inline struct page *follow_devmap_pmd(struct gup_context *ctx, pmd_t
*pmd)
{
return NULL;
}
-static inline struct page *follow_devmap_pud(struct vm_area_struct *vma,
- unsigned long addr, pud_t *pud, int flags)
+static inline struct page *follow_devmap_pud(struct gup_context *ctx, pud_t
*pud)
{
return NULL;
}
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6b68e345f0ca..64b675863793 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -180,7 +180,7 @@ static inline void hugetlb_report_meminfo(struct seq_file
*m)
static inline void hugetlb_show_meminfo(void)
{
}
-#define follow_huge_pd(vma, addr, hpd, flags, pdshift) NULL
+#define follow_huge_pd(ctx, hpd, pdshift) NULL
#define follow_huge_pmd(mm, addr, pmd, flags) NULL
#define follow_huge_pud(mm, addr, pud, flags) NULL
#define follow_huge_pgd(mm, addr, pgd, flags) NULL
diff --git a/include/linux/mm.h b/include/linux/mm.h
index a61ebe8ad4ca..f1fd241c9071 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -378,6 +378,13 @@ struct vm_fault {
*/
};
+struct follow_page_context {
+ struct vm_area_struct *vma;
+ unsigned long address;
+ unsigned int page_mask;
+ unsigned int flags;
+};
+
/* page entry size for vm->huge_fault() */
enum page_entry_size {
PE_SIZE_PTE = 0,
@@ -2534,15 +2541,19 @@ static inline vm_fault_t vmf_error(int err)
return VM_FAULT_SIGBUS;
}
-struct page *follow_page_mask(struct vm_area_struct *vma,
- unsigned long address, unsigned int foll_flags,
- unsigned int *page_mask);
+struct page *follow_page_mask(struct follow_page_context *ctx);
static inline struct page *follow_page(struct vm_area_struct *vma,
unsigned long address, unsigned int foll_flags)
{
- unsigned int unused_page_mask;
- return follow_page_mask(vma, address, foll_flags, &unused_page_mask);
+ struct follow_page_context ctx = {
+ .vma = vma,
+ .address = address,
+ .page_mask = 0,
+ .flags = foll_flags,
+ };
+
+ return follow_page_mask(&ctx);
}
#define FOLL_WRITE 0x01/* check pte is writable */
diff --git a/mm/gup.c b/mm/gup.c
index 1abc8b4afff6..4c4da54f8dbe 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -20,8 +20,7 @@
#include "internal.h"
-static struct page *no_page_table(struct vm_area_struct *vma,
- unsigned int flags)
+static struct page *no_page_table(struct follow_page_context *ctx)
{
/*
* When core dumping an enormous anonymous area that nobody
@@ -31,28 +30,28 @@ static struct page *no_page_table(struct vm_area_struct
*vma,
* But we can only make this optimization where a hole would surely
* be zero-filled if handle_mm_fault() actually did handle it.
*/
- if ((flags & FOLL_DUMP) && (!vma->vm_ops || !vma->vm_ops->fault))
+ if ((ctx->flags & FOLL_DUMP) && (!ctx->vma->vm_ops ||
+!ctx->vma->vm_ops->fault))
return ERR_PTR(-EFAULT);
return NULL;
}
-static int follow_pfn_pte(struct vm_area_struct *vma, unsigned long address,
- pte_t *pte, unsigned int flags)
+static int follow_pfn_pte(struct follow_page_context *ctx, pte_t *pte)
{
/* No page to get reference */
- if (flags & FOLL_GET)
+
[PATCH v2] slub: extend slub debug to handle multiple slabs
Extend the slub_debug syntax to "slub_debug=[,]*", where
may contain an asterisk at the end. For example, the following would poison
all kmalloc slabs:
slub_debug=P,kmalloc*
and the following would apply the default flags to all kmalloc and all block IO
slabs:
slub_debug=,bio*,kmalloc*
Please note that a similar patch was posted by Iliyan Malchev some time ago but
was never merged:
https://marc.info/?l=linux-mm&m=131283905330474&w=2
Signed-off-by: Aaron Tomlin
---
Changes from v1 [1]:
- Add appropriate cast to address compiler warning
[1]: https://lore.kernel.org/lkml/20180910111358.10539-1-atom...@redhat.com/
---
Documentation/vm/slub.rst | 12 +---
mm/slub.c | 34 +++---
2 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/Documentation/vm/slub.rst b/Documentation/vm/slub.rst
index 3a775fd64e2d..195928808bac 100644
--- a/Documentation/vm/slub.rst
+++ b/Documentation/vm/slub.rst
@@ -36,9 +36,10 @@ debugging is enabled. Format:
slub_debug=
Enable options for all slabs
-slub_debug=,
- Enable options only for select slabs
+slub_debug=,,,...
+ Enable options only for select slabs (no spaces
+ after a comma)
Possible debug options are::
@@ -62,7 +63,12 @@ Trying to find an issue in the dentry cache? Try::
slub_debug=,dentry
-to only enable debugging on the dentry cache.
+to only enable debugging on the dentry cache. You may use an asterisk at the
+end of the slab name, in order to cover all slabs with the same prefix. For
+example, here's how you can poison the dentry cache as well as all kmalloc
+slabs:
+
+ slub_debug=P,kmalloc-*,dentry
Red zoning and tracking may realign the slab. We can just apply sanity checks
to the dentry cache with::
diff --git a/mm/slub.c b/mm/slub.c
index 8da34a8af53d..d20901514075 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1283,9 +1283,37 @@ slab_flags_t kmem_cache_flags(unsigned int object_size,
/*
* Enable debugging if selected on the kernel commandline.
*/
- if (slub_debug && (!slub_debug_slabs || (name &&
- !strncmp(slub_debug_slabs, name, strlen(slub_debug_slabs)
- flags |= slub_debug;
+
+ char *end, *n, *glob;
+ int len = strlen(name);
+
+ /* If slub_debug = 0, it folds into the if conditional. */
+ if (!slub_debug_slabs)
+ return flags | slub_debug;
+
+ n = slub_debug_slabs;
+ while (*n) {
+ int cmplen;
+
+ end = strchr(n, ',');
+ if (!end)
+ end = n + strlen(n);
+
+ glob = strnchr(n, end - n, '*');
+ if (glob)
+ cmplen = glob - n;
+ else
+ cmplen = max(len, (int)(end - n));
+
+ if (!strncmp(name, n, cmplen)) {
+ flags |= slub_debug;
+ break;
+ }
+
+ if (!*end)
+ break;
+ n = end + 1;
+ }
return flags;
}
--
2.14.4
[tip:x86/urgent] x86/intel_rdt: Add Reinette as co-maintainer for RDT
Commit-ID: a8b3bb338e4ee4cc84a2b9a6fdf27049b84baa59 Gitweb: https://git.kernel.org/tip/a8b3bb338e4ee4cc84a2b9a6fdf27049b84baa59 Author: Fenghua Yu AuthorDate: Thu, 20 Sep 2018 12:37:08 -0700 Committer: Thomas Gleixner CommitDate: Thu, 20 Sep 2018 21:44:35 +0200 x86/intel_rdt: Add Reinette as co-maintainer for RDT Reinette Chatre is doing great job on enabling pseudo-locking and other features in RDT. Add her as co-maintainer for RDT. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Signed-off-by: Thomas Gleixner Acked-by: Ingo Molnar Acked-by: Reinette Chatre Cc: "H Peter Anvin" Cc: "Tony Luck" Link: https://lkml.kernel.org/r/1537472228-221799-1-git-send-email-fenghua...@intel.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 091e66b60cd2..140ea6ee3ac8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12260,6 +12260,7 @@ F: Documentation/networking/rds.txt RDT - RESOURCE ALLOCATION M: Fenghua Yu +M: Reinette Chatre L: linux-kernel@vger.kernel.org S: Supported F: arch/x86/kernel/cpu/intel_rdt*
Re: [PATCH v2 0/8] gpio-addr-flash: Support for device-tree and cleanup
Ping? No comments? Thanks! On Wed, Sep 5, 2018 at 4:36 PM Ricardo Ribalda Delgado wrote: > > This patch series does the following: > > 1) Fix bug regarding ioremap size > 2) Cleanup code to use new APIs > 3) Simplify numerical operations > 4) Add support for device-tree devices > > Thanks! > > Changelog v2: > > From Boris Brezillon: > -Add Fixes and cc:stable > > From kbuild: > - Fix warnings > > - Rebase > > Ricardo Ribalda Delgado (8): > mtd: maps: gpio-addr-flash: Replace custom printk > mtd: maps: gpio-addr-flash: Fix ioremapped size > mtd: maps: gpio-addr-flash: Use devm_* functions > mtd: maps: gpio-addr-flash: Use order insted of size > mtd: maps: gpio-addr-flash: Replace array with an integer > mtd: maps: gpio-addr-flash: Split allocation in two > mtd: maps: gpio-addr-flash: Add support for device-tree devices > dt-binding: mtd: Document gpio-addr-flash > > .../bindings/mtd/gpio-addr-flash.txt | 46 +++ > drivers/mtd/maps/gpio-addr-flash.c| 276 -- > 2 files changed, 236 insertions(+), 86 deletions(-) > create mode 100644 Documentation/devicetree/bindings/mtd/gpio-addr-flash.txt > > -- > 2.18.0 > -- Ricardo Ribalda
[PATCH] x86/intel_rdt: Add Reinette as co-maintainer for RDT
Reinette Chatre is doing great job on enabling pseudo-locking and other features in RDT. Add her as co-maintainer for RDT. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Acked-by: Ingo Molnar Acked-by: Reinette Chatre --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4ece30f15777..c884dc08a580 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12260,6 +12260,7 @@ F: Documentation/networking/rds.txt RDT - RESOURCE ALLOCATION M: Fenghua Yu +M: Reinette Chatre L: linux-kernel@vger.kernel.org S: Supported F: arch/x86/kernel/cpu/intel_rdt* -- 2.5.0
[PATCH 04/44] coresight: platform: Fix leaking device reference
From: Suzuki K Poulose We don't drop the reference on the remote device while parsing the connection, held by bus_find_device(). Fix this by duplicating the device name and dropping the reference. Cc: Mathieu Poirier Cc: Kim Phillips Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 28d3aef1660b..4b279f8fea0c 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -162,7 +162,9 @@ static int of_coresight_parse_endpoint(struct device *dev, } pdata->outports[i] = endpoint.port; - pdata->child_names[i] = dev_name(rdev); + pdata->child_names[i] = devm_kstrdup(dev, +dev_name(rdev), +GFP_KERNEL); pdata->child_ports[i] = rendpoint.id; /* Connection record updated */ ret = 1; @@ -172,6 +174,8 @@ static int of_coresight_parse_endpoint(struct device *dev, of_node_put(rparent); if (rport) of_node_put(rport); + if (rdev) + put_device(rdev); return ret; } -- 2.7.4
[PATCH 02/44] coresight: platform: Refactor graph endpoint parsing
From: Suzuki K Poulose
Refactor the of graph endpoint parsing code, to make the error
handling easier.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 138 +
1 file changed, 83 insertions(+), 55 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 6880bee195c8..70205f3eae8e 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -114,17 +114,70 @@ int of_coresight_get_cpu(const struct device_node *node)
}
EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
+/*
+ * of_coresight_parse_endpoint : Parse the given output endpoint @ep
+ * and fill the connection information in @pdata[@i].
+ *
+ * Parses the local port, remote device name and the remote port.
+ *
+ * Returns :
+ * 1 - If the parsing is successful and a connection record
+ * was created for an output connection.
+ * 0 - If the parsing completed without any fatal errors.
+ * -Errno - Fatal error, abort the scanning.
+ */
+static int of_coresight_parse_endpoint(struct device *dev,
+ struct device_node *ep,
+ struct coresight_platform_data *pdata,
+ int i)
+{
+ int ret = 0;
+ struct of_endpoint endpoint, rendpoint;
+ struct device_node *rparent = NULL;
+ struct device_node *rport = NULL;
+ struct device *rdev = NULL;
+
+ do {
+ /* Parse the local port details */
+ if (of_graph_parse_endpoint(ep, &endpoint))
+ break;
+ /*
+* Get a handle on the remote port and parent
+* attached to it.
+*/
+ rparent = of_graph_get_remote_port_parent(ep);
+ if (!rparent)
+ break;
+ rport = of_graph_get_remote_port(ep);
+ if (!rport)
+ break;
+ if (of_graph_parse_endpoint(rport, &rendpoint))
+ break;
+
+ /* If the remote device is not available, defer probing */
+ rdev = of_coresight_get_endpoint_device(rparent);
+ if (!rdev) {
+ ret = -EPROBE_DEFER;
+ break;
+ }
+
+ pdata->outports[i] = endpoint.port;
+ pdata->child_names[i] = dev_name(rdev);
+ pdata->child_ports[i] = rendpoint.id;
+ /* Connection record updated */
+ ret = 1;
+ } while (0);
+
+ return ret;
+}
+
struct coresight_platform_data *
of_get_coresight_platform_data(struct device *dev,
const struct device_node *node)
{
int i = 0, ret = 0;
struct coresight_platform_data *pdata;
- struct of_endpoint endpoint, rendpoint;
- struct device *rdev;
struct device_node *ep = NULL;
- struct device_node *rparent = NULL;
- struct device_node *rport = NULL;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
@@ -132,64 +185,39 @@ of_get_coresight_platform_data(struct device *dev,
/* Use device name as sysfs handle */
pdata->name = dev_name(dev);
+ pdata->cpu = of_coresight_get_cpu(node);
/* Get the number of input and output port for this component */
of_coresight_get_ports(node, &pdata->nr_inport, &pdata->nr_outport);
- if (pdata->nr_outport) {
- ret = of_coresight_alloc_memory(dev, pdata);
- if (ret)
+ /* If there are no output connections, we are done */
+ if (!pdata->nr_outport)
+ return pdata;
+
+ ret = of_coresight_alloc_memory(dev, pdata);
+ if (ret)
+ return ERR_PTR(ret);
+
+ /* Iterate through each port to discover topology */
+ while ((ep = of_graph_get_next_endpoint(node, ep))) {
+ /*
+* No need to deal with input ports, as processing the
+* output ports connected to them will process the details.
+*/
+ if (of_find_property(ep, "slave-mode", NULL))
+ continue;
+
+ ret = of_coresight_parse_endpoint(dev, ep, pdata, i);
+ switch (ret) {
+ case 1:
+ i++;/* Fall through */
+ case 0:
+ break;
+ default:
return ERR_PTR(ret);
-
- /* Iterate through each port to discover topology */
- do {
- /* Get a handle on a port */
- ep = of_graph_get_next_endpoint(node, ep);
- if (!ep)
-
[PATCH 07/44] coresight: platform: Cleanup coresight connection handling
From: Suzuki K Poulose
The platform code parses the component connections and populates
a platform-description of the output connections in arrays of fields
(which is never freed). This is later copied in the coresight_register
to a newly allocated area, represented by coresight_connection(s).
This patch cleans up the code dealing with connections by making
use of the "coresight_connection" structure right at the platform
code and lets the generic driver simply re-use information provided
by the platform.
Thus making it reader friendly as well as avoiding the wastage of
unused memory.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c| 21 +---
drivers/hwtracing/coresight/of_coresight.c | 53 +++---
include/linux/coresight.h | 9 ++---
3 files changed, 22 insertions(+), 61 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index 9fd0c387e678..5e8880ca8078 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -995,13 +995,11 @@ postcore_initcall(coresight_init);
struct coresight_device *coresight_register(struct coresight_desc *desc)
{
- int i;
int ret;
int link_subtype;
int nr_refcnts = 1;
atomic_t *refcnts = NULL;
struct coresight_device *csdev;
- struct coresight_connection *conns = NULL;
csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
if (!csdev) {
@@ -1030,22 +1028,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
csdev->nr_inport = desc->pdata->nr_inport;
csdev->nr_outport = desc->pdata->nr_outport;
- /* Initialise connections if there is at least one outport */
- if (csdev->nr_outport) {
- conns = kcalloc(csdev->nr_outport, sizeof(*conns), GFP_KERNEL);
- if (!conns) {
- ret = -ENOMEM;
- goto err_free_refcnts;
- }
-
- for (i = 0; i < csdev->nr_outport; i++) {
- conns[i].outport = desc->pdata->outports[i];
- conns[i].child_name = desc->pdata->child_names[i];
- conns[i].child_port = desc->pdata->child_ports[i];
- }
- }
-
- csdev->conns = conns;
+ csdev->conns = desc->pdata->conns;
csdev->type = desc->type;
csdev->subtype = desc->subtype;
@@ -1078,8 +1061,6 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
return csdev;
-err_free_refcnts:
- kfree(refcnts);
err_free_csdev:
kfree(csdev);
err_out:
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 44903d35009f..e8fb4e124744 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -75,29 +75,13 @@ static void of_coresight_get_ports(const struct device_node
*node,
static int of_coresight_alloc_memory(struct device *dev,
struct coresight_platform_data *pdata)
{
- /* List of output port on this component */
- pdata->outports = devm_kcalloc(dev,
- pdata->nr_outport,
- sizeof(*pdata->outports),
- GFP_KERNEL);
- if (!pdata->outports)
- return -ENOMEM;
-
- /* Children connected to this component via @outports */
- pdata->child_names = devm_kcalloc(dev,
- pdata->nr_outport,
- sizeof(*pdata->child_names),
- GFP_KERNEL);
- if (!pdata->child_names)
- return -ENOMEM;
-
- /* Port number on the child this component is connected to */
- pdata->child_ports = devm_kcalloc(dev,
- pdata->nr_outport,
- sizeof(*pdata->child_ports),
- GFP_KERNEL);
- if (!pdata->child_ports)
- return -ENOMEM;
+ if (pdata->nr_outport) {
+ pdata->conns = devm_kzalloc(dev, pdata->nr_outport *
+ sizeof(*pdata->conns),
+ GFP_KERNEL);
+ if (!pdata->conns)
+ return -ENOMEM;
+ }
return 0;
}
@@ -121,7 +105,7 @@ EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
/*
* of_coresight_parse_endpoint : Parse the given output endpoint @ep
- * and fill the connection information in @pdata[@i].
+ * and fill the connection information in @conn
*
* Parses the local port, remote device name and the remote port.
*
@@ -133,8 +117,7 @@ EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
*/
[PATCH 08/44] coresight: Cleanup coresight DT bindings
From: Suzuki K Poulose
The coresight drivers relied on default bindings for graph
in DT, while reusing the "reg" field of the "ports" to indicate
the actual hardware port number for the connections. This can
cause duplicate ports with same addresses, but different
direction. However, with the rules getting stricter for the
address mismatch with the label, it is no longer possible to use
the port address field for the hardware port number.
This patch introduces new DT binding rules for coresight
components, based on the same generic DT graph bindings, but
avoiding the address duplication.
- All output ports must be specified under a child node with
name "out-ports".
- All input ports must be specified under a childe node with
name "in-ports".
- Port address should match the hardware port number.
The support for legacy bindings is retained, with a warning.
Cc: Sudeep Holla
Cc: Rob Herring
Signed-off-by: Suzuki K Poulose
Reviewed-by: Rob Herring
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 95 -
drivers/hwtracing/coresight/of_coresight.c | 98 +++---
2 files changed, 143 insertions(+), 50 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index 5d1ad09bafb4..f39d2c6eb49c 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -54,9 +54,7 @@ its hardware characteristcs.
clocks the core of that coresight component. The latter clock
is optional.
- * port or ports: The representation of the component's port
- layout using the generic DT graph presentation found in
- "bindings/graph.txt".
+ * port or ports: see "Graph bindings for Coresight" below.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
@@ -73,7 +71,7 @@ its hardware characteristcs.
AMBA markee):
- "arm,coresight-replicator"
- * port or ports: same as above.
+ * port or ports: see "Graph bindings for Coresight" below.
* Optional properties for ETM/PTMs:
@@ -96,6 +94,20 @@ its hardware characteristcs.
* interrupts : Exactly one SPI may be listed for reporting the address
error
+Graph bindings for Coresight
+---
+
+Coresight components are interconnected to create a data path for the flow of
+trace data generated from the "sources" to their collection points "sink".
+Each coresight component must describe the "input" and "output" connections.
+The connections must be described via generic DT graph bindings as described
+by the "bindings/graph.txt", where each "port" along with an "endpoint"
+component represents a hardware port and the connection.
+
+ * All output ports must be listed inside a child node named "out-ports"
+ * All input ports must be listed inside a child node named "in-ports".
+ * Port address must match the hardware port number.
+
Example:
1. Sinks
@@ -105,10 +117,11 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- etb_in_port: endpoint@0 {
- slave-mode;
- remote-endpoint = <&replicator_out_port0>;
+ in-ports {
+ port {
+ etb_in_port: endpoint@0 {
+ remote-endpoint =
<&replicator_out_port0>;
+ };
};
};
};
@@ -119,10 +132,11 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- tpiu_in_port: endpoint@0 {
- slave-mode;
- remote-endpoint = <&replicator_out_port1>;
+ out-ports {
+ port {
+ tpiu_in_port: endpoint@0 {
+ remote-endpoint =
<&replicator_out_port1>;
+ };
};
};
};
@@ -163,7 +177,7 @@ Example:
*/
compatible = "arm,coresight-replicator";
- ports {
+ out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -181,12 +195,11 @@ Example:
remote-endpoint = <&tpiu_in_port>;
};
};
+ };
- /* replicator input port */
- port@2 {
- reg = <0>;
+ in-ports {
+ port {
[PATCH 10/44] coresight: Fix handling of sinks
From: Suzuki K Poulose
The coresight components could be operated either in sysfs mode or in perf
mode. For some of the components, the mode of operation doesn't matter as
they simply relay the data to the next component in the trace path. But for
sinks, they need to be able to provide the trace data back to the user.
Thus we need to make sure that "mode" is handled appropriately. e.g,
the sysfs mode could have multiple sources driving the trace data, while
perf mode doesn't allow sharing the sink.
The coresight_enable_sink() however doesn't really allow this check to
trigger as it skips the "enable_sink" callback if the component is
already enabled, irrespective of the mode. This could cause mixing
of data from different modes or even same mode (in perf), if the
sources are different. Also, if we fail to enable the sink while
enabling a path (where sink is the first component enabled),
we could end up in disabling the components in the "entire"
path which were not enabled in this trial, causing disruptions
in the existing trace paths.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index 5e8880ca8078..07382c55b31d 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -132,12 +132,14 @@ static int coresight_enable_sink(struct coresight_device
*csdev, u32 mode)
{
int ret;
- if (!csdev->enable) {
- if (sink_ops(csdev)->enable) {
- ret = sink_ops(csdev)->enable(csdev, mode);
- if (ret)
- return ret;
- }
+ /*
+* We need to make sure the "new" session is compatible with the
+* existing "mode" of operation.
+*/
+ if (sink_ops(csdev)->enable) {
+ ret = sink_ops(csdev)->enable(csdev, mode);
+ if (ret)
+ return ret;
csdev->enable = true;
}
@@ -339,8 +341,14 @@ int coresight_enable_path(struct list_head *path, u32 mode)
switch (type) {
case CORESIGHT_DEV_TYPE_SINK:
ret = coresight_enable_sink(csdev, mode);
+ /*
+* Sink is the first component turned on. If we
+* failed to enable the sink, there are no components
+* that need disabling. Disabling the path here
+* would mean we could disrupt an existing session.
+*/
if (ret)
- goto err;
+ goto out;
break;
case CORESIGHT_DEV_TYPE_SOURCE:
/* sources are enabled from either sysFS or Perf */
--
2.7.4
[PATCH 12/44] coresight: perf: Fix per cpu path management
From: Suzuki K Poulose
We create a coresight trace path for each online CPU when
we start the event. We rely on the number of online CPUs
and then go on to allocate an array matching the "number of
online CPUs" for holding the path and then uses normal
CPU id as the index to the array. This is problematic as
we could have some offline CPUs causing us to access beyond
the actual array size (e.g, on a dual SMP system, if CPU0 is
offline, CPU1 could be really accessing beyond the array).
The solution is to switch to per-cpu array for holding the path.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 55 +---
1 file changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 677695635211..6338dd180031 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -33,7 +34,7 @@ struct etm_event_data {
struct work_struct work;
cpumask_t mask;
void *snk_config;
- struct list_head **path;
+ struct list_head * __percpu *path;
};
static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
@@ -61,6 +62,18 @@ static const struct attribute_group *etm_pmu_attr_groups[] =
{
NULL,
};
+static inline struct list_head **
+etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu)
+{
+ return per_cpu_ptr(data->path, cpu);
+}
+
+static inline struct list_head *
+etm_event_cpu_path(struct etm_event_data *data, int cpu)
+{
+ return *etm_event_cpu_path_ptr(data, cpu);
+}
+
static void etm_event_read(struct perf_event *event) {}
static int etm_addr_filters_alloc(struct perf_event *event)
@@ -120,23 +133,26 @@ static void free_event_data(struct work_struct *work)
*/
if (event_data->snk_config) {
cpu = cpumask_first(mask);
- sink = coresight_get_sink(event_data->path[cpu]);
+ sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu));
if (sink_ops(sink)->free_buffer)
sink_ops(sink)->free_buffer(event_data->snk_config);
}
for_each_cpu(cpu, mask) {
- if (!(IS_ERR_OR_NULL(event_data->path[cpu])))
- coresight_release_path(event_data->path[cpu]);
+ struct list_head **ppath;
+
+ ppath = etm_event_cpu_path_ptr(event_data, cpu);
+ if (!(IS_ERR_OR_NULL(*ppath)))
+ coresight_release_path(*ppath);
+ *ppath = NULL;
}
- kfree(event_data->path);
+ free_percpu(event_data->path);
kfree(event_data);
}
static void *alloc_event_data(int cpu)
{
- int size;
cpumask_t *mask;
struct etm_event_data *event_data;
@@ -147,7 +163,6 @@ static void *alloc_event_data(int cpu)
/* Make sure nothing disappears under us */
get_online_cpus();
- size = num_online_cpus();
mask = &event_data->mask;
if (cpu != -1)
@@ -164,8 +179,8 @@ static void *alloc_event_data(int cpu)
* unused memory when dealing with single CPU trace scenarios is small
* compared to the cost of searching through an optimized array.
*/
- event_data->path = kcalloc(size,
- sizeof(struct list_head *), GFP_KERNEL);
+ event_data->path = alloc_percpu(struct list_head *);
+
if (!event_data->path) {
kfree(event_data);
return NULL;
@@ -213,6 +228,7 @@ static void *etm_setup_aux(int event_cpu, void **pages,
/* Setup the path for each CPU in a trace session */
for_each_cpu(cpu, mask) {
+ struct list_head *path;
struct coresight_device *csdev;
csdev = per_cpu(csdev_src, cpu);
@@ -224,9 +240,11 @@ static void *etm_setup_aux(int event_cpu, void **pages,
* list of devices from source to sink that can be
* referenced later when the path is actually needed.
*/
- event_data->path[cpu] = coresight_build_path(csdev, sink);
- if (IS_ERR(event_data->path[cpu]))
+ path = coresight_build_path(csdev, sink);
+ if (IS_ERR(path))
goto err;
+
+ *etm_event_cpu_path_ptr(event_data, cpu) = path;
}
if (!sink_ops(sink)->alloc_buffer)
@@ -255,6 +273,7 @@ static void etm_event_start(struct perf_event *event, int
flags)
struct etm_event_data *event_data;
struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
+ struct list_head *path
[PATCH 14/44] coresight: perf: Allow tracing on hotplugged CPUs
From: Suzuki K Poulose
At the moment, if there is no CPU specified for a given
event, we use cpu_online_mask and try to build path for
each of the CPUs in the mask. This could prevent any CPU
that is turned online later to be used for the tracing.
This patch changes to use the cpu_present_mask and tries
to build path for as much CPUs as possible ignoring the
failures in building path for some of the CPUs. If ever
we try to trace on those CPUs, we fail the operation.
Based on a patch from Mathieu Poirier.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 44
1 file changed, 29 insertions(+), 15 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 6beb662d230c..afe7e7fc1a93 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -127,11 +127,9 @@ static void free_event_data(struct work_struct *work)
event_data = container_of(work, struct etm_event_data, work);
mask = &event_data->mask;
- /*
-* First deal with the sink configuration. See comment in
-* etm_setup_aux() about why we take the first available path.
-*/
- if (event_data->snk_config) {
+
+ /* Free the sink buffers, if there are any */
+ if (event_data->snk_config && !WARN_ON(cpumask_empty(mask))) {
cpu = cpumask_first(mask);
sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu));
if (sink_ops(sink)->free_buffer)
@@ -166,7 +164,7 @@ static void *alloc_event_data(int cpu)
if (cpu != -1)
cpumask_set_cpu(cpu, mask);
else
- cpumask_copy(mask, cpu_online_mask);
+ cpumask_copy(mask, cpu_present_mask);
/*
* Each CPU has a single path between source and destination. As such
@@ -218,19 +216,32 @@ static void *etm_setup_aux(int event_cpu, void **pages,
* on the cmd line. As such the "enable_sink" flag in sysFS is reset.
*/
sink = coresight_get_enabled_sink(true);
- if (!sink)
+ if (!sink || !sink_ops(sink)->alloc_buffer)
goto err;
mask = &event_data->mask;
- /* Setup the path for each CPU in a trace session */
+ /*
+* Setup the path for each CPU in a trace session. We try to build
+* trace path for each CPU in the mask. If we don't find an ETM
+* for the CPU or fail to build a path, we clear the CPU from the
+* mask and continue with the rest. If ever we try to trace on those
+* CPUs, we can handle it and fail the session.
+*/
for_each_cpu(cpu, mask) {
struct list_head *path;
struct coresight_device *csdev;
csdev = per_cpu(csdev_src, cpu);
- if (!csdev)
- goto err;
+ /*
+* If there is no ETM associated with this CPU clear it from
+* the mask and continue with the rest. If ever we try to trace
+* on this CPU, we handle it accordingly.
+*/
+ if (!csdev) {
+ cpumask_clear_cpu(cpu, mask);
+ continue;
+ }
/*
* Building a path doesn't enable it, it simply builds a
@@ -238,17 +249,20 @@ static void *etm_setup_aux(int event_cpu, void **pages,
* referenced later when the path is actually needed.
*/
path = coresight_build_path(csdev, sink);
- if (IS_ERR(path))
- goto err;
+ if (IS_ERR(path)) {
+ cpumask_clear_cpu(cpu, mask);
+ continue;
+ }
*etm_event_cpu_path_ptr(event_data, cpu) = path;
}
- if (!sink_ops(sink)->alloc_buffer)
+ /* If we don't have any CPUs ready for tracing, abort */
+ cpu = cpumask_first(mask);
+ if (cpu >= nr_cpu_ids)
goto err;
- cpu = cpumask_first(mask);
- /* Get the AUX specific data from the sink buffer */
+ /* Allocate the sink buffer for this session */
event_data->snk_config =
sink_ops(sink)->alloc_buffer(sink, cpu, pages,
nr_pages, overwrite);
--
2.7.4
[PATCH 18/44] coresight: Convert driver messages to dev_dbg
From: Suzuki K Poulose
Convert component enable/disable messages from dev_info to dev_dbg.
When used with perf, the components in the paths are enabled/disabled
during each schedule of the run, which can flood the dmesg with these
messages. Moreover, they are only useful for debug purposes. So,
convert such messages to dev_dbg() which can be turned on as
needed.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 4 ++--
drivers/hwtracing/coresight/coresight-etb10.c | 6 +++---
drivers/hwtracing/coresight/coresight-etm3x.c | 4 ++--
drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
drivers/hwtracing/coresight/coresight-funnel.c | 4 ++--
drivers/hwtracing/coresight/coresight-replicator.c | 4 ++--
drivers/hwtracing/coresight/coresight-stm.c| 4 ++--
drivers/hwtracing/coresight/coresight-tmc-etf.c| 8
drivers/hwtracing/coresight/coresight-tmc-etr.c| 4 ++--
drivers/hwtracing/coresight/coresight-tmc.c| 4 ++--
drivers/hwtracing/coresight/coresight-tpiu.c | 4 ++--
11 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index f6d0571ab9dd..ebb80438f6a5 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -56,7 +56,7 @@ static int replicator_enable(struct coresight_device *csdev,
int inport,
CS_LOCK(drvdata->base);
- dev_info(drvdata->dev, "REPLICATOR enabled\n");
+ dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
return 0;
}
@@ -75,7 +75,7 @@ static void replicator_disable(struct coresight_device
*csdev, int inport,
CS_LOCK(drvdata->base);
- dev_info(drvdata->dev, "REPLICATOR disabled\n");
+ dev_dbg(drvdata->dev, "REPLICATOR disabled\n");
}
static const struct coresight_ops_link replicator_link_ops = {
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 0dad8626bcfb..3d4b6df32a06 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -160,7 +160,7 @@ static int etb_enable(struct coresight_device *csdev, u32
mode)
spin_unlock_irqrestore(&drvdata->spinlock, flags);
out:
- dev_info(drvdata->dev, "ETB enabled\n");
+ dev_dbg(drvdata->dev, "ETB enabled\n");
return 0;
}
@@ -266,7 +266,7 @@ static void etb_disable(struct coresight_device *csdev)
local_set(&drvdata->mode, CS_MODE_DISABLED);
- dev_info(drvdata->dev, "ETB disabled\n");
+ dev_dbg(drvdata->dev, "ETB disabled\n");
}
static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
@@ -509,7 +509,7 @@ static void etb_dump(struct etb_drvdata *drvdata)
}
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- dev_info(drvdata->dev, "ETB dumped\n");
+ dev_dbg(drvdata->dev, "ETB dumped\n");
}
static int etb_open(struct inode *inode, struct file *file)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c
b/drivers/hwtracing/coresight/coresight-etm3x.c
index 7c74263c333d..9ce8fba20b0f 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -501,7 +501,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
drvdata->sticky_enable = true;
spin_unlock(&drvdata->spinlock);
- dev_info(drvdata->dev, "ETM tracing enabled\n");
+ dev_dbg(drvdata->dev, "ETM tracing enabled\n");
return 0;
err:
@@ -604,7 +604,7 @@ static void etm_disable_sysfs(struct coresight_device
*csdev)
spin_unlock(&drvdata->spinlock);
cpus_read_unlock();
- dev_info(drvdata->dev, "ETM tracing disabled\n");
+ dev_dbg(drvdata->dev, "ETM tracing disabled\n");
}
static void etm_disable(struct coresight_device *csdev,
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index 1d94ebec027b..c1dcc7c289a5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -267,7 +267,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)
drvdata->sticky_enable = true;
spin_unlock(&drvdata->spinlock);
- dev_info(drvdata->dev, "ETM tracing enabled\n");
+ dev_dbg(drvdata->dev, "ETM tracing enabled\n");
return 0;
err:
@@ -380,7 +380,7 @@ static void etm4_disable_sysfs(struct coresight_device
*csdev)
spin_unlock(&drvdata->spinlock);
cpus_read_unlock();
- dev_info(drvdata->dev, "ETM tracing disabled\n");
+ dev_dbg(drvdata->dev, "ETM tracing disabled\n");
[PATCH 16/44] coresight: tmc-etr: Handle driver mode specific ETR buffers
From: Suzuki K Poulose
Since the ETR could be driven either by SYSFS or by perf, it
becomes complicated how we deal with the buffers used for each
of these modes. The ETR driver cannot simply free the current
attached buffer without knowing the provider (i.e, sysfs vs perf).
To solve this issue, we provide:
1) the driver-mode specific etr buffer to be retained in the drvdata
2) the etr_buf for a session should be passed on when enabling the
hardware, which will be stored in drvdata->etr_buf. This will be
replaced (not free'd) as soon as the hardware is disabled, after
necessary sync operation.
The advantages of this are :
1) The common code path doesn't need to worry about how to dispose
an existing buffer, if it is about to start a new session with a
different buffer, possibly in a different mode.
2) The driver mode can control its buffers and can get access to the
saved session even when the hardware is operating in a different
mode. (e.g, we can still access a trace buffer from a sysfs mode
even if the etr is now used in perf mode, without disrupting the
current session.)
Towards this, we introduce a sysfs specific data which will hold the
etr_buf used for sysfs mode of operation, controlled solely by the
sysfs mode handling code.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 58 -
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 11963647e19a..2d6f428176ff 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -895,10 +895,15 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
-static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
+static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
+ struct etr_buf *etr_buf)
{
u32 axictl, sts;
- struct etr_buf *etr_buf = drvdata->etr_buf;
+
+ /* Callers should provide an appropriate buffer for use */
+ if (WARN_ON(!etr_buf || drvdata->etr_buf))
+ return;
+ drvdata->etr_buf = etr_buf;
/*
* If this ETR is connected to a CATU, enable it before we turn
@@ -960,13 +965,16 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
* also updating the @bufpp on where to find it. Since the trace data
* starts at anywhere in the buffer, depending on the RRP, we adjust the
* @len returned to handle buffer wrapping around.
+ *
+ * We are protected here by drvdata->reading != 0, which ensures the
+ * sysfs_buf stays alive.
*/
ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
loff_t pos, size_t len, char **bufpp)
{
s64 offset;
ssize_t actual = len;
- struct etr_buf *etr_buf = drvdata->etr_buf;
+ struct etr_buf *etr_buf = drvdata->sysfs_buf;
if (pos + actual > etr_buf->len)
actual = etr_buf->len - pos;
@@ -996,7 +1004,14 @@ tmc_etr_free_sysfs_buf(struct etr_buf *buf)
static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
{
- tmc_sync_etr_buf(drvdata);
+ struct etr_buf *etr_buf = drvdata->etr_buf;
+
+ if (WARN_ON(drvdata->sysfs_buf != etr_buf)) {
+ tmc_etr_free_sysfs_buf(drvdata->sysfs_buf);
+ drvdata->sysfs_buf = NULL;
+ } else {
+ tmc_sync_etr_buf(drvdata);
+ }
}
static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
@@ -1017,6 +1032,8 @@ static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata)
/* Disable CATU device if this ETR is connected to one */
tmc_etr_disable_catu(drvdata);
+ /* Reset the ETR buf used by hardware */
+ drvdata->etr_buf = NULL;
}
static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
@@ -1024,7 +1041,7 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
int ret = 0;
unsigned long flags;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- struct etr_buf *new_buf = NULL, *free_buf = NULL;
+ struct etr_buf *sysfs_buf = NULL, *new_buf = NULL, *free_buf = NULL;
/*
* If we are enabling the ETR from disabled state, we need to make
@@ -1035,7 +1052,8 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
* with the lock released.
*/
spin_lock_irqsave(&drvdata->spinlock, flags);
- if (!drvdata->etr_buf || (drvdata->etr_buf->size != drvdata->size)) {
+ sysfs_buf = READ_ONCE(drvdata->sysfs_buf);
+ if (!sysfs_buf || (sysfs_buf->size != drvdata->size)) {
spin_unlock_irqrestor
[PATCH 21/44] coresight: perf: Remove set_buffer call back
From: Suzuki K Poulose
In coresight perf mode, we need to prepare the sink before
starting a session, which is done via set_buffer call back.
We then proceed to enable the tracing. If we fail to start
the session successfully, we leave the sink configuration
unchanged. In order to make the operation atomic and to
avoid yet another call back to clear the buffer, we get
rid of the "set_buffer" call back and pass the buffer details
via enable() call back to the sink.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c| 32 ++--
drivers/hwtracing/coresight/coresight-etm-perf.c | 9 ++-
drivers/hwtracing/coresight/coresight-priv.h | 2 +-
drivers/hwtracing/coresight/coresight-tmc-etf.c | 28 ++---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 +++---
drivers/hwtracing/coresight/coresight-tpiu.c | 2 +-
drivers/hwtracing/coresight/coresight.c | 11
include/linux/coresight.h| 6 +
8 files changed, 59 insertions(+), 38 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index dba75c905e57..9fd77fdc1244 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -28,6 +28,7 @@
#include "coresight-priv.h"
+#include "coresight-etm-perf.h"
#define ETB_RAM_DEPTH_REG 0x004
#define ETB_STATUS_REG 0x00c
@@ -90,6 +91,9 @@ struct etb_drvdata {
u32 trigger_cntr;
};
+static int etb_set_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle);
+
static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
{
u32 depth = 0;
@@ -131,12 +135,24 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static int etb_enable(struct coresight_device *csdev, u32 mode)
+static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
{
+ int ret = 0;
u32 val;
unsigned long flags;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ /*
+* We don't have an internal state to clean up if we fail to setup
+* the perf buffer. So we can perform the step before we turn the
+* ETB on and leave without cleaning up.
+*/
+ if (mode == CS_MODE_PERF) {
+ ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
+ if (ret)
+ goto out;
+ }
+
val = local_cmpxchg(&drvdata->mode,
CS_MODE_DISABLED, mode);
/*
@@ -160,8 +176,9 @@ static int etb_enable(struct coresight_device *csdev, u32
mode)
spin_unlock_irqrestore(&drvdata->spinlock, flags);
out:
- dev_dbg(drvdata->dev, "ETB enabled\n");
- return 0;
+ if (!ret)
+ dev_dbg(drvdata->dev, "ETB enabled\n");
+ return ret;
}
static void etb_disable_hw(struct etb_drvdata *drvdata)
@@ -298,12 +315,14 @@ static void etb_free_buffer(void *config)
}
static int etb_set_buffer(struct coresight_device *csdev,
- struct perf_output_handle *handle,
- void *sink_config)
+ struct perf_output_handle *handle)
{
int ret = 0;
unsigned long head;
- struct cs_buffers *buf = sink_config;
+ struct cs_buffers *buf = etm_perf_sink_config(handle);
+
+ if (!buf)
+ return -EINVAL;
/* wrap head around to the amount of space we have */
head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
@@ -457,7 +476,6 @@ static const struct coresight_ops_sink etb_sink_ops = {
.disable= etb_disable,
.alloc_buffer = etb_alloc_buffer,
.free_buffer= etb_free_buffer,
- .set_buffer = etb_set_buffer,
.update_buffer = etb_update_buffer,
};
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 16b83d8b2ac2..abe8249b893b 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -286,16 +286,11 @@ static void etm_event_start(struct perf_event *event, int
flags)
path = etm_event_cpu_path(event_data, cpu);
/* We need a sink, no need to continue without one */
sink = coresight_get_sink(path);
- if (WARN_ON_ONCE(!sink || !sink_ops(sink)->set_buffer))
- goto fail_end_stop;
-
- /* Configure the sink */
- if (sink_ops(sink)->set_buffer(sink, handle,
- event_data->snk_config))
+ if (WARN_ON_ONCE(!sink))
goto fail_end_stop;
/* Nothing will happen without a path */
- if (coresight_enable_p
[PATCH 23/44] coresight: etb10: Refactor etb_drvdata::mode handling
This patch moves the etb_drvdata::mode from a locat_t to a simple u32,
as it is for the ETF and ETR drivers. This streamlines the code and adds
commonality with the other drivers when dealing with similar operations.
Signed-off-by: Mathieu Poirier
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etb10.c | 62 +++
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 9fd77fdc1244..69287163ce4e 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -5,7 +5,6 @@
* Description: CoreSight Embedded Trace Buffer driver
*/
-#include
#include
#include
#include
@@ -72,8 +71,8 @@
* @miscdev: specifics to handle "/dev/xyz.etb" entry.
* @spinlock: only one at a time pls.
* @reading: synchronise user space access to etb buffer.
- * @mode: this ETB is being used.
* @buf: area of memory where ETB buffer content gets sent.
+ * @mode: this ETB is being used.
* @buffer_depth: size of @buf.
* @trigger_cntr: amount of words to store after a trigger.
*/
@@ -85,8 +84,8 @@ struct etb_drvdata {
struct miscdevice miscdev;
spinlock_t spinlock;
local_t reading;
- local_t mode;
u8 *buf;
+ u32 mode;
u32 buffer_depth;
u32 trigger_cntr;
};
@@ -138,44 +137,48 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
{
int ret = 0;
- u32 val;
unsigned long flags;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- /*
-* We don't have an internal state to clean up if we fail to setup
-* the perf buffer. So we can perform the step before we turn the
-* ETB on and leave without cleaning up.
-*/
- if (mode == CS_MODE_PERF) {
- ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
- if (ret)
- goto out;
- }
+ spin_lock_irqsave(&drvdata->spinlock, flags);
- val = local_cmpxchg(&drvdata->mode,
- CS_MODE_DISABLED, mode);
/*
* When accessing from Perf, a HW buffer can be handled
* by a single trace entity. In sysFS mode many tracers
* can be logging to the same HW buffer.
*/
- if (val == CS_MODE_PERF)
- return -EBUSY;
+ if (drvdata->mode == CS_MODE_PERF) {
+ ret = -EBUSY;
+ goto out;
+ }
/* Don't let perf disturb sysFS sessions */
- if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF)
- return -EBUSY;
+ if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_PERF) {
+ ret = -EBUSY;
+ goto out;
+ }
/* Nothing to do, the tracer is already enabled. */
- if (val == CS_MODE_SYSFS)
+ if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_SYSFS)
goto out;
- spin_lock_irqsave(&drvdata->spinlock, flags);
+ /*
+* We don't have an internal state to clean up if we fail to setup
+* the perf buffer. So we can perform the step before we turn the
+* ETB on and leave without cleaning up.
+*/
+ if (mode == CS_MODE_PERF) {
+ ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
+ if (ret)
+ goto out;
+ }
+
+ drvdata->mode = mode;
etb_enable_hw(drvdata);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
out:
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
if (!ret)
dev_dbg(drvdata->dev, "ETB enabled\n");
return ret;
@@ -277,11 +280,14 @@ static void etb_disable(struct coresight_device *csdev)
unsigned long flags;
spin_lock_irqsave(&drvdata->spinlock, flags);
- etb_disable_hw(drvdata);
- etb_dump_hw(drvdata);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
- local_set(&drvdata->mode, CS_MODE_DISABLED);
+ /* Disable the ETB only if it needs to */
+ if (drvdata->mode != CS_MODE_DISABLED) {
+ etb_disable_hw(drvdata);
+ etb_dump_hw(drvdata);
+ drvdata->mode = CS_MODE_DISABLED;
+ }
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
dev_dbg(drvdata->dev, "ETB disabled\n");
}
@@ -488,7 +494,7 @@ static void etb_dump(struct etb_drvdata *drvdata)
unsigned long flags;
spin_lock_irqsave(&drvdata->spinlock, flags);
- if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
+ if (drvdata->mode == CS_MODE_SYSFS) {
[PATCH 24/44] coresight: etb10: Splitting function etb_enable()
Up until now the relative simplicity of enabling the ETB made it
possible to accommodate processing for both sysFS and perf methods.
But work on claimtags and CPU-wide trace scenarios is adding some
complexity, making the current code messy and hard to maintain.
As such follow what has been done for ETF and ETR components and split
function etb_enable() so that processing for both API can be done
cleanly.
Signed-off-by: Mathieu Poirier
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etb10.c | 73 +++
1 file changed, 52 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 69287163ce4e..08fa660098f8 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -134,7 +134,7 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
+static int etb_enable_sysfs(struct coresight_device *csdev)
{
int ret = 0;
unsigned long flags;
@@ -142,48 +142,79 @@ static int etb_enable(struct coresight_device *csdev, u32
mode, void *data)
spin_lock_irqsave(&drvdata->spinlock, flags);
- /*
-* When accessing from Perf, a HW buffer can be handled
-* by a single trace entity. In sysFS mode many tracers
-* can be logging to the same HW buffer.
-*/
+ /* Don't messup with perf sessions. */
if (drvdata->mode == CS_MODE_PERF) {
ret = -EBUSY;
goto out;
}
- /* Don't let perf disturb sysFS sessions */
- if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_PERF) {
- ret = -EBUSY;
+ /* Nothing to do, the tracer is already enabled. */
+ if (drvdata->mode == CS_MODE_SYSFS)
goto out;
- }
- /* Nothing to do, the tracer is already enabled. */
- if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_SYSFS)
+ drvdata->mode = CS_MODE_SYSFS;
+ etb_enable_hw(drvdata);
+
+out:
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ return ret;
+}
+
+static int etb_enable_perf(struct coresight_device *csdev, void *data)
+{
+ int ret = 0;
+ unsigned long flags;
+ struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+
+ /* No need to continue if the component is already in use. */
+ if (drvdata->mode != CS_MODE_DISABLED) {
+ ret = -EBUSY;
goto out;
+ }
/*
* We don't have an internal state to clean up if we fail to setup
* the perf buffer. So we can perform the step before we turn the
* ETB on and leave without cleaning up.
*/
- if (mode == CS_MODE_PERF) {
- ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
- if (ret)
- goto out;
- }
+ ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
+ if (ret)
+ goto out;
- drvdata->mode = mode;
+ drvdata->mode = CS_MODE_PERF;
etb_enable_hw(drvdata);
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
-
- if (!ret)
- dev_dbg(drvdata->dev, "ETB enabled\n");
return ret;
}
+static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
+{
+ int ret;
+ struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ switch (mode) {
+ case CS_MODE_SYSFS:
+ ret = etb_enable_sysfs(csdev);
+ break;
+ case CS_MODE_PERF:
+ ret = etb_enable_perf(csdev, data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ return ret;
+
+ dev_dbg(drvdata->dev, "ETB enabled\n");
+ return 0;
+}
+
static void etb_disable_hw(struct etb_drvdata *drvdata)
{
u32 ffcr;
--
2.7.4
[PATCH 32/44] coresight: etm4x: Add support for handling errors
From: Suzuki K Poulose
Add support for handling errors in enabling the component.
The ETM is enabled via cross call to owner CPU. Make
necessary changes to report the error back from the cross
call.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm4x.c | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index b7379e9cfb30..064e0bfaefd0 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -78,10 +78,14 @@ static int etm4_trace_id(struct coresight_device *csdev)
return drvdata->trcid;
}
-static void etm4_enable_hw(void *info)
+struct etm4_enable_arg {
+ struct etmv4_drvdata *drvdata;
+ int rc;
+};
+
+static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i;
- struct etmv4_drvdata *drvdata = info;
struct etmv4_config *config = &drvdata->config;
CS_UNLOCK(drvdata->base);
@@ -178,6 +182,16 @@ static void etm4_enable_hw(void *info)
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
+ return 0;
+}
+
+static void etm4_enable_hw_smp_call(void *info)
+{
+ struct etm4_enable_arg *arg = info;
+
+ if (WARN_ON(!arg))
+ return;
+ arg->rc = etm4_enable_hw(arg->drvdata);
}
static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
@@ -243,7 +257,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
if (ret)
goto out;
/* And enable it */
- etm4_enable_hw(drvdata);
+ ret = etm4_enable_hw(drvdata);
out:
return ret;
@@ -252,6 +266,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
static int etm4_enable_sysfs(struct coresight_device *csdev)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ struct etm4_enable_arg arg = { 0 };
int ret;
spin_lock(&drvdata->spinlock);
@@ -260,19 +275,17 @@ static int etm4_enable_sysfs(struct coresight_device
*csdev)
* Executing etm4_enable_hw on the cpu whose ETM is being enabled
* ensures that register writes occur when cpu is powered.
*/
+ arg.drvdata = drvdata;
ret = smp_call_function_single(drvdata->cpu,
- etm4_enable_hw, drvdata, 1);
- if (ret)
- goto err;
-
- drvdata->sticky_enable = true;
+ etm4_enable_hw_smp_call, &arg, 1);
+ if (!ret)
+ ret = arg.rc;
+ if (!ret)
+ drvdata->sticky_enable = true;
spin_unlock(&drvdata->spinlock);
- dev_dbg(drvdata->dev, "ETM tracing enabled\n");
- return 0;
-
-err:
- spin_unlock(&drvdata->spinlock);
+ if (!ret)
+ dev_dbg(drvdata->dev, "ETM tracing enabled\n");
return ret;
}
--
2.7.4
[PATCH 33/44] coresight: etm3: Add support for handling errors
From: Suzuki K Poulose
Add support for reporting errors back from the SMP cross
function call for enabling ETM.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 42 ++-
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c
b/drivers/hwtracing/coresight/coresight-etm3x.c
index 9ce8fba20b0f..206c2381a11a 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -355,11 +355,10 @@ static int etm_parse_event_config(struct etm_drvdata
*drvdata,
return 0;
}
-static void etm_enable_hw(void *info)
+static int etm_enable_hw(struct etm_drvdata *drvdata)
{
int i;
u32 etmcr;
- struct etm_drvdata *drvdata = info;
struct etm_config *config = &drvdata->config;
CS_UNLOCK(drvdata->base);
@@ -421,6 +420,21 @@ static void etm_enable_hw(void *info)
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
+ return 0;
+}
+
+struct etm_enable_arg {
+ struct etm_drvdata *drvdata;
+ int rc;
+};
+
+static void etm_enable_hw_smp_call(void *info)
+{
+ struct etm_enable_arg *arg = info;
+
+ if (WARN_ON(!arg))
+ return;
+ arg->rc = etm_enable_hw(arg->drvdata);
}
static int etm_cpu_id(struct coresight_device *csdev)
@@ -475,14 +489,13 @@ static int etm_enable_perf(struct coresight_device *csdev,
/* Configure the tracer based on the session's specifics */
etm_parse_event_config(drvdata, event);
/* And enable it */
- etm_enable_hw(drvdata);
-
- return 0;
+ return etm_enable_hw(drvdata);
}
static int etm_enable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ struct etm_enable_arg arg = { 0 };
int ret;
spin_lock(&drvdata->spinlock);
@@ -492,20 +505,21 @@ static int etm_enable_sysfs(struct coresight_device
*csdev)
* hw configuration will take place on the local CPU during bring up.
*/
if (cpu_online(drvdata->cpu)) {
+ arg.drvdata = drvdata;
ret = smp_call_function_single(drvdata->cpu,
- etm_enable_hw, drvdata, 1);
- if (ret)
- goto err;
+ etm_enable_hw_smp_call, &arg, 1);
+ if (!ret)
+ ret = arg.rc;
+ if (!ret)
+ drvdata->sticky_enable = true;
+ } else {
+ ret = -ENODEV;
}
- drvdata->sticky_enable = true;
spin_unlock(&drvdata->spinlock);
- dev_dbg(drvdata->dev, "ETM tracing enabled\n");
- return 0;
-
-err:
- spin_unlock(&drvdata->spinlock);
+ if (!ret)
+ dev_dbg(drvdata->dev, "ETM tracing enabled\n");
return ret;
}
--
2.7.4
[PATCH 30/44] coresight: tmc-etr: Handle errors enabling CATU
From: Suzuki K Poulose
Make sure we honor the errors in CATU device and abort the operation.
While at it, delay setting the etr_buf for the session until we are
sure that we are indeed enabling the ETR.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index c42693542ec8..daad52146140 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -751,12 +751,14 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata)
return NULL;
}
-static inline void tmc_etr_enable_catu(struct tmc_drvdata *drvdata)
+static inline int tmc_etr_enable_catu(struct tmc_drvdata *drvdata,
+ struct etr_buf *etr_buf)
{
struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
if (catu && helper_ops(catu)->enable)
- helper_ops(catu)->enable(catu, drvdata->etr_buf);
+ return helper_ops(catu)->enable(catu, etr_buf);
+ return 0;
}
static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata)
@@ -971,6 +973,8 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
struct etr_buf *etr_buf)
{
+ int rc;
+
/* Callers should provide an appropriate buffer for use */
if (WARN_ON(!etr_buf))
return -EINVAL;
@@ -982,16 +986,17 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
if (WARN_ON(drvdata->etr_buf))
return -EBUSY;
- /* Set the buffer for the session */
- drvdata->etr_buf = etr_buf;
/*
* If this ETR is connected to a CATU, enable it before we turn
* this on.
*/
- tmc_etr_enable_catu(drvdata);
+ rc = tmc_etr_enable_catu(drvdata, etr_buf);
+ if (!rc) {
+ drvdata->etr_buf = etr_buf;
+ __tmc_etr_enable_hw(drvdata);
+ }
- __tmc_etr_enable_hw(drvdata);
- return 0;
+ return rc;
}
/*
--
2.7.4
[PATCH 27/44] coresight: tmc: Fix byte-address alignment for RRP
From: Leo Yan >From the comment in the code, it claims the requirement for byte-address alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s'. This isn't consistent with the program, the program sets five LSBs as zeros for 32/64/128-bit wide trace memory and set six LSBs zeros for 256-bit wide trace memory. After checking with the CoreSight Trace Memory Controller technical reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer Register), it proves the comment is right and the program does wrong setting. This patch fixes byte-address alignment for RRP by following correct definition in the technical reference manual. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Leo Yan Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 4bf3bfd7c078..b54a3db13fee 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -417,10 +417,10 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, case TMC_MEM_INTF_WIDTH_32BITS: case TMC_MEM_INTF_WIDTH_64BITS: case TMC_MEM_INTF_WIDTH_128BITS: - mask = GENMASK(31, 5); + mask = GENMASK(31, 4); break; case TMC_MEM_INTF_WIDTH_256BITS: - mask = GENMASK(31, 6); + mask = GENMASK(31, 5); break; } -- 2.7.4
[PATCH 41/44] coreisght: tmc: Claim device before use
From: Suzuki K Poulose
Use CLAIM tags to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 22 +++---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 4
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 36af23d2c0f8..53fc83b72a49 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -36,6 +36,11 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
{
+ int rc = coresight_claim_device(drvdata->base);
+
+ if (rc)
+ return rc;
+
__tmc_etb_enable_hw(drvdata);
return 0;
}
@@ -63,7 +68,7 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
return;
}
-static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -79,6 +84,12 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
+{
+ coresight_disclaim_device(drvdata);
+ __tmc_etb_disable_hw(drvdata);
+}
+
static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -97,6 +108,11 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
{
+ int rc = coresight_claim_device(drvdata->base);
+
+ if (rc)
+ return rc;
+
__tmc_etf_enable_hw(drvdata);
return 0;
}
@@ -107,7 +123,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
tmc_flush_and_stop(drvdata);
tmc_disable_hw(drvdata);
-
+ coresight_disclaim_device_unlocked(drvdata->base);
CS_LOCK(drvdata->base);
}
@@ -553,7 +569,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
/* Disable the TMC if need be */
if (drvdata->mode == CS_MODE_SYSFS)
- tmc_etb_disable_hw(drvdata);
+ __tmc_etb_disable_hw(drvdata);
drvdata->reading = true;
out:
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index daad52146140..f684283890d3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -991,6 +991,9 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
* this on.
*/
rc = tmc_etr_enable_catu(drvdata, etr_buf);
+ if (rc)
+ return rc;
+ rc = coresight_claim_device(drvdata->base);
if (!rc) {
drvdata->etr_buf = etr_buf;
__tmc_etr_enable_hw(drvdata);
@@ -1077,6 +1080,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata)
__tmc_etr_disable_hw(drvdata);
/* Disable CATU device if this ETR is connected to one */
tmc_etr_disable_catu(drvdata);
+ coresight_disclaim_device(drvdata->base);
/* Reset the ETR buf used by hardware */
drvdata->etr_buf = NULL;
}
--
2.7.4
[PATCH 43/44] coresight: dts: binding: Update coresight binding examples
From: Suzuki K Poulose
While we updated the coresight DT bindings, some of the
new examples were not updated due to the order in which they
were merged. Let us update all the missed out ones to the
new bindings to avoid confusion.
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: Frank Rowand
Signed-off-by: Suzuki K Poulose
Reviewed-by: Rob Herring
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 25 +-
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index 13b6198ce01c..f8aff65ab921 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -147,22 +147,16 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* input port */
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
etr_in_port: endpoint {
- slave-mode;
remote-endpoint =
<&replicator2_out_port0>;
};
};
+ };
- /* CATU link represented by output port */
- port@1 {
- reg = <1>;
+ out-ports {
+ port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
@@ -310,10 +304,11 @@ Example:
clock-names = "apb_pclk";
interrupts = ;
- port {
- catu_in_port: endpoint {
- slave-mode;
- remote-endpoint = <&etr_out_port>;
+ in-ports {
+ port {
+ catu_in_port: endpoint {
+ remote-endpoint = <&etr_out_port>;
+ };
};
};
};
--
2.7.4
[PATCH 42/44] coresight: dts: binding: Fix example for TPIU component
From: Suzuki K Poulose
TPIU component has an input port. The example uses out-ports
which is wrong. Let us fix it.
Reported-by: Leo Yan
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
Documentation/devicetree/bindings/arm/coresight.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index f39d2c6eb49c..13b6198ce01c 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -132,7 +132,7 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- out-ports {
+ in-ports {
port {
tpiu_in_port: endpoint@0 {
remote-endpoint =
<&replicator_out_port1>;
--
2.7.4
[PATCH 35/44] coresight: dynamic-replicator: Handle multiple connections
From: Suzuki K Poulose
When a replicator port is enabled, we block the traffic
on the other port and route all traffic to the new enabled
port. If there are two active trace sessions each targeting
the two different paths from the replicator, the second session
will disable the first session and route all the data to the
second path.
ETR
/
e.g, replicator
\
ETB
If CPU0 is operated in sysfs mode to ETR and CPU1 is operated
in perf mode to ETB, depending on the order in which the
replicator is enabled one device is blocked.
Ideally we need trace-id for the session to make the
right choice. That implies we need a trace-id allocation
logic for the coresight subsystem and use that to route
the traffic. The short term solution is to only manage
the "target port" and leave the other port untouched.
That leaves both the paths unaffected, except that some
unwanted traffic may be pushed to the paths (if the Trace-IDs
are not far enough), which is still fine and can be filtered
out while processing rather than silently blocking the data.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 64 --
1 file changed, 47 insertions(+), 17 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index ebb80438f6a5..97f4673452cb 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -34,26 +34,42 @@ struct replicator_state {
struct coresight_device *csdev;
};
+/*
+ * replicator_reset : Reset the replicator configuration to sane values.
+ */
+static void replicator_reset(struct replicator_state *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+
+ CS_LOCK(drvdata->base);
+}
+
static int replicator_enable(struct coresight_device *csdev, int inport,
int outport)
{
+ u32 reg;
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
+ switch (outport) {
+ case 0:
+ reg = REPLICATOR_IDFILTER0;
+ break;
+ case 1:
+ reg = REPLICATOR_IDFILTER1;
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
CS_UNLOCK(drvdata->base);
- /*
-* Ensure that the other port is disabled
-* 0x00 - passing through the replicator unimpeded
-* 0xff - disable (or impede) the flow of ATB data
-*/
- if (outport == 0) {
- writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
- } else {
- writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
- }
+ /* Ensure that the outport is enabled. */
+ writel_relaxed(0x00, drvdata->base + reg);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
@@ -63,15 +79,25 @@ static int replicator_enable(struct coresight_device
*csdev, int inport,
static void replicator_disable(struct coresight_device *csdev, int inport,
int outport)
{
+ u32 reg;
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
+ switch (outport) {
+ case 0:
+ reg = REPLICATOR_IDFILTER0;
+ break;
+ case 1:
+ reg = REPLICATOR_IDFILTER1;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
CS_UNLOCK(drvdata->base);
/* disable the flow of ATB data through port */
- if (outport == 0)
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
- else
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ writel_relaxed(0xff, drvdata->base + reg);
CS_LOCK(drvdata->base);
@@ -156,7 +182,11 @@ static int replicator_probe(struct amba_device *adev,
const struct amba_id *id)
desc.groups = replicator_groups;
drvdata->csdev = coresight_register(&desc);
- return PTR_ERR_OR_ZERO(drvdata->csdev);
+ if (!IS_ERR(drvdata->csdev)) {
+ replicator_reset(drvdata);
+ return 0;
+ }
+ return PTR_ERR(drvdata->csdev);
}
#ifdef CONFIG_PM
--
2.7.4
[PATCH 38/44] coresight: funnel: Claim devices before use
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-funnel.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c
b/drivers/hwtracing/coresight/coresight-funnel.c
index ee7a30bf9480..927925151509 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -25,6 +25,7 @@
#define FUNNEL_HOLDTIME_MASK 0xf00
#define FUNNEL_HOLDTIME_SHFT 0x8
#define FUNNEL_HOLDTIME(0x7 << FUNNEL_HOLDTIME_SHFT)
+#define FUNNEL_ENSx_MASK 0xff
/**
* struct funnel_drvdata - specifics associated to a funnel component
@@ -42,31 +43,42 @@ struct funnel_drvdata {
unsigned long priority;
};
-static void funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
+static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
{
u32 functl;
+ int rc = 0;
CS_UNLOCK(drvdata->base);
functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
+ /* Claim the device only when we enable the first slave */
+ if (!(functl & FUNNEL_ENSx_MASK)) {
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ goto done;
+ }
+
functl &= ~FUNNEL_HOLDTIME_MASK;
functl |= FUNNEL_HOLDTIME;
functl |= (1 << port);
writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL);
writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL);
-
+done:
CS_LOCK(drvdata->base);
+ return rc;
}
static int funnel_enable(struct coresight_device *csdev, int inport,
int outport)
{
+ int rc;
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- funnel_enable_hw(drvdata, inport);
+ rc = funnel_enable_hw(drvdata, inport);
- dev_dbg(drvdata->dev, "FUNNEL inport %d enabled\n", inport);
- return 0;
+ if (!rc)
+ dev_dbg(drvdata->dev, "FUNNEL inport %d enabled\n", inport);
+ return rc;
}
static void funnel_disable_hw(struct funnel_drvdata *drvdata, int inport)
@@ -79,6 +91,10 @@ static void funnel_disable_hw(struct funnel_drvdata
*drvdata, int inport)
functl &= ~(1 << inport);
writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL);
+ /* Disclaim the device if none of the slaves are now active */
+ if (!(functl & FUNNEL_ENSx_MASK))
+ coresight_disclaim_device_unlocked(drvdata->base);
+
CS_LOCK(drvdata->base);
}
--
2.7.4
[PATCH 37/44] coresight: etmx: Claim devices before use
From: Suzuki K Poulose
Use the CLAIM tags to grab the device for self-hosted usage.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 16 +---
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +++---
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c
b/drivers/hwtracing/coresight/coresight-etm3x.c
index 206c2381a11a..fd5c4cca7db5 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -357,7 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata
*drvdata,
static int etm_enable_hw(struct etm_drvdata *drvdata)
{
- int i;
+ int i, rc;
u32 etmcr;
struct etm_config *config = &drvdata->config;
@@ -369,6 +369,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
etm_set_pwrup(drvdata);
/* Make sure all registers are accessible */
etm_os_unlock(drvdata);
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ goto done;
etm_set_prog(drvdata);
@@ -417,10 +420,15 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
etm_writel(drvdata, 0x0, ETMVMIDCVR);
etm_clr_prog(drvdata);
+
+done:
+ if (rc)
+ etm_set_pwrdwn(drvdata);
CS_LOCK(drvdata->base);
- dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
- return 0;
+ dev_dbg(drvdata->dev, "cpu: %d enable smp call done: %d\n",
+ drvdata->cpu, rc);
+ return rc;
}
struct etm_enable_arg {
@@ -569,6 +577,8 @@ static void etm_disable_hw(void *info)
for (i = 0; i < drvdata->nr_cntr; i++)
config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
+ coresight_disclaim_device_unlocked(drvdata->base);
+
etm_set_pwrdwn(drvdata);
CS_LOCK(drvdata->base);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index 064e0bfaefd0..53e2fb6e86f6 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -85,13 +85,17 @@ struct etm4_enable_arg {
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
- int i;
+ int i, rc;
struct etmv4_config *config = &drvdata->config;
CS_UNLOCK(drvdata->base);
etm4_os_unlock(drvdata);
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ goto done;
+
/* Disable the trace unit before programming trace registers */
writel_relaxed(0, drvdata->base + TRCPRGCTLR);
@@ -179,10 +183,12 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
dev_err(drvdata->dev,
"timeout while waiting for Idle Trace Status\n");
+done:
CS_LOCK(drvdata->base);
- dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
- return 0;
+ dev_dbg(drvdata->dev, "cpu: %d enable smp call done: %d\n",
+ drvdata->cpu, rc);
+ return rc;
}
static void etm4_enable_hw_smp_call(void *info)
@@ -342,6 +348,8 @@ static void etm4_disable_hw(void *info)
isb();
writel_relaxed(control, drvdata->base + TRCPRGCTLR);
+ coresight_disclaim_device_unlocked(drvdata->base);
+
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
--
2.7.4
Re: [PATCH 0/9] AHCI and SATA PHY support for BCM63138
On 09/20/2018 12:16 PM, Florian Fainelli wrote: > Hi Kishon, Tejun, > > This patch series adds support for the SATA AHCI and PHY found on the > ARM-basd BCM63138 DSL SoCs. > > It would probably make sense for patches 1-3 to go through Kishon's > tree, patches 4-7 through Tejun's tree, and I would be merging the last > two patches through the Broadcom ARM-SoC tree. > > Let me know if this is not a workable plan, thank you very much! Looks like I had left patches with the incorrect subject, please disregard the following patches: [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for DSL SoCs [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings since they have incorrect/inconsistent titles, the other patches are fine though. Sorry about that. > > Florian Fainelli (9): > dt-bindings: phy: Document BCM63138 compatible string > phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs > phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence > dt-bindings: ata: Document BCM63138 compatible string > ata: ahci_brcm: Allow optional reset controller to be used > ata: ahci_brcm: Match BCM63138 compatible strings > ata: ahci_brcm: Allow using driver or DSL SoCs > ARM: dts: BCM63xx: enable SATA PHY and AHCI controller > ARM: bcm63138: Enable SATA AHCI and PHY > > .../bindings/ata/brcm,sata-brcm.txt | 1 + > .../devicetree/bindings/phy/brcm-sata-phy.txt | 1 + > arch/arm/boot/dts/bcm63138.dtsi | 30 > arch/arm/boot/dts/bcm963138dvt.dts| 8 +++ > drivers/ata/Kconfig | 3 +- > drivers/ata/ahci_brcm.c | 10 +++ > drivers/phy/broadcom/Kconfig | 3 +- > drivers/phy/broadcom/phy-brcm-sata.c | 70 +++ > 8 files changed, 124 insertions(+), 2 deletions(-) > -- Florian
[PATCH 34/44] coresight: etb10: Handle errors enabling the device
From: Suzuki K Poulose
Prepare the etb10 driver to return errors in enabling
the device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 08fa660098f8..824be0c5f592 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -106,7 +106,7 @@ static unsigned int etb_get_buffer_depth(struct etb_drvdata
*drvdata)
return depth;
}
-static void etb_enable_hw(struct etb_drvdata *drvdata)
+static void __etb_enable_hw(struct etb_drvdata *drvdata)
{
int i;
u32 depth;
@@ -134,6 +134,12 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int etb_enable_hw(struct etb_drvdata *drvdata)
+{
+ __etb_enable_hw(drvdata);
+ return 0;
+}
+
static int etb_enable_sysfs(struct coresight_device *csdev)
{
int ret = 0;
@@ -152,8 +158,9 @@ static int etb_enable_sysfs(struct coresight_device *csdev)
if (drvdata->mode == CS_MODE_SYSFS)
goto out;
- drvdata->mode = CS_MODE_SYSFS;
- etb_enable_hw(drvdata);
+ ret = etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -183,8 +190,9 @@ static int etb_enable_perf(struct coresight_device *csdev,
void *data)
if (ret)
goto out;
- drvdata->mode = CS_MODE_PERF;
- etb_enable_hw(drvdata);
+ ret = etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_PERF;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
--
2.7.4
[PATCH 31/44] coresight: tmc-etb/etf: Prepare to handle errors enabling
From: Suzuki K Poulose
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 73 +++--
1 file changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index b54a3db13fee..36af23d2c0f8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -15,7 +15,7 @@
static int tmc_set_etf_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle);
-static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -34,6 +34,12 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etb_enable_hw(drvdata);
+ return 0;
+}
+
static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
char *bufp;
@@ -73,7 +79,7 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -89,6 +95,12 @@ static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etf_enable_hw(drvdata);
+ return 0;
+}
+
static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -171,8 +183,12 @@ static int tmc_enable_etf_sink_sysfs(struct
coresight_device *csdev)
drvdata->buf = buf;
}
- drvdata->mode = CS_MODE_SYSFS;
- tmc_etb_enable_hw(drvdata);
+ ret = tmc_etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
+ else
+ /* Free up the buffer if we failed to enable */
+ used = false;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -191,27 +207,25 @@ static int tmc_enable_etf_sink_perf(struct
coresight_device *csdev, void *data)
struct perf_output_handle *handle = data;
spin_lock_irqsave(&drvdata->spinlock, flags);
- if (drvdata->reading) {
- ret = -EINVAL;
- goto out;
- }
-
- /*
-* In Perf mode there can be only one writer per sink. There
-* is also no need to continue if the ETB/ETR is already operated
-* from sysFS.
-*/
- if (drvdata->mode != CS_MODE_DISABLED) {
+ do {
ret = -EINVAL;
- goto out;
- }
+ if (drvdata->reading)
+ break;
+ /*
+* In Perf mode there can be only one writer per sink. There
+* is also no need to continue if the ETB/ETF is already
+* operated from sysFS.
+*/
+ if (drvdata->mode != CS_MODE_DISABLED)
+ break;
- ret = tmc_set_etf_buffer(csdev, handle);
- if (!ret) {
- drvdata->mode = CS_MODE_PERF;
- tmc_etb_enable_hw(drvdata);
- }
-out:
+ ret = tmc_set_etf_buffer(csdev, handle);
+ if (ret)
+ break;
+ ret = tmc_etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_PERF;
+ } while (0);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
return ret;
@@ -268,6 +282,7 @@ static void tmc_disable_etf_sink(struct coresight_device
*csdev)
static int tmc_enable_etf_link(struct coresight_device *csdev,
int inport, int outport)
{
+ int ret;
unsigned long flags;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -277,12 +292,14 @@ static int tmc_enable_etf_link(struct coresight_device
*csdev,
return -EBUSY;
}
- tmc_etf_enable_hw(drvdata);
- drvdata->mode = CS_MODE_SYSFS;
+ ret = tmc_etf_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- dev_dbg(drvdata->dev, "TMC-ETF enabled\n");
- return 0;
+ if (!ret)
+ dev_dbg(drvdata->dev, "TMC-ETF enabled\n");
+ return ret;
}
static void tmc_disable_etf_link(struct coresight_device *csdev,
@@ -576,7 +593,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
* can't be NULL.
*/
memset(drvdata->buf, 0, drvdata->size);
-
[PATCH 44/44] coresight: Remove redundant null pointer check before of_node_put and put_device
From: zhong jiang of_node_put and put_device has taken the null pointer check into account. So it is safe to remove the duplicated check. Signed-off-by: zhong jiang Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index da71c975e3f7..89092f83567e 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -219,12 +219,9 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); - if (rparent) - of_node_put(rparent); - if (rep) - of_node_put(rep); - if (rdev) - put_device(rdev); + of_node_put(rparent); + of_node_put(rep); + put_device(rdev); return ret; } -- 2.7.4
[PATCH 40/44] coresight: dynamic-replicator: Claim device for use
From: Suzuki K Poulose
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index 97f4673452cb..299667b887fc 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -41,8 +41,11 @@ static void replicator_reset(struct replicator_state
*drvdata)
{
CS_UNLOCK(drvdata->base);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ if (!coresight_claim_device_unlocked(drvdata->base)) {
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ coresight_disclaim_device_unlocked(drvdata->base);
+ }
CS_LOCK(drvdata->base);
}
@@ -50,6 +53,7 @@ static void replicator_reset(struct replicator_state *drvdata)
static int replicator_enable(struct coresight_device *csdev, int inport,
int outport)
{
+ int rc = 0;
u32 reg;
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -67,13 +71,19 @@ static int replicator_enable(struct coresight_device
*csdev, int inport,
CS_UNLOCK(drvdata->base);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ rc = coresight_claim_device_unlocked(drvdata->base);
/* Ensure that the outport is enabled. */
- writel_relaxed(0x00, drvdata->base + reg);
+ if (!rc) {
+ writel_relaxed(0x00, drvdata->base + reg);
+ dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
+ }
+
CS_LOCK(drvdata->base);
- dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
- return 0;
+ return rc;
}
static void replicator_disable(struct coresight_device *csdev, int inport,
@@ -99,6 +109,9 @@ static void replicator_disable(struct coresight_device
*csdev, int inport,
/* disable the flow of ATB data through port */
writel_relaxed(0xff, drvdata->base + reg);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ coresight_disclaim_device_unlocked(drvdata->base);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "REPLICATOR disabled\n");
--
2.7.4
[PATCH 39/44] coresight: catu: Claim device before use
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers/hwtracing/coresight/coresight-catu.c
index ff94e58845b7..170fbb66bda2 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -406,6 +406,7 @@ static inline int catu_wait_for_ready(struct catu_drvdata
*drvdata)
static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
{
+ int rc;
u32 control, mode;
struct etr_buf *etr_buf = data;
@@ -418,6 +419,10 @@ static int catu_enable_hw(struct catu_drvdata *drvdata,
void *data)
return -EBUSY;
}
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ return rc;
+
control |= BIT(CATU_CONTROL_ENABLE);
if (etr_buf && etr_buf->mode == ETR_MODE_CATU) {
@@ -459,6 +464,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata)
int rc = 0;
catu_write_control(drvdata, 0);
+ coresight_disclaim_device_unlocked(drvdata->base);
if (catu_wait_for_ready(drvdata)) {
dev_info(drvdata->dev, "Timeout while waiting for READY\n");
rc = -EAGAIN;
--
2.7.4
[PATCH 13/44] coresight: perf: Avoid unncessary CPU hotplug read lock
From: Suzuki K Poulose
We hold the read lock on CPU hotplug to simply copy the
online mask, which is not really needed. And this can
cause a lockdep warning, like :
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency detected
[ 54.644322] 4.18.0-rc3-00042-g2d39e6356bb7-dirty #309 Not tainted
[ 54.650350] --
[ 54.656464] perf/2862 is trying to acquire lock:
[ 54.661031] 7e21d170 (&event->mmap_mutex){+.+.}, at:
perf_event_set_output+0x98/0x138
[ 54.669486]
[ 54.669486] but task is already holding lock:
[ 54.675256] 1080eb1b (&cpuctx_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
[ 54.683704]
[ 54.683704] which lock already depends on the new lock.
[ 54.683704]
[ 54.691797]
[ 54.691797] the existing dependency chain (in reverse order) is:
[ 54.699201]
[ 54.699201] -> #3 (&cpuctx_mutex){+.+.}:
[ 54.704556]__mutex_lock+0x70/0x808
[ 54.708608]mutex_lock_nested+0x1c/0x28
[ 54.713005]perf_event_init_cpu+0x8c/0xd8
[ 54.717574]perf_event_init+0x194/0x1d4
[ 54.721971]start_kernel+0x2b8/0x42c
[ 54.726107]
[ 54.726107] -> #2 (pmus_lock){+.+.}:
[ 54.731114]__mutex_lock+0x70/0x808
[ 54.735165]mutex_lock_nested+0x1c/0x28
[ 54.739560]perf_event_init_cpu+0x30/0xd8
[ 54.744129]cpuhp_invoke_callback+0x84/0x248
[ 54.748954]_cpu_up+0xe8/0x1c8
[ 54.752576]do_cpu_up+0xa8/0xc8
[ 54.756283]cpu_up+0x10/0x18
[ 54.759731]smp_init+0xa0/0x114
[ 54.763438]kernel_init_freeable+0x120/0x288
[ 54.768264]kernel_init+0x10/0x108
[ 54.772230]ret_from_fork+0x10/0x18
[ 54.776279]
[ 54.776279] -> #1 (cpu_hotplug_lock.rw_sem){}:
[ 54.782492]cpus_read_lock+0x34/0xb0
[ 54.786631]etm_setup_aux+0x5c/0x308
[ 54.790769]rb_alloc_aux+0x1ec/0x300
[ 54.794906]perf_mmap+0x284/0x610
[ 54.798787]mmap_region+0x388/0x570
[ 54.802838]do_mmap+0x344/0x4f8
[ 54.806544]vm_mmap_pgoff+0xe4/0x110
[ 54.810682]ksys_mmap_pgoff+0xa8/0x240
[ 54.814992]sys_mmap+0x18/0x28
[ 54.818613]el0_svc_naked+0x30/0x34
[ 54.822661]
[ 54.822661] -> #0 (&event->mmap_mutex){+.+.}:
[ 54.828445]lock_acquire+0x48/0x68
[ 54.832409]__mutex_lock+0x70/0x808
[ 54.836459]mutex_lock_nested+0x1c/0x28
[ 54.840855]perf_event_set_output+0x98/0x138
[ 54.845680]_perf_ioctl+0x2a0/0x6a0
[ 54.849731]perf_ioctl+0x3c/0x68
[ 54.853526]do_vfs_ioctl+0xb8/0xa20
[ 54.857577]ksys_ioctl+0x80/0xb8
[ 54.861370]sys_ioctl+0xc/0x18
[ 54.864990]el0_svc_naked+0x30/0x34
[ 54.869039]
[ 54.869039] other info that might help us debug this:
[ 54.869039]
[ 54.876960] Chain exists of:
[ 54.876960] &event->mmap_mutex --> pmus_lock --> &cpuctx_mutex
[ 54.876960]
[ 54.887217] Possible unsafe locking scenario:
[ 54.887217]
[ 54.893073]CPU0CPU1
[ 54.897552]
[ 54.902030] lock(&cpuctx_mutex);
[ 54.905396]lock(pmus_lock);
[ 54.910911]lock(&cpuctx_mutex);
[ 54.916770] lock(&event->mmap_mutex);
[ 54.920566]
[ 54.920566] *** DEADLOCK ***
[ 54.920566]
[ 54.926424] 1 lock held by perf/2862:
[ 54.930042] #0: 1080eb1b (&cpuctx_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
Since we have per-cpu array for the paths, we simply don't care about
the number of online CPUs. This patch gets rid of the
{get/put}_online_cpus().
Reported-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 6338dd180031..6beb662d230c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -161,15 +161,12 @@ static void *alloc_event_data(int cpu)
if (!event_data)
return NULL;
- /* Make sure nothing disappears under us */
- get_online_cpus();
mask = &event_data->mask;
if (cpu != -1)
cpumask_set_cpu(cpu, mask);
else
cpumask_copy(mask, cpu_online_mask);
- put_online_cpus();
/*
* Each CPU has a single path between source and destination. As such
--
2.7.4
[PATCH 36/44] coresight: Add support for CLAIM tag protocol
From: Suzuki K Poulose
Coresight architecture defines CLAIM tags for a device to negotiate
control of the components (external agent vs self-hosted). Each device
has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM
tags. However, the protocol for the CLAIM tags is IMPLEMENTATION DEFINED.
PSCI has recommendations for the use of the CLAIM tags to negotiate
controls for external agent vs self-hosted use. This patch implements
the recommended protocol by PSCI.
The claim/disclaim operations are performed from the device specific
drivers. The disadvantage is that the calls are sprinkled in each driver,
but this makes the operation much simpler.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-priv.h | 7 +++
drivers/hwtracing/coresight/coresight.c | 86
include/linux/coresight.h| 20 +++
3 files changed, 113 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h
b/drivers/hwtracing/coresight/coresight-priv.h
index c11da5564a67..579f34943bf1 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -25,6 +25,13 @@
#define CORESIGHT_DEVID0xfc8
#define CORESIGHT_DEVTYPE 0xfcc
+
+/*
+ * Coresight device CLAIM protocol.
+ * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
+ */
+#define CORESIGHT_CLAIM_SELF_HOSTEDBIT(1)
+
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index f4f50753cf75..2b0df1a0a8df 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -128,6 +128,92 @@ static int coresight_find_link_outport(struct
coresight_device *csdev,
return -ENODEV;
}
+static inline u32 coresight_read_claim_tags(void __iomem *base)
+{
+ return readl_relaxed(base + CORESIGHT_CLAIMCLR);
+}
+
+static inline bool coresight_is_claimed_self_hosted(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
+}
+
+static inline bool coresight_is_claimed_any(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) != 0;
+}
+
+static inline void coresight_set_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET);
+ isb();
+}
+
+static inline void coresight_clear_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR);
+ isb();
+}
+
+/*
+ * coresight_claim_device_unlocked : Claim the device for self-hosted usage
+ * to prevent an external tool from touching this device. As per PSCI
+ * standards, section "Preserving the execution context" => "Debug and Trace
+ * save and Restore", DBGCLAIM[1] is reserved for Self-hosted debug/trace and
+ * DBGCLAIM[0] is reserved for external tools.
+ *
+ * Called with CS_UNLOCKed for the component.
+ * Returns : 0 on success
+ */
+int coresight_claim_device_unlocked(void __iomem *base)
+{
+ if (coresight_is_claimed_any(base))
+ return -EBUSY;
+
+ coresight_set_claim_tags(base);
+ if (coresight_is_claimed_self_hosted(base))
+ return 0;
+ /* There was a race setting the tags, clean up and fail */
+ coresight_clear_claim_tags(base);
+ return -EBUSY;
+}
+
+int coresight_claim_device(void __iomem *base)
+{
+ int rc;
+
+ CS_UNLOCK(base);
+ rc = coresight_claim_device_unlocked(base);
+ CS_LOCK(base);
+
+ return rc;
+}
+
+/*
+ * coresight_disclaim_device_unlocked : Clear the claim tags for the device.
+ * Called with CS_UNLOCKed for the component.
+ */
+void coresight_disclaim_device_unlocked(void __iomem *base)
+{
+
+ if (coresight_is_claimed_self_hosted(base))
+ coresight_clear_claim_tags(base);
+ else
+ /*
+* The external agent may have not honoured our claim
+* and has manipulated it. Or something else has seriously
+* gone wrong in our driver.
+*/
+ WARN_ON_ONCE(1);
+}
+
+void coresight_disclaim_device(void __iomem *base)
+{
+ CS_UNLOCK(base);
+ coresight_disclaim_device_unlocked(base);
+ CS_LOCK(base);
+}
+
static int coresight_enable_sink(struct coresight_device *csdev,
u32 mode, void *data)
{
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 53535821dc25..46c67a764877 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -257,6 +257,13 @@ extern int coresight_enable(struct coresight_device
*csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
[PATCH 11/44] coresight: etb10: Fix handling of perf mode
From: Suzuki K Poulose If the ETB is already enabled in sysfs mode, the ETB reports success even if a perf mode is requested. Fix this by checking the requested mode. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 306119eaf16a..0dad8626bcfb 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -147,6 +147,10 @@ static int etb_enable(struct coresight_device *csdev, u32 mode) if (val == CS_MODE_PERF) return -EBUSY; + /* Don't let perf disturb sysFS sessions */ + if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF) + return -EBUSY; + /* Nothing to do, the tracer is already enabled. */ if (val == CS_MODE_SYSFS) goto out; -- 2.7.4
[PATCH 05/44] coresight: Fix remote endpoint parsing
From: Suzuki K Poulose
When parsing the remote endpoint of an output port, we do :
rport = of_graph_get_remote_port(ep);
rparent = of_graph_get_remote_port_parent(ep);
and then parse the "remote_port" as if it was the remote endpoint,
which is wrong. The code worked fine because we used endpoint number
as the port number. Let us fix it and optimise a bit as:
remote_ep = of_graph_get_remote_endpoint(ep);
if (remote_ep)
remote_parent = of_graph_get_port_parent(remote_ep);
and then, parse the remote_ep for the port/endpoint details.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 4b279f8fea0c..2ecdd1432b5c 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -134,7 +134,7 @@ static int of_coresight_parse_endpoint(struct device *dev,
int ret = 0;
struct of_endpoint endpoint, rendpoint;
struct device_node *rparent = NULL;
- struct device_node *rport = NULL;
+ struct device_node *rep = NULL;
struct device *rdev = NULL;
do {
@@ -142,16 +142,16 @@ static int of_coresight_parse_endpoint(struct device *dev,
if (of_graph_parse_endpoint(ep, &endpoint))
break;
/*
-* Get a handle on the remote port and parent
-* attached to it.
+* Get a handle on the remote endpoint and the device it is
+* attached to.
*/
- rparent = of_graph_get_remote_port_parent(ep);
- if (!rparent)
+ rep = of_graph_get_remote_endpoint(ep);
+ if (!rep)
break;
- rport = of_graph_get_remote_port(ep);
- if (!rport)
+ rparent = of_graph_get_port_parent(rep);
+ if (!rparent)
break;
- if (of_graph_parse_endpoint(rport, &rendpoint))
+ if (of_graph_parse_endpoint(rep, &rendpoint))
break;
/* If the remote device is not available, defer probing */
@@ -165,15 +165,15 @@ static int of_coresight_parse_endpoint(struct device *dev,
pdata->child_names[i] = devm_kstrdup(dev,
dev_name(rdev),
GFP_KERNEL);
- pdata->child_ports[i] = rendpoint.id;
+ pdata->child_ports[i] = rendpoint.port;
/* Connection record updated */
ret = 1;
} while (0);
if (rparent)
of_node_put(rparent);
- if (rport)
- of_node_put(rport);
+ if (rep)
+ of_node_put(rep);
if (rdev)
put_device(rdev);
--
2.7.4
[PATCH 06/44] coresight: Add helper to check if the endpoint is input
From: Suzuki K Poulose
Add a helper to check if the given endpoint is input.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 2ecdd1432b5c..44903d35009f 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -45,6 +45,11 @@ of_coresight_get_endpoint_device(struct device_node
*endpoint)
endpoint, of_dev_node_match);
}
+static inline bool of_coresight_ep_is_input(struct device_node *ep)
+{
+ return of_property_read_bool(ep, "slave-mode");
+}
+
static void of_coresight_get_ports(const struct device_node *node,
int *nr_inport, int *nr_outport)
{
@@ -56,7 +61,7 @@ static void of_coresight_get_ports(const struct device_node
*node,
if (!ep)
break;
- if (of_property_read_bool(ep, "slave-mode"))
+ if (of_coresight_ep_is_input(ep))
in++;
else
out++;
@@ -213,7 +218,7 @@ of_get_coresight_platform_data(struct device *dev,
* No need to deal with input ports, as processing the
* output ports connected to them will process the details.
*/
- if (of_find_property(ep, "slave-mode", NULL))
+ if (of_coresight_ep_is_input(ep))
continue;
ret = of_coresight_parse_endpoint(dev, ep, pdata, i);
--
2.7.4
[PATCH 29/44] coresight: tmc-etr: Refactor for handling errors
From: Suzuki K Poulose
Refactor the tmc-etr enable operation to make it easier to
handle errors in enabling the hardware. We need to make
sure that the buffer is compatible with the ETR. This
patch re-arranges to make the error handling easier, by
deferring the hardware enablement until all the errors
are checked. This also avoids turning the CATU on/off
during a sysfs read session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 67 -
1 file changed, 43 insertions(+), 24 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 56fea4ff947e..c42693542ec8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -918,21 +918,10 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
-static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
- struct etr_buf *etr_buf)
+static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
{
u32 axictl, sts;
-
- /* Callers should provide an appropriate buffer for use */
- if (WARN_ON(!etr_buf || drvdata->etr_buf))
- return;
- drvdata->etr_buf = etr_buf;
-
- /*
-* If this ETR is connected to a CATU, enable it before we turn
-* this on
-*/
- tmc_etr_enable_catu(drvdata);
+ struct etr_buf *etr_buf = drvdata->etr_buf;
CS_UNLOCK(drvdata->base);
@@ -952,11 +941,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
axictl |= TMC_AXICTL_ARCACHE_OS;
}
- if (etr_buf->mode == ETR_MODE_ETR_SG) {
- if (WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
- return;
+ if (etr_buf->mode == ETR_MODE_ETR_SG)
axictl |= TMC_AXICTL_SCT_GAT_MODE;
- }
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, etr_buf->hwaddr);
@@ -982,6 +968,32 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
CS_LOCK(drvdata->base);
}
+static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
+struct etr_buf *etr_buf)
+{
+ /* Callers should provide an appropriate buffer for use */
+ if (WARN_ON(!etr_buf))
+ return -EINVAL;
+
+ if ((etr_buf->mode == ETR_MODE_ETR_SG) &&
+ WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
+ return -EINVAL;
+
+ if (WARN_ON(drvdata->etr_buf))
+ return -EBUSY;
+
+ /* Set the buffer for the session */
+ drvdata->etr_buf = etr_buf;
+ /*
+* If this ETR is connected to a CATU, enable it before we turn
+* this on.
+*/
+ tmc_etr_enable_catu(drvdata);
+
+ __tmc_etr_enable_hw(drvdata);
+ return 0;
+}
+
/*
* Return the available trace data in the buffer (starts at etr_buf->offset,
* limited by etr_buf->len) from @pos, with a maximum limit of @len,
@@ -1037,7 +1049,7 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata
*drvdata)
}
}
-static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -1053,6 +1065,11 @@ static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata)
CS_LOCK(drvdata->base);
+}
+
+static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etr_disable_hw(drvdata);
/* Disable CATU device if this ETR is connected to one */
tmc_etr_disable_catu(drvdata);
/* Reset the ETR buf used by hardware */
@@ -,8 +1128,9 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
drvdata->sysfs_buf = new_buf;
}
- drvdata->mode = CS_MODE_SYSFS;
- tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -1342,8 +1360,9 @@ static int tmc_enable_etr_sink_perf(struct
coresight_device *csdev, void *data)
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
drvdata->perf_data = etr_perf;
- drvdata->mode = CS_MODE_PERF;
- tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ if (!rc)
+ drvdata->mode = CS_MODE_PERF;
unlock_out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -1425,7 +1444,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
/* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
-
[PATCH 28/44] coresight: Handle failures in enabling a trace path
From: Suzuki K Poulose
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index e73ca6af4765..f4f50753cf75 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -187,8 +187,10 @@ static int coresight_enable_link(struct coresight_device
*csdev,
if (atomic_inc_return(&csdev->refcnt[refport]) == 1) {
if (link_ops(csdev)->enable) {
ret = link_ops(csdev)->enable(csdev, inport, outport);
- if (ret)
+ if (ret) {
+ atomic_dec(&csdev->refcnt[refport]);
return ret;
+ }
}
}
@@ -277,13 +279,21 @@ static bool coresight_disable_source(struct
coresight_device *csdev)
return !csdev->enable;
}
-void coresight_disable_path(struct list_head *path)
+/*
+ * coresight_disable_path_from : Disable components in the given path beyond
+ * @nd in the list. If @nd is NULL, all the components, except the SOURCE are
+ * disabled.
+ */
+static void coresight_disable_path_from(struct list_head *path,
+ struct coresight_node *nd)
{
u32 type;
- struct coresight_node *nd;
struct coresight_device *csdev, *parent, *child;
- list_for_each_entry(nd, path, link) {
+ if (!nd)
+ nd = list_first_entry(path, struct coresight_node, link);
+
+ list_for_each_entry_continue(nd, path, link) {
csdev = nd->csdev;
type = csdev->type;
@@ -303,7 +313,12 @@ void coresight_disable_path(struct list_head *path)
coresight_disable_sink(csdev);
break;
case CORESIGHT_DEV_TYPE_SOURCE:
- /* sources are disabled from either sysFS or Perf */
+ /*
+* We skip the first node in the path assuming that it
+* is the source. So we don't expect a source device in
+* the middle of a path.
+*/
+ WARN_ON(1);
break;
case CORESIGHT_DEV_TYPE_LINK:
parent = list_prev_entry(nd, link)->csdev;
@@ -316,6 +331,11 @@ void coresight_disable_path(struct list_head *path)
}
}
+void coresight_disable_path(struct list_head *path)
+{
+ coresight_disable_path_from(path, NULL);
+}
+
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
{
@@ -369,7 +389,7 @@ int coresight_enable_path(struct list_head *path, u32 mode,
void *sink_data)
out:
return ret;
err:
- coresight_disable_path(path);
+ coresight_disable_path_from(path, nd);
goto out;
}
--
2.7.4
[PATCH 26/44] coresight: tmc: Refactor loops in etb dump
From: Leo Yan
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second
level loop is to iterate index in the range [0 .. drvdata->memwidth);
but the index isn't really used in the code, thus the second level
loop is useless.
This patch is to remove the second level loop; the refactor also reduces
indentation and we can use 'break' to replace 'goto' tag.
Cc: Mathieu Poirier
Signed-off-by: Leo Yan
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 4156c95ce1bb..4bf3bfd7c078 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -38,23 +38,20 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
char *bufp;
u32 read_data, lost;
- int i;
/* Check if the buffer wrapped around. */
lost = readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL;
bufp = drvdata->buf;
drvdata->len = 0;
while (1) {
- for (i = 0; i < drvdata->memwidth; i++) {
- read_data = readl_relaxed(drvdata->base + TMC_RRD);
- if (read_data == 0x)
- goto done;
- memcpy(bufp, &read_data, 4);
- bufp += 4;
- drvdata->len += 4;
- }
+ read_data = readl_relaxed(drvdata->base + TMC_RRD);
+ if (read_data == 0x)
+ break;
+ memcpy(bufp, &read_data, 4);
+ bufp += 4;
+ drvdata->len += 4;
}
-done:
+
if (lost)
coresight_insert_barrier_packet(drvdata->buf);
return;
--
2.7.4
[PATCH 25/44] coresight: etm4x: Configure EL2 exception level when kernel is running in HYP
From: Tomasz Nowicki
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever
hypervisor code should be executed. In this case ETM4x driver must
restrict configuration to EL1 when it setups kernel tracing.
However, there is no separate hypervisor privilege level when VHE
is enabled, the host kernel runs at EL2.
This patch fixes configuration of TRCACATRn register for VHE systems
so that ETM_EXLEVEL_NS_HYP bit is used instead of ETM_EXLEVEL_NS_OS
to on/off kernel tracing. At the same time, it moves common code
to new helper.
Signed-off-by: Tomasz Nowicki
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm4x.c | 40 +--
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index c1dcc7c289a5..b7379e9cfb30 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "coresight-etm4x.h"
#include "coresight-etm-perf.h"
@@ -605,7 +606,7 @@ static void etm4_set_default_config(struct etmv4_config
*config)
config->vinst_ctrl |= BIT(0);
}
-static u64 etm4_get_access_type(struct etmv4_config *config)
+static u64 etm4_get_ns_access_type(struct etmv4_config *config)
{
u64 access_type = 0;
@@ -616,17 +617,26 @@ static u64 etm4_get_access_type(struct etmv4_config
*config)
* Bit[13] Exception level 1 - OS
* Bit[14] Exception level 2 - Hypervisor
* Bit[15] Never implemented
-*
-* Always stay away from hypervisor mode.
*/
- access_type = ETM_EXLEVEL_NS_HYP;
-
- if (config->mode & ETM_MODE_EXCL_KERN)
- access_type |= ETM_EXLEVEL_NS_OS;
+ if (!is_kernel_in_hyp_mode()) {
+ /* Stay away from hypervisor mode for non-VHE */
+ access_type = ETM_EXLEVEL_NS_HYP;
+ if (config->mode & ETM_MODE_EXCL_KERN)
+ access_type |= ETM_EXLEVEL_NS_OS;
+ } else if (config->mode & ETM_MODE_EXCL_KERN) {
+ access_type = ETM_EXLEVEL_NS_HYP;
+ }
if (config->mode & ETM_MODE_EXCL_USER)
access_type |= ETM_EXLEVEL_NS_APP;
+ return access_type;
+}
+
+static u64 etm4_get_access_type(struct etmv4_config *config)
+{
+ u64 access_type = etm4_get_ns_access_type(config);
+
/*
* EXLEVEL_S, bits[11:8], don't trace anything happening
* in secure state.
@@ -880,20 +890,10 @@ void etm4_config_trace_mode(struct etmv4_config *config)
addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
/* clear default config */
- addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
+ addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
+ ETM_EXLEVEL_NS_HYP);
- /*
-* EXLEVEL_NS, bits[15:12]
-* The Exception levels are:
-* Bit[12] Exception level 0 - Application
-* Bit[13] Exception level 1 - OS
-* Bit[14] Exception level 2 - Hypervisor
-* Bit[15] Never implemented
-*/
- if (mode & ETM_MODE_EXCL_KERN)
- addr_acc |= ETM_EXLEVEL_NS_OS;
- else
- addr_acc |= ETM_EXLEVEL_NS_APP;
+ addr_acc |= etm4_get_ns_access_type(config);
config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
--
2.7.4
[PATCH 22/44] coresight: etm-perf: Add support for ETR backend
From: Suzuki K Poulose
Add support for using TMC-ETR as backend for ETM perf tracing.
We use software double buffering at the moment. i.e, the TMC-ETR
uses a separate buffer than the perf ring buffer. The data is
copied to the perf ring buffer once a session completes.
The TMC-ETR would try to match the larger of perf ring buffer
or the ETR buffer size configured via sysfs, scaling down to
a minimum limit of 1MB.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 248 +++-
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 248 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 1aedfc3629c0..56fea4ff947e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -10,6 +10,7 @@
#include
#include
#include "coresight-catu.h"
+#include "coresight-etm-perf.h"
#include "coresight-priv.h"
#include "coresight-tmc.h"
@@ -21,6 +22,28 @@ struct etr_flat_buf {
};
/*
+ * etr_perf_buffer - Perf buffer used for ETR
+ * @etr_buf- Actual buffer used by the ETR
+ * @snaphost - Perf session mode
+ * @head - handle->head at the beginning of the session.
+ * @nr_pages - Number of pages in the ring buffer.
+ * @pages - Array of Pages in the ring buffer.
+ */
+struct etr_perf_buffer {
+ struct etr_buf *etr_buf;
+ boolsnapshot;
+ unsigned long head;
+ int nr_pages;
+ void**pages;
+};
+
+/* Convert the perf index to an offset within the ETR buffer */
+#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
+
+/* Lower limit for ETR hardware buffer */
+#define TMC_ETR_PERF_MIN_BUF_SIZE SZ_1M
+
+/*
* The TMC ETR SG has a page size of 4K. The SG table contains pointers
* to 4KB buffers. However, the OS may use a PAGE_SIZE different from
* 4K (i.e, 16KB or 64KB). This implies that a single OS page could
@@ -1103,10 +1126,228 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
return ret;
}
+/*
+ * tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf.
+ * The size of the hardware buffer is dependent on the size configured
+ * via sysfs and the perf ring buffer size. We prefer to allocate the
+ * largest possible size, scaling down the size by half until it
+ * reaches a minimum limit (1M), beyond which we give up.
+ */
+static struct etr_perf_buffer *
+tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages,
+ void **pages, bool snapshot)
+{
+ struct etr_buf *etr_buf;
+ struct etr_perf_buffer *etr_perf;
+ unsigned long size;
+
+ etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node);
+ if (!etr_perf)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+* Try to match the perf ring buffer size if it is larger
+* than the size requested via sysfs.
+*/
+ if ((nr_pages << PAGE_SHIFT) > drvdata->size) {
+ etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT),
+ 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ }
+
+ /*
+* Else switch to configured size for this ETR
+* and scale down until we hit the minimum limit.
+*/
+ size = drvdata->size;
+ do {
+ etr_buf = tmc_alloc_etr_buf(drvdata, size, 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ size /= 2;
+ } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE);
+
+ kfree(etr_perf);
+ return ERR_PTR(-ENOMEM);
+
+done:
+ etr_perf->etr_buf = etr_buf;
+ return etr_perf;
+}
+
+
+static void *tmc_alloc_etr_buffer(struct coresight_device *csdev,
+ int cpu, void **pages, int nr_pages,
+ bool snapshot)
+{
+ struct etr_perf_buffer *etr_perf;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+
+ etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu),
+ nr_pages, pages, snapshot);
+ if (IS_ERR(etr_perf)) {
+ dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n");
+ return NULL;
+ }
+
+ etr_perf->snapshot = snapshot;
+ etr_perf->nr_pages = nr_pages;
+ etr_perf->pages = pages;
+
+ return etr_perf;
+}
+
+static void tmc_free_etr_buffer(void *config)
+{
+ struct etr_perf_buffer *etr_perf = config;
+
+ if (etr_perf->etr_buf)
+ tmc_free_et
[PATCH 17/44] coresight: tmc-etr: Relax collection of trace from sysfs mode
From: Suzuki K Poulose
Since the ETR now uses mode specific buffers, we can reliably
provide the trace data captured in sysfs mode, even when the ETR
is operating in PERF mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2d6f428176ff..bafd73e71c4c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1168,19 +1168,17 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
goto out;
}
- /* Don't interfere if operated from Perf */
- if (drvdata->mode == CS_MODE_PERF) {
- ret = -EINVAL;
- goto out;
- }
-
- /* If sysfs_buf is NULL the trace data has been read already */
+ /*
+* We can safely allow reads even if the ETR is operating in PERF mode,
+* since the sysfs session is captured in mode specific data.
+* If drvdata::sysfs_data is NULL the trace data has been read already.
+*/
if (!drvdata->sysfs_buf) {
ret = -EINVAL;
goto out;
}
- /* Disable the TMC if we are trying to read from a running session */
+ /* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
tmc_etr_disable_hw(drvdata);
--
2.7.4
[PATCH 15/44] coresight: perf: Disable trace path upon source error
From: Suzuki K Poulose We enable the trace path, before activating the source. If we fail to enable the source, we must disable the path to make sure it is available for another session. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index afe7e7fc1a93..6db76ce6ba5f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -317,11 +317,13 @@ static void etm_event_start(struct perf_event *event, int flags) /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) - goto fail_end_stop; + goto fail_disable_path; out: return; +fail_disable_path: + coresight_disable_path(path); fail_end_stop: perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); perf_aux_output_end(handle, 0); -- 2.7.4
[PATCH 19/44] coresight: perf: Remove reset_buffer call back for sinks
From: Suzuki K Poulose
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make sure the ring buffer
is updated with the trace data. And we store information about the
size of the data collected only to be consumed by the reset_buffer
callback which always follows the update_buffer. This was originally
designed for handling future IPs which could trigger a buffer overflow
interrupt. This patch gets rid of the reset_buffer callback altogether
and performs the actions in update_buffer, making it return the size
collected. We can always add the support for handling the overflow
interrupt case later.
This removes some not-so pretty hack (storing the new head in the
size field for snapshot mode) and cleans it up a little bit.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c| 56 +--
drivers/hwtracing/coresight/coresight-etm-perf.c | 9 +---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 58 +---
include/linux/coresight.h| 6 +--
4 files changed, 26 insertions(+), 103 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 3d4b6df32a06..dba75c905e57 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -319,37 +319,7 @@ static int etb_set_buffer(struct coresight_device *csdev,
return ret;
}
-static unsigned long etb_reset_buffer(struct coresight_device *csdev,
- struct perf_output_handle *handle,
- void *sink_config)
-{
- unsigned long size = 0;
- struct cs_buffers *buf = sink_config;
-
- if (buf) {
- /*
-* In snapshot mode ->data_size holds the new address of the
-* ring buffer's head. The size itself is the whole address
-* range since we want the latest information.
-*/
- if (buf->snapshot)
- handle->head = local_xchg(&buf->data_size,
- buf->nr_pages << PAGE_SHIFT);
-
- /*
-* Tell the tracer PMU how much we got in this run and if
-* something went wrong along the way. Nobody else can use
-* this cs_buffers instance until we are done. As such
-* resetting parameters here and squaring off with the ring
-* buffer API in the tracer PMU is fine.
-*/
- size = local_xchg(&buf->data_size, 0);
- }
-
- return size;
-}
-
-static void etb_update_buffer(struct coresight_device *csdev,
+static unsigned long etb_update_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
@@ -358,13 +328,13 @@ static void etb_update_buffer(struct coresight_device
*csdev,
u8 *buf_ptr;
const u32 *barrier;
u32 read_ptr, write_ptr, capacity;
- u32 status, read_data, to_read;
- unsigned long offset;
+ u32 status, read_data;
+ unsigned long offset, to_read;
struct cs_buffers *buf = sink_config;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
if (!buf)
- return;
+ return 0;
capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
@@ -469,18 +439,17 @@ static void etb_update_buffer(struct coresight_device
*csdev,
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
/*
-* In snapshot mode all we have to do is communicate to
-* perf_aux_output_end() the address of the current head. In full
-* trace mode the same function expects a size to move rb->aux_head
-* forward.
+* In snapshot mode we have to update the handle->head to point
+* to the new location.
*/
- if (buf->snapshot)
- local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
- else
- local_add(to_read, &buf->data_size);
-
+ if (buf->snapshot) {
+ handle->head = (cur * PAGE_SIZE) + offset;
+ to_read = buf->nr_pages << PAGE_SHIFT;
+ }
etb_enable_hw(drvdata);
CS_LOCK(drvdata->base);
+
+ return to_read;
}
static const struct coresight_ops_sink etb_sink_ops = {
@@ -489,7 +458,6 @@ static const struct coresight_ops_sink etb_sink_ops = {
.alloc_buffer = etb_alloc_buffer,
.free_buffer= etb_free_buffer,
.set_buffer = etb_set_buffer,
- .reset_buffer = etb_reset_buffer,
.update_buffer = etb_update_buffer,
};
diff --git
[PATCH 20/44] coresight: perf: Add helper to retrieve sink configuration
From: Suzuki K Poulose
We can always find the sink configuration for a given perf_output_handle.
Add a helper to retrieve the sink configuration for a given
perf_output_handle. This will be used to get rid of the set_buffer()
call back.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 -
drivers/hwtracing/coresight/coresight-etm-perf.h | 26
2 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index ad87441f65d7..16b83d8b2ac2 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -23,20 +23,6 @@
static struct pmu etm_pmu;
static bool etm_perf_up;
-/**
- * struct etm_event_data - Coresight specifics associated to an event
- * @work: Handle to free allocated memory outside IRQ context.
- * @mask: Hold the CPU(s) this event was set for.
- * @snk_config:The sink configuration.
- * @path: An array of path, each slot for one CPU.
- */
-struct etm_event_data {
- struct work_struct work;
- cpumask_t mask;
- void *snk_config;
- struct list_head * __percpu *path;
-};
-
static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index 4197df4faf5e..da7d9336a15c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -7,6 +7,7 @@
#ifndef _CORESIGHT_ETM_PERF_H
#define _CORESIGHT_ETM_PERF_H
+#include
#include "coresight-priv.h"
struct coresight_device;
@@ -42,14 +43,39 @@ struct etm_filters {
boolssstatus;
};
+/**
+ * struct etm_event_data - Coresight specifics associated to an event
+ * @work: Handle to free allocated memory outside IRQ context.
+ * @mask: Hold the CPU(s) this event was set for.
+ * @snk_config:The sink configuration.
+ * @path: An array of path, each slot for one CPU.
+ */
+struct etm_event_data {
+ struct work_struct work;
+ cpumask_t mask;
+ void *snk_config;
+ struct list_head * __percpu *path;
+};
#ifdef CONFIG_CORESIGHT
int etm_perf_symlink(struct coresight_device *csdev, bool link);
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ struct etm_event_data *data = perf_get_aux(handle);
+ if (data)
+ return data->snk_config;
+ return NULL;
+}
#else
static inline int etm_perf_symlink(struct coresight_device *csdev, bool link)
{ return -EINVAL; }
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ return NULL;
+}
+
#endif /* CONFIG_CORESIGHT */
#endif
--
2.7.4
[PATCH 01/44] coresight: Document error handling in coresight_register
From: Suzuki K Poulose
commit 6403587a930c ("coresight: use put_device() instead of kfree()")
fixes the double freeing of resources and ensures that the device
refcount is dropped properly. Add a comment to explain this to
help the readers and prevent people trying to "unfix" it again.
While at it, rename the labels for better readability.
Cc: Mathieu Poirier
Cc: Arvind Yadav
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index 3e07fd335f8c..9fd0c387e678 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -1006,7 +1006,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
if (!csdev) {
ret = -ENOMEM;
- goto err_kzalloc_csdev;
+ goto err_out;
}
if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
@@ -1022,7 +1022,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts) {
ret = -ENOMEM;
- goto err_kzalloc_refcnts;
+ goto err_free_csdev;
}
csdev->refcnt = refcnts;
@@ -1035,7 +1035,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
conns = kcalloc(csdev->nr_outport, sizeof(*conns), GFP_KERNEL);
if (!conns) {
ret = -ENOMEM;
- goto err_kzalloc_conns;
+ goto err_free_refcnts;
}
for (i = 0; i < csdev->nr_outport; i++) {
@@ -1062,7 +1062,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
ret = device_register(&csdev->dev);
if (ret) {
put_device(&csdev->dev);
- goto err_kzalloc_csdev;
+ /*
+* All resources are free'd explicitly via
+* coresight_device_release(), triggered from put_device().
+*/
+ goto err_out;
}
mutex_lock(&coresight_mutex);
@@ -1074,11 +1078,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
return csdev;
-err_kzalloc_conns:
+err_free_refcnts:
kfree(refcnts);
-err_kzalloc_refcnts:
+err_free_csdev:
kfree(csdev);
-err_kzalloc_csdev:
+err_out:
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(coresight_register);
--
2.7.4
[PATCH 3/9] phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/phy-brcm-sata.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c
b/drivers/phy/broadcom/phy-brcm-sata.c
index 8708ea3b4d6d..218735305d85 100644
--- a/drivers/phy/broadcom/phy-brcm-sata.c
+++ b/drivers/phy/broadcom/phy-brcm-sata.c
@@ -47,6 +47,7 @@ enum brcm_sata_phy_version {
BRCM_SATA_PHY_IPROC_NS2,
BRCM_SATA_PHY_IPROC_NSP,
BRCM_SATA_PHY_IPROC_SR,
+ BRCM_SATA_PHY_DSL_28NM,
};
enum brcm_sata_phy_rxaeq_mode {
@@ -96,7 +97,10 @@ enum sata_phy_regs {
PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
PLLCONTROL_0_FREQ_MONITOR = BIT(12),
PLLCONTROL_0_SEQ_START = BIT(15),
+ PLL_CAP_CHARGE_TIME = 0x83,
+ PLL_VCO_CAL_THRESH = 0x84,
PLL_CAP_CONTROL = 0x85,
+ PLL_FREQ_DET_TIME = 0x86,
PLL_ACTRL2 = 0x8b,
PLL_ACTRL2_SELDIV_MASK = 0x1f,
PLL_ACTRL2_SELDIV_SHIFT = 9,
@@ -106,6 +110,9 @@ enum sata_phy_regs {
PLL1_ACTRL2 = 0x82,
PLL1_ACTRL3 = 0x83,
PLL1_ACTRL4 = 0x84,
+ PLL1_ACTRL5 = 0x85,
+ PLL1_ACTRL6 = 0x86,
+ PLL1_ACTRL7 = 0x87,
TX_REG_BANK = 0x070,
TX_ACTRL0 = 0x80,
@@ -119,6 +126,8 @@ enum sata_phy_regs {
AEQ_FRC_EQ_FORCE= BIT(0),
AEQ_FRC_EQ_FORCE_VAL= BIT(1),
AEQRX_REG_BANK_1= 0xe0,
+ AEQRX_SLCAL0_CTRL0 = 0x82,
+ AEQRX_SLCAL1_CTRL0 = 0x86,
OOB_REG_BANK= 0x150,
OOB1_REG_BANK = 0x160,
@@ -168,6 +177,7 @@ static inline void __iomem *brcm_sata_pcb_base(struct
brcm_sata_port *port)
switch (priv->version) {
case BRCM_SATA_PHY_STB_28NM:
case BRCM_SATA_PHY_IPROC_NS2:
+ case BRCM_SATA_PHY_DSL_28NM:
size = SATA_PCB_REG_28NM_SPACE_SIZE;
break;
case BRCM_SATA_PHY_STB_40NM:
@@ -482,6 +492,61 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
return 0;
}
+static int brcm_dsl_sata_init(struct brcm_sata_port *port)
+{
+ void __iomem *base = brcm_sata_pcb_base(port);
+ struct device *dev = port->phy_priv->dev;
+ unsigned int try;
+ u32 tmp;
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3089);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3088);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+0, 0x3000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+0, 0x3000);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+ usleep_range(1000, 2000);
+
+ /* Acquire PLL lock */
+ try = 50;
+ while (try) {
+ tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+ BLOCK0_XGXSSTATUS);
+ if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
+ break;
+ msleep(20);
+ try--;
+ };
+
+ if (!try) {
+ /* PLL did not lock; give up */
+ dev_err(dev, "port%d PLL did not lock\n", port->portnum);
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "port%d initialized\n", port->portnum);
+
+ return 0;
+}
+
static int brcm_sata_phy_init(struct phy *phy)
{
int rc;
@@ -501,6 +566,9 @@ static int brcm_sata_phy_init(struct phy *phy)
case BRCM_SATA_PHY_IPROC_SR:
rc = brcm_sr_sata_init(port);
break;
+ case BRCM_SATA_PHY_DSL_28NM:
+ rc = brcm_dsl_sata_init(port);
+ break;
default:
rc = -ENODEV;
[PATCH 00/44] coresight: next v4.19-rc4
Good day Greg, To start with here is the tally I gathered for inclusion in the 4.20 cycle - please consider at your convenience. As usual everything applies cleanly on your char-misc-next branch (f685fc6ab051). Second, given the increasing number of patches coming into the coresight subsystem and your new reponsabilities, I was wondering if you'd rather receive a pull request from hereon. Let me know what works best for you. Cordially, Mathieu Leo Yan (2): coresight: tmc: Refactor loops in etb dump coresight: tmc: Fix byte-address alignment for RRP Mathieu Poirier (2): coresight: etb10: Refactor etb_drvdata::mode handling coresight: etb10: Splitting function etb_enable() Suzuki K Poulose (37): coresight: Document error handling in coresight_register coresight: platform: Refactor graph endpoint parsing coresight: platform: Fix refcounting for graph nodes coresight: platform: Fix leaking device reference coresight: Fix remote endpoint parsing coresight: Add helper to check if the endpoint is input coresight: platform: Cleanup coresight connection handling coresight: Cleanup coresight DT bindings coresight: Fix handling of sinks coresight: etb10: Fix handling of perf mode coresight: perf: Fix per cpu path management coresight: perf: Avoid unncessary CPU hotplug read lock coresight: perf: Allow tracing on hotplugged CPUs coresight: perf: Disable trace path upon source error coresight: tmc-etr: Handle driver mode specific ETR buffers coresight: tmc-etr: Relax collection of trace from sysfs mode coresight: Convert driver messages to dev_dbg coresight: perf: Remove reset_buffer call back for sinks coresight: perf: Add helper to retrieve sink configuration coresight: perf: Remove set_buffer call back coresight: etm-perf: Add support for ETR backend coresight: Handle failures in enabling a trace path coresight: tmc-etr: Refactor for handling errors coresight: tmc-etr: Handle errors enabling CATU coresight: tmc-etb/etf: Prepare to handle errors enabling coresight: etm4x: Add support for handling errors coresight: etm3: Add support for handling errors coresight: etb10: Handle errors enabling the device coresight: dynamic-replicator: Handle multiple connections coresight: Add support for CLAIM tag protocol coresight: etmx: Claim devices before use coresight: funnel: Claim devices before use coresight: catu: Claim device before use coresight: dynamic-replicator: Claim device for use coreisght: tmc: Claim device before use coresight: dts: binding: Fix example for TPIU component coresight: dts: binding: Update coresight binding examples Tomasz Nowicki (1): coresight: etm4x: Configure EL2 exception level when kernel is running in HYP zhong jiang (2): coresight: Use ERR_CAST instead of ERR_PTR coresight: Remove redundant null pointer check before of_node_put and put_device .../devicetree/bindings/arm/coresight.txt | 120 --- drivers/hwtracing/coresight/coresight-catu.c | 6 + .../coresight/coresight-dynamic-replicator.c | 81 - drivers/hwtracing/coresight/coresight-etb10.c | 183 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 132 +++ drivers/hwtracing/coresight/coresight-etm-perf.h | 26 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 58 +++- drivers/hwtracing/coresight/coresight-etm4x.c | 93 +++-- drivers/hwtracing/coresight/coresight-funnel.c | 28 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- drivers/hwtracing/coresight/coresight-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-stm.c| 4 +- drivers/hwtracing/coresight/coresight-tmc-etf.c| 198 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c| 385 ++--- drivers/hwtracing/coresight/coresight-tmc.c| 4 +- drivers/hwtracing/coresight/coresight-tmc.h| 4 + drivers/hwtracing/coresight/coresight-tpiu.c | 6 +- drivers/hwtracing/coresight/coresight.c| 184 +++--- drivers/hwtracing/coresight/of_coresight.c | 262 +- include/linux/coresight.h | 41 ++- 20 files changed, 1268 insertions(+), 560 deletions(-) -- 2.7.4
[PATCH 03/44] coresight: platform: Fix refcounting for graph nodes
From: Suzuki K Poulose The coresight driver doesn't drop the references on the remote endpoint/port nodes. Add the missing of_node_put() calls. Reported-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 70205f3eae8e..28d3aef1660b 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -168,6 +168,11 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); + if (rparent) + of_node_put(rparent); + if (rport) + of_node_put(rport); + return ret; } -- 2.7.4
[PATCH 09/44] coresight: Use ERR_CAST instead of ERR_PTR
From: zhong jiang
Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
make the code more concise.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2eda5de304c2..11963647e19a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -536,7 +536,7 @@ tmc_init_etr_sg_table(struct device *dev, int node,
sg_table = tmc_alloc_sg_table(dev, node, nr_tpages, nr_dpages, pages);
if (IS_ERR(sg_table)) {
kfree(etr_table);
- return ERR_PTR(PTR_ERR(sg_table));
+ return ERR_CAST(sg_table);
}
etr_table->sg_table = sg_table;
--
2.7.4
[PATCH 5/9] ata: ahci_brcm: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 8/9] ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 6df61518776f..546aabc6f965 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -143,6 +143,36 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
+
+ ahci: sata@8000 {
+ compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0xa000 0x9ac>, <0x8040 0x24>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&pmb0 3 1>;
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy0>;
+ };
+ };
+
+ sata_phy: sata-phy@8100 {
+ compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
+ reg = <0x8100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
/* Legacy UBUS base */
--
2.17.1
[PATCH 9/9] ARM: bcm63138: Enable SATA AHCI and PHY
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm963138dvt.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts
b/arch/arm/boot/dts/bcm963138dvt.dts
index c61673638fa8..8dca97eeaf57 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -41,3 +41,11 @@
brcm,nand-oob-sectors-size = <16>;
};
};
+
+&ahci {
+ status = "okay";
+};
+
+&sata_phy {
+ status = "okay";
+};
--
2.17.1
[PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 0/9] AHCI and SATA PHY support for BCM63138
Hi Kishon, Tejun, This patch series adds support for the SATA AHCI and PHY found on the ARM-basd BCM63138 DSL SoCs. It would probably make sense for patches 1-3 to go through Kishon's tree, patches 4-7 through Tejun's tree, and I would be merging the last two patches through the Broadcom ARM-SoC tree. Let me know if this is not a workable plan, thank you very much! Florian Fainelli (9): dt-bindings: phy: Document BCM63138 compatible string phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence dt-bindings: ata: Document BCM63138 compatible string ata: ahci_brcm: Allow optional reset controller to be used ata: ahci_brcm: Match BCM63138 compatible strings ata: ahci_brcm: Allow using driver or DSL SoCs ARM: dts: BCM63xx: enable SATA PHY and AHCI controller ARM: bcm63138: Enable SATA AHCI and PHY .../bindings/ata/brcm,sata-brcm.txt | 1 + .../devicetree/bindings/phy/brcm-sata-phy.txt | 1 + arch/arm/boot/dts/bcm63138.dtsi | 30 arch/arm/boot/dts/bcm963138dvt.dts| 8 +++ drivers/ata/Kconfig | 3 +- drivers/ata/ahci_brcm.c | 10 +++ drivers/phy/broadcom/Kconfig | 3 +- drivers/phy/broadcom/phy-brcm-sata.c | 70 +++ 8 files changed, 124 insertions(+), 2 deletions(-) -- 2.17.1
[PATCH 4/9] dt-bindings: ata: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-ahci" as a valid compatible string for the standard Broadcom AHCI controller. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt index 0a5b3b47f217..7713a413c6a7 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt @@ -9,6 +9,7 @@ Required properties: "brcm,bcm7445-ahci" "brcm,bcm-nsp-ahci" "brcm,sata3-ahci" + "brcm,bcm63138-ahci" - reg: register mappings for AHCI and SATA_TOP_CTRL - reg-names : "ahci" and "top-ctrl" - interrupts : interrupt mapping for SATA IRQ -- 2.17.1
[PATCH 7/9] ata: ahci_brcm: Allow using driver or DSL SoCs
The Broadcom STB AHCI controller is the same as the one found on DSL SoCs, so we will utilize the same driver on these systems as well. Signed-off-by: Florian Fainelli --- drivers/ata/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 39b181d6bd0d..99698d7fe585 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -121,7 +121,8 @@ config SATA_AHCI_PLATFORM config AHCI_BRCM tristate "Broadcom AHCI SATA support" - depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP + depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP || \ + ARCH_BCM_63XX help This option enables support for the AHCI SATA3 controller found on Broadcom SoC's. -- 2.17.1
[PATCH 6/9] ata: ahci_brcm: Match BCM63138 compatible strings
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 2/9] phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 1/9] dt-bindings: phy: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-sata-phy" as a valid compatible string describing the standard Broadcom SATA PHY block. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index 0aced97d8092..b640845fec67 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -8,6 +8,7 @@ Required properties: "brcm,iproc-nsp-sata-phy" "brcm,phy-sata3" "brcm,iproc-sr-sata-phy" + "brcm,bcm63138-sata-phy" - address-cells: should be 1 - size-cells: should be 0 - reg: register ranges for the PHY PCB interface -- 2.17.1
Re: [PATCH v7 3/4] dt-bindings: power: supply: qcom_bms: Add bindings
On 20 September 2018 17:58:47 BST, Sebastian Reichel wrote: >[Dropped a couple of people from CC, added Baolin] > >Hi Craig, Baolin and Rob, > >On Thu, Sep 20, 2018 at 03:32:29PM +0100, Craig wrote: >> On 16 September 2018 13:10:45 BST, Sebastian Reichel > wrote: >> >Sorry for my long delay in reviewing this. I like the binding, >> >but the "qcom," specific properties should become common properties >> >in >> > >> >Documentation/devicetree/bindings/power/supply/battery.txt >> >and referenced via monitored-battery. > >> Thanks for the review, what bindings for ocv would you prefer? The >> spreadtrum ones or mine? > >Most importantly I want to see only one generic binding supporting >both use cases. As far as I can see there are two major differences: > >1. Qcom uses legend properties and SC27XX embedds this into data >2. Qcom supports temperature based mapping > >The second point is easy: Not having temperature information can >be a subset of the data with temperature info. The main thing to >discuss are the legend properties. I suppose we have these >proposals: > >Proposal A (from Qcom BMS binding): > >ocv-capacity-legend = /bits/ 8 <100 95 90 85 80 75 70 65 60 55 50 45 >...>; >ocv-temp-legend-celsius = /bits/ 8 <(-10) 0 25 50 65>; >ocv-lut-microvolt = <4305 4305 4303 4299 > >Proposal B (from SC27XX binding): > >ocv-cap-table = <4185 100>, <4113 95>, <4066 90>, <4022 85> ...; > >I prefer the second binding (with mV -> uV), but I think it becomes >messy when temperature is added. What do you think about the >following proposal (derived from pinctrl style): > >Proposal C: > >ocv-capacity-table-temperatures = <(-10) 0 10>; >ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, ...; >ocv-capacity-table-1 = <420 100>, <4185000 95>, <4113000 90>, ...; >ocv-capacity-table-2 = <425 100>, <420 95>, <4185000 90>, ...; > >-- Sebastian C looks good to me however I do kinda think it should be millivolts as I don't think any hardware reads in microvolts and the zeroes make it look quite ugly
mmotm 2018-09-20-12-10 uploaded
The mm-of-the-moment snapshot 2018-09-20-12-10 has been uploaded to http://www.ozlabs.org/~akpm/mmotm/ mmotm-readme.txt says README for mm-of-the-moment: http://www.ozlabs.org/~akpm/mmotm/ This is a snapshot of my -mm patch queue. Uploaded at random hopefully more than once a week. You will need quilt to apply these patches to the latest Linus release (4.x or 4.x-rcY). The series file is in broken-out.tar.gz and is duplicated in http://ozlabs.org/~akpm/mmotm/series The file broken-out.tar.gz contains two datestamp files: .DATE and .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, followed by the base kernel version against which this patch series is to be applied. This tree is partially included in linux-next. To see which patches are included in linux-next, consult the `series' file. Only the patches within the #NEXT_PATCHES_START/#NEXT_PATCHES_END markers are included in linux-next. A git tree which contains the memory management portion of this tree is maintained at git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git by Michal Hocko. It contains the patches which are between the "#NEXT_PATCHES_START mm" and "#NEXT_PATCHES_END" markers, from the series file, http://www.ozlabs.org/~akpm/mmotm/series. A full copy of the full kernel tree with the linux-next and mmotm patches already applied is available through git within an hour of the mmotm release. Individual mmotm releases are tagged. The master branch always points to the latest release, so it's constantly rebasing. http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/ To develop on top of mmotm git: $ git remote add mmotm git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git $ git remote update mmotm $ git checkout -b topic mmotm/master $ git send-email mmotm/master.. [...] To rebase a branch with older patches to a new mmotm release: $ git remote update mmotm $ git rebase --onto mmotm/master topic The directory http://www.ozlabs.org/~akpm/mmots/ (mm-of-the-second) contains daily snapshots of the -mm tree. It is updated more frequently than mmotm, and is untested. A git copy of this tree is available at http://git.cmpxchg.org/cgit.cgi/linux-mmots.git/ and use of this tree is similar to http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/, described above. This mmotm tree contains the following patches against 4.19-rc4: (patches marked "*" will be included in linux-next) origin.patch * fork-report-pid-exhaustion-correctly.patch * mm-disable-deferred-struct-page-for-32-bit-arches.patch * proc-kcore-fix-invalid-memory-access-in-multi-page-read-optimization-v3.patch * mm-shmem-correctly-annotate-new-inodes-for-lockdep.patch * kernel-remove-duplicated-include-from-sysc.patch * mm-slowly-shrink-slabs-with-a-relatively-small-number-of-objects.patch * ocfs2-fix-ocfs2-read-block-panic.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages-v7.patch * hugetlb-take-pmd-sharing-into-account-when-flushing-tlb-caches.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5-checkpatch-fixes.patch * mm-thp-fix-mlocking-thp-page-with-migration-enabled.patch * arm-arch-arm-include-asm-pageh-needs-personalityh.patch * linkageh-align-weak-symbols.patch * arm64-lib-use-c-string-functions-with-kasan-enabled.patch * lib-test_kasan-add-tests-for-several-string-memory-api-functions.patch * scripts-tags-add-declare_hashtable.patch * ocfs2-fix-a-gcc-compiled-warning.patch * ocfs2-get-rid-of-ocfs2_is_o2cb_active-function.patch * ocfs2-without-quota-support-try-to-avoid-calling-quota-recovery.patch * ocfs2-dont-use-iocb-when-eiocbqueued-returns.patch * ocfs2-fix-a-misuse-a-of-brelse-after-failing-ocfs2_check_dir_entry.patch * ocfs2-dont-put-and-assigning-null-to-bh-allocated-outside.patch * ocfs2-dlmglue-clean-up-timestamp-handling.patch * fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * ocfs2-fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent-fix.patch * block-restore-proc-partitions-to-not-display-non-partitionable-removable-devices.patch * vfs-allow-dedupe-of-user-owned-read-only-files.patch * vfs-dedupe-should-return-eperm-if-permission-is-not-granted.patch * fs-iomap-change-return-type-to-vm_fault_t.patch * xtensa-use-generic-vgah.patch mm.patch * mm-slubc-switch-to-bitmap_zalloc.patch * mm-rework-memcg-kernel-stack-accounting.patch * mm-drain-memcg-stocks-on-css-offlining.patch * mm-dont-miss-the-last-page-because-of-round-off-error.patch * mm-dont-miss-the-last-page-because-of-round-off-error-fix.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry-fix.patch * mm-mmu_notifier-be-explicit-about-range-invalition-non-bl
[PATCH] kernel/kcov: Replace vm_insert_page with vmf_insert_page
There is a plan to replace vm_insert_page with new API
vmf_insert_page. As part of it, converting vm_insert_page
to use vmf_insert_page.
Signed-off-by: Souptick Joarder
---
kernel/kcov.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/kcov.c b/kernel/kcov.c
index 3ebd09e..8900d8e 100644
--- a/kernel/kcov.c
+++ b/kernel/kcov.c
@@ -293,8 +293,9 @@ static int kcov_mmap(struct file *filep, struct
vm_area_struct *vma)
spin_unlock(&kcov->lock);
for (off = 0; off < size; off += PAGE_SIZE) {
page = vmalloc_to_page(kcov->area + off);
- if (vm_insert_page(vma, vma->vm_start + off, page))
- WARN_ONCE(1, "vm_insert_page() failed");
+ if (vmf_insert_page(vma, vma->vm_start + off, page)
+ != VM_FAULT_NOPAGE)
+ WARN_ONCE(1, "vmf_insert_page() failed");
}
return 0;
}
--
1.9.1
RE: [PATCH V2 4/13] KVM/MMU: Flush tlb directly in the kvm_handle_hva_range()
From: Tianyu Lan Sent: Thursday, September 20, 2018 7:30 AM
> On 9/20/2018 12:08 AM, Michael Kelley (EOSG) wrote:
> > From: Tianyu Lan Sent: Monday, September 17, 2018 8:19 PM
> >> +
> >> + if (ret && kvm_available_flush_tlb_with_range()) {
> >> + kvm_flush_remote_tlbs_with_address(kvm,
> >> + gfn_start,
> >> + gfn_end - gfn_start);
> >
> > Does the above need to be gfn_end - gfn_start + 1?
>
> The flush range depends on the input parameter frame start and frame end
> of for_each_slot_rmap_range().
>
> for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
> PT_MAX_HUGEPAGE_LEVEL,
> gfn_start, gfn_end - 1,
> &iterator)
> ret |= handler(kvm, iterator.rmap, memslot,
> iterator.gfn, iterator.level, data);
>
>
> The start is "gfn_start" and the end is "gfn_end - 1". The flush size is
> (gfn_end - 1) - gfn_start + 1 = gfn_end - gfn_start.
>
Got it. I agree.
Michael
Re: [PATCH] Don't hardcode path as it is architecture dependent
Am Donnerstag, 20. September 2018, 08:26:38 CEST schrieb Ritesh Raj Sarraf:
> The current code fails to run on amd64 because of hardcoded reference to
> i386
>
> Signed-off-by: Ritesh Raj Sarraf
Thanks for spotting this!
> ---
> arch/um/drivers/port_user.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/um/drivers/port_user.c b/arch/um/drivers/port_user.c
> index 9a8e1b64c22e..5f56d11b886f 100644
> --- a/arch/um/drivers/port_user.c
> +++ b/arch/um/drivers/port_user.c
> @@ -168,7 +168,7 @@ int port_connection(int fd, int *socket, int *pid_out)
> {
> int new, err;
> char *argv[] = { "/usr/sbin/in.telnetd", "-L",
> - "/usr/lib/uml/port-helper", NULL };
> + OS_LIB_PATH "/uml/port-helper", NULL };
> struct port_pre_exec_data data;
>
> new = accept(fd, NULL, 0);
Thanks,
//richard
Re: [PATCH v3 00/16] Another round of tsens cleanups
On Wed, Sep 12, 2018 at 03:22:45PM +0530, Amit Kucheria wrote: > This is another series of tsens cleanups before we add interrupt support. > This applies on top of 4.19-rc2. > > Patches [1-6] can directly be applied by Eduardo. > Patches [9-16] can directly be applied by Andy. Eduardo, I ACKed the DTS patches for this. Can you take 9-16 along with the 1-6 through your tree? Thanks, Andy
[PATCH V6 5/6] x86/intel_rdt: Use perf infrastructure for measurements
The success of a cache pseudo-locked region is measured using
performance monitoring events that are programmed directly at the time
the user requests a measurement.
Modifying the performance event registers directly is not appropriate
since it circumvents the in-kernel perf infrastructure that exists to
manage these resources and provide resource arbitration to the
performance monitoring hardware.
The cache pseudo-locking measurements are modified to use the in-kernel
perf infrastructure. Performance events are created and validated with
the appropriate perf API. The performance counters are still read as
directly as possible to avoid the additional cache hits. This is
done safely by first ensuring with the perf API that the counters have
been programmed correctly and only accessing the counters in an
interrupt disabled section where they are not able to be moved.
As part of the transition to the in-kernel perf infrastructure the L2
and L3 measurements are split into two separate measurements that can
be triggered independently. This separation prevents additional cache
misses incurred during the extra testing code used to decide if a
L2 and/or L3 measurement should be made.
Signed-off-by: Reinette Chatre
---
V6:
- Replace an expanded minimum check with min(). Thanks to Peter for
noticing this.
Documentation/x86/intel_rdt_ui.txt | 22 +-
arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c | 304
2 files changed, 203 insertions(+), 123 deletions(-)
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index f662d3c530e5..52b10945ff75 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -520,18 +520,24 @@ the pseudo-locked region:
2) Cache hit and miss measurements using model specific precision counters if
available. Depending on the levels of cache on the system the pseudo_lock_l2
and pseudo_lock_l3 tracepoints are available.
- WARNING: triggering this measurement uses from two (for just L2
- measurements) to four (for L2 and L3 measurements) precision counters on
- the system, if any other measurements are in progress the counters and
- their corresponding event registers will be clobbered.
When a pseudo-locked region is created a new debugfs directory is created for
it in debugfs as /sys/kernel/debug/resctrl/. A single
write-only file, pseudo_lock_measure, is present in this directory. The
-measurement on the pseudo-locked region depends on the number, 1 or 2,
-written to this debugfs file. Since the measurements are recorded with the
-tracing infrastructure the relevant tracepoints need to be enabled before the
-measurement is triggered.
+measurement of the pseudo-locked region depends on the number written to this
+debugfs file:
+1 - writing "1" to the pseudo_lock_measure file will trigger the latency
+ measurement captured in the pseudo_lock_mem_latency tracepoint. See
+ example below.
+2 - writing "2" to the pseudo_lock_measure file will trigger the L2 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l2 tracepoint. See example below.
+3 - writing "3" to the pseudo_lock_measure file will trigger the L3 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l3 tracepoint.
+
+All measurements are recorded with the tracing infrastructure. This requires
+the relevant tracepoints to be enabled before the measurement is triggered.
Example of latency debugging interface:
In this example a pseudo-locked region named "newlock" was created. Here is
diff --git a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
index 33d7968f152a..d68836139cf9 100644
--- a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
+++ b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
@@ -27,6 +27,7 @@
#include
#include
+#include "../../events/perf_event.h" /* For X86_CONFIG() */
#include "intel_rdt.h"
#define CREATE_TRACE_POINTS
@@ -107,16 +108,6 @@ static u64 get_prefetch_disable_bits(void)
return 0;
}
-/*
- * Helper to write 64bit value to MSR without tracing. Used when
- * use of the cache should be restricted and use of registers used
- * for local variables avoided.
- */
-static inline void pseudo_wrmsrl_notrace(unsigned int msr, u64 val)
-{
- __wrmsr(msr, (u32)(val & 0xULL), (u32)(val >> 32));
-}
-
/**
* pseudo_lock_minor_get - Obtain available minor number
* @minor: Pointer to where new minor number will be stored
@@ -925,7 +916,7 @@ static int measure_cycles_lat_fn(void *_plr)
* The actual configuration of the event is set right before use in order
* to use the X86_CONFIG macro.
*/
-static struct perf_event_attr __attribute__((unused)) perf_miss_attr = {
+static struct perf_event_attr perf_miss_attr = {
.type = PERF_TYPE_RAW,
.size = sizeof(struct perf_event_attr),
.pinned = 1,
@@ -
Re: [PATCH v3 16/16] arm64: dts: sdm845: enable tsens thermal zones
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote: > One thermal zone per cpu is defined > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Tested-by: Matthias Kaehlcke > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++ > 1 file changed, 170 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0c9a2aa6a1b5..eb801922f6bb 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi Acked-by: Andy Gross
Re: [PATCH v3 15/16] arm64: dts: msm8916: Add camera thermal zone
On Wed, Sep 12, 2018 at 03:23:00PM +0530, Amit Kucheria wrote: > Initialise the camera thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 + > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 62f079ae9ba3..3dc8b8aa76c7 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 14/16] arm64: dts: msm8916: Add gpu thermal zone
On Wed, Sep 12, 2018 at 03:22:59PM +0530, Amit Kucheria wrote: > Initialise the gpu thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index be27d8dc9e6b..62f079ae9ba3 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 12/16] arm64: dts: msm8916: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:57PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Bjorn Andersson > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 6a277fce..be27d8dc9e6b 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 11/16] arm: dts: msm8974: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:56PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Reviewed-by: Bjorn Andersson > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi > b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 56dbbf788d15..3c4b81c29798 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi Acked-by: Andy Gross
Re: [PATCH v3 10/16] arm64: dts: msm8916: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:55PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8916 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: [PATCH v3 09/16] arm: dts: msm8974: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8974 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: Linux RDMA mini-conf at Plumbers 2018
On Thu, Sep 20, 2018 at 12:19:23PM -0600, Jason Gunthorpe wrote: > This is just a friendly reminder that registration deadlines are > approaching for this conference. Please see > > https://www.linuxplumbersconf.org/event/2/page/7-attend > > For details. > > This year we expect to have close to a day set aside for RDMA related > topics. Including up to half a day for the thorny general kernel issues > related to get_user_pages(), particularly as exasperated by RDMA. > > We have been working on the following concepts for sessions, I've > roughly marked names based on past participation in related email > threads. As we get closer to the conference date we will be organizing > leaders for each section based on these lists, please let us know of > any changes, or desire to be a leader! > > RDMA and get_user_pages > === > Dan Williams > Matthew Wilcox > John Hubbard > Nicholas Piggin > Jan Kara > > RDMA, DAX and persistant memory co-existence. > > Explore the limits of what is possible without using On > Demand Paging Memory Registration. Discuss 'shootdown' > of userspace MRs > > Dirtying pages obtained with get_user_pages() can oops ext4 > discuss open solutions. > > RDMA and PCI peer to peer > = > Don Dutile > Alex Williamson > Christoph Hellwig > Stephen Bates > Logan Gunthorpe > Jérôme Glisse > Christian König > Bjorn Helgaas > > RDMA and PCI peer to peer transactions. IOMMU issues. Integration > with HMM. How to expose PCI BAR memory to userspace and other > drivers as a DMA target. > > Improving testing of RDMA with syzkaller, RXE and Python > > Noa Osherovich > Don Dutile > Jason Gunthorpe > > Problem solve RDMA's distinct lack of public tests. > Provide a better framework for all drivers to test with, > and a framework for basic testing in userspace. > > Worst remaining unfixed syzkaller bugs and how to try to fix them > > How to hook syzkaller more deeply into RDMA. > > IOCTL conversion and new kABI topics > > Jason Gunthorpe > Alex Rosenbaum > > Attempt to close on the remaining tasks to complete the project > > Restore fork() support to userspace > > Container and namespaces for RDMA topics > > Parav Pandit > Doug Ledford > > Remaining sticky situations with containers > > namespaces in sysfs and legacy all-namespace operation > > Remaining CM issues > > Security isolation problems > > Very large Contiguous regions in userspace > == > Christopher Lameter > Parav Pandit > > Poor performance of get_user_pages on very large virtual ranges > > No standardized API to allocate regions to user space > > Carry over from last year > > As we get closer to the conference date the exact schedule will be > published on the conference web site. I belive we have the Thursday > set aside right now. > > If there are any last minute topics people would like to see please > let us know. I want to remind you that Mike wanted to bring the topic of enhancing remote page faults during post-copy container migration in CRIU over RDMA. Thanks > > See you all in Vancouver! > > Thanks, > Jason & Leon > signature.asc Description: PGP signature
Re: [PATCH v4 2/6] dt-bindings: power: Add qcom rpm power domain driver bindings
On Wed, Aug 29, 2018 at 11:31 PM Rajendra Nayak wrote:
>
>
>
> On 7/4/2018 11:27 AM, Viresh Kumar wrote:
> > On 03-07-18, 16:35, Rob Herring wrote:
> >>> +qcom,level values specified in the OPP tables for RPMh power domains
> >>> +should use the RPMH_REGULATOR_LEVEL_* constants from
> >>> +
> >>> +
> >>> + rpmhpd: power-controller {
> >>> + compatible = "qcom,sdm845-rpmhpd";
> >>> + #power-domain-cells = <1>;
> >>> + operating-points-v2 = <&rpmhpd_opp_table>;
> >>> + };
> >>> +
> >>> + rpmhpd_opp_table: opp-table {
> >>> + compatible = "operating-points-v2-qcom-level";
> >>> +
> >>> + rpmhpd_opp_ret: opp1 {
> >>> + qcom,level = ;
> >>> + };
> >>
> >> I don't see the point in using the OPP binding here when you aren't
> >> using *any* of the properties from it.
> >
> > Yeah, that's the case for now. But there are cases (as Stephen
> > mentioned earlier [1]) where the voltage values (and maybe other
> > values like current, etc) would be known and filled in DT. And that's
> > why we all agreed to use OPP tables for PM domains as well, as these
> > are really "operating performance points" of these PM domains.
>
> Rob, are you fine with these bindings then?
Okay, my only thought is whether we should just use 'reg' here, or do
we need 'level' for anything else and should make it common?
Rob
Re: [RFC 02/20] timens: Add timens_offsets
On Wed, Sep 19, 2018 at 09:50:19PM +0100, Dmitry Safonov wrote: > From: Andrei Vagin > > Introduce offsets for time namespace. They will contain adjustment > needed to convert clocks to/from host's. > > Allocate one page for each time namespace that will be premapped into > userspace with vvar pages. Is not it too much?! The whole page per each clone(new-time-ns) call. Moreover everytime it is get explicitly zeroifyed. Don't get me wrong, maybe I miss something obvious, but additional 4K per process, guys :)
[RFC] i2c: qup: Use the interconnect API
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
Use the interconnect API to get() the path between the endpoints used for
data transfers by the I2C QUP and report the needed bandwidth based on the
i2c mode.
Signed-off-by: Georgi Djakov
---
This patch depends on the interconnect API: https://lkml.org/lkml/2018/8/31/444
TODO: Use a macro for converting and rounding to icc units instead of
converting between kilobits, kilobytes etc. in the consumer drivers.
drivers/i2c/busses/i2c-qup.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index c86c3ae1318f..436747a74dc6 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -280,6 +281,11 @@ struct qup_i2c_dev {
void (*read_rx_fifo)(struct qup_i2c_dev *qup);
/* function to write tags in tx fifo for i2c read transfer */
void (*write_rx_tags)(struct qup_i2c_dev *qup);
+
+ /* frequency mode standard */
+ u32 clk_freq;
+ /* interconnect path to scale according to bandwidth needs */
+ struct icc_path *path;
};
static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
@@ -1657,6 +1663,16 @@ static void qup_i2c_disable_clocks(struct qup_i2c_dev
*qup)
clk_disable_unprepare(qup->pclk);
}
+static void qup_i2c_enable_icc(struct qup_i2c_dev *qup)
+{
+ icc_set(qup->path, 0, qup->clk_freq / 8000);
+}
+
+static void qup_i2c_disable_icc(struct qup_i2c_dev *qup)
+{
+ icc_set(qup->path, 0, 0);
+}
+
static const struct acpi_device_id qup_i2c_acpi_match[] = {
{ "QCOM8010"},
{ },
@@ -1784,6 +1800,10 @@ static int qup_i2c_probe(struct platform_device *pdev)
}
ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
} else {
+ qup->path = of_icc_get(qup->dev, "i2c-mem");
+ if (IS_ERR(qup->path))
+ return PTR_ERR(qup->path);
+
qup->clk = devm_clk_get(qup->dev, "core");
if (IS_ERR(qup->clk)) {
dev_err(qup->dev, "Could not get core clock\n");
@@ -1795,6 +1815,8 @@ static int qup_i2c_probe(struct platform_device *pdev)
dev_err(qup->dev, "Could not get iface clock\n");
return PTR_ERR(qup->pclk);
}
+ qup->clk_freq = clk_freq;
+ qup_i2c_enable_icc(qup);
qup_i2c_enable_clocks(qup);
src_clk_freq = clk_get_rate(qup->clk);
}
@@ -1927,6 +1949,7 @@ static int qup_i2c_remove(struct platform_device *pdev)
disable_irq(qup->irq);
qup_i2c_disable_clocks(qup);
+ icc_put(qup->path);
i2c_del_adapter(&qup->adap);
pm_runtime_disable(qup->dev);
pm_runtime_set_suspended(qup->dev);
@@ -1939,6 +1962,7 @@ static int qup_i2c_pm_suspend_runtime(struct device
*device)
struct qup_i2c_dev *qup = dev_get_drvdata(device);
dev_dbg(device, "pm_runtime: suspending...\n");
+ qup_i2c_disable_icc(qup);
qup_i2c_disable_clocks(qup);
return 0;
}
@@ -1948,6 +1972,7 @@ static int qup_i2c_pm_resume_runtime(struct device
*device)
struct qup_i2c_dev *qup = dev_get_drvdata(device);
dev_dbg(device, "pm_runtime: resuming...\n");
+ qup_i2c_enable_icc(qup);
qup_i2c_enable_clocks(qup);
return 0;
}
Linux RDMA mini-conf at Plumbers 2018
This is just a friendly reminder that registration deadlines are approaching for this conference. Please see https://www.linuxplumbersconf.org/event/2/page/7-attend For details. This year we expect to have close to a day set aside for RDMA related topics. Including up to half a day for the thorny general kernel issues related to get_user_pages(), particularly as exasperated by RDMA. We have been working on the following concepts for sessions, I've roughly marked names based on past participation in related email threads. As we get closer to the conference date we will be organizing leaders for each section based on these lists, please let us know of any changes, or desire to be a leader! RDMA and get_user_pages === Dan Williams Matthew Wilcox John Hubbard Nicholas Piggin Jan Kara RDMA, DAX and persistant memory co-existence. Explore the limits of what is possible without using On Demand Paging Memory Registration. Discuss 'shootdown' of userspace MRs Dirtying pages obtained with get_user_pages() can oops ext4 discuss open solutions. RDMA and PCI peer to peer = Don Dutile Alex Williamson Christoph Hellwig Stephen Bates Logan Gunthorpe Jérôme Glisse Christian König Bjorn Helgaas RDMA and PCI peer to peer transactions. IOMMU issues. Integration with HMM. How to expose PCI BAR memory to userspace and other drivers as a DMA target. Improving testing of RDMA with syzkaller, RXE and Python Noa Osherovich Don Dutile Jason Gunthorpe Problem solve RDMA's distinct lack of public tests. Provide a better framework for all drivers to test with, and a framework for basic testing in userspace. Worst remaining unfixed syzkaller bugs and how to try to fix them How to hook syzkaller more deeply into RDMA. IOCTL conversion and new kABI topics Jason Gunthorpe Alex Rosenbaum Attempt to close on the remaining tasks to complete the project Restore fork() support to userspace Container and namespaces for RDMA topics Parav Pandit Doug Ledford Remaining sticky situations with containers namespaces in sysfs and legacy all-namespace operation Remaining CM issues Security isolation problems Very large Contiguous regions in userspace == Christopher Lameter Parav Pandit Poor performance of get_user_pages on very large virtual ranges No standardized API to allocate regions to user space Carry over from last year As we get closer to the conference date the exact schedule will be published on the conference web site. I belive we have the Thursday set aside right now. If there are any last minute topics people would like to see please let us know. See you all in Vancouver! Thanks, Jason & Leon
Re: RFC/error: Re: [PATCH 3/6] perf tools: Improve thread_stack__event() for trace begin / end
Em Thu, Sep 20, 2018 at 03:13:52PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Wed, Sep 19, 2018 at 02:23:35PM +0300, Adrian Hunter escreveu:
> > + return thread_stack__push(thread->ts, ret_addr,
> > + flags && PERF_IP_FLAG_TRACE_END);
> > + } else if (flags & PERF_IP_FLAG_TRACE_BEGIN) {
>
> Some of the build containers caught this:
>
> util/thread-stack.c:274:14: error: use of logical '&&' with constant operand
> [-Werror,-Wconstant-logical-operand]
> flags && PERF_IP_FLAG_TRACE_END);
> ^ ~~
> util/thread-stack.c:274:14: note: use '&' for a bitwise operation
> flags && PERF_IP_FLAG_TRACE_END);
> ^~
> &
> util/thread-stack.c:274:14: note: remove constant to silence this warning
> flags && PERF_IP_FLAG_TRACE_END);
>~^
> 1 error generated.
>
>
> --
>
> Should be a '&' as suggested by:
>
> 16 146.45 debian:9 : FAIL gcc (Debian
> 6.3.0-18+deb9u1) 6.3.0 20170516
> 17 138.35 debian:experimental : FAIL gcc (Debian 8.2.0-4) 8.2.0
Ok, the compilers that caught this was:
debian:9:clang version 3.8.1-24 (tags/RELEASE_381/final)
debian:experimental: clang version 6.0.1-6 (tags/RELEASE_601/final)
Those gcc versions (6.3 and 8.2) compiled it without warnings.
- Arnaldo
>
> I'm changing this here, please Ack.
>
> - Arnaldo
Re: [PATCH 2/2] pinctrl: tegra: move probe to __init section
On 20.09.2018 08:16, Linus Walleij wrote: > On Tue, Sep 18, 2018 at 6:24 PM Stefan Agner wrote: > >> The Tegra pinctrl drivers are always built-in. This allows to use >> platform_driver_probe() and mark several functions as __init. >> This allows the kernel to free about 1KiB of memory if Tegra >> pinctrl drivers are not used. >> >> Signed-off-by: Stefan Agner > > It appears the test robot complains about this patch, so I'll > wait for a v2! Yes I saw it, will send v2 of this patch only. -- Stefan > > Yours, > Linus Walleij
RFC/error: Re: [PATCH 3/6] perf tools: Improve thread_stack__event() for trace begin / end
Em Wed, Sep 19, 2018 at 02:23:35PM +0300, Adrian Hunter escreveu:
> + return thread_stack__push(thread->ts, ret_addr,
> + flags && PERF_IP_FLAG_TRACE_END);
> + } else if (flags & PERF_IP_FLAG_TRACE_BEGIN) {
Some of the build containers caught this:
util/thread-stack.c:274:14: error: use of logical '&&' with constant operand
[-Werror,-Wconstant-logical-operand]
flags && PERF_IP_FLAG_TRACE_END);
^ ~~
util/thread-stack.c:274:14: note: use '&' for a bitwise operation
flags && PERF_IP_FLAG_TRACE_END);
^~
&
util/thread-stack.c:274:14: note: remove constant to silence this warning
flags && PERF_IP_FLAG_TRACE_END);
~^
1 error generated.
--
Should be a '&' as suggested by:
16 146.45 debian:9 : FAIL gcc (Debian 6.3.0-18+deb9u1)
6.3.0 20170516
17 138.35 debian:experimental : FAIL gcc (Debian 8.2.0-4) 8.2.0
I'm changing this here, please Ack.
- Arnaldo
[PATCH v6 1/5] tools, perf, script: Add --insn-trace for instruction decoding
From: Andi Kleen Add a --insn-trace short hand option for decoding and disassembling instruction streams for intel_pt. This automatically pipes the output into the xed disassembler to generate disassembled instructions. This just makes this use model much nicer to use Before % perf record -e intel_pt// ... % perf script --itrace=i0ns --ns -F +insn,-event,-period | xed -F insn: -A -64 swapper 0 [000] 117276.429606186: 81010486 pt_config ([kernel.kallsyms]) nopl %eax, (%rax,%rax,1) swapper 0 [000] 117276.429606186: 8101048b pt_config ([kernel.kallsyms]) add $0x10, %rsp swapper 0 [000] 117276.429606186: 8101048f pt_config ([kernel.kallsyms]) popq %rbx swapper 0 [000] 117276.429606186: 81010490 pt_config ([kernel.kallsyms]) popq %rbp swapper 0 [000] 117276.429606186: 81010491 pt_config ([kernel.kallsyms]) popq %r12 swapper 0 [000] 117276.429606186: 81010493 pt_config ([kernel.kallsyms]) popq %r13 swapper 0 [000] 117276.429606186: 81010495 pt_config ([kernel.kallsyms]) popq %r14 swapper 0 [000] 117276.429606186: 81010497 pt_config ([kernel.kallsyms]) popq %r15 swapper 0 [000] 117276.429606186: 81010499 pt_config ([kernel.kallsyms]) retq swapper 0 [000] 117276.429606186: 8101063e pt_event_add ([kernel.kallsyms]) cmpl $0x1, 0x1b0(%rbx) swapper 0 [000] 117276.429606186: 81010645 pt_event_add ([kernel.kallsyms]) mov $0xffea, %eax swapper 0 [000] 117276.429606186: 8101064a pt_event_add ([kernel.kallsyms]) mov $0x0, %edx swapper 0 [000] 117276.429606186: 8101064f pt_event_add ([kernel.kallsyms]) popq %rbx swapper 0 [000] 117276.429606186: 81010650 pt_event_add ([kernel.kallsyms]) cmovnz %edx, %eax swapper 0 [000] 117276.429606186: 81010653 pt_event_add ([kernel.kallsyms]) jmp 0x81010635 swapper 0 [000] 117276.429606186: 81010635 pt_event_add ([kernel.kallsyms]) retq swapper 0 [000] 117276.429606186: 8115e687 event_sched_in.isra.107 ([kernel.kallsyms])test %eax, %eax Now % perf record -e intel_pt// ... % perf script --insn-trace --xed ... same output ... XED needs to be installed with: > git clone https://github.com/intelxed/mbuild.git mbuild > git clone https://github.com/intelxed/xed > cd xed > mkdir obj > cd obj > ../mfile.py > sudo ../mfile.py --prefix=/usr/local install Signed-off-by: Andi Kleen -- v2: Add separate --xed option v3: Add xed build documentation and update commit --- tools/perf/Documentation/build-xed.txt | 11 +++ tools/perf/Documentation/perf-script.txt | 7 +++ tools/perf/builtin-script.c | 23 +++ 3 files changed, 41 insertions(+) create mode 100644 tools/perf/Documentation/build-xed.txt diff --git a/tools/perf/Documentation/build-xed.txt b/tools/perf/Documentation/build-xed.txt new file mode 100644 index ..8da3028e6dca --- /dev/null +++ b/tools/perf/Documentation/build-xed.txt @@ -0,0 +1,11 @@ + +For --xed the xed tool is needed. Here is how to install it: + +> git clone https://github.com/intelxed/mbuild.git mbuild +> git clone https://github.com/intelxed/xed +> cd xed +> mkdir obj +> cd obj +> ../mfile.py +> sudo ../mfile.py --prefix=/usr/local install + diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index afdafe2110a1..00c655ab4968 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -383,6 +383,13 @@ include::itrace.txt[] will be printed. Each entry has function name and file/line. Enabled by default, disable with --no-inline. +--insn-trace:: + Show instruction stream for intel_pt traces. Combine with --xed to + show disassembly. + +--xed:: + Run xed disassembler on output. Requires installing the xed disassembler. + SEE ALSO linkperf:perf-record[1],
[PATCH v6 2/5] perf, tools, script: Make itrace script default to all calls
From: Andi Kleen
By default perf script for itrace outputs sampled instructions or
branches. In my experience this is confusing to users because it's
hard to correlate with real program behavior. The sampling makes
sense for tools like report that actually sample to reduce
the run time, but run time is normally not a problem for perf script.
It's better to give an accurate representation of the program flow.
Default perf script to output all calls for itrace. That's a much saner
default. The old behavior can be still requested with
perf script --itrace=ibxwpe10
v2: Fix ETM build failure
v3: Really fix ETM build failure (Kim Phillips)
Signed-off-by: Andi Kleen
---
tools/perf/Documentation/itrace.txt | 7 ---
tools/perf/builtin-script.c | 5 -
tools/perf/util/auxtrace.c | 17 -
tools/perf/util/auxtrace.h | 5 -
tools/perf/util/cs-etm.c| 3 ++-
tools/perf/util/intel-bts.c | 3 ++-
tools/perf/util/intel-pt.c | 3 ++-
7 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/tools/perf/Documentation/itrace.txt
b/tools/perf/Documentation/itrace.txt
index a3abe04c779d..c2182cbabde3 100644
--- a/tools/perf/Documentation/itrace.txt
+++ b/tools/perf/Documentation/itrace.txt
@@ -11,10 +11,11 @@
l synthesize last branch entries (use with i or x)
s skip initial number of events
- The default is all events i.e. the same as --itrace=ibxwpe
+ The default is all events i.e. the same as --itrace=ibxwpe,
+ except for perf script where it is --itrace=ce
- In addition, the period (default 10) for instructions events
- can be specified in units of:
+ In addition, the period (default 10, except for perf script where
it is 1)
+ for instructions events can be specified in units of:
i instructions
t ticks
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index 311f5b53dd83..519ebb5a1f96 100644
--- a/tools/perf/builtin-script.c
+++ b/tools/perf/builtin-script.c
@@ -3128,7 +3128,10 @@ int cmd_script(int argc, const char **argv)
char *rec_script_path = NULL;
char *rep_script_path = NULL;
struct perf_session *session;
- struct itrace_synth_opts itrace_synth_opts = { .set = false, };
+ struct itrace_synth_opts itrace_synth_opts = {
+ .set = false,
+ .default_no_sample = true,
+ };
char *script_path = NULL;
const char **__argv;
int i, j, err = 0;
diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c
index c4617bcfd521..72d5ba2479bf 100644
--- a/tools/perf/util/auxtrace.c
+++ b/tools/perf/util/auxtrace.c
@@ -962,16 +962,23 @@ s64 perf_event__process_auxtrace(struct perf_session
*session,
#define PERF_ITRACE_DEFAULT_LAST_BRANCH_SZ 64
#define PERF_ITRACE_MAX_LAST_BRANCH_SZ 1024
-void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts)
+void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts,
+ bool no_sample)
{
- synth_opts->instructions = true;
synth_opts->branches = true;
synth_opts->transactions = true;
synth_opts->ptwrites = true;
synth_opts->pwr_events = true;
synth_opts->errors = true;
- synth_opts->period_type = PERF_ITRACE_DEFAULT_PERIOD_TYPE;
- synth_opts->period = PERF_ITRACE_DEFAULT_PERIOD;
+ if (no_sample) {
+ synth_opts->period_type = PERF_ITRACE_PERIOD_INSTRUCTIONS;
+ synth_opts->period = 1;
+ synth_opts->calls = true;
+ } else {
+ synth_opts->instructions = true;
+ synth_opts->period_type = PERF_ITRACE_DEFAULT_PERIOD_TYPE;
+ synth_opts->period = PERF_ITRACE_DEFAULT_PERIOD;
+ }
synth_opts->callchain_sz = PERF_ITRACE_DEFAULT_CALLCHAIN_SZ;
synth_opts->last_branch_sz = PERF_ITRACE_DEFAULT_LAST_BRANCH_SZ;
synth_opts->initial_skip = 0;
@@ -999,7 +1006,7 @@ int itrace_parse_synth_opts(const struct option *opt,
const char *str,
}
if (!str) {
- itrace_synth_opts__set_default(synth_opts);
+ itrace_synth_opts__set_default(synth_opts, false);
return 0;
}
diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h
index 0a6ce9c4fc11..f6df30187e1c 100644
--- a/tools/perf/util/auxtrace.h
+++ b/tools/perf/util/auxtrace.h
@@ -57,6 +57,7 @@ enum itrace_period_type {
/**
* struct itrace_synth_opts - AUX area tracing synthesis options.
* @set: indicates whether or not options have been set
+ * @default_no_sample: Default to no sampling.
* @inject: indicates the event (not just the sample) must be fully synthesized
* because 'perf inject' will write it out
* @instructions: whether to synthesize 'instruction
[PATCH v6 5/5] perf, tools, script: Support total cycles count
From: Andi Kleen
For perf script brstackinsn also print a running cycles count.
This makes it easier to calculate cycle deltas for code sections
measured with LBRs.
% perf record -b -a sleep 1
% perf script -F +brstackinsn
...
_dl_sysdep_start+330:
7eff9f20583ainsn: 75 c4 # PRED 24
cycles [24]
7eff9f205800insn: 48 83 e8 03
7eff9f205804insn: 48 83 f8 1e
7eff9f205808insn: 77 26
7eff9f20580ainsn: 48 63 04 81
7eff9f20580einsn: 48 01 c8
7eff9f205811insn: ff e0 # MISPRED 31
cycles [7] 0.71 IPC
7eff9f2059c0insn: 44 8b 62 08
7eff9f2059c4insn: e9 67 fe ff ff# PRED 55
cycles [24] 0.04 IPC
7eff9f205830insn: 48 83 c2 10
7eff9f205834insn: 48 8b 02
7eff9f205837insn: 48 85 c0
7eff9f20583ainsn: 75 c4 # PRED 68
cycles [13] 0.23 IPC
Signed-off-by: Andi Kleen
---
v2: reflow line
---
tools/perf/builtin-script.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index 6232658c6f31..53dc27e63d98 100644
--- a/tools/perf/builtin-script.c
+++ b/tools/perf/builtin-script.c
@@ -913,7 +913,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end,
static int ip__fprintf_jump(uint64_t ip, struct branch_entry *en,
struct perf_insn *x, u8 *inbuf, int len,
- int insn, FILE *fp)
+ int insn, FILE *fp, int *total_cycles)
{
int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t#%s%s%s%s", ip,
dump_insn(x, ip, inbuf, len, NULL),
@@ -922,7 +922,8 @@ static int ip__fprintf_jump(uint64_t ip, struct
branch_entry *en,
en->flags.in_tx ? " INTX" : "",
en->flags.abort ? " ABORT" : "");
if (en->flags.cycles) {
- printed += fprintf(fp, " %d cycles", en->flags.cycles);
+ *total_cycles += en->flags.cycles;
+ printed += fprintf(fp, " %d cycles [%d]", *total_cycles,
en->flags.cycles);
if (insn)
printed += fprintf(fp, " %.2f IPC", (float)insn /
en->flags.cycles);
}
@@ -979,6 +980,7 @@ static int perf_sample__fprintf_brstackinsn(struct
perf_sample *sample,
u8 buffer[MAXBB];
unsigned off;
struct symbol *lastsym = NULL;
+ int total_cycles = 0;
if (!(br && br->nr))
return 0;
@@ -999,7 +1001,7 @@ static int perf_sample__fprintf_brstackinsn(struct
perf_sample *sample,
printed += ip__fprintf_sym(br->entries[nr - 1].from, thread,
x.cpumode, x.cpu, &lastsym, attr,
fp);
printed += ip__fprintf_jump(br->entries[nr - 1].from,
&br->entries[nr - 1],
- &x, buffer, len, 0, fp);
+ &x, buffer, len, 0, fp,
&total_cycles);
}
/* Print all blocks */
@@ -1027,7 +1029,8 @@ static int perf_sample__fprintf_brstackinsn(struct
perf_sample *sample,
printed += ip__fprintf_sym(ip, thread, x.cpumode,
x.cpu, &lastsym, attr, fp);
if (ip == end) {
- printed += ip__fprintf_jump(ip,
&br->entries[i], &x, buffer + off, len - off, insn, fp);
+ printed += ip__fprintf_jump(ip,
&br->entries[i], &x, buffer + off, len - off, insn, fp,
+ &total_cycles);
break;
} else {
printed += fprintf(fp, "\t%016" PRIx64
"\t%s\n", ip,
--
2.17.1
Make perf script easier to use for itrace
Implement a range of improvements to make it easier to look at itrace traces with perf script. Nothing here couldn't be done before with some additional scripting, but add simple high level options to make it easier to use. % perf record -e intel_pt//k -a sleep 1 Show function calls: % perf script --call-trace perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_pmu_enable perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) event_filter_match perf 900 [000] 194167.205652203: ([kernel.kallsyms]) group_sched_in perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) event_sched_in.isra.107 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_set_state.part.71 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_update_time perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_pmu_disable perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_log_itrace_start perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_update_userpage Show function calls and returns: % perf script --call-ret-trace perf 900 [000] 194167.205652203: tr strt ([unknown]) pt_config perf 900 [000] 194167.205652203: return ([kernel.kallsyms])pt_config perf 900 [000] 194167.205652203: return ([kernel.kallsyms])pt_event_add perf 900 [000] 194167.205652203: call ([kernel.kallsyms])perf_pmu_enable perf 900 [000] 194167.205652203: return ([kernel.kallsyms])perf_pmu_nop_void perf 900 [000] 194167.205652203: return ([kernel.kallsyms])event_sched_in.isra.107 perf 900 [000] 194167.205652203: call ([kernel.kallsyms])__x86_indirect_thunk_rax perf 900 [000] 194167.205652203: return ([kernel.kallsyms])perf_pmu_nop_int perf 900 [000] 194167.205652203: return ([kernel.kallsyms])group_sched_in perf 900 [000] 194167.205652203: call ([kernel.kallsyms])event_filter_match perf 900 [000] 194167.205652203: return ([kernel.kallsyms])event_filter_match perf 900 [000] 194167.205652203: call ([kernel.kallsyms])group_sched_in Show instruction traces (using XED): % perf script --insn-trace --xed swapper 0 [000] 117276.429606186: 81010486 pt_config ([kernel.kallsyms]) nopl %eax, (%rax,%rax,1) swapper 0 [000] 117276.429606186: 8101048b pt_config ([kernel.kallsyms]) add $0x10, %rsp swapper 0 [000] 117276.429606186: 8101048f pt_config ([kernel.kallsyms]) popq %rbx swapper 0 [000] 117276.429606186: 81010490 pt_config ([kernel.kallsyms]) popq %rbp swapper 0 [000] 117276.429606186: 81010491 pt_config ([kernel.kallsyms]) popq %r12 swapper 0 [000] 117276.429606186: 81010493 pt_config ([kernel.kallsyms]) popq %r13 swapper 0 [000] 117276.429606186: 81010495 pt_config ([kernel.kallsyms]) popq %r14 swapper 0 [000] 117276.429606186: 81010497 pt_config ([kernel.kallsyms]) popq %r15 swapper 0 [000] 117276.429606186: 81010499 pt_config ([kernel.kallsyms]) retq Filter by a ftrace style graph function: % perf script --graph-function group_sched_in --call-trace perf 900 [000] 194167.205652203: ([kernel.kallsyms]) group_sched_in perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) event_sched_in.isra.107 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_set_state.part.71 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_update_time perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_pmu_disable perf 900 [000] 194167.205652203: ([kernel.kallsyms])
[PATCH v6 4/5] tools, perf, script: Implement --graph-function
From: Andi Kleen Add a ftrace style --graph-function argument to perf script that allows to print itrace function calls only below a given function. This makes it easier to find the code of interest in a large trace. % perf record -e intel_pt//k -a sleep 1 % perf script --graph-function group_sched_in --call-trace perf 900 [000] 194167.205652203: ([kernel.kallsyms]) group_sched_in perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) event_sched_in.isra.107 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_set_state.part.71 perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_update_time perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_pmu_disable perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_log_itrace_start perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_event_update_userpage perf 900 [000] 194167.205652203: ([kernel.kallsyms]) calc_timer_values perf 900 [000] 194167.205652203: ([kernel.kallsyms]) sched_clock_cpu perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax perf 900 [000] 194167.205652203: ([kernel.kallsyms]) arch_perf_update_userpage perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __fentry__ perf 900 [000] 194167.205652203: ([kernel.kallsyms]) using_native_sched_clock perf 900 [000] 194167.205652203: ([kernel.kallsyms]) sched_clock_stable perf 900 [000] 194167.205652203: ([kernel.kallsyms]) perf_pmu_enable perf 900 [000] 194167.205652203: ([kernel.kallsyms]) __x86_indirect_thunk_rax swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) group_sched_in swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) __x86_indirect_thunk_rax swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) event_sched_in.isra.107 swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) perf_event_set_state.part.71 swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) perf_event_update_time swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) perf_pmu_disable swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) perf_log_itrace_start swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) __x86_indirect_thunk_rax swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) perf_event_update_userpage swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) calc_timer_values swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) sched_clock_cpu swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) __x86_indirect_thunk_rax swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) arch_perf_update_userpage swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) __fentry__ swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) using_native_sched_clock swapper 0 [001] 194167.205660693: ([kernel.kallsyms]) sched_clock_stable v2: Remove debug printout Signed-off-by: Andi Kleen --- tools/perf/Documentation/perf-script.txt | 4 + tools/perf/builtin-script.c | 96 +++- tools/perf/util/symbol.h | 3 +- tools/perf/util/thread.h | 2 + 4 files changed, 86 insertions(+), 19 deletions(-) diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index 805baabd238e..a2b37ce48094 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -397,6 +397,10 @@ include::itrace.txt[] --call-ret-trace:: Show call and return stream for intel_pt traces. +--graph-function:: + For itrace only show specified functions and their callees for + itrace. Multiple functions can be separated by comma. + SEE ALSO linkperf:perf-record[1], linkperf:perf-script-perl[1], diff --git a/to
[PATCH v6 3/5] tools, perf, script: Add --call-trace and --call-ret-trace
From: Andi Kleen
Add short cut options to print PT call trace and call-ret-trace,
for calls and call and returns. Roughly corresponds to ftrace
function tracer and function graph tracer.
Just makes these common use cases nicer to use.
% perf record -a -e intel_pt// sleep 1
% perf script --call-trace
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_pmu_enable
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
__x86_indirect_thunk_rax
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
event_filter_match
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
group_sched_in
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
__x86_indirect_thunk_rax
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
event_sched_in.isra.107
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_event_set_state.part.71
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_event_update_time
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_pmu_disable
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_log_itrace_start
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
__x86_indirect_thunk_rax
perf 900 [000] 194167.205652203: ([kernel.kallsyms])
perf_event_update_userpage
% perf script --call-ret-trace
perf 900 [000] 194167.205652203: tr strt ([unknown])
pt_config
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])pt_config
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])pt_event_add
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])perf_pmu_enable
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])perf_pmu_nop_void
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])event_sched_in.isra.107
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])__x86_indirect_thunk_rax
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])perf_pmu_nop_int
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])group_sched_in
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])event_filter_match
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])event_filter_match
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])group_sched_in
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])__x86_indirect_thunk_rax
perf 900 [000] 194167.205652203: return
([kernel.kallsyms])perf_pmu_nop_txn
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])event_sched_in.isra.107
perf 900 [000] 194167.205652203: call
([kernel.kallsyms])perf_event_set_state.part.71
Signed-off-by: Andi Kleen
---
v2: Print errors, power, ptwrite too
---
tools/perf/Documentation/perf-script.txt | 7 +++
tools/perf/builtin-script.c | 24
2 files changed, 31 insertions(+)
diff --git a/tools/perf/Documentation/perf-script.txt
b/tools/perf/Documentation/perf-script.txt
index 00c655ab4968..805baabd238e 100644
--- a/tools/perf/Documentation/perf-script.txt
+++ b/tools/perf/Documentation/perf-script.txt
@@ -390,6 +390,13 @@ include::itrace.txt[]
--xed::
Run xed disassembler on output. Requires installing the xed
disassembler.
+--call-trace::
+ Show call stream for intel_pt traces. The CPUs are interleaved, but
+ can be filtered with -C.
+
+--call-ret-trace::
+ Show call and return stream for intel_pt traces.
+
SEE ALSO
linkperf:perf-record[1], linkperf:perf-script-perl[1],
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index 519ebb5a1f96..6c4562973983 100644
--- a/tools/perf/builtin-script.c
+++ b/tools/perf/builtin-script.c
@@ -3119,6 +3119,26 @@ static int parse_xed(const struct option *opt
__maybe_unused,
return 0;
}
+static int parse_call_trace(const struct option *opt __maybe_unused,
+ const char *str __maybe_unused,
+ int unset __maybe_unused)
+{
+ parse_output_fields(NULL, "-ip,-addr,-event,-period,+callindent", 0);
+ itrace_parse_synth_opts(opt, "cewp", 0);
+ nanosecs = true;
+ return 0;
+}
+
+static int parse_callret_trace(const struct option *opt __maybe_unused,
+
Re: [PATCH] iio: magnetometer: Add support for PNI RM3100 9-axis magnetometer
On Thu, Sep 20, 2018 at 03:46:03PM +0200, Peter Meerwald-Stadler wrote:
> On Thu, 20 Sep 2018, Song Qiang wrote:
>
> > PNI RM3100 magnetometer is a high resolution, large signal immunity
> > magnetometer, composed of 3 single sensors and a processing chip.
> > PNI is currently not in the vendors list, so this is also adding it.
>
> comments below
>
> >
> > Following functions are available:
> > - Single-shot measurement from
> >/sys/bus/iio/devices/iio:deviceX/in_magn_{axis}_raw
> > - Triggerd buffer measurement.
> > - Both i2c and spi interface are supported.
> > - Both interrupt and polling measurement is supported, depands on if
> >the 'interrupts' in DT is declared.
> >
> > Signed-off-by: Song Qiang
> > ---
> > .../bindings/iio/magnetometer/pni,rm3100.txt | 57 +++
> > .../devicetree/bindings/vendor-prefixes.txt | 1 +
> > MAINTAINERS | 10 +
> > drivers/iio/magnetometer/Kconfig | 29 ++
> > drivers/iio/magnetometer/Makefile | 4 +
> > drivers/iio/magnetometer/rm3100-core.c| 399 ++
> > drivers/iio/magnetometer/rm3100-i2c.c | 66 +++
> > drivers/iio/magnetometer/rm3100-spi.c | 72
> > drivers/iio/magnetometer/rm3100.h | 90
> > 9 files changed, 728 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt
> > create mode 100644 drivers/iio/magnetometer/rm3100-core.c
> > create mode 100644 drivers/iio/magnetometer/rm3100-i2c.c
> > create mode 100644 drivers/iio/magnetometer/rm3100-spi.c
> > create mode 100644 drivers/iio/magnetometer/rm3100.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt
> > b/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt
> > new file mode 100644
> > index ..d0d2063e943f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt
> > @@ -0,0 +1,57 @@
> > +* PNI RM3100 9-axis magnetometer sensor
> > +
> > +I2C Bus:
> > +
> > +Required properties:
> > +
> > +- compatible : should be "pni,rm3100-i2c"
> > +- reg : the I2C address of the magnetometer
> > +
> > +Optional properties:
> > +
> > +- interrupts: data ready (DRDY) from the chip.
> > + The interrupts can be triggered on rising edges.
> > +
> > + Refer to interrupt-controller/interrupts.txt for generic
> > + interrupt client node bindings.
> > +
> > +- pinctrl-*: pinctrl setup for DRDY line.
> > +
> > +Example:
> > +
> > +rm3100: rm3100@20 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&rm3100_pins>;
> > +
> > + compatible = "pni,rm3100-i2c";
> > + reg = <0x20>;
> > + interrupt-parent = <&gpio0>;
> > + interrupts = <4 IRQ_TYPE_EDGE_RISING>;
> > +};
> > +
> > +SPI Bus:
> > +
> > +Required properties:
> > +
> > +- compatible : should be "pni,rm3100-spi"
> > +- reg : address of sensor, usually 0 or 1.
> > +
> > +Optional properties:
> > +
> > +- interrupts: data ready (DRDY) from the chip.
> > + The interrupts can be triggered on rising edges.
> > +
> > + Refer to interrupt-controller/interrupts.txt for generic
> > + interrupt client node bindings.
> > +
> > +- pinctrl-*: pinctrl setup for DRDY line, depands on archtechture.
>
> depends
> architecture
>
Hi Peter,
Thanks for spending time with my patch!
Sorry for my English, I'll use a spell checker next time.
> > +
> > +Example:
> > +
> > +rm3100: rm3100@0{
> > + compatible = "pni,rm3100-spi";
> > + reg = <0>;
> > +
> > + interrupt-parent = <&gpio0>;
> > + interrupts = <4 IRQ_TYPE_EDGE_RISING>;
> > +};
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > index 41f0b97eb933..5bf3395fe9ae 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > @@ -288,6 +288,7 @@ pine64 Pine64
> > pixcir PIXCIR MICROELECTRONICS Co., Ltd
> > plathome Plat'Home Co., Ltd.
> > plda PLDA
> > +pni PNI
> > portwell Portwell Inc.
> > poslab Poslab Technology Co., Ltd.
> > powervrPowerVR (deprecated, use img)
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 967ce8cdd1cc..30ee8cf98312 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11393,6 +11393,16 @@ M: "Rafael J. Wysocki"
> > S: Maintained
> > F: drivers/pnp/
> >
> > +PNI RM3100 IIO DRIVER
> > +M: Song Qiang
> > +L: linux-...@vger.kernel.org
> > +S: Maintained
> > +F: drivers/iio/magnetometer/rm3100-core.c
> > +F: drivers/iio/magnetometer/rm3100-i2c.c
> > +F: drivers/iio/magnetometer/rm3100-spi.c
> > +F: drivers/iio/magnetometer/rm3100.h
> > +F: Documentation/devicetree/bindings/iio/magnetometer/rm3100.txt
> > +
> > POSIX CLOCKS and TIMERS
> > M: Thomas Gleixner
> > L: linux-kernel@vger.kernel.org
> > diff --git a/drivers/iio/magnetometer/Kconfig
> > b/drivers/iio/magnetometer/Kconfig
>
[PATCH v2 1/2] i2c: i2c-qcom-geni: Properly handle DMA safe buffers
We shouldn't attempt to DMA map the message buffers passed into this driver from the i2c core unless the message we're mapping have been properly setup for DMA. The i2c core indicates such a situation by setting the I2C_M_DMA_SAFE flag, so check for that flag before using DMA mode. We can also bounce the buffer if it isn't already mapped properly by using the i2c_get_dma_safe_msg_buf() APIs, so do that when we want to use DMA for a message. This fixes a problem where the kernel oopses cleaning pages for a buffer that's mapped into the vmalloc space. The pages are returned from request_firmware() and passed down directly to the i2c master to write to the i2c touchscreen device. Mapping vmalloc buffers with dma_map_single() won't work reliably, causing an oops like below: Unable to handle kernel paging request at virtual address ffc01391d000 Mem abort info: Exception class = DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 Data abort info: ISV = 0, ISS = 0x0146 CM = 1, WnR = 1 swapper pgtable: 4k pages, 39-bit VAs, pgd = ff8009ecf000 [ffc01391d000] *pgd=00017fffa803, *pud=00017fffa803, *pmd= Internal error: Oops: 96000146 [#1] PREEMPT SMP Modules linked in: i2c_dev rfcomm uinput lzo lzo_compress hci_uart zram btqca qcom_q6v5_pil bluetooth ecdh_generic qcom_common bridge qcom_q6v5 stp llc ipt_MASQUERADE nf_nat_masquerade_ipv4 xt_mark fuse snd_seq_dummy snd_seq snd_seq_device cfg80211 rmtfs_mem smsc95xx usbnet mii joydev CPU: 0 PID: 1269 Comm: bash Not tainted 4.14.68 #1 task: ffc0dc2a0080 task.stack: ff800f978000 PC is at __clean_dcache_area_poc+0x20/0x38 LR is at __swiotlb_map_page+0x80/0x98 pc : [] lr : [] pstate: 80400149 sp : ff800f97ba20 x29: ff800f97ba50 x28: 0001 x27: ff8008a04000 x26: ffc0f79a7a28 x25: x24: ffbf004e4740 x23: x22: ffc0f94eb290 x21: 9391d000 x20: 0084 x19: 0001 x18: x17: x16: ffc0dc2a0080 x15: x14: 0001 x13: 000c00b1 x12: x11: 0200 x10: x9 : 8000 x8 : 1391d000 x7 : ff80085649dc x6 : x5 : x4 : 0001 x3 : 003f x2 : 0040 x1 : ffc01391d084 x0 : ffc01391d000 Process bash (pid: 1269, stack limit = 0xff800f978000) Call trace: Exception stack(0xff800f97b8e0 to 0xff800f97ba20) b8e0: ffc01391d000 ffc01391d084 0040 003f b900: 0001 ff80085649dc b920: 1391d000 8000 0200 b940: 000c00b1 0001 cros-ec-spi spi10.0: SPI transfer timed out b960: ffc0dc2a0080 0001 b980: 0084 9391d000 ffc0f94eb290 b9a0: ffbf004e4740 ffc0f79a7a28 ff8008a04000 b9c0: 0001 ff800f97ba50 ff800809a150 ff800f97ba20 b9e0: ff800809bfb4 80400149 ffc0f94eb290 ba00: 007f 0001 ff800f97ba50 ff800809bfb4 [] __clean_dcache_area_poc+0x20/0x38 [] geni_se_tx_dma_prep+0x80/0x154 [] geni_i2c_xfer+0x14c/0x3dc [] __i2c_transfer+0x428/0x83c [] i2c_transfer+0x80/0xbc [] i2c_master_send+0x5c/0x90 [] elants_i2c_send+0x30/0x84 [] write_update_fw+0x324/0x484 [] dev_attr_store+0x40/0x58 [] sysfs_kf_write+0x4c/0x64 [] kernfs_fop_write+0x124/0x1bc [] __vfs_write+0x54/0x14c [] vfs_write+0xcc/0x188 [] SyS_write+0x60/0xc0 Exception stack(0xff800f97bec0 to 0xff800f97c000) bec0: 0001 0e7ede70 0002 bee0: 0002 0e7ede70 ec049bc8 0004 bf00: 0002 0e7f0f10 0ca2bcd8 bf20: ff9df69c ebfaf229 bf40: bf60: bf80: bfa0: bfc0: ebfec978 400e0030 0001 0004 bfe0: [] el0_svc_naked+0x34/0x38 Code: 9ac32042 8b010001 d1000443 8a23 (d50b7a20) Reported-by: Philip Chen Cc: Karthikeyan Ramasubramanian Cc: Sagar Dharia Cc: Girish Mahadevan Signed-off-by: Stephen Boyd --- drivers/i2c/busses/i2c-qcom-geni.c | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/bus
