[PATCH 34/44] coresight: etb10: Handle errors enabling the device
From: Suzuki K Poulose
Prepare the etb10 driver to return errors in enabling
the device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 08fa660098f8..824be0c5f592 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -106,7 +106,7 @@ static unsigned int etb_get_buffer_depth(struct etb_drvdata
*drvdata)
return depth;
}
-static void etb_enable_hw(struct etb_drvdata *drvdata)
+static void __etb_enable_hw(struct etb_drvdata *drvdata)
{
int i;
u32 depth;
@@ -134,6 +134,12 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int etb_enable_hw(struct etb_drvdata *drvdata)
+{
+ __etb_enable_hw(drvdata);
+ return 0;
+}
+
static int etb_enable_sysfs(struct coresight_device *csdev)
{
int ret = 0;
@@ -152,8 +158,9 @@ static int etb_enable_sysfs(struct coresight_device *csdev)
if (drvdata->mode == CS_MODE_SYSFS)
goto out;
- drvdata->mode = CS_MODE_SYSFS;
- etb_enable_hw(drvdata);
+ ret = etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -183,8 +190,9 @@ static int etb_enable_perf(struct coresight_device *csdev,
void *data)
if (ret)
goto out;
- drvdata->mode = CS_MODE_PERF;
- etb_enable_hw(drvdata);
+ ret = etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_PERF;
out:
spin_unlock_irqrestore(>spinlock, flags);
--
2.7.4
[PATCH 31/44] coresight: tmc-etb/etf: Prepare to handle errors enabling
From: Suzuki K Poulose
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 73 +++--
1 file changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index b54a3db13fee..36af23d2c0f8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -15,7 +15,7 @@
static int tmc_set_etf_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle);
-static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -34,6 +34,12 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etb_enable_hw(drvdata);
+ return 0;
+}
+
static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
char *bufp;
@@ -73,7 +79,7 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -89,6 +95,12 @@ static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etf_enable_hw(drvdata);
+ return 0;
+}
+
static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -171,8 +183,12 @@ static int tmc_enable_etf_sink_sysfs(struct
coresight_device *csdev)
drvdata->buf = buf;
}
- drvdata->mode = CS_MODE_SYSFS;
- tmc_etb_enable_hw(drvdata);
+ ret = tmc_etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
+ else
+ /* Free up the buffer if we failed to enable */
+ used = false;
out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -191,27 +207,25 @@ static int tmc_enable_etf_sink_perf(struct
coresight_device *csdev, void *data)
struct perf_output_handle *handle = data;
spin_lock_irqsave(>spinlock, flags);
- if (drvdata->reading) {
- ret = -EINVAL;
- goto out;
- }
-
- /*
-* In Perf mode there can be only one writer per sink. There
-* is also no need to continue if the ETB/ETR is already operated
-* from sysFS.
-*/
- if (drvdata->mode != CS_MODE_DISABLED) {
+ do {
ret = -EINVAL;
- goto out;
- }
+ if (drvdata->reading)
+ break;
+ /*
+* In Perf mode there can be only one writer per sink. There
+* is also no need to continue if the ETB/ETF is already
+* operated from sysFS.
+*/
+ if (drvdata->mode != CS_MODE_DISABLED)
+ break;
- ret = tmc_set_etf_buffer(csdev, handle);
- if (!ret) {
- drvdata->mode = CS_MODE_PERF;
- tmc_etb_enable_hw(drvdata);
- }
-out:
+ ret = tmc_set_etf_buffer(csdev, handle);
+ if (ret)
+ break;
+ ret = tmc_etb_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_PERF;
+ } while (0);
spin_unlock_irqrestore(>spinlock, flags);
return ret;
@@ -268,6 +282,7 @@ static void tmc_disable_etf_sink(struct coresight_device
*csdev)
static int tmc_enable_etf_link(struct coresight_device *csdev,
int inport, int outport)
{
+ int ret;
unsigned long flags;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -277,12 +292,14 @@ static int tmc_enable_etf_link(struct coresight_device
*csdev,
return -EBUSY;
}
- tmc_etf_enable_hw(drvdata);
- drvdata->mode = CS_MODE_SYSFS;
+ ret = tmc_etf_enable_hw(drvdata);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
spin_unlock_irqrestore(>spinlock, flags);
- dev_dbg(drvdata->dev, "TMC-ETF enabled\n");
- return 0;
+ if (!ret)
+ dev_dbg(drvdata->dev, "TMC-ETF enabled\n");
+ return ret;
}
static void tmc_disable_etf_link(struct coresight_device *csdev,
@@ -576,7 +593,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
* can't be NULL.
*/
memset(drvdata->buf, 0, drvdata->size);
-
[PATCH 44/44] coresight: Remove redundant null pointer check before of_node_put and put_device
From: zhong jiang of_node_put and put_device has taken the null pointer check into account. So it is safe to remove the duplicated check. Signed-off-by: zhong jiang Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index da71c975e3f7..89092f83567e 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -219,12 +219,9 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); - if (rparent) - of_node_put(rparent); - if (rep) - of_node_put(rep); - if (rdev) - put_device(rdev); + of_node_put(rparent); + of_node_put(rep); + put_device(rdev); return ret; } -- 2.7.4
[PATCH 44/44] coresight: Remove redundant null pointer check before of_node_put and put_device
From: zhong jiang of_node_put and put_device has taken the null pointer check into account. So it is safe to remove the duplicated check. Signed-off-by: zhong jiang Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index da71c975e3f7..89092f83567e 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -219,12 +219,9 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); - if (rparent) - of_node_put(rparent); - if (rep) - of_node_put(rep); - if (rdev) - put_device(rdev); + of_node_put(rparent); + of_node_put(rep); + put_device(rdev); return ret; } -- 2.7.4
[PATCH 40/44] coresight: dynamic-replicator: Claim device for use
From: Suzuki K Poulose
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index 97f4673452cb..299667b887fc 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -41,8 +41,11 @@ static void replicator_reset(struct replicator_state
*drvdata)
{
CS_UNLOCK(drvdata->base);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ if (!coresight_claim_device_unlocked(drvdata->base)) {
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ coresight_disclaim_device_unlocked(drvdata->base);
+ }
CS_LOCK(drvdata->base);
}
@@ -50,6 +53,7 @@ static void replicator_reset(struct replicator_state *drvdata)
static int replicator_enable(struct coresight_device *csdev, int inport,
int outport)
{
+ int rc = 0;
u32 reg;
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -67,13 +71,19 @@ static int replicator_enable(struct coresight_device
*csdev, int inport,
CS_UNLOCK(drvdata->base);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ rc = coresight_claim_device_unlocked(drvdata->base);
/* Ensure that the outport is enabled. */
- writel_relaxed(0x00, drvdata->base + reg);
+ if (!rc) {
+ writel_relaxed(0x00, drvdata->base + reg);
+ dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
+ }
+
CS_LOCK(drvdata->base);
- dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
- return 0;
+ return rc;
}
static void replicator_disable(struct coresight_device *csdev, int inport,
@@ -99,6 +109,9 @@ static void replicator_disable(struct coresight_device
*csdev, int inport,
/* disable the flow of ATB data through port */
writel_relaxed(0xff, drvdata->base + reg);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ coresight_disclaim_device_unlocked(drvdata->base);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "REPLICATOR disabled\n");
--
2.7.4
[PATCH 39/44] coresight: catu: Claim device before use
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers/hwtracing/coresight/coresight-catu.c
index ff94e58845b7..170fbb66bda2 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -406,6 +406,7 @@ static inline int catu_wait_for_ready(struct catu_drvdata
*drvdata)
static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
{
+ int rc;
u32 control, mode;
struct etr_buf *etr_buf = data;
@@ -418,6 +419,10 @@ static int catu_enable_hw(struct catu_drvdata *drvdata,
void *data)
return -EBUSY;
}
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ return rc;
+
control |= BIT(CATU_CONTROL_ENABLE);
if (etr_buf && etr_buf->mode == ETR_MODE_CATU) {
@@ -459,6 +464,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata)
int rc = 0;
catu_write_control(drvdata, 0);
+ coresight_disclaim_device_unlocked(drvdata->base);
if (catu_wait_for_ready(drvdata)) {
dev_info(drvdata->dev, "Timeout while waiting for READY\n");
rc = -EAGAIN;
--
2.7.4
[PATCH 13/44] coresight: perf: Avoid unncessary CPU hotplug read lock
From: Suzuki K Poulose
We hold the read lock on CPU hotplug to simply copy the
online mask, which is not really needed. And this can
cause a lockdep warning, like :
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency detected
[ 54.644322] 4.18.0-rc3-00042-g2d39e6356bb7-dirty #309 Not tainted
[ 54.650350] --
[ 54.656464] perf/2862 is trying to acquire lock:
[ 54.661031] 7e21d170 (>mmap_mutex){+.+.}, at:
perf_event_set_output+0x98/0x138
[ 54.669486]
[ 54.669486] but task is already holding lock:
[ 54.675256] 1080eb1b (_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
[ 54.683704]
[ 54.683704] which lock already depends on the new lock.
[ 54.683704]
[ 54.691797]
[ 54.691797] the existing dependency chain (in reverse order) is:
[ 54.699201]
[ 54.699201] -> #3 (_mutex){+.+.}:
[ 54.704556]__mutex_lock+0x70/0x808
[ 54.708608]mutex_lock_nested+0x1c/0x28
[ 54.713005]perf_event_init_cpu+0x8c/0xd8
[ 54.717574]perf_event_init+0x194/0x1d4
[ 54.721971]start_kernel+0x2b8/0x42c
[ 54.726107]
[ 54.726107] -> #2 (pmus_lock){+.+.}:
[ 54.731114]__mutex_lock+0x70/0x808
[ 54.735165]mutex_lock_nested+0x1c/0x28
[ 54.739560]perf_event_init_cpu+0x30/0xd8
[ 54.744129]cpuhp_invoke_callback+0x84/0x248
[ 54.748954]_cpu_up+0xe8/0x1c8
[ 54.752576]do_cpu_up+0xa8/0xc8
[ 54.756283]cpu_up+0x10/0x18
[ 54.759731]smp_init+0xa0/0x114
[ 54.763438]kernel_init_freeable+0x120/0x288
[ 54.768264]kernel_init+0x10/0x108
[ 54.772230]ret_from_fork+0x10/0x18
[ 54.776279]
[ 54.776279] -> #1 (cpu_hotplug_lock.rw_sem){}:
[ 54.782492]cpus_read_lock+0x34/0xb0
[ 54.786631]etm_setup_aux+0x5c/0x308
[ 54.790769]rb_alloc_aux+0x1ec/0x300
[ 54.794906]perf_mmap+0x284/0x610
[ 54.798787]mmap_region+0x388/0x570
[ 54.802838]do_mmap+0x344/0x4f8
[ 54.806544]vm_mmap_pgoff+0xe4/0x110
[ 54.810682]ksys_mmap_pgoff+0xa8/0x240
[ 54.814992]sys_mmap+0x18/0x28
[ 54.818613]el0_svc_naked+0x30/0x34
[ 54.822661]
[ 54.822661] -> #0 (>mmap_mutex){+.+.}:
[ 54.828445]lock_acquire+0x48/0x68
[ 54.832409]__mutex_lock+0x70/0x808
[ 54.836459]mutex_lock_nested+0x1c/0x28
[ 54.840855]perf_event_set_output+0x98/0x138
[ 54.845680]_perf_ioctl+0x2a0/0x6a0
[ 54.849731]perf_ioctl+0x3c/0x68
[ 54.853526]do_vfs_ioctl+0xb8/0xa20
[ 54.857577]ksys_ioctl+0x80/0xb8
[ 54.861370]sys_ioctl+0xc/0x18
[ 54.864990]el0_svc_naked+0x30/0x34
[ 54.869039]
[ 54.869039] other info that might help us debug this:
[ 54.869039]
[ 54.876960] Chain exists of:
[ 54.876960] >mmap_mutex --> pmus_lock --> _mutex
[ 54.876960]
[ 54.887217] Possible unsafe locking scenario:
[ 54.887217]
[ 54.893073]CPU0CPU1
[ 54.897552]
[ 54.902030] lock(_mutex);
[ 54.905396]lock(pmus_lock);
[ 54.910911]lock(_mutex);
[ 54.916770] lock(>mmap_mutex);
[ 54.920566]
[ 54.920566] *** DEADLOCK ***
[ 54.920566]
[ 54.926424] 1 lock held by perf/2862:
[ 54.930042] #0: 1080eb1b (_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
Since we have per-cpu array for the paths, we simply don't care about
the number of online CPUs. This patch gets rid of the
{get/put}_online_cpus().
Reported-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 6338dd180031..6beb662d230c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -161,15 +161,12 @@ static void *alloc_event_data(int cpu)
if (!event_data)
return NULL;
- /* Make sure nothing disappears under us */
- get_online_cpus();
mask = _data->mask;
if (cpu != -1)
cpumask_set_cpu(cpu, mask);
else
cpumask_copy(mask, cpu_online_mask);
- put_online_cpus();
/*
* Each CPU has a single path between source and destination. As such
--
2.7.4
[PATCH 36/44] coresight: Add support for CLAIM tag protocol
From: Suzuki K Poulose
Coresight architecture defines CLAIM tags for a device to negotiate
control of the components (external agent vs self-hosted). Each device
has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM
tags. However, the protocol for the CLAIM tags is IMPLEMENTATION DEFINED.
PSCI has recommendations for the use of the CLAIM tags to negotiate
controls for external agent vs self-hosted use. This patch implements
the recommended protocol by PSCI.
The claim/disclaim operations are performed from the device specific
drivers. The disadvantage is that the calls are sprinkled in each driver,
but this makes the operation much simpler.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-priv.h | 7 +++
drivers/hwtracing/coresight/coresight.c | 86
include/linux/coresight.h| 20 +++
3 files changed, 113 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h
b/drivers/hwtracing/coresight/coresight-priv.h
index c11da5564a67..579f34943bf1 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -25,6 +25,13 @@
#define CORESIGHT_DEVID0xfc8
#define CORESIGHT_DEVTYPE 0xfcc
+
+/*
+ * Coresight device CLAIM protocol.
+ * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
+ */
+#define CORESIGHT_CLAIM_SELF_HOSTEDBIT(1)
+
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index f4f50753cf75..2b0df1a0a8df 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -128,6 +128,92 @@ static int coresight_find_link_outport(struct
coresight_device *csdev,
return -ENODEV;
}
+static inline u32 coresight_read_claim_tags(void __iomem *base)
+{
+ return readl_relaxed(base + CORESIGHT_CLAIMCLR);
+}
+
+static inline bool coresight_is_claimed_self_hosted(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
+}
+
+static inline bool coresight_is_claimed_any(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) != 0;
+}
+
+static inline void coresight_set_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET);
+ isb();
+}
+
+static inline void coresight_clear_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR);
+ isb();
+}
+
+/*
+ * coresight_claim_device_unlocked : Claim the device for self-hosted usage
+ * to prevent an external tool from touching this device. As per PSCI
+ * standards, section "Preserving the execution context" => "Debug and Trace
+ * save and Restore", DBGCLAIM[1] is reserved for Self-hosted debug/trace and
+ * DBGCLAIM[0] is reserved for external tools.
+ *
+ * Called with CS_UNLOCKed for the component.
+ * Returns : 0 on success
+ */
+int coresight_claim_device_unlocked(void __iomem *base)
+{
+ if (coresight_is_claimed_any(base))
+ return -EBUSY;
+
+ coresight_set_claim_tags(base);
+ if (coresight_is_claimed_self_hosted(base))
+ return 0;
+ /* There was a race setting the tags, clean up and fail */
+ coresight_clear_claim_tags(base);
+ return -EBUSY;
+}
+
+int coresight_claim_device(void __iomem *base)
+{
+ int rc;
+
+ CS_UNLOCK(base);
+ rc = coresight_claim_device_unlocked(base);
+ CS_LOCK(base);
+
+ return rc;
+}
+
+/*
+ * coresight_disclaim_device_unlocked : Clear the claim tags for the device.
+ * Called with CS_UNLOCKed for the component.
+ */
+void coresight_disclaim_device_unlocked(void __iomem *base)
+{
+
+ if (coresight_is_claimed_self_hosted(base))
+ coresight_clear_claim_tags(base);
+ else
+ /*
+* The external agent may have not honoured our claim
+* and has manipulated it. Or something else has seriously
+* gone wrong in our driver.
+*/
+ WARN_ON_ONCE(1);
+}
+
+void coresight_disclaim_device(void __iomem *base)
+{
+ CS_UNLOCK(base);
+ coresight_disclaim_device_unlocked(base);
+ CS_LOCK(base);
+}
+
static int coresight_enable_sink(struct coresight_device *csdev,
u32 mode, void *data)
{
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 53535821dc25..46c67a764877 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -257,6 +257,13 @@ extern int coresight_enable(struct coresight_device
*csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
[PATCH 40/44] coresight: dynamic-replicator: Claim device for use
From: Suzuki K Poulose
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index 97f4673452cb..299667b887fc 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -41,8 +41,11 @@ static void replicator_reset(struct replicator_state
*drvdata)
{
CS_UNLOCK(drvdata->base);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
- writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ if (!coresight_claim_device_unlocked(drvdata->base)) {
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+ writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+ coresight_disclaim_device_unlocked(drvdata->base);
+ }
CS_LOCK(drvdata->base);
}
@@ -50,6 +53,7 @@ static void replicator_reset(struct replicator_state *drvdata)
static int replicator_enable(struct coresight_device *csdev, int inport,
int outport)
{
+ int rc = 0;
u32 reg;
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -67,13 +71,19 @@ static int replicator_enable(struct coresight_device
*csdev, int inport,
CS_UNLOCK(drvdata->base);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ rc = coresight_claim_device_unlocked(drvdata->base);
/* Ensure that the outport is enabled. */
- writel_relaxed(0x00, drvdata->base + reg);
+ if (!rc) {
+ writel_relaxed(0x00, drvdata->base + reg);
+ dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
+ }
+
CS_LOCK(drvdata->base);
- dev_dbg(drvdata->dev, "REPLICATOR enabled\n");
- return 0;
+ return rc;
}
static void replicator_disable(struct coresight_device *csdev, int inport,
@@ -99,6 +109,9 @@ static void replicator_disable(struct coresight_device
*csdev, int inport,
/* disable the flow of ATB data through port */
writel_relaxed(0xff, drvdata->base + reg);
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
+ coresight_disclaim_device_unlocked(drvdata->base);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "REPLICATOR disabled\n");
--
2.7.4
[PATCH 39/44] coresight: catu: Claim device before use
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers/hwtracing/coresight/coresight-catu.c
index ff94e58845b7..170fbb66bda2 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -406,6 +406,7 @@ static inline int catu_wait_for_ready(struct catu_drvdata
*drvdata)
static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
{
+ int rc;
u32 control, mode;
struct etr_buf *etr_buf = data;
@@ -418,6 +419,10 @@ static int catu_enable_hw(struct catu_drvdata *drvdata,
void *data)
return -EBUSY;
}
+ rc = coresight_claim_device_unlocked(drvdata->base);
+ if (rc)
+ return rc;
+
control |= BIT(CATU_CONTROL_ENABLE);
if (etr_buf && etr_buf->mode == ETR_MODE_CATU) {
@@ -459,6 +464,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata)
int rc = 0;
catu_write_control(drvdata, 0);
+ coresight_disclaim_device_unlocked(drvdata->base);
if (catu_wait_for_ready(drvdata)) {
dev_info(drvdata->dev, "Timeout while waiting for READY\n");
rc = -EAGAIN;
--
2.7.4
[PATCH 13/44] coresight: perf: Avoid unncessary CPU hotplug read lock
From: Suzuki K Poulose
We hold the read lock on CPU hotplug to simply copy the
online mask, which is not really needed. And this can
cause a lockdep warning, like :
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency detected
[ 54.644322] 4.18.0-rc3-00042-g2d39e6356bb7-dirty #309 Not tainted
[ 54.650350] --
[ 54.656464] perf/2862 is trying to acquire lock:
[ 54.661031] 7e21d170 (>mmap_mutex){+.+.}, at:
perf_event_set_output+0x98/0x138
[ 54.669486]
[ 54.669486] but task is already holding lock:
[ 54.675256] 1080eb1b (_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
[ 54.683704]
[ 54.683704] which lock already depends on the new lock.
[ 54.683704]
[ 54.691797]
[ 54.691797] the existing dependency chain (in reverse order) is:
[ 54.699201]
[ 54.699201] -> #3 (_mutex){+.+.}:
[ 54.704556]__mutex_lock+0x70/0x808
[ 54.708608]mutex_lock_nested+0x1c/0x28
[ 54.713005]perf_event_init_cpu+0x8c/0xd8
[ 54.717574]perf_event_init+0x194/0x1d4
[ 54.721971]start_kernel+0x2b8/0x42c
[ 54.726107]
[ 54.726107] -> #2 (pmus_lock){+.+.}:
[ 54.731114]__mutex_lock+0x70/0x808
[ 54.735165]mutex_lock_nested+0x1c/0x28
[ 54.739560]perf_event_init_cpu+0x30/0xd8
[ 54.744129]cpuhp_invoke_callback+0x84/0x248
[ 54.748954]_cpu_up+0xe8/0x1c8
[ 54.752576]do_cpu_up+0xa8/0xc8
[ 54.756283]cpu_up+0x10/0x18
[ 54.759731]smp_init+0xa0/0x114
[ 54.763438]kernel_init_freeable+0x120/0x288
[ 54.768264]kernel_init+0x10/0x108
[ 54.772230]ret_from_fork+0x10/0x18
[ 54.776279]
[ 54.776279] -> #1 (cpu_hotplug_lock.rw_sem){}:
[ 54.782492]cpus_read_lock+0x34/0xb0
[ 54.786631]etm_setup_aux+0x5c/0x308
[ 54.790769]rb_alloc_aux+0x1ec/0x300
[ 54.794906]perf_mmap+0x284/0x610
[ 54.798787]mmap_region+0x388/0x570
[ 54.802838]do_mmap+0x344/0x4f8
[ 54.806544]vm_mmap_pgoff+0xe4/0x110
[ 54.810682]ksys_mmap_pgoff+0xa8/0x240
[ 54.814992]sys_mmap+0x18/0x28
[ 54.818613]el0_svc_naked+0x30/0x34
[ 54.822661]
[ 54.822661] -> #0 (>mmap_mutex){+.+.}:
[ 54.828445]lock_acquire+0x48/0x68
[ 54.832409]__mutex_lock+0x70/0x808
[ 54.836459]mutex_lock_nested+0x1c/0x28
[ 54.840855]perf_event_set_output+0x98/0x138
[ 54.845680]_perf_ioctl+0x2a0/0x6a0
[ 54.849731]perf_ioctl+0x3c/0x68
[ 54.853526]do_vfs_ioctl+0xb8/0xa20
[ 54.857577]ksys_ioctl+0x80/0xb8
[ 54.861370]sys_ioctl+0xc/0x18
[ 54.864990]el0_svc_naked+0x30/0x34
[ 54.869039]
[ 54.869039] other info that might help us debug this:
[ 54.869039]
[ 54.876960] Chain exists of:
[ 54.876960] >mmap_mutex --> pmus_lock --> _mutex
[ 54.876960]
[ 54.887217] Possible unsafe locking scenario:
[ 54.887217]
[ 54.893073]CPU0CPU1
[ 54.897552]
[ 54.902030] lock(_mutex);
[ 54.905396]lock(pmus_lock);
[ 54.910911]lock(_mutex);
[ 54.916770] lock(>mmap_mutex);
[ 54.920566]
[ 54.920566] *** DEADLOCK ***
[ 54.920566]
[ 54.926424] 1 lock held by perf/2862:
[ 54.930042] #0: 1080eb1b (_mutex){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
Since we have per-cpu array for the paths, we simply don't care about
the number of online CPUs. This patch gets rid of the
{get/put}_online_cpus().
Reported-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 6338dd180031..6beb662d230c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -161,15 +161,12 @@ static void *alloc_event_data(int cpu)
if (!event_data)
return NULL;
- /* Make sure nothing disappears under us */
- get_online_cpus();
mask = _data->mask;
if (cpu != -1)
cpumask_set_cpu(cpu, mask);
else
cpumask_copy(mask, cpu_online_mask);
- put_online_cpus();
/*
* Each CPU has a single path between source and destination. As such
--
2.7.4
[PATCH 36/44] coresight: Add support for CLAIM tag protocol
From: Suzuki K Poulose
Coresight architecture defines CLAIM tags for a device to negotiate
control of the components (external agent vs self-hosted). Each device
has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM
tags. However, the protocol for the CLAIM tags is IMPLEMENTATION DEFINED.
PSCI has recommendations for the use of the CLAIM tags to negotiate
controls for external agent vs self-hosted use. This patch implements
the recommended protocol by PSCI.
The claim/disclaim operations are performed from the device specific
drivers. The disadvantage is that the calls are sprinkled in each driver,
but this makes the operation much simpler.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-priv.h | 7 +++
drivers/hwtracing/coresight/coresight.c | 86
include/linux/coresight.h| 20 +++
3 files changed, 113 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h
b/drivers/hwtracing/coresight/coresight-priv.h
index c11da5564a67..579f34943bf1 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -25,6 +25,13 @@
#define CORESIGHT_DEVID0xfc8
#define CORESIGHT_DEVTYPE 0xfcc
+
+/*
+ * Coresight device CLAIM protocol.
+ * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
+ */
+#define CORESIGHT_CLAIM_SELF_HOSTEDBIT(1)
+
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index f4f50753cf75..2b0df1a0a8df 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -128,6 +128,92 @@ static int coresight_find_link_outport(struct
coresight_device *csdev,
return -ENODEV;
}
+static inline u32 coresight_read_claim_tags(void __iomem *base)
+{
+ return readl_relaxed(base + CORESIGHT_CLAIMCLR);
+}
+
+static inline bool coresight_is_claimed_self_hosted(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
+}
+
+static inline bool coresight_is_claimed_any(void __iomem *base)
+{
+ return coresight_read_claim_tags(base) != 0;
+}
+
+static inline void coresight_set_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET);
+ isb();
+}
+
+static inline void coresight_clear_claim_tags(void __iomem *base)
+{
+ writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR);
+ isb();
+}
+
+/*
+ * coresight_claim_device_unlocked : Claim the device for self-hosted usage
+ * to prevent an external tool from touching this device. As per PSCI
+ * standards, section "Preserving the execution context" => "Debug and Trace
+ * save and Restore", DBGCLAIM[1] is reserved for Self-hosted debug/trace and
+ * DBGCLAIM[0] is reserved for external tools.
+ *
+ * Called with CS_UNLOCKed for the component.
+ * Returns : 0 on success
+ */
+int coresight_claim_device_unlocked(void __iomem *base)
+{
+ if (coresight_is_claimed_any(base))
+ return -EBUSY;
+
+ coresight_set_claim_tags(base);
+ if (coresight_is_claimed_self_hosted(base))
+ return 0;
+ /* There was a race setting the tags, clean up and fail */
+ coresight_clear_claim_tags(base);
+ return -EBUSY;
+}
+
+int coresight_claim_device(void __iomem *base)
+{
+ int rc;
+
+ CS_UNLOCK(base);
+ rc = coresight_claim_device_unlocked(base);
+ CS_LOCK(base);
+
+ return rc;
+}
+
+/*
+ * coresight_disclaim_device_unlocked : Clear the claim tags for the device.
+ * Called with CS_UNLOCKed for the component.
+ */
+void coresight_disclaim_device_unlocked(void __iomem *base)
+{
+
+ if (coresight_is_claimed_self_hosted(base))
+ coresight_clear_claim_tags(base);
+ else
+ /*
+* The external agent may have not honoured our claim
+* and has manipulated it. Or something else has seriously
+* gone wrong in our driver.
+*/
+ WARN_ON_ONCE(1);
+}
+
+void coresight_disclaim_device(void __iomem *base)
+{
+ CS_UNLOCK(base);
+ coresight_disclaim_device_unlocked(base);
+ CS_LOCK(base);
+}
+
static int coresight_enable_sink(struct coresight_device *csdev,
u32 mode, void *data)
{
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 53535821dc25..46c67a764877 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -257,6 +257,13 @@ extern int coresight_enable(struct coresight_device
*csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
[PATCH 06/44] coresight: Add helper to check if the endpoint is input
From: Suzuki K Poulose
Add a helper to check if the given endpoint is input.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 2ecdd1432b5c..44903d35009f 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -45,6 +45,11 @@ of_coresight_get_endpoint_device(struct device_node
*endpoint)
endpoint, of_dev_node_match);
}
+static inline bool of_coresight_ep_is_input(struct device_node *ep)
+{
+ return of_property_read_bool(ep, "slave-mode");
+}
+
static void of_coresight_get_ports(const struct device_node *node,
int *nr_inport, int *nr_outport)
{
@@ -56,7 +61,7 @@ static void of_coresight_get_ports(const struct device_node
*node,
if (!ep)
break;
- if (of_property_read_bool(ep, "slave-mode"))
+ if (of_coresight_ep_is_input(ep))
in++;
else
out++;
@@ -213,7 +218,7 @@ of_get_coresight_platform_data(struct device *dev,
* No need to deal with input ports, as processing the
* output ports connected to them will process the details.
*/
- if (of_find_property(ep, "slave-mode", NULL))
+ if (of_coresight_ep_is_input(ep))
continue;
ret = of_coresight_parse_endpoint(dev, ep, pdata, i);
--
2.7.4
[PATCH 11/44] coresight: etb10: Fix handling of perf mode
From: Suzuki K Poulose If the ETB is already enabled in sysfs mode, the ETB reports success even if a perf mode is requested. Fix this by checking the requested mode. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 306119eaf16a..0dad8626bcfb 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -147,6 +147,10 @@ static int etb_enable(struct coresight_device *csdev, u32 mode) if (val == CS_MODE_PERF) return -EBUSY; + /* Don't let perf disturb sysFS sessions */ + if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF) + return -EBUSY; + /* Nothing to do, the tracer is already enabled. */ if (val == CS_MODE_SYSFS) goto out; -- 2.7.4
[PATCH 05/44] coresight: Fix remote endpoint parsing
From: Suzuki K Poulose
When parsing the remote endpoint of an output port, we do :
rport = of_graph_get_remote_port(ep);
rparent = of_graph_get_remote_port_parent(ep);
and then parse the "remote_port" as if it was the remote endpoint,
which is wrong. The code worked fine because we used endpoint number
as the port number. Let us fix it and optimise a bit as:
remote_ep = of_graph_get_remote_endpoint(ep);
if (remote_ep)
remote_parent = of_graph_get_port_parent(remote_ep);
and then, parse the remote_ep for the port/endpoint details.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 4b279f8fea0c..2ecdd1432b5c 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -134,7 +134,7 @@ static int of_coresight_parse_endpoint(struct device *dev,
int ret = 0;
struct of_endpoint endpoint, rendpoint;
struct device_node *rparent = NULL;
- struct device_node *rport = NULL;
+ struct device_node *rep = NULL;
struct device *rdev = NULL;
do {
@@ -142,16 +142,16 @@ static int of_coresight_parse_endpoint(struct device *dev,
if (of_graph_parse_endpoint(ep, ))
break;
/*
-* Get a handle on the remote port and parent
-* attached to it.
+* Get a handle on the remote endpoint and the device it is
+* attached to.
*/
- rparent = of_graph_get_remote_port_parent(ep);
- if (!rparent)
+ rep = of_graph_get_remote_endpoint(ep);
+ if (!rep)
break;
- rport = of_graph_get_remote_port(ep);
- if (!rport)
+ rparent = of_graph_get_port_parent(rep);
+ if (!rparent)
break;
- if (of_graph_parse_endpoint(rport, ))
+ if (of_graph_parse_endpoint(rep, ))
break;
/* If the remote device is not available, defer probing */
@@ -165,15 +165,15 @@ static int of_coresight_parse_endpoint(struct device *dev,
pdata->child_names[i] = devm_kstrdup(dev,
dev_name(rdev),
GFP_KERNEL);
- pdata->child_ports[i] = rendpoint.id;
+ pdata->child_ports[i] = rendpoint.port;
/* Connection record updated */
ret = 1;
} while (0);
if (rparent)
of_node_put(rparent);
- if (rport)
- of_node_put(rport);
+ if (rep)
+ of_node_put(rep);
if (rdev)
put_device(rdev);
--
2.7.4
[PATCH 11/44] coresight: etb10: Fix handling of perf mode
From: Suzuki K Poulose If the ETB is already enabled in sysfs mode, the ETB reports success even if a perf mode is requested. Fix this by checking the requested mode. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 306119eaf16a..0dad8626bcfb 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -147,6 +147,10 @@ static int etb_enable(struct coresight_device *csdev, u32 mode) if (val == CS_MODE_PERF) return -EBUSY; + /* Don't let perf disturb sysFS sessions */ + if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF) + return -EBUSY; + /* Nothing to do, the tracer is already enabled. */ if (val == CS_MODE_SYSFS) goto out; -- 2.7.4
[PATCH 05/44] coresight: Fix remote endpoint parsing
From: Suzuki K Poulose
When parsing the remote endpoint of an output port, we do :
rport = of_graph_get_remote_port(ep);
rparent = of_graph_get_remote_port_parent(ep);
and then parse the "remote_port" as if it was the remote endpoint,
which is wrong. The code worked fine because we used endpoint number
as the port number. Let us fix it and optimise a bit as:
remote_ep = of_graph_get_remote_endpoint(ep);
if (remote_ep)
remote_parent = of_graph_get_port_parent(remote_ep);
and then, parse the remote_ep for the port/endpoint details.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 4b279f8fea0c..2ecdd1432b5c 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -134,7 +134,7 @@ static int of_coresight_parse_endpoint(struct device *dev,
int ret = 0;
struct of_endpoint endpoint, rendpoint;
struct device_node *rparent = NULL;
- struct device_node *rport = NULL;
+ struct device_node *rep = NULL;
struct device *rdev = NULL;
do {
@@ -142,16 +142,16 @@ static int of_coresight_parse_endpoint(struct device *dev,
if (of_graph_parse_endpoint(ep, ))
break;
/*
-* Get a handle on the remote port and parent
-* attached to it.
+* Get a handle on the remote endpoint and the device it is
+* attached to.
*/
- rparent = of_graph_get_remote_port_parent(ep);
- if (!rparent)
+ rep = of_graph_get_remote_endpoint(ep);
+ if (!rep)
break;
- rport = of_graph_get_remote_port(ep);
- if (!rport)
+ rparent = of_graph_get_port_parent(rep);
+ if (!rparent)
break;
- if (of_graph_parse_endpoint(rport, ))
+ if (of_graph_parse_endpoint(rep, ))
break;
/* If the remote device is not available, defer probing */
@@ -165,15 +165,15 @@ static int of_coresight_parse_endpoint(struct device *dev,
pdata->child_names[i] = devm_kstrdup(dev,
dev_name(rdev),
GFP_KERNEL);
- pdata->child_ports[i] = rendpoint.id;
+ pdata->child_ports[i] = rendpoint.port;
/* Connection record updated */
ret = 1;
} while (0);
if (rparent)
of_node_put(rparent);
- if (rport)
- of_node_put(rport);
+ if (rep)
+ of_node_put(rep);
if (rdev)
put_device(rdev);
--
2.7.4
[PATCH 06/44] coresight: Add helper to check if the endpoint is input
From: Suzuki K Poulose
Add a helper to check if the given endpoint is input.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c
b/drivers/hwtracing/coresight/of_coresight.c
index 2ecdd1432b5c..44903d35009f 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -45,6 +45,11 @@ of_coresight_get_endpoint_device(struct device_node
*endpoint)
endpoint, of_dev_node_match);
}
+static inline bool of_coresight_ep_is_input(struct device_node *ep)
+{
+ return of_property_read_bool(ep, "slave-mode");
+}
+
static void of_coresight_get_ports(const struct device_node *node,
int *nr_inport, int *nr_outport)
{
@@ -56,7 +61,7 @@ static void of_coresight_get_ports(const struct device_node
*node,
if (!ep)
break;
- if (of_property_read_bool(ep, "slave-mode"))
+ if (of_coresight_ep_is_input(ep))
in++;
else
out++;
@@ -213,7 +218,7 @@ of_get_coresight_platform_data(struct device *dev,
* No need to deal with input ports, as processing the
* output ports connected to them will process the details.
*/
- if (of_find_property(ep, "slave-mode", NULL))
+ if (of_coresight_ep_is_input(ep))
continue;
ret = of_coresight_parse_endpoint(dev, ep, pdata, i);
--
2.7.4
[PATCH 29/44] coresight: tmc-etr: Refactor for handling errors
From: Suzuki K Poulose
Refactor the tmc-etr enable operation to make it easier to
handle errors in enabling the hardware. We need to make
sure that the buffer is compatible with the ETR. This
patch re-arranges to make the error handling easier, by
deferring the hardware enablement until all the errors
are checked. This also avoids turning the CATU on/off
during a sysfs read session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 67 -
1 file changed, 43 insertions(+), 24 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 56fea4ff947e..c42693542ec8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -918,21 +918,10 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
-static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
- struct etr_buf *etr_buf)
+static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
{
u32 axictl, sts;
-
- /* Callers should provide an appropriate buffer for use */
- if (WARN_ON(!etr_buf || drvdata->etr_buf))
- return;
- drvdata->etr_buf = etr_buf;
-
- /*
-* If this ETR is connected to a CATU, enable it before we turn
-* this on
-*/
- tmc_etr_enable_catu(drvdata);
+ struct etr_buf *etr_buf = drvdata->etr_buf;
CS_UNLOCK(drvdata->base);
@@ -952,11 +941,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
axictl |= TMC_AXICTL_ARCACHE_OS;
}
- if (etr_buf->mode == ETR_MODE_ETR_SG) {
- if (WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
- return;
+ if (etr_buf->mode == ETR_MODE_ETR_SG)
axictl |= TMC_AXICTL_SCT_GAT_MODE;
- }
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, etr_buf->hwaddr);
@@ -982,6 +968,32 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
CS_LOCK(drvdata->base);
}
+static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
+struct etr_buf *etr_buf)
+{
+ /* Callers should provide an appropriate buffer for use */
+ if (WARN_ON(!etr_buf))
+ return -EINVAL;
+
+ if ((etr_buf->mode == ETR_MODE_ETR_SG) &&
+ WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
+ return -EINVAL;
+
+ if (WARN_ON(drvdata->etr_buf))
+ return -EBUSY;
+
+ /* Set the buffer for the session */
+ drvdata->etr_buf = etr_buf;
+ /*
+* If this ETR is connected to a CATU, enable it before we turn
+* this on.
+*/
+ tmc_etr_enable_catu(drvdata);
+
+ __tmc_etr_enable_hw(drvdata);
+ return 0;
+}
+
/*
* Return the available trace data in the buffer (starts at etr_buf->offset,
* limited by etr_buf->len) from @pos, with a maximum limit of @len,
@@ -1037,7 +1049,7 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata
*drvdata)
}
}
-static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -1053,6 +1065,11 @@ static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata)
CS_LOCK(drvdata->base);
+}
+
+static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etr_disable_hw(drvdata);
/* Disable CATU device if this ETR is connected to one */
tmc_etr_disable_catu(drvdata);
/* Reset the ETR buf used by hardware */
@@ -,8 +1128,9 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
drvdata->sysfs_buf = new_buf;
}
- drvdata->mode = CS_MODE_SYSFS;
- tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -1342,8 +1360,9 @@ static int tmc_enable_etr_sink_perf(struct
coresight_device *csdev, void *data)
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
drvdata->perf_data = etr_perf;
- drvdata->mode = CS_MODE_PERF;
- tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ if (!rc)
+ drvdata->mode = CS_MODE_PERF;
unlock_out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -1425,7 +1444,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
/* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
-
[PATCH 29/44] coresight: tmc-etr: Refactor for handling errors
From: Suzuki K Poulose
Refactor the tmc-etr enable operation to make it easier to
handle errors in enabling the hardware. We need to make
sure that the buffer is compatible with the ETR. This
patch re-arranges to make the error handling easier, by
deferring the hardware enablement until all the errors
are checked. This also avoids turning the CATU on/off
during a sysfs read session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 67 -
1 file changed, 43 insertions(+), 24 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 56fea4ff947e..c42693542ec8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -918,21 +918,10 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
-static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
- struct etr_buf *etr_buf)
+static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
{
u32 axictl, sts;
-
- /* Callers should provide an appropriate buffer for use */
- if (WARN_ON(!etr_buf || drvdata->etr_buf))
- return;
- drvdata->etr_buf = etr_buf;
-
- /*
-* If this ETR is connected to a CATU, enable it before we turn
-* this on
-*/
- tmc_etr_enable_catu(drvdata);
+ struct etr_buf *etr_buf = drvdata->etr_buf;
CS_UNLOCK(drvdata->base);
@@ -952,11 +941,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
axictl |= TMC_AXICTL_ARCACHE_OS;
}
- if (etr_buf->mode == ETR_MODE_ETR_SG) {
- if (WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
- return;
+ if (etr_buf->mode == ETR_MODE_ETR_SG)
axictl |= TMC_AXICTL_SCT_GAT_MODE;
- }
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, etr_buf->hwaddr);
@@ -982,6 +968,32 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
CS_LOCK(drvdata->base);
}
+static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
+struct etr_buf *etr_buf)
+{
+ /* Callers should provide an appropriate buffer for use */
+ if (WARN_ON(!etr_buf))
+ return -EINVAL;
+
+ if ((etr_buf->mode == ETR_MODE_ETR_SG) &&
+ WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
+ return -EINVAL;
+
+ if (WARN_ON(drvdata->etr_buf))
+ return -EBUSY;
+
+ /* Set the buffer for the session */
+ drvdata->etr_buf = etr_buf;
+ /*
+* If this ETR is connected to a CATU, enable it before we turn
+* this on.
+*/
+ tmc_etr_enable_catu(drvdata);
+
+ __tmc_etr_enable_hw(drvdata);
+ return 0;
+}
+
/*
* Return the available trace data in the buffer (starts at etr_buf->offset,
* limited by etr_buf->len) from @pos, with a maximum limit of @len,
@@ -1037,7 +1049,7 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata
*drvdata)
}
}
-static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -1053,6 +1065,11 @@ static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata)
CS_LOCK(drvdata->base);
+}
+
+static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+{
+ __tmc_etr_disable_hw(drvdata);
/* Disable CATU device if this ETR is connected to one */
tmc_etr_disable_catu(drvdata);
/* Reset the ETR buf used by hardware */
@@ -,8 +1128,9 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
drvdata->sysfs_buf = new_buf;
}
- drvdata->mode = CS_MODE_SYSFS;
- tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
+ if (!ret)
+ drvdata->mode = CS_MODE_SYSFS;
out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -1342,8 +1360,9 @@ static int tmc_enable_etr_sink_perf(struct
coresight_device *csdev, void *data)
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
drvdata->perf_data = etr_perf;
- drvdata->mode = CS_MODE_PERF;
- tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
+ if (!rc)
+ drvdata->mode = CS_MODE_PERF;
unlock_out:
spin_unlock_irqrestore(>spinlock, flags);
@@ -1425,7 +1444,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
/* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
-
[PATCH 28/44] coresight: Handle failures in enabling a trace path
From: Suzuki K Poulose
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index e73ca6af4765..f4f50753cf75 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -187,8 +187,10 @@ static int coresight_enable_link(struct coresight_device
*csdev,
if (atomic_inc_return(>refcnt[refport]) == 1) {
if (link_ops(csdev)->enable) {
ret = link_ops(csdev)->enable(csdev, inport, outport);
- if (ret)
+ if (ret) {
+ atomic_dec(>refcnt[refport]);
return ret;
+ }
}
}
@@ -277,13 +279,21 @@ static bool coresight_disable_source(struct
coresight_device *csdev)
return !csdev->enable;
}
-void coresight_disable_path(struct list_head *path)
+/*
+ * coresight_disable_path_from : Disable components in the given path beyond
+ * @nd in the list. If @nd is NULL, all the components, except the SOURCE are
+ * disabled.
+ */
+static void coresight_disable_path_from(struct list_head *path,
+ struct coresight_node *nd)
{
u32 type;
- struct coresight_node *nd;
struct coresight_device *csdev, *parent, *child;
- list_for_each_entry(nd, path, link) {
+ if (!nd)
+ nd = list_first_entry(path, struct coresight_node, link);
+
+ list_for_each_entry_continue(nd, path, link) {
csdev = nd->csdev;
type = csdev->type;
@@ -303,7 +313,12 @@ void coresight_disable_path(struct list_head *path)
coresight_disable_sink(csdev);
break;
case CORESIGHT_DEV_TYPE_SOURCE:
- /* sources are disabled from either sysFS or Perf */
+ /*
+* We skip the first node in the path assuming that it
+* is the source. So we don't expect a source device in
+* the middle of a path.
+*/
+ WARN_ON(1);
break;
case CORESIGHT_DEV_TYPE_LINK:
parent = list_prev_entry(nd, link)->csdev;
@@ -316,6 +331,11 @@ void coresight_disable_path(struct list_head *path)
}
}
+void coresight_disable_path(struct list_head *path)
+{
+ coresight_disable_path_from(path, NULL);
+}
+
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
{
@@ -369,7 +389,7 @@ int coresight_enable_path(struct list_head *path, u32 mode,
void *sink_data)
out:
return ret;
err:
- coresight_disable_path(path);
+ coresight_disable_path_from(path, nd);
goto out;
}
--
2.7.4
[PATCH 26/44] coresight: tmc: Refactor loops in etb dump
From: Leo Yan
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second
level loop is to iterate index in the range [0 .. drvdata->memwidth);
but the index isn't really used in the code, thus the second level
loop is useless.
This patch is to remove the second level loop; the refactor also reduces
indentation and we can use 'break' to replace 'goto' tag.
Cc: Mathieu Poirier
Signed-off-by: Leo Yan
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 4156c95ce1bb..4bf3bfd7c078 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -38,23 +38,20 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
char *bufp;
u32 read_data, lost;
- int i;
/* Check if the buffer wrapped around. */
lost = readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL;
bufp = drvdata->buf;
drvdata->len = 0;
while (1) {
- for (i = 0; i < drvdata->memwidth; i++) {
- read_data = readl_relaxed(drvdata->base + TMC_RRD);
- if (read_data == 0x)
- goto done;
- memcpy(bufp, _data, 4);
- bufp += 4;
- drvdata->len += 4;
- }
+ read_data = readl_relaxed(drvdata->base + TMC_RRD);
+ if (read_data == 0x)
+ break;
+ memcpy(bufp, _data, 4);
+ bufp += 4;
+ drvdata->len += 4;
}
-done:
+
if (lost)
coresight_insert_barrier_packet(drvdata->buf);
return;
--
2.7.4
[PATCH 25/44] coresight: etm4x: Configure EL2 exception level when kernel is running in HYP
From: Tomasz Nowicki
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever
hypervisor code should be executed. In this case ETM4x driver must
restrict configuration to EL1 when it setups kernel tracing.
However, there is no separate hypervisor privilege level when VHE
is enabled, the host kernel runs at EL2.
This patch fixes configuration of TRCACATRn register for VHE systems
so that ETM_EXLEVEL_NS_HYP bit is used instead of ETM_EXLEVEL_NS_OS
to on/off kernel tracing. At the same time, it moves common code
to new helper.
Signed-off-by: Tomasz Nowicki
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm4x.c | 40 +--
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index c1dcc7c289a5..b7379e9cfb30 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "coresight-etm4x.h"
#include "coresight-etm-perf.h"
@@ -605,7 +606,7 @@ static void etm4_set_default_config(struct etmv4_config
*config)
config->vinst_ctrl |= BIT(0);
}
-static u64 etm4_get_access_type(struct etmv4_config *config)
+static u64 etm4_get_ns_access_type(struct etmv4_config *config)
{
u64 access_type = 0;
@@ -616,17 +617,26 @@ static u64 etm4_get_access_type(struct etmv4_config
*config)
* Bit[13] Exception level 1 - OS
* Bit[14] Exception level 2 - Hypervisor
* Bit[15] Never implemented
-*
-* Always stay away from hypervisor mode.
*/
- access_type = ETM_EXLEVEL_NS_HYP;
-
- if (config->mode & ETM_MODE_EXCL_KERN)
- access_type |= ETM_EXLEVEL_NS_OS;
+ if (!is_kernel_in_hyp_mode()) {
+ /* Stay away from hypervisor mode for non-VHE */
+ access_type = ETM_EXLEVEL_NS_HYP;
+ if (config->mode & ETM_MODE_EXCL_KERN)
+ access_type |= ETM_EXLEVEL_NS_OS;
+ } else if (config->mode & ETM_MODE_EXCL_KERN) {
+ access_type = ETM_EXLEVEL_NS_HYP;
+ }
if (config->mode & ETM_MODE_EXCL_USER)
access_type |= ETM_EXLEVEL_NS_APP;
+ return access_type;
+}
+
+static u64 etm4_get_access_type(struct etmv4_config *config)
+{
+ u64 access_type = etm4_get_ns_access_type(config);
+
/*
* EXLEVEL_S, bits[11:8], don't trace anything happening
* in secure state.
@@ -880,20 +890,10 @@ void etm4_config_trace_mode(struct etmv4_config *config)
addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
/* clear default config */
- addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
+ addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
+ ETM_EXLEVEL_NS_HYP);
- /*
-* EXLEVEL_NS, bits[15:12]
-* The Exception levels are:
-* Bit[12] Exception level 0 - Application
-* Bit[13] Exception level 1 - OS
-* Bit[14] Exception level 2 - Hypervisor
-* Bit[15] Never implemented
-*/
- if (mode & ETM_MODE_EXCL_KERN)
- addr_acc |= ETM_EXLEVEL_NS_OS;
- else
- addr_acc |= ETM_EXLEVEL_NS_APP;
+ addr_acc |= etm4_get_ns_access_type(config);
config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
--
2.7.4
[PATCH 28/44] coresight: Handle failures in enabling a trace path
From: Suzuki K Poulose
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index e73ca6af4765..f4f50753cf75 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -187,8 +187,10 @@ static int coresight_enable_link(struct coresight_device
*csdev,
if (atomic_inc_return(>refcnt[refport]) == 1) {
if (link_ops(csdev)->enable) {
ret = link_ops(csdev)->enable(csdev, inport, outport);
- if (ret)
+ if (ret) {
+ atomic_dec(>refcnt[refport]);
return ret;
+ }
}
}
@@ -277,13 +279,21 @@ static bool coresight_disable_source(struct
coresight_device *csdev)
return !csdev->enable;
}
-void coresight_disable_path(struct list_head *path)
+/*
+ * coresight_disable_path_from : Disable components in the given path beyond
+ * @nd in the list. If @nd is NULL, all the components, except the SOURCE are
+ * disabled.
+ */
+static void coresight_disable_path_from(struct list_head *path,
+ struct coresight_node *nd)
{
u32 type;
- struct coresight_node *nd;
struct coresight_device *csdev, *parent, *child;
- list_for_each_entry(nd, path, link) {
+ if (!nd)
+ nd = list_first_entry(path, struct coresight_node, link);
+
+ list_for_each_entry_continue(nd, path, link) {
csdev = nd->csdev;
type = csdev->type;
@@ -303,7 +313,12 @@ void coresight_disable_path(struct list_head *path)
coresight_disable_sink(csdev);
break;
case CORESIGHT_DEV_TYPE_SOURCE:
- /* sources are disabled from either sysFS or Perf */
+ /*
+* We skip the first node in the path assuming that it
+* is the source. So we don't expect a source device in
+* the middle of a path.
+*/
+ WARN_ON(1);
break;
case CORESIGHT_DEV_TYPE_LINK:
parent = list_prev_entry(nd, link)->csdev;
@@ -316,6 +331,11 @@ void coresight_disable_path(struct list_head *path)
}
}
+void coresight_disable_path(struct list_head *path)
+{
+ coresight_disable_path_from(path, NULL);
+}
+
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
{
@@ -369,7 +389,7 @@ int coresight_enable_path(struct list_head *path, u32 mode,
void *sink_data)
out:
return ret;
err:
- coresight_disable_path(path);
+ coresight_disable_path_from(path, nd);
goto out;
}
--
2.7.4
[PATCH 26/44] coresight: tmc: Refactor loops in etb dump
From: Leo Yan
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second
level loop is to iterate index in the range [0 .. drvdata->memwidth);
but the index isn't really used in the code, thus the second level
loop is useless.
This patch is to remove the second level loop; the refactor also reduces
indentation and we can use 'break' to replace 'goto' tag.
Cc: Mathieu Poirier
Signed-off-by: Leo Yan
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 4156c95ce1bb..4bf3bfd7c078 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -38,23 +38,20 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
char *bufp;
u32 read_data, lost;
- int i;
/* Check if the buffer wrapped around. */
lost = readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL;
bufp = drvdata->buf;
drvdata->len = 0;
while (1) {
- for (i = 0; i < drvdata->memwidth; i++) {
- read_data = readl_relaxed(drvdata->base + TMC_RRD);
- if (read_data == 0x)
- goto done;
- memcpy(bufp, _data, 4);
- bufp += 4;
- drvdata->len += 4;
- }
+ read_data = readl_relaxed(drvdata->base + TMC_RRD);
+ if (read_data == 0x)
+ break;
+ memcpy(bufp, _data, 4);
+ bufp += 4;
+ drvdata->len += 4;
}
-done:
+
if (lost)
coresight_insert_barrier_packet(drvdata->buf);
return;
--
2.7.4
[PATCH 25/44] coresight: etm4x: Configure EL2 exception level when kernel is running in HYP
From: Tomasz Nowicki
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever
hypervisor code should be executed. In this case ETM4x driver must
restrict configuration to EL1 when it setups kernel tracing.
However, there is no separate hypervisor privilege level when VHE
is enabled, the host kernel runs at EL2.
This patch fixes configuration of TRCACATRn register for VHE systems
so that ETM_EXLEVEL_NS_HYP bit is used instead of ETM_EXLEVEL_NS_OS
to on/off kernel tracing. At the same time, it moves common code
to new helper.
Signed-off-by: Tomasz Nowicki
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm4x.c | 40 +--
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index c1dcc7c289a5..b7379e9cfb30 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "coresight-etm4x.h"
#include "coresight-etm-perf.h"
@@ -605,7 +606,7 @@ static void etm4_set_default_config(struct etmv4_config
*config)
config->vinst_ctrl |= BIT(0);
}
-static u64 etm4_get_access_type(struct etmv4_config *config)
+static u64 etm4_get_ns_access_type(struct etmv4_config *config)
{
u64 access_type = 0;
@@ -616,17 +617,26 @@ static u64 etm4_get_access_type(struct etmv4_config
*config)
* Bit[13] Exception level 1 - OS
* Bit[14] Exception level 2 - Hypervisor
* Bit[15] Never implemented
-*
-* Always stay away from hypervisor mode.
*/
- access_type = ETM_EXLEVEL_NS_HYP;
-
- if (config->mode & ETM_MODE_EXCL_KERN)
- access_type |= ETM_EXLEVEL_NS_OS;
+ if (!is_kernel_in_hyp_mode()) {
+ /* Stay away from hypervisor mode for non-VHE */
+ access_type = ETM_EXLEVEL_NS_HYP;
+ if (config->mode & ETM_MODE_EXCL_KERN)
+ access_type |= ETM_EXLEVEL_NS_OS;
+ } else if (config->mode & ETM_MODE_EXCL_KERN) {
+ access_type = ETM_EXLEVEL_NS_HYP;
+ }
if (config->mode & ETM_MODE_EXCL_USER)
access_type |= ETM_EXLEVEL_NS_APP;
+ return access_type;
+}
+
+static u64 etm4_get_access_type(struct etmv4_config *config)
+{
+ u64 access_type = etm4_get_ns_access_type(config);
+
/*
* EXLEVEL_S, bits[11:8], don't trace anything happening
* in secure state.
@@ -880,20 +890,10 @@ void etm4_config_trace_mode(struct etmv4_config *config)
addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
/* clear default config */
- addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
+ addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
+ ETM_EXLEVEL_NS_HYP);
- /*
-* EXLEVEL_NS, bits[15:12]
-* The Exception levels are:
-* Bit[12] Exception level 0 - Application
-* Bit[13] Exception level 1 - OS
-* Bit[14] Exception level 2 - Hypervisor
-* Bit[15] Never implemented
-*/
- if (mode & ETM_MODE_EXCL_KERN)
- addr_acc |= ETM_EXLEVEL_NS_OS;
- else
- addr_acc |= ETM_EXLEVEL_NS_APP;
+ addr_acc |= etm4_get_ns_access_type(config);
config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
--
2.7.4
[PATCH 22/44] coresight: etm-perf: Add support for ETR backend
From: Suzuki K Poulose
Add support for using TMC-ETR as backend for ETM perf tracing.
We use software double buffering at the moment. i.e, the TMC-ETR
uses a separate buffer than the perf ring buffer. The data is
copied to the perf ring buffer once a session completes.
The TMC-ETR would try to match the larger of perf ring buffer
or the ETR buffer size configured via sysfs, scaling down to
a minimum limit of 1MB.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 248 +++-
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 248 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 1aedfc3629c0..56fea4ff947e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -10,6 +10,7 @@
#include
#include
#include "coresight-catu.h"
+#include "coresight-etm-perf.h"
#include "coresight-priv.h"
#include "coresight-tmc.h"
@@ -21,6 +22,28 @@ struct etr_flat_buf {
};
/*
+ * etr_perf_buffer - Perf buffer used for ETR
+ * @etr_buf- Actual buffer used by the ETR
+ * @snaphost - Perf session mode
+ * @head - handle->head at the beginning of the session.
+ * @nr_pages - Number of pages in the ring buffer.
+ * @pages - Array of Pages in the ring buffer.
+ */
+struct etr_perf_buffer {
+ struct etr_buf *etr_buf;
+ boolsnapshot;
+ unsigned long head;
+ int nr_pages;
+ void**pages;
+};
+
+/* Convert the perf index to an offset within the ETR buffer */
+#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
+
+/* Lower limit for ETR hardware buffer */
+#define TMC_ETR_PERF_MIN_BUF_SIZE SZ_1M
+
+/*
* The TMC ETR SG has a page size of 4K. The SG table contains pointers
* to 4KB buffers. However, the OS may use a PAGE_SIZE different from
* 4K (i.e, 16KB or 64KB). This implies that a single OS page could
@@ -1103,10 +1126,228 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
return ret;
}
+/*
+ * tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf.
+ * The size of the hardware buffer is dependent on the size configured
+ * via sysfs and the perf ring buffer size. We prefer to allocate the
+ * largest possible size, scaling down the size by half until it
+ * reaches a minimum limit (1M), beyond which we give up.
+ */
+static struct etr_perf_buffer *
+tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages,
+ void **pages, bool snapshot)
+{
+ struct etr_buf *etr_buf;
+ struct etr_perf_buffer *etr_perf;
+ unsigned long size;
+
+ etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node);
+ if (!etr_perf)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+* Try to match the perf ring buffer size if it is larger
+* than the size requested via sysfs.
+*/
+ if ((nr_pages << PAGE_SHIFT) > drvdata->size) {
+ etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT),
+ 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ }
+
+ /*
+* Else switch to configured size for this ETR
+* and scale down until we hit the minimum limit.
+*/
+ size = drvdata->size;
+ do {
+ etr_buf = tmc_alloc_etr_buf(drvdata, size, 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ size /= 2;
+ } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE);
+
+ kfree(etr_perf);
+ return ERR_PTR(-ENOMEM);
+
+done:
+ etr_perf->etr_buf = etr_buf;
+ return etr_perf;
+}
+
+
+static void *tmc_alloc_etr_buffer(struct coresight_device *csdev,
+ int cpu, void **pages, int nr_pages,
+ bool snapshot)
+{
+ struct etr_perf_buffer *etr_perf;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+
+ etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu),
+ nr_pages, pages, snapshot);
+ if (IS_ERR(etr_perf)) {
+ dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n");
+ return NULL;
+ }
+
+ etr_perf->snapshot = snapshot;
+ etr_perf->nr_pages = nr_pages;
+ etr_perf->pages = pages;
+
+ return etr_perf;
+}
+
+static void tmc_free_etr_buffer(void *config)
+{
+ struct etr_perf_buffer *etr_perf = config;
+
+ if (etr_perf->etr_buf)
+
[PATCH 17/44] coresight: tmc-etr: Relax collection of trace from sysfs mode
From: Suzuki K Poulose
Since the ETR now uses mode specific buffers, we can reliably
provide the trace data captured in sysfs mode, even when the ETR
is operating in PERF mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2d6f428176ff..bafd73e71c4c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1168,19 +1168,17 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
goto out;
}
- /* Don't interfere if operated from Perf */
- if (drvdata->mode == CS_MODE_PERF) {
- ret = -EINVAL;
- goto out;
- }
-
- /* If sysfs_buf is NULL the trace data has been read already */
+ /*
+* We can safely allow reads even if the ETR is operating in PERF mode,
+* since the sysfs session is captured in mode specific data.
+* If drvdata::sysfs_data is NULL the trace data has been read already.
+*/
if (!drvdata->sysfs_buf) {
ret = -EINVAL;
goto out;
}
- /* Disable the TMC if we are trying to read from a running session */
+ /* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
tmc_etr_disable_hw(drvdata);
--
2.7.4
[PATCH 15/44] coresight: perf: Disable trace path upon source error
From: Suzuki K Poulose We enable the trace path, before activating the source. If we fail to enable the source, we must disable the path to make sure it is available for another session. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index afe7e7fc1a93..6db76ce6ba5f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -317,11 +317,13 @@ static void etm_event_start(struct perf_event *event, int flags) /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) - goto fail_end_stop; + goto fail_disable_path; out: return; +fail_disable_path: + coresight_disable_path(path); fail_end_stop: perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); perf_aux_output_end(handle, 0); -- 2.7.4
[PATCH 19/44] coresight: perf: Remove reset_buffer call back for sinks
From: Suzuki K Poulose
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make sure the ring buffer
is updated with the trace data. And we store information about the
size of the data collected only to be consumed by the reset_buffer
callback which always follows the update_buffer. This was originally
designed for handling future IPs which could trigger a buffer overflow
interrupt. This patch gets rid of the reset_buffer callback altogether
and performs the actions in update_buffer, making it return the size
collected. We can always add the support for handling the overflow
interrupt case later.
This removes some not-so pretty hack (storing the new head in the
size field for snapshot mode) and cleans it up a little bit.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c| 56 +--
drivers/hwtracing/coresight/coresight-etm-perf.c | 9 +---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 58 +---
include/linux/coresight.h| 6 +--
4 files changed, 26 insertions(+), 103 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 3d4b6df32a06..dba75c905e57 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -319,37 +319,7 @@ static int etb_set_buffer(struct coresight_device *csdev,
return ret;
}
-static unsigned long etb_reset_buffer(struct coresight_device *csdev,
- struct perf_output_handle *handle,
- void *sink_config)
-{
- unsigned long size = 0;
- struct cs_buffers *buf = sink_config;
-
- if (buf) {
- /*
-* In snapshot mode ->data_size holds the new address of the
-* ring buffer's head. The size itself is the whole address
-* range since we want the latest information.
-*/
- if (buf->snapshot)
- handle->head = local_xchg(>data_size,
- buf->nr_pages << PAGE_SHIFT);
-
- /*
-* Tell the tracer PMU how much we got in this run and if
-* something went wrong along the way. Nobody else can use
-* this cs_buffers instance until we are done. As such
-* resetting parameters here and squaring off with the ring
-* buffer API in the tracer PMU is fine.
-*/
- size = local_xchg(>data_size, 0);
- }
-
- return size;
-}
-
-static void etb_update_buffer(struct coresight_device *csdev,
+static unsigned long etb_update_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
@@ -358,13 +328,13 @@ static void etb_update_buffer(struct coresight_device
*csdev,
u8 *buf_ptr;
const u32 *barrier;
u32 read_ptr, write_ptr, capacity;
- u32 status, read_data, to_read;
- unsigned long offset;
+ u32 status, read_data;
+ unsigned long offset, to_read;
struct cs_buffers *buf = sink_config;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
if (!buf)
- return;
+ return 0;
capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
@@ -469,18 +439,17 @@ static void etb_update_buffer(struct coresight_device
*csdev,
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
/*
-* In snapshot mode all we have to do is communicate to
-* perf_aux_output_end() the address of the current head. In full
-* trace mode the same function expects a size to move rb->aux_head
-* forward.
+* In snapshot mode we have to update the handle->head to point
+* to the new location.
*/
- if (buf->snapshot)
- local_set(>data_size, (cur * PAGE_SIZE) + offset);
- else
- local_add(to_read, >data_size);
-
+ if (buf->snapshot) {
+ handle->head = (cur * PAGE_SIZE) + offset;
+ to_read = buf->nr_pages << PAGE_SHIFT;
+ }
etb_enable_hw(drvdata);
CS_LOCK(drvdata->base);
+
+ return to_read;
}
static const struct coresight_ops_sink etb_sink_ops = {
@@ -489,7 +458,6 @@ static const struct coresight_ops_sink etb_sink_ops = {
.alloc_buffer = etb_alloc_buffer,
.free_buffer= etb_free_buffer,
.set_buffer = etb_set_buffer,
- .reset_buffer = etb_reset_buffer,
.update_buffer = etb_update_buffer,
};
diff --git
[PATCH 20/44] coresight: perf: Add helper to retrieve sink configuration
From: Suzuki K Poulose
We can always find the sink configuration for a given perf_output_handle.
Add a helper to retrieve the sink configuration for a given
perf_output_handle. This will be used to get rid of the set_buffer()
call back.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 -
drivers/hwtracing/coresight/coresight-etm-perf.h | 26
2 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index ad87441f65d7..16b83d8b2ac2 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -23,20 +23,6 @@
static struct pmu etm_pmu;
static bool etm_perf_up;
-/**
- * struct etm_event_data - Coresight specifics associated to an event
- * @work: Handle to free allocated memory outside IRQ context.
- * @mask: Hold the CPU(s) this event was set for.
- * @snk_config:The sink configuration.
- * @path: An array of path, each slot for one CPU.
- */
-struct etm_event_data {
- struct work_struct work;
- cpumask_t mask;
- void *snk_config;
- struct list_head * __percpu *path;
-};
-
static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index 4197df4faf5e..da7d9336a15c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -7,6 +7,7 @@
#ifndef _CORESIGHT_ETM_PERF_H
#define _CORESIGHT_ETM_PERF_H
+#include
#include "coresight-priv.h"
struct coresight_device;
@@ -42,14 +43,39 @@ struct etm_filters {
boolssstatus;
};
+/**
+ * struct etm_event_data - Coresight specifics associated to an event
+ * @work: Handle to free allocated memory outside IRQ context.
+ * @mask: Hold the CPU(s) this event was set for.
+ * @snk_config:The sink configuration.
+ * @path: An array of path, each slot for one CPU.
+ */
+struct etm_event_data {
+ struct work_struct work;
+ cpumask_t mask;
+ void *snk_config;
+ struct list_head * __percpu *path;
+};
#ifdef CONFIG_CORESIGHT
int etm_perf_symlink(struct coresight_device *csdev, bool link);
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ struct etm_event_data *data = perf_get_aux(handle);
+ if (data)
+ return data->snk_config;
+ return NULL;
+}
#else
static inline int etm_perf_symlink(struct coresight_device *csdev, bool link)
{ return -EINVAL; }
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ return NULL;
+}
+
#endif /* CONFIG_CORESIGHT */
#endif
--
2.7.4
[PATCH 22/44] coresight: etm-perf: Add support for ETR backend
From: Suzuki K Poulose
Add support for using TMC-ETR as backend for ETM perf tracing.
We use software double buffering at the moment. i.e, the TMC-ETR
uses a separate buffer than the perf ring buffer. The data is
copied to the perf ring buffer once a session completes.
The TMC-ETR would try to match the larger of perf ring buffer
or the ETR buffer size configured via sysfs, scaling down to
a minimum limit of 1MB.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 248 +++-
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 248 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 1aedfc3629c0..56fea4ff947e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -10,6 +10,7 @@
#include
#include
#include "coresight-catu.h"
+#include "coresight-etm-perf.h"
#include "coresight-priv.h"
#include "coresight-tmc.h"
@@ -21,6 +22,28 @@ struct etr_flat_buf {
};
/*
+ * etr_perf_buffer - Perf buffer used for ETR
+ * @etr_buf- Actual buffer used by the ETR
+ * @snaphost - Perf session mode
+ * @head - handle->head at the beginning of the session.
+ * @nr_pages - Number of pages in the ring buffer.
+ * @pages - Array of Pages in the ring buffer.
+ */
+struct etr_perf_buffer {
+ struct etr_buf *etr_buf;
+ boolsnapshot;
+ unsigned long head;
+ int nr_pages;
+ void**pages;
+};
+
+/* Convert the perf index to an offset within the ETR buffer */
+#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
+
+/* Lower limit for ETR hardware buffer */
+#define TMC_ETR_PERF_MIN_BUF_SIZE SZ_1M
+
+/*
* The TMC ETR SG has a page size of 4K. The SG table contains pointers
* to 4KB buffers. However, the OS may use a PAGE_SIZE different from
* 4K (i.e, 16KB or 64KB). This implies that a single OS page could
@@ -1103,10 +1126,228 @@ static int tmc_enable_etr_sink_sysfs(struct
coresight_device *csdev)
return ret;
}
+/*
+ * tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf.
+ * The size of the hardware buffer is dependent on the size configured
+ * via sysfs and the perf ring buffer size. We prefer to allocate the
+ * largest possible size, scaling down the size by half until it
+ * reaches a minimum limit (1M), beyond which we give up.
+ */
+static struct etr_perf_buffer *
+tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages,
+ void **pages, bool snapshot)
+{
+ struct etr_buf *etr_buf;
+ struct etr_perf_buffer *etr_perf;
+ unsigned long size;
+
+ etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node);
+ if (!etr_perf)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+* Try to match the perf ring buffer size if it is larger
+* than the size requested via sysfs.
+*/
+ if ((nr_pages << PAGE_SHIFT) > drvdata->size) {
+ etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT),
+ 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ }
+
+ /*
+* Else switch to configured size for this ETR
+* and scale down until we hit the minimum limit.
+*/
+ size = drvdata->size;
+ do {
+ etr_buf = tmc_alloc_etr_buf(drvdata, size, 0, node, NULL);
+ if (!IS_ERR(etr_buf))
+ goto done;
+ size /= 2;
+ } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE);
+
+ kfree(etr_perf);
+ return ERR_PTR(-ENOMEM);
+
+done:
+ etr_perf->etr_buf = etr_buf;
+ return etr_perf;
+}
+
+
+static void *tmc_alloc_etr_buffer(struct coresight_device *csdev,
+ int cpu, void **pages, int nr_pages,
+ bool snapshot)
+{
+ struct etr_perf_buffer *etr_perf;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+
+ etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu),
+ nr_pages, pages, snapshot);
+ if (IS_ERR(etr_perf)) {
+ dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n");
+ return NULL;
+ }
+
+ etr_perf->snapshot = snapshot;
+ etr_perf->nr_pages = nr_pages;
+ etr_perf->pages = pages;
+
+ return etr_perf;
+}
+
+static void tmc_free_etr_buffer(void *config)
+{
+ struct etr_perf_buffer *etr_perf = config;
+
+ if (etr_perf->etr_buf)
+
[PATCH 17/44] coresight: tmc-etr: Relax collection of trace from sysfs mode
From: Suzuki K Poulose
Since the ETR now uses mode specific buffers, we can reliably
provide the trace data captured in sysfs mode, even when the ETR
is operating in PERF mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2d6f428176ff..bafd73e71c4c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1168,19 +1168,17 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
goto out;
}
- /* Don't interfere if operated from Perf */
- if (drvdata->mode == CS_MODE_PERF) {
- ret = -EINVAL;
- goto out;
- }
-
- /* If sysfs_buf is NULL the trace data has been read already */
+ /*
+* We can safely allow reads even if the ETR is operating in PERF mode,
+* since the sysfs session is captured in mode specific data.
+* If drvdata::sysfs_data is NULL the trace data has been read already.
+*/
if (!drvdata->sysfs_buf) {
ret = -EINVAL;
goto out;
}
- /* Disable the TMC if we are trying to read from a running session */
+ /* Disable the TMC if we are trying to read from a running session. */
if (drvdata->mode == CS_MODE_SYSFS)
tmc_etr_disable_hw(drvdata);
--
2.7.4
[PATCH 15/44] coresight: perf: Disable trace path upon source error
From: Suzuki K Poulose We enable the trace path, before activating the source. If we fail to enable the source, we must disable the path to make sure it is available for another session. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index afe7e7fc1a93..6db76ce6ba5f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -317,11 +317,13 @@ static void etm_event_start(struct perf_event *event, int flags) /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) - goto fail_end_stop; + goto fail_disable_path; out: return; +fail_disable_path: + coresight_disable_path(path); fail_end_stop: perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); perf_aux_output_end(handle, 0); -- 2.7.4
[PATCH 19/44] coresight: perf: Remove reset_buffer call back for sinks
From: Suzuki K Poulose
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make sure the ring buffer
is updated with the trace data. And we store information about the
size of the data collected only to be consumed by the reset_buffer
callback which always follows the update_buffer. This was originally
designed for handling future IPs which could trigger a buffer overflow
interrupt. This patch gets rid of the reset_buffer callback altogether
and performs the actions in update_buffer, making it return the size
collected. We can always add the support for handling the overflow
interrupt case later.
This removes some not-so pretty hack (storing the new head in the
size field for snapshot mode) and cleans it up a little bit.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c| 56 +--
drivers/hwtracing/coresight/coresight-etm-perf.c | 9 +---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 58 +---
include/linux/coresight.h| 6 +--
4 files changed, 26 insertions(+), 103 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c
b/drivers/hwtracing/coresight/coresight-etb10.c
index 3d4b6df32a06..dba75c905e57 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -319,37 +319,7 @@ static int etb_set_buffer(struct coresight_device *csdev,
return ret;
}
-static unsigned long etb_reset_buffer(struct coresight_device *csdev,
- struct perf_output_handle *handle,
- void *sink_config)
-{
- unsigned long size = 0;
- struct cs_buffers *buf = sink_config;
-
- if (buf) {
- /*
-* In snapshot mode ->data_size holds the new address of the
-* ring buffer's head. The size itself is the whole address
-* range since we want the latest information.
-*/
- if (buf->snapshot)
- handle->head = local_xchg(>data_size,
- buf->nr_pages << PAGE_SHIFT);
-
- /*
-* Tell the tracer PMU how much we got in this run and if
-* something went wrong along the way. Nobody else can use
-* this cs_buffers instance until we are done. As such
-* resetting parameters here and squaring off with the ring
-* buffer API in the tracer PMU is fine.
-*/
- size = local_xchg(>data_size, 0);
- }
-
- return size;
-}
-
-static void etb_update_buffer(struct coresight_device *csdev,
+static unsigned long etb_update_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
@@ -358,13 +328,13 @@ static void etb_update_buffer(struct coresight_device
*csdev,
u8 *buf_ptr;
const u32 *barrier;
u32 read_ptr, write_ptr, capacity;
- u32 status, read_data, to_read;
- unsigned long offset;
+ u32 status, read_data;
+ unsigned long offset, to_read;
struct cs_buffers *buf = sink_config;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
if (!buf)
- return;
+ return 0;
capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
@@ -469,18 +439,17 @@ static void etb_update_buffer(struct coresight_device
*csdev,
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
/*
-* In snapshot mode all we have to do is communicate to
-* perf_aux_output_end() the address of the current head. In full
-* trace mode the same function expects a size to move rb->aux_head
-* forward.
+* In snapshot mode we have to update the handle->head to point
+* to the new location.
*/
- if (buf->snapshot)
- local_set(>data_size, (cur * PAGE_SIZE) + offset);
- else
- local_add(to_read, >data_size);
-
+ if (buf->snapshot) {
+ handle->head = (cur * PAGE_SIZE) + offset;
+ to_read = buf->nr_pages << PAGE_SHIFT;
+ }
etb_enable_hw(drvdata);
CS_LOCK(drvdata->base);
+
+ return to_read;
}
static const struct coresight_ops_sink etb_sink_ops = {
@@ -489,7 +458,6 @@ static const struct coresight_ops_sink etb_sink_ops = {
.alloc_buffer = etb_alloc_buffer,
.free_buffer= etb_free_buffer,
.set_buffer = etb_set_buffer,
- .reset_buffer = etb_reset_buffer,
.update_buffer = etb_update_buffer,
};
diff --git
[PATCH 20/44] coresight: perf: Add helper to retrieve sink configuration
From: Suzuki K Poulose
We can always find the sink configuration for a given perf_output_handle.
Add a helper to retrieve the sink configuration for a given
perf_output_handle. This will be used to get rid of the set_buffer()
call back.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 -
drivers/hwtracing/coresight/coresight-etm-perf.h | 26
2 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index ad87441f65d7..16b83d8b2ac2 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -23,20 +23,6 @@
static struct pmu etm_pmu;
static bool etm_perf_up;
-/**
- * struct etm_event_data - Coresight specifics associated to an event
- * @work: Handle to free allocated memory outside IRQ context.
- * @mask: Hold the CPU(s) this event was set for.
- * @snk_config:The sink configuration.
- * @path: An array of path, each slot for one CPU.
- */
-struct etm_event_data {
- struct work_struct work;
- cpumask_t mask;
- void *snk_config;
- struct list_head * __percpu *path;
-};
-
static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index 4197df4faf5e..da7d9336a15c 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -7,6 +7,7 @@
#ifndef _CORESIGHT_ETM_PERF_H
#define _CORESIGHT_ETM_PERF_H
+#include
#include "coresight-priv.h"
struct coresight_device;
@@ -42,14 +43,39 @@ struct etm_filters {
boolssstatus;
};
+/**
+ * struct etm_event_data - Coresight specifics associated to an event
+ * @work: Handle to free allocated memory outside IRQ context.
+ * @mask: Hold the CPU(s) this event was set for.
+ * @snk_config:The sink configuration.
+ * @path: An array of path, each slot for one CPU.
+ */
+struct etm_event_data {
+ struct work_struct work;
+ cpumask_t mask;
+ void *snk_config;
+ struct list_head * __percpu *path;
+};
#ifdef CONFIG_CORESIGHT
int etm_perf_symlink(struct coresight_device *csdev, bool link);
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ struct etm_event_data *data = perf_get_aux(handle);
+ if (data)
+ return data->snk_config;
+ return NULL;
+}
#else
static inline int etm_perf_symlink(struct coresight_device *csdev, bool link)
{ return -EINVAL; }
+static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
+{
+ return NULL;
+}
+
#endif /* CONFIG_CORESIGHT */
#endif
--
2.7.4
[PATCH 01/44] coresight: Document error handling in coresight_register
From: Suzuki K Poulose
commit 6403587a930c ("coresight: use put_device() instead of kfree()")
fixes the double freeing of resources and ensures that the device
refcount is dropped properly. Add a comment to explain this to
help the readers and prevent people trying to "unfix" it again.
While at it, rename the labels for better readability.
Cc: Mathieu Poirier
Cc: Arvind Yadav
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index 3e07fd335f8c..9fd0c387e678 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -1006,7 +1006,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
if (!csdev) {
ret = -ENOMEM;
- goto err_kzalloc_csdev;
+ goto err_out;
}
if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
@@ -1022,7 +1022,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts) {
ret = -ENOMEM;
- goto err_kzalloc_refcnts;
+ goto err_free_csdev;
}
csdev->refcnt = refcnts;
@@ -1035,7 +1035,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
conns = kcalloc(csdev->nr_outport, sizeof(*conns), GFP_KERNEL);
if (!conns) {
ret = -ENOMEM;
- goto err_kzalloc_conns;
+ goto err_free_refcnts;
}
for (i = 0; i < csdev->nr_outport; i++) {
@@ -1062,7 +1062,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
ret = device_register(>dev);
if (ret) {
put_device(>dev);
- goto err_kzalloc_csdev;
+ /*
+* All resources are free'd explicitly via
+* coresight_device_release(), triggered from put_device().
+*/
+ goto err_out;
}
mutex_lock(_mutex);
@@ -1074,11 +1078,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
return csdev;
-err_kzalloc_conns:
+err_free_refcnts:
kfree(refcnts);
-err_kzalloc_refcnts:
+err_free_csdev:
kfree(csdev);
-err_kzalloc_csdev:
+err_out:
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(coresight_register);
--
2.7.4
[PATCH 01/44] coresight: Document error handling in coresight_register
From: Suzuki K Poulose
commit 6403587a930c ("coresight: use put_device() instead of kfree()")
fixes the double freeing of resources and ensures that the device
refcount is dropped properly. Add a comment to explain this to
help the readers and prevent people trying to "unfix" it again.
While at it, rename the labels for better readability.
Cc: Mathieu Poirier
Cc: Arvind Yadav
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index 3e07fd335f8c..9fd0c387e678 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -1006,7 +1006,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
if (!csdev) {
ret = -ENOMEM;
- goto err_kzalloc_csdev;
+ goto err_out;
}
if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
@@ -1022,7 +1022,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts) {
ret = -ENOMEM;
- goto err_kzalloc_refcnts;
+ goto err_free_csdev;
}
csdev->refcnt = refcnts;
@@ -1035,7 +1035,7 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
conns = kcalloc(csdev->nr_outport, sizeof(*conns), GFP_KERNEL);
if (!conns) {
ret = -ENOMEM;
- goto err_kzalloc_conns;
+ goto err_free_refcnts;
}
for (i = 0; i < csdev->nr_outport; i++) {
@@ -1062,7 +1062,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
ret = device_register(>dev);
if (ret) {
put_device(>dev);
- goto err_kzalloc_csdev;
+ /*
+* All resources are free'd explicitly via
+* coresight_device_release(), triggered from put_device().
+*/
+ goto err_out;
}
mutex_lock(_mutex);
@@ -1074,11 +1078,11 @@ struct coresight_device *coresight_register(struct
coresight_desc *desc)
return csdev;
-err_kzalloc_conns:
+err_free_refcnts:
kfree(refcnts);
-err_kzalloc_refcnts:
+err_free_csdev:
kfree(csdev);
-err_kzalloc_csdev:
+err_out:
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(coresight_register);
--
2.7.4
[PATCH 3/9] phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/phy-brcm-sata.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c
b/drivers/phy/broadcom/phy-brcm-sata.c
index 8708ea3b4d6d..218735305d85 100644
--- a/drivers/phy/broadcom/phy-brcm-sata.c
+++ b/drivers/phy/broadcom/phy-brcm-sata.c
@@ -47,6 +47,7 @@ enum brcm_sata_phy_version {
BRCM_SATA_PHY_IPROC_NS2,
BRCM_SATA_PHY_IPROC_NSP,
BRCM_SATA_PHY_IPROC_SR,
+ BRCM_SATA_PHY_DSL_28NM,
};
enum brcm_sata_phy_rxaeq_mode {
@@ -96,7 +97,10 @@ enum sata_phy_regs {
PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
PLLCONTROL_0_FREQ_MONITOR = BIT(12),
PLLCONTROL_0_SEQ_START = BIT(15),
+ PLL_CAP_CHARGE_TIME = 0x83,
+ PLL_VCO_CAL_THRESH = 0x84,
PLL_CAP_CONTROL = 0x85,
+ PLL_FREQ_DET_TIME = 0x86,
PLL_ACTRL2 = 0x8b,
PLL_ACTRL2_SELDIV_MASK = 0x1f,
PLL_ACTRL2_SELDIV_SHIFT = 9,
@@ -106,6 +110,9 @@ enum sata_phy_regs {
PLL1_ACTRL2 = 0x82,
PLL1_ACTRL3 = 0x83,
PLL1_ACTRL4 = 0x84,
+ PLL1_ACTRL5 = 0x85,
+ PLL1_ACTRL6 = 0x86,
+ PLL1_ACTRL7 = 0x87,
TX_REG_BANK = 0x070,
TX_ACTRL0 = 0x80,
@@ -119,6 +126,8 @@ enum sata_phy_regs {
AEQ_FRC_EQ_FORCE= BIT(0),
AEQ_FRC_EQ_FORCE_VAL= BIT(1),
AEQRX_REG_BANK_1= 0xe0,
+ AEQRX_SLCAL0_CTRL0 = 0x82,
+ AEQRX_SLCAL1_CTRL0 = 0x86,
OOB_REG_BANK= 0x150,
OOB1_REG_BANK = 0x160,
@@ -168,6 +177,7 @@ static inline void __iomem *brcm_sata_pcb_base(struct
brcm_sata_port *port)
switch (priv->version) {
case BRCM_SATA_PHY_STB_28NM:
case BRCM_SATA_PHY_IPROC_NS2:
+ case BRCM_SATA_PHY_DSL_28NM:
size = SATA_PCB_REG_28NM_SPACE_SIZE;
break;
case BRCM_SATA_PHY_STB_40NM:
@@ -482,6 +492,61 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
return 0;
}
+static int brcm_dsl_sata_init(struct brcm_sata_port *port)
+{
+ void __iomem *base = brcm_sata_pcb_base(port);
+ struct device *dev = port->phy_priv->dev;
+ unsigned int try;
+ u32 tmp;
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3089);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3088);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+0, 0x3000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+0, 0x3000);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+ usleep_range(1000, 2000);
+
+ /* Acquire PLL lock */
+ try = 50;
+ while (try) {
+ tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+ BLOCK0_XGXSSTATUS);
+ if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
+ break;
+ msleep(20);
+ try--;
+ };
+
+ if (!try) {
+ /* PLL did not lock; give up */
+ dev_err(dev, "port%d PLL did not lock\n", port->portnum);
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "port%d initialized\n", port->portnum);
+
+ return 0;
+}
+
static int brcm_sata_phy_init(struct phy *phy)
{
int rc;
@@ -501,6 +566,9 @@ static int brcm_sata_phy_init(struct phy *phy)
case BRCM_SATA_PHY_IPROC_SR:
rc = brcm_sr_sata_init(port);
break;
+ case BRCM_SATA_PHY_DSL_28NM:
+ rc = brcm_dsl_sata_init(port);
+ break;
default:
rc =
[PATCH 00/44] coresight: next v4.19-rc4
Good day Greg, To start with here is the tally I gathered for inclusion in the 4.20 cycle - please consider at your convenience. As usual everything applies cleanly on your char-misc-next branch (f685fc6ab051). Second, given the increasing number of patches coming into the coresight subsystem and your new reponsabilities, I was wondering if you'd rather receive a pull request from hereon. Let me know what works best for you. Cordially, Mathieu Leo Yan (2): coresight: tmc: Refactor loops in etb dump coresight: tmc: Fix byte-address alignment for RRP Mathieu Poirier (2): coresight: etb10: Refactor etb_drvdata::mode handling coresight: etb10: Splitting function etb_enable() Suzuki K Poulose (37): coresight: Document error handling in coresight_register coresight: platform: Refactor graph endpoint parsing coresight: platform: Fix refcounting for graph nodes coresight: platform: Fix leaking device reference coresight: Fix remote endpoint parsing coresight: Add helper to check if the endpoint is input coresight: platform: Cleanup coresight connection handling coresight: Cleanup coresight DT bindings coresight: Fix handling of sinks coresight: etb10: Fix handling of perf mode coresight: perf: Fix per cpu path management coresight: perf: Avoid unncessary CPU hotplug read lock coresight: perf: Allow tracing on hotplugged CPUs coresight: perf: Disable trace path upon source error coresight: tmc-etr: Handle driver mode specific ETR buffers coresight: tmc-etr: Relax collection of trace from sysfs mode coresight: Convert driver messages to dev_dbg coresight: perf: Remove reset_buffer call back for sinks coresight: perf: Add helper to retrieve sink configuration coresight: perf: Remove set_buffer call back coresight: etm-perf: Add support for ETR backend coresight: Handle failures in enabling a trace path coresight: tmc-etr: Refactor for handling errors coresight: tmc-etr: Handle errors enabling CATU coresight: tmc-etb/etf: Prepare to handle errors enabling coresight: etm4x: Add support for handling errors coresight: etm3: Add support for handling errors coresight: etb10: Handle errors enabling the device coresight: dynamic-replicator: Handle multiple connections coresight: Add support for CLAIM tag protocol coresight: etmx: Claim devices before use coresight: funnel: Claim devices before use coresight: catu: Claim device before use coresight: dynamic-replicator: Claim device for use coreisght: tmc: Claim device before use coresight: dts: binding: Fix example for TPIU component coresight: dts: binding: Update coresight binding examples Tomasz Nowicki (1): coresight: etm4x: Configure EL2 exception level when kernel is running in HYP zhong jiang (2): coresight: Use ERR_CAST instead of ERR_PTR coresight: Remove redundant null pointer check before of_node_put and put_device .../devicetree/bindings/arm/coresight.txt | 120 --- drivers/hwtracing/coresight/coresight-catu.c | 6 + .../coresight/coresight-dynamic-replicator.c | 81 - drivers/hwtracing/coresight/coresight-etb10.c | 183 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 132 +++ drivers/hwtracing/coresight/coresight-etm-perf.h | 26 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 58 +++- drivers/hwtracing/coresight/coresight-etm4x.c | 93 +++-- drivers/hwtracing/coresight/coresight-funnel.c | 28 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- drivers/hwtracing/coresight/coresight-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-stm.c| 4 +- drivers/hwtracing/coresight/coresight-tmc-etf.c| 198 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c| 385 ++--- drivers/hwtracing/coresight/coresight-tmc.c| 4 +- drivers/hwtracing/coresight/coresight-tmc.h| 4 + drivers/hwtracing/coresight/coresight-tpiu.c | 6 +- drivers/hwtracing/coresight/coresight.c| 184 +++--- drivers/hwtracing/coresight/of_coresight.c | 262 +- include/linux/coresight.h | 41 ++- 20 files changed, 1268 insertions(+), 560 deletions(-) -- 2.7.4
[PATCH 03/44] coresight: platform: Fix refcounting for graph nodes
From: Suzuki K Poulose The coresight driver doesn't drop the references on the remote endpoint/port nodes. Add the missing of_node_put() calls. Reported-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 70205f3eae8e..28d3aef1660b 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -168,6 +168,11 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); + if (rparent) + of_node_put(rparent); + if (rport) + of_node_put(rport); + return ret; } -- 2.7.4
[PATCH 09/44] coresight: Use ERR_CAST instead of ERR_PTR
From: zhong jiang
Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
make the code more concise.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2eda5de304c2..11963647e19a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -536,7 +536,7 @@ tmc_init_etr_sg_table(struct device *dev, int node,
sg_table = tmc_alloc_sg_table(dev, node, nr_tpages, nr_dpages, pages);
if (IS_ERR(sg_table)) {
kfree(etr_table);
- return ERR_PTR(PTR_ERR(sg_table));
+ return ERR_CAST(sg_table);
}
etr_table->sg_table = sg_table;
--
2.7.4
[PATCH 3/9] phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/phy-brcm-sata.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c
b/drivers/phy/broadcom/phy-brcm-sata.c
index 8708ea3b4d6d..218735305d85 100644
--- a/drivers/phy/broadcom/phy-brcm-sata.c
+++ b/drivers/phy/broadcom/phy-brcm-sata.c
@@ -47,6 +47,7 @@ enum brcm_sata_phy_version {
BRCM_SATA_PHY_IPROC_NS2,
BRCM_SATA_PHY_IPROC_NSP,
BRCM_SATA_PHY_IPROC_SR,
+ BRCM_SATA_PHY_DSL_28NM,
};
enum brcm_sata_phy_rxaeq_mode {
@@ -96,7 +97,10 @@ enum sata_phy_regs {
PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
PLLCONTROL_0_FREQ_MONITOR = BIT(12),
PLLCONTROL_0_SEQ_START = BIT(15),
+ PLL_CAP_CHARGE_TIME = 0x83,
+ PLL_VCO_CAL_THRESH = 0x84,
PLL_CAP_CONTROL = 0x85,
+ PLL_FREQ_DET_TIME = 0x86,
PLL_ACTRL2 = 0x8b,
PLL_ACTRL2_SELDIV_MASK = 0x1f,
PLL_ACTRL2_SELDIV_SHIFT = 9,
@@ -106,6 +110,9 @@ enum sata_phy_regs {
PLL1_ACTRL2 = 0x82,
PLL1_ACTRL3 = 0x83,
PLL1_ACTRL4 = 0x84,
+ PLL1_ACTRL5 = 0x85,
+ PLL1_ACTRL6 = 0x86,
+ PLL1_ACTRL7 = 0x87,
TX_REG_BANK = 0x070,
TX_ACTRL0 = 0x80,
@@ -119,6 +126,8 @@ enum sata_phy_regs {
AEQ_FRC_EQ_FORCE= BIT(0),
AEQ_FRC_EQ_FORCE_VAL= BIT(1),
AEQRX_REG_BANK_1= 0xe0,
+ AEQRX_SLCAL0_CTRL0 = 0x82,
+ AEQRX_SLCAL1_CTRL0 = 0x86,
OOB_REG_BANK= 0x150,
OOB1_REG_BANK = 0x160,
@@ -168,6 +177,7 @@ static inline void __iomem *brcm_sata_pcb_base(struct
brcm_sata_port *port)
switch (priv->version) {
case BRCM_SATA_PHY_STB_28NM:
case BRCM_SATA_PHY_IPROC_NS2:
+ case BRCM_SATA_PHY_DSL_28NM:
size = SATA_PCB_REG_28NM_SPACE_SIZE;
break;
case BRCM_SATA_PHY_STB_40NM:
@@ -482,6 +492,61 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
return 0;
}
+static int brcm_dsl_sata_init(struct brcm_sata_port *port)
+{
+ void __iomem *base = brcm_sata_pcb_base(port);
+ struct device *dev = port->phy_priv->dev;
+ unsigned int try;
+ u32 tmp;
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3089);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+0, 0x3088);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+0, 0x3000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+0, 0x3000);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+ usleep_range(1000, 2000);
+
+ /* Acquire PLL lock */
+ try = 50;
+ while (try) {
+ tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+ BLOCK0_XGXSSTATUS);
+ if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
+ break;
+ msleep(20);
+ try--;
+ };
+
+ if (!try) {
+ /* PLL did not lock; give up */
+ dev_err(dev, "port%d PLL did not lock\n", port->portnum);
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "port%d initialized\n", port->portnum);
+
+ return 0;
+}
+
static int brcm_sata_phy_init(struct phy *phy)
{
int rc;
@@ -501,6 +566,9 @@ static int brcm_sata_phy_init(struct phy *phy)
case BRCM_SATA_PHY_IPROC_SR:
rc = brcm_sr_sata_init(port);
break;
+ case BRCM_SATA_PHY_DSL_28NM:
+ rc = brcm_dsl_sata_init(port);
+ break;
default:
rc =
[PATCH 00/44] coresight: next v4.19-rc4
Good day Greg, To start with here is the tally I gathered for inclusion in the 4.20 cycle - please consider at your convenience. As usual everything applies cleanly on your char-misc-next branch (f685fc6ab051). Second, given the increasing number of patches coming into the coresight subsystem and your new reponsabilities, I was wondering if you'd rather receive a pull request from hereon. Let me know what works best for you. Cordially, Mathieu Leo Yan (2): coresight: tmc: Refactor loops in etb dump coresight: tmc: Fix byte-address alignment for RRP Mathieu Poirier (2): coresight: etb10: Refactor etb_drvdata::mode handling coresight: etb10: Splitting function etb_enable() Suzuki K Poulose (37): coresight: Document error handling in coresight_register coresight: platform: Refactor graph endpoint parsing coresight: platform: Fix refcounting for graph nodes coresight: platform: Fix leaking device reference coresight: Fix remote endpoint parsing coresight: Add helper to check if the endpoint is input coresight: platform: Cleanup coresight connection handling coresight: Cleanup coresight DT bindings coresight: Fix handling of sinks coresight: etb10: Fix handling of perf mode coresight: perf: Fix per cpu path management coresight: perf: Avoid unncessary CPU hotplug read lock coresight: perf: Allow tracing on hotplugged CPUs coresight: perf: Disable trace path upon source error coresight: tmc-etr: Handle driver mode specific ETR buffers coresight: tmc-etr: Relax collection of trace from sysfs mode coresight: Convert driver messages to dev_dbg coresight: perf: Remove reset_buffer call back for sinks coresight: perf: Add helper to retrieve sink configuration coresight: perf: Remove set_buffer call back coresight: etm-perf: Add support for ETR backend coresight: Handle failures in enabling a trace path coresight: tmc-etr: Refactor for handling errors coresight: tmc-etr: Handle errors enabling CATU coresight: tmc-etb/etf: Prepare to handle errors enabling coresight: etm4x: Add support for handling errors coresight: etm3: Add support for handling errors coresight: etb10: Handle errors enabling the device coresight: dynamic-replicator: Handle multiple connections coresight: Add support for CLAIM tag protocol coresight: etmx: Claim devices before use coresight: funnel: Claim devices before use coresight: catu: Claim device before use coresight: dynamic-replicator: Claim device for use coreisght: tmc: Claim device before use coresight: dts: binding: Fix example for TPIU component coresight: dts: binding: Update coresight binding examples Tomasz Nowicki (1): coresight: etm4x: Configure EL2 exception level when kernel is running in HYP zhong jiang (2): coresight: Use ERR_CAST instead of ERR_PTR coresight: Remove redundant null pointer check before of_node_put and put_device .../devicetree/bindings/arm/coresight.txt | 120 --- drivers/hwtracing/coresight/coresight-catu.c | 6 + .../coresight/coresight-dynamic-replicator.c | 81 - drivers/hwtracing/coresight/coresight-etb10.c | 183 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 132 +++ drivers/hwtracing/coresight/coresight-etm-perf.h | 26 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 58 +++- drivers/hwtracing/coresight/coresight-etm4x.c | 93 +++-- drivers/hwtracing/coresight/coresight-funnel.c | 28 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- drivers/hwtracing/coresight/coresight-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-stm.c| 4 +- drivers/hwtracing/coresight/coresight-tmc-etf.c| 198 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c| 385 ++--- drivers/hwtracing/coresight/coresight-tmc.c| 4 +- drivers/hwtracing/coresight/coresight-tmc.h| 4 + drivers/hwtracing/coresight/coresight-tpiu.c | 6 +- drivers/hwtracing/coresight/coresight.c| 184 +++--- drivers/hwtracing/coresight/of_coresight.c | 262 +- include/linux/coresight.h | 41 ++- 20 files changed, 1268 insertions(+), 560 deletions(-) -- 2.7.4
[PATCH 03/44] coresight: platform: Fix refcounting for graph nodes
From: Suzuki K Poulose The coresight driver doesn't drop the references on the remote endpoint/port nodes. Add the missing of_node_put() calls. Reported-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/of_coresight.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c index 70205f3eae8e..28d3aef1660b 100644 --- a/drivers/hwtracing/coresight/of_coresight.c +++ b/drivers/hwtracing/coresight/of_coresight.c @@ -168,6 +168,11 @@ static int of_coresight_parse_endpoint(struct device *dev, ret = 1; } while (0); + if (rparent) + of_node_put(rparent); + if (rport) + of_node_put(rport); + return ret; } -- 2.7.4
[PATCH 09/44] coresight: Use ERR_CAST instead of ERR_PTR
From: zhong jiang
Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
make the code more concise.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2eda5de304c2..11963647e19a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -536,7 +536,7 @@ tmc_init_etr_sg_table(struct device *dev, int node,
sg_table = tmc_alloc_sg_table(dev, node, nr_tpages, nr_dpages, pages);
if (IS_ERR(sg_table)) {
kfree(etr_table);
- return ERR_PTR(PTR_ERR(sg_table));
+ return ERR_CAST(sg_table);
}
etr_table->sg_table = sg_table;
--
2.7.4
[PATCH 5/9] ata: ahci_brcm: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 8/9] ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 6df61518776f..546aabc6f965 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -143,6 +143,36 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
+
+ ahci: sata@8000 {
+ compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0xa000 0x9ac>, <0x8040 0x24>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 3 1>;
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <_phy0>;
+ };
+ };
+
+ sata_phy: sata-phy@8100 {
+ compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
+ reg = <0x8100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
/* Legacy UBUS base */
--
2.17.1
[PATCH 9/9] ARM: bcm63138: Enable SATA AHCI and PHY
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm963138dvt.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts
b/arch/arm/boot/dts/bcm963138dvt.dts
index c61673638fa8..8dca97eeaf57 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -41,3 +41,11 @@
brcm,nand-oob-sectors-size = <16>;
};
};
+
+ {
+ status = "okay";
+};
+
+_phy {
+ status = "okay";
+};
--
2.17.1
[PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 5/9] ata: ahci_brcm: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d55d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
[PATCH 8/9] ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 6df61518776f..546aabc6f965 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -143,6 +143,36 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
+
+ ahci: sata@8000 {
+ compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0xa000 0x9ac>, <0x8040 0x24>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 3 1>;
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <_phy0>;
+ };
+ };
+
+ sata_phy: sata-phy@8100 {
+ compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
+ reg = <0x8100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
/* Legacy UBUS base */
--
2.17.1
[PATCH 9/9] ARM: bcm63138: Enable SATA AHCI and PHY
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm963138dvt.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts
b/arch/arm/boot/dts/bcm963138dvt.dts
index c61673638fa8..8dca97eeaf57 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -41,3 +41,11 @@
brcm,nand-oob-sectors-size = <16>;
};
};
+
+ {
+ status = "okay";
+};
+
+_phy {
+ status = "okay";
+};
--
2.17.1
[PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 0/9] AHCI and SATA PHY support for BCM63138
Hi Kishon, Tejun, This patch series adds support for the SATA AHCI and PHY found on the ARM-basd BCM63138 DSL SoCs. It would probably make sense for patches 1-3 to go through Kishon's tree, patches 4-7 through Tejun's tree, and I would be merging the last two patches through the Broadcom ARM-SoC tree. Let me know if this is not a workable plan, thank you very much! Florian Fainelli (9): dt-bindings: phy: Document BCM63138 compatible string phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence dt-bindings: ata: Document BCM63138 compatible string ata: ahci_brcm: Allow optional reset controller to be used ata: ahci_brcm: Match BCM63138 compatible strings ata: ahci_brcm: Allow using driver or DSL SoCs ARM: dts: BCM63xx: enable SATA PHY and AHCI controller ARM: bcm63138: Enable SATA AHCI and PHY .../bindings/ata/brcm,sata-brcm.txt | 1 + .../devicetree/bindings/phy/brcm-sata-phy.txt | 1 + arch/arm/boot/dts/bcm63138.dtsi | 30 arch/arm/boot/dts/bcm963138dvt.dts| 8 +++ drivers/ata/Kconfig | 3 +- drivers/ata/ahci_brcm.c | 10 +++ drivers/phy/broadcom/Kconfig | 3 +- drivers/phy/broadcom/phy-brcm-sata.c | 70 +++ 8 files changed, 124 insertions(+), 2 deletions(-) -- 2.17.1
[PATCH 4/9] dt-bindings: ata: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-ahci" as a valid compatible string for the standard Broadcom AHCI controller. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt index 0a5b3b47f217..7713a413c6a7 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt @@ -9,6 +9,7 @@ Required properties: "brcm,bcm7445-ahci" "brcm,bcm-nsp-ahci" "brcm,sata3-ahci" + "brcm,bcm63138-ahci" - reg: register mappings for AHCI and SATA_TOP_CTRL - reg-names : "ahci" and "top-ctrl" - interrupts : interrupt mapping for SATA IRQ -- 2.17.1
[PATCH 0/9] AHCI and SATA PHY support for BCM63138
Hi Kishon, Tejun, This patch series adds support for the SATA AHCI and PHY found on the ARM-basd BCM63138 DSL SoCs. It would probably make sense for patches 1-3 to go through Kishon's tree, patches 4-7 through Tejun's tree, and I would be merging the last two patches through the Broadcom ARM-SoC tree. Let me know if this is not a workable plan, thank you very much! Florian Fainelli (9): dt-bindings: phy: Document BCM63138 compatible string phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence dt-bindings: ata: Document BCM63138 compatible string ata: ahci_brcm: Allow optional reset controller to be used ata: ahci_brcm: Match BCM63138 compatible strings ata: ahci_brcm: Allow using driver or DSL SoCs ARM: dts: BCM63xx: enable SATA PHY and AHCI controller ARM: bcm63138: Enable SATA AHCI and PHY .../bindings/ata/brcm,sata-brcm.txt | 1 + .../devicetree/bindings/phy/brcm-sata-phy.txt | 1 + arch/arm/boot/dts/bcm63138.dtsi | 30 arch/arm/boot/dts/bcm963138dvt.dts| 8 +++ drivers/ata/Kconfig | 3 +- drivers/ata/ahci_brcm.c | 10 +++ drivers/phy/broadcom/Kconfig | 3 +- drivers/phy/broadcom/phy-brcm-sata.c | 70 +++ 8 files changed, 124 insertions(+), 2 deletions(-) -- 2.17.1
[PATCH 4/9] dt-bindings: ata: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-ahci" as a valid compatible string for the standard Broadcom AHCI controller. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt index 0a5b3b47f217..7713a413c6a7 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt @@ -9,6 +9,7 @@ Required properties: "brcm,bcm7445-ahci" "brcm,bcm-nsp-ahci" "brcm,sata3-ahci" + "brcm,bcm63138-ahci" - reg: register mappings for AHCI and SATA_TOP_CTRL - reg-names : "ahci" and "top-ctrl" - interrupts : interrupt mapping for SATA IRQ -- 2.17.1
[PATCH 7/9] ata: ahci_brcm: Allow using driver or DSL SoCs
The Broadcom STB AHCI controller is the same as the one found on DSL SoCs, so we will utilize the same driver on these systems as well. Signed-off-by: Florian Fainelli --- drivers/ata/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 39b181d6bd0d..99698d7fe585 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -121,7 +121,8 @@ config SATA_AHCI_PLATFORM config AHCI_BRCM tristate "Broadcom AHCI SATA support" - depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP + depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP || \ + ARCH_BCM_63XX help This option enables support for the AHCI SATA3 controller found on Broadcom SoC's. -- 2.17.1
[PATCH 6/9] ata: ahci_brcm: Match BCM63138 compatible strings
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 7/9] ata: ahci_brcm: Allow using driver or DSL SoCs
The Broadcom STB AHCI controller is the same as the one found on DSL SoCs, so we will utilize the same driver on these systems as well. Signed-off-by: Florian Fainelli --- drivers/ata/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 39b181d6bd0d..99698d7fe585 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -121,7 +121,8 @@ config SATA_AHCI_PLATFORM config AHCI_BRCM tristate "Broadcom AHCI SATA support" - depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP + depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP || \ + ARCH_BCM_63XX help This option enables support for the AHCI SATA3 controller found on Broadcom SoC's. -- 2.17.1
[PATCH 6/9] ata: ahci_brcm: Match BCM63138 compatible strings
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
[PATCH 2/9] phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 1/9] dt-bindings: phy: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-sata-phy" as a valid compatible string describing the standard Broadcom SATA PHY block. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index 0aced97d8092..b640845fec67 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -8,6 +8,7 @@ Required properties: "brcm,iproc-nsp-sata-phy" "brcm,phy-sata3" "brcm,iproc-sr-sata-phy" + "brcm,bcm63138-sata-phy" - address-cells: should be 1 - size-cells: should be 0 - reg: register ranges for the PHY PCB interface -- 2.17.1
[PATCH 2/9] phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 8786a9674471..aa917a61071d 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD config PHY_BRCM_SATA tristate "Broadcom SATA PHY driver" - depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \ + ARCH_BCM_63XX || COMPILE_TEST depends on OF select GENERIC_PHY default ARCH_BCM_IPROC -- 2.17.1
[PATCH 1/9] dt-bindings: phy: Document BCM63138 compatible string
Document the compatible string "brcm,bcm63138-sata-phy" as a valid compatible string describing the standard Broadcom SATA PHY block. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index 0aced97d8092..b640845fec67 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -8,6 +8,7 @@ Required properties: "brcm,iproc-nsp-sata-phy" "brcm,phy-sata3" "brcm,iproc-sr-sata-phy" + "brcm,bcm63138-sata-phy" - address-cells: should be 1 - size-cells: should be 0 - reg: register ranges for the PHY PCB interface -- 2.17.1
Re: [PATCH v7 3/4] dt-bindings: power: supply: qcom_bms: Add bindings
On 20 September 2018 17:58:47 BST, Sebastian Reichel wrote: >[Dropped a couple of people from CC, added Baolin] > >Hi Craig, Baolin and Rob, > >On Thu, Sep 20, 2018 at 03:32:29PM +0100, Craig wrote: >> On 16 September 2018 13:10:45 BST, Sebastian Reichel > wrote: >> >Sorry for my long delay in reviewing this. I like the binding, >> >but the "qcom," specific properties should become common properties >> >in >> > >> >Documentation/devicetree/bindings/power/supply/battery.txt >> >and referenced via monitored-battery. > >> Thanks for the review, what bindings for ocv would you prefer? The >> spreadtrum ones or mine? > >Most importantly I want to see only one generic binding supporting >both use cases. As far as I can see there are two major differences: > >1. Qcom uses legend properties and SC27XX embedds this into data >2. Qcom supports temperature based mapping > >The second point is easy: Not having temperature information can >be a subset of the data with temperature info. The main thing to >discuss are the legend properties. I suppose we have these >proposals: > >Proposal A (from Qcom BMS binding): > >ocv-capacity-legend = /bits/ 8 <100 95 90 85 80 75 70 65 60 55 50 45 >...>; >ocv-temp-legend-celsius = /bits/ 8 <(-10) 0 25 50 65>; >ocv-lut-microvolt = <4305 4305 4303 4299 > >Proposal B (from SC27XX binding): > >ocv-cap-table = <4185 100>, <4113 95>, <4066 90>, <4022 85> ...; > >I prefer the second binding (with mV -> uV), but I think it becomes >messy when temperature is added. What do you think about the >following proposal (derived from pinctrl style): > >Proposal C: > >ocv-capacity-table-temperatures = <(-10) 0 10>; >ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, ...; >ocv-capacity-table-1 = <420 100>, <4185000 95>, <4113000 90>, ...; >ocv-capacity-table-2 = <425 100>, <420 95>, <4185000 90>, ...; > >-- Sebastian C looks good to me however I do kinda think it should be millivolts as I don't think any hardware reads in microvolts and the zeroes make it look quite ugly
Re: [PATCH v7 3/4] dt-bindings: power: supply: qcom_bms: Add bindings
On 20 September 2018 17:58:47 BST, Sebastian Reichel wrote: >[Dropped a couple of people from CC, added Baolin] > >Hi Craig, Baolin and Rob, > >On Thu, Sep 20, 2018 at 03:32:29PM +0100, Craig wrote: >> On 16 September 2018 13:10:45 BST, Sebastian Reichel > wrote: >> >Sorry for my long delay in reviewing this. I like the binding, >> >but the "qcom," specific properties should become common properties >> >in >> > >> >Documentation/devicetree/bindings/power/supply/battery.txt >> >and referenced via monitored-battery. > >> Thanks for the review, what bindings for ocv would you prefer? The >> spreadtrum ones or mine? > >Most importantly I want to see only one generic binding supporting >both use cases. As far as I can see there are two major differences: > >1. Qcom uses legend properties and SC27XX embedds this into data >2. Qcom supports temperature based mapping > >The second point is easy: Not having temperature information can >be a subset of the data with temperature info. The main thing to >discuss are the legend properties. I suppose we have these >proposals: > >Proposal A (from Qcom BMS binding): > >ocv-capacity-legend = /bits/ 8 <100 95 90 85 80 75 70 65 60 55 50 45 >...>; >ocv-temp-legend-celsius = /bits/ 8 <(-10) 0 25 50 65>; >ocv-lut-microvolt = <4305 4305 4303 4299 > >Proposal B (from SC27XX binding): > >ocv-cap-table = <4185 100>, <4113 95>, <4066 90>, <4022 85> ...; > >I prefer the second binding (with mV -> uV), but I think it becomes >messy when temperature is added. What do you think about the >following proposal (derived from pinctrl style): > >Proposal C: > >ocv-capacity-table-temperatures = <(-10) 0 10>; >ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, ...; >ocv-capacity-table-1 = <420 100>, <4185000 95>, <4113000 90>, ...; >ocv-capacity-table-2 = <425 100>, <420 95>, <4185000 90>, ...; > >-- Sebastian C looks good to me however I do kinda think it should be millivolts as I don't think any hardware reads in microvolts and the zeroes make it look quite ugly
mmotm 2018-09-20-12-10 uploaded
The mm-of-the-moment snapshot 2018-09-20-12-10 has been uploaded to http://www.ozlabs.org/~akpm/mmotm/ mmotm-readme.txt says README for mm-of-the-moment: http://www.ozlabs.org/~akpm/mmotm/ This is a snapshot of my -mm patch queue. Uploaded at random hopefully more than once a week. You will need quilt to apply these patches to the latest Linus release (4.x or 4.x-rcY). The series file is in broken-out.tar.gz and is duplicated in http://ozlabs.org/~akpm/mmotm/series The file broken-out.tar.gz contains two datestamp files: .DATE and .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, followed by the base kernel version against which this patch series is to be applied. This tree is partially included in linux-next. To see which patches are included in linux-next, consult the `series' file. Only the patches within the #NEXT_PATCHES_START/#NEXT_PATCHES_END markers are included in linux-next. A git tree which contains the memory management portion of this tree is maintained at git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git by Michal Hocko. It contains the patches which are between the "#NEXT_PATCHES_START mm" and "#NEXT_PATCHES_END" markers, from the series file, http://www.ozlabs.org/~akpm/mmotm/series. A full copy of the full kernel tree with the linux-next and mmotm patches already applied is available through git within an hour of the mmotm release. Individual mmotm releases are tagged. The master branch always points to the latest release, so it's constantly rebasing. http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/ To develop on top of mmotm git: $ git remote add mmotm git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git $ git remote update mmotm $ git checkout -b topic mmotm/master $ git send-email mmotm/master.. [...] To rebase a branch with older patches to a new mmotm release: $ git remote update mmotm $ git rebase --onto mmotm/master topic The directory http://www.ozlabs.org/~akpm/mmots/ (mm-of-the-second) contains daily snapshots of the -mm tree. It is updated more frequently than mmotm, and is untested. A git copy of this tree is available at http://git.cmpxchg.org/cgit.cgi/linux-mmots.git/ and use of this tree is similar to http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/, described above. This mmotm tree contains the following patches against 4.19-rc4: (patches marked "*" will be included in linux-next) origin.patch * fork-report-pid-exhaustion-correctly.patch * mm-disable-deferred-struct-page-for-32-bit-arches.patch * proc-kcore-fix-invalid-memory-access-in-multi-page-read-optimization-v3.patch * mm-shmem-correctly-annotate-new-inodes-for-lockdep.patch * kernel-remove-duplicated-include-from-sysc.patch * mm-slowly-shrink-slabs-with-a-relatively-small-number-of-objects.patch * ocfs2-fix-ocfs2-read-block-panic.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages-v7.patch * hugetlb-take-pmd-sharing-into-account-when-flushing-tlb-caches.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5-checkpatch-fixes.patch * mm-thp-fix-mlocking-thp-page-with-migration-enabled.patch * arm-arch-arm-include-asm-pageh-needs-personalityh.patch * linkageh-align-weak-symbols.patch * arm64-lib-use-c-string-functions-with-kasan-enabled.patch * lib-test_kasan-add-tests-for-several-string-memory-api-functions.patch * scripts-tags-add-declare_hashtable.patch * ocfs2-fix-a-gcc-compiled-warning.patch * ocfs2-get-rid-of-ocfs2_is_o2cb_active-function.patch * ocfs2-without-quota-support-try-to-avoid-calling-quota-recovery.patch * ocfs2-dont-use-iocb-when-eiocbqueued-returns.patch * ocfs2-fix-a-misuse-a-of-brelse-after-failing-ocfs2_check_dir_entry.patch * ocfs2-dont-put-and-assigning-null-to-bh-allocated-outside.patch * ocfs2-dlmglue-clean-up-timestamp-handling.patch * fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * ocfs2-fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent-fix.patch * block-restore-proc-partitions-to-not-display-non-partitionable-removable-devices.patch * vfs-allow-dedupe-of-user-owned-read-only-files.patch * vfs-dedupe-should-return-eperm-if-permission-is-not-granted.patch * fs-iomap-change-return-type-to-vm_fault_t.patch * xtensa-use-generic-vgah.patch mm.patch * mm-slubc-switch-to-bitmap_zalloc.patch * mm-rework-memcg-kernel-stack-accounting.patch * mm-drain-memcg-stocks-on-css-offlining.patch * mm-dont-miss-the-last-page-because-of-round-off-error.patch * mm-dont-miss-the-last-page-because-of-round-off-error-fix.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry-fix.patch *
mmotm 2018-09-20-12-10 uploaded
The mm-of-the-moment snapshot 2018-09-20-12-10 has been uploaded to http://www.ozlabs.org/~akpm/mmotm/ mmotm-readme.txt says README for mm-of-the-moment: http://www.ozlabs.org/~akpm/mmotm/ This is a snapshot of my -mm patch queue. Uploaded at random hopefully more than once a week. You will need quilt to apply these patches to the latest Linus release (4.x or 4.x-rcY). The series file is in broken-out.tar.gz and is duplicated in http://ozlabs.org/~akpm/mmotm/series The file broken-out.tar.gz contains two datestamp files: .DATE and .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, followed by the base kernel version against which this patch series is to be applied. This tree is partially included in linux-next. To see which patches are included in linux-next, consult the `series' file. Only the patches within the #NEXT_PATCHES_START/#NEXT_PATCHES_END markers are included in linux-next. A git tree which contains the memory management portion of this tree is maintained at git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git by Michal Hocko. It contains the patches which are between the "#NEXT_PATCHES_START mm" and "#NEXT_PATCHES_END" markers, from the series file, http://www.ozlabs.org/~akpm/mmotm/series. A full copy of the full kernel tree with the linux-next and mmotm patches already applied is available through git within an hour of the mmotm release. Individual mmotm releases are tagged. The master branch always points to the latest release, so it's constantly rebasing. http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/ To develop on top of mmotm git: $ git remote add mmotm git://git.kernel.org/pub/scm/linux/kernel/git/mhocko/mm.git $ git remote update mmotm $ git checkout -b topic mmotm/master $ git send-email mmotm/master.. [...] To rebase a branch with older patches to a new mmotm release: $ git remote update mmotm $ git rebase --onto mmotm/master topic The directory http://www.ozlabs.org/~akpm/mmots/ (mm-of-the-second) contains daily snapshots of the -mm tree. It is updated more frequently than mmotm, and is untested. A git copy of this tree is available at http://git.cmpxchg.org/cgit.cgi/linux-mmots.git/ and use of this tree is similar to http://git.cmpxchg.org/cgit.cgi/linux-mmotm.git/, described above. This mmotm tree contains the following patches against 4.19-rc4: (patches marked "*" will be included in linux-next) origin.patch * fork-report-pid-exhaustion-correctly.patch * mm-disable-deferred-struct-page-for-32-bit-arches.patch * proc-kcore-fix-invalid-memory-access-in-multi-page-read-optimization-v3.patch * mm-shmem-correctly-annotate-new-inodes-for-lockdep.patch * kernel-remove-duplicated-include-from-sysc.patch * mm-slowly-shrink-slabs-with-a-relatively-small-number-of-objects.patch * ocfs2-fix-ocfs2-read-block-panic.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages.patch * mm-migration-fix-migration-of-huge-pmd-shared-pages-v7.patch * hugetlb-take-pmd-sharing-into-account-when-flushing-tlb-caches.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5.patch * fix-crash-on-ocfs2_duplicate_clusters_by_page-v5-checkpatch-fixes.patch * mm-thp-fix-mlocking-thp-page-with-migration-enabled.patch * arm-arch-arm-include-asm-pageh-needs-personalityh.patch * linkageh-align-weak-symbols.patch * arm64-lib-use-c-string-functions-with-kasan-enabled.patch * lib-test_kasan-add-tests-for-several-string-memory-api-functions.patch * scripts-tags-add-declare_hashtable.patch * ocfs2-fix-a-gcc-compiled-warning.patch * ocfs2-get-rid-of-ocfs2_is_o2cb_active-function.patch * ocfs2-without-quota-support-try-to-avoid-calling-quota-recovery.patch * ocfs2-dont-use-iocb-when-eiocbqueued-returns.patch * ocfs2-fix-a-misuse-a-of-brelse-after-failing-ocfs2_check_dir_entry.patch * ocfs2-dont-put-and-assigning-null-to-bh-allocated-outside.patch * ocfs2-dlmglue-clean-up-timestamp-handling.patch * fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * ocfs2-fix-dead-lock-caused-by-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent.patch * fix-clusters-leak-in-ocfs2_defrag_extent-fix.patch * block-restore-proc-partitions-to-not-display-non-partitionable-removable-devices.patch * vfs-allow-dedupe-of-user-owned-read-only-files.patch * vfs-dedupe-should-return-eperm-if-permission-is-not-granted.patch * fs-iomap-change-return-type-to-vm_fault_t.patch * xtensa-use-generic-vgah.patch mm.patch * mm-slubc-switch-to-bitmap_zalloc.patch * mm-rework-memcg-kernel-stack-accounting.patch * mm-drain-memcg-stocks-on-css-offlining.patch * mm-dont-miss-the-last-page-because-of-round-off-error.patch * mm-dont-miss-the-last-page-because-of-round-off-error-fix.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry.patch * mmpage_alloc-pf_wq_worker-threads-must-sleep-at-should_reclaim_retry-fix.patch *
[PATCH] kernel/kcov: Replace vm_insert_page with vmf_insert_page
There is a plan to replace vm_insert_page with new API
vmf_insert_page. As part of it, converting vm_insert_page
to use vmf_insert_page.
Signed-off-by: Souptick Joarder
---
kernel/kcov.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/kcov.c b/kernel/kcov.c
index 3ebd09e..8900d8e 100644
--- a/kernel/kcov.c
+++ b/kernel/kcov.c
@@ -293,8 +293,9 @@ static int kcov_mmap(struct file *filep, struct
vm_area_struct *vma)
spin_unlock(>lock);
for (off = 0; off < size; off += PAGE_SIZE) {
page = vmalloc_to_page(kcov->area + off);
- if (vm_insert_page(vma, vma->vm_start + off, page))
- WARN_ONCE(1, "vm_insert_page() failed");
+ if (vmf_insert_page(vma, vma->vm_start + off, page)
+ != VM_FAULT_NOPAGE)
+ WARN_ONCE(1, "vmf_insert_page() failed");
}
return 0;
}
--
1.9.1
[PATCH] kernel/kcov: Replace vm_insert_page with vmf_insert_page
There is a plan to replace vm_insert_page with new API
vmf_insert_page. As part of it, converting vm_insert_page
to use vmf_insert_page.
Signed-off-by: Souptick Joarder
---
kernel/kcov.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/kcov.c b/kernel/kcov.c
index 3ebd09e..8900d8e 100644
--- a/kernel/kcov.c
+++ b/kernel/kcov.c
@@ -293,8 +293,9 @@ static int kcov_mmap(struct file *filep, struct
vm_area_struct *vma)
spin_unlock(>lock);
for (off = 0; off < size; off += PAGE_SIZE) {
page = vmalloc_to_page(kcov->area + off);
- if (vm_insert_page(vma, vma->vm_start + off, page))
- WARN_ONCE(1, "vm_insert_page() failed");
+ if (vmf_insert_page(vma, vma->vm_start + off, page)
+ != VM_FAULT_NOPAGE)
+ WARN_ONCE(1, "vmf_insert_page() failed");
}
return 0;
}
--
1.9.1
RE: [PATCH V2 4/13] KVM/MMU: Flush tlb directly in the kvm_handle_hva_range()
From: Tianyu Lan Sent: Thursday, September 20, 2018 7:30 AM
> On 9/20/2018 12:08 AM, Michael Kelley (EOSG) wrote:
> > From: Tianyu Lan Sent: Monday, September 17, 2018 8:19 PM
> >> +
> >> + if (ret && kvm_available_flush_tlb_with_range()) {
> >> + kvm_flush_remote_tlbs_with_address(kvm,
> >> + gfn_start,
> >> + gfn_end - gfn_start);
> >
> > Does the above need to be gfn_end - gfn_start + 1?
>
> The flush range depends on the input parameter frame start and frame end
> of for_each_slot_rmap_range().
>
> for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
> PT_MAX_HUGEPAGE_LEVEL,
> gfn_start, gfn_end - 1,
> )
> ret |= handler(kvm, iterator.rmap, memslot,
> iterator.gfn, iterator.level, data);
>
>
> The start is "gfn_start" and the end is "gfn_end - 1". The flush size is
> (gfn_end - 1) - gfn_start + 1 = gfn_end - gfn_start.
>
Got it. I agree.
Michael
RE: [PATCH V2 4/13] KVM/MMU: Flush tlb directly in the kvm_handle_hva_range()
From: Tianyu Lan Sent: Thursday, September 20, 2018 7:30 AM
> On 9/20/2018 12:08 AM, Michael Kelley (EOSG) wrote:
> > From: Tianyu Lan Sent: Monday, September 17, 2018 8:19 PM
> >> +
> >> + if (ret && kvm_available_flush_tlb_with_range()) {
> >> + kvm_flush_remote_tlbs_with_address(kvm,
> >> + gfn_start,
> >> + gfn_end - gfn_start);
> >
> > Does the above need to be gfn_end - gfn_start + 1?
>
> The flush range depends on the input parameter frame start and frame end
> of for_each_slot_rmap_range().
>
> for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
> PT_MAX_HUGEPAGE_LEVEL,
> gfn_start, gfn_end - 1,
> )
> ret |= handler(kvm, iterator.rmap, memslot,
> iterator.gfn, iterator.level, data);
>
>
> The start is "gfn_start" and the end is "gfn_end - 1". The flush size is
> (gfn_end - 1) - gfn_start + 1 = gfn_end - gfn_start.
>
Got it. I agree.
Michael
Re: [PATCH] Don't hardcode path as it is architecture dependent
Am Donnerstag, 20. September 2018, 08:26:38 CEST schrieb Ritesh Raj Sarraf:
> The current code fails to run on amd64 because of hardcoded reference to
> i386
>
> Signed-off-by: Ritesh Raj Sarraf
Thanks for spotting this!
> ---
> arch/um/drivers/port_user.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/um/drivers/port_user.c b/arch/um/drivers/port_user.c
> index 9a8e1b64c22e..5f56d11b886f 100644
> --- a/arch/um/drivers/port_user.c
> +++ b/arch/um/drivers/port_user.c
> @@ -168,7 +168,7 @@ int port_connection(int fd, int *socket, int *pid_out)
> {
> int new, err;
> char *argv[] = { "/usr/sbin/in.telnetd", "-L",
> - "/usr/lib/uml/port-helper", NULL };
> + OS_LIB_PATH "/uml/port-helper", NULL };
> struct port_pre_exec_data data;
>
> new = accept(fd, NULL, 0);
Thanks,
//richard
Re: [PATCH] Don't hardcode path as it is architecture dependent
Am Donnerstag, 20. September 2018, 08:26:38 CEST schrieb Ritesh Raj Sarraf:
> The current code fails to run on amd64 because of hardcoded reference to
> i386
>
> Signed-off-by: Ritesh Raj Sarraf
Thanks for spotting this!
> ---
> arch/um/drivers/port_user.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/um/drivers/port_user.c b/arch/um/drivers/port_user.c
> index 9a8e1b64c22e..5f56d11b886f 100644
> --- a/arch/um/drivers/port_user.c
> +++ b/arch/um/drivers/port_user.c
> @@ -168,7 +168,7 @@ int port_connection(int fd, int *socket, int *pid_out)
> {
> int new, err;
> char *argv[] = { "/usr/sbin/in.telnetd", "-L",
> - "/usr/lib/uml/port-helper", NULL };
> + OS_LIB_PATH "/uml/port-helper", NULL };
> struct port_pre_exec_data data;
>
> new = accept(fd, NULL, 0);
Thanks,
//richard
Re: [PATCH v3 00/16] Another round of tsens cleanups
On Wed, Sep 12, 2018 at 03:22:45PM +0530, Amit Kucheria wrote: > This is another series of tsens cleanups before we add interrupt support. > This applies on top of 4.19-rc2. > > Patches [1-6] can directly be applied by Eduardo. > Patches [9-16] can directly be applied by Andy. Eduardo, I ACKed the DTS patches for this. Can you take 9-16 along with the 1-6 through your tree? Thanks, Andy
Re: [PATCH v3 00/16] Another round of tsens cleanups
On Wed, Sep 12, 2018 at 03:22:45PM +0530, Amit Kucheria wrote: > This is another series of tsens cleanups before we add interrupt support. > This applies on top of 4.19-rc2. > > Patches [1-6] can directly be applied by Eduardo. > Patches [9-16] can directly be applied by Andy. Eduardo, I ACKed the DTS patches for this. Can you take 9-16 along with the 1-6 through your tree? Thanks, Andy
[PATCH V6 5/6] x86/intel_rdt: Use perf infrastructure for measurements
The success of a cache pseudo-locked region is measured using
performance monitoring events that are programmed directly at the time
the user requests a measurement.
Modifying the performance event registers directly is not appropriate
since it circumvents the in-kernel perf infrastructure that exists to
manage these resources and provide resource arbitration to the
performance monitoring hardware.
The cache pseudo-locking measurements are modified to use the in-kernel
perf infrastructure. Performance events are created and validated with
the appropriate perf API. The performance counters are still read as
directly as possible to avoid the additional cache hits. This is
done safely by first ensuring with the perf API that the counters have
been programmed correctly and only accessing the counters in an
interrupt disabled section where they are not able to be moved.
As part of the transition to the in-kernel perf infrastructure the L2
and L3 measurements are split into two separate measurements that can
be triggered independently. This separation prevents additional cache
misses incurred during the extra testing code used to decide if a
L2 and/or L3 measurement should be made.
Signed-off-by: Reinette Chatre
---
V6:
- Replace an expanded minimum check with min(). Thanks to Peter for
noticing this.
Documentation/x86/intel_rdt_ui.txt | 22 +-
arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c | 304
2 files changed, 203 insertions(+), 123 deletions(-)
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index f662d3c530e5..52b10945ff75 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -520,18 +520,24 @@ the pseudo-locked region:
2) Cache hit and miss measurements using model specific precision counters if
available. Depending on the levels of cache on the system the pseudo_lock_l2
and pseudo_lock_l3 tracepoints are available.
- WARNING: triggering this measurement uses from two (for just L2
- measurements) to four (for L2 and L3 measurements) precision counters on
- the system, if any other measurements are in progress the counters and
- their corresponding event registers will be clobbered.
When a pseudo-locked region is created a new debugfs directory is created for
it in debugfs as /sys/kernel/debug/resctrl/. A single
write-only file, pseudo_lock_measure, is present in this directory. The
-measurement on the pseudo-locked region depends on the number, 1 or 2,
-written to this debugfs file. Since the measurements are recorded with the
-tracing infrastructure the relevant tracepoints need to be enabled before the
-measurement is triggered.
+measurement of the pseudo-locked region depends on the number written to this
+debugfs file:
+1 - writing "1" to the pseudo_lock_measure file will trigger the latency
+ measurement captured in the pseudo_lock_mem_latency tracepoint. See
+ example below.
+2 - writing "2" to the pseudo_lock_measure file will trigger the L2 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l2 tracepoint. See example below.
+3 - writing "3" to the pseudo_lock_measure file will trigger the L3 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l3 tracepoint.
+
+All measurements are recorded with the tracing infrastructure. This requires
+the relevant tracepoints to be enabled before the measurement is triggered.
Example of latency debugging interface:
In this example a pseudo-locked region named "newlock" was created. Here is
diff --git a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
index 33d7968f152a..d68836139cf9 100644
--- a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
+++ b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
@@ -27,6 +27,7 @@
#include
#include
+#include "../../events/perf_event.h" /* For X86_CONFIG() */
#include "intel_rdt.h"
#define CREATE_TRACE_POINTS
@@ -107,16 +108,6 @@ static u64 get_prefetch_disable_bits(void)
return 0;
}
-/*
- * Helper to write 64bit value to MSR without tracing. Used when
- * use of the cache should be restricted and use of registers used
- * for local variables avoided.
- */
-static inline void pseudo_wrmsrl_notrace(unsigned int msr, u64 val)
-{
- __wrmsr(msr, (u32)(val & 0xULL), (u32)(val >> 32));
-}
-
/**
* pseudo_lock_minor_get - Obtain available minor number
* @minor: Pointer to where new minor number will be stored
@@ -925,7 +916,7 @@ static int measure_cycles_lat_fn(void *_plr)
* The actual configuration of the event is set right before use in order
* to use the X86_CONFIG macro.
*/
-static struct perf_event_attr __attribute__((unused)) perf_miss_attr = {
+static struct perf_event_attr perf_miss_attr = {
.type = PERF_TYPE_RAW,
.size = sizeof(struct perf_event_attr),
.pinned = 1,
@@
[PATCH V6 5/6] x86/intel_rdt: Use perf infrastructure for measurements
The success of a cache pseudo-locked region is measured using
performance monitoring events that are programmed directly at the time
the user requests a measurement.
Modifying the performance event registers directly is not appropriate
since it circumvents the in-kernel perf infrastructure that exists to
manage these resources and provide resource arbitration to the
performance monitoring hardware.
The cache pseudo-locking measurements are modified to use the in-kernel
perf infrastructure. Performance events are created and validated with
the appropriate perf API. The performance counters are still read as
directly as possible to avoid the additional cache hits. This is
done safely by first ensuring with the perf API that the counters have
been programmed correctly and only accessing the counters in an
interrupt disabled section where they are not able to be moved.
As part of the transition to the in-kernel perf infrastructure the L2
and L3 measurements are split into two separate measurements that can
be triggered independently. This separation prevents additional cache
misses incurred during the extra testing code used to decide if a
L2 and/or L3 measurement should be made.
Signed-off-by: Reinette Chatre
---
V6:
- Replace an expanded minimum check with min(). Thanks to Peter for
noticing this.
Documentation/x86/intel_rdt_ui.txt | 22 +-
arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c | 304
2 files changed, 203 insertions(+), 123 deletions(-)
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index f662d3c530e5..52b10945ff75 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -520,18 +520,24 @@ the pseudo-locked region:
2) Cache hit and miss measurements using model specific precision counters if
available. Depending on the levels of cache on the system the pseudo_lock_l2
and pseudo_lock_l3 tracepoints are available.
- WARNING: triggering this measurement uses from two (for just L2
- measurements) to four (for L2 and L3 measurements) precision counters on
- the system, if any other measurements are in progress the counters and
- their corresponding event registers will be clobbered.
When a pseudo-locked region is created a new debugfs directory is created for
it in debugfs as /sys/kernel/debug/resctrl/. A single
write-only file, pseudo_lock_measure, is present in this directory. The
-measurement on the pseudo-locked region depends on the number, 1 or 2,
-written to this debugfs file. Since the measurements are recorded with the
-tracing infrastructure the relevant tracepoints need to be enabled before the
-measurement is triggered.
+measurement of the pseudo-locked region depends on the number written to this
+debugfs file:
+1 - writing "1" to the pseudo_lock_measure file will trigger the latency
+ measurement captured in the pseudo_lock_mem_latency tracepoint. See
+ example below.
+2 - writing "2" to the pseudo_lock_measure file will trigger the L2 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l2 tracepoint. See example below.
+3 - writing "3" to the pseudo_lock_measure file will trigger the L3 cache
+ residency (cache hits and misses) measurement captured in the
+ pseudo_lock_l3 tracepoint.
+
+All measurements are recorded with the tracing infrastructure. This requires
+the relevant tracepoints to be enabled before the measurement is triggered.
Example of latency debugging interface:
In this example a pseudo-locked region named "newlock" was created. Here is
diff --git a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
index 33d7968f152a..d68836139cf9 100644
--- a/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
+++ b/arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c
@@ -27,6 +27,7 @@
#include
#include
+#include "../../events/perf_event.h" /* For X86_CONFIG() */
#include "intel_rdt.h"
#define CREATE_TRACE_POINTS
@@ -107,16 +108,6 @@ static u64 get_prefetch_disable_bits(void)
return 0;
}
-/*
- * Helper to write 64bit value to MSR without tracing. Used when
- * use of the cache should be restricted and use of registers used
- * for local variables avoided.
- */
-static inline void pseudo_wrmsrl_notrace(unsigned int msr, u64 val)
-{
- __wrmsr(msr, (u32)(val & 0xULL), (u32)(val >> 32));
-}
-
/**
* pseudo_lock_minor_get - Obtain available minor number
* @minor: Pointer to where new minor number will be stored
@@ -925,7 +916,7 @@ static int measure_cycles_lat_fn(void *_plr)
* The actual configuration of the event is set right before use in order
* to use the X86_CONFIG macro.
*/
-static struct perf_event_attr __attribute__((unused)) perf_miss_attr = {
+static struct perf_event_attr perf_miss_attr = {
.type = PERF_TYPE_RAW,
.size = sizeof(struct perf_event_attr),
.pinned = 1,
@@
Re: [PATCH v3 16/16] arm64: dts: sdm845: enable tsens thermal zones
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote: > One thermal zone per cpu is defined > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Tested-by: Matthias Kaehlcke > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++ > 1 file changed, 170 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0c9a2aa6a1b5..eb801922f6bb 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi Acked-by: Andy Gross
Re: [PATCH v3 16/16] arm64: dts: sdm845: enable tsens thermal zones
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote: > One thermal zone per cpu is defined > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Tested-by: Matthias Kaehlcke > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++ > 1 file changed, 170 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0c9a2aa6a1b5..eb801922f6bb 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi Acked-by: Andy Gross
Re: [PATCH v3 15/16] arm64: dts: msm8916: Add camera thermal zone
On Wed, Sep 12, 2018 at 03:23:00PM +0530, Amit Kucheria wrote: > Initialise the camera thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 + > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 62f079ae9ba3..3dc8b8aa76c7 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 15/16] arm64: dts: msm8916: Add camera thermal zone
On Wed, Sep 12, 2018 at 03:23:00PM +0530, Amit Kucheria wrote: > Initialise the camera thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 + > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 62f079ae9ba3..3dc8b8aa76c7 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 14/16] arm64: dts: msm8916: Add gpu thermal zone
On Wed, Sep 12, 2018 at 03:22:59PM +0530, Amit Kucheria wrote: > Initialise the gpu thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index be27d8dc9e6b..62f079ae9ba3 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 14/16] arm64: dts: msm8916: Add gpu thermal zone
On Wed, Sep 12, 2018 at 03:22:59PM +0530, Amit Kucheria wrote: > Initialise the gpu thermal zone to export temperature to userspace. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index be27d8dc9e6b..62f079ae9ba3 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 12/16] arm64: dts: msm8916: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:57PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Bjorn Andersson > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 6a277fce..be27d8dc9e6b 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 12/16] arm64: dts: msm8916: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:57PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Bjorn Andersson > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi > b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 6a277fce..be27d8dc9e6b 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi Acked-by: Andy Gross
Re: [PATCH v3 11/16] arm: dts: msm8974: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:56PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Reviewed-by: Bjorn Andersson > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi > b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 56dbbf788d15..3c4b81c29798 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi Acked-by: Andy Gross
Re: [PATCH v3 11/16] arm: dts: msm8974: thermal: Add "qcom,sensors" property
On Wed, Sep 12, 2018 at 03:22:56PM +0530, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > Reviewed-by: Bjorn Andersson > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi > b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 56dbbf788d15..3c4b81c29798 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi Acked-by: Andy Gross
Re: [PATCH v3 10/16] arm64: dts: msm8916: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:55PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8916 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: [PATCH v3 10/16] arm64: dts: msm8916: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:55PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8916 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: [PATCH v3 09/16] arm: dts: msm8974: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8974 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: [PATCH v3 09/16] arm: dts: msm8974: thermal: split address space into two
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8974 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria > Reviewed-by: Matthias Kaehlcke > --- Acked-by: Andy Gross
Re: Linux RDMA mini-conf at Plumbers 2018
On Thu, Sep 20, 2018 at 12:19:23PM -0600, Jason Gunthorpe wrote: > This is just a friendly reminder that registration deadlines are > approaching for this conference. Please see > > https://www.linuxplumbersconf.org/event/2/page/7-attend > > For details. > > This year we expect to have close to a day set aside for RDMA related > topics. Including up to half a day for the thorny general kernel issues > related to get_user_pages(), particularly as exasperated by RDMA. > > We have been working on the following concepts for sessions, I've > roughly marked names based on past participation in related email > threads. As we get closer to the conference date we will be organizing > leaders for each section based on these lists, please let us know of > any changes, or desire to be a leader! > > RDMA and get_user_pages > === > Dan Williams > Matthew Wilcox > John Hubbard > Nicholas Piggin > Jan Kara > > RDMA, DAX and persistant memory co-existence. > > Explore the limits of what is possible without using On > Demand Paging Memory Registration. Discuss 'shootdown' > of userspace MRs > > Dirtying pages obtained with get_user_pages() can oops ext4 > discuss open solutions. > > RDMA and PCI peer to peer > = > Don Dutile > Alex Williamson > Christoph Hellwig > Stephen Bates > Logan Gunthorpe > Jérôme Glisse > Christian König > Bjorn Helgaas > > RDMA and PCI peer to peer transactions. IOMMU issues. Integration > with HMM. How to expose PCI BAR memory to userspace and other > drivers as a DMA target. > > Improving testing of RDMA with syzkaller, RXE and Python > > Noa Osherovich > Don Dutile > Jason Gunthorpe > > Problem solve RDMA's distinct lack of public tests. > Provide a better framework for all drivers to test with, > and a framework for basic testing in userspace. > > Worst remaining unfixed syzkaller bugs and how to try to fix them > > How to hook syzkaller more deeply into RDMA. > > IOCTL conversion and new kABI topics > > Jason Gunthorpe > Alex Rosenbaum > > Attempt to close on the remaining tasks to complete the project > > Restore fork() support to userspace > > Container and namespaces for RDMA topics > > Parav Pandit > Doug Ledford > > Remaining sticky situations with containers > > namespaces in sysfs and legacy all-namespace operation > > Remaining CM issues > > Security isolation problems > > Very large Contiguous regions in userspace > == > Christopher Lameter > Parav Pandit > > Poor performance of get_user_pages on very large virtual ranges > > No standardized API to allocate regions to user space > > Carry over from last year > > As we get closer to the conference date the exact schedule will be > published on the conference web site. I belive we have the Thursday > set aside right now. > > If there are any last minute topics people would like to see please > let us know. I want to remind you that Mike wanted to bring the topic of enhancing remote page faults during post-copy container migration in CRIU over RDMA. Thanks > > See you all in Vancouver! > > Thanks, > Jason & Leon > signature.asc Description: PGP signature
Re: Linux RDMA mini-conf at Plumbers 2018
On Thu, Sep 20, 2018 at 12:19:23PM -0600, Jason Gunthorpe wrote: > This is just a friendly reminder that registration deadlines are > approaching for this conference. Please see > > https://www.linuxplumbersconf.org/event/2/page/7-attend > > For details. > > This year we expect to have close to a day set aside for RDMA related > topics. Including up to half a day for the thorny general kernel issues > related to get_user_pages(), particularly as exasperated by RDMA. > > We have been working on the following concepts for sessions, I've > roughly marked names based on past participation in related email > threads. As we get closer to the conference date we will be organizing > leaders for each section based on these lists, please let us know of > any changes, or desire to be a leader! > > RDMA and get_user_pages > === > Dan Williams > Matthew Wilcox > John Hubbard > Nicholas Piggin > Jan Kara > > RDMA, DAX and persistant memory co-existence. > > Explore the limits of what is possible without using On > Demand Paging Memory Registration. Discuss 'shootdown' > of userspace MRs > > Dirtying pages obtained with get_user_pages() can oops ext4 > discuss open solutions. > > RDMA and PCI peer to peer > = > Don Dutile > Alex Williamson > Christoph Hellwig > Stephen Bates > Logan Gunthorpe > Jérôme Glisse > Christian König > Bjorn Helgaas > > RDMA and PCI peer to peer transactions. IOMMU issues. Integration > with HMM. How to expose PCI BAR memory to userspace and other > drivers as a DMA target. > > Improving testing of RDMA with syzkaller, RXE and Python > > Noa Osherovich > Don Dutile > Jason Gunthorpe > > Problem solve RDMA's distinct lack of public tests. > Provide a better framework for all drivers to test with, > and a framework for basic testing in userspace. > > Worst remaining unfixed syzkaller bugs and how to try to fix them > > How to hook syzkaller more deeply into RDMA. > > IOCTL conversion and new kABI topics > > Jason Gunthorpe > Alex Rosenbaum > > Attempt to close on the remaining tasks to complete the project > > Restore fork() support to userspace > > Container and namespaces for RDMA topics > > Parav Pandit > Doug Ledford > > Remaining sticky situations with containers > > namespaces in sysfs and legacy all-namespace operation > > Remaining CM issues > > Security isolation problems > > Very large Contiguous regions in userspace > == > Christopher Lameter > Parav Pandit > > Poor performance of get_user_pages on very large virtual ranges > > No standardized API to allocate regions to user space > > Carry over from last year > > As we get closer to the conference date the exact schedule will be > published on the conference web site. I belive we have the Thursday > set aside right now. > > If there are any last minute topics people would like to see please > let us know. I want to remind you that Mike wanted to bring the topic of enhancing remote page faults during post-copy container migration in CRIU over RDMA. Thanks > > See you all in Vancouver! > > Thanks, > Jason & Leon > signature.asc Description: PGP signature
