Re: [PATCH v3] ARM: dts: stm32: Add DMAMUX support for STM32H743 SoC
Hi
On 09/29/2017 04:18 PM, Pierre-Yves MORDRET wrote:
This patch adds DMAMUX support for STM32H743 SoC.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
* Rebase on v4.14-rc2
v2:
* Update DTS to be compliant with up-streamed bindings
v1:
* Initial
---
---
arch/arm/boot/dts/stm32h743.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 58ec227..e8457f6 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
Applied on stm32-dt-for-v4.15 branch.
Thanks
Alex
@@ -121,6 +121,7 @@
clocks = <&timer_clk>;
#dma-cells = <4>;
st,mem2mem;
+ dma-requests = <8>;
status = "disabled";
};
@@ -138,6 +139,7 @@
clocks = <&timer_clk>;
#dma-cells = <4>;
st,mem2mem;
+ dma-requests = <8>;
status = "disabled";
};
@@ -193,6 +195,16 @@
status = "disabled";
};
};
+
+ dmamux1: dma-router@40020800 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x40020800 0x1c>;
+ #dma-cells = <3>;
+ dma-channels = <16>;
+ dma-requests = <128>;
+ dma-masters = <&dma1 &dma2>;
+ clocks = <&timer_clk>;
+ };
};
};
Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in STM32 defconfig
Hi, On 09/22/2017 09:31 AM, Pierre-Yves MORDRET wrote: This patch adds DMAMUX support in STM32 defconfig file Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET --- Version history: v5: v4: v3: v2: * None --- --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 90e5c46..988f395 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_STM32=y CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y CONFIG_IIO=y CONFIG_STM32_ADC_CORE=y CONFIG_STM32_ADC=y Applied on stm32-defconfig-for-v4.15 branch. Thanks Alex
Re: [PATCH v2 3/3] ARM: dts: stm32: add vrefbuf to stm32h743
Hi Fabrice,
On 08/30/2017 05:55 PM, Fabrice Gasnier wrote:
Add STM32H743 VREFBUF (Voltage Reference Buffer) definition.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32h743.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 36a99db..83ee8fe 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -82,6 +82,15 @@
interrupts = <50>;
clocks = <&timer_clk>;
};
+
+ vrefbuf: regulator@58003C00 {
+ compatible = "st,stm32-vrefbuf";
+ reg = <0x58003C00 0x8>;
+ clocks = <&timer_clk>;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <250>;
+ status = "disabled";
+ };
};
};
Applied on stm32-dt-for-v4.15 branch.
Thanks
Alex
Re: [PATCH v4 5/5] ARM: dts: stm32: Add I2C1 support for STM32F746 eval board
Hi
On 09/14/2017 04:28 PM, Pierre-Yves MORDRET wrote:
This patch adds I2C1 support for STM32F746 eval board
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v4:
v3:
* None
v2:
* Add SCL Rising/Falling time for eval board
---
---
arch/arm/boot/dts/stm32746g-eval.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts
b/arch/arm/boot/dts/stm32746g-eval.dts
index 69a9579..9288c7a 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
Applied on stm32-dt-for-v4.15 branch.
Thanks
Alex
@@ -102,3 +102,11 @@
pinctrl-names = "default";
status = "okay";
};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_b>;
+ pinctrl-names = "default";
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
Re: [PATCH v4 4/5] ARM: dts: stm32: Add I2C1 support for STM32F746 SoC
Hi
On 09/14/2017 04:28 PM, Pierre-Yves MORDRET wrote:
This patch adds I2C1 support for STM32F746 SoC.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v4:
v3:
* None
v2:
* Update I2C SoC device tree with latest Linux version
---
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 4506eb9..ddd8f2c 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
Applied on stm32-dt-for-v4.15 branch.
Thanks
Alex
@@ -361,6 +361,16 @@
bias-disable;
};
};
+
+ i2c1_pins_b: i2c1@0 {
+ pins {
+ pinmux = ,
+;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
};
crc: crc@40023000 {
@@ -380,6 +390,18 @@
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <100>;
};
+
+ i2c1: i2c@40005400 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+<32>;
+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+ clocks = <&rcc 1 CLK_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
Re: [PATCH] ARM: dts: stm32: add Timers driver for stm32f746 MCU
Hi Benjamin,
On 10/04/2017 11:27 AM, Benjamin Gaignard wrote:
Add Timers and it sub-nodes into DT for stm32f746 family.
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f746.dtsi | 270 +++
1 file changed, 270 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 4506eb9..ae84816 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -82,6 +82,27 @@
status = "disabled";
};
+ timers2: timers@4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4000 0x400>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
timer3: timer@4400 {
compatible = "st,stm32-timer";
reg = <0x4400 0x400>;
@@ -90,6 +111,27 @@
status = "disabled";
};
+ timers3: timers@4400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4400 0x400>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
timer4: timer@4800 {
compatible = "st,stm32-timer";
reg = <0x4800 0x400>;
@@ -98,6 +140,27 @@
status = "disabled";
};
+ timers4: timers@4800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4800 0x400>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
timer5: timer@4c00 {
compatible = "st,stm32-timer";
reg = <0x4c00 0x400>;
@@ -105,6 +168,27 @@
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
+ timers5: timers@4c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4C00 0x400>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
@@ -113,6 +197,22 @@
status = "disabled";
};
+ timers6: timers@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ clock
Re: [PATCH 0/3] Arm: dts: stm32: remove extra compatible uart string
Hi Vikas On 09/29/2017 12:51 AM, Vikas Manocha wrote: stm32 uart driver is using two compatible strings "st,stm32-usart" & "st,stm32-uart". One can be removed safely to save some space & time. Vikas Manocha (3): Arm: dts: stm32: remove extra compatible string for uart Arm: dts: stm32: remove extra compatible string from DT & driver ARM: dts: stm32h7: correct uart nodes compatible string Documentation/devicetree/bindings/dma/stm32-dma.txt | 2 +- Documentation/devicetree/bindings/serial/st,stm32-usart.txt | 10 +++--- arch/arm/boot/dts/stm32f429.dtsi| 12 ++-- arch/arm/boot/dts/stm32f746.dtsi| 12 ++-- arch/arm/boot/dts/stm32h743.dtsi| 4 ++-- drivers/tty/serial/stm32-usart.c| 3 --- 6 files changed, 18 insertions(+), 25 deletions(-) I think it is better to put people in CC of patch 1, 2, 3 also in CC of cover-letter. I think you should split patches differently. Maybe one for drivers and bindings (doc) updates. And others for DT updates. Conerning DT patches, all headers should start by "ARM: dts: stm32: blabla" Regards Alex
[PATCH] ARM: configs: stm32: Update default configuration for v4.14-rc1
Regenerate the default configuration on top of v4.14-rc1. Signed-off-by: Alexandre Torgue diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 90e5c46..3ed3158 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -18,7 +18,6 @@ CONFIG_EMBEDDED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set # CONFIG_MMU is not set -CONFIG_ARM_SINGLE_ARMV7M=y CONFIG_ARCH_STM32=y CONFIG_CPU_V7M_NUM_IRQ=240 CONFIG_SET_MEM_PARAM=y @@ -44,18 +43,17 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_UNIX98_PTYS is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_DEVKMEM is not set CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_STM32F4=y +CONFIG_GPIO_STMPE=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y -CONFIG_REGULATOR=y -CONFIG_GPIO_STMPE=y CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y @@ -81,8 +79,6 @@ CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_FTRACE is not set CONFIG_CRYPTO=y -CONFIG_CRYPTO_DEV_STM32=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y -- 2.7.4
Re: [PATCH v4 3/4] ARM: dts: stm32: Add MDMA support for STM32H743 SoC
Hi Vinod
On 09/26/2017 07:44 PM, Vinod Koul wrote:
On Fri, Aug 25, 2017 at 04:31:05PM +0200, Pierre-Yves MORDRET wrote:
This patch adds MDMA support for STM32H743 SoC.
Need ACK from ARM folks
I will take ARM patches (config + DT) in my pull request for 4.15 (if
you plan to take driver part in your PR for 4.15)
Regards
Alex
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v4:
v3:
* None
v2:
* Add MDMA support in DT for H7
---
---
arch/arm/boot/dts/stm32h743.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 36a99db..af44eae 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -82,6 +82,16 @@
interrupts = <50>;
clocks = <&timer_clk>;
};
+
+ mdma1: dma@5200 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x5200 0x1000>;
+ interrupts = <122>;
+ clocks = <&timer_clk>;
+ #dma-cells = <5>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ };
};
};
--
2.7.4
Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in STM32 defconfig
Hi Vinod On 09/26/2017 06:46 PM, Vinod Koul wrote: On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote: This patch adds DMAMUX support in STM32 defconfig file Need ACK from ARM folks on this. I will take it in my pull request. Regards Alex Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET --- Version history: v5: v4: v3: v2: * None --- --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 90e5c46..988f395 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_STM32=y CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y CONFIG_IIO=y CONFIG_STM32_ADC_CORE=y CONFIG_STM32_ADC=y -- 2.7.4
[PATCH v4] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 DT will use the common macro to define pinmux. Furthermore, it will make maintenance and integration of new SOC easier. I made only one patch to avoid dependencies. Let me know if you prefer that I split it. To check that patch generate same dtb than befrore I used dtc binary to (re)generate dts files (before and after apply the series). Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb Then diff -u stm32f469-disco-before.dts stm32f469-disco-after.dts Changes since v3: -Rewrite documentation part -Simplify macro Changes since v2: -Drop RFC tag -Add reviewers -Enhance modifications to all STM32 (F4/F7/H7) Changes since v1: -According to Vikas Manocha review, use generic macro to define port. Regards Alex Alexandre Torgue (1): ARM: dts: stm32: change pinctrl bindings definition .../bindings/pinctrl/st,stm32-pinctrl.txt | 22 +- arch/arm/boot/dts/stm32f429.dtsi | 176 +-- arch/arm/boot/dts/stm32f746.dtsi | 10 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 10 +- include/dt-bindings/pinctrl/stm32-pinfunc.h| 30 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1239 --- include/dt-bindings/pinctrl/stm32f746-pinfunc.h| 1324 include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 8 files changed, 148 insertions(+), 4275 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32h7-pinfunc.h -- 2.7.4
Re: [PATCH v3] ARM: dts: stm32: change pinctrl bindings definition
Hi Rob,
On 08/03/2017 10:21 PM, Rob Herring wrote:
On Thu, Jul 27, 2017 at 03:49:53PM +0200, Alexandre Torgue wrote:
Initially each pin was declared in "include/dt-bindings/stm32-pinfunc.h"
and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
Since this approach was approved, the number of supported MCU has
increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new
file in "include/dt-bindings" each time a new STM32 SOC arrives I propose
a new approach which consist to use a macro to define pin muxing in device
tree. All STM32 will use the common macro to define pinmux. Furthermore, it
will make STM32 maintenance and integration of new SOC easier .
Signed-off-by: Alexandre TORGUE
Reviewed-by: Vikas MANOCHA
Reviewed-by: Benjamin Gaignard
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index d907a74..567aa72 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -126,22 +126,27 @@ configuration, pullups, drive, output high/low and output
speed.
};
Required properties:
-- pinmux: integer array, represents gpio pin number and mux setting.
- Supported pin number and mux varies for different SoCs, and are defined in
- dt-bindings/pinctrl/-pinfunc.h directly.
- These defines are calculated as:
-((port * 16 + line) << 8) | function
+- pinmux: integer array, represents gpio pin number and mux setting. Use
+ following macro: STM32_PINMUX(PIN_NO(port_name, line), mode) to declare it.
I would keep the above formula. It can't change because that is the ABI.
The macro is just convenience.
Is there any reason to have 2 macros? I'd just do STM32_PINMUX(port,
line, mode) and make port names defines (PA, PB, PC, etc.).
No. It has been done in this way to simplify macro definition, but it
could be done in another way. I can try to create a macro like you
propose: STM32_PINMUX(port, line, mode) if you think it is more readable.
+
With:
-- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
-- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
-- function: The function number, can be:
- * 0 : GPIO
- * 1 : Alternate Function 0
- * 2 : Alternate Function 1
- * 3 : Alternate Function 2
+- port_name: The gpio port name ('A', 'B', ..., 'K')
+- line: The line offset within the port (0, 1, ..., 15)
+- mode: The mode can be:
+ * GPIO
+ * AF0 : Alternate Function 0
+ * AF1 : Alternate Function 1
+ * AF2 : Alternate Function 2
* ...
- * 16 : Alternate Function 15
- * 17 : Analog
+ * AF15 : Alternate Function 15
+ * ANALOG
Here too, keeping the numbers is important.
Perhaps the macro description should either be its own additional
section or document it inline with the macro definition.
I agree. I can keep previous definition like it was done, and add a
section only for the new macro.
Thanks for your review.
Alex
Overall, it does seem like a nice shrinking of the header files.
+
+ Example:
+To declare pin PA7 in mode "alternate function 7" you have to
+declare:
+ pinmux = ;
+
+ This macro is defined in dt-bindings/pinctrl/stm32-pinfunc.h
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
@@ -165,13 +170,13 @@ pin-controller {
...
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ; /*
USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = ;
+ pinmux = ; /*
USART1_RX */
bias-disable;
};
};
Re: [RESEND PATCH] ARM: dts: stm32: Add DMA support for STM32H743 SoC
Hi,
On 07/11/2017 08:56 AM, Pierre-Yves MORDRET wrote:
This patch adds DMA support for STM32H743 SoC.
Signed-off-by: Pierre-Yves MORDRET
---
arch/arm/boot/dts/stm32h743.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 4685629..3d1cd88 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -74,6 +74,38 @@
interrupts = <50>;
clocks = <&timer_clk>;
};
+
+ dma1: dma@4002 {
+ compatible = "st,stm32-dma";
+ reg = <0x4002 0x400>;
+ interrupts = <11>,
+<12>,
+<13>,
+<14>,
+<15>,
+<16>,
+<17>,
+<47>;
+ clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
+
+ dma2: dma@40020400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020400 0x400>;
+ interrupts = <56>,
+<57>,
+<58>,
+<59>,
+<60>,
+<68>,
+<69>,
+<70>;
+ clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
};
};
Applied on stm32-dt-for-v4.14 branch.
However, I prefer to keep DMA nodes disabled.
Indeed on cortex-M7, dma allocations have to be done in a
"strongly-ordered" area. So If you want to use DMA you need to create in
your device tree a "reserved memory" area like that:
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xd1c0 0x40>;
+ };
+ };
In the same time, you have to configure in the same way the cortex-m7
MPU in your bootloader.
FYI, patches are under review to configure MPU directly in the kernel
(bootloader will not longer have to configure it). It seems also that
discussions are ongoing about the way to declare "linux,dma" area in
devicetree.
As soon all discussions will close and MPU patches applied, we will be
able to enable DMA.
Regards
Alex
Re: [RESEND PATCH] ARM: dts: stm32: Add DMA support for STM32F746 SoC
Hi Pierre-Yves,
On 07/11/2017 08:54 AM, Pierre-Yves MORDRET wrote:
This patch adds DMA support for STM32F746 SoC.
Signed-off-by: Pierre-Yves MORDRET
---
arch/arm/boot/dts/stm32f746.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index c2765ce..bfffea4 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -344,6 +344,37 @@
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <100>;
};
+
+ dma1: dma@40026000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026000 0x400>;
+ interrupts = <11>,
+<12>,
+<13>,
+<14>,
+<15>,
+<16>,
+<17>,
+<47>;
+ clocks = <&rcc 0 21>;
+ #dma-cells = <4>;
+ };
+
+ dma2: dma@40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+<57>,
+<58>,
+<59>,
+<60>,
+<68>,
+<69>,
+<70>;
+ clocks = <&rcc 0 22>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
};
};
Applied on stm32-dt-for-v4.14 branch.
However, I prefer to keep DMA nodes disabled.
Indeed on cortex-M7, dma allocations have to be done in a
"strongly-ordered" area. So If you want to use DMA you need to create in
your device tree a "reserved memory" area like that:
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xd1c0 0x40>;
+ };
+ };
In the same time, you have to configure in the same way the cortex-m7
MPU in your bootloader.
FYI, patches are under review to configure MPU directly in the kernel
(bootloader will not longer have to configure it). It seems also that
discussions are ongoing about the way to declare "linux,dma" area in
devicetree.
As soon all discussions will close and MPU patches applied, we will be
able to enable DMA.
Regards
Alex
[PATCH v3] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 DT will use the common macro to define pinmux. Furthermore, it will make maintenance and integration of new SOC easier. I made only one patch to avoid dependencies. Let me know if you prefer that I split it. To check that patch generate same dtb than befrore I used dtc binary to (re)generate dts files (before and after apply the series). Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb Then diff -u stm32f469-disco-before.dts stm32f469-disco-after.dts Changes since v2: -Drop RFC tag -Add reviewers -Enhance modifications to all STM32 (F4/F7/H7) Changes since v1: -According to Vikas Manocha review, use generic macro to define port. Regards Alex Alexandre Torgue (1): ARM: dts: stm32: change pinctrl bindings definition .../bindings/pinctrl/st,stm32-pinctrl.txt | 37 +- arch/arm/boot/dts/stm32f429.dtsi | 176 +-- arch/arm/boot/dts/stm32f746.dtsi | 10 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 10 +- include/dt-bindings/pinctrl/stm32-pinfunc.h| 31 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1239 --- include/dt-bindings/pinctrl/stm32f746-pinfunc.h| 1324 include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 8 files changed, 150 insertions(+), 4289 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32h7-pinfunc.h -- 2.7.4
Re: [PATCH 4/4] ARM: dts: stm32: Add DAC support on stm32f429
Hi,
On 07/10/2017 03:24 PM, Fabrice Gasnier wrote:
Add support for DAC (Digital to Analog Converter) to STM32F429.
STM32F429 DAC has two output channels.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32f429.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..f15f633 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -354,6 +354,31 @@
status = "disabled";
};
+ dac: dac@40007400 {
+ compatible = "st,stm32f4-dac-core";
+ reg = <0x40007400 0x400>;
+ resets = <&rcc STM32F4_APB1_RESET(DAC)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
usart7: serial@40007800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40007800 0x400>;
Applied on stm32-dt-for-v4.14 branch.
Thanks
Alex
Re: [PATCH 0/2] Enable ADC support on STM32H7
Hi Fabrice, On 07/11/2017 06:13 PM, Fabrice Gasnier wrote: This patchset adds ADC device-tree nodes to STM32H7 SoC and enables ADC1 by default on stm32h743i-eval board. Fabrice Gasnier (2): ARM: dts: stm32: add ADC support on stm32h7 ARM: dts: stm32: enable ADC on stm32h743i-eval board arch/arm/boot/dts/stm32h743.dtsi | 53 +++ arch/arm/boot/dts/stm32h743i-eval.dts | 18 2 files changed, 71 insertions(+) Series applied on stm32-dt-for-v4.14 branch. Thanks Alex
Re: [PATCH] ARM: dts: stm32: Add DAC support on stm32h7
Hi Fabrice
On 07/10/2017 01:59 PM, Fabrice Gasnier wrote:
Add support for DAC (Digital to Analog Converter) to STM32H7.
STM32H7 DAC has two output channels.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32h743.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 4685629..d0b28c5 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -74,6 +74,30 @@
interrupts = <50>;
clocks = <&timer_clk>;
};
+
+ dac: dac@40007400 {
+ compatible = "st,stm32h7-dac-core";
+ reg = <0x40007400 0x400>;
+ clocks = <&timer_clk>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
};
};
Applied on stm32-dt-for-v4.14 branch.
Thanks
Alex
Re: [PATCH 2/2] arm: dts: stm32: enable cec for stm32f769 discovery
Hi Benjamin,
On 07/18/2017 10:22 AM, Benjamin Gaignard wrote:
enable cec for stm32f769 discovery board
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f769-disco.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts
b/arch/arm/boot/dts/stm32f769-disco.dts
index 166728a..14e54da 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -72,3 +72,9 @@
pinctrl-names = "default";
status = "okay";
};
+
+&cec {
+ pinctrl-0 = <&cec_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
After minor changes, applied on stm32-dt-for-v4.14 branch.
Thanks
Alex
Re: [PATCH 1/2] arm: dts: stm32: add cec for stm32f7 familly
Hi Benjamin,
On 07/18/2017 10:51 AM, Benjamin Gaignard wrote:
add cec in devicetree for stm32f7 familly
version 1.1:
- with correct slew rate
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f746.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 0c3dd1f..770e474 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -167,6 +167,15 @@
status = "disabled";
};
+ cec: cec@40006c00 {
+ compatible = "st,stm32-cec";
+ reg = <0x40006C00 0x400>;
+ interrupts = <94>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1
CLK_HDMI_CEC>;
+ clock-names = "cec", "hdmi-cec";
+ status = "disabled";
+ };
+
usart7: serial@40007800 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007800 0x400>;
@@ -339,6 +348,15 @@
st,bank-name = "GPIOK";
};
+ cec_pins_a: cec@0 {
+ pins {
+ pinmux = ;
+ slew-rate = <0>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
usart1_pins_a: usart1@0 {
pins1 {
pinmux = ;
After minor changes, applied on stm32-dt-for-v4.14 branch.
Thanks
Alex
[RFC PATCH v2] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 DT will use the common macro to define pinmux. Furthermore, it will make maintenance and integration of new SOC easier. To check that patch generate same dtb than befrore I used dtc binary to (re)generate dts files (before and after apply the series). Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb Then diff -u stm32f469-disco-before.dts stm32f469-disco-after.dts Changes since v1: -According to Vikas Manocha review, use generic macro to define port. Regards Alex Alexandre Torgue (1): ARM: dts: stm32: change pinctrl bindings definition arch/arm/boot/dts/stm32f429.dtsi| 176 ++-- include/dt-bindings/pinctrl/stm32-pinfunc.h | 31 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 --- 3 files changed, 119 insertions(+), 1327 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 2.7.4
[RFC PATCH v2] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h"
and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
Since this approach was approved, the number of supported MCU has
increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new
file in "include/dt-bindings" each time a new STM32 SOC arrives I propose
a new approach which consist to use a macro to define pin muxing in device
tree. All STM32 will use the common macro to define pinmux. Furthermore, it
will make maintenance and integration of new SOC easier .
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index a8113dc..e9e46ee 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
#include
#include
@@ -687,35 +687,35 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ; /* USART1_RX */
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
- pinmux =
;
+ pinmux = ; /* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ; /* USART3_RX */
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = , /* OTG_FS_ID */
+, /* OTG_FS_DM */
+; /* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -724,9 +724,9 @@
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = , /* OTG_HS_ID */
+, /* OTG_HS_DM */
+; /* OTG_HS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -735,18 +735,18 @@
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux = , /* OTG_HS_ULPI_NXT*/
+, /* OTG_HS_ULPI_DIR */
+, /* OTG_HS_ULPI_STP */
+, /* OTG_HS_ULPI_CK */
+, /* OTG_HS_ULPI_D0 */
+, /* OTG_HS_ULPI_D1 */
+, /* OTG_HS_ULPI_D2 */
+, /* OTG_HS_ULPI_D3 */
+
Re: [PATCH] irqchip: Convert to using %pOF instead of full_name
On 07/18/2017 11:43 PM, Rob Herring wrote:
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Lee Jones
Cc: Eric Anholt
Cc: Stefan Wahren
Cc: Florian Fainelli
Cc: Ray Jui
Cc: Scott Branden
Cc: bcm-kernel-feedback-l...@broadcom.com
Cc: Baruch Siach
Cc: Vladimir Zapolskiy
Cc: Sylvain Lemieux
Cc: Matthias Brugger
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Michal Simek
Cc: "Sören Brinkmann"
Cc: linux-rpi-ker...@lists.infradead.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-media...@lists.infradead.org
Cc: linux-te...@vger.kernel.org
---
drivers/irqchip/irq-bcm2835.c| 9 -
drivers/irqchip/irq-bcm2836.c| 5 ++---
drivers/irqchip/irq-crossbar.c | 6 +++---
drivers/irqchip/irq-digicolor.c | 8
drivers/irqchip/irq-dw-apb-ictl.c| 12 ++--
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 2 +-
drivers/irqchip/irq-gic-v3-its.c | 6 +++---
drivers/irqchip/irq-gic-v3.c | 11 ---
drivers/irqchip/irq-imx-gpcv2.c | 4 ++--
drivers/irqchip/irq-lpc32xx.c| 2 +-
drivers/irqchip/irq-mtk-sysirq.c | 3 +--
drivers/irqchip/irq-mxs.c| 4 ++--
drivers/irqchip/irq-stm32-exti.c | 8
drivers/irqchip/irq-sun4i.c | 6 +++---
drivers/irqchip/irq-tegra.c | 16
drivers/irqchip/irq-xilinx-intc.c| 4 ++--
16 files changed, 50 insertions(+), 56 deletions(-)
For irq-stm32-exti.c:
Acked-by: Alexandre TORGUE
Regards
Alex
diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
index 44d7c38dde47..d2da8a1e6b1b 100644
--- a/drivers/irqchip/irq-bcm2835.c
+++ b/drivers/irqchip/irq-bcm2835.c
@@ -147,13 +147,12 @@ static int __init armctrl_of_init(struct device_node
*node,
base = of_iomap(node, 0);
if (!base)
- panic("%s: unable to map IC registers\n",
- node->full_name);
+ panic("%pOF: unable to map IC registers\n", node);
intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
&armctrl_ops, NULL);
if (!intc.domain)
- panic("%s: unable to create IRQ domain\n", node->full_name);
+ panic("%pOF: unable to create IRQ domain\n", node);
for (b = 0; b < NR_BANKS; b++) {
intc.pending[b] = base + reg_pending[b];
@@ -173,8 +172,8 @@ static int __init armctrl_of_init(struct device_node *node,
int parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq) {
- panic("%s: unable to get parent interrupt.\n",
- node->full_name);
+ panic("%pOF: unable to get parent interrupt.\n",
+ node);
}
irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
} else {
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index e7463e3c0814..dc8c1e3eafe7 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -282,8 +282,7 @@ static int __init
bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
{
intc.base = of_iomap(node, 0);
if (!intc.base) {
- panic("%s: unable to map local interrupt registers\n",
- node->full_name);
+ panic("%pOF: unable to map local interrupt registers\n", node);
}
bcm2835_init_local_timer_frequency();
@@ -292,7 +291,7 @@ static int __init
bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
&bcm2836_arm_irqchip_intc_ops,
NULL);
if (!intc.domain)
- panic("%s: unable to create IRQ domain\n", node->full_name);
+ panic("%pOF: unable to create IRQ domain\n", node);
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
&bcm2836_arm_irqchip_timer);
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index f96601268f71..99d97d7e3fd7 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -341,13 +341,13 @@ static int __init irqcrossbar_init(struct device_node
*node,
int err;
if (!parent) {
- pr_err("%s: no parent, giving up\n", node->full_name);
+ pr_err(&q
Re: [PATCH] clk: Convert to using %pOF instead of full_name
On 07/18/2017 11:42 PM, Rob Herring wrote:
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Cc: Russell King
Cc: Matthias Brugger
Cc: Geert Uytterhoeven
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: "Emilio López"
Cc: Peter De Schrijver
Cc: Prashant Gaikwad
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Tero Kristo
Cc: linux-...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-media...@lists.infradead.org
Cc: linux-renesas-...@vger.kernel.org
Cc: linux-te...@vger.kernel.org
Cc: linux-o...@vger.kernel.org
---
drivers/clk/berlin/bg2.c | 3 +--
drivers/clk/berlin/bg2q.c| 7 +++
drivers/clk/clk-asm9260.c| 4 ++--
drivers/clk/clk-conf.c | 16
drivers/clk/clk-moxart.c | 12 ++--
drivers/clk/clk-qoriq.c | 7 +++
drivers/clk/clk-stm32f4.c| 4 ++--
drivers/clk/clk-xgene.c | 15 ++-
drivers/clk/clk.c| 4 ++--
drivers/clk/clkdev.c | 4 ++--
drivers/clk/mediatek/clk-cpumux.c| 2 +-
drivers/clk/mediatek/clk-mtk.c | 2 +-
drivers/clk/mediatek/reset.c | 2 +-
drivers/clk/renesas/clk-mstp.c | 2 +-
drivers/clk/renesas/clk-rcar-gen2.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun5i.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 3 +--
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +--
drivers/clk/sunxi/clk-sunxi.c| 17 +++--
drivers/clk/tegra/clk-emc.c | 12 +---
drivers/clk/ti/clockdomain.c | 4 ++--
25 files changed, 61 insertions(+), 80 deletions(-)
For clk/clk-stm32f4.c
Acked-by: Alexandre TORGUE
Regards
Alex
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index 1d99292e2039..e7331ace0337 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -679,8 +679,7 @@ static void __init berlin2_clock_setup(struct device_node
*np)
if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2_fail;
}
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 3b784b593afd..67c270b143f7 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -304,14 +304,14 @@ static void __init berlin2q_clock_setup(struct
device_node *np)
gbase = of_iomap(parent_np, 0);
if (!gbase) {
- pr_err("%s: Unable to map global base\n", np->full_name);
+ pr_err("%pOF: Unable to map global base\n", np);
return;
}
/* BG2Q CPU PLL is not part of global registers */
cpupll_base = of_iomap(parent_np, 1);
if (!cpupll_base) {
- pr_err("%s: Unable to map cpupll base\n", np->full_name);
+ pr_err("%pOF: Unable to map cpupll base\n", np);
iounmap(gbase);
return;
}
@@ -376,8 +376,7 @@ static void __init berlin2q_clock_setup(struct device_node
*np)
if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2q_fail;
}
diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c
index ea8568536193..bf0582cbbf38 100644
--- a/drivers/clk/clk-asm9260.c
+++ b/drivers/clk/clk-asm9260.c
@@ -338,8 +338,8 @@ static void __init asm9260_acc_init(struct device_node *np)
if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n",
+ np, n);
goto fail;
}
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 7ec36722f8ab..49819b546134 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -23,8 +23,8 @@ static int __set_clk_parents(struct device_node *node, bool
clk_supplier)
num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
Re: [PATCH] clocksource: Convert to using %pOF instead of full_name
Hi Rob,
On 07/18/2017 11:42 PM, Rob Herring wrote:
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Marc Gonzalez
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Cc: linux-arm-ker...@lists.infradead.org
---
drivers/clocksource/tango_xtal.c | 6 +++---
drivers/clocksource/timer-of.c| 11 +--
drivers/clocksource/timer-probe.c | 3 +--
drivers/clocksource/timer-stm32.c | 8
4 files changed, 13 insertions(+), 15 deletions(-)
For timer-stm32:
Acked-by: Alexandre TORGUE
regards
Alex
diff --git a/drivers/clocksource/tango_xtal.c b/drivers/clocksource/tango_xtal.c
index c4e1c2e6046f..6a8d9838ce33 100644
--- a/drivers/clocksource/tango_xtal.c
+++ b/drivers/clocksource/tango_xtal.c
@@ -26,13 +26,13 @@ static int __init tango_clocksource_init(struct device_node
*np)
xtal_in_cnt = of_iomap(np, 0);
if (xtal_in_cnt == NULL) {
- pr_err("%s: invalid address\n", np->full_name);
+ pr_err("%pOF: invalid address\n", np);
return -ENXIO;
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
- pr_err("%s: invalid clock\n", np->full_name);
+ pr_err("%pOF: invalid clock\n", np);
return PTR_ERR(clk);
}
@@ -43,7 +43,7 @@ static int __init tango_clocksource_init(struct device_node
*np)
ret = clocksource_mmio_init(xtal_in_cnt, "tango-xtal", xtal_freq, 350,
32, clocksource_mmio_readl_up);
if (ret) {
- pr_err("%s: registration failed\n", np->full_name);
+ pr_err("%pOF: registration failed\n", np);
return ret;
}
diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c
index f6e7491c873c..a07b923d3d6e 100644
--- a/drivers/clocksource/timer-of.c
+++ b/drivers/clocksource/timer-of.c
@@ -44,7 +44,7 @@ static __init int timer_irq_init(struct device_node *np,
of_irq->irq = of_irq->name ? of_irq_get_byname(np, of_irq->name):
irq_of_parse_and_map(np, of_irq->index);
if (!of_irq->irq) {
- pr_err("Failed to map interrupt for %s\n", np->full_name);
+ pr_err("Failed to map interrupt for %pOF\n", np);
return -EINVAL;
}
@@ -55,8 +55,7 @@ static __init int timer_irq_init(struct device_node *np,
of_irq->flags ? of_irq->flags : IRQF_TIMER,
np->full_name, clkevt);
if (ret) {
- pr_err("Failed to request irq %d for %s\n", of_irq->irq,
- np->full_name);
+ pr_err("Failed to request irq %d for %pOF\n", of_irq->irq, np);
return ret;
}
@@ -80,20 +79,20 @@ static __init int timer_clk_init(struct device_node *np,
of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) :
of_clk_get(np, of_clk->index);
if (IS_ERR(of_clk->clk)) {
- pr_err("Failed to get clock for %s\n", np->full_name);
+ pr_err("Failed to get clock for %pOF\n", np);
return PTR_ERR(of_clk->clk);
}
ret = clk_prepare_enable(of_clk->clk);
if (ret) {
- pr_err("Failed for enable clock for %s\n", np->full_name);
+ pr_err("Failed for enable clock for %pOF\n", np);
goto out_clk_put;
}
of_clk->rate = clk_get_rate(of_clk->clk);
if (!of_clk->rate) {
ret = -EINVAL;
- pr_err("Failed to get clock rate for %s\n", np->full_name);
+ pr_err("Failed to get clock rate for %pOF\n", np);
goto out_clk_disable;
}
diff --git a/drivers/clocksource/timer-probe.c
b/drivers/clocksource/timer-probe.c
index da81e5de74fe..028075720334 100644
--- a/drivers/clocksource/timer-probe.c
+++ b/drivers/clocksource/timer-probe.c
@@ -40,8 +40,7 @@ void __init timer_probe(void)
ret = init_func_ret(np);
if (ret) {
- pr_err("Failed to initialize '%s': %d\n",
- of_node_full_name(np), ret);
+ pr_err("Failed to initialize '%pOF': %d\n", np, ret);
continue;
}
diff --git a/drivers/clocksource/timer-stm32.c
b/drivers/clocksource/timer-stm32.c
index 174d1243ea93..8f2423789ba9 100644
--- a/drivers/clocksource/timer-stm32.c
+++ b/drivers/clocksource/timer-stm32.c
@@
Re: [RESEND RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
Hi Vikas
On 07/17/2017 10:42 PM, Vikas Manocha wrote:
Hi Alex,
On 07/17/2017 09:23 AM, Alexandre Torgue wrote:
From: Alexandre TORGUE
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h"
and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
Since this approach was approved, the number of supported MCU has
increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new
file in "include/dt-bindings" each time a new STM32 SOC arrives I propose
a new approach which consist to use a macro to define pin muxing in device
tree. All STM32 will use the common macro to define pinmux. Furthermore, it
will make easy maintenance and integration of new SOC.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index a8113dc..4bb2b4f 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
#include
#include
@@ -687,35 +687,35 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ; /*
USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART1_RX */
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
- pinmux =
;
+ pinmux = ;
/* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART3_RX */
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_FS_ID */
+,
/* OTG_FS_DM */
+;
/* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -724,9 +724,9 @@
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ID */
+,
/* OTG_HS_DM */
+;
/* OTG_HS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -735,18 +735,18 @@
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ULPI_NXT*/
+,
/* OTG_HS_ULPI_DIR */
+,
/* OTG_HS_ULPI_STP */
+,
/* OTG_HS_ULPI_CK */
+,
/* OTG_HS_ULPI_D0 */
+,
/* OTG_HS_ULPI_D1 */
+,
/* OTG_HS_ULPI_D2 */
+
[RESEND RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 DT will use the common macro to define pinmux. Furthermore, it will make easy maintenance and integration of new SOC. To check that patch generate same dtb than befrore I used dtc binary to (re)generate dts files (before and after apply the series). Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb Then diff -u stm32f469-disco-before.dts stm32f469-disco-after.dts Regards Alex Alexandre TORGUE (1): ARM: dts: stm32: change pinctrl bindings definition arch/arm/boot/dts/stm32f429.dtsi| 176 ++-- include/dt-bindings/pinctrl/stm32-pinfunc.h | 61 ++ include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 --- 3 files changed, 149 insertions(+), 1327 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1
[RESEND RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
From: Alexandre TORGUE
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h"
and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
Since this approach was approved, the number of supported MCU has
increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new
file in "include/dt-bindings" each time a new STM32 SOC arrives I propose
a new approach which consist to use a macro to define pin muxing in device
tree. All STM32 will use the common macro to define pinmux. Furthermore, it
will make easy maintenance and integration of new SOC.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index a8113dc..4bb2b4f 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
#include
#include
@@ -687,35 +687,35 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ; /*
USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART1_RX */
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
- pinmux =
;
+ pinmux = ;
/* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART3_RX */
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_FS_ID */
+,
/* OTG_FS_DM */
+;
/* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -724,9 +724,9 @@
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ID */
+,
/* OTG_HS_DM */
+;
/* OTG_HS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -735,18 +735,18 @@
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ULPI_NXT*/
+,
/* OTG_HS_ULPI_DIR */
+,
/* OTG_HS_ULPI_STP */
+,
/* OTG_HS_ULPI_CK */
+,
/* OTG_HS_ULPI_D0 */
+,
/* OTG_HS_ULPI_D1 */
+,
/* OTG_HS_ULPI_D2 */
+
Re: [RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
Hi On 07/17/2017 01:15 PM, Arnd Bergmann wrote: On Mon, Jul 17, 2017 at 1:00 PM, Alexandre TORGUE wrote: blabla Signed-off-by: Alexandre TORGUE You may want to provide a little more detail here ;-) Oh!! Sorry, I changed it but no sent the good commit :). Please translate blablable by: Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h"and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 will use the common macro to define pinmux. Furthermore, it will make easy maintenance and integration of new SOC. Regards Alex Arnd
[RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
blabla
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index a8113dc..4bb2b4f 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
#include
#include
@@ -687,35 +687,35 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ; /*
USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART1_RX */
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
- pinmux =
;
+ pinmux = ;
/* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
/* USART3_RX */
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_FS_ID */
+,
/* OTG_FS_DM */
+;
/* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -724,9 +724,9 @@
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
- pinmux =
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ID */
+,
/* OTG_HS_DM */
+;
/* OTG_HS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -735,18 +735,18 @@
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux = ,
/* OTG_HS_ULPI_NXT*/
+,
/* OTG_HS_ULPI_DIR */
+,
/* OTG_HS_ULPI_STP */
+,
/* OTG_HS_ULPI_CK */
+,
/* OTG_HS_ULPI_D0 */
+,
/* OTG_HS_ULPI_D1 */
+,
/* OTG_HS_ULPI_D2 */
+,
/* OTG_HS_ULPI_D3 */
+,
/* OTG_HS_ULPI_D4 */
+,
/* OTG_HS_ULPI_D5 */
+,
/* OTG_HS_ULPI_D6 */
+;
/* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -755,49 +755,49 @@
ethernet_mii: mii@0 {
pin
[RFC PATCH] ARM: dts: stm32: change pinctrl bindings definition
Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 DT will use the common macro to define pinmux. Furthermore, it will make easy maintenance and integration of new SOC. To check that patch generate same dtb than befrore I used dtc binary to (re)generate dts files (before and after apply the series). Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb Then diff -u stm32f469-disco-before.dts stm32f469-disco-after.dts Regards Alex Alexandre TORGUE (1): ARM: dts: stm32: change pinctrl bindings definition arch/arm/boot/dts/stm32f429.dtsi| 176 ++-- include/dt-bindings/pinctrl/stm32-pinfunc.h | 61 ++ include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 --- 3 files changed, 149 insertions(+), 1327 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1
Re: [PATCH 1/2] pinctrl: stm32: select IRQ_DOMAIN_HIERARCHY instead of depends on
Hi, On 07/12/2017 01:11 AM, Masahiro Yamada wrote: Drivers that need IRQ_DOMAIN_HIERARCHY should "select" it, but drivers/pinctrl/stm32/Kconfig is the only exception that uses "depends on" syntax. This prevents GPIO drivers from select'ing IRQ_DOMAIN_HIERARCHY. For example, if I add "select IRQ_DOMAIN_HIERARCHY" to GPIO_XGENE_SB, I get the following recursive dependency error. drivers/gpio/Kconfig:13:error: recursive dependency detected! For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:13:symbol GPIOLIB is selected by PINCTRL_STM32 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:3:symbol PINCTRL_STM32 is selected by PINCTRL_STM32F429 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:11: symbol PINCTRL_STM32F429 depends on IRQ_DOMAIN_HIERARCHY For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" kernel/irq/Kconfig:67: symbol IRQ_DOMAIN_HIERARCHY is selected by GPIO_XGENE_SB For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:502: symbol GPIO_XGENE_SB depends on GPIOLIB Signed-off-by: Masahiro Yamada Thanks for the patch. Tested-by: Alexandre TORGUE regards Alex drivers/pinctrl/stm32/Kconfig | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index 3b8026fca057..7e1fe39a56a5 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -6,29 +6,30 @@ config PINCTRL_STM32 select PINMUX select GENERIC_PINCONF select GPIOLIB + select IRQ_DOMAIN_HIERARCHY select MFD_SYSCON config PINCTRL_STM32F429 bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 - depends on OF && IRQ_DOMAIN_HIERARCHY + depends on OF default MACH_STM32F429 select PINCTRL_STM32 config PINCTRL_STM32F469 bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST && !MACH_STM32F469 - depends on OF && IRQ_DOMAIN_HIERARCHY + depends on OF default MACH_STM32F469 select PINCTRL_STM32 config PINCTRL_STM32F746 bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746 - depends on OF && IRQ_DOMAIN_HIERARCHY + depends on OF default MACH_STM32F746 select PINCTRL_STM32 config PINCTRL_STM32H743 bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743 - depends on OF && IRQ_DOMAIN_HIERARCHY + depends on OF default MACH_STM32H743 select PINCTRL_STM32 endif
Re: [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl
Hi Ludovic
On 07/07/2017 09:26 AM, Ludovic Barre wrote:
From: Ludovic Barre
Signed-off-by: Ludovic Barre
---
Can you fill commit message please
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index fcc1e06..8854d26 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x5802 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@5802 {
@@ -57,6 +59,8 @@
reg = <0x0 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
reg = <0x400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
reg = <0x800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
usart1_pins: usart1@0 {
Re: [PATCH 00/20] Update STM32 usart driver
Greg, Rob On 06/26/2017 02:49 PM, Bich HEMON wrote: From: Bich Hemon This patchset updates the stm32 usart driver. It mainly adds support for fifo, dma, debugfs anf fixes various bugs. Bich Hemon (20): serial: stm32: adding fifo support dt-bindings: serial: each stm32 usart needs an alias serial: stm32: fix multi ports management serial: stm32: make fifoen as property for each port serial: stm32: add debugfs serial: stm32: fix pio transmit timeout serial: stm32: less messages on dma alloc error serial: stm32: timeout interrupt using with dma serial: stm32: fix end of transfer serial: stm32: fix dma receive serial: stm32: add RTS support serial: stm32: fix last_res value serial: stm32: fix error handling in probe dt-bindings: serial: document option wake-up interrupt for STM32 USART serial: stm32: Add wakeup mechanism serial: stm32: fix fifo usage dt-bindings: serial: stm32: add dma using note serial: stm32: update dma buffers length serial: stm32: add dma rx callback serial: stm32: fix rx interrupt handling in startup .../devicetree/bindings/serial/st,stm32-usart.txt | 55 +++- drivers/tty/serial/stm32-usart.c | 310 ++--- drivers/tty/serial/stm32-usart.h | 51 +++- 3 files changed, 375 insertions(+), 41 deletions(-) This series have been abandoned (maybe not in correct way). Don't waste your time with that. New patches will be sent in several series and patches will be reworked. Thanks Alex
Re: [PATCH v3] ARM: dts: stm32f7: add stm32f769I & stm32f746 discovery board support
Hi Vikas On 04/13/2017 02:27 AM, Vikas Manocha wrote: Stm32f769I & stm32f746 are MCUs of stm32f7 family. Here are the major specs of the two boards: stm32f769I discovery board: - Cortex-M7 core @216MHz - 2MB mcu internal flash - 512KB internal sram - 16MB sdram memory - 64MB qspi flash memory - 4 inch wvga LCD-TFT Display stm32f746 discovery board: - Cortex-M7 core @216MHz - 1MB mcu internal flash - 320KB internal sram - 8MB sdram memory - 16MB qspi flash memory - 4.3 inch 480x272 LCD-TFT display Signed-off-by: Vikas Manocha --- Changed in v3: - fixed usart pin muxing for stm32f746 board, correct one is usart1_pins_pa9_pb7. - Added patch version in the patch title, was missed in v2. Changed in v2: - moved pin muxing from board dts file to soc dtsi arch/arm/boot/dts/Makefile| 2 + arch/arm/boot/dts/stm32f746-disco.dts | 74 +++ arch/arm/boot/dts/stm32f746.dtsi | 12 ++ arch/arm/boot/dts/stm32f769-disco.dts | 74 +++ 4 files changed, 162 insertions(+) create mode 100644 arch/arm/boot/dts/stm32f746-disco.dts create mode 100644 arch/arm/boot/dts/stm32f769-disco.dts ... Applied on stm32-dt-for-v4.13. Regards Alex
Re: [PATCH v5 0/5] STM32 Independent watchdog
Hi Yannick On 04/06/2017 02:19 PM, Yannick Fertre wrote: Version 5: - Update bindings (add field timeout-sec) - Update driver (rework start, rework settings & remove max_timeout) Version 4: - Update bindings (iwdg > watchdog) - Update typo - Update commit header - remove gerrit tags - Update driver (remove unnecessary tests) a add watchdog_init_timeout Version 3: - Update typo into bindings file - Reorder node in devicetree (ordering by address) - Remove unnecessary lines in commits Version 2: - Add commit messages Version 1: - Initial commit The purpose of this set of patches is to add a new watchdog driver for stm32f429. This driver was developed and tested on evaluation board stm32429i. Yannick Fertre (5): dt-bindings: watchdog: Document STM32 IWDG bindings drivers: watchdog: Add STM32 IWDG driver ARM: dts: stm32: Add watchdog support for STM32F429 SoC ARM: dts: stm32: Add watchdog support for STM32F429 eval board ARM: configs: stm32: Add watchdog support in STM32 defconfig .../devicetree/bindings/watchdog/st,stm32-iwdg.txt | 19 ++ arch/arm/boot/dts/stm32429i-eval.dts | 5 + arch/arm/boot/dts/stm32f429.dtsi | 9 +- arch/arm/configs/stm32_defconfig | 1 + drivers/watchdog/Kconfig | 12 + drivers/watchdog/Makefile | 1 + drivers/watchdog/stm32_iwdg.c | 253 + 7 files changed, 299 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt create mode 100644 drivers/watchdog/stm32_iwdg.c Patches 3&4 applied on stm32-dt-for-v4.13 Patch 5 applied on stm32-defconfig-for-v4.13 regards Alex
Re: [PATCH v5 0/8] Add support for DCMI camera interface of STMicroelectronics STM32 SoC series
Hi Hugues On 05/05/2017 05:31 PM, Hugues Fruchet wrote: This patchset introduces a basic support for Digital Camera Memory Interface (DCMI) of STMicroelectronics STM32 SoC series. This first basic support implements RGB565 & YUV frame grabbing. Cropping and JPEG support will be added later on. This has been tested on STM324x9I-EVAL evaluation board embedding an OV2640 camera sensor. . Hugues Fruchet (8): dt-bindings: Document STM32 DCMI bindings [media] stm32-dcmi: STM32 DCMI camera interface driver ARM: dts: stm32: Enable DCMI support on STM32F429 MCU ARM: dts: stm32: Enable DCMI camera interface on STM32F429-EVAL board ARM: dts: stm32: Enable STMPE1600 gpio expander of STM32F429-EVAL board ARM: dts: stm32: Enable OV2640 camera support of STM32F429-EVAL board ARM: configs: stm32: STMPE1600 GPIO expander ARM: configs: stm32: DCMI + OV2640 camera support .../devicetree/bindings/media/st,stm32-dcmi.txt| 46 + arch/arm/boot/dts/stm32429i-eval.dts | 56 + arch/arm/boot/dts/stm32f429.dtsi | 37 + arch/arm/configs/stm32_defconfig |9 + drivers/media/platform/Kconfig | 12 + drivers/media/platform/Makefile|2 + drivers/media/platform/stm32/Makefile |1 + drivers/media/platform/stm32/stm32-dcmi.c | 1403 8 files changed, 1566 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dcmi.txt create mode 100644 drivers/media/platform/stm32/Makefile create mode 100644 drivers/media/platform/stm32/stm32-dcmi.c Patches 3, 4, 5, 6 applied on stm32-dt-for-v4.13 Patch 7 applied on stm32-defconfig-for-v4.13 Patch 8 will not be applied: As SDRAM used on STM32 MCUs is small, I don't want to penalize other users: - by increasing static kernel size - by enabling devices which consume dynamically lot of memory User will be free to enable it through menuconfig. Regards Alex
Re: [PATCH v3 0/5] Add support for the STM32F4 CRC32
Hi Cosar,
On 05/22/2017 04:33 PM, Cosar Dindar wrote:
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.
Changes in v3:
Rearranged patch order to fix build test error.
Cosar Dindar (5):
dt-bindings : Document the STM32F4 CRC32 binding
crypto : stm32 - Add STM32F4 CRC32 support
ARM: dts: stm32: Add CRC support to stm32f429
ARM: dts: stm32: enable CRC32 on stm32429-disco board
ARM: dts: stm32: enable CRC32 on stm32429i-eval board
.../devicetree/bindings/crypto/st,stm32-crc.txt| 4 +-
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
drivers/crypto/stm32/stm32_crc32.c | 68 ++
5 files changed, 75 insertions(+), 12 deletions(-)
Patches 3, 4, 5 applied on stm32-dt-for-v4.13
regards
Alex
Re: [PATCH 0/3] Add stm32h743i-disco board
Hi Patrice, On 06/07/2017 09:16 AM, patrice.chot...@st.com wrote: From: Patrice Chotard This series adds basic support for the stm32h743i discovery board based on stm32h7 MCU. v2: _ update commit messages header with format "ARM: dts: stm32: " Patrice Chotard (3): ARM: dts: stm32: Add usart2_pins on stm32h743. ARM: dts: stm32: Add usart2 support on stm32h743. ARM: dts: stm32: Add stm32h743i-disco board arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 13 ++ arch/arm/boot/dts/stm32h743.dtsi | 8 arch/arm/boot/dts/stm32h743i-disco.dts | 73 4 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32h743i-disco.dts Series applied on stm32-dt-for-v4.13 Regards Alex
Re: [PATCH v2 3/7] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings
Hi Rob, Gentle ping. On 04/12/2017 03:31 PM, Alexandre Torgue wrote: Hi Rob, On 04/10/2017 10:27 PM, Rob Herring wrote: On Fri, Apr 07, 2017 at 02:43:00PM +0200, Alexandre TORGUE wrote: STM32F4 MCU series is composed of several SOC (STM32F429, STM32F469, ...). Most of muxing definition are identical. So to avoid to duplicate bindings definition, this patch create common definitions. This is a lot of churn. Some confirmation that the resultant dtb is the same before and after would be nice. Perhaps the script you used to convert this as well. I tried to use fdtdump but it seems bugged. So I used directly dtc binary to (re)generate dts files (before and after apply the series) and I compared "pinmux" field in both case. Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb cat stm32f469-disco-after.dts | grep pinmux cat stm32f469-disco-before.dts | grep pinmux Do you agree with verifications ? regards alex Rob
Re: [PATCH 0/3] Add stm32h743i-disco board
Hi Patrice On 06/06/2017 06:13 PM, patrice.chot...@st.com wrote: From: Patrice Chotard This series adds basic support for the stm32h743i discovery board based on stm32h7 MCU. Patrice Chotard (3): ARM: dts: stm32h743: Add usart2_pins ARM: dts: stm32h743: Add usart2 support ARM: dts: stm32h743: Add stm32h743i-disco board arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 13 ++ arch/arm/boot/dts/stm32h743.dtsi | 8 arch/arm/boot/dts/stm32h743i-disco.dts | 74 4 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32h743i-disco.dts Series looks fine for me, but can you change commit header please. For example: ARM: dts: stm32: Add usart2_pins on stm32h743. Soon it will be done, I will apply it for next pull request. Regards Alex
Re: [PATCH net] net: stmmac: fix completely hung TX when using TSO
Hi Guys, On 06/06/2017 10:00 AM, Giuseppe CAVALLARO wrote: Hi Niklas I get the point and I acked the patch but Alex, please, can you confirm that this issue has never seen on your boxes where the TSO has been fully tested? The initial development (commit f748be531) introduces the following: (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), I don't remember to have seen this kind of issue in the past but for sure I agree with this patch. Acked-by: Alexandre TORGUE ... On 6/6/2017 9:25 AM, Niklas Cassel wrote: stmmac_tso_allocator can fail to set the Last Descriptor bit on a descriptor that actually was the last descriptor. This happens when the buffer of the last descriptor ends up having a size of exactly TSO_MAX_BUFF_SIZE. When the IP eventually reaches the next last descriptor, which actually has the bit set, the DMA will hang. When the DMA hangs, we get a tx timeout, however, since stmmac does not do a complete reset of the IP in stmmac_tx_timeout, we end up in a state with completely hung TX. Signed-off-by: Niklas Cassel Acked-by: Giuseppe Cavallaro --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 68a188e74c54..440bea049a7f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2723,7 +2723,7 @@ static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, 0, 1, -(last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), +(last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 0, 0); tmp_len -= TSO_MAX_BUFF_SIZE; Regards Peppe
[PATCH] pinctrl: stm32: remove useless check
There is no link between the number of elements of tab which contains all
pin desc (located in each pinctrl-stm32.c files) and the pin number
(defined in the tab).
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index d3c5f5d..8be7ebd 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -411,11 +411,6 @@ static int stm32_pctrl_dt_subnode_to_map(struct
pinctrl_dev *pctldev,
pin = STM32_GET_PIN_NO(pinfunc);
func = STM32_GET_PIN_FUNC(pinfunc);
- if (pin >= pctl->match_data->npins) {
- dev_err(pctl->dev, "invalid pin number.\n");
- return -EINVAL;
- }
-
if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
dev_err(pctl->dev, "invalid function.\n");
return -EINVAL;
--
1.9.1
[PATCH] pinctrl: stm32: Fix bad function call
In stm32_pconf_parse_conf function, stm32_pmx_gpio_set_direction is
called with wrong parameter value. Indeed, using NULL value for range
will raise an oops.
Fixes: aceb16dc2da5 ("pinctrl: Add STM32 MCUs support")
Reported-by: Dan Carpenter
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index d3c5f5d..222b668 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -798,7 +798,7 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev
*pctldev,
break;
case PIN_CONFIG_OUTPUT:
__stm32_gpio_set(bank, offset, arg);
- ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
default:
ret = -EINVAL;
--
1.9.1
[PATCH v2 3/3] ARM: dts: stm32: Set gpio controller also as interrupt controller
This patch set each gpio controller as a interrupt controller. User who
wants to use gpio as interrupt will have choice to use either "gpiolib"
interface or "common" interrupt interface.
Acked-by: Linus Walleij
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..bbd725d 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -561,6 +561,8 @@
gpioa: gpio@4002 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
@@ -569,6 +571,8 @@
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
@@ -577,6 +581,8 @@
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
@@ -585,6 +591,8 @@
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
@@ -593,6 +601,8 @@
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
@@ -601,6 +611,8 @@
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
@@ -609,6 +621,8 @@
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
@@ -617,6 +631,8 @@
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
@@ -625,6 +641,8 @@
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
@@ -633,6 +651,8
[PATCH v2 2/3] pinctrl: stm32: Implement .get_direction gpio_chip callback
Add .get_direction() gpiochip callback in STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 5a15c7d..814f76c 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -209,6 +209,24 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
return irq_create_fwspec_mapping(&fwspec);
}
+static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int
offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ int pin = stm32_gpio_pin(offset);
+ int ret;
+ u32 mode, alt;
+
+ stm32_pmx_get_mode(bank, pin, &mode, &alt);
+ if ((alt == 0) && (mode == 0))
+ ret = 1;
+ else if ((alt == 0) && (mode == 1))
+ ret = 0;
+ else
+ ret = -EINVAL;
+
+ return ret;
+}
+
static const struct gpio_chip stm32_gpio_template = {
.request= stm32_gpio_request,
.free = stm32_gpio_free,
@@ -217,6 +235,7 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
.direction_input= stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
+ .get_direction = stm32_gpio_get_direction,
};
static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
@@ -577,8 +596,8 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
clk_disable(bank->clk);
}
-static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
- int pin, u32 *mode, u32 *alt)
+void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
+ u32 *alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h
b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 35ebc94..8702a99 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -45,7 +45,10 @@ struct stm32_pinctrl_match_data {
const unsigned int npins;
};
-int stm32_pctl_probe(struct platform_device *pdev);
+struct stm32_gpio_bank;
+int stm32_pctl_probe(struct platform_device *pdev);
+void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
+ int pin, u32 *mode, u32 *alt);
#endif /* __PINCTRL_STM32_H */
--
1.9.1
[PATCH v2 1/3] pinctrl: stm32: set pin to gpio input when used as interrupt
This patch ensures that pin is correctly set as gpio input when it is used
as an interrupt.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index d3c5f5d..5a15c7d 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -219,12 +219,41 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
.to_irq = stm32_gpio_to_irq,
};
+static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ int ret;
+
+ ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
+ if (ret)
+ return ret;
+
+ ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
+ if (ret) {
+ dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
+ irq_data->hwirq);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+
+ gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
+}
+
static struct irq_chip stm32_gpio_irq_chip = {
.name = "stm32gpio",
.irq_eoi= irq_chip_eoi_parent,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_set_type = irq_chip_set_type_parent,
+ .irq_request_resources = stm32_gpio_irq_request_resources,
+ .irq_release_resources = stm32_gpio_irq_release_resources,
};
static int stm32_gpio_domain_translate(struct irq_domain *d,
@@ -248,15 +277,6 @@ static void stm32_gpio_domain_activate(struct irq_domain
*d,
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
- gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
-}
-
-static void stm32_gpio_domain_deactivate(struct irq_domain *d,
- struct irq_data *irq_data)
-{
- struct stm32_gpio_bank *bank = d->host_data;
-
- gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
}
static int stm32_gpio_domain_alloc(struct irq_domain *d,
@@ -285,7 +305,6 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d,
.alloc = stm32_gpio_domain_alloc,
.free = irq_domain_free_irqs_common,
.activate = stm32_gpio_domain_activate,
- .deactivate = stm32_gpio_domain_deactivate,
};
/* Pinctrl functions */
--
1.9.1
[PATCH v2 0/3] Add fixes to STM32 pintrl
This series add several fixes to STM32 pinctrl: - Set input mode when PIN is used as interrupt - Implement .get_direction() gpio_chip callback - In DT: set each gpio controller as a interrupt controller. User who wants to use gpio as interrupt will have choice to use either "gpiolib" interface or "common" interrupt interface. Changes since v1: -rebase on 4.12-rc1 -Let gpiochip and irqchip orthogonal in stm32 pinctrl driver -Don't use gpiolib internal define Regards Alex Alexandre TORGUE (3): pinctrl: stm32: set pin to gpio input when used as interrupt pinctrl: stm32: Implement .get_direction gpio_chip callback ARM: dts: stm32: Set gpio controller also as interrupt controller arch/arm/boot/dts/stm32f429.dtsi | 22 + arch/arm/boot/dts/stm32f746.dtsi | 22 + drivers/pinctrl/stm32/pinctrl-stm32.c | 62 --- drivers/pinctrl/stm32/pinctrl-stm32.h | 5 ++- 4 files changed, 98 insertions(+), 13 deletions(-) -- 1.9.1
Re: [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board
On 05/22/2017 04:34 PM, Cosar Dindar wrote:
Enable the CRC32 crypto on stm32429-disco board.
Signed-off-by: Cosar Dindar
---
Will be applied in STM32 branch for next pull request.
Thanks
Alex
arch/arm/boot/dts/stm32f429-disco.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 191fa50..ae47cde 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -102,6 +102,10 @@
clock-frequency = <800>;
};
+&crc {
+ status = "okay";
+};
+
&rtc {
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSI>;
Re: [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board
On 05/22/2017 04:35 PM, Cosar Dindar wrote:
Enable the CRC32 crypto on stm32429i-eval board.
Signed-off-by: Cosar Dindar
---
Will be applied in STM32 branch for next pull request.
Thanks
Alex
arch/arm/boot/dts/stm32429i-eval.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index b633114..360fb19 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -141,6 +141,10 @@
clock-frequency = <2500>;
};
+&crc {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
Re: [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429
On 05/22/2017 04:34 PM, Cosar Dindar wrote:
Add CRC32 Crypto support to stm32f429.
Signed-off-by: Cosar Dindar
Will be applied in STM32 branch for next pull request.
Thanks
Alex
---
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..18343de 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -766,6 +766,13 @@
};
};
+ crc: crc@40023000 {
+ compatible = "st,stm32f4-crc";
+ reg = <0x40023000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+ status = "disabled";
+ };
+
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
Re: [PATCH v4 0/8] Add support for DCMI camera interface of STMicroelectronics STM32 SoC series
Hi Hugues, On 04/20/2017 06:07 PM, Hugues Fruchet wrote: This patchset introduces a basic support for Digital Camera Memory Interface (DCMI) of STMicroelectronics STM32 SoC series. This first basic support implements RGB565 & YUV frame grabbing. Cropping and JPEG support will be added later on. This has been tested on STM324x9I-EVAL evaluation board embedding an OV2640 camera sensor. This driver depends on: - [PATCHv6 00/14] atmel-isi/ov7670/ov2640: convert to standalone drivers http://www.spinics.net/lists/linux-media/msg113480.html For stm32 machine part (DT+config): Acked-by: Alexandre TORGUE I will add it in future pull request. Regards Alex === = history = === version 4: - "v4l2-compliance -s -f" report - fix behaviour in case of start_streaming failure (DMA memory shortage for ex.) - dt-bindings: Fix remarks from Rob Herring: http://www.mail-archive.com/linux-media@vger.kernel.org/msg111340.html Add "Acked-by: Rob Herring " version 3: - stm32-dcmi: Add "Reviewed-by: Hans Verkuil " - dt-bindings: Fix remarks from Rob Herring: http://www.mail-archive.com/linux-media@vger.kernel.org/msg110956.html version 2: - Fix a Kbuild warning in probe: http://www.mail-archive.com/linux-media@vger.kernel.org/msg110678.html - Fix a warning in dcmi_queue_setup() - dt-bindings: warn on sensor signals level inversion in board example - Typos fixing version 1: - Initial submission === = v4l2-compliance = === Below is the v4l2-compliance report for this current version of the DCMI camera interface. v4l2-compliance has been built from v4l-utils-1.12.3. ~ # v4l2-compliance -s -f -d /dev/video0 v4l2-compliance SHA : f5f45e17ee98a0ebad7836ade2b34ceec909d751 Driver Info: Driver name : stm32-dcmi Card type : STM32 Digital Camera Memory Int Bus info : platform:dcmi Driver version: 4.11.0 Capabilities : 0x8521 Video Capture Read/Write Streaming Extended Pix Format Device Capabilities Device Caps : 0x0521 Video Capture Read/Write Streaming Extended Pix Format Compliance test for device /dev/video0 (not using libv4l2): Required ioctls: test VIDIOC_QUERYCAP: OK Allow for multiple opens: test second video open: OK test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 1 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Test input 0: Control ioctls: test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 3 Private Controls: 0 Format ioctls: test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK Codec ioctls: test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls: test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK Test input 0: Streaming ioctls: test re
Re: [PATCH 1/4] pinctrl: stm32: set pin to gpio input when used as interrupt
Hi Linus,
On 04/24/2017 02:36 PM, Linus Walleij wrote:
On Fri, Apr 7, 2017 at 5:10 PM, Alexandre TORGUE
wrote:
This patch ensures that pin is correctly set as gpio input when it is used
as an interrupt.
Signed-off-by: Alexandre TORGUE
(...)
+static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+ u32 ret;
+
+ if (!gpiochip_is_requested(&bank->gpio_chip, irq_data->hwirq)) {
+ ret = stm32_gpio_request(&bank->gpio_chip, irq_data->hwirq);
+ if (ret)
+ return ret;
+ }
This is wrong. You should only use gpiochip_lock_as_irq(), because of the
following in Documentation/gpio/driver.txt:
---
It is legal for any IRQ consumer to request an IRQ from any irqchip no matter
if that is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
irq_chip are orthogonal, and offering their services independent of each
other.
(...)
So always prepare the hardware and make it ready for action in respective
callbacks from the GPIO and irqchip APIs. Do not rely on gpiod_to_irq() having
been called first.
Ok, so actually the action to set pin in input mode is necessary in
stm32_gpio_irq_request_resources.
I'll fix it in V2.
This orthogonality leads to ambiguities that we need to solve: if there is
competition inside the subsystem which side is using the resource (a certain
GPIO line and register for example) it needs to deny certain operations and
keep track of usage inside of the gpiolib subsystem. This is why the API
below exists.
Locking IRQ usage
-
Input GPIOs can be used as IRQ signals. When this happens, a driver is requested
to mark the GPIO as being used as an IRQ:
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
is released:
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
When implementing an irqchip inside a GPIO driver, these two functions should
typically be called in the .startup() and .shutdown() callbacks from the
irqchip.
When using the gpiolib irqchip helpers, these callback are automatically
assigned.
--
It is because of easy to make errors like this that I prefer that people try
to use GPIOLIB_IRQCHIP helpers insteaf of rolling their own irqchip code.
I understand. It was difficult in our case due to design.
Thanks for review.
Alex
Yours,
Linus Walleij
Re: [PATCH 3/4] pinctrl: stm32: Implement .get_direction gpio_chip callback
Hi Linus, On 04/24/2017 02:37 PM, Linus Walleij wrote: On Fri, Apr 7, 2017 at 5:10 PM, Alexandre TORGUE wrote: Add .get_direction() gpiochip callback in STM32 pinctrl driver. Signed-off-by: Alexandre TORGUE (...) +#include No this is wrong, drivers should never include this file. It is a deprecated consumer header. + if ((alt == 0) && (mode == 0)) + ret = GPIOF_DIR_IN; + else if ((alt == 0) && (mode == 1)) + ret = GPIOF_DIR_OUT; Just return 0 or 1, that is the driver-internal API. Ok. I will fix it in V2. Thanks Alex Yours, Linus Walleij
Re: [PATCH v2 6/7] ARM: Kconfig: Introduce MACH_STM32F469 flag
Hi On 04/24/2017 02:30 PM, Linus Walleij wrote: On Fri, Apr 7, 2017 at 2:43 PM, Alexandre TORGUE wrote: This patch introduces the MACH_STM32F469 to make possible to only select STM32F469 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE Acked-by: Linus Walleij Please funnel this through the ARM SoC tree. Yes, I'll merge it in future pull request. Thanks for the series. Regards Alex Yours, Linus Walleij
Re: [PATCH v2 3/7] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings
Hi Rob, On 04/10/2017 10:27 PM, Rob Herring wrote: On Fri, Apr 07, 2017 at 02:43:00PM +0200, Alexandre TORGUE wrote: STM32F4 MCU series is composed of several SOC (STM32F429, STM32F469, ...). Most of muxing definition are identical. So to avoid to duplicate bindings definition, this patch create common definitions. This is a lot of churn. Some confirmation that the resultant dtb is the same before and after would be nice. Perhaps the script you used to convert this as well. I tried to use fdtdump but it seems bugged. So I used directly dtc binary to (re)generate dts files (before and after apply the series) and I compared "pinmux" field in both case. Example on stm32f469-disco: ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-after.dts stm32f469-disco-after.dtb ./scripts/dtc/dtc -I dtb -O dts -o stm32f469-disco-before.dts stm32f469-disco-before.dtb cat stm32f469-disco-after.dts | grep pinmux cat stm32f469-disco-before.dts | grep pinmux regards alex Rob
Re: [PATCH v2 2/7] Documentation: dt: Remove bindings for STM32 pinctrl
Hi Rob On 04/10/2017 10:20 PM, Rob Herring wrote: On Fri, Apr 07, 2017 at 02:42:59PM +0200, Alexandre TORGUE wrote: Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl driver. I read the subject as "rm Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt". You can be more specific: dt-bindings: pinctrl: remove ngpios from stm32-pinctrl binding With that, Acked-by: Rob Herring Thanks for review. I think that documentations patches (patch 2 & 3) will be merged by Linus W. Linus, do you want a V3 to fix commit header ? Regards Alex
Re: [PATCH] ARM: dts: stm32f7: add STM32f769I & stm32f746 discovery board support
Hi Vikas
On 04/10/2017 08:40 PM, Vikas Manocha wrote:
Thanks Alex,
On 04/10/2017 12:23 AM, Alexandre Torgue wrote:
Hi
On 04/08/2017 03:12 AM, Vikas Manocha wrote:
Stm32f769I & stm32f746 are MCUs of stm32f7 family. Here are the major
spces of the two boards:
stm32f769I discovery board:
- Cortex-M7 core @216MHz
- 2MB mcu internal flash
- 512KB internal sram
- 16MB sdram memory
- 64MB qspi flash memory
- 4 inch wvga LCD-TFT Display
stm32f746 discovery board:
- Cortex-M7 core @216MHz
- 1MB mcu internal flash
- 320KB internal sram
- 8MB sdram memory
- 16MB qspi flash memory
- 4.3 inch 480x272 LCD-TFT display
Signed-off-by: Vikas Manocha
---
arch/arm/boot/dts/Makefile| 2 +
arch/arm/boot/dts/stm32f746-disco.dts | 101 ++
arch/arm/boot/dts/stm32f746.dtsi | 2 +-
arch/arm/boot/dts/stm32f769-disco.dts | 101 ++
4 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stm32f746-disco.dts
create mode 100644 arch/arm/boot/dts/stm32f769-disco.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..a119f74 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,8 @@ dtb-$(CONFIG_ARCH_STI) += \
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
+stm32f746-disco.dtb \
+stm32f769-disco.dtb \
stm32429i-eval.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts
b/arch/arm/boot/dts/stm32f746-disco.dts
new file mode 100644
index 000..c0e313f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2017 - Vikas MANOCHA
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include
+
+/ {
+model = "STMicroelectronics STM32F746-DISCO board";
+compatible = "st,stm32f746-disco", "st,stm32f746";
+
+chosen {
+bootargs = "root=/dev/ram";
+stdout-path = "serial0:115200n8";
+};
+
+memory {
+reg = <0xC000 0x80>;
+};
+
+aliases {
+serial0 = &usart1;
+};
+
+};
+
+&clk_hse {
+clock-frequency = <2500>;
+};
+
+&pinctrl {
Pin muxing is not defined in board file. Please move it into SOC dtsi file.
Pin muxing used is different for different boards. e.g. usart1_rx pad is PA10
for stm32f769-disco board while it is PB7 for stm32f746-disco board.
The other possibilities for same pad (usart1_rx) is PB15. To make situation bit
more complex, it is only available in f769 device.
Putting in SOC dtsi file means having lot of combinations for different pins in
separate groups.
e.g. only for one instance of one ip (usart1), following groups might be
required at one point of time:
usart1_pa10_pa9 {..}
usart1_pa10_pb14 {..}
usart1_pa10_pb6 {..}
usart1_pb7_p
Re: [PATCH net-next] net: stmmac: set total length of the packet to be transmitted in TDES3
Hi,
On 04/11/2017 07:40 AM, Giuseppe CAVALLARO wrote:
Hi Niklas
patch looks ok for me, Alex any feedback?
It sounds good for me to.
peppe
On 4/10/2017 8:33 PM, Niklas Cassel wrote:
From: Niklas Cassel
Field FL/TPL in register TDES3 is not correctly set on GMAC4.
TX appears to be functional on GMAC 4.10a even if this field is not set,
however, to avoid relying on undefined behavior, set the length in TDES3.
The field has a different meaning depending on if the TSE bit in TDES3
is set or not (TSO). However, regardless of the TSE bit, the field is
not optional. The field is already set correctly when the TSE bit is set.
Since there is no limit for the number of descriptors that can be
used for a single packet, the field should be set to the sum of
the buffers contained in:
[ ... ...
], which should be equal to skb->len.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/chain_mode.c | 6 +++---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 3 ++-
drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/norm_desc.c| 2 +-
drivers/net/ethernet/stmicro/stmmac/ring_mode.c| 9 ++---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++--
7 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
index 37881f81319e..e93c40b4631e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
@@ -52,7 +52,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff
*skb, int csum)
tx_q->tx_skbuff_dma[entry].len = bmax;
/* do not close the descriptor and do not set own bit */
priv->hw->desc->prepare_tx_desc(desc, 1, bmax, csum,
STMMAC_CHAIN_MODE,
-0, false);
+0, false, skb->len);
while (len != 0) {
tx_q->tx_skbuff[entry] = NULL;
@@ -70,7 +70,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff
*skb, int csum)
tx_q->tx_skbuff_dma[entry].len = bmax;
priv->hw->desc->prepare_tx_desc(desc, 0, bmax, csum,
STMMAC_CHAIN_MODE, 1,
-false);
+false, skb->len);
len -= bmax;
i++;
} else {
@@ -85,7 +85,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff
*skb, int csum)
/* last descriptor can be set now */
priv->hw->desc->prepare_tx_desc(desc, 0, len, csum,
STMMAC_CHAIN_MODE, 1,
-true);
+true, skb->len);
len = 0;
}
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 90d28bcad880..b7ce3fbb5375 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -373,7 +373,7 @@ struct stmmac_desc_ops {
/* Invoked by the xmit function to prepare the tx descriptor */
void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
bool csum_flag, int mode, bool tx_own,
- bool ls);
+ bool ls, unsigned int tot_pkt_len);
void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int
len1,
int len2, bool tx_own, bool ls,
unsigned int tcphdrlen,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index 843ec69222ea..aa6476439aee 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
@@ -304,12 +304,13 @@ static void dwmac4_rd_init_tx_desc(struct
dma_desc *p, int mode, int end)
static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int
is_fs, int len,
bool csum_flag, int mode, bool tx_own,
- bool ls)
+ bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes3 = le32_to_cpu(p->des3);
p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
+tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
if (is_fs)
tdes3 |= TDES3_FIRST_DESCRIPTOR;
else
diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
index 323b59ec74a3..7546b3664113 100644
--- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
@@ -315,7 +315,7 @@ static void enh_desc_release_tx_desc(struct
dma_desc *p, int mode)
static void enh_desc_prepare_tx_desc(struct dma_desc *p, int
is_fs, int len,
bool csum_flag, int mode, bool tx_own,
- bool ls)
+ bool ls, unsigned int tot_pkt_len)
{
Re: [PATCH] ARM: dts: stm32f7: add STM32f769I & stm32f746 discovery board support
Hi
On 04/08/2017 03:12 AM, Vikas Manocha wrote:
Stm32f769I & stm32f746 are MCUs of stm32f7 family. Here are the major
spces of the two boards:
stm32f769I discovery board:
- Cortex-M7 core @216MHz
- 2MB mcu internal flash
- 512KB internal sram
- 16MB sdram memory
- 64MB qspi flash memory
- 4 inch wvga LCD-TFT Display
stm32f746 discovery board:
- Cortex-M7 core @216MHz
- 1MB mcu internal flash
- 320KB internal sram
- 8MB sdram memory
- 16MB qspi flash memory
- 4.3 inch 480x272 LCD-TFT display
Signed-off-by: Vikas Manocha
---
arch/arm/boot/dts/Makefile| 2 +
arch/arm/boot/dts/stm32f746-disco.dts | 101 ++
arch/arm/boot/dts/stm32f746.dtsi | 2 +-
arch/arm/boot/dts/stm32f769-disco.dts | 101 ++
4 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stm32f746-disco.dts
create mode 100644 arch/arm/boot/dts/stm32f769-disco.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..a119f74 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,8 @@ dtb-$(CONFIG_ARCH_STI) += \
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
+ stm32f746-disco.dtb \
+ stm32f769-disco.dtb \
stm32429i-eval.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts
b/arch/arm/boot/dts/stm32f746-disco.dts
new file mode 100644
index 000..c0e313f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2017 - Vikas MANOCHA
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include
+
+/ {
+ model = "STMicroelectronics STM32F746-DISCO board";
+ compatible = "st,stm32f746-disco", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC000 0x80>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+};
+
+&clk_hse {
+ clock-frequency = <2500>;
+};
+
+&pinctrl {
Pin muxing is not defined in board file. Please move it into SOC dtsi file.
+ usart1_pins: usart1@0 {
+ pins1 {
+ pinmux = ;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = ;
+ bias-disable;
+ };
+ };
+
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ slew-rate =
[PATCH 0/4] Add fixes to STM32 pintrl
This series add several fixes to STM32 pinctrl: - Set input mode when PIN is used as interrupt - Implement .get_direction() gpio_chip callback - In DT: set each gpio controller as a interrupt controller. User who wants to use gpio as interrupt will have choice to use either "gpiolib" interface or "common" interrupt interface. Regards Alex Alexandre TORGUE (4): pinctrl: stm32: set pin to gpio input when used as interrupt pinctrl: stm32: replace device_initcall() with arch_initcall() pinctrl: stm32: Implement .get_direction gpio_chip callback ARM: dts: stm32: Set gpio controller also as interrupt controller arch/arm/boot/dts/stm32f429.dtsi | 22 +++ arch/arm/boot/dts/stm32f746.dtsi | 22 +++ drivers/pinctrl/stm32/pinctrl-stm32.c | 47 +-- drivers/pinctrl/stm32/pinctrl-stm32.h | 5 +++- drivers/pinctrl/stm32/pinctrl-stm32f429.c | 6 +++- drivers/pinctrl/stm32/pinctrl-stm32f746.c | 7 - drivers/pinctrl/stm32/pinctrl-stm32h743.c | 6 +++- 7 files changed, 109 insertions(+), 6 deletions(-) -- 1.9.1
[PATCH 2/4] pinctrl: stm32: replace device_initcall() with arch_initcall()
Pinctrl has to be registered earlier. Mainly to register bank irqdomain
earlier as other devices could use interrupts from those irqdomain.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c
b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
index 990b867..4bbade2 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f429.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
@@ -1584,4 +1584,8 @@
},
};
-builtin_platform_driver(stm32f429_pinctrl_driver);
+static int __init stm32f429_pinctrl_init(void)
+{
+ return platform_driver_register(&stm32f429_pinctrl_driver);
+}
+arch_initcall(stm32f429_pinctrl_init);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f746.c
b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
index c0b4462..a2fae73 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f746.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
@@ -1678,4 +1678,9 @@
.of_match_table = stm32f746_pctrl_match,
},
};
-builtin_platform_driver(stm32f746_pinctrl_driver);
+
+static int __init stm32f746_pinctrl_init(void)
+{
+ return platform_driver_register(&stm32f746_pinctrl_driver);
+}
+arch_initcall(stm32f746_pinctrl_init);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32h743.c
b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
index f7f9eac..e34b2b9 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32h743.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
@@ -1977,4 +1977,8 @@
},
};
-builtin_platform_driver(stm32h743_pinctrl_driver);
+static int __init stm32h743_pinctrl_init(void)
+{
+ return platform_driver_register(&stm32h743_pinctrl_driver);
+}
+arch_initcall(stm32h743_pinctrl_init);
--
1.9.1
[PATCH 1/4] pinctrl: stm32: set pin to gpio input when used as interrupt
This patch ensures that pin is correctly set as gpio input when it is used
as an interrupt.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index abc405b..c8825e5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -207,12 +207,35 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
.to_irq = stm32_gpio_to_irq,
};
+static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+ u32 ret;
+
+ if (!gpiochip_is_requested(&bank->gpio_chip, irq_data->hwirq)) {
+ ret = stm32_gpio_request(&bank->gpio_chip, irq_data->hwirq);
+ if (ret)
+ return ret;
+ }
+
+ return stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
+}
+
+static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+
+ stm32_gpio_free(&bank->gpio_chip, irq_data->hwirq);
+}
+
static struct irq_chip stm32_gpio_irq_chip = {
.name = "stm32gpio",
.irq_eoi= irq_chip_eoi_parent,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_set_type = irq_chip_set_type_parent,
+ .irq_request_resources = stm32_gpio_irq_request_resources,
+ .irq_release_resources = stm32_gpio_irq_release_resources,
};
static int stm32_gpio_domain_translate(struct irq_domain *d,
--
1.9.1
[PATCH 3/4] pinctrl: stm32: Implement .get_direction gpio_chip callback
Add .get_direction() gpiochip callback in STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index c8825e5..fdde60f 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "../core.h"
#include "../pinconf.h"
@@ -197,6 +198,24 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
return irq_create_fwspec_mapping(&fwspec);
}
+static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int
offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ int pin = stm32_gpio_pin(offset);
+ int ret;
+ u32 mode, alt;
+
+ stm32_pmx_get_mode(bank, pin, &mode, &alt);
+ if ((alt == 0) && (mode == 0))
+ ret = GPIOF_DIR_IN;
+ else if ((alt == 0) && (mode == 1))
+ ret = GPIOF_DIR_OUT;
+ else
+ ret = -EINVAL;
+
+ return ret;
+}
+
static const struct gpio_chip stm32_gpio_template = {
.request= stm32_gpio_request,
.free = stm32_gpio_free,
@@ -205,6 +224,7 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip,
unsigned int offset)
.direction_input= stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
+ .get_direction = stm32_gpio_get_direction,
};
static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
@@ -569,8 +589,8 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
clk_disable(bank->clk);
}
-static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
- int pin, u32 *mode, u32 *alt)
+void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
+ u32 *alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h
b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 35ebc94..8702a99 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -45,7 +45,10 @@ struct stm32_pinctrl_match_data {
const unsigned int npins;
};
-int stm32_pctl_probe(struct platform_device *pdev);
+struct stm32_gpio_bank;
+int stm32_pctl_probe(struct platform_device *pdev);
+void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
+ int pin, u32 *mode, u32 *alt);
#endif /* __PINCTRL_STM32_H */
--
1.9.1
[PATCH 4/4] ARM: dts: stm32: Set gpio controller also as interrupt controller
This patch set each gpio controller as a interrupt controller. User who
wants to use gpio as interrupt will have choice to use either "gpiolib"
interface or "common" interrupt interface.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da97..12c6b70 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -555,6 +555,8 @@
gpioa: gpio@4002 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
@@ -563,6 +565,8 @@
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
@@ -571,6 +575,8 @@
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
@@ -579,6 +585,8 @@
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
@@ -587,6 +595,8 @@
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
@@ -595,6 +605,8 @@
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
@@ -603,6 +615,8 @@
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
@@ -611,6 +625,8 @@
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
@@ -619,6 +635,8 @@
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
@@ -627,6 +645,8 @@
[PATCH v2 7/7] ARM: dts: stm32: create dedicated files for pinctrl definitions
Create dedicated file by MCU for pinmuxing and gpio definitions.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 3c99466..de95156 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -46,6 +46,7 @@
*/
/dts-v1/;
+#include "stm32f429-pinctrl.dtsi"
#include "stm32f429.dtsi"
#include
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
new file mode 100644
index 000..06a0833
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2016 - Alexandre Torgue
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+
+/ {
+ soc {
+
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4002 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@4002 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
+
[PATCH v2 4/7] pinctrl: stm32: Add STM32F469 MCU support
This patch which adds STM32F469 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index f5ccabd..3b8026f 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -14,6 +14,12 @@ config PINCTRL_STM32F429
default MACH_STM32F429
select PINCTRL_STM32
+config PINCTRL_STM32F469
+ bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST &&
!MACH_STM32F469
+ depends on OF && IRQ_DOMAIN_HIERARCHY
+ default MACH_STM32F469
+ select PINCTRL_STM32
+
config PINCTRL_STM32F746
bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST &&
!MACH_STM32F746
depends on OF && IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index cb31b4d..5f379f5 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
+obj-$(CONFIG_PINCTRL_STM32F469)+= pinctrl-stm32f469.o
obj-$(CONFIG_PINCTRL_STM32F746)+= pinctrl-stm32f746.o
obj-$(CONFIG_PINCTRL_STM32H743)+= pinctrl-stm32h743.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f469.c
b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
new file mode 100644
index 000..86c8ceb
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
@@ -0,0 +1,1578 @@
+/*
+ * Copyright (C) Alexandre Torgue 2016
+ * Author: Alexandre Torgue
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include
+#include
+#include
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32f469_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(12, "ETH_MDIO"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(10, "LCD_B2"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(6, "SPI1_NSS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(13, "OTG_HS_SOF"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVE
[PATCH v2 5/7] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index e4cda3d..d907a74 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,6 +9,7 @@ Pin controller node: Required properies: - compatible: value should be one of the following: "st,stm32f429-pinctrl" + "st,stm32f469-pinctrl" "st,stm32f746-pinctrl" "st,stm32h743-pinctrl" - #address-cells: The value of this property must be 1 -- 1.9.1
[PATCH v2 3/7] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings
STM32F4 MCU series is composed of several SOC (STM32F429, STM32F469, ...).
Most of muxing definition are identical. So to avoid to duplicate bindings
definition, this patch create common definitions.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da97..3afa203 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
#include
#include
@@ -642,44 +642,44 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
- pinmux =
;
+ pinmux = ;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
bias-disable;
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux =
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
;
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -688,49 +688,49 @@
ethernet_mii: mii@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-,
-,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux =
,
+
,
+
,
+
,
+
,
+
,
+,
+,
+
,
+
,
+
,
+
,
+
,
+
;
[PATCH v2 6/7] ARM: Kconfig: Introduce MACH_STM32F469 flag
This patch introduces the MACH_STM32F469 to make possible to only select STM32F469 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d4e71b..19c43e6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -894,6 +894,11 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config MACH_STM32F469 + bool "STMicrolectronics STM32F469" + depends on ARCH_STM32 + default y + config MACH_STM32F746 bool "STMicrolectronics STM32F746" depends on ARCH_STM32 -- 1.9.1
[PATCH v2 0/7] Add STM32F469 pinctrl and fix issues in STM32 pinctrl
This series adds support of a dedicated driver for STM32F469 MCU pinctroller. This add generates some changes inside STM32 pinctrl driver and inside STM32 device tree. Changes in STM32 pinctrl driver: --- - Add STM32F469 driver. - Change STM32 pinctrl core in order to use "gpio-ranges" devicetree definitions. Indeed, on STM32F469 there an hole in BANK J. We need to declare a gpio-ranges in gpioj controller node to handle this hole. Changes in STM32 device tree: I propose a new architecture (a new file split) for pinmux definition: - Create a common stm32f4-pinctrl.dtsi for pinmuxing definitions which are common between STM32F429 and STM32F469 MCU. - Create dedicated stm32fxxx-pinctrl.dtsi file for each MCU (stm32f429-pinctrl.dtsi and stm32f469-pinctrl.dtsi) each one will include stm32f4-pinctrl.dtsi. All differences (pinmuxing or GPIO bank holes) will be put inside the dedicated files. This series fix a locking issue when a gpio is used as IRQ. Changes since v1: -Rebase on 4.11-rc1. -Fix issues for "gpio-ranges" patch. Regards Alex Alexandre TORGUE (7): pinctrl: stm32: add possibility to use gpio-ranges to declare bank range Documentation: dt: Remove bindings for STM32 pinctrl includes: dt-bindings: Rename STM32F429 pinctrl DT bindings pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Add new compatible to STM32 pinctrl driver bindings ARM: Kconfig: Introduce MACH_STM32F469 flag ARM: dts: stm32: create dedicated files for pinctrl definitions .../bindings/pinctrl/st,stm32-pinctrl.txt |3 +- arch/arm/Kconfig |5 + arch/arm/boot/dts/stm32429i-eval.dts |1 + arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 243 +++ arch/arm/boot/dts/stm32f429-disco.dts |1 + arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 95 ++ arch/arm/boot/dts/stm32f429.dtsi | 196 --- arch/arm/boot/dts/stm32f469-disco.dts |1 + arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 96 ++ drivers/pinctrl/stm32/Kconfig |6 + drivers/pinctrl/stm32/Makefile |1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 115 +- drivers/pinctrl/stm32/pinctrl-stm32f469.c | 1578 include/dt-bindings/pinctrl/stm32f4-pinfunc.h | 1302 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1239 --- 15 files changed, 3395 insertions(+), 1487 deletions(-) create mode 100644 arch/arm/boot/dts/stm32f4-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f429-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f469-pinctrl.dtsi create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f469.c create mode 100644 include/dt-bindings/pinctrl/stm32f4-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1
[PATCH v2 2/7] Documentation: dt: Remove bindings for STM32 pinctrl
Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl driver. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index eac20aa..e4cda3d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -38,8 +38,6 @@ Optional properties: - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node which includes IRQ mux selection register, and the offset of the IRQ mux selection register. - - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less - than 16). - gpio-ranges: Define a dedicated mapping between a pin-controller and a gpio controller. Format is <&phandle a b c> with: -(phandle): phandle of pin-controller. -- 1.9.1
[PATCH v2 1/7] pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
Use device tree entries to declare gpio range. It will allow to use
no contiguous gpio bank and holes inside a bank.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index abc405b..d3c5f5d 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -71,6 +71,7 @@ struct stm32_gpio_bank {
struct pinctrl_gpio_range range;
struct fwnode_handle *fwnode;
struct irq_domain *domain;
+ u32 bank_nr;
};
struct stm32_pinctrl {
@@ -138,6 +139,17 @@ static inline void __stm32_gpio_set(struct stm32_gpio_bank
*bank,
static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ struct pinctrl_gpio_range *range;
+ int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
+
+ range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
+ if (!range) {
+ dev_err(pctl->dev, "pin %d not in range.\n", pin);
+ return -EINVAL;
+ }
+
return pinctrl_request_gpio(chip->base + offset);
}
@@ -235,7 +247,7 @@ static void stm32_gpio_domain_activate(struct irq_domain *d,
struct stm32_gpio_bank *bank = d->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
- regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+ regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
}
@@ -589,7 +601,7 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
}
range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
mode = stm32_gpio_get_mode(function);
@@ -604,7 +616,7 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
struct pinctrl_gpio_range *range, unsigned gpio,
bool input)
{
- struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
+ struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
int pin = stm32_gpio_pin(gpio);
stm32_pmx_set_mode(bank, pin, !input, 0);
@@ -762,7 +774,7 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev
*pctldev,
int offset, ret = 0;
range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
switch (param) {
@@ -843,7 +855,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev
*pctldev,
bool val;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
stm32_pmx_get_mode(bank, offset, &mode, &alt);
@@ -898,13 +910,14 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev
*pctldev,
static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
struct device_node *np)
{
- int bank_nr = pctl->nbanks;
- struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
+ struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
struct pinctrl_gpio_range *range = &bank->range;
+ struct of_phandle_args args;
struct device *dev = pctl->dev;
struct resource res;
struct reset_control *rstc;
- int err, npins;
+ int npins = STM32_GPIO_PINS_PER_BANK;
+ int bank_nr, err;
rstc = of_reset_control_get(np, NULL);
if (!IS_ERR(rstc))
@@ -929,28 +942,33 @@ static int stm32_gpiolib_register_bank(struct
stm32_pinctrl *pctl,
return err;
}
- npins = pctl->match_data->npins;
- npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
- if (npins < 0)
- return -EINVAL;
- else if (npins > STM32_GPIO_PINS_PER_BANK)
- npins = STM32_GPIO_PINS_PER_BANK;
-
bank->gpio_chip = stm32_gpio_template;
+
+ of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
+
+ if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
+ bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
+ bank->gpio_chip.base = args.args[1];
+ } else {
+ bank_nr = pctl->nbanks;
+ bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
+ range->name = bank->gpio_chip.label;
+ range->id = bank_n
Re: [PATCH 0/3] Add RTC support on STM32F746
Hi On 01/19/2017 02:45 PM, Amelie Delaunay wrote: This patchset enables STM32 RTC on STM32F746 MCU. Amelie Delaunay (3): ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746 ARM: dts: stm32: Add RTC support for STM32F746 MCU ARM: dts: stm32: enable RTC on stm32746g-eval arch/arm/boot/dts/stm32746g-eval.dts | 4 arch/arm/boot/dts/stm32f746.dtsi | 16 2 files changed, 20 insertions(+) Series applied on stm32-dt-for-v4.12 regards Alex
Re: [PATCH v2 0/7] Add support for triggered buffer mode to STM32 ADC
Hi On 01/26/2017 03:28 PM, Fabrice Gasnier wrote: The following patches add support for triggered buffer mode. These are based on top of "Add PWM and IIO timer drivers for STM32" series. Reference: https://lkml.org/lkml/2017/1/20/116 STM32 ADC, can use either interrupts or DMA to collect data. Either timer trigger output (TRGO) or PWM can be used as trigger source. This patchset has been tested on STM32F429 eval board. ... Fabrice Gasnier (7): iio: adc: stm32: add support for triggered buffer mode iio: adc: stm32: Enable use of stm32 timer triggers iio: adc: stm32: add trigger polarity extended attribute Documentation: dt: iio: stm32-adc: optional dma support iio: adc: stm32: add optional dma support ARM: dts: stm32: Enable dma by default on stm32f4 adc ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval Patches 6 & 7 (DT) applied on stm32-dt-for-v4.12 Regards Alex Documentation/ABI/testing/sysfs-bus-iio-adc-stm32 | 18 + .../devicetree/bindings/iio/adc/st,stm32-adc.txt | 7 + arch/arm/boot/dts/stm32429i-eval.dts | 28 + arch/arm/boot/dts/stm32f429.dtsi | 6 + drivers/iio/adc/Kconfig| 5 + drivers/iio/adc/stm32-adc-core.c | 1 + drivers/iio/adc/stm32-adc-core.h | 2 + drivers/iio/adc/stm32-adc.c| 633 - 8 files changed, 676 insertions(+), 24 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-stm32
Re: [PATCH 0/4] Introduce STM32F7 Clocks
hi On 01/06/2017 02:59 PM, gabriel.fernan...@st.com wrote: From: Gabriel Fernandez This patch-set introduces STM32F7 clocks. F7 Clocks are very similar as F4. We have some new clocks: - hdmi-cec - spdif-rx - lptim1 - sai2 Uarts & I2cs can have different clock sources. Gabriel Fernandez (4): clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boards ARM: dts: stm32: stm32f7: Enable clocks for STM32F746 boards dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file .../devicetree/bindings/clock/st,stm32-rcc.txt | 20 ++ arch/arm/boot/dts/stm32f746.dtsi | 80 -- drivers/clk/clk-stm32f4.c | 277 - include/dt-bindings/clock/stm32fx-clock.h | 20 ++ include/dt-bindings/mfd/stm32f7-rcc.h | 112 + 5 files changed, 476 insertions(+), 33 deletions(-) create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h Patchs 3 & 4 applied on stm32-dt-for-v4.12
Re: [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig
Hi, On 01/19/2017 02:25 PM, M'boumba Cedric Madianga wrote: This patch adds I2C support for STM32 default configuration Signed-off-by: M'boumba Cedric Madianga --- Applied on stm32-defconfig-for-v4.12 Regards Alex arch/arm/configs/stm32_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 5a72d69..323d2a3 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y
Re: [PATCH] ARM: configs: stm32: Set CPU_V7M_NUM_IRQ to max value
Hi Arnd On 03/30/2017 05:36 PM, Arnd Bergmann wrote: On Thu, Mar 23, 2017 at 11:09 AM, Alexandre TORGUE wrote: stm32_defconfig is used for several STM32 MCU: STM32F429, STM32F469, STM32F746 and now STM32H743. Each of MCU listed have different interrupts number mapped on NVIC. STM32F429: 81, STM32F469: 92, STM32F746: 97 and STM32H743: 149. I could set CPU_V7M_NUM_IRQ to 149 but in order to avoid forgetting to update this value for next STM32 MCU I prefer to set it to max value: 240. Signed-off-by: Alexandre TORGUE It's not entirely clear who you want to apply this (if any), given that you sent the patch to yourself. I've applied it to next/defconfig now, hope that's what you intended. Actually, I pushed it mainly to share the patch and check comments. I planned to add it in my pull request, but no pb if you already took it :). Regards Alex Arnd
Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range
Hi Linus
On 02/01/2017 04:01 PM, Linus Walleij wrote:
On Mon, Jan 30, 2017 at 5:29 PM, Alexandre Torgue
wrote:
On 01/30/2017 04:19 PM, Linus Walleij wrote:
+ if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
&args))
+ bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
+ else {
+ range->name = bank->gpio_chip.label;
+ range->id = bank_nr;
+ range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->npins = npins;
+ range->gc = &bank->gpio_chip;
+ pinctrl_add_gpio_range(pctl->pctl_dev,
+ &pctl->banks[bank_nr].range);
+ }
I Keep the old way to get range in order to keep compatibility with older
device tree (if no gpio ranges are defined).
Aha I understand. Sorry for my stupidity.
Go ahead with this!
I saw an issue about this patch. It doesn't seem to be merged, so I will
send a V2 only for this patch.
Regards
Alex
Yours,
Linus Walleij
Re: [PATCH v3 5/5] ARM: configs: Add watchdog support in STM32 defconfig
Hi, On 03/22/2017 04:04 PM, Yannick Fertre wrote: This patch adds STM32 watchdog support in stm32_defconfig file Signed-off-by: Yannick Fertre --- Update commit header please (ARM: configs: stm32: Add watchdog support) arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index a9d8e3c..83afa73 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -48,6 +48,7 @@ CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set
[PATCH] ARM: configs: stm32: Set CPU_V7M_NUM_IRQ to max value
stm32_defconfig is used for several STM32 MCU: STM32F429, STM32F469, STM32F746 and now STM32H743. Each of MCU listed have different interrupts number mapped on NVIC. STM32F429: 81, STM32F469: 92, STM32F746: 97 and STM32H743: 149. I could set CPU_V7M_NUM_IRQ to 149 but in order to avoid forgetting to update this value for next STM32 MCU I prefer to set it to max value: 240. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index a9d8e3c..7c9c157 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -20,6 +20,7 @@ CONFIG_EMBEDDED=y # CONFIG_MMU is not set CONFIG_ARM_SINGLE_ARMV7M=y CONFIG_ARCH_STM32=y +CONFIG_CPU_V7M_NUM_IRQ=240 CONFIG_SET_MEM_PARAM=y CONFIG_DRAM_BASE=0x9000 CONFIG_FLASH_MEM_BASE=0x0800 -- 1.9.1
Re: [PATCH v1 3/5] ARM: dts: stm32ap: Add watchdog support for STM32F429 SoC
Hi
On 03/22/2017 02:36 PM, Yannick Fertre wrote:
Signed-off-by: Yannick FERTRE
---
Please add a commit message, and change commit header as following:
ARM: dts: stm32: ...
arch/arm/boot/dts/stm32f429.dtsi | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da97..148273b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -65,7 +65,7 @@
clock-frequency = <32768>;
};
- clk-lsi {
+ clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
@@ -812,6 +812,13 @@
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
};
+
+ iwdg: iwdg@40003000 {
Please try to keep nodes ordered.
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ status = "disabled";
+ };
};
};
Re: [PATCH v1 4/5] ARM: dts: stm32ap: Add watchdog support for STM32F429 eval board
Hi
On 03/22/2017 02:36 PM, Yannick Fertre wrote:
Signed-off-by: Yannick Fertre
---
Please add a commit message and change commit header as following:
ARM: dts: stm32: .
arch/arm/boot/dts/stm32429i-eval.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 3c99466..aab81ed 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -181,3 +181,7 @@
pinctrl-names = "default";
status = "okay";
};
+
+&iwdg {
+ status = "okay";
+};
Re: [PATCH 0/3] Add RTC support on STM32F746
Hi Amélie, On 01/19/2017 02:45 PM, Amelie Delaunay wrote: This patchset enables STM32 RTC on STM32F746 MCU. Amelie Delaunay (3): ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746 ARM: dts: stm32: Add RTC support for STM32F746 MCU ARM: dts: stm32: enable RTC on stm32746g-eval Can you please rebase this series on 4.11-rc1 and resend ? Thanks in advance arch/arm/boot/dts/stm32746g-eval.dts | 4 arch/arm/boot/dts/stm32f746.dtsi | 16 2 files changed, 20 insertions(+)
Re: [PATCH 1/2] reset: add reset-simple to unify socfpga, stm32, and sunxi
Hi Philipp,
On 03/08/2017 11:19 AM, Andre Przywara wrote:
Hi,
On 08/03/17 09:54, Philipp Zabel wrote:
Reset operations for simple reset controllers with reset lines that can
be controlled by toggling bits in (mostly) contiguous register ranges
using read-modify-write cycles under a spinlock. So far this covers the
socfpga, stm32, and sunxi drivers.
Wow, that looks nice, thanks for that.
But can't we go one step further and unify those driver into one file then?
And either have different probe functions to cover the different DT
requirements or to just have one unified probe checking for the super
set of all properties?
I agree with Andre. It looks nice and it should be a good thing to have
a common probe inside reset-simple.c
Maybe only "nresets" and "inverted" DT properties are needed.
Regards
Alex
Also
Signed-off-by: Philipp Zabel
---
drivers/reset/Kconfig | 6 +++
drivers/reset/Makefile| 1 +
drivers/reset/reset-simple.c | 92 +
drivers/reset/reset-simple.h | 53
drivers/reset/reset-socfpga.c | 96 +--
drivers/reset/reset-stm32.c | 73
drivers/reset/reset-sunxi.c | 82 +---
7 files changed, 181 insertions(+), 222 deletions(-)
create mode 100644 drivers/reset/reset-simple.c
create mode 100644 drivers/reset/reset-simple.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d21c07ccc94e5..d968becd0474c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -62,21 +62,27 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_SIMPLE
+ bool
+
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST
default ARCH_SOCFPGA
+ select RESET_SIMPLE
help
This enables the reset controller driver for Altera SoCFPGAs.
config RESET_STM32
bool "STM32 Reset Driver" if COMPILE_TEST
default ARCH_STM32
+ select RESET_SIMPLE
help
This enables the RCC reset controller driver for STM32 MCUs.
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
+ select RESET_SIMPLE
help
This enables the reset driver for Allwinner SoCs.
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 02a74db943397..f5cc015f20956 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_STM32) += reset-stm32.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
new file mode 100644
index 0..2160e84fe216b
--- /dev/null
+++ b/drivers/reset/reset-simple.c
@@ -0,0 +1,92 @@
+/*
+ * Simple Reset Controller ops
+ *
+ * Based on Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "reset-simple.h"
+
+static inline struct reset_simple_data *
+to_reset_simple_data(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct reset_simple_data, rcdev);
+}
+
+static int reset_simple_clear(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct reset_simple_data *data = to_reset_simple_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + (bank * reg_width));
+ writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
+
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static int reset_simple_set(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct reset_simple_data *data = to_reset_simple_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + (bank * reg_width));
+ writel(reg | BIT(of
Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
On 02/06/2017 09:46 AM, Linus Walleij wrote: On Wed, Feb 1, 2017 at 4:58 PM, Alexandre Torgue wrote: On 02/01/2017 04:06 PM, Rob Herring wrote: On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 25d9809..4f0487d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,7 +9,8 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + (b) "st,stm32f469-pinctrl" + (c) "st,stm32f746-pinctrl" Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every time. I completely agree. Linus, Do i need to send a v2 for this patch ? Nopes, applied the amended v1 patch already with these changes, check the result. Thanks Linus! Yours, Linus Walleij
Re: [PATCH 0/8] ADD STM32H743 MCU and STM32H743i-Eval board supports
Hi Linus On 02/01/2017 04:16 PM, Linus Walleij wrote: On Tue, Jan 31, 2017 at 2:14 PM, Alexandre TORGUE wrote: This series adds basic support for STM32H743 MCU and stm32h743i-eval board. With it, you can boot stm32h743i-eval board successfully. Patch 1 & 2 look fine to me. Shall I just apply them and offer them on an immutable branch based on v4.10 so you can pull that into ARM SoC if you want to get this in for v4.11? Thanks, but I think it is a bit late for this cycle. Indeed I'm close to send a second round for STM32 DT, but I don't plan to add STM32H7 support. I prefere to let machine & DT patches in review. Anyway, I 'll be happy if you take pinctrl & bindings parts in this cycle :). Regards Alex Yours, Linus Walleij
Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
On 02/01/2017 04:06 PM, Rob Herring wrote: On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 25d9809..4f0487d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,7 +9,8 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + (b) "st,stm32f469-pinctrl" + (c) "st,stm32f746-pinctrl" Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every time. I completely agree. Linus, Do i need to send a v2 for this patch ? With that, Acked-by: Rob Herring - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- 1.9.1
[PATCH 3/8] Documentation: dt-bindings: Add STM32 pinctrl driver DT bindings
Add compatible sting for stm32h743 MCU. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index b24583a..ac8dcb7 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -10,6 +10,7 @@ Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" (b) "st,stm32f746-pinctrl" + (c) "st,stm32h743-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- 1.9.1
[PATCH 4/8] ARM: stm32: create dedicated kconfig for STM32 machine
Create a dedicated Kconfig file in mach-stm32/ and move existing stm32 configs inside. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5fab553..e84936c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -813,6 +813,8 @@ source "arch/arm/mach-spear/Kconfig" source "arch/arm/mach-sti/Kconfig" +source "arch/arm/mach-stm32/Kconfig" + source "arch/arm/mach-s3c24xx/Kconfig" source "arch/arm/mach-s3c64xx/Kconfig" @@ -871,28 +873,6 @@ config ARCH_LPC18XX Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 high performance microcontrollers. -config ARCH_STM32 - bool "STMicrolectronics STM32" - depends on ARM_SINGLE_ARMV7M - select ARCH_HAS_RESET_CONTROLLER - select ARMV7M_SYSTICK - select CLKSRC_STM32 - select PINCTRL - select RESET_CONTROLLER - select STM32_EXTI - help - Support for STMicroelectronics STM32 processors. - -config MACH_STM32F429 - bool "STMicrolectronics STM32F429" - depends on ARCH_STM32 - default y - -config MACH_STM32F746 - bool "STMicrolectronics STM32F746" - depends on ARCH_STM32 - default y - config ARCH_MPS2 bool "ARM MPS2 platform" depends on ARM_SINGLE_ARMV7M diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig new file mode 100644 index 000..40115fa --- /dev/null +++ b/arch/arm/mach-stm32/Kconfig @@ -0,0 +1,21 @@ +config ARCH_STM32 + bool "STMicrolectronics STM32" + depends on ARM_SINGLE_ARMV7M + select ARCH_HAS_RESET_CONTROLLER + select ARMV7M_SYSTICK + select CLKSRC_STM32 + select PINCTRL + select RESET_CONTROLLER + select STM32_EXTI + help + Support for STMicroelectronics STM32 processors. + +config MACH_STM32F429 + bool "STMicrolectronics STM32F429" + depends on ARCH_STM32 + default y + +config MACH_STM32F746 + bool "STMicrolectronics STM32F746" + depends on ARCH_STM32 + default y -- 1.9.1
[PATCH 2/8] pinctrl: stm32: Add STM32H743 MCU support
This patch adds STM32H743 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index c03dce7..f5ccabd 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -20,4 +20,9 @@ config PINCTRL_STM32F746
default MACH_STM32F746
select PINCTRL_STM32
+config PINCTRL_STM32H743
+ bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST &&
!MACH_STM32H743
+ depends on OF && IRQ_DOMAIN_HIERARCHY
+ default MACH_STM32H743
+ select PINCTRL_STM32
endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index 4a1ee74..cb31b4d 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
obj-$(CONFIG_PINCTRL_STM32F746)+= pinctrl-stm32f746.o
+obj-$(CONFIG_PINCTRL_STM32H743)+= pinctrl-stm32h743.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32h743.c
b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
new file mode 100644
index 000..f7f9eac
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
@@ -0,0 +1,1980 @@
+/*
+ * Copyright (C) Alexandre Torgue 2017
+ * Author: Alexandre Torgue
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include
+#include
+#include
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32h743_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(5, "TIM15_BKIN"),
+ STM32_FUNCTION(8, "USART2_CTS_NSS"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(10, "SDMMC2_CMD"),
+ STM32_FUNCTION(11, "SAI2_SD_B"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(4, "LPTIM3_OUT"),
+ STM32_FUNCTION(5, "TIM15_CH1N"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(11, "SAI2_MCK_B"),
+ STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(4, "LPTIM4_OUT"),
+ STM32_FUNCTION(5, "TIM15_CH1"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(9, "SAI2_SCK_B"),
+ STM32_FUNCTION(12, "ETH_MDIO"),
+ STM32_FUNCTION(13, "MDIOS_MDIO"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(4, "LPTIM5_OUT"),
+ STM32_FUNCTION(5, "TIM15_CH2"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(10, "LCD_B2"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(3, "TIM5_ETR"),
+
[PATCH 1/8] include: dt-bindings: Add STM32H7 pinctrl DT bindings
Adds common pinctrl device tree bindings for STM32H743 and STM32H753 MCU. Signed-off-by: Alexandre TORGUE diff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h new file mode 100644 index 000..cb673b5 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h @@ -0,0 +1,1612 @@ +#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H +#define _DT_BINDINGS_STM32H7_PINFUNC_H + +#define STM32H7_PA0_FUNC_GPIO 0x0 +#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32H7_PA0_FUNC_TIM5_CH1 0x3 +#define STM32H7_PA0_FUNC_TIM8_ETR 0x4 +#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5 +#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8 +#define STM32H7_PA0_FUNC_UART4_TX 0x9 +#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa +#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb +#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32H7_PA0_FUNC_EVENTOUT 0x10 +#define STM32H7_PA0_FUNC_ANALOG 0x11 + +#define STM32H7_PA1_FUNC_GPIO 0x100 +#define STM32H7_PA1_FUNC_TIM2_CH2 0x102 +#define STM32H7_PA1_FUNC_TIM5_CH2 0x103 +#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104 +#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105 +#define STM32H7_PA1_FUNC_USART2_RTS 0x108 +#define STM32H7_PA1_FUNC_UART4_RX 0x109 +#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a +#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b +#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32H7_PA1_FUNC_LCD_R2 0x10f +#define STM32H7_PA1_FUNC_EVENTOUT 0x110 +#define STM32H7_PA1_FUNC_ANALOG 0x111 + +#define STM32H7_PA2_FUNC_GPIO 0x200 +#define STM32H7_PA2_FUNC_TIM2_CH3 0x202 +#define STM32H7_PA2_FUNC_TIM5_CH3 0x203 +#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204 +#define STM32H7_PA2_FUNC_TIM15_CH1 0x205 +#define STM32H7_PA2_FUNC_USART2_TX 0x208 +#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209 +#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c +#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d +#define STM32H7_PA2_FUNC_LCD_R1 0x20f +#define STM32H7_PA2_FUNC_EVENTOUT 0x210 +#define STM32H7_PA2_FUNC_ANALOG 0x211 + +#define STM32H7_PA3_FUNC_GPIO 0x300 +#define STM32H7_PA3_FUNC_TIM2_CH4 0x302 +#define STM32H7_PA3_FUNC_TIM5_CH4 0x303 +#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304 +#define STM32H7_PA3_FUNC_TIM15_CH2 0x305 +#define STM32H7_PA3_FUNC_USART2_RX 0x308 +#define STM32H7_PA3_FUNC_LCD_B2 0x30a +#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32H7_PA3_FUNC_LCD_B5 0x30f +#define STM32H7_PA3_FUNC_EVENTOUT 0x310 +#define STM32H7_PA3_FUNC_ANALOG 0x311 + +#define STM32H7_PA4_FUNC_GPIO 0x400 +#define STM32H7_PA4_FUNC_TIM5_ETR 0x403 +#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 +#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32H7_PA4_FUNC_USART2_CK 0x408 +#define STM32H7_PA4_FUNC_SPI6_NSS 0x409 +#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32H7_PA4_FUNC_EVENTOUT 0x410 +#define STM32H7_PA4_FUNC_ANALOG 0x411 + +#define STM32H7_PA5_FUNC_GPIO 0x500 +#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 +#define STM32H7_PA5_FUNC_SPI6_SCK 0x509 +#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32H7_PA5_FUNC_LCD_R4 0x50f +#define STM32H7_PA5_FUNC_EVENTOUT 0x510 +#define STM32H7_PA5_FUNC_ANALOG 0x511 + +#define STM32H7_PA6_FUNC_GPIO 0x600 +#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32H7_PA6_FUNC_TIM3_CH1 0x603 +#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606 +#define STM32H7_PA6_FUNC_SPI6_MISO 0x609 +#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a +#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b +#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c +#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d +#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32H7_PA6_FUNC_LCD_G2 0x60f +#define STM32H7_PA6_FUNC_EVENTOUT 0x610 +#define STM32H7_PA6_FUNC_ANALOG 0x611 + +#define STM32H7_PA7_FUNC_GPIO 0x700 +#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32H7_PA7_FUNC_TIM3_CH2 0x703 +#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706 +#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709 +#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a +#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d +#define STM32H7_PA7_FUNC_EVENTOUT 0x710 +#define STM32H7_PA7_FUNC_ANALOG 0x711 + +#define STM32H7_PA8_FUNC_GPIO 0x800 +#define STM32H7_PA8_FUNC_MCO1 0x801 +#define STM32H7_PA8_FUNC_TIM1_CH1 0x802 +#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803 +#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804 +#define STM32H7_PA8_FUNC_I2C3_SCL 0x805 +#define STM32H7_PA8_FUNC_USART1_CK 0x808 +#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32H7_PA8_FUNC_UART7_RX 0x80c +#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d +#define STM32H7_PA8_FUNC_LCD_B3 0x80e +#define STM32H7_PA8_FUNC_LCD_R6 0x80f +#define STM32H7_PA8_FUNC_EVENTOUT 0x810 +#define STM32H7_PA8_FUNC_ANALOG 0x811
[PATCH 7/8] ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board
Add basic support for STM32H743 MCU and his eval board.
The STMicrolectornics's STM32H743 MCU is based on Cortex-M7 core
running up to @400MHz with 2MB internal flash and 1MB internal RAM.
For more details see:
Documentation/arm/stm32/stm32h743-overview.txt
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb..f38a845 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -746,7 +746,8 @@ dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
stm32429i-eval.dtb \
- stm32746g-eval.dtb
+ stm32746g-eval.dtb \
+ stm32h743i-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
new file mode 100644
index 000..fcc1e06
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2017 - Alexandre Torgue
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+
+/ {
+ soc {
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32h743-pinctrl";
+ ranges = <0 0x5802 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio@5802 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&timer_clk>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@58020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&timer_clk>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@58020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&timer_clk>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@58020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&timer_clk>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@58021000 {
+ gpio-controller;
+
[PATCH 0/8] ADD STM32H743 MCU and STM32H743i-Eval board supports
This series adds basic support for STM32H743 MCU and stm32h743i-eval board. With it, you can boot stm32h743i-eval board successfully. For your information: The STMicrolectornics's STM32H743 MCU has the following main features: - Cortex-M7 core running up to @400MHz - 2MB internal flash, about 1MBytes internal RAM - FMC controller to connect SDRAM, NOR and NAND memories - Dual mode QSPI - SD/MMC/SDIO support - Ethernet controller - USB OTFG FS & HS controllers - I2C, SPI, CAN busses support - Several 16 & 32 bits general purpose timers - Serial Audio interface - LCD controller - HDMI-CEC - SPDIFRX Regards Alex Alexandre TORGUE (8): include: dt-bindings: Add STM32H7 pinctrl DT bindings pinctrl: stm32: Add STM32H743 MCU support Documentation: dt-bindings: Add STM32 pinctrl driver DT bindings ARM: stm32: create dedicated kconfig for STM32 machine ARM: stm32: Add a new SOC - STM32H743 ARM: stm32: Introduce MACH_STM32H743 flag ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board ARM: configs: Add new config fragment to change RAM start point Documentation/arm/stm32/stm32h743-overview.txt | 30 + .../bindings/pinctrl/st,stm32-pinctrl.txt |1 + arch/arm/Kconfig | 24 +- arch/arm/boot/dts/Makefile |3 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 156 ++ arch/arm/boot/dts/stm32h743.dtsi | 83 + arch/arm/boot/dts/stm32h743i-eval.dts | 74 + arch/arm/configs/dram_0xd000.config|1 + arch/arm/mach-stm32/Kconfig| 26 + arch/arm/mach-stm32/board-dt.c |1 + drivers/pinctrl/stm32/Kconfig |5 + drivers/pinctrl/stm32/Makefile |1 + drivers/pinctrl/stm32/pinctrl-stm32h743.c | 1980 include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 14 files changed, 3974 insertions(+), 23 deletions(-) create mode 100644 Documentation/arm/stm32/stm32h743-overview.txt create mode 100644 arch/arm/boot/dts/stm32h743-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32h743.dtsi create mode 100644 arch/arm/boot/dts/stm32h743i-eval.dts create mode 100644 arch/arm/configs/dram_0xd000.config create mode 100644 arch/arm/mach-stm32/Kconfig create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32h743.c create mode 100644 include/dt-bindings/pinctrl/stm32h7-pinfunc.h -- 1.9.1
[PATCH 8/8] ARM: configs: Add new config fragment to change RAM start point
Add a new fragment to over-ride the RAM start point to 0xd000. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/configs/dram_0xd000.config b/arch/arm/configs/dram_0xd000.config new file mode 100644 index 000..61ba704 --- /dev/null +++ b/arch/arm/configs/dram_0xd000.config @@ -0,0 +1 @@ +CONFIG_DRAM_BASE=0xd000 -- 1.9.1
[PATCH 6/8] ARM: stm32: Introduce MACH_STM32H743 flag
This patch introduces the MACH_STM32H743 to make possible to only select STM32H743 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 40115fa..2d1419e 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -19,3 +19,8 @@ config MACH_STM32F746 bool "STMicrolectronics STM32F746" depends on ARCH_STM32 default y + +config MACH_STM32H743 + bool "STMicrolectronics STM32H743" + depends on ARCH_STM32 + default y -- 1.9.1
[PATCH 5/8] ARM: stm32: Add a new SOC - STM32H743
The STM32H743 is a Cortex-M7 MCU running at 400MHz and containing 1MBytes internal RAM. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/arm/stm32/stm32h743-overview.txt b/Documentation/arm/stm32/stm32h743-overview.txt new file mode 100644 index 000..3031cba --- /dev/null +++ b/Documentation/arm/stm32/stm32h743-overview.txt @@ -0,0 +1,30 @@ + STM32H743 Overview + == + + Introduction + + The STM32H743 is a Cortex-M7 MCU aimed at various applications. + It features: + - Cortex-M7 core running up to @400MHz + - 2MB internal flash, 1MBytes internal RAM + - FMC controller to connect SDRAM, NOR and NAND memories + - Dual mode QSPI + - SD/MMC/SDIO support + - Ethernet controller + - USB OTFG FS & HS controllers + - I2C, SPI, CAN busses support + - Several 16 & 32 bits general purpose timers + - Serial Audio interface + - LCD controller + - HDMI-CEC + - SPDIFRX + - DFSDM + + Resources + - + Datasheet and reference manual are publicly available on ST website: + - http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033 + + Document Author + --- + Alexandre Torgue diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index c354222..e918686 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -12,6 +12,7 @@ "st,stm32f429", "st,stm32f469", "st,stm32f746", + "st,stm32h743", NULL }; -- 1.9.1
Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range
Hi Linus,
On 01/30/2017 04:19 PM, Linus Walleij wrote:
On Fri, Jan 27, 2017 at 5:15 PM, Alexandre TORGUE
wrote:
Use device tree entries to declare gpio range. It will allow to use
no contiguous gpio bank and holes inside a bank.
Signed-off-by: Alexandre TORGUE
(...)
+ of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
+
+ if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args))
+ bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
+ else {
+ range->name = bank->gpio_chip.label;
+ range->id = bank_nr;
+ range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->npins = npins;
+ range->gc = &bank->gpio_chip;
+ pinctrl_add_gpio_range(pctl->pctl_dev,
+ &pctl->banks[bank_nr].range);
+ }
I Keep the old way to get range in order to keep compatibility with
older device tree (if no gpio ranges are defined).
Why are you doing this?
There is already code in drivers/gpio/gpiolib-of.c to pick ranges
from the device tree and add when you're adding the GPIO chips.
Yes, If I declare gpio-ranges inside DT node, the range is well handled
by the gpiolib. But in this condition I use gpio-ranges entry to get the
pin base offset for the bank we are registering. For example, if there
an hole between 2 banks (GPIOA, GPIOD, ...) I need to know at which pin
offset the bank D starts. It is the only way I found.
The "else" statement is here to get compatibility with older device tree
(which don't use gpio-ranges entry).
Regards
Alex
Please use that or figure out what is needed to make it work for
you instead of reimplementing it.
Yours,
Linus Walleij
Re: [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl
Hi, On 01/27/2017 05:15 PM, Alexandre TORGUE wrote: This series adds support of a dedicated driver for STM32F469 MCU pinctroller. This add generates some changes inside STM32 pinctrl driver and inside STM32 device tree. Changes in STM32 pinctrl driver: --- - Add STM32F469 driver. - Change STM32 pinctrl core in order to use "gpio-ranges" devicetree definitions. Indeed, on STM32F469 there an hole in BANK J. We need to declare a gpio-ranges in gpioj controller node to handle this hole. Changes in STM32 device tree: I propose a new architecture (a new file split) for pinmux definition: - Create a common stm32f4-pinctrl.dtsi for pinmuxing definitions which are common between STM32F429 and STM32F469 MCU. - Create dedicated stm32fxxx-pinctrl.dtsi file for each MCU (stm32f429-pinctrl.dtsi and stm32f469-pinctrl.dtsi) each one will include stm32f4-pinctrl.dtsi. All differences (pinmuxing or GPIO bank holes) will be put inside the dedicated files. This series fix a locking issue when a gpio is used as IRQ. Regards Alex Alexandre TORGUE (8): pinctrl: stm32: fix bad location of gpiochip_lock_as_irq pinctrl: stm32: use gpio-ranges to declare bank range I just see typo issue in patch 1&2. I will send a V2 when more review will be done. Regards Alex Documentation: dt: Add bindings for STM32 pinctrl includes: dt-bindings: Rename STM32F429 pinctrl DT bindings pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Add new compatible to STM32 pinctrl driver bindings ARM: Kconfig: Introduce MACH_STM32F469 flag ARM: dts: stm32: create dedicated files for pinctrl definitions .../bindings/pinctrl/st,stm32-pinctrl.txt | 57 +- arch/arm/Kconfig |5 + arch/arm/boot/dts/stm32429i-eval.dts |1 + arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 196 +++ arch/arm/boot/dts/stm32f429-disco.dts |1 + arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 106 ++ arch/arm/boot/dts/stm32f429.dtsi | 153 -- arch/arm/boot/dts/stm32f469-disco.dts |1 + arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 107 ++ drivers/pinctrl/stm32/Kconfig |6 + drivers/pinctrl/stm32/Makefile |1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 129 +- drivers/pinctrl/stm32/pinctrl-stm32f469.c | 1574 include/dt-bindings/pinctrl/stm32f4-pinfunc.h | 1302 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1239 --- 15 files changed, 3414 insertions(+), 1464 deletions(-) create mode 100644 arch/arm/boot/dts/stm32f4-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f429-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f469-pinctrl.dtsi create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f469.c create mode 100644 include/dt-bindings/pinctrl/stm32f4-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h
[PATCH 4/8] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings
STM32F4 MCU series is composed of several SOC (STM32F429, STM32F469, ...).
Most of muxing definition are identical. So to avoid to duplicate bindings
definition, this patch create common definitions.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..d585288 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include
+#include
/ {
clocks {
@@ -305,31 +305,31 @@
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = ;
+ pinmux = ;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux =
;
+ pinmux = ;
bias-disable;
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux =
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
,
+
;
bias-disable;
drive-push-pull;
slew-rate = <2>;
@@ -338,20 +338,20 @@
ethernet_mii: mii@0 {
pins {
- pinmux =
,
-
,
-
,
-
,
-
,
-
,
-,
-,
-
,
-
,
-
,
-
,
-
,
-
;
+ pinmux =
,
+
,
+
,
+
,
+
,
+
,
+,
+,
+
,
+
,
+
,
+
,
+
,
+
;
slew-rate = <2>;
};
};
diff --git a/include/dt-bindings/pinctrl/stm32f4-pinfunc.h
b/include/dt-bindings/pinctrl/stm32f4-pinfunc.h
new file mode 100644
index 000..fae2ccf
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f4-pinfunc.h
@@ -0,0 +1,1302 @@
+#ifndef _DT_BINDINGS_STM32F4_PINFUNC_H
+#define _DT_BINDINGS_STM32F4_PINFUNC_H
+
+#define STM32F4_PA0_FUNC_GPIO 0x0
+#define STM32F4_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F4_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F4_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F4_PA0_FUNC_USART2_CTS 0x8
+#define
