[PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range
Use device tree entries to declare gpio range. It will allow to use
no contiguous gpio bank and holes inside a bank.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index b145431..d0a968a 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -589,7 +589,7 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
}
range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
mode = stm32_gpio_get_mode(function);
@@ -604,7 +604,7 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
struct pinctrl_gpio_range *range, unsigned gpio,
bool input)
{
- struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
+ struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
int pin = stm32_gpio_pin(gpio);
stm32_pmx_set_mode(bank, pin, !input, 0);
@@ -761,7 +761,7 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev
*pctldev,
int offset, ret = 0;
range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
switch (param) {
@@ -842,7 +842,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev
*pctldev,
bool val;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
- bank = gpio_range_to_bank(range);
+ bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
stm32_pmx_get_mode(bank, offset, &mode, &alt);
@@ -900,10 +900,12 @@ static int stm32_gpiolib_register_bank(struct
stm32_pinctrl *pctl,
int bank_nr = pctl->nbanks;
struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
struct pinctrl_gpio_range *range = &bank->range;
+ struct of_phandle_args args;
struct device *dev = pctl->dev;
struct resource res;
struct reset_control *rstc;
- int err, npins;
+ unsigned int npins;
+ int err;
rstc = of_reset_control_get(np, NULL);
if (!IS_ERR(rstc))
@@ -928,28 +930,32 @@ static int stm32_gpiolib_register_bank(struct
stm32_pinctrl *pctl,
return err;
}
- npins = pctl->match_data->npins;
- npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
- if (npins < 0)
- return -EINVAL;
- else if (npins > STM32_GPIO_PINS_PER_BANK)
+ if (of_property_read_u32(np, "ngpios", &npins))
npins = STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip = stm32_gpio_template;
+
+ of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
+
+ if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args))
+ bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
+ else {
+ range->name = bank->gpio_chip.label;
+ range->id = bank_nr;
+ range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->npins = npins;
+ range->gc = &bank->gpio_chip;
+ pinctrl_add_gpio_range(pctl->pctl_dev,
+ &pctl->banks[bank_nr].range);
+ }
+
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip.ngpio = npins;
bank->gpio_chip.of_node = np;
bank->gpio_chip.parent = dev;
spin_lock_init(&bank->lock);
- of_property_read_string(np, "st,bank-name", &range->name);
- bank->gpio_chip.label = range->name;
-
- range->id = bank_nr;
- range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
- range->npins = bank->gpio_chip.ngpio;
- range->gc = &bank->gpio_chip;
-
/* create irq hierarchical domain */
bank->fwnode = of_node_to_fwnode(np);
@@ -966,7 +972,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl
*pctl,
return err;
}
- dev_info(dev, "%s bank added\n", range->name);
+ dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
return 0;
}
@@ -1085,30 +1091,6 @@ int stm32_pctl_probe(struct platform_device *pdev)
return ret;
}
- for_each_child_of_node(np, child)
- if (of_property_read_bool(child, "gpio-controller"))
- banks++;
-
- if (!banks) {
- d
[PATCH 8/8] ARM: dts: stm32: create dedicated files for pinctrl definitions
Create dedicated file by MCU for pinmuxing and gpio definitions.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 5436e88..7f22385 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -46,6 +46,7 @@
*/
/dts-v1/;
+#include "stm32f429-pinctrl.dtsi"
#include "stm32f429.dtsi"
#include
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
new file mode 100644
index 000..d349c59
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2016 - Alexandre Torgue
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4002 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@4002 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 0>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 1>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 2>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 3>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 4>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@40021400 {
+
[PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl
This series adds support of a dedicated driver for STM32F469 MCU pinctroller. This add generates some changes inside STM32 pinctrl driver and inside STM32 device tree. Changes in STM32 pinctrl driver: --- - Add STM32F469 driver. - Change STM32 pinctrl core in order to use "gpio-ranges" devicetree definitions. Indeed, on STM32F469 there an hole in BANK J. We need to declare a gpio-ranges in gpioj controller node to handle this hole. Changes in STM32 device tree: I propose a new architecture (a new file split) for pinmux definition: - Create a common stm32f4-pinctrl.dtsi for pinmuxing definitions which are common between STM32F429 and STM32F469 MCU. - Create dedicated stm32fxxx-pinctrl.dtsi file for each MCU (stm32f429-pinctrl.dtsi and stm32f469-pinctrl.dtsi) each one will include stm32f4-pinctrl.dtsi. All differences (pinmuxing or GPIO bank holes) will be put inside the dedicated files. This series fix a locking issue when a gpio is used as IRQ. Regards Alex Alexandre TORGUE (8): pinctrl: stm32: fix bad location of gpiochip_lock_as_irq pinctrl: stm32: use gpio-ranges to declare bank range Documentation: dt: Add bindings for STM32 pinctrl includes: dt-bindings: Rename STM32F429 pinctrl DT bindings pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Add new compatible to STM32 pinctrl driver bindings ARM: Kconfig: Introduce MACH_STM32F469 flag ARM: dts: stm32: create dedicated files for pinctrl definitions .../bindings/pinctrl/st,stm32-pinctrl.txt | 57 +- arch/arm/Kconfig |5 + arch/arm/boot/dts/stm32429i-eval.dts |1 + arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 196 +++ arch/arm/boot/dts/stm32f429-disco.dts |1 + arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 106 ++ arch/arm/boot/dts/stm32f429.dtsi | 153 -- arch/arm/boot/dts/stm32f469-disco.dts |1 + arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 107 ++ drivers/pinctrl/stm32/Kconfig |6 + drivers/pinctrl/stm32/Makefile |1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 129 +- drivers/pinctrl/stm32/pinctrl-stm32f469.c | 1574 include/dt-bindings/pinctrl/stm32f4-pinfunc.h | 1302 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1239 --- 15 files changed, 3414 insertions(+), 1464 deletions(-) create mode 100644 arch/arm/boot/dts/stm32f4-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f429-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32f469-pinctrl.dtsi create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f469.c create mode 100644 include/dt-bindings/pinctrl/stm32f4-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1
[PATCH 5/8] pinctrl: stm32: Add STM32F469 MCU support
This patch which adds STM32F469 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index c03dce7..a065fe3 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -14,6 +14,12 @@ config PINCTRL_STM32F429
default MACH_STM32F429
select PINCTRL_STM32
+config PINCTRL_STM32F469
+ bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST &&
!MACH_STM32F469
+ depends on OF && IRQ_DOMAIN_HIERARCHY
+ default MACH_STM32F469
+ select PINCTRL_STM32
+
config PINCTRL_STM32F746
bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST &&
!MACH_STM32F746
depends on OF && IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index 4a1ee74..0a9a853 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
+obj-$(CONFIG_PINCTRL_STM32F469)+= pinctrl-stm32f469.o
obj-$(CONFIG_PINCTRL_STM32F746)+= pinctrl-stm32f746.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f469.c
b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
new file mode 100644
index 000..4098fde
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
@@ -0,0 +1,1574 @@
+/*
+ * Copyright (C) Alexandre Torgue 2016
+ * Author: Alexandre Torgue
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include
+#include
+#include
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32f469_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(12, "ETH_MDIO"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(10, "LCD_B2"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(6, "SPI1_NSS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(13, "OTG_HS_SOF"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(
[PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 25d9809..4f0487d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,7 +9,8 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + (b) "st,stm32f469-pinctrl" + (c) "st,stm32f746-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- 1.9.1
[PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl
Adds "ngpios" and "gpio-ranges" bindings definition.
Signed-off-by: Alexandre TORGUE
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index b24583a..25d9809 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -37,8 +37,23 @@ Optional properties:
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
which includes IRQ mux selection register, and the offset of the IRQ mux
selection register.
+ - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
+ than 16).
+ - gpio-ranges: Define a dedicated mapping between a pin-controller and
+ a gpio controller. Format is <&phandle a b c> with:
+ -(phandle): phandle of pin-controller.
+ -(a): gpio base offset in range.
+ -(b): pin base offset in range.
+ -(c): gpio count in range
+ This entry has to be used either if there are holes inside a bank:
+ GPIOB0/B1/B2/B14/B15 (see example 2)
+ or if banks are not contiguous:
+ GPIOA/B/C/E...
+ NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
+ have to use a "gpio-ranges" entry.
+ More details in Documentation/devicetree/bindings/gpio/gpio.txt.
-Example:
+Example 1:
#include
...
@@ -60,6 +75,43 @@ Example:
pin-functions nodes follow...
};
+Example 2:
+#include
+...
+
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f429-pinctrl";
+ ranges = <0 0x4002 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio@4002 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOA";
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOB";
+ ngpios = 4;
+ gpio-ranges = <&pinctrl 0 16 3>,
+ <&pinctrl 14 30 2>;
+ };
+
+
+ ...
+ pin-functions nodes follow...
+ };
+
+
Contents of function subnode node:
--
Subnode format
--
1.9.1
[PATCH 7/8] ARM: Kconfig: Introduce MACH_STM32F469 flag
This patch introduces the MACH_STM32F469 to make possible to only select STM32F469 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5fab553..f54402c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,6 +888,11 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config MACH_STM32F469 + bool "STMicrolectronics STM32F469" + depends on ARCH_STM32 + default y + config MACH_STM32F746 bool "STMicrolectronics STM32F746" depends on ARCH_STM32 -- 1.9.1
[PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
Move gpio lock as irq from "domain alloc" callback to "domain activate"
callback. It will allow to use gpiolib sysfs correctly.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index efc4371..b145431 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -236,6 +236,15 @@ static void stm32_gpio_domain_activate(struct irq_domain
*d,
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+ gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
+}
+
+static void stm32_gpio_domain_deactivate(struct irq_domain *d,
+ struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = d->host_data;
+
+ gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
}
static int stm32_gpio_domain_alloc(struct irq_domain *d,
@@ -243,11 +252,9 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d,
unsigned int nr_irqs, void *data)
{
struct stm32_gpio_bank *bank = d->host_data;
- struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
struct irq_fwspec *fwspec = data;
struct irq_fwspec parent_fwspec;
irq_hw_number_t hwirq;
- int ret;
hwirq = fwspec->param[0];
parent_fwspec.fwnode = d->parent->fwnode;
@@ -258,35 +265,15 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d,
irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
bank);
- ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq);
- if (ret) {
- dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n",
- bank->gpio_chip.label, hwirq);
- return ret;
- }
-
- ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
- if (ret)
- gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq);
-
- return ret;
-}
-
-static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
- unsigned int nr_irqs)
-{
- struct stm32_gpio_bank *bank = d->host_data;
- struct irq_data *data = irq_get_irq_data(virq);
-
- irq_domain_free_irqs_common(d, virq, nr_irqs);
- gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq);
+ return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
}
static const struct irq_domain_ops stm32_gpio_domain_ops = {
.translate = stm32_gpio_domain_translate,
.alloc = stm32_gpio_domain_alloc,
- .free = stm32_gpio_domain_free,
+ .free = irq_domain_free_irqs_common,
.activate = stm32_gpio_domain_activate,
+ .deactivate = stm32_gpio_domain_deactivate,
};
/* Pinctrl functions */
--
1.9.1
Re: [PATCH 7/7] ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-eval
Hi Fabrice
On 01/19/2017 02:34 PM, Fabrice Gasnier wrote:
Define and enable pwm1 and pwm3, timers1 & 3 trigger outputs on
stm32f469-eval board.
Signed-off-by: Fabrice Gasnier
---
Typo issue in commit header (stm32f469 --> stm32f429)
arch/arm/boot/dts/stm32429i-eval.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 2181220..892100f 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -171,3 +171,31 @@
pinctrl-names = "default";
status = "okay";
};
+
+&timers1 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@2 {
+ status = "okay";
+ };
+};
Re: [PATCH v9 7/8] ARM: dts: stm32: add Timers driver for stm32f429 MCU
{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4001 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ timers8: timers@40010400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010400 0x400>;
+ clocks = <&rcc 0 161>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+ };
+
usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
@@ -201,6 +410,57 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
};
+ timers9: timers@40014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014000 0x400>;
+ clocks = <&rcc 0 176>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@8 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <8>;
+ status = "disabled";
+ };
+ };
+
+ timers10: timers@40014400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014400 0x400>;
+ clocks = <&rcc 0 177>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ timers11: timers@40014800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014800 0x400>;
+ clocks = <&rcc 0 178>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
pwrcfg: power-config@40007000 {
compatible = "syscon";
reg = <0x40007000 0x400>;
@@ -355,6 +615,21 @@
slew-rate = <2>;
};
};
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = ,
+
,
+
;
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = ,
+;
+ };
+ };
};
rcc: rcc@40023810 {
Acked-by: Alexandre TORGUE
Thanks!
Alex
Re: [PATCH v9 8/8] ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
Hi Benjamin,
On 01/20/2017 10:15 AM, Benjamin Gaignard wrote:
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f469-disco.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 8a163d7..92552d3 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -81,3 +81,31 @@
&usart3 {
status = "okay";
};
+
+&timers1 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@2 {
+ status = "okay";
+ };
+};
Acked-by: Alexandre TORGUE
Thanks
Alex
Re: [PATCH] stmmac: add missing of_node_put
Hi On 01/17/2017 12:23 PM, Julia Lawall wrote: The function stmmac_dt_phy provides several possibilities for initializing plat->mdio_node, all of which have the effect of increasing the reference count of the assigned value. This field is not updated elsewhere, so the value is live until the end of the lifetime of plat (devm_allocated), just after the end of stmmac_remove_config_dt. Thus, add an of_node_put on plat->mdio_node in stmmac_remove_config_dt. It is possible that the field mdio_node is never initialized, but of_node_put is NULL-safe, so it is also safe to call of_node_put in that case. Signed-off-by: Julia Lawall --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 4daa8a3..460f94f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -409,6 +409,7 @@ void stmmac_remove_config_dt(struct platform_device *pdev, if (of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); of_node_put(plat->phy_node); + of_node_put(plat->mdio_node); } #else struct plat_stmmacenet_data * Acked-by: Alexandre TORGUE Thanks Alex
Re: [patch net-next] stmmac: indent an if statement
Dear David On 01/16/2017 11:00 PM, David Miller wrote: From: Dan Carpenter Date: Tue, 17 Jan 2017 00:56:15 +0300 (It would be better if one of the stmmac people were responding here insead of a random fix the indenting weenie like myself.) They are all too busy trying to rename the driver, because that's so much more important. No, we don't spend all our times to deals with stmmac renaming. Just busy on other topic and we continue to do our best with Peppe to review stmmac patch. Regards Alexandre
Re: [patch net-next] stmmac: indent an if statement
Hi Julia On 01/16/2017 11:10 PM, Julia Lawall wrote: On Tue, 17 Jan 2017, Dan Carpenter wrote: On Mon, Jan 16, 2017 at 10:46:22PM +0100, Julia Lawall wrote: On Mon, 16 Jan 2017, Dan Carpenter wrote: On Mon, Jan 16, 2017 at 12:19:24PM +0300, Dan Carpenter wrote: On Sun, Jan 15, 2017 at 10:14:38PM -0500, David Miller wrote: From: Dan Carpenter Date: Thu, 12 Jan 2017 21:46:32 +0300 The break statement should be indented one more tab. Signed-off-by: Dan Carpenter Applied, but like Julia I think we might have a missing of_node_put() here. Of course, sorry for dropping the ball on this. I'll send a patch for that. Actually, I've looked at it some more and I think this function is OK. We're supposed to do an of_node_put() later... I can't find where that happens, but presumably that's because I don't know stmmac well. This code here, though, is fine. Why do you think it is fine? Does anyone in the calling context know which child would have caused the break? Yeah. It's saved in plat->mdio_node and we expect to be holding on either path through the function. (It would be better if one of the stmmac people were responding here insead of a random fix the indenting weenie like myself.) OK, I agree that there should not be an of_node_put with the break. Perhaps there should be an of_node_put on plat->mdio_node in stmmac_remove_config_dt, like there is an of_node_put on plat->phy_node. But it would certainly be helpful to hear from someone who knows the code better. I also think it's missing! Can you propose a patch ? br Alex julia
Re: [PATCHv3 RESEND 7/8] ARM: dts: stm32: enable RTC on stm32429i-eval
On 01/16/2017 02:29 PM, Amelie Delaunay wrote:
This patch enables RTC on stm32429i-eval with default LSE clock source.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32429i-eval.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 2181220..eedb27d 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -157,6 +157,10 @@
};
};
+&rtc {
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCHv3 RESEND 6/8] ARM: dts: stm32: enable RTC on stm32f469-disco
On 01/16/2017 02:29 PM, Amelie Delaunay wrote:
This patch enables RTC on stm32f469-disco with default LSE clock source.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32f469-disco.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index fda12a4..f52b9f6 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -78,6 +78,10 @@
clock-frequency = <800>;
};
+&rtc {
+ status = "okay";
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCHv3 RESEND 4/8] ARM: dts: stm32: Add RTC support for STM32F429 MCU
On 01/16/2017 02:29 PM, Amelie Delaunay wrote:
This patch adds STM32 RTC bindings for STM32F429.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32f429.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 557c1f4..f05a9d9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -125,6 +125,20 @@
status = "disabled";
};
+ rtc: rtc@40002800 {
+ compatible = "st,stm32-rtc";
+ reg = <0x40002800 0x400>;
+ clocks = <&rcc 1 CLK_RTC>;
+ clock-names = "ck_rtc";
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSE>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 1>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCHv3 RESEND 5/8] ARM: dts: stm32: enable RTC on stm32f429-disco
On 01/16/2017 02:29 PM, Amelie Delaunay wrote:
This patch enables RTC on stm32f429-disco with LSI as clock source because
X2 crystal for LSE is not fitted by default.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32f429-disco.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..9222b9f 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -94,6 +94,12 @@
clock-frequency = <800>;
};
+&rtc {
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSI>;
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCHv3 RESEND 1/8] ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f429
Hi Amélie,
On 01/16/2017 02:29 PM, Amelie Delaunay wrote:
This patch set HSE_RTC clock frequency to 1 MHz, as the clock supplied to
the RTC must be 1 MHz.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32f429.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e9324a3..557c1f4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -433,6 +433,8 @@
reg = <0x40023800 0x400>;
clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
+ assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+ assigned-clock-rates = <100>;
};
dma1: dma-controller@40026000 {
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCHv3 8/8] ARM: configs: stm32: Add RTC support in STM32 defconfig
Hi Amélie, On 01/05/2017 02:43 PM, Amelie Delaunay wrote: This patch adds STM32 RTC support in stm32_defconfig file. Signed-off-by: Amelie Delaunay --- arch/arm/configs/stm32_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index be19e09..0acff9e 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -57,6 +57,8 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_STM32=y CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y # CONFIG_FILE_LOCKING is not set Applied on stm32-defconfig-for-v4.11 thanks Alex
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
On 01/16/2017 11:26 AM, Bruno Herrera wrote:
Hi Alex,
On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
wrote:
Hi Bruno,
On 01/16/2017 03:09 AM, Bruno Herrera wrote:
This patch adds the USB pins and nodes for USB HS/FS cores working at FS
speed,
using embedded PHY.
Signed-off-by: Bruno Herrera
Sorry, but what is patch 1 & pacth 3 status ?
My bad, I'll add the status of the patch series version 3.
For this one, can split it in 3 patches (one patch for SOC and one for each
board) please.
No problem.
---
arch/arm/boot/dts/stm32f429-disco.dts | 30 ++
arch/arm/boot/dts/stm32f429.dtsi | 35
++-
arch/arm/boot/dts/stm32f469-disco.dts | 30 ++
3 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..374c5ed 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,16 @@
gpios = <&gpioa 0 0>;
};
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -99,3 +109,23 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ compatible = "st,stm32-fsotg", "snps,dwc2";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ usbotg_pwren_h: usbotg-pwren-h {
+ pins {
+ pinmux = ;
+ bias-disable;
+ drive-push-pull;
+ };
+ };
+ };
+};
Pinctrl muxing has to be defined/declared in stm32f429.dtsi
This is board specific logic and it vary from board to board, should
it be defined here?
Pinmuxing definition is a SOC part (as it is a possibility offered by
SOC). Pinmuxing choice is board specific.
Regarding your code, it should not boot. Ex for disco:
+ gpio = <&gpiob 2 0>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&usbotg_pwren_h>;
+
usb-host {
>>> + usbotg_pwren_h: usbotg-pwren-h {
>>> + pins {
>>> + pinmux = ;
Indeed, you are declaring two time the pin PB2 (one time through pinctrl
and one other time through gpiolib). in strict mode you can't request 2
times the same Pin.
I assume that your driver want controls this GPIO (request/set direction
/ set, get value ...). in this case you only need to declare this part:
gpio = <&gpiob 2 0>;
The GPIO lib will deal with pinctrl framework for you.
And in this case, yes gpio declaration is board specific so this part
will be in board file.
Let me know, if I'm not enough clear.
Regards
Alex
diff --git a/arch/arm/boot/dts/stm32f429.dtsi
b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..bc07aa8 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -206,7 +206,7 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -316,6 +316,30 @@
};
};
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+
+
usbotg_hs_pins_a: usbot
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Hi Bruno,
On 01/16/2017 03:09 AM, Bruno Herrera wrote:
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.
Signed-off-by: Bruno Herrera
Sorry, but what is patch 1 & pacth 3 status ?
For this one, can split it in 3 patches (one patch for SOC and one for
each board) please.
---
arch/arm/boot/dts/stm32f429-disco.dts | 30 ++
arch/arm/boot/dts/stm32f429.dtsi | 35 ++-
arch/arm/boot/dts/stm32f469-disco.dts | 30 ++
3 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..374c5ed 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,16 @@
gpios = <&gpioa 0 0>;
};
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -99,3 +109,23 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ compatible = "st,stm32-fsotg", "snps,dwc2";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ usbotg_pwren_h: usbotg-pwren-h {
+ pins {
+ pinmux = ;
+ bias-disable;
+ drive-push-pull;
+ };
+ };
+ };
+};
Pinctrl muxing has to be defined/declared in stm32f429.dtsi
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..bc07aa8 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -206,7 +206,7 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -316,6 +316,30 @@
};
};
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
@@ -420,6 +444,15 @@
status = "disabled";
};
+ usbotg_fs: usb@5000 {
+ compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
+ reg = <0x5000 0x4>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 8877c00..8ae6763 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -68,6 +68,17 @@
soc {
dma-ranges = <0xc000 0x0 0x1000>;
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
Re: [PATCH v4 8/9] ARM: dts: stm32f4: Add external I2S clock
Hi
On 12/13/2016 03:20 PM, Gabriel FERNANDEZ wrote:
From: Gabriel Fernandez
This patch adds an external I2S clock in the DT.
The I2S clock could be derived from an external I2S clock or by I2S pll.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f429.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..7c7dfbd 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -68,6 +68,12 @@
compatible = "fixed-clock";
clock-frequency = <32000>;
};
+
+ clk_i2s_ckin: i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
};
soc {
@@ -362,7 +368,7 @@
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
- clocks = <&clk_hse>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
};
Applied on stm32-dt-for-v4.11
Thanks
Re: [PATCH v4 9/9] ARM: dts: stm32f4: Include auxiliary stm32fx clock definition
hi
On 12/13/2016 03:20 PM, Gabriel FERNANDEZ wrote:
From: Gabriel Fernandez
This patch include auxiliary clock definition (clocks which are not derived
from system clock.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f429.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 7c7dfbd..041e3fc 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -48,6 +48,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
+#include
/ {
clocks {
Applied on stm32-dt-for-v4.11
Thanks
Re: [PATCH 4/4] dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
Hi Gabriel
On 01/06/2017 02:59 PM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch lists STM32F7's RCC numeric constants.
It will be used by clock and reset drivers, and DT bindings.
Signed-off-by: Gabriel Fernandez
can you please split this commit ? (one part for binding and another for DT)
Thanks in advance
Alex
---
arch/arm/boot/dts/stm32f746.dtsi | 51
include/dt-bindings/mfd/stm32f7-rcc.h | 112 ++
2 files changed, 138 insertions(+), 25 deletions(-)
create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index e05e131..09d6649 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -44,6 +44,7 @@
#include "armv7-m.dtsi"
#include
#include
+#include
/ {
clocks {
@@ -77,7 +78,7 @@
compatible = "st,stm32-timer";
reg = <0x4000 0x400>;
interrupts = <28>;
- clocks = <&rcc 0 128>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
@@ -85,7 +86,7 @@
compatible = "st,stm32-timer";
reg = <0x4400 0x400>;
interrupts = <29>;
- clocks = <&rcc 0 129>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
@@ -93,7 +94,7 @@
compatible = "st,stm32-timer";
reg = <0x4800 0x400>;
interrupts = <30>;
- clocks = <&rcc 0 130>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
@@ -101,14 +102,14 @@
compatible = "st,stm32-timer";
reg = <0x4c00 0x400>;
interrupts = <50>;
- clocks = <&rcc 0 131>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
- clocks = <&rcc 0 132>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
@@ -116,7 +117,7 @@
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
- clocks = <&rcc 0 133>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
@@ -124,7 +125,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
- clocks = <&rcc 0 145>;
+ clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
@@ -132,7 +133,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
- clocks = <&rcc 0 146>;
+ clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
@@ -140,7 +141,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
- clocks = <&rcc 0 147>;
+ clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
@@ -148,7 +149,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
- clocks = <&rcc 0 148>;
+ clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
@@ -156,7 +157,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
- clocks = <&rcc 0 158>;
+ clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
@@ -164,7 +165,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
- clocks = <&rcc 0 159>;
+ clocks = <&rcc 1 CLK_UART8>;
Re: [PATCH 3/4] ARM: dts: stm32: stm32f7: Enable clocks for STM32F746 boards
Hi Gabriel
On 01/06/2017 02:59 PM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez
---
In commit header, "stm32f7" is not usefull.
arch/arm/boot/dts/stm32f746.dtsi | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f321ffe..e05e131 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -43,6 +43,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
+#include
This patch depends on another series not yet merged (maybe "[PATCH-next
... is a better header ?
/ {
clocks {
@@ -51,6 +52,24 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
+
+ clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_i2s_ckin: clk-i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4800>;
+ };
};
soc {
@@ -178,6 +197,11 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
};
+ pwrcfg: power-config@40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@@ -291,9 +315,10 @@
rcc: rcc@40023800 {
#clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
- clocks = <&clk_hse>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
};
};
};
Re: [PATCH v4 1/9] clk: stm32f4: Update DT bindings documentation
On 01/09/2017 08:33 PM, Stephen Boyd wrote: On 01/09, Alexandre Torgue wrote: Hi Stephen, On 12/22/2016 01:10 AM, Stephen Boyd wrote: On 12/13, gabriel.fernan...@st.com wrote: From: Gabriel Fernandez Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by: Gabriel Fernandez Acked-by: Rob Herring --- Applied to clk-stm32f4 and merged into clk-next. I'm preparing pull request branch for STM32 DT part. This patch is also requested to build correctly DT patches. Do you know how could we synchronize our pull request ? clk-stm32f4 is stable and not going to be rebased, so you're good to base patches on it and send it off to arm-soc if the arm-soc maintainers agree to it. You can also base off an earlier part of the branch if you only need this first patch for example. I will base my DT branch from 4.10-rc1 + this commit (seen with Arnd) Thanks
Re: [PATCH v4 1/9] clk: stm32f4: Update DT bindings documentation
Hi Stephen, On 12/22/2016 01:10 AM, Stephen Boyd wrote: On 12/13, gabriel.fernan...@st.com wrote: From: Gabriel Fernandez Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by: Gabriel Fernandez Acked-by: Rob Herring --- Applied to clk-stm32f4 and merged into clk-next. I'm preparing pull request branch for STM32 DT part. This patch is also requested to build correctly DT patches. Do you know how could we synchronize our pull request ? Thanks Alex
Re: [PATCH 1/3] ARM: configs: stm32: enable ADC driver
Hi Fabrice On 12/02/2016 02:57 PM, Fabrice GASNIER wrote: ADC driver depends on REGULATOR and IIO that are not yet selected. Current hardware boards (like stm32f429i-eval) is using fixed regulators. Signed-off-by: Fabrice Gasnier --- arch/arm/configs/stm32_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index a60b5cb..92ccc3c 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -49,6 +49,8 @@ CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -57,6 +59,9 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y +CONFIG_IIO=y +CONFIG_STM32_ADC_CORE=y +CONFIG_STM32_ADC=y # CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set Applied on stm32-defconfig-for-v4.11 Thanks. Alex
Re: [PATCH 3/3] ARM: dts: stm32: enable ADC on stm32f429i-eval board
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Enable analog to digital converter on stm32f429i-eval board.
It has on-board potentimeter wired to ADC3 in8 analog pin and
uses fixed regulator to provide reference voltage.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32429i-eval.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 13c7cd2..6be0a24 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -65,6 +65,20 @@
serial0 = &usart1;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_vref: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vref";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
green {
@@ -123,3 +137,14 @@
pinctrl-names = "default";
status = "okay";
};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc3_in8_pin>;
+ vref-supply = <®_vref>;
+ status = "okay";
+ adc3: adc@200 {
+ st,adc-channels = <8>;
+ status = "okay";
+ };
+};
After node reordering:
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [PATCH 2/3] ARM: dts: stm32: Add ADC support to stm32f429
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Add ADC support & pinctrl analog phandle (adc3_in8) to stm32f429.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32f429.dtsi | 49
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 3dd47eb..be1d970 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -172,6 +172,49 @@
status = "disabled";
};
+ adc: adc@40012000 {
+ compatible = "st,stm32f4-adc-core";
+ reg = <0x40012000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc 0 168>;
+ clock-names = "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ clocks = <&rcc 0 168>;
+ interrupt-parent = <&adc>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ clocks = <&rcc 0 169>;
+ interrupt-parent = <&adc>;
+ interrupts = <1>;
+ status = "disabled";
+ };
+
+ adc3: adc@200 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x200>;
+ clocks = <&rcc 0 170>;
+ interrupt-parent = <&adc>;
+ interrupts = <2>;
+ status = "disabled";
+ };
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
@@ -334,6 +377,12 @@
slew-rate = <2>;
};
};
+
+ adc3_in8_pin: adc@200 {
+ pins {
+ pinmux = ;
+ };
+ };
};
rcc: rcc@40023810 {
Applied on stm32-dt-for-v4.11
Thanks
Alex
Re: [RESEND PATCH v1] ARM: dts: stm32f429: Add missing USART3 pin config to STM32F469I-DISCO board
Hi Bruno,
On 11/18/2016 04:10 PM, Bruno Meirelles Herrera wrote:
Including new STM32 maintainer. Rebased at stm32-dt-for-v4.10-1 and
stm32-dt-for-v4.10-2 branches. It fix the port/pin initialization in
case boot-loader does not configure/initialize the pins.
Fixing line wrapping from last patch
This patch adds USART3 pin configuration on PB10/PA11 pins
for STM32F469I-DISCO board.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f429.dtsi | 13 +
arch/arm/boot/dts/stm32f469-disco.dts | 2 ++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..1b8b105 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -316,6 +316,19 @@
};
};
+ usart3_pins_a: usart3@0 {
+ pins1 {
+ pinmux =
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux =
;
+ bias-disable;
+ };
+ };
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 8877c00..75f4303 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -79,5 +79,7 @@
};
&usart3 {
+ pinctrl-0 = <&usart3_pins_a>;
+ pinctrl-names = "default";
status = "okay";
};
After a little cosmetic change in commit header:
Applied on stm32-dt-for-v4.11-1
Thanks!
Alex
Re: [RESEND PATCH] ARM: dts: stm32f469-disco: Fix memory size from 8MB to 16MB
Hi Bruno,
On 11/18/2016 03:58 PM, Bruno Meirelles Herrera wrote:
From: Bruno Herrera
This patch fix memory size to support 16MB of external SDRAM.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f469-disco.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 75f4303..fda12a4 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -58,7 +58,7 @@
};
memory {
- reg = <0x 0x80>;
+ reg = <0x 0x100>;
};
aliases {
After a little cosmetic change in commit header:
Applied on stm32-dt-for-v4.11-1
Thanks!
Alex
Re: [PATCH v6 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig
Hi Cedric, On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote: Signed-off-by: M'boumba Cedric Madianga Can you please add a commit message. Thx in advance Alex --- arch/arm/configs/stm32_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index e7b56d4..9494eaf 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,9 @@ CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y
Re: [PATCH v6 4/5] ARM: dts: stm32: Add I2C1 support for STM32429 eval board
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
Can you please add a commit message.
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index afb90bc..74e0045 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -141,3 +141,9 @@
pinctrl-names = "default";
status = "okay";
};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
Re: [PATCH v6 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: Patrice Chotard
Signed-off-by: M'boumba Cedric Madianga
Please Add a commit message.
---
arch/arm/boot/dts/stm32f429.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 7de52ee..cbdece7 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -48,6 +48,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
+#include
/ {
clocks {
@@ -337,6 +338,16 @@
slew-rate = <2>;
};
};
+
+ i2c1_pins_b: i2c1@0 {
+ pins1 {
+ pinmux = ;
+ drive-open-drain;
+ };
+ pins2 {
+ pinmux = ;
+ };
+ };
};
rcc: rcc@40023810 {
@@ -409,6 +420,18 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ i2c1: i2c@40005400 {
Can you check the order on device node please ? (should follow base@)
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+<32>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
Re: [PATCH net-next 0/2] Initial driver for Synopsys DWC XLGMAC
Hi On 12/07/2016 04:57 AM, Jie Deng wrote: This series provides the support for 25/40/50/100 GbE devices using Synopsys DWC Enterprise Ethernet (XLGMAC). Can you explain which GMAC are you targeted ? A driver which support some Synopsys GMAC IP already exists. It support GMAC 3.5, 3.7, 4.0, 4.10 versions. You can find it in: drivers/net/ethernet/stmicro/stmmac/. When I look at all files your gonna to create, it looks like to ones in stmmac driver so maybe you could easily add your IP inside stmmac driver. Note that an other driver is existing for synopsys GMAC 4.0 IP. it is located in drivers/net/ethernet/synopsys/dwc_eth_qos.c and coming from AXIS guys. A task is ongoing to only have stmmac driver so it should be harmful to create a new one. Regards Alex The first patch adds support for Synopsys XLGMII. The second patch provides the initial driver for Synopsys XLGMAC The driver has three layers by refactoring AMD XGBE. dwc-eth-xxx.x The DWC ethernet core layer (DWC ECL). This layer contains codes can be shared by different DWC series ethernet cores dwc-xxx.x (e.g. dwc-xlgmac.c) The DWC MAC HW adapter layer (DWC MHAL). This layer contains special support for a specific MAC. e.g. currently, XLGMAC. xxx-xxx-pci.c xxx-xxx-plat.c (e.g. dwc-xlgmac-pci.c) The glue adapter layer (GAL). Vendors who adopt Synopsys Etherent cores can develop a glue driver for their platform. Jie Deng (2): net: phy: add extension of phy-mode for XLGMII net: ethernet: Initial driver for Synopsys DWC XLGMAC Documentation/devicetree/bindings/net/ethernet.txt |1 + MAINTAINERS|6 + drivers/net/ethernet/synopsys/Kconfig |2 + drivers/net/ethernet/synopsys/Makefile |1 + drivers/net/ethernet/synopsys/dwc/Kconfig | 37 + drivers/net/ethernet/synopsys/dwc/Makefile |9 + drivers/net/ethernet/synopsys/dwc/dwc-eth-dcb.c| 228 ++ .../net/ethernet/synopsys/dwc/dwc-eth-debugfs.c| 328 +++ drivers/net/ethernet/synopsys/dwc/dwc-eth-desc.c | 715 + .../net/ethernet/synopsys/dwc/dwc-eth-ethtool.c| 567 drivers/net/ethernet/synopsys/dwc/dwc-eth-hw.c | 3098 drivers/net/ethernet/synopsys/dwc/dwc-eth-mdio.c | 252 ++ drivers/net/ethernet/synopsys/dwc/dwc-eth-net.c| 2319 +++ drivers/net/ethernet/synopsys/dwc/dwc-eth-ptp.c| 216 ++ drivers/net/ethernet/synopsys/dwc/dwc-eth-regacc.h | 1115 +++ drivers/net/ethernet/synopsys/dwc/dwc-eth.h| 738 + drivers/net/ethernet/synopsys/dwc/dwc-xlgmac-pci.c | 538 drivers/net/ethernet/synopsys/dwc/dwc-xlgmac.c | 135 + drivers/net/ethernet/synopsys/dwc/dwc-xlgmac.h | 85 + include/linux/phy.h|3 + 20 files changed, 10393 insertions(+) create mode 100644 drivers/net/ethernet/synopsys/dwc/Kconfig create mode 100644 drivers/net/ethernet/synopsys/dwc/Makefile create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-dcb.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-debugfs.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-desc.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-ethtool.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-hw.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-mdio.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-net.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-ptp.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth-regacc.h create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-eth.h create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-xlgmac-pci.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-xlgmac.c create mode 100644 drivers/net/ethernet/synopsys/dwc/dwc-xlgmac.h
Re: [PATCH v3 1/6] net: stmmac: return error if no DMA configuration is found
Hi David, On 12/08/2016 04:19 PM, David Miller wrote: From: Alexandre Torgue Date: Thu, 8 Dec 2016 11:44:35 +0100 Acked-by: Alexandre Torgue Typo in your email. I would suggest that you put this into an editor macro or similar in order to avoid such typos in the future. That's what people do who review a lot of patches. Sorry, I will pay attention next time.
Re: [PATCH v3 1/6] net: stmmac: return error if no DMA configuration is found
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
All drivers except pci glue layer calls stmmac_probe_config_dt.
stmmac_probe_config_dt does a kzalloc dma_cfg.
pci glue layer does kzalloc dma_cfg explicitly, so all current
drivers does a kzalloc dma_cfg.
Return an error if no DMA configuration is found, that way
we can assume that the DMA configuration always exists.
Signed-off-by: Niklas Cassel
Acked-by: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 982c95213da4..14366800e5e6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1578,16 +1578,12 @@ static void stmmac_check_ether_addr(struct stmmac_priv
*priv)
*/
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
{
- int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
- int mixed_burst = 0;
int atds = 0;
int ret = 0;
- if (priv->plat->dma_cfg) {
- pbl = priv->plat->dma_cfg->pbl;
- fixed_burst = priv->plat->dma_cfg->fixed_burst;
- mixed_burst = priv->plat->dma_cfg->mixed_burst;
- aal = priv->plat->dma_cfg->aal;
+ if (!priv->plat->dma_cfg) {
+ dev_err(priv->device, "DMA configuration not found\n");
+ return -EINVAL;
}
if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
@@ -1599,8 +1595,12 @@ static int stmmac_init_dma_engine(struct stmmac_priv
*priv)
return ret;
}
- priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
- aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
+ priv->hw->dma->init(priv->ioaddr,
+ priv->plat->dma_cfg->pbl,
+ priv->plat->dma_cfg->fixed_burst,
+ priv->plat->dma_cfg->mixed_burst,
+ priv->plat->dma_cfg->aal,
+ priv->dma_tx_phy, priv->dma_rx_phy, atds);
if (priv->synopsys_id >= DWMAC_CORE_4_00) {
priv->rx_tail_addr = priv->dma_rx_phy +
Re: [PATCH v3 6/6] net: smmac: allow configuring lower pbl values
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to allow the DT to configure lower pbl values, while at the
same time not changing behavior of any existing device trees using the
pbl/txpbl/rxpbl settings, add a property to disable the multiplication
of the pbl by 8/4 in the hardware.
Suggested-by: Rabin Vincent
Signed-off-by: Niklas Cassel
Thanks for this patch, you can add my Acked-by.
Thanks for the whole series.
Alex
---
Documentation/devicetree/bindings/net/stmmac.txt | 2 ++
Documentation/networking/stmmac.txt | 5 -
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 3 ++-
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 3 ++-
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 2 ++
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
include/linux/stmmac.h| 1 +
7 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
b/Documentation/devicetree/bindings/net/stmmac.txt
index 8080038ff1b2..128da752fec9 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -39,6 +39,8 @@ Optional properties:
If set, DMA tx will use this value rather than snps,pbl.
- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer.
If set, DMA rx will use this value rather than snps,pbl.
+- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8.
+ For core rev < 3.50, don't multiply the values by 4.
- snps,aal Address-Aligned Beats
- snps,fixed-burst Program the DMA to use the fixed burst mode
- snps,mixed-burst Program the DMA to use the mixed burst mode
diff --git a/Documentation/networking/stmmac.txt
b/Documentation/networking/stmmac.txt
index 6add57374f70..2bb07078f535 100644
--- a/Documentation/networking/stmmac.txt
+++ b/Documentation/networking/stmmac.txt
@@ -152,8 +152,9 @@ Where:
o dma_cfg: internal DMA parameters
o pbl: the Programmable Burst Length is maximum number of beats to
be transferred in one DMA transaction.
- GMAC also enables the 4xPBL by default.
+ GMAC also enables the 4xPBL by default. (8xPBL for GMAC 3.50 and newer)
o txpbl/rxpbl: GMAC and newer supports independent DMA pbl for tx/rx.
+ o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default.
o fixed_burst/mixed_burst/aal
o clk_csr: fixed CSR Clock range selection.
o has_gmac: uses the GMAC core.
@@ -208,6 +209,7 @@ struct stmmac_dma_cfg {
int pbl;
int txpbl;
int rxpbl;
+ bool pblx8;
int fixed_burst;
int mixed_burst;
bool aal;
@@ -219,6 +221,7 @@ Where:
If set, DMA tx will use this value rather than pbl.
o rxpbl: Receive Programmable Burst Length. Only for GMAC and newer.
If set, DMA rx will use this value rather than pbl.
+ o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default.
o fixed_burst: program the DMA to use the fixed burst mode
o mixed_burst: program the DMA to use the mixed burst mode
o aal: Address-Aligned Beats
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 99b8040af592..612d3aaac9a4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -98,7 +98,8 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
* Note: before stmmac core 3.50 this mode bit was 4xPBL, and
* post 3.5 mode bit acts as 8*PBL.
*/
- value |= DMA_BUS_MODE_MAXPBL;
+ if (dma_cfg->pblx8)
+ value |= DMA_BUS_MODE_MAXPBL;
value |= DMA_BUS_MODE_USP;
value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 2c3b2098f350..8196ab5fc33c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -84,7 +84,8 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr,
* on each channel
*/
value = readl(ioaddr + DMA_CHAN_CONTROL(channel));
- value = value | DMA_BUS_MODE_PBL;
+ if (dma_cfg->pblx8)
+ value = value | DMA_BUS_MODE_PBL;
writel(value, ioaddr + DMA_CHAN_CONTROL(channel));
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
index 56c8a2342c14..a2
Re: [PATCH v3 5/6] net: stmmac: add support for independent DMA pbl for tx/rx
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid, but
snps,txpbl/snps,rxpbl will override the value in snps,pbl if set.
If the IP is synthesized to use the AXI interface, there is a register
and a matching DT property inside the optional stmmac-axi-config DT node
for controlling burst lengths, named snps,blen.
However, using this register, it is not possible to control tx and rx
independently. Also, this register is not available if the IP was
synthesized with, e.g., the AHB interface.
Signed-off-by: Niklas Cassel
Thanks, you can add my Acked-by.
Regards
Alex
---
Documentation/devicetree/bindings/net/stmmac.txt | 6 +-
Documentation/networking/stmmac.txt | 19 +--
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 12 ++--
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++-
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 ++
include/linux/stmmac.h| 2 ++
6 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
b/Documentation/devicetree/bindings/net/stmmac.txt
index b95ff998ba73..8080038ff1b2 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -34,7 +34,11 @@ Optional properties:
platforms.
- tx-fifo-depth: See ethernet.txt file in the same directory
- rx-fifo-depth: See ethernet.txt file in the same directory
-- snps,pbl Programmable Burst Length
+- snps,pbl Programmable Burst Length (tx and rx)
+- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer.
+ If set, DMA tx will use this value rather than snps,pbl.
+- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer.
+ If set, DMA rx will use this value rather than snps,pbl.
- snps,aal Address-Aligned Beats
- snps,fixed-burst Program the DMA to use the fixed burst mode
- snps,mixed-burst Program the DMA to use the mixed burst mode
diff --git a/Documentation/networking/stmmac.txt
b/Documentation/networking/stmmac.txt
index 014f4f756cb7..6add57374f70 100644
--- a/Documentation/networking/stmmac.txt
+++ b/Documentation/networking/stmmac.txt
@@ -153,7 +153,8 @@ Where:
o pbl: the Programmable Burst Length is maximum number of beats to
be transferred in one DMA transaction.
GMAC also enables the 4xPBL by default.
- o fixed_burst/mixed_burst/burst_len
+ o txpbl/rxpbl: GMAC and newer supports independent DMA pbl for tx/rx.
+ o fixed_burst/mixed_burst/aal
o clk_csr: fixed CSR Clock range selection.
o has_gmac: uses the GMAC core.
o enh_desc: if sets the MAC will use the enhanced descriptor structure.
@@ -205,16 +206,22 @@ tuned according to the HW capabilities.
struct stmmac_dma_cfg {
int pbl;
+ int txpbl;
+ int rxpbl;
int fixed_burst;
- int burst_len_supported;
+ int mixed_burst;
+ bool aal;
};
Where:
- o pbl: Programmable Burst Length
+ o pbl: Programmable Burst Length (tx and rx)
+ o txpbl: Transmit Programmable Burst Length. Only for GMAC and newer.
+If set, DMA tx will use this value rather than pbl.
+ o rxpbl: Receive Programmable Burst Length. Only for GMAC and newer.
+If set, DMA rx will use this value rather than pbl.
o fixed_burst: program the DMA to use the fixed burst mode
- o burst_len: this is the value we put in the register
- supported values are provided as macros in
- linux/stmmac.h header file.
+ o mixed_burst: program the DMA to use the mixed burst mode
+ o aal: Address-Aligned Beats
---
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 318ae9f10104..99b8040af592 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -89,20 +89,20 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
u32 dma_tx, u32 dma_rx, int atds)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
+ int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
+ int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
/*
* Set the DMA PBL (Programmable Burst Length) mode.
*
* Note: before stmmac core 3.50 this mode bit was 4xPBL, and
* post 3.5 mode bit acts as 8*PBL.
-*
-* This configuration doesn't take care about the Separate PBL
-* so only the bits: 13-8 are programmed with the PBL passed from the
-* platform.
*/
value |= DMA_BUS_MODE_MAXPBL;
- value &= ~DMA_BUS_MODE_PBL_MASK;
-
Re: [PATCH v3 3/6] net: stmmac: stmmac_platform: fix parsing of DT binding
Hi
On 12/08/2016 10:46 AM, Niklas Cassel wrote:
On 12/08/2016 10:02 AM, Alexandre Torgue wrote:
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl existed or not.
After the commit, fixed burst and mixed burst are only parsed if
snps,pbl exists. Now when snps,aal has been added, it too is only
parsed if snps,pbl exists.
Since the DT binding does not specify that fixed burst, mixed burst
or aal depend on snps,pbl being specified, undo changes introduced
by 64c3b252e9fc.
The issue commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with
DT") tries to address is solved in another way:
The databook specifies that all values other than
1, 2, 4, 8, 16, or 32 results in undefined behavior,
so snps,pbl = <0> is invalid.
If pbl is 0 after parsing, set pbl to DEFAULT_DMA_PBL.
This handles the case where the property is omitted, and also handles
the case where the property is specified without any data.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +--
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 29 +++---
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index b1e42ddf0370..b5188122bc15 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1581,8 +1581,8 @@ static int stmmac_init_dma_engine(struct stmmac_priv
*priv)
int atds = 0;
int ret = 0;
-if (!priv->plat->dma_cfg) {
-dev_err(priv->device, "DMA configuration not found\n");
+if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
How "priv->plat->dma_cfg->pbl" could be equal to 0 if you force it to DEFAULT_DMA_PBL in
"stmmac_probe_config_dt" in case of DT doesn't set pbl value?
The PCI glue code does not call stmmac_probe_config_dt.
Also any glue driver could override the value set by stmmac_probe_config_dt
before calling stmmac_dvr_probe. So I guess if we want any trustworthy
sanity-checking, it actually has to be done in stmmac_main.c.
Ok I see, it is more safe. You can add my Acked-by.
Thanks
Alex
+dev_err(priv->device, "Invalid DMA configuration\n");
return -EINVAL;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index d3b6f92f350a..81800f23a9c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -304,21 +304,22 @@ stmmac_probe_config_dt(struct platform_device *pdev,
const char **mac)
plat->force_sf_dma_mode = 1;
}
-if (of_find_property(np, "snps,pbl", NULL)) {
-dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
- GFP_KERNEL);
-if (!dma_cfg) {
-stmmac_remove_config_dt(pdev, plat);
-return ERR_PTR(-ENOMEM);
-}
-plat->dma_cfg = dma_cfg;
-of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
-dma_cfg->aal = of_property_read_bool(np, "snps,aal");
-dma_cfg->fixed_burst =
-of_property_read_bool(np, "snps,fixed-burst");
-dma_cfg->mixed_burst =
-of_property_read_bool(np, "snps,mixed-burst");
+dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
+ GFP_KERNEL);
+if (!dma_cfg) {
+stmmac_remove_config_dt(pdev, plat);
+return ERR_PTR(-ENOMEM);
}
+plat->dma_cfg = dma_cfg;
+
+of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
+if (!dma_cfg->pbl)
+dma_cfg->pbl = DEFAULT_DMA_PBL;
+
+dma_cfg->aal = of_property_read_bool(np, "snps,aal");
+dma_cfg->fixed_burst = of_property_read_bool(np, "snps,fixed-burst");
+dma_cfg->mixed_burst = of_property_read_bool(np, "snps,mixed-burst");
+
plat->force_thresh_dma_mode = of_property_read_bool(np,
"snps,force_thresh_dma_mode");
if (plat->force_thresh_dma_mode) {
plat->force_sf_dma_mode = 0;
Re: [PATCH v3 4/6] net: stmmac: dwmac1000: fix define DMA_BUS_MODE_RPBL_MASK
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index ff3e5ab39bd0..52b9407a8a39 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -225,7 +225,7 @@ enum rx_tx_priority_ratio {
#define DMA_BUS_MODE_FB0x0001 /* Fixed burst */
#define DMA_BUS_MODE_MB0x0400 /* Mixed burst */
-#define DMA_BUS_MODE_RPBL_MASK 0x003e /* Rx-Programmable Burst Len */
+#define DMA_BUS_MODE_RPBL_MASK 0x007e /* Rx-Programmable Burst Len */
Well spot. You can add my Acked-by.
Regards
Alex
#define DMA_BUS_MODE_RPBL_SHIFT17
#define DMA_BUS_MODE_USP 0x0080
#define DMA_BUS_MODE_MAXPBL0x0100
Re: [PATCH v3 3/6] net: stmmac: stmmac_platform: fix parsing of DT binding
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl existed or not.
After the commit, fixed burst and mixed burst are only parsed if
snps,pbl exists. Now when snps,aal has been added, it too is only
parsed if snps,pbl exists.
Since the DT binding does not specify that fixed burst, mixed burst
or aal depend on snps,pbl being specified, undo changes introduced
by 64c3b252e9fc.
The issue commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with
DT") tries to address is solved in another way:
The databook specifies that all values other than
1, 2, 4, 8, 16, or 32 results in undefined behavior,
so snps,pbl = <0> is invalid.
If pbl is 0 after parsing, set pbl to DEFAULT_DMA_PBL.
This handles the case where the property is omitted, and also handles
the case where the property is specified without any data.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +--
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 29 +++---
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index b1e42ddf0370..b5188122bc15 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1581,8 +1581,8 @@ static int stmmac_init_dma_engine(struct stmmac_priv
*priv)
int atds = 0;
int ret = 0;
- if (!priv->plat->dma_cfg) {
- dev_err(priv->device, "DMA configuration not found\n");
+ if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
How "priv->plat->dma_cfg->pbl" could be equal to 0 if you force it to
DEFAULT_DMA_PBL in "stmmac_probe_config_dt" in case of DT doesn't set
pbl value?
+ dev_err(priv->device, "Invalid DMA configuration\n");
return -EINVAL;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index d3b6f92f350a..81800f23a9c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -304,21 +304,22 @@ stmmac_probe_config_dt(struct platform_device *pdev,
const char **mac)
plat->force_sf_dma_mode = 1;
}
- if (of_find_property(np, "snps,pbl", NULL)) {
- dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
- GFP_KERNEL);
- if (!dma_cfg) {
- stmmac_remove_config_dt(pdev, plat);
- return ERR_PTR(-ENOMEM);
- }
- plat->dma_cfg = dma_cfg;
- of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
- dma_cfg->aal = of_property_read_bool(np, "snps,aal");
- dma_cfg->fixed_burst =
- of_property_read_bool(np, "snps,fixed-burst");
- dma_cfg->mixed_burst =
- of_property_read_bool(np, "snps,mixed-burst");
+ dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
+ GFP_KERNEL);
+ if (!dma_cfg) {
+ stmmac_remove_config_dt(pdev, plat);
+ return ERR_PTR(-ENOMEM);
}
+ plat->dma_cfg = dma_cfg;
+
+ of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
+ if (!dma_cfg->pbl)
+ dma_cfg->pbl = DEFAULT_DMA_PBL;
+
+ dma_cfg->aal = of_property_read_bool(np, "snps,aal");
+ dma_cfg->fixed_burst = of_property_read_bool(np, "snps,fixed-burst");
+ dma_cfg->mixed_burst = of_property_read_bool(np, "snps,mixed-burst");
+
plat->force_thresh_dma_mode = of_property_read_bool(np,
"snps,force_thresh_dma_mode");
if (plat->force_thresh_dma_mode) {
plat->force_sf_dma_mode = 0;
Re: [PATCH v3 2/6] net: stmmac: simplify the common DMA init API
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel
Thanks for this patch. You can add my Acked-by.
Regards
Alex
---
drivers/net/ethernet/stmicro/stmmac/common.h| 4 ++--
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 13 +++--
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 7 ---
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c| 14 --
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
5 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 3ced2e1703c1..b13a144f72ad 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -412,8 +412,8 @@ extern const struct stmmac_desc_ops ndesc_ops;
struct stmmac_dma_ops {
/* DMA core initialization */
int (*reset)(void __iomem *ioaddr);
- void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
-int aal, u32 dma_tx, u32 dma_rx, int atds);
+ void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
+u32 dma_tx, u32 dma_rx, int atds);
/* Configure the AXI Bus Mode Register */
void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
/* Dump DMA registers */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index f35385266fbf..318ae9f10104 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -84,8 +84,9 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct
stmmac_axi *axi)
writel(value, ioaddr + DMA_AXI_BUS_MODE);
}
-static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
- int aal, u32 dma_tx, u32 dma_rx, int atds)
+static void dwmac1000_dma_init(void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ u32 dma_tx, u32 dma_rx, int atds)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -101,20 +102,20 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, int
pbl, int fb, int mb,
*/
value |= DMA_BUS_MODE_MAXPBL;
value &= ~DMA_BUS_MODE_PBL_MASK;
- value |= (pbl << DMA_BUS_MODE_PBL_SHIFT);
+ value |= (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT);
/* Set the Fixed burst mode */
- if (fb)
+ if (dma_cfg->fixed_burst)
value |= DMA_BUS_MODE_FB;
/* Mixed Burst has no effect when fb is set */
- if (mb)
+ if (dma_cfg->mixed_burst)
value |= DMA_BUS_MODE_MB;
if (atds)
value |= DMA_BUS_MODE_ATDS;
- if (aal)
+ if (dma_cfg->aal)
value |= DMA_BUS_MODE_AAL;
writel(value, ioaddr + DMA_BUS_MODE);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index 61f54c99a7de..e5664da382f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -32,11 +32,12 @@
#include "dwmac100.h"
#include "dwmac_dma.h"
-static void dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
- int aal, u32 dma_tx, u32 dma_rx, int atds)
+static void dwmac100_dma_init(void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ u32 dma_tx, u32 dma_rx, int atds)
{
/* Enable Application Access by writing to DMA CSR0 */
- writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
+ writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
ioaddr + DMA_BUS_MODE);
/* Mask interrupts by writing to CSR7 */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index e81b6e565c29..7d82a3464097 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -99,27 +99,29 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr,
int pbl,
writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
}
-static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
- int aal, u32 dma_tx, u32 dma_rx, int atds)
+static void dwmac4_dma_init(void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ u32 dma_tx, u32 dma_rx, int atds)
{
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
int i;
/* Set the Fixed burst mode */
- if (fb)
+ if (dma_cfg->fixed_burs
Re: [PATCH v5 4/5] ARM: dts: Add I2C1 support for STM32429 eval board
Hi Cedric,
On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
Can you change the commit header by: ARM: dts: stm32: Add I2C1 support
for STM32429 eval board
thx
Alex
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index afb90bc..74e0045 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -141,3 +141,9 @@
pinctrl-names = "default";
status = "okay";
};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
Re: [PATCH v5 5/5] ARM: configs: Add I2C support for STM32 defconfig
Hi Cedric, On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote: Signed-off-by: M'boumba Cedric Madianga --- arch/arm/configs/stm32_defconfig | 3 +++ 1 file changed, 3 insertions(+) Can you change the commit header by ARM: configs: stm32: Add I2C support Thx alex diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index e7b56d4..9494eaf 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,9 @@ CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT
Hi Lee,
On 12/06/2016 10:48 AM, Lee Jones wrote:
On Mon, 05 Dec 2016, Alexandre Torgue wrote:
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware capabilities
- do not use references for pwm and iio timer subnodes
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f429.dtsi | 333 +-
arch/arm/boot/dts/stm32f469-disco.dts | 28 +++
2 files changed, 360 insertions(+), 1 deletion(-)
[...]
If you're only commenting on a little piece of the patch, it's always
a good idea to trim the rest.
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 8a163d7..df4ca7e 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -81,3 +81,31 @@
&usart3 {
status = "okay";
};
+
+&gptimer1 {
+ status = "okay";
+
+ pwm1@0 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer1@0 {
+ status = "okay";
+ };
+};
This is a much *better* format than before.
I still don't like the '&' syntax though.
Please keep "&" format to match with existing nodes.
Right. I wasn't suggesting that he differs from the current format in
*this* set. I am suggesting that we change the format in a subsequent
set though.
Why change? Looking at Linux ARM kernel patchwork, new DT board file
contains this format. Did you already discuss with Arnd or Olof about it
?
regards
Alex
+&gptimer3 {
+ status = "okay";
+
+ pwm3@0 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer3@0 {
+ status = "okay";
+ };
+};
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT
Hi,
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware capabilities
- do not use references for pwm and iio timer subnodes
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f429.dtsi | 333 +-
arch/arm/boot/dts/stm32f469-disco.dts | 28 +++
2 files changed, 360 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index bca491d..8c50d03 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -48,7 +48,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
-
+#include
/ {
clocks {
clk_hse: clk-hse {
@@ -355,6 +355,21 @@
slew-rate = <2>;
};
};
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = ,
+
,
+
;
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = ,
+;
+ };
+ };
};
rcc: rcc@40023810 {
@@ -426,6 +441,322 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ gptimer1: gptimer1@4001 {
timer@xxx
Node names should be generic and not numbered.
I suggest that this isn't actually a timer either. Is contains a
timer (and a PWM), but in it's completeness it is not a timer per
say.
+ compatible = "st,stm32-gptimer";
+ reg = <0x4001 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+ status = "disabled";
+
+ pwm1@0 {
+ compatible = "st,stm32-pwm";
+ st,pwm-num-chan = <4>;
+ st,breakinput;
+ st,complementary;
+ status = "disabled";
+ };
+
+ timer1@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <27>;
+ st,input-triggers-names = TIM5_TRGO,
+ TIM2_TRGO,
+ TIM4_TRGO,
+ TIM3_TRGO;
I'm still dubious with matching by strings.
I'll take a look at the C code to see what the alternatives could be.
+ st,output-triggers-names = TIM1_TRGO,
+ TIM1_CH1,
+ TIM1_CH2,
+ TIM1_CH3,
+ TIM1_CH4;
+ status = "disabled";
+ };
+ };
+
+ gptimer2: gptimer2@4000 {
+ compatible = "st,stm32-gptimer";
+ reg = <0x4000 0x400>;
+ clocks = <&rcc 0 128>;
+ clock-names = "clk_int";
+ status = "disabled";
+
+ pwm2@0 {
+ compatible = "st,stm32-pwm";
+ st,pwm-num-chan = <4>;
+ st,32bits-counter;
+ status = "disabled";
+ };
+
+ timer2@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <28>;
+ st,input-triggers-names = TIM1_TRGO,
+ TIM8_TRGO,
+ TIM3_TRGO,
+ TIM4_TRGO;
+ st,output-triggers-names = TIM2_TRGO,
+ TIM2_CH1,
+ TIM2_CH2,
+ TIM2_CH3,
+
Re: stmmac ethernet in kernel 4.9-rc6: coalescing related pauses.
Hi Pavel and Peppe,
On 12/02/2016 02:51 PM, Giuseppe CAVALLARO wrote:
On 12/2/2016 1:32 PM, Pavel Machek wrote:
Hi!
Well, if you have a workload that sends and receive packets, it tends
to work ok, as you do tx_clean() in stmmac_poll(). My workload is not
like that -- it is "sending packets at 3MB/sec, receiving none". So
the stmmac_tx_timer() is rescheduled and rescheduled and rescheduled,
and then we run out of transmit descriptors, and then 40msec passes,
and then we clean them. Bad.
And that's why low-res timers do not cut it.
in that case, I expect that the tuning of the driver could help you.
I mean, by using ethtool, it could be enough to set the IC bit on all
the descriptors. You should touch the tx_coal_frames.
Then you can use ethtool -S to monitor the status.
Yes, I did something similar. Unfortnunately that meant crash within
minutes, at least with 4.4 kernel. (If you know what was fixed between
4.4 and 4.9, that would be helpful).
4.4 has no GMAC4 support.
Alex, do you remember any patches to fix that?
No sorry Peppe.
Pavel,
Sorry but I'm a little bit confused. I'm dropped in some mails without
historic. I see cleanup, coalescence issue and TSO question.
What is your main issue? Are you working on gmac4 or 3.x ?
Can you refresh a little bit the story please ?
Regards
Alex
We had experimented this tuning on STB IP where just datagrams
had to send externally. To be honest, although we had seen
better results w/o any timer, we kept this approach enabled
because the timer was fast enough to cover our tests on SH4 boxes.
Please reply to David, and explain how it is supposed to
work... because right now it does not. 40 msec delays are not
acceptable in default configuration.
I mean, that on UP and SMP system this schema helped
to improve the performance saving CPU on my side and this has been
tested since a long time (~4 years).
I tested something similar to yours where unidirectional traffic
with limited throughput was needed and I can confirm you that
tuning/removing coalesce parameters this helped. The tuning I decided
to keep in the driver was suitable in several user cases and if now
you have problems or you want to review it I can just confirm that
there are no problems on my side. If you want to simply the logic
around the tx process and remove timer on official driver I can accept
that. I will just ask you uto double check if the throughput and
CPU usage when request max throughput (better if on GiGa setup) has
no regressions.
Otherwise we could start thinking about adaptive schema if feasible.
In the ring, some descriptors can raise the irq (according to a
threshold) and set the IC bit. In this path, the NAPI poll will be
scheduled.
Not NAPI poll but stmmac_tx_timer(), right?
in the xmit according the the threshold the timer is started or the
interrupt is set inside the descriptor.
Then stmmac_tx_clean will be always called and, if you see the flow,
no irqlock protection is needed!
Agreed that no irqlock protection is needed if we rely on napi and
timers.
ok
Concerning the lock protection, we had reviewed long time ago and
IIRC, no raise condition should be present. Open to review it,
again!
...
There's nothing that protect stmmac_poll() from running concurently
with stmmac_dma_interrupt(), right?
This is not necessary.
dma_interrupt accesses shared priv->xstats; variables are of type
unsigned long (not atomic_t), yet they are accesssed from interrupt
context and from stmmac_ethtool without any locking. That can result
in broken statistics AFAICT.
ok we can check this and welcome patches and I'd prefer to
remove xstats from critical part of the code like ISR (that
comes from old story of the driver).
Please take another look. As far as I can tell, you can have two cpus
at #1 and #2 in the code, at the same time. It looks like napi_... has
some atomic opertions inside so that looks safe at the first look. But
I'm not sure if they also include enough memory barriers to make it
safe...?
Although I have never reproduced related issues on SMP platforms
due to reordering of memory operations but, as said above, welcome
review on this especially if you are seeing problems when manage NAPI.
FYI, the only memory barrier you will see in the driver are about the
OWN_BIT setting till now.
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
{
...
status = priv->hw->dma->dma_interrupt(priv->ioaddr,
&priv->xstats);
if (likely((status & handle_rx)) || (status & handle_tx)) {
if (likely(napi_schedule_prep(&priv->napi))) {
#1
stmmac_disable_dma_irq(priv);
__napi_schedule(&priv->napi);
}
}
static int stmmac_poll(struct napi_struct *napi, int budget)
{
struct stmmac_priv *priv = container_of(napi, struct
stmmac_priv, napi);
int work_done = 0;
priv->xstats.napi_poll++;
stmmac_tx_clean(priv);
work_done
Re: [PATCH] stmmac: reduce code duplication getting basic descriptors
Hi Pavel,
On 11/28/2016 01:17 PM, Pavel Machek wrote:
Remove code duplication getting basic descriptors.
I agree with your patch, it will make code easier to understand.
After fix kbuild issue you can add my Acked-by;
Regards
Alex
Signed-off-by: Pavel Machek
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index f7133d0..ed20668 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -929,6 +929,17 @@ static int stmmac_set_bfsize(int mtu, int bufsize)
return ret;
}
+static inline struct dma_desc *stmmac_tx_desc(struct stmmac_priv *priv, int i)
+{
+ struct dma_desc *p;
+ if (priv->extend_desc)
+ p = &((priv->dma_etx + i)->basic);
+ else
+ p = priv->dma_tx + i;
+ return p;
+}
+
+
/**
* stmmac_clear_descriptors - clear descriptors
* @priv: driver private structure
@@ -1078,11 +1089,7 @@ static int init_dma_desc_rings(struct net_device *dev,
gfp_t flags)
/* TX INITIALIZATION */
for (i = 0; i < DMA_TX_SIZE; i++) {
- struct dma_desc *p;
- if (priv->extend_desc)
- p = &((priv->dma_etx + i)->basic);
- else
- p = priv->dma_tx + i;
+ struct dma_desc *p = stmmac_tx_desc(priv, i);
if (priv->synopsys_id >= DWMAC_CORE_4_00) {
p->des0 = 0;
@@ -1129,12 +1136,7 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv)
int i;
for (i = 0; i < DMA_TX_SIZE; i++) {
- struct dma_desc *p;
-
- if (priv->extend_desc)
- p = &((priv->dma_etx + i)->basic);
- else
- p = priv->dma_tx + i;
+ struct dma_desc *p = stmmac_tx_desc(priv, i);
if (priv->tx_skbuff_dma[i].buf) {
if (priv->tx_skbuff_dma[i].map_as_page)
@@ -1314,14 +1316,9 @@ static void __stmmac_tx_clean(struct stmmac_priv *priv)
while (entry != priv->cur_tx) {
struct sk_buff *skb = priv->tx_skbuff[entry];
- struct dma_desc *p;
+ struct dma_desc *p = stmmac_tx_desc(priv, entry);
int status;
- if (priv->extend_desc)
- p = (struct dma_desc *)(priv->dma_etx + entry);
- else
- p = priv->dma_tx + entry;
-
status = priv->hw->desc->tx_status(&priv->dev->stats,
&priv->xstats, p,
priv->ioaddr);
@@ -2227,11 +2224,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb,
struct net_device *dev)
csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
- if (likely(priv->extend_desc))
- desc = (struct dma_desc *)(priv->dma_etx + entry);
- else
- desc = priv->dma_tx + entry;
-
+ desc = stmmac_tx_desc(priv, entry);
first = desc;
priv->tx_skbuff[first_entry] = skb;
@@ -2254,10 +2247,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb,
struct net_device *dev)
entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
- if (likely(priv->extend_desc))
- desc = (struct dma_desc *)(priv->dma_etx + entry);
- else
- desc = priv->dma_tx + entry;
+ desc = stmmac_tx_desc(priv, entry);
des = skb_frag_dma_map(priv->device, frag, 0, len,
DMA_TO_DEVICE);
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT
Hi Benjamin,
On 12/02/2016 11:17 AM, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware capabilities
- do not use references for pwm and iio timer subnodes
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32f429.dtsi | 333 +-
arch/arm/boot/dts/stm32f469-disco.dts | 28 +++
2 files changed, 360 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index bca491d..8c50d03 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -48,7 +48,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
-
+#include
/ {
clocks {
clk_hse: clk-hse {
@@ -355,6 +355,21 @@
slew-rate = <2>;
};
};
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = ,
+
,
+
;
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = ,
+;
+ };
+ };
};
rcc: rcc@40023810 {
@@ -426,6 +441,322 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ gptimer1: gptimer1@4001 {
Currently, nodes are ordered following base address.
+ compatible = "st,stm32-gptimer";
+ reg = <0x4001 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+ status = "disabled";
+
+ pwm1@0 {
+ compatible = "st,stm32-pwm";
+ st,pwm-num-chan = <4>;
+ st,breakinput;
+ st,complementary;
+ status = "disabled";
+ };
+
+ timer1@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <27>;
+ st,input-triggers-names = TIM5_TRGO,
+ TIM2_TRGO,
+ TIM4_TRGO,
+ TIM3_TRGO;
+ st,output-triggers-names = TIM1_TRGO,
+ TIM1_CH1,
+ TIM1_CH2,
+ TIM1_CH3,
+ TIM1_CH4;
+ status = "disabled";
+ };
+ };
+
+ gptimer2: gptimer2@4000 {
+ compatible = "st,stm32-gptimer";
+ reg = <0x4000 0x400>;
+ clocks = <&rcc 0 128>;
+ clock-names = "clk_int";
+ status = "disabled";
+
+ pwm2@0 {
+ compatible = "st,stm32-pwm";
+ st,pwm-num-chan = <4>;
+ st,32bits-counter;
+ status = "disabled";
+ };
+
+ timer2@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <28>;
+ st,input-triggers-names = TIM1_TRGO,
+ TIM8_TRGO,
+ TIM3_TRGO,
+ TIM4_TRGO;
+ st,output-triggers-names = TIM2_TRGO,
+ TIM2_CH1,
+ TIM2_CH2,
+ TIM2_CH3,
+ TIM2_CH4;
+ status = "disabled";
+ };
+ };
+
+ gptimer3: gptimer3@4400 {
+ compatible = "st,stm32-gptimer";
+ reg = <0x4400 0x400>;
+ clocks =
Re: [PATCH] net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
Hi David and Niklas, On 11/28/2016 05:29 PM, David Miller wrote: From: Niklas Cassel Date: Thu, 24 Nov 2016 15:36:33 +0100 From: Niklas Cassel The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W. Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1. The driver does still not utilize more than one tx queue in the IP. Signed-off-by: Niklas Cassel Alexandre, we are still waiting for your implicit/explicit ACK on this change. Yes you could add my Acked-by but it is already merged. My fault. Sorry for my late answer :( Thank you.
Re: [PATCH] net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
Hi Niklas
On 11/25/2016 01:14 PM, Niklas Cassel wrote:
On 11/25/2016 01:10 PM, Niklas Cassel wrote:
On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
Hi Niklas,
Hello Alexandre
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized
with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 3 +++
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 6f4f5ce25114..3e8d4fefa5e0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -155,8 +155,11 @@ enum power_event {
#define MTL_CHAN_RX_DEBUG(x)(MTL_CHANX_BASE_ADDR(x) + 0x38)
#define MTL_OP_MODE_RSFBIT(5)
+#define MTL_OP_MODE_TXQENBIT(3)
#define MTL_OP_MODE_TSFBIT(1)
+#define MTL_OP_MODE_TQS_MASKGENMASK(24, 16)
+
#define MTL_OP_MODE_TTC_MASK0x70
#define MTL_OP_MODE_TTC_SHIFT4
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 116151cd6a95..577316de6ba8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr,
int txmode,
else
mtl_tx_op |= MTL_OP_MODE_TTC_512;
}
-
+/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
+ * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+ * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+ * with reset values: TXQEN off, TQS 256 bytes.
+ *
+ * Write the bits in both cases, since it will have no effect when RO.
+ * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+ * be RO, however, writing the whole TQS field will result in a value
+ * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+ */
+mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several
values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W
■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video
Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved
Do you plan to manage av mode in a future patch ?
We are not planning on using the AV mode.
We will probably not use TXQ1 at all.
I noticed that the MAC_HW_Feature2 Register actually has a TXQCNT field.
It is currently saved in priv->dma_cap.number_tx_channel.
If you prefer, I could do a patch V2 where we only set the bits if
priv->dma_cap.number_tx_channel > 1
Oh, sorry, that was number of tx _channels_,
not number of tx _queues_.
However, we could add a number_tx_queue to struct dma_features,
if you would prefer that.
I agree your patch is good. It will work even if we use several tx
channels. We will see in the future for AV mode.
regards
alex
However, I don't think the current patch is too bad either, since the bits
are RO when number_tx_channel == 1.
Regards
Alex
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
Re: [PATCH] net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
Hi Niklas,
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized
with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 3 +++
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 6f4f5ce25114..3e8d4fefa5e0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -155,8 +155,11 @@ enum power_event {
#define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
#define MTL_OP_MODE_RSFBIT(5)
+#define MTL_OP_MODE_TXQEN BIT(3)
#define MTL_OP_MODE_TSFBIT(1)
+#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
+
#define MTL_OP_MODE_TTC_MASK 0x70
#define MTL_OP_MODE_TTC_SHIFT 4
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 116151cd6a95..577316de6ba8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr,
int txmode,
else
mtl_tx_op |= MTL_OP_MODE_TTC_512;
}
-
+ /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
+* with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+* For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+* with reset values: TXQEN off, TQS 256 bytes.
+*
+* Write the bits in both cases, since it will have no effect when RO.
+* For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+* be RO, however, writing the whole TQS field will result in a value
+* equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+*/
+ mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2
can take several values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W
■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video
Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved
Do you plan to manage av mode in a future patch ?
Regards
Alex
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
Re: [PATCH 4/4] net: stmmac: stmmac_platform: use correct setup function for gmac4
Hi Niklas,
On 11/23/2016 03:25 PM, Niklas Cassel wrote:
From: Niklas Cassel
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Previously, when specifying "snps,dwmac-4.10a", "snps,dwmac" as your
compatible string, plat_stmmacenet_data would have both has_gmac and
has_gmac4 set.
This would lead to stmmac_hw_init calling dwmac1000_setup rather than
dwmac4_setup, resulting in a non-functional driver.
This happened since the check for has_gmac is done before the check for
has_gmac4. However, the order should not matter, so it does not make sense
to have both set.
Well spot.
If something is valid for both, you should do as the stmmac_interrupt does:
if (priv->plat->has_gmac || priv->plat->has_gmac4) ...
The places where it was obvious that the author actually meant
if (has_gmac || has_gmac4) rather than if (has_gmac) has been updated.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 4 ++--
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index d5a8122b6033..dd5b38e4cd1f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -263,7 +263,7 @@ static void stmmac_ethtool_getdrvinfo(struct net_device
*dev,
{
struct stmmac_priv *priv = netdev_priv(dev);
- if (priv->plat->has_gmac)
+ if (priv->plat->has_gmac || priv->plat->has_gmac4)
strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
else
strlcpy(info->driver, MAC100_ETHTOOL_NAME,
@@ -448,7 +448,7 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
memset(reg_space, 0x0, REG_SPACE_SIZE);
- if (!priv->plat->has_gmac) {
+ if (!(priv->plat->has_gmac || priv->plat->has_gmac4)) {
/* MAC registers */
for (i = 0; i < 12; i++)
reg_space[i] = readl(priv->ioaddr + (i * 4));
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 4d544c34c1f2..c8a59f396c6e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -291,6 +291,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const
char **mac)
if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
of_device_is_compatible(np, "snps,dwmac-4.10a")) {
plat->has_gmac4 = 1;
+ plat->has_gmac = 0;
plat->pmt = 1;
plat->tso_en = of_property_read_bool(np, "snps,tso");
}
Thanks Niklas, Acked-by:
Regards
Alex
Re: [PATCH 1/4] bindings: net: stmmac: correct note about TSO
Hi Niklas, On 11/23/2016 03:24 PM, Niklas Cassel wrote: From: Niklas Cassel snps,tso was previously placed under AXI BUS Mode parameters, suggesting that the property should be in the stmmac-axi-config node. TSO (TCP Segmentation Offloading) has nothing to do with AXI BUS Mode parameters, and the parser actually expects it to be in the root node, not in the stmmac-axi-config. Also added a note about snps,tso only being available on GMAC4 and newer. Signed-off-by: Niklas Cassel --- Documentation/devicetree/bindings/net/stmmac.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index 41b49e6075f5..b95ff998ba73 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@ -1,7 +1,7 @@ * STMicroelectronics 10/100/1000 Ethernet driver (GMAC) Required properties: -- compatible: Should be "snps,dwmac-" "snps,dwmac" +- compatible: Should be "snps,dwmac-", "snps,dwmac" For backwards compatibility: "st,spear600-gmac" is also supported. - reg: Address and length of the register set for the device - interrupt-parent: Should be the phandle for the interrupt controller @@ -50,6 +50,8 @@ Optional properties: - snps,ps-speed: port selection speed that can be passed to the core when PCS is supported. For example, this is used in case of SGMII and MAC2MAC connection. +- snps,tso: this enables the TSO feature otherwise it will be managed by +MAC HW capability register. Only for GMAC4 and newer. - AXI BUS Mode parameters: below the list of all the parameters to program the AXI register inside the DMA module: - snps,lpi_en: enable Low Power Interface @@ -62,8 +64,6 @@ Optional properties: - snps,fb: fixed-burst - snps,mb: mixed-burst - snps,rb: rebuild INCRx Burst - - snps,tso: this enables the TSO feature otherwise it will be managed by - MAC HW capability register. - mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. Examples: Acked-by:
Re: [PATCH 7/7] add stm32 multi-functions timer driver in DT
Hi Benjamin,
On 11/22/2016 05:13 PM, Benjamin Gaignard wrote:
Add timers MFD and childs into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard
If you have to send a v2 for this series please change commit header by:
"ARM: dts: stm32: ..." (if not I will do it by myself)
---
arch/arm/boot/dts/stm32f429.dtsi | 246 ++
arch/arm/boot/dts/stm32f469-disco.dts | 29
2 files changed, 275 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index bca491d..28a0fe9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -355,6 +355,21 @@
slew-rate = <2>;
};
};
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = ,
+
,
+
;
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = ,
+;
+ };
+ };
};
rcc: rcc@40023810 {
@@ -426,6 +441,237 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ mfd_timer1: mfdtimer1@4001 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x4001 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+ status = "disabled";
+
+ pwm1: pwm1@4001 {
+ compatible = "st,stm32-pwm1";
+ status = "disabled";
+ };
+
+ iiotimer1: iiotimer1@4001 {
+ compatible = "st,stm32-iio-timer1";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer2: mfdtimer2@4000 {
+ compatible = "st,stm32-mfd-timer2";
+ reg = <0x4000 0x400>;
+ clocks = <&rcc 0 128>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <28>;
+ status = "disabled";
+
+ pwm2: pwm2@4000 {
+ compatible = "st,stm32-pwm2";
+ status = "disabled";
+ };
+ iiotimer2: iiotimer2@4000 {
+ compatible = "st,stm32-iio-timer2";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer3: mfdtimer3@4400 {
+ compatible = "st,stm32-mfd-timer3";
+ reg = <0x4400 0x400>;
+ clocks = <&rcc 0 129>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <29>;
+ status = "disabled";
+
+ pwm3: pwm3@4400 {
+ compatible = "st,stm32-pwm3";
+ status = "disabled";
+ };
+ iiotimer3: iiotimer3@4400 {
+ compatible = "st,stm32-iio-timer3";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer4: mfdtimer4@4800 {
+ compatible = "st,stm32-mfd-timer4";
+ reg = <0x4800 0x400>;
+ clocks = <&rcc 0 130>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <30>;
+ status = "disabled";
+
+ pwm4: pwm4@4800 {
+ compatible = "st,stm32-pwm4";
+ status = "disabled";
+ };
+ iiotimer4: iiotimer4@4800 {
+ compatible = "st,stm32-iio-timer4";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer5: mfdtimer5@4C00 {
+ compatible = "st,stm32-mfd-timer5";
+ reg = <0x4C00 0x400>;
+ clocks = <&rcc 0 131>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <50>;
+ status = "disabled";
+
+
Re: [PATCH 1/2] ARM: dts: stm32f429: add LSI and LSE clocks
Gabriel,
On 11/04/2016 09:52 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable these clocks.
Is it the same than you sent in last series ? If yes I will take it
directly as review has already been done.
regards
Alex
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f429.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4f..2700449 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -56,6 +56,18 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
+
+ clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
};
soc {
@@ -185,6 +197,11 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
};
+ pwrcfg: power-config@40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@@ -340,6 +357,7 @@
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
};
dma1: dma-controller@40026000 {
Re: [PATCH v2 6/6] ARM: dts: stm32f429: Add QSPI clock
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds the QSPI clock for stm32f469 discovery board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f469-disco.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index e911af8..4052023 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,10 @@
};
};
+&rcc {
+ compatible = "st,stm32f469-rcc", "st,stm32-rcc";
+};
+
With this patch, stm32f469-disco doesn't boot if clk drivers patch are
not applied.
Can you please send a new version to keep compatibility with older clk
driver.
&rcc {
> + compatible = "st,stm32f469-rcc", "st,stm32-rcc";
-> compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
> +};
> +
I will take it in next pull request round.
Regards
Alex
&clk_hse {
clock-frequency = <800>;
};
Re: [PATCH v2 0/6] STM32F4 Add RTC & QSPI clocks
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
v2:
- rename compatible property "st,stm32f46xx-rcc" into "st,stm32f469-rcc"
- cosmetic: remove bad copy/paste
This patch-set introduce RTC and QSPI clocks for STM32F4 socs
RTC clock has 3 parents clock oscillators (lsi/lse/hse_rtc)
example to use rtc clock:
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
...
clocks = <&rcc 1 CLK_RTC>;
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
...
};
Gabriel Fernandez (6):
clk: stm32f4: Add LSI & LSE clocks
ARM: dts: stm32f429: add LSI and LSE clocks
arm: stmf32: Enable SYSCON
clk: stm32f4: Add RTC clock
clk: stm32f469: Add QSPI clock
ARM: dts: stm32f429: Add QSPI clock
You sent a V3 without DT patches. Should I take DT patches from this V2
patchset ?
Regards
Alex
.../devicetree/bindings/clock/st,stm32-rcc.txt | 4 +-
arch/arm/boot/dts/stm32f429.dtsi | 18 +
arch/arm/boot/dts/stm32f469-disco.dts | 4 +
arch/arm/configs/stm32_defconfig | 1 +
drivers/clk/clk-stm32f4.c | 442 -
5 files changed, 447 insertions(+), 22 deletions(-)
Re: [PATCH (net.git) 0/3] stmmac: fix PTP support
Hi Peppe, On 10/26/2016 08:56 AM, Giuseppe Cavallaro wrote: This subset of patches aim to fix the PTP support for the stmmac and especially for 4.x chip series. While setting PTP on an ST box with 4.00a Ethernet core, the kernel panics due to a broken settings of the descriptors. The patches review the register configuration, the algo used for configuring the protocol, the way to get the timestamp inside the RX/TX descriptors and, in the end, the statistics displayed by ethtool. Giuseppe Cavallaro (3): stmmac: update the PTP header file stmmac: fix PTP support for GMAC4 stmmac: fix PTP type ethtool stats drivers/net/ethernet/stmicro/stmmac/common.h | 24 +++--- drivers/net/ethernet/stmicro/stmmac/descs.h| 20 +++-- drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 95 - drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h | 4 + drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 28 --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 19 +++-- .../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 43 -- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 97 +++--- drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 9 +- drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 72 11 files changed, 260 insertions(+), 152 deletions(-) For the series: Acked-by: Alexandre Torgue Thanks Alex
Re: ERROR: "bad_dma_ops" [drivers/tty/serial/stm32-usart.ko] undefined!
Hi Greg, On 10/23/2016 11:54 AM, kbuild test robot wrote: Hi Alexandre, First bad commit (maybe != root cause): tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 0c2b6dc4fd4fa13796b319aae969a009f03222c6 commit: 3489187204eb75e5635d8836babfd0a18be613f4 serial: stm32: adding dma support date: 4 weeks ago config: m32r-allmodconfig (attached as .config) compiler: m32r-linux-gcc (GCC) 6.2.0 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 3489187204eb75e5635d8836babfd0a18be613f4 # save the attached .config to linux build tree make.cross ARCH=m32r All errors (new ones prefixed by >>): ERROR: "bad_dma_ops" [sound/soc/bcm/snd-soc-cygnus.ko] undefined! ERROR: "bad_dma_ops" [sound/core/snd-pcm.ko] undefined! ERROR: "dma_common_mmap" [sound/core/snd-pcm.ko] undefined! ERROR: "bad_dma_ops" [drivers/tty/serial/stm32-usart.ko] undefined! This issue will be fixed by patch: "[PATCH] serial: SERIAL_STM32 should depend on HAS_DMA" sent by Geert Uytterhoeven. Regards Alex
[PATCH 0/2] STM32 pinctrl: remove dependency between pinctrl driver and device tree
Hi, Currently 4.9-rc1 is not booting correctly on STM32F4. By adding gpios irqs support to stm32 pinctrl, a dependency has been added between pinctrl stm32 and stm32f4 device tree (my mistake). This series breaks this dependency and has to be taken on 4.9_rcs. Regards Alex Alexandre TORGUE (2): pinctrl: stm32: remove dependency with interrupt controller pinctrl: stm32: move gpio irqs binding to optional Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 10 +- drivers/pinctrl/stm32/pinctrl-stm32.c | 8 +--- 2 files changed, 10 insertions(+), 8 deletions(-) -- 1.9.1
[PATCH 2/2] pinctrl: stm32: move gpio irqs binding to optional
stm32 pinctrl driver could be probed even if no interrupt controller is defined to manage gpio irqs. Entries related to gpio irq management are moved to optional. Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index f9753c4..b24583a 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -14,11 +14,6 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). - - interrupt-parent: phandle of the interrupt parent to which the external - GPIO interrupts are forwarded to. - - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node - which includes IRQ mux selection register, and the offset of the IRQ mux - selection register. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. @@ -37,6 +32,11 @@ Required properties: Optional properties: - reset:: Reference to the reset controller + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node + which includes IRQ mux selection register, and the offset of the IRQ mux + selection register. Example: #include -- 1.9.1
[PATCH 1/2] pinctrl: stm32: remove dependency with interrupt controller
This patch allows to probe stm32 pinctrl driver even if no interrupt
controller is defined to manage gpio irqs.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 200667f..efc4371 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -1092,9 +1092,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
return -EINVAL;
}
- ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
- if (ret)
- return ret;
+ if (of_find_property(np, "interrupt-parent", NULL)) {
+ ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+ if (ret)
+ return ret;
+ }
for_each_child_of_node(np, child)
if (of_property_read_bool(child, "gpio-controller"))
--
1.9.1
Re: [PATCH] Reorganize STM32 clocks in order to prepare them for PLLI2S and PLLSAI
Hi Radoslaw, I add Gabriel in the discussion. Gabriel is updating PLL management for STM32F429. Regards Alex On 10/10/2016 12:31 PM, Daniel Thompson wrote: On 10/10/16 10:56, Radosław Pietrzyk wrote: Hi, all plls have the same clock parent which is after a main divider. Currently the divider and multiplier are connected together within vco clock and therefore there is no chance to reuse the divider and clearly state where the conncetion "really" is. We can arrange all of them separately but than the divider will be hidden for all of them separately. Quoting my last mail "I can see the value of naming the "/M" pre-division separately". In other words I agree with the idea of the patch. To more explicitly state my review comments... From: Radoslaw Pietrzyk Please add a explanation of the problem and solution in the patch description. Signed-off-by: Radoslaw Pietrzyk --- drivers/clk/clk-stm32f4.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 02d6810..1fd3eac 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -245,9 +245,10 @@ static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk) const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk; unsigned long pllq = (pllcfgr >> 24) & 0xf; -clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm); -clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp); -clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); +clk_register_fixed_factor(NULL, "vco-div", pllsrc, 0, 1, pllm); This strikes me as a bad name for a clock that is shared by all three PLLs (the vco being an internal component of the PLL) however since the clock is not named in the datasheet we are forced to invent a name [I suspect that's why I gave up trying to name it when I wrote the driver originally ;-) ]. Perhaps "pllin-prediv"? +clk_register_fixed_factor(NULL, "vco-mul", "vco-div", 0, plln, 1); Why rename this clock? Multiplying is a what the vco (and its control circuits) is *for*. Tagging it "-mul" is meaningless. Daniel.
Re: [PATCH] serial: SERIAL_STM32 should depend on HAS_DMA
Hi Geert, On 10/06/2016 03:55 PM, Geert Uytterhoeven wrote: If NO_DMA=y: drivers/built-in.o: In function `stm32_serial_remove': stm32-usart.c:(.text+0xcea1a): undefined reference to `bad_dma_ops' stm32-usart.c:(.text+0xcea7a): undefined reference to `bad_dma_ops' Add a dependency on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven --- drivers/tty/serial/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index c7831407a882d2bb..25c1d7bc010043b1 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1625,6 +1625,7 @@ config SERIAL_SPRD_CONSOLE config SERIAL_STM32 tristate "STMicroelectronics STM32 serial port support" select SERIAL_CORE + depends on HAS_DMA depends on ARM || COMPILE_TEST help This driver is for the on-chip Serial Controller on I sent same kind of patch this morning (but mine have a bad copy paste). I will abandon my patch. However for this one: Acked-by: Alexandre Torgue regards Alex
[tip:irq/core] ARM/dts: Add EXTI controller node to stm32f429
Commit-ID: 5a79d596378b65e773d93d00edcb57a33f87ea94
Gitweb: http://git.kernel.org/tip/5a79d596378b65e773d93d00edcb57a33f87ea94
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:59 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
ARM/dts: Add EXTI controller node to stm32f429
Originally-from: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Thompson
Cc: Jason Cooper
Cc: a...@arndb.de
Cc: Marc Zyngier
Cc: bruherr...@gmail.com
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
Cc: Rob Herring
Cc: lee.jo...@linaro.org
Cc: linux-arm-ker...@lists.infradead.org
Link:
http://lkml.kernel.org/r/1474387259-18926-5-git-send-email-alexandre.tor...@st.com
Signed-off-by: Thomas Gleixner
---
arch/arm/boot/dts/stm32f429.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
reg = <0x40013800 0x400>;
};
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>,
<23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
[tip:irq/core] ARM/STM32: Select external interrupts controller
Commit-ID: 47f91519546ce39cceee2c51b0f5045eadc688a9 Gitweb: http://git.kernel.org/tip/47f91519546ce39cceee2c51b0f5045eadc688a9 Author: Alexandre TORGUE AuthorDate: Tue, 20 Sep 2016 18:00:58 +0200 Committer: Thomas Gleixner CommitDate: Wed, 21 Sep 2016 14:13:21 +0200 ARM/STM32: Select external interrupts controller Originally-from: Maxime Coquelin Signed-off-by: Alexandre TORGUE Cc: Mark Rutland Cc: devicet...@vger.kernel.org Cc: Daniel Thompson Cc: Jason Cooper Cc: a...@arndb.de Cc: Marc Zyngier Cc: bruherr...@gmail.com Cc: Linus Walleij Cc: linux-g...@vger.kernel.org Cc: Rob Herring Cc: lee.jo...@linaro.org Cc: linux-arm-ker...@lists.infradead.org Link: http://lkml.kernel.org/r/1474387259-18926-4-git-send-email-alexandre.tor...@st.com Signed-off-by: Thomas Gleixner --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a9c4e48..bc9d6df 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -878,6 +878,7 @@ config ARCH_STM32 select CLKSRC_STM32 select PINCTRL select RESET_CONTROLLER + select STM32_EXTI help Support for STMicroelectronics STM32 processors.
[tip:irq/core] drivers/irqchip: Add STM32 external interrupts support
Commit-ID: e072041688ca73f125719815fa4b0fd23a45152c
Gitweb: http://git.kernel.org/tip/e072041688ca73f125719815fa4b0fd23a45152c
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:57 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
drivers/irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.
Originally-from: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Thompson
Cc: Jason Cooper
Cc: a...@arndb.de
Cc: Marc Zyngier
Cc: bruherr...@gmail.com
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
Cc: Rob Herring
Cc: lee.jo...@linaro.org
Cc: linux-arm-ker...@lists.infradead.org
Link:
http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.tor...@st.com
Signed-off-by: Thomas Gleixner
---
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-stm32-exti.c | 201 +++
3 files changed, 206 insertions(+)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9aeea1d..329c941 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -265,3 +265,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+ bool
+ select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..491568c
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EXTI_IMR 0x0
+#define EXTI_EMR 0x4
+#define EXTI_RTSR 0x8
+#define EXTI_FTSR 0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
+ struct irq_chip_generic *gc = domain->gc->gc[0];
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long pending;
+ int n;
+
+ chained_irq_enter(chip, desc);
+
+ while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+ for_each_set_bit(n, &pending, BITS_PER_LONG) {
+ generic_handle_irq(irq_find_mapping(domain, n));
+ irq_reg_writel(gc, BIT(n), EXTI_PR);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 rtsr, ftsr;
+
+ irq_gc_lock(gc);
+
+ rtsr = irq_reg_readl(gc, EXTI_RTSR);
+ ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ rtsr |= BIT(pin);
+ ftsr &= ~BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ rtsr &= ~BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ rtsr |= BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ default:
+ irq_gc_unlock(gc);
+ return -EINVAL;
+ }
+
+ irq_reg_writel(gc, rtsr, EXTI_RTSR);
+ irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 emr;
+
+ irq_gc_lock(gc);
+
+ emr = irq_reg_readl(gc, EXTI_EMR);
+ if (on)
+ emr |= BIT(pin);
+ else
+ emr &= ~BIT(pin);
+ irq_reg_writel(gc, emr, EXTI_EMR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs, v
[tip:irq/core] Documentation/dt-bindings: Document STM32 EXTI controller bindings
Commit-ID: 3027f78bb7243bef28c103507fc857e1471d769d
Gitweb: http://git.kernel.org/tip/3027f78bb7243bef28c103507fc857e1471d769d
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:56 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
Documentation/dt-bindings: Document STM32 EXTI controller bindings
Originally-from: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Thompson
Cc: Jason Cooper
Cc: a...@arndb.de
Cc: Marc Zyngier
Cc: bruherr...@gmail.com
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
Cc: Rob Herring
Cc: lee.jo...@linaro.org
Cc: linux-arm-ker...@lists.infradead.org
Link:
http://lkml.kernel.org/r/1474387259-18926-2-git-send-email-alexandre.tor...@st.com
Signed-off-by: Thomas Gleixner
---
.../bindings/interrupt-controller/st,stm32-exti.txt | 20
1 file changed, 20 insertions(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+ specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
+};
Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support
Hi Thomas, On 09/20/2016 10:16 PM, Thomas Gleixner wrote: Alexandre, On Tue, 20 Sep 2016, Alexandre TORGUE wrote: The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, falling or both edges. Each line can also be masked independently. Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE That all looks very reasonable now. The only remaining question is your SOB chain. Who is the author of these patches? You or Maxime? If it's Maxime, then the changelog misses a From: tag. If it's you then Maximes SOB is bogus. Actually Maxime wrote the main part of this driver and sent version 1 and 2 of the series. After Linus W. reviews, rework was required to use hierarchical domain. According to Maxime, I coded the rework (adaptation to hierarchical domain) and sent other version of the series. Regards Alex Thanks, tglx
[PATCH v6 4/4] ARM: dts: Add EXTI controller node to stm32f429
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
reg = <0x40013800 0x400>;
};
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>,
<23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
--
1.9.1
[PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+ bool
+ select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..491568c
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EXTI_IMR 0x0
+#define EXTI_EMR 0x4
+#define EXTI_RTSR 0x8
+#define EXTI_FTSR 0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
+ struct irq_chip_generic *gc = domain->gc->gc[0];
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long pending;
+ int n;
+
+ chained_irq_enter(chip, desc);
+
+ while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+ for_each_set_bit(n, &pending, BITS_PER_LONG) {
+ generic_handle_irq(irq_find_mapping(domain, n));
+ irq_reg_writel(gc, BIT(n), EXTI_PR);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 rtsr, ftsr;
+
+ irq_gc_lock(gc);
+
+ rtsr = irq_reg_readl(gc, EXTI_RTSR);
+ ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ rtsr |= BIT(pin);
+ ftsr &= ~BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ rtsr &= ~BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ rtsr |= BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ default:
+ irq_gc_unlock(gc);
+ return -EINVAL;
+ }
+
+ irq_reg_writel(gc, rtsr, EXTI_RTSR);
+ irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 emr;
+
+ irq_gc_lock(gc);
+
+ emr = irq_reg_readl(gc, EXTI_EMR);
+ if (on)
+ emr |= BIT(pin);
+ else
+ emr &= ~BIT(pin);
+ irq_reg_writel(gc, emr, EXTI_EMR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct irq_chip_generic *gc = d->gc->gc[0];
+ struct irq_fwspec *fwspec = data;
+ irq_hw_number_t hwirq;
+
+ hwirq = fwspec->param[0];
+
+ irq_map_generic_chip(d, virq, hwirq);
+ irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
+ handle_simple_irq, NULL, NULL);
+
+ return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_domain_get_irq_data(d, virq);
+
+ irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+ .map= irq_map_generic_chip,
+ .xlate = irq_domain_xlate_onetwocell,
+ .alloc = stm32_exti_alloc,
+ .free = stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+ struct d
[PATCH v6 3/4] ARM: STM32: Select external interrupts controller
Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d601d7..157cea9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -877,6 +877,7 @@ config ARCH_STM32 select CLKSRC_STM32 select PINCTRL select RESET_CONTROLLER + select STM32_EXTI help Support for STMicroelectronics STM32 processors. -- 1.9.1
[PATCH v6 0/4] Add STM32 EXTI interrupt controller support
Hi, This v6 fix useless mask in .free callback of stm32 exti driver (thanks Thomas). I resend only patches concerning STM32 EXTI driver (as pinctrl part has already been applied by Linus W.) The series adds support to EXTI interrupt controller and GPIO IRQ support in STM32 pinctrl driver. The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, fallin or both edges. Each line can also be masked independently. Regards Alex Changes since v5: - - Fix .free callback according to Thomas Changes since v4: - - Fix bad copy/paste in stm32 exti driver - Remove GPIOLIB_IRQCHIP config in stm32 pinctrl driver Changes since v3: - - Review domain dealloc/free irq in stm32 pinctrl driver - Review domain dealloc/free irq in stm32 exti driver - Fix remarks on coding style Changes since v2: - - Define irq_chip for GPIO banks - Use hierarchical domain for GPIO banks - Improve search loop inside stm32_exti handler - Rebased on top of v4.8-rc1 Changes since v1: - - Rebased on top of v4.6-rc1 - Change variable name from virq to irq (Linus W.) Alexandre TORGUE (4): Documentation: dt-bindings: Document STM32 EXTI controller bindings drivers: irqchip: Add STM32 external interrupts support ARM: STM32: Select external interrupts controller ARM: dts: Add EXTI controller node to stm32f429 .../interrupt-controller/st,stm32-exti.txt | 20 ++ arch/arm/Kconfig | 1 + arch/arm/boot/dts/stm32f429.dtsi | 8 + drivers/irqchip/Kconfig| 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-stm32-exti.c | 201 + 6 files changed, 235 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt create mode 100644 drivers/irqchip/irq-stm32-exti.c -- 1.9.1
[PATCH v6 1/4] Documentation: dt-bindings: Document STM32 EXTI controller bindings
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+ specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
+};
--
1.9.1
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Thomas,
On 09/20/2016 04:02 PM, Thomas Gleixner wrote:
On Tue, 20 Sep 2016, Alexandre Torgue wrote:
On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
Free will be called when a interrupt in the child domain is torn down,
i.e. when irq_domain_free_irqs() is called. And it will be called for both
domains like the alloc callback is invoked on both domains via
irq_domain_alloc_irqs().
Thanks Thomas for this clarification (I'm sure now that we need .free
callbacks).
irq_domain_free_irqs() is called in 2 scenario:
1- when issue occurs in irq_create_fwspec_mapping()
2- when irq_dispose_mapping() is called
Case 2 is the one I tested some times ago. In this case, I need to mask
interrupts in .free callback of EXTI (parent) domain to avoid spurious
interrupts.
And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
interrupt? The masking is just papering over that.
Ok. So my test was wrong and irq_dispose_mapping() has to be called when
irq is masked (for example just after free_irq()). For sure in this
case the mask inside exti free callback has no sens (catch :))
I will change .free callback by:
static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(d, virq);
irq_domain_reset_irq_data(data);
}
so if you agree I will resend only patches concerning stm32 exti driver
[1],[2],[3],[4]
Thanks for your time.
alex
Thanks,
tglx
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Thomas, On 09/20/2016 02:44 PM, Thomas Gleixner wrote: On Tue, 20 Sep 2016, Alexandre Torgue wrote: Thomas, On 09/20/2016 11:51 AM, Thomas Gleixner wrote: On Tue, 20 Sep 2016, Alexandre Torgue wrote: On 09/14/2016 03:34 PM, Thomas Gleixner wrote: Well, you just used some function in some context which is not relevant to the normal operation. So adding that mask() is just paranoia for no value. A gentle reminder ping... If ".free" callback is not relevant then I 'll remove it from exti domain. Sorry for discussing about the same thing again (and again) but I just want to be sure before sending a new version. As you know I have 2 domains: EXTI domain (parent) and stm32-pinctrl-bank domain (child one). There does it make sens to have ".free" callbacks defined in both domain (actually if I define one for the child domain I have to define also ".free" callback for parent domain (EXTI) as it is hierarchical) ? If ".free" have no chance to be called then I will send a new version by removing .free callbacks (in both domain). Free will be called when a interrupt in the child domain is torn down, i.e. when irq_domain_free_irqs() is called. And it will be called for both domains like the alloc callback is invoked on both domains via irq_domain_alloc_irqs(). Thanks Thomas for this clarification (I'm sure now that we need .free callbacks). irq_domain_free_irqs() is called in 2 scenario: 1- when issue occurs in irq_create_fwspec_mapping() 2- when irq_dispose_mapping() is called Case 2 is the one I tested some times ago. In this case, I need to mask interrupts in .free callback of EXTI (parent) domain to avoid spurious interrupts. Regards Alex Thanks, tglx
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Thomas, On 09/20/2016 11:51 AM, Thomas Gleixner wrote: On Tue, 20 Sep 2016, Alexandre Torgue wrote: On 09/14/2016 03:34 PM, Thomas Gleixner wrote: Well, you just used some function in some context which is not relevant to the normal operation. So adding that mask() is just paranoia for no value. A gentle reminder ping... If ".free" callback is not relevant then I 'll remove it from exti domain. Sorry for discussing about the same thing again (and again) but I just want to be sure before sending a new version. As you know I have 2 domains: EXTI domain (parent) and stm32-pinctrl-bank domain (child one). There does it make sens to have ".free" callbacks defined in both domain (actually if I define one for the child domain I have to define also ".free" callback for parent domain (EXTI) as it is hierarchical) ? If ".free" have no chance to be called then I will send a new version by removing .free callbacks (in both domain). Regards Alex I was not talking about the .free callback in general. I was talking about the masking. But yes, if the thing is otherwise a NOOP, then you can spare it completely. Thanks, tglx
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Hi Thomas, On 09/14/2016 03:44 PM, Alexandre Torgue wrote: On 09/14/2016 03:34 PM, Thomas Gleixner wrote: On Wed, 14 Sep 2016, Alexandre Torgue wrote: On 09/14/2016 11:19 AM, Thomas Gleixner wrote: Now what really bugs me is that you do that at all. An interrupt which is freed must be masked already. Why is it unmasked in the first place? Honestly I don't know. When "devm_free_irq" is called to release virq, there is no issue and interrupt is well masked. But, when I tried to use "irq_dispose_mapping(virq)" I observed that .free is called (child and parent domain) but interrupt is not masked. Well, you just used some function in some context which is not relevant to the normal operation. So adding that mask() is just paranoia for no value. A gentle reminder ping... If ".free" callback is not relevant then I 'll remove it from exti domain. I agree. I just wanted to "force" a test for .free callback. If it not relevant I'll remove ".free" callback of exti domain. As a part of this series has already been taken by Linus (pinctrl part), I will send a new series only for irqchip part (patches [1] and [2]). Do you agree ? Thanks in advance Alex Thanks Alex Thanks, tglx ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
On 09/14/2016 03:34 PM, Thomas Gleixner wrote: On Wed, 14 Sep 2016, Alexandre Torgue wrote: On 09/14/2016 11:19 AM, Thomas Gleixner wrote: Now what really bugs me is that you do that at all. An interrupt which is freed must be masked already. Why is it unmasked in the first place? Honestly I don't know. When "devm_free_irq" is called to release virq, there is no issue and interrupt is well masked. But, when I tried to use "irq_dispose_mapping(virq)" I observed that .free is called (child and parent domain) but interrupt is not masked. Well, you just used some function in some context which is not relevant to the normal operation. So adding that mask() is just paranoia for no value. I agree. I just wanted to "force" a test for .free callback. If it not relevant I'll remove ".free" callback of exti domain. As a part of this series has already been taken by Linus (pinctrl part), I will send a new series only for irqchip part (patches [1] and [2]). Do you agree ? Thanks Alex Thanks, tglx
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Hi Thomas,
On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
On Tue, 13 Sep 2016, Alexandre Torgue wrote:
On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_get_irq_data(virq);
+
+ irq_gc_mask_clr_bit(data->parent_data);
I have a hard time to understand this. The irq domain is not hierarchical.
Actually, I wanted to test ".free" callback function of gpio_irq_domain in
STM32 pinctrl driver. To do that I modified gpio driver: just after getting
virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.
Doing that, I see that ".free" callback of gpio domain is called but as it is
hirerchical ".free" callback for parent domain (exti one) is also called. I
observed that virq was well unmapped, but not masked at exti level. It is for
this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
interrupt at exti level.
Aargh. I really misread the patch, but this is entirely non obvious and you
should do:
struct irq_data *data = irq_domain_get_irq_data(d, virq);
irq_gc_mask_clr_bit(d);
Then it is entirely clear that you mask the interrupt of _this_ (the exti)
domain.
Ok, it's easier to understand like that.
Now what really bugs me is that you do that at all. An interrupt which is
freed must be masked already. Why is it unmasked in the first place?
Honestly I don't know. When "devm_free_irq" is called to release virq,
there is no issue and interrupt is well masked. But, when I tried to use
"irq_dispose_mapping(virq)" I observed that .free is called (child and
parent domain) but interrupt is not masked.
Regards
Alex
Thanks,
tglx
Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
Hi Thomas,
On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_get_irq_data(virq);
+
+ irq_gc_mask_clr_bit(data->parent_data);
I have a hard time to understand this. The irq domain is not hierarchical.
Actually, I wanted to test ".free" callback function of gpio_irq_domain
in STM32 pinctrl driver. To do that I modified gpio driver: just after
getting virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.
Doing that, I see that ".free" callback of gpio domain is called but as
it is hirerchical ".free" callback for parent domain (exti one) is also
called. I observed that virq was well unmapped, but not masked at exti
level. It is for this reason than I added
"irq_gc_mask_clr_bit(data->parent_data);" which mask interrupt at exti
level.
Maybe this use case can never happen ? (and in this case all this stuff
is not needed)
+ irq_domain_reset_irq_data(data);
+ domain = irq_domain_add_linear(node, nr_exti,
+ &irq_exti_domain_ops, NULL);
It's a simple linear domain. So how can data->parent_data be a valid
irq_data pointer? Answer: It can't!
This Exti domain is parent of stm32 gpio domain. When ".free" callback
of stm32 gpio domain is called then ".free" callback of Exti domain will
be automatically called. Those both ".free" callbacks are called with
"virq". This virq is created through stm32 gpio domain (in stm32 pinctrl
driver), data and parent->data are then associated to it.
Sorry if it is not clear.
Regards
Alex
But it doesn't blow up in your face simply because the alloc/free callbacks
are never invoked for simple non hierarchical domains. So you should have
removed that stuff after copying some other irqchip driver.
Thanks,
tglx
Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl
Hi Linus, On 09/13/2016 10:18 AM, Linus Walleij wrote: On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE wrote: Signed-off-by: Maxime Coquelin Acked-by: Rob Herring Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 587bffb..a0eed99 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -14,6 +14,9 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: phandle of the syscfg node used for IRQ mux selection. Actually this doc is incomplete. This is a phandle + offset, not just a phandle. It is a small detail so I don't care much, either send a patch to fix up this doc (I have already merged it) or patch the driver to not retrieve the offset and instead use #define SYSCFG_OFFSET 0x08 or something... I'll send a patch for Documentation. Do I need to wait this series is officially released (4.9-rc1) or can I send it now ? Regards Alex Yours, Linus Walleij
Re: [PATCH 13/15] stmmac: use IS_ENABLED() instead of checking for built-in or module
Hi Javier, On 09/12/2016 04:03 PM, Javier Martinez Canillas wrote: The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either built-in or as a module, use that macro instead of open coding the same. Using the macro makes the code more readable by helping abstract away some of the Kconfig built-in and module enable details. Signed-off-by: Javier Martinez Canillas --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 2533b91f1421..d3292c4a6eda 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -30,7 +30,7 @@ #include #include #include -#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) +#if IS_ENABLED(CONFIG_VLAN_8021Q) #define STMMAC_VLAN_TAG_USED #include #endif Reviewed-by: Alexandre TORGUE Thanks, Alex
Re: [PATCH v4 6/9] pinctrl: Add IRQ support to STM32 gpios
Hi Linus, On 09/12/2016 02:58 PM, Linus Walleij wrote: On Thu, Sep 8, 2016 at 5:47 PM, Alexandre Torgue wrote: Just one question, when you say "super-complex irqchip in use", do you mean I could use another (simplest) solution to handle this EXTI controller? I don't know, GPIOLIB_IRQCHIP is to be used for some specific cases documented in Documentation/gpio/driver.txt. For anything complex, we either need to have this hairy code or invent new abstractions. Ok I see . For now, I assume this is needed... Yes it is. Regards Alex Yours, Linus Walleij
[PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+ specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>,
<42>, <62>, <76>;
+};
--
1.9.1
[PATCH v5 7/9] ARM: dts: Add GPIO irq support to STM2F429
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1a189d4..6824762 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -189,6 +189,8 @@
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x4002 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@4002 {
--
1.9.1
[PATCH v5 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 boards
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..0fd78e4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
+#include
/ {
model = "STMicroelectronics STM32429i-EVAL board";
@@ -82,6 +83,23 @@
};
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "Wake up";
+ linux,code = ;
+ gpios = <&gpioa 0 0>;
+ };
+ button@1 {
+ label = "Tamper";
+ linux,code = ;
+ gpios = <&gpioc 13 0>;
+ };
+ };
+
usbotg_hs_phy: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 0140807..7d0415e 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
+#include
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -75,6 +76,18 @@
linux,default-trigger = "heartbeat";
};
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = ;
+ gpios = <&gpioa 0 0>;
+ };
+ };
};
&clk_hse {
--
1.9.1
[PATCH v5 0/9] Add STM32 EXTI interrupt controller support
Hi, This v5 fixes bad copy/paste inside stm32exti driver (spot by Jason), and remove GPIOLIB_IRQCHIP config for stm32 pinctrl driver (Linus). The series adds support to EXTI interrupt controller and GPIO IRQ support in STM32 pinctrl driver. The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, fallin or both edges. Each line can also be masked independently. Regards Alex Changes since v4: - - Fix bad copy/paste in stm32 exti driver - Remove GPIOLIB_IRQCHIP config in stm32 pinctrl driver Changes since v3: - - Review domain dealloc/free irq in stm32 pinctrl driver - Review domain dealloc/free irq in stm32 exti driver - Fix remarks on coding style Changes since v2: - - Define irq_chip for GPIO banks - Use hierarchical domain for GPIO banks - Improve search loop inside stm32_exti handler - Rebased on top of v4.8-rc1 Changes since v1: - - Rebased on top of v4.6-rc1 - Change variable name from virq to irq (Linus W.) Alexandre TORGUE (9): Documentation: dt-bindings: Document STM32 EXTI controller bindings drivers: irqchip: Add STM32 external interrupts support ARM: STM32: Select external interrupts controller ARM: dts: Add EXTI controller node to stm32f429 Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl pinctrl: Add IRQ support to STM32 gpios ARM: dts: Add GPIO irq support to STM2F429 ARM: dts: Declare push button as GPIO key on stm32f429 boards ARM: config: Enable GPIO Key driver in stm32_defconfig .../interrupt-controller/st,stm32-exti.txt | 20 ++ .../bindings/pinctrl/st,stm32-pinctrl.txt | 3 + arch/arm/Kconfig | 1 + arch/arm/boot/dts/stm32429i-eval.dts | 18 ++ arch/arm/boot/dts/stm32f429-disco.dts | 13 ++ arch/arm/boot/dts/stm32f429.dtsi | 10 + arch/arm/configs/stm32_defconfig | 6 +- drivers/irqchip/Kconfig| 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-stm32-exti.c | 202 + drivers/pinctrl/stm32/Kconfig | 1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 163 - 12 files changed, 440 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt create mode 100644 drivers/irqchip/irq-stm32-exti.c -- 1.9.1
[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+ bool
+ select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..95e46ba
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EXTI_IMR 0x0
+#define EXTI_EMR 0x4
+#define EXTI_RTSR 0x8
+#define EXTI_FTSR 0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
+ struct irq_chip_generic *gc = domain->gc->gc[0];
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long pending;
+ int n;
+
+ chained_irq_enter(chip, desc);
+
+ while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+ for_each_set_bit(n, &pending, BITS_PER_LONG) {
+ generic_handle_irq(irq_find_mapping(domain, n));
+ irq_reg_writel(gc, BIT(n), EXTI_PR);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 rtsr, ftsr;
+
+ irq_gc_lock(gc);
+
+ rtsr = irq_reg_readl(gc, EXTI_RTSR);
+ ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ rtsr |= BIT(pin);
+ ftsr &= ~BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ rtsr &= ~BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ rtsr |= BIT(pin);
+ ftsr |= BIT(pin);
+ break;
+ default:
+ irq_gc_unlock(gc);
+ return -EINVAL;
+ }
+
+ irq_reg_writel(gc, rtsr, EXTI_RTSR);
+ irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ int pin = data->hwirq;
+ u32 emr;
+
+ irq_gc_lock(gc);
+
+ emr = irq_reg_readl(gc, EXTI_EMR);
+ if (on)
+ emr |= BIT(pin);
+ else
+ emr &= ~BIT(pin);
+ irq_reg_writel(gc, emr, EXTI_EMR);
+
+ irq_gc_unlock(gc);
+
+ return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct irq_chip_generic *gc = d->gc->gc[0];
+ struct irq_fwspec *fwspec = data;
+ irq_hw_number_t hwirq;
+
+ hwirq = fwspec->param[0];
+
+ irq_map_generic_chip(d, virq, hwirq);
+ irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
+ handle_simple_irq, NULL, NULL);
+
+ return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_get_irq_data(virq);
+
+ irq_gc_mask_clr_bit(data->parent_data);
+ irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+ .map= irq_map_generic_chip,
+ .xlate = irq_domain_xlate_onetwocell,
+ .alloc = stm32_exti_alloc,
+ .free = stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+
[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl
Signed-off-by: Maxime Coquelin Acked-by: Rob Herring Signed-off-by: Alexandre TORGUE diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 587bffb..a0eed99 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -14,6 +14,9 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: phandle of the syscfg node used for IRQ mux selection. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. -- 1.9.1
[PATCH v5 4/9] ARM: dts: Add EXTI controller node to stm32f429
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
reg = <0x40013800 0x400>;
};
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>,
<23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
--
1.9.1
[PATCH v5 3/9] ARM: STM32: Select external interrupts controller
Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d601d7..157cea9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -877,6 +877,7 @@ config ARCH_STM32 select CLKSRC_STM32 select PINCTRL select RESET_CONTROLLER + select STM32_EXTI help Support for STMicroelectronics STM32 processors. -- 1.9.1
[PATCH v5 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig
Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 1e5ec2a..e7b56d4 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set # CONFIG_BLK_DEV is not set CONFIG_EEPROM_93CX6=y -# CONFIG_INPUT is not set +# CONFIG_INPUT_LEDS is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_UNIX98_PTYS is not set -- 1.9.1
[PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios
This patch adds IRQ support to STM32 gpios.
The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 4c40dae..24bc683 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,7 @@ config PINCTRL_STM32
select PINMUX
select GENERIC_PINCONF
select GPIOLIB
+ select MFD_SYSCON
config PINCTRL_STM32F429
bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST &&
!MACH_STM32F429
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 4ae596b..4f01025 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -20,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
@@ -40,6 +43,7 @@
#define STM32_GPIO_AFRH0x24
#define STM32_GPIO_PINS_PER_BANK 16
+#define STM32_GPIO_IRQ_LINE 16
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
@@ -65,6 +69,8 @@ struct stm32_gpio_bank {
spinlock_t lock;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
+ struct fwnode_handle *fwnode;
+ struct irq_domain *domain;
};
struct stm32_pinctrl {
@@ -77,6 +83,9 @@ struct stm32_pinctrl {
struct stm32_gpio_bank *banks;
unsigned nbanks;
const struct stm32_pinctrl_match_data *match_data;
+ struct irq_domain *domain;
+ struct regmap *regmap;
+ struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
};
static inline int stm32_gpio_pin(int gpio)
@@ -174,6 +183,20 @@ static int stm32_gpio_direction_output(struct gpio_chip
*chip,
return 0;
}
+
+static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ struct irq_fwspec fwspec;
+
+ fwspec.fwnode = bank->fwnode;
+ fwspec.param_count = 2;
+ fwspec.param[0] = offset;
+ fwspec.param[1] = IRQ_TYPE_NONE;
+
+ return irq_create_fwspec_mapping(&fwspec);
+}
+
static struct gpio_chip stm32_gpio_template = {
.request= stm32_gpio_request,
.free = stm32_gpio_free,
@@ -181,10 +204,92 @@ static struct gpio_chip stm32_gpio_template = {
.set= stm32_gpio_set,
.direction_input= stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
+ .to_irq = stm32_gpio_to_irq,
};
-/* Pinctrl functions */
+static struct irq_chip stm32_gpio_irq_chip = {
+ .name = "stm32gpio",
+ .irq_eoi= irq_chip_eoi_parent,
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+};
+
+static int stm32_gpio_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ if ((fwspec->param_count != 2) ||
+ (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
+ return -EINVAL;
+
+ *hwirq = fwspec->param[0];
+ *type = fwspec->param[1];
+ return 0;
+}
+static void stm32_gpio_domain_activate(struct irq_domain *d,
+ struct irq_data *irq_data)
+{
+ struct stm32_gpio_bank *bank = d->host_data;
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+
+ regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+}
+
+static int stm32_gpio_domain_alloc(struct irq_domain *d,
+ unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct stm32_gpio_bank *bank = d->host_data;
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ struct irq_fwspec *fwspec = data;
+ struct irq_fwspec parent_fwspec;
+ irq_hw_number_t hwirq;
+ int ret;
+
+ hwirq = fwspec->param[0];
+ parent_fwspec.fwnode = d->parent->fwnode;
+ parent_fwspec.param_count = 2;
+ parent_fwspec.param[0] = fwspec->param[0];
+ parent_fwspec.param[1] = fwspec->param[1];
+
+ irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_i
Re: [PATCH v4 6/9] pinctrl: Add IRQ support to STM32 gpios
Hi Linus, On 09/07/2016 11:06 PM, Linus Walleij wrote: On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE wrote: This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE +++ b/drivers/pinctrl/stm32/Kconfig @@ -6,6 +6,8 @@ config PINCTRL_STM32 select PINMUX select GENERIC_PINCONF select GPIOLIB + select GPIOLIB_IRQCHIP But you're not really using GPIOLIB_IRQCHIP. You have a different, super-complex irqchip in use. Thanks Linus for this review. I will send a V5. Just one question, when you say "super-complex irqchip in use", do you mean I could use another (simplest) solution to handle this EXTI controller? Regards Alex So just don't select this. + bank->gpio_chip.irqdomain = irq_domain_create_hierarchy(pctl->domain, + 0, STM32_GPIO_IRQ_LINE, bank->fwnode, + &stm32_gpio_domain_ops, bank); Don't use that irqdomain pointer inside the gpio_chip. Instead declare the irqdomain pointer inside struct stm32_gpio_bank or something like that. Yours, Linus Walleij
Re: [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support
Hi Thomas, On 09/02/2016 08:57 PM, Thomas Gleixner wrote: > Alexandre, > > On Fri, 2 Sep 2016, Alexandre TORGUE wrote: > > This all looks very reasonable. The only complaint I have is your variable > declaration ordering or the lack thereof. > > 1) >> +struct irq_domain *domain = irq_desc_get_handler_data(desc); >> +struct irq_chip_generic *gc = domain->gc->gc[0]; >> +struct irq_chip *chip = irq_desc_get_chip(desc); >> +unsigned long pending; >> +int n; > > 2) >> +struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> +u32 rtsr, ftsr; >> +int pin = data->hwirq; > > 3) >> +struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> +int pin = data->hwirq; >> +u32 emr; > > 4) >> +irq_hw_number_t hwirq; >> +struct irq_fwspec *fwspec = data; >> +struct irq_chip_generic *gc = d->gc->gc[0]; > > 5) >> +int nr_irqs, nr_exti, ret, i; >> +unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> +struct irq_domain *domain; >> +struct irq_chip_generic *gc; >> +void *base; > > #1 and 3 have the ordering which is preferred in the irq code. > > #2, #4 and #5 are three permutations which are way harder to read. > >> +struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> +int pin = data->hwirq; >> +u32 rtsr, ftsr; > >> +struct irq_chip_generic *gc = d->gc->gc[0]; >> +struct irq_fwspec *fwspec = data; >> +irq_hw_number_t hwirq; > >> +unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> +int nr_irqs, nr_exti, ret, i; >> +struct irq_chip_generic *gc; >> +struct irq_domain *domain; >> +void *base; > > Can you spot the difference? Thanks for review and for proposal. It Will be in next version. Regards Alex > > Thanks, > > tglx >
