[PATCH v2 2/2] phy: stm32: manage optional vbus regulator on phy_power_on/off

[Amelie Delaunay]

This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.

Signed-off-by: Amelie Delaunay 
---
No changes in v2.
---
 drivers/phy/st/phy-stm32-usbphyc.c | 31 ++
 1 file changed, 31 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index c184f4e34584..3e491dfb2525 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -57,6 +57,7 @@ struct pll_params {
 struct stm32_usbphyc_phy {
struct phy *phy;
struct stm32_usbphyc *usbphyc;
+   struct regulator *vbus;
u32 index;
bool active;
 };
@@ -291,9 +292,31 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return stm32_usbphyc_pll_disable(usbphyc);
 }
 
+static int stm32_usbphyc_phy_power_on(struct phy *phy)
+{
+   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+
+   if (usbphyc_phy->vbus)
+   return regulator_enable(usbphyc_phy->vbus);
+
+   return 0;
+}
+
+static int stm32_usbphyc_phy_power_off(struct phy *phy)
+{
+   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+
+   if (usbphyc_phy->vbus)
+   return regulator_disable(usbphyc_phy->vbus);
+
+   return 0;
+}
+
 static const struct phy_ops stm32_usbphyc_phy_ops = {
.init = stm32_usbphyc_phy_init,
.exit = stm32_usbphyc_phy_exit,
+   .power_on = stm32_usbphyc_phy_power_on,
+   .power_off = stm32_usbphyc_phy_power_off,
.owner = THIS_MODULE,
 };
 
@@ -519,6 +542,14 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
usbphyc->phys[port]->index = index;
usbphyc->phys[port]->active = false;
 
+   usbphyc->phys[port]->vbus = 
devm_regulator_get_optional(&phy->dev, "vbus");
+   if (IS_ERR(usbphyc->phys[port]->vbus)) {
+   ret = PTR_ERR(usbphyc->phys[port]->vbus);
+   if (ret == -EPROBE_DEFER)
+   goto put_child;
+   usbphyc->phys[port]->vbus = NULL;
+   }
+
port++;
}
 
-- 
2.17.1

[PATCH v2 0/2] STM32 USBPHYC vbus-supply property support

[Amelie Delaunay]

STM32 USBPHYC provides two USB High-Speed ports which are used by controllers
with Host capabilities. That's why vbus-supply has to be supported on each
phy node.

---
Changes in v2:
- use connector node vbus-supply property as suggested by Rob
---
Amelie Delaunay (2):
  dt-bindings: phy: add vbus-supply optional property to
phy-stm32-usbphyc
  phy: stm32: manage optional vbus regulator on phy_power_on/off

 .../bindings/phy/phy-stm32-usbphyc.yaml   | 11 +++
 drivers/phy/st/phy-stm32-usbphyc.c| 31 +++
 2 files changed, 42 insertions(+)

-- 
2.17.1

[PATCH v2 1/2] dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc

[Amelie Delaunay]

This patch adds vbus-supply optional property to phy sub-nodes using
connector node.
A regulator for USB VBUS may be needed for host mode.

Signed-off-by: Amelie Delaunay 
---
Changes in v2:
- add connector vbus-supply property as suggested by Rob
---
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml| 11 +++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 018cc1246ee1..3329f1d33a4f 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -74,6 +74,13 @@ patternProperties:
   "#phy-cells":
 enum: [ 0x0, 0x1 ]
 
+  connector:
+type: object
+allOf:
+  - $ref: ../connector/usb-connector.yaml
+properties:
+  vbus-supply: true
+
 allOf:
   - if:
   properties:
@@ -130,6 +137,10 @@ examples:
 reg = <0>;
 phy-supply = <&vdd_usb>;
 #phy-cells = <0>;
+connector {
+compatible = "usb-a-connector";
+vbus-supply = <&vbus_sw>;
+};
 };
 
 usbphyc_port1: usb-phy@1 {
-- 
2.17.1

Re: [PATCH 1/2] dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc

[Amelie DELAUNAY]

Hi Rob,

On 3/26/21 1:28 AM, Rob Herring wrote:

On Wed, Mar 17, 2021 at 05:09:53PM +0100, Amelie Delaunay wrote:

This patch adds vbus-supply optional property to phy sub-nodes.
A regulator for USB VBUS may be needed for host mode.

Signed-off-by: Amelie Delaunay 
---
  Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 018cc1246ee1..ad2378c30334 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -71,6 +71,9 @@ patternProperties:
phy-supply:
  description: regulator providing 3V3 power supply to the PHY.
  
+  vbus-supply:

+description: regulator providing 5V Vbus to the USB connector.


Unless Vbus is powering the phy, then this only belongs in the USB
connector node.



Do you mean I should declare a connector node as a child of the phy node 
and get the vbus-supply property from this connector node ?


In case of a on-board autonomous hub between the phy and the connectors, 
so no driver to drive it nor to get the vbus-supply property to provide 
VBUS to the hub, then the connectors, how to use connector ?


[USB controller]===[USB PHY]===[(USB HUB)]===|> USB A connector
  /  |> USB A connector
VBUS |> USB A connector
 |> USB A connector

Please advise.

Regards,
Amelie


+
"#phy-cells":
  enum: [ 0x0, 0x1 ]
  
--

2.17.1

[PATCH 1/2] dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc

[Amelie Delaunay]

This patch adds vbus-supply optional property to phy sub-nodes.
A regulator for USB VBUS may be needed for host mode.

Signed-off-by: Amelie Delaunay 
---
 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 018cc1246ee1..ad2378c30334 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -71,6 +71,9 @@ patternProperties:
   phy-supply:
 description: regulator providing 3V3 power supply to the PHY.
 
+  vbus-supply:
+description: regulator providing 5V Vbus to the USB connector.
+
   "#phy-cells":
 enum: [ 0x0, 0x1 ]
 
-- 
2.17.1

[PATCH 0/2] STM32 USBPHYC vbus-supply property support

[Amelie Delaunay]

STM32 USBPHYC provides two USB High-Speed ports which are used by controllers
with Host capabilities. That's why vbus-supply has to be supported on each
phy node.

Amelie Delaunay (2):
  dt-bindings: phy: add vbus-supply optional property to
phy-stm32-usbphyc
  phy: stm32: manage optional vbus regulator on phy_power_on/off

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  3 ++
 drivers/phy/st/phy-stm32-usbphyc.c| 31 +++
 2 files changed, 34 insertions(+)

-- 
2.17.1

[PATCH 2/2] phy: stm32: manage optional vbus regulator on phy_power_on/off

[Amelie Delaunay]

This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 31 ++
 1 file changed, 31 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index c184f4e34584..3e491dfb2525 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -57,6 +57,7 @@ struct pll_params {
 struct stm32_usbphyc_phy {
struct phy *phy;
struct stm32_usbphyc *usbphyc;
+   struct regulator *vbus;
u32 index;
bool active;
 };
@@ -291,9 +292,31 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return stm32_usbphyc_pll_disable(usbphyc);
 }
 
+static int stm32_usbphyc_phy_power_on(struct phy *phy)
+{
+   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+
+   if (usbphyc_phy->vbus)
+   return regulator_enable(usbphyc_phy->vbus);
+
+   return 0;
+}
+
+static int stm32_usbphyc_phy_power_off(struct phy *phy)
+{
+   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+
+   if (usbphyc_phy->vbus)
+   return regulator_disable(usbphyc_phy->vbus);
+
+   return 0;
+}
+
 static const struct phy_ops stm32_usbphyc_phy_ops = {
.init = stm32_usbphyc_phy_init,
.exit = stm32_usbphyc_phy_exit,
+   .power_on = stm32_usbphyc_phy_power_on,
+   .power_off = stm32_usbphyc_phy_power_off,
.owner = THIS_MODULE,
 };
 
@@ -519,6 +542,14 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
usbphyc->phys[port]->index = index;
usbphyc->phys[port]->active = false;
 
+   usbphyc->phys[port]->vbus = 
devm_regulator_get_optional(&phy->dev, "vbus");
+   if (IS_ERR(usbphyc->phys[port]->vbus)) {
+   ret = PTR_ERR(usbphyc->phys[port]->vbus);
+   if (ret == -EPROBE_DEFER)
+   goto put_child;
+   usbphyc->phys[port]->vbus = NULL;
+   }
+
port++;
}
 
-- 
2.17.1

[RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property

[Amelie Delaunay]

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
Acked-by: Rob Herring 
---
Changes in v3:
- add Rob's Acked-by
- remove #clock-cells from required properties
---
 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..018cc1246ee1 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
   vdda1v8-supply:
 description: regulator providing 1V8 power supply to the PLL block
 
+  '#clock-cells':
+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
 #Required child nodes:
 
 patternProperties:
@@ -120,6 +124,7 @@ examples:
 vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
+#clock-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
-- 
2.17.1

[RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider

[Amelie Delaunay]

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

---
Resent with linux-phy ML in cc
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
  dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
  phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  5 ++
 drivers/phy/st/Kconfig|  1 +
 drivers/phy/st/phy-stm32-usbphyc.c| 65 +++
 3 files changed, 71 insertions(+)

-- 
2.17.1

[RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

[Amelie Delaunay]

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
 drivers/phy/st/Kconfig |  1 +
 drivers/phy/st/phy-stm32-usbphyc.c | 65 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
 config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+   depends on COMMON_CLK
select GENERIC_PHY
help
  Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..c184f4e34584 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+   struct clk_hw clk48_hw;
int switch_setup;
 };
 
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
 };
 
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, 
unsigned long parent_rate)
+{
+   return 4800;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+   .prepare = stm32_usbphyc_clk48_prepare,
+   .unprepare = stm32_usbphyc_clk48_unprepare,
+   .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+   struct stm32_usbphyc *usbphyc = data;
+
+   of_clk_del_provider(usbphyc->dev->of_node);
+   clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+   struct device_node *node = usbphyc->dev->of_node;
+   struct clk_init_data init = { };
+   int ret = 0;
+
+   init.name = "ck_usbo_48m";
+   init.ops = &usbphyc_clk48_ops;
+
+   usbphyc->clk48_hw.init = &init;
+
+   ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+   if (ret)
+   return ret;
+
+   ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, 
&usbphyc->clk48_hw);
+   if (ret)
+   clk_hw_unregister(&usbphyc->clk48_hw);
+
+   return ret;
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
   u32 utmi_switch)
 {
@@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
+   ret = stm32_usbphyc_clk48_register(usbphyc);
+   if (ret) {
+   dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
+   goto clk_disable;
+   }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device 
*pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
+   stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
 
return 0;
-- 
2.17.1

[RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider

[Amelie Delaunay]

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

---
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
  dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
  phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  5 ++
 drivers/phy/st/Kconfig|  1 +
 drivers/phy/st/phy-stm32-usbphyc.c| 65 +++
 3 files changed, 71 insertions(+)

-- 
2.17.1

[RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

[Amelie Delaunay]

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
 drivers/phy/st/Kconfig |  1 +
 drivers/phy/st/phy-stm32-usbphyc.c | 65 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
 config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+   depends on COMMON_CLK
select GENERIC_PHY
help
  Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..c184f4e34584 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+   struct clk_hw clk48_hw;
int switch_setup;
 };
 
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
 };
 
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, 
unsigned long parent_rate)
+{
+   return 4800;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+   .prepare = stm32_usbphyc_clk48_prepare,
+   .unprepare = stm32_usbphyc_clk48_unprepare,
+   .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+   struct stm32_usbphyc *usbphyc = data;
+
+   of_clk_del_provider(usbphyc->dev->of_node);
+   clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+   struct device_node *node = usbphyc->dev->of_node;
+   struct clk_init_data init = { };
+   int ret = 0;
+
+   init.name = "ck_usbo_48m";
+   init.ops = &usbphyc_clk48_ops;
+
+   usbphyc->clk48_hw.init = &init;
+
+   ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+   if (ret)
+   return ret;
+
+   ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, 
&usbphyc->clk48_hw);
+   if (ret)
+   clk_hw_unregister(&usbphyc->clk48_hw);
+
+   return ret;
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
   u32 utmi_switch)
 {
@@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
+   ret = stm32_usbphyc_clk48_register(usbphyc);
+   if (ret) {
+   dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
+   goto clk_disable;
+   }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device 
*pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
+   stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
 
return 0;
-- 
2.17.1

[RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property

[Amelie Delaunay]

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
Acked-by: Rob Herring 
---
Changes in v3:
- add Rob's Acked-by
- remove #clock-cells from required properties
---
 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..018cc1246ee1 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
   vdda1v8-supply:
 description: regulator providing 1V8 power supply to the PLL block
 
+  '#clock-cells':
+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
 #Required child nodes:
 
 patternProperties:
@@ -120,6 +124,7 @@ examples:
 vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
+#clock-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
-- 
2.17.1

[PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider

[Amelie Delaunay]

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

---
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
  dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
  phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  5 ++
 drivers/phy/st/Kconfig|  1 +
 drivers/phy/st/phy-stm32-usbphyc.c| 65 +++
 3 files changed, 71 insertions(+)

-- 
2.17.1

[PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property

[Amelie Delaunay]

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
Changes in v3:
- remove #clock-cells from required properties
---
 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..018cc1246ee1 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
   vdda1v8-supply:
 description: regulator providing 1V8 power supply to the PLL block
 
+  '#clock-cells':
+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
 #Required child nodes:
 
 patternProperties:
@@ -120,6 +124,7 @@ examples:
 vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
+#clock-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
-- 
2.17.1

[PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

[Amelie Delaunay]

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
 drivers/phy/st/Kconfig |  1 +
 drivers/phy/st/phy-stm32-usbphyc.c | 65 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
 config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+   depends on COMMON_CLK
select GENERIC_PHY
help
  Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..c184f4e34584 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+   struct clk_hw clk48_hw;
int switch_setup;
 };
 
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
 };
 
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, 
unsigned long parent_rate)
+{
+   return 4800;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+   .prepare = stm32_usbphyc_clk48_prepare,
+   .unprepare = stm32_usbphyc_clk48_unprepare,
+   .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+   struct stm32_usbphyc *usbphyc = data;
+
+   of_clk_del_provider(usbphyc->dev->of_node);
+   clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+   struct device_node *node = usbphyc->dev->of_node;
+   struct clk_init_data init = { };
+   int ret = 0;
+
+   init.name = "ck_usbo_48m";
+   init.ops = &usbphyc_clk48_ops;
+
+   usbphyc->clk48_hw.init = &init;
+
+   ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+   if (ret)
+   return ret;
+
+   ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, 
&usbphyc->clk48_hw);
+   if (ret)
+   clk_hw_unregister(&usbphyc->clk48_hw);
+
+   return ret;
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
   u32 utmi_switch)
 {
@@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
+   ret = stm32_usbphyc_clk48_register(usbphyc);
+   if (ret) {
+   dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
+   goto clk_disable;
+   }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device 
*pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
+   stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
 
return 0;
-- 
2.17.1

Re: [PATCH v2 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required property

[Amelie DELAUNAY]

Hi Rob,

On 1/25/21 10:40 PM, Rob Herring wrote:

On Thu, Jan 14, 2021 at 06:13:13PM +0100, Amelie Delaunay wrote:

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
No change in v2.
---
  .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml  | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..4e4da64b8e01 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
vdda1v8-supply:
  description: regulator providing 1V8 power supply to the PLL block
  
+  '#clock-cells':

+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
  #Required child nodes:
  
  patternProperties:

@@ -102,6 +106,7 @@ required:
- "#size-cells"
- vdda1v1-supply
- vdda1v8-supply
+  - '#clock-cells'


You can't really make new properties required as it's not backwards
compatible. If things can never work without or the binding has never
been used, then you can. You just need to spell this out in the commit
msg.



In fact things can work without this property. But I made this new 
property required because in clock-bindings, #clock-cells property is a 
required property for clock providers.


phy-stm32-usbphyc bindings are only used in stm32mp151.dtsi, which will 
be updated with this new property as soon as this bindings will be reviewed.


I can remove this new property from required ones, but is it okay as 
#clock-cells property is a required property for clock providers?


Regards,
Amelie


- usb-phy@0
- usb-phy@1
  
@@ -120,6 +125,7 @@ examples:

  vdda1v8-supply = <®18>;
  #address-cells = <1>;
  #size-cells = <0>;
+#clock-cells = <0>;
  
  usbphyc_port0: usb-phy@0 {

  reg = <0>;
--
2.17.1

[PATCH v2 0/2] STM32 USBPHYC ck_usbo_48m clock provider

[Amelie Delaunay]

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

---
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
  dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required
property
  phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  6 ++
 drivers/phy/st/Kconfig|  1 +
 drivers/phy/st/phy-stm32-usbphyc.c| 66 +++
 3 files changed, 73 insertions(+)

-- 
2.17.1

[PATCH v2 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

[Amelie Delaunay]

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
 drivers/phy/st/Kconfig |  1 +
 drivers/phy/st/phy-stm32-usbphyc.c | 66 ++
 2 files changed, 67 insertions(+)

diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
 config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+   depends on COMMON_CLK
select GENERIC_PHY
help
  Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..349976259112 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+   struct clk_hw clk48_hw;
int switch_setup;
 };
 
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
 };
 
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, 
unsigned long parent_rate)
+{
+   return 4800;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+   .prepare = stm32_usbphyc_clk48_prepare,
+   .unprepare = stm32_usbphyc_clk48_unprepare,
+   .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+   struct stm32_usbphyc *usbphyc = data;
+
+   of_clk_del_provider(usbphyc->dev->of_node);
+   clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+   struct device_node *node = usbphyc->dev->of_node;
+   struct clk_init_data init = { };
+   int ret = 0;
+
+   init.name = "ck_usbo_48m";
+   init.ops = &usbphyc_clk48_ops;
+
+   usbphyc->clk48_hw.init = &init;
+
+   ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+   if (ret)
+   return ret;
+
+   ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, 
&usbphyc->clk48_hw);
+   if (ret)
+   clk_hw_unregister(&usbphyc->clk48_hw);
+
+   return ret;
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
   u32 utmi_switch)
 {
@@ -473,6 +530,13 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
+   ret = stm32_usbphyc_clk48_register(usbphyc);
+   if (ret) {
+   dev_err(dev,
+   "failed to register ck_usbo_48m clock: %d\n", ret);
+   goto clk_disable;
+   }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +561,8 @@ static int stm32_usbphyc_remove(struct platform_device 
*pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
+   stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
 
return 0;
-- 
2.17.1

[PATCH v2 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required property

[Amelie Delaunay]

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
No change in v2.
---
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml  | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..4e4da64b8e01 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
   vdda1v8-supply:
 description: regulator providing 1V8 power supply to the PLL block
 
+  '#clock-cells':
+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
 #Required child nodes:
 
 patternProperties:
@@ -102,6 +106,7 @@ required:
   - "#size-cells"
   - vdda1v1-supply
   - vdda1v8-supply
+  - '#clock-cells'
   - usb-phy@0
   - usb-phy@1
 
@@ -120,6 +125,7 @@ examples:
 vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
+#clock-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
-- 
2.17.1

[PATCH v2 1/3] ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on stm32mp151

[Amelie Delaunay]

vdda1v1 and vdda1v8 supplies are required by USB PLL. Add them in usbphyc
node.

Cc: Manivannan Sadhasivam 
Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374..07cb927ba06d 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1486,6 +1486,8 @@
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
+   vdda1v1-supply = <®11>;
+   vdda1v8-supply = <®18>;
status = "disabled";
 
usbphyc_port0: usb-phy@0 {
-- 
2.17.1

[PATCH v2 2/3] ARM: dts: stm32: remove usbphyc ports vdda1v1 & vdda1v8 on stm32mp15 boards

[Amelie Delaunay]

vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.

Cc: Manivannan Sadhasivam 
Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp157a-stinger96.dtsi   | 4 
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 2 --
 arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi  | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi   | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 4 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 7 files changed, 26 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi 
b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
index 58275bcf9e26..113c48b2ef93 100644
--- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
@@ -331,12 +331,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 81a7d5849db4..95b08876b2b3 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -393,12 +393,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
index 62ab23824a3e..f6bc86065151 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
@@ -152,6 +152,4 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
index 8456f172d4b1..5523f4138fd6 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -300,12 +300,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi
index 356150d28c42..8f9748ee2ecd 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi
@@ -132,12 +132,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
index ec02cee1dd9b..b09e87fe901a 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -391,12 +391,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 89c0e1ddc387..59f18846cf5d 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -694,14 +694,10 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &vrefbuf {
-- 
2.17.1

[PATCH v2 3/3] ARM: dts: stm32: add #clock-cells property to usbphyc node on stm32mp151

[Amelie Delaunay]

usbphyc is a 48Mhz clock provider: the clock can be used as clock source
for USB OTG. Add #clock-cells property to usbphyc node to reflect this
capability.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 07cb927ba06d..51acb2b04720 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1482,6 +1482,7 @@
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
+   #clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
-- 
2.17.1

[PATCH v2 0/3] ARM: stm32: USBPHYC updates on stm32mp15

[Amelie Delaunay]

This series updates usbphyc parent and child nodes to follow latest DT
bindings.

---
Changes in v2:
- squash all DT board patches in one patch
- update also non-ST DT

Amelie Delaunay (3):
  ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on
stm32mp151
  ARM: dts: stm32: remove usbphyc ports vdda1v1 & vdda1v8 on stm32mp15
boards
  ARM: dts: stm32: add #clock-cells property to usbphyc node on
stm32mp151

 arch/arm/boot/dts/stm32mp151.dtsi  | 3 +++
 arch/arm/boot/dts/stm32mp157a-stinger96.dtsi   | 4 
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 2 --
 arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi  | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi   | 4 
 arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 4 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 8 files changed, 3 insertions(+), 26 deletions(-)

-- 
2.17.1

[PATCH 2/4] ARM: dts: stm32: remove usbphyc ports vdda1v1-vdda1v8 on stm32mp157c-ed1

[Amelie Delaunay]

vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 81a7d5849db4..95b08876b2b3 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -393,12 +393,8 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
-- 
2.17.1

[PATCH 1/4] ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on stm32mp151

[Amelie Delaunay]

vdda1v1 and vdda1v8 supplies are required by USB PLL. Add them in usbphyc
node.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374..07cb927ba06d 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1486,6 +1486,8 @@
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
+   vdda1v1-supply = <®11>;
+   vdda1v8-supply = <®18>;
status = "disabled";
 
usbphyc_port0: usb-phy@0 {
-- 
2.17.1

[PATCH 4/4] ARM: dts: stm32: add #clock-cells property to usbphyc node on stm32mp151

[Amelie Delaunay]

usbphyc is a 48Mhz clock provider: the clock can be used as clock source
for USB OTG. Add #clock-cells property to usbphyc node to reflect this
capability.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 07cb927ba06d..51acb2b04720 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1482,6 +1482,7 @@
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
+   #clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
-- 
2.17.1

[PATCH 3/4] ARM: dts: stm32: remove usbphyc ports vdda1v1-vdda1v8 on stm32mp15xx-dkx

[Amelie Delaunay]

vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 89c0e1ddc387..59f18846cf5d 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -694,14 +694,10 @@
 
 &usbphyc_port0 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &usbphyc_port1 {
phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>;
 };
 
 &vrefbuf {
-- 
2.17.1

[PATCH 0/4] ARM: stm32: USBPHYC updates on stm32mp15

[Amelie Delaunay]

This series updates usbphyc parent and child nodes to follow latest DT
bindings.

Amelie Delaunay (4):
  ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on
stm32mp151
  ARM: dts: stm32: remove usbphyc ports vdda1v1-vdda1v8 on
stm32mp157c-ed1
  ARM: dts: stm32: remove usbphyc ports vdda1v1-vdda1v8 on
stm32mp15xx-dkx
  ARM: dts: stm32: add #clock-cells property to usbphyc node on
stm32mp151

 arch/arm/boot/dts/stm32mp151.dtsi  | 3 +++
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 4 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 3 files changed, 3 insertions(+), 8 deletions(-)

-- 
2.17.1

[PATCH 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

[Amelie Delaunay]

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 66 ++
 1 file changed, 66 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..349976259112 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+   struct clk_hw clk48_hw;
int switch_setup;
 };
 
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
 };
 
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+   struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, 
clk48_hw);
+
+   stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, 
unsigned long parent_rate)
+{
+   return 4800;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+   .prepare = stm32_usbphyc_clk48_prepare,
+   .unprepare = stm32_usbphyc_clk48_unprepare,
+   .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+   struct stm32_usbphyc *usbphyc = data;
+
+   of_clk_del_provider(usbphyc->dev->of_node);
+   clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+   struct device_node *node = usbphyc->dev->of_node;
+   struct clk_init_data init = { };
+   int ret = 0;
+
+   init.name = "ck_usbo_48m";
+   init.ops = &usbphyc_clk48_ops;
+
+   usbphyc->clk48_hw.init = &init;
+
+   ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+   if (ret)
+   return ret;
+
+   ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, 
&usbphyc->clk48_hw);
+   if (ret)
+   clk_hw_unregister(&usbphyc->clk48_hw);
+
+   return ret;
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
   u32 utmi_switch)
 {
@@ -473,6 +530,13 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
+   ret = stm32_usbphyc_clk48_register(usbphyc);
+   if (ret) {
+   dev_err(dev,
+   "failed to register ck_usbo_48m clock: %d\n", ret);
+   goto clk_disable;
+   }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +561,8 @@ static int stm32_usbphyc_remove(struct platform_device 
*pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
+   stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
 
return 0;
-- 
2.17.1

[PATCH 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required property

[Amelie Delaunay]

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay 
---
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml  | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..4e4da64b8e01 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
   vdda1v8-supply:
 description: regulator providing 1V8 power supply to the PLL block
 
+  '#clock-cells':
+description: number of clock cells for ck_usbo_48m consumer
+const: 0
+
 #Required child nodes:
 
 patternProperties:
@@ -102,6 +106,7 @@ required:
   - "#size-cells"
   - vdda1v1-supply
   - vdda1v8-supply
+  - '#clock-cells'
   - usb-phy@0
   - usb-phy@1
 
@@ -120,6 +125,7 @@ examples:
 vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
+#clock-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
-- 
2.17.1

[PATCH 0/2] STM32 USBPHYC ck_usbo_48m clock provider

[Amelie Delaunay]

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

Amelie Delaunay (2):
  dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required
property
  phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  6 ++
 drivers/phy/st/phy-stm32-usbphyc.c| 66 +++
 2 files changed, 72 insertions(+)

-- 
2.17.1

[PATCH v2 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

[Amelie Delaunay]

Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 4900.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.

To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.

Signed-off-by: Amelie Delaunay 
Acked-by: Minas Harutyunyan 
---
 drivers/usb/dwc2/params.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct 
dwc2_hsotg *hsotg)
p->host_perio_tx_fifo_size = 256;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+   p->lpm = false;
+   p->lpm_clock_gating = false;
+   p->besl = false;
+   p->hird_threshold_en = false;
 }
 
 const struct of_device_id dwc2_of_match_table[] = {
-- 
2.17.1

[PATCH v2 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS

[Amelie Delaunay]

STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN)
to Single (32-bit accesses on AHB), which is not recommended, according
to STM32MP157 Reference manual [1].
This patch sets Burst length/type (HBSTLEN) so that bus transactions
target 16x32 bit accesses. This improves OTG controller performance.

[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149

Signed-off-by: Amelie Delaunay 
Acked-by: Minas Harutyunyan 
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 267543c3dc38..0df693319f0a 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -177,6 +177,7 @@ static void dwc2_set_stm32mp15_fsotg_params(struct 
dwc2_hsotg *hsotg)
p->i2c_enable = false;
p->activate_stm_fs_transceiver = true;
p->activate_stm_id_vb_detection = true;
+   p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 }
 
@@ -189,6 +190,7 @@ static void dwc2_set_stm32mp15_hsotg_params(struct 
dwc2_hsotg *hsotg)
p->host_rx_fifo_size = 440;
p->host_nperio_tx_fifo_size = 256;
p->host_perio_tx_fifo_size = 256;
+   p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 }
 
-- 
2.17.1

[PATCH v2 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG

[Amelie Delaunay]

When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.

Signed-off-by: Amelie Delaunay 
Acked-by: Minas Harutyunyan 
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 0df693319f0a..9e5dd7f3f2f6 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct 
dwc2_hsotg *hsotg)
p->activate_stm_id_vb_detection = true;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+   p->host_support_fs_ls_low_power = true;
+   p->host_ls_low_power_phy_clk = true;
 }
 
 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
-- 
2.17.1

[PATCH v2 0/3] STM32MP15 OTG params updates

[Amelie Delaunay]

This patchset brings some updates on STM32MP15 OTG HS and FS.
It sets ahbcfg parameter for both HS and FS as the value reported by the
hardware is not recommended.
It also disables Link Power Management on OTG HS because with some Host
controllers (at least seen with some USB 3.2 Gen2 controllers), OTG doesn't
succeed to exit L1 state.
It also enables FS/LS PHY clock selection when the Core is in FS Host mode,
to have 6MHz PHY clock when the connected device is LS, and 48Mhz PHY clock
otherwise. 

---
Changes in v2:
- Move author mail address from @st.com to @foss.st.com
- Add Minas' Reviewed-by on all patches

Amelie Delaunay (3):
  usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
  usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
  usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

 drivers/usb/dwc2/params.c | 8 
 1 file changed, 8 insertions(+)

-- 
2.17.1

[PATCH v2 3/6] phy: stm32: replace regulator_bulk* by multiple regulator_*

[Amelie Delaunay]

Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 69 ++
 1 file changed, 52 insertions(+), 17 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index c78a2c7947ce..8ef97c8806ff 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -36,13 +36,6 @@
 #define MINREV GENMASK(3, 0)
 #define MAJREV GENMASK(7, 4)
 
-static const char * const supplies_names[] = {
-   "vdda1v1",  /* 1V1 */
-   "vdda1v8",  /* 1V8 */
-};
-
-#define NUM_SUPPLIES   ARRAY_SIZE(supplies_names)
-
 #define PLL_LOCK_TIME_US   100
 #define PLL_PWR_DOWN_TIME_US   5
 #define PLL_FVCO_MHZ   2880
@@ -69,7 +62,8 @@ struct stm32_usbphyc {
struct reset_control *rst;
struct stm32_usbphyc_phy **phys;
int nphys;
-   struct regulator_bulk_data supplies[NUM_SUPPLIES];
+   struct regulator *vdda1v1;
+   struct regulator *vdda1v8;
int switch_setup;
 };
 
@@ -83,6 +77,41 @@ static inline void stm32_usbphyc_clr_bits(void __iomem *reg, 
u32 bits)
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
 }
 
+static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
+{
+   int ret;
+
+   ret = regulator_enable(usbphyc->vdda1v1);
+   if (ret)
+   return ret;
+
+   ret = regulator_enable(usbphyc->vdda1v8);
+   if (ret)
+   goto vdda1v1_disable;
+
+   return 0;
+
+vdda1v1_disable:
+   regulator_disable(usbphyc->vdda1v1);
+
+   return ret;
+}
+
+static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
+{
+   int ret;
+
+   ret = regulator_disable(usbphyc->vdda1v8);
+   if (ret)
+   return ret;
+
+   ret = regulator_disable(usbphyc->vdda1v1);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 struct pll_params *pll_params)
 {
@@ -170,7 +199,7 @@ static int stm32_usbphyc_pll_disable(struct stm32_usbphyc 
*usbphyc)
return -EIO;
}
 
-   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+   return stm32_usbphyc_regulators_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
@@ -189,7 +218,7 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return ret;
}
 
-   ret = regulator_bulk_enable(NUM_SUPPLIES, usbphyc->supplies);
+   ret = stm32_usbphyc_regulators_enable(usbphyc);
if (ret)
return ret;
 
@@ -210,7 +239,7 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return 0;
 
 reg_disable:
-   regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+   stm32_usbphyc_regulators_disable(usbphyc);
 
return ret;
 }
@@ -306,7 +335,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
struct device_node *child, *np = dev->of_node;
struct phy_provider *phy_provider;
u32 version;
-   int ret, i, port = 0;
+   int ret, port = 0;
 
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
if (!usbphyc)
@@ -348,13 +377,19 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
-   for (i = 0; i < NUM_SUPPLIES; i++)
-   usbphyc->supplies[i].supply = supplies_names[i];
+   usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
+   if (IS_ERR(usbphyc->vdda1v1)) {
+   ret = PTR_ERR(usbphyc->vdda1v1);
+   if (ret != -EPROBE_DEFER)
+   dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
+   goto clk_disable;
+   }
 
-   ret = devm_regulator_bulk_get(dev, NUM_SUPPLIES, usbphyc->supplies);
-   if (ret) {
+   usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
+   if (IS_ERR(usbphyc->vdda1v8)) {
+   ret = PTR_ERR(usbphyc->vdda1v8);
if (ret != -EPROBE_DEFER)
-   dev_err(dev, "failed to get regulators: %d\n", ret);
+   dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
goto clk_disable;
}
 
-- 
2.17.1

[PATCH v2 1/6] dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node

[Amelie Delaunay]

PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE
signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
parent node and not in phy children nodes.

Signed-off-by: Amelie Delaunay 
Reviewed-by: Rob Herring 
---
Note that even with bindings change, it doesn't break the backward
compatibility: old device trees are still compatible, USB is still
functional. Device trees will be updated with this new bindings
when approved.
---
 .../bindings/phy/phy-stm32-usbphyc.yaml   | 22 +--
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 0ba61979b970..46df6786727a 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -45,6 +45,12 @@ properties:
   "#size-cells":
 const: 0
 
+  vdda1v1-supply:
+description: regulator providing 1V1 power supply to the PLL block
+
+  vdda1v8-supply:
+description: regulator providing 1V8 power supply to the PLL block
+
 #Required child nodes:
 
 patternProperties:
@@ -61,12 +67,6 @@ patternProperties:
   phy-supply:
 description: regulator providing 3V3 power supply to the PHY.
 
-  vdda1v1-supply:
-description: regulator providing 1V1 power supply to the PLL block
-
-  vdda1v8-supply:
-description: regulator providing 1V8 power supply to the PLL block
-
   "#phy-cells":
 enum: [ 0x0, 0x1 ]
 
@@ -90,8 +90,6 @@ patternProperties:
 required:
   - reg
   - phy-supply
-  - vdda1v1-supply
-  - vdda1v8-supply
   - "#phy-cells"
 
 additionalProperties: false
@@ -102,6 +100,8 @@ required:
   - clocks
   - "#address-cells"
   - "#size-cells"
+  - vdda1v1-supply
+  - vdda1v8-supply
   - usb-phy@0
   - usb-phy@1
 
@@ -116,22 +116,20 @@ examples:
 reg = <0x5a006000 0x1000>;
 clocks = <&rcc USBPHY_K>;
 resets = <&rcc USBPHY_R>;
+vdda1v1-supply = <®11>;
+vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
 phy-supply = <&vdd_usb>;
-vdda1v1-supply = <®11>;
-vdda1v8-supply = <®18>;
 #phy-cells = <0>;
 };
 
 usbphyc_port1: usb-phy@1 {
 reg = <1>;
 phy-supply = <&vdd_usb>;
-vdda1v1-supply = <®11>;
-vdda1v8-supply = <®18>;
 #phy-cells = <1>;
 };
 };
-- 
2.17.1

[PATCH v2 0/6] STM32 USBPHYC PLL management rework

[Amelie Delaunay]

STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
supplies. To ensure a good behavior of the PLL, during boot, runtime and
suspend/resume sequences, this series reworks its management to fix regulators
issues and improve PLL status reliability.

---
Changes in v2:
- Move author mail address from @st.com to @foss.st.com
- Add Rob's Reviewed-by on bindings patch 1/6

Amelie Delaunay (6):
  dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node
  phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation
  phy: stm32: replace regulator_bulk* by multiple regulator_*
  phy: stm32: ensure pll is disabled before phys creation
  phy: stm32: ensure phy are no more active when removing the driver
  phy: stm32: rework PLL Lock detection

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  22 +-
 drivers/phy/st/phy-stm32-usbphyc.c| 222 +++---
 2 files changed, 153 insertions(+), 91 deletions(-)

-- 
2.17.1

[PATCH v2 4/6] phy: stm32: ensure pll is disabled before phys creation

[Amelie Delaunay]

To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 8ef97c8806ff..33367a325612 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -8,7 +8,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -334,7 +334,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;
struct phy_provider *phy_provider;
-   u32 version;
+   u32 pllen, version;
int ret, port = 0;
 
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
@@ -366,6 +366,19 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
ret = PTR_ERR(usbphyc->rst);
if (ret == -EPROBE_DEFER)
goto clk_disable;
+
+   stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, 
PLLEN);
+   }
+
+   /*
+* Wait for minimum width of powerdown pulse (ENABLE = Low):
+* we have to ensure the PLL is disabled before phys initialization.
+*/
+   if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
+  pllen, !(pllen & PLLEN), 5, 50)) {
+   dev_warn(usbphyc->dev, "PLL not reset\n");
+   ret = -EPROBE_DEFER;
+   goto clk_disable;
}
 
usbphyc->switch_setup = -EINVAL;
-- 
2.17.1

[PATCH v2 2/6] phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation

[Amelie Delaunay]

PLL block requires to be powered with 1v1 and 1v8 supplies to catch
ENABLE signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
node and not in phy children nodes.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 102 +
 1 file changed, 46 insertions(+), 56 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index a54317e96c41..c78a2c7947ce 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -58,7 +58,6 @@ struct pll_params {
 struct stm32_usbphyc_phy {
struct phy *phy;
struct stm32_usbphyc *usbphyc;
-   struct regulator_bulk_data supplies[NUM_SUPPLIES];
u32 index;
bool active;
 };
@@ -70,6 +69,7 @@ struct stm32_usbphyc {
struct reset_control *rst;
struct stm32_usbphyc_phy **phys;
int nphys;
+   struct regulator_bulk_data supplies[NUM_SUPPLIES];
int switch_setup;
 };
 
@@ -153,10 +153,30 @@ static bool stm32_usbphyc_has_one_phy_active(struct 
stm32_usbphyc *usbphyc)
return false;
 }
 
+static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
+{
+   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+
+   /* Check if other phy port active */
+   if (stm32_usbphyc_has_one_phy_active(usbphyc))
+   return 0;
+
+   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
+   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
+   udelay(PLL_PWR_DOWN_TIME_US);
+
+   if (readl_relaxed(pll_reg) & PLLEN) {
+   dev_err(usbphyc->dev, "PLL not reset\n");
+   return -EIO;
+   }
+
+   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+}
+
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 {
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-   bool pllen = (readl_relaxed(pll_reg) & PLLEN);
+   bool pllen = readl_relaxed(pll_reg) & PLLEN;
int ret;
 
/* Check if one phy port has already configured the pll */
@@ -164,46 +184,35 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return 0;
 
if (pllen) {
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
+   ret = stm32_usbphyc_pll_disable(usbphyc);
+   if (ret)
+   return ret;
}
 
-   ret = stm32_usbphyc_pll_init(usbphyc);
+   ret = regulator_bulk_enable(NUM_SUPPLIES, usbphyc->supplies);
if (ret)
return ret;
 
-   stm32_usbphyc_set_bits(pll_reg, PLLEN);
+   ret = stm32_usbphyc_pll_init(usbphyc);
+   if (ret)
+   goto reg_disable;
 
+   stm32_usbphyc_set_bits(pll_reg, PLLEN);
/* Wait for maximum lock time */
udelay(PLL_LOCK_TIME_US);
 
if (!(readl_relaxed(pll_reg) & PLLEN)) {
dev_err(usbphyc->dev, "PLLEN not set\n");
-   return -EIO;
+   ret = -EIO;
+   goto reg_disable;
}
 
return 0;
-}
-
-static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
-{
-   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-
-   /* Check if other phy port active */
-   if (stm32_usbphyc_has_one_phy_active(usbphyc))
-   return 0;
 
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
+reg_disable:
+   regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
 
-   if (readl_relaxed(pll_reg) & PLLEN) {
-   dev_err(usbphyc->dev, "PLL not reset\n");
-   return -EIO;
-   }
-
-   return 0;
+   return ret;
 }
 
 static int stm32_usbphyc_phy_init(struct phy *phy)
@@ -231,25 +240,9 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return stm32_usbphyc_pll_disable(usbphyc);
 }
 
-static int stm32_usbphyc_phy_power_on(struct phy *phy)
-{
-   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
-
-   return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
-}
-
-static int stm32_usbphyc_phy_power_off(struct phy *phy)
-{
-   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
-
-   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
-}
-
 static const struct phy_ops stm32_usbphyc_phy_ops = {
.init 

[PATCH v2 6/6] phy: stm32: rework PLL Lock detection

[Amelie Delaunay]

USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to know if PLL Lock input to phy is
high. That means the PLL is ready for HS operation.
Instead of using an hard-coded delay after PLL enable and PLL disable, use
this bit to ensure good operating of the HS PHY.
Also use an atomic counter (n_pll_cons) to count the actual number of PLL
consumers and get rid of stm32_usbphyc_has_one_phy_active.
The boolean active in the usbphyc_phy structure is kept, because we need to
know in remove if a phy_exit is required to properly disable the PLL.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 88 ++
 1 file changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 8b11d95b2c20..d08fbb180e43 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -17,6 +17,7 @@
 
 #define STM32_USBPHYC_PLL  0x0
 #define STM32_USBPHYC_MISC 0x8
+#define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
 #define STM32_USBPHYC_VERSION  0x3F4
 
 /* STM32_USBPHYC_PLL bit fields */
@@ -32,12 +33,16 @@
 /* STM32_USBPHYC_MISC bit fields */
 #define SWITHOST   BIT(0)
 
+/* STM32_USBPHYC_MONITOR bit fields */
+#define STM32_USBPHYC_MON_OUT  GENMASK(3, 0)
+#define STM32_USBPHYC_MON_SEL  GENMASK(8, 4)
+#define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
+#define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
+
 /* STM32_USBPHYC_VERSION bit fields */
 #define MINREV GENMASK(3, 0)
 #define MAJREV GENMASK(7, 4)
 
-#define PLL_LOCK_TIME_US   100
-#define PLL_PWR_DOWN_TIME_US   5
 #define PLL_FVCO_MHZ   2880
 #define PLL_INFF_MIN_RATE_HZ   1920
 #define PLL_INFF_MAX_RATE_HZ   3840
@@ -64,6 +69,7 @@ struct stm32_usbphyc {
int nphys;
struct regulator *vdda1v1;
struct regulator *vdda1v8;
+   atomic_t n_pll_cons;
int switch_setup;
 };
 
@@ -171,35 +177,27 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc 
*usbphyc)
return 0;
 }
 
-static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
+static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 {
-   int i;
+   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+   u32 pllen;
+
+   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 
-   for (i = 0; i < usbphyc->nphys; i++)
-   if (usbphyc->phys[i]->active)
-   return true;
+   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
+   if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
+   dev_err(usbphyc->dev, "PLL not reset\n");
 
-   return false;
+   return stm32_usbphyc_regulators_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 {
-   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-
-   /* Check if other phy port active */
-   if (stm32_usbphyc_has_one_phy_active(usbphyc))
+   /* Check if a phy port is still active or clk48 in use */
+   if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
return 0;
 
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
-
-   if (readl_relaxed(pll_reg) & PLLEN) {
-   dev_err(usbphyc->dev, "PLL not reset\n");
-   return -EIO;
-   }
-
-   return stm32_usbphyc_regulators_disable(usbphyc);
+   return __stm32_usbphyc_pll_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
@@ -208,39 +206,43 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
bool pllen = readl_relaxed(pll_reg) & PLLEN;
int ret;
 
-   /* Check if one phy port has already configured the pll */
-   if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
+   /*
+* Check if a phy port or clk48 prepare has configured the pll
+* and ensure the PLL is enabled
+*/
+   if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
return 0;
 
if (pllen) {
-   ret = stm32_usbphyc_pll_disable(usbphyc);
+   /*
+* PLL shouldn't be enabled without known consumer,
+* disable it and reinit n_pll_cons
+*/
+   dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
+
+   ret = __stm32_usbphyc_pll_disable(usbphyc);
if (ret)
return ret;
}
 
ret = stm32_usbphyc_regulators_enable(usbphyc);
if (ret)
-   return ret;
+

[PATCH v2 5/6] phy: stm32: ensure phy are no more active when removing the driver

[Amelie Delaunay]

To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 33367a325612..8b11d95b2c20 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -470,6 +470,12 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
 static int stm32_usbphyc_remove(struct platform_device *pdev)
 {
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
+   int port;
+
+   /* Ensure PHYs are not active, to allow PLL disabling */
+   for (port = 0; port < usbphyc->nphys; port++)
+   if (usbphyc->phys[port]->active)
+   stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
clk_disable_unprepare(usbphyc->clk);
 
-- 
2.17.1

[PATCH 1/1] mfd: stmfx: remove .of_compatible from stmfx_cells for idd and ts

[Amelie Delaunay]

idd and ts features are not described in stmfx bindings. Remove the
.of_compatible field from relative mfd_cells to avoid having to add
corresponding disabled node in device trees using stmfx:
stmfx_idd: idd {
compatible = "st,stmfx-0300-idd";
status = "disabled";
};
stmfx_ts: stmfx_ts {
compatible = "st,stmfx-0300-ts";
status = "disabled";
};
The warning "Failed to locate of_node [id: -1]" won't appear anymore.
.of_compatible could be added as soon as idd or ts bindings are described
and drivers available.

Signed-off-by: Amelie Delaunay 
---
 drivers/mfd/stmfx.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index e095a3930142..b411d2958c18 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -81,13 +81,11 @@ static struct mfd_cell stmfx_cells[] = {
.num_resources = ARRAY_SIZE(stmfx_pinctrl_resources),
},
{
-   .of_compatible = "st,stmfx-0300-idd",
.name = "stmfx-idd",
.resources = stmfx_idd_resources,
.num_resources = ARRAY_SIZE(stmfx_idd_resources),
},
{
-   .of_compatible = "st,stmfx-0300-ts",
.name = "stmfx-ts",
.resources = stmfx_ts_resources,
.num_resources = ARRAY_SIZE(stmfx_ts_resources),
-- 
2.17.1

[PATCH 1/1] dmaengine: stm32-mdma: fix STM32_MDMA_VERY_HIGH_PRIORITY value

[Amelie Delaunay]

STM32_MDMA_VERY_HIGH_PRIORITY is b11 not 0x11, so fix it with 0x3.

Signed-off-by: Amelie Delaunay 
---
 drivers/dma/stm32-mdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index e4637ec786d3..36ba8b43e78d 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -199,7 +199,7 @@
 #define STM32_MDMA_MAX_CHANNELS63
 #define STM32_MDMA_MAX_REQUESTS256
 #define STM32_MDMA_MAX_BURST   128
-#define STM32_MDMA_VERY_HIGH_PRIORITY  0x11
+#define STM32_MDMA_VERY_HIGH_PRIORITY  0x3
 
 enum stm32_mdma_trigger_mode {
STM32_MDMA_BUFFER,
-- 
2.17.1

Re: [Linux-stm32] [PATCH v5 1/1 RESEND] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie DELAUNAY]

On 11/27/20 2:45 PM, Greg Kroah-Hartman wrote:

On Fri, Nov 27, 2020 at 02:17:35PM +0100, Amelie Delaunay wrote:

Device tree property is named typec-power-opmode, not power-opmode.

Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller 
family")
Signed-off-by: Amelie Delaunay 
Reviewed-by: Heikki Krogerus 
---
  drivers/usb/typec/stusb160x.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Now applied, sorry for missing it before.


Thanks!

Amelie

[PATCH v5 1/1 RESEND] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie Delaunay]

Device tree property is named typec-power-opmode, not power-opmode.

Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller 
family")
Signed-off-by: Amelie Delaunay 
Reviewed-by: Heikki Krogerus 
---
 drivers/usb/typec/stusb160x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/typec/stusb160x.c b/drivers/usb/typec/stusb160x.c
index 2a618f02f4f1..d2175044 100644
--- a/drivers/usb/typec/stusb160x.c
+++ b/drivers/usb/typec/stusb160x.c
@@ -562,7 +562,7 @@ static int stusb160x_get_fw_caps(struct stusb160x *chip,
 * Supported power operation mode can be configured through device tree
 * else it is read from chip registers in stusb160x_get_caps.
 */
-   ret = fwnode_property_read_string(fwnode, "power-opmode", &cap_str);
+   ret = fwnode_property_read_string(fwnode, "typec-power-opmode", 
&cap_str);
if (!ret) {
ret = typec_find_pwr_opmode(cap_str);
/* Power delivery not yet supported */
-- 
2.17.1

Re: [PATCH v5 3/5] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie DELAUNAY]

On 11/27/20 2:07 PM, Greg Kroah-Hartman wrote:

On Fri, Nov 27, 2020 at 02:01:29PM +0100, Amelie DELAUNAY wrote:

Hi Greg,

gentle reminder for this patch, lost in the middle of a DT series (DT part
already in stm32-next).


Odd, I don't see this anymore, can you resend just this one so I can
apply it directly?


Sure :) I rebase it and send it right now.

Amelie

Re: [PATCH v5 3/5] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie DELAUNAY]

Hi Greg,

gentle reminder for this patch, lost in the middle of a DT series (DT 
part already in stm32-next).


Thanks and regards,
Amelie

On 11/6/20 5:58 PM, Amelie Delaunay wrote:

Device tree property is named typec-power-opmode, not power-opmode.

Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller 
family")
Signed-off-by: Amelie Delaunay 
Reviewed-by: Heikki Krogerus 
---
  drivers/usb/typec/stusb160x.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/typec/stusb160x.c b/drivers/usb/typec/stusb160x.c
index 2a618f02f4f1..d2175044 100644
--- a/drivers/usb/typec/stusb160x.c
+++ b/drivers/usb/typec/stusb160x.c
@@ -562,7 +562,7 @@ static int stusb160x_get_fw_caps(struct stusb160x *chip,
 * Supported power operation mode can be configured through device tree
 * else it is read from chip registers in stusb160x_get_caps.
 */
-   ret = fwnode_property_read_string(fwnode, "power-opmode", &cap_str);
+   ret = fwnode_property_read_string(fwnode, "typec-power-opmode", 
&cap_str);
if (!ret) {
ret = typec_find_pwr_opmode(cap_str);
/* Power delivery not yet supported */

[PATCH 6/6] phy: stm32: rework PLL Lock detection

[Amelie Delaunay]

USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to know if PLL Lock input to phy is
high. That means the PLL is ready for HS operation.
Instead of using an hard-coded delay after PLL enable and PLL disable, use
this bit to ensure good operating of the HS PHY.
Also use an atomic counter (n_pll_cons) to count the actual number of PLL
consumers and get rid of stm32_usbphyc_has_one_phy_active.
The boolean active in the usbphyc_phy structure is kept, because we need to
know in remove if a phy_exit is required to properly disable the PLL.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 88 ++
 1 file changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 8b11d95b2c20..d08fbb180e43 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -17,6 +17,7 @@
 
 #define STM32_USBPHYC_PLL  0x0
 #define STM32_USBPHYC_MISC 0x8
+#define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
 #define STM32_USBPHYC_VERSION  0x3F4
 
 /* STM32_USBPHYC_PLL bit fields */
@@ -32,12 +33,16 @@
 /* STM32_USBPHYC_MISC bit fields */
 #define SWITHOST   BIT(0)
 
+/* STM32_USBPHYC_MONITOR bit fields */
+#define STM32_USBPHYC_MON_OUT  GENMASK(3, 0)
+#define STM32_USBPHYC_MON_SEL  GENMASK(8, 4)
+#define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
+#define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
+
 /* STM32_USBPHYC_VERSION bit fields */
 #define MINREV GENMASK(3, 0)
 #define MAJREV GENMASK(7, 4)
 
-#define PLL_LOCK_TIME_US   100
-#define PLL_PWR_DOWN_TIME_US   5
 #define PLL_FVCO_MHZ   2880
 #define PLL_INFF_MIN_RATE_HZ   1920
 #define PLL_INFF_MAX_RATE_HZ   3840
@@ -64,6 +69,7 @@ struct stm32_usbphyc {
int nphys;
struct regulator *vdda1v1;
struct regulator *vdda1v8;
+   atomic_t n_pll_cons;
int switch_setup;
 };
 
@@ -171,35 +177,27 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc 
*usbphyc)
return 0;
 }
 
-static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
+static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 {
-   int i;
+   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+   u32 pllen;
+
+   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 
-   for (i = 0; i < usbphyc->nphys; i++)
-   if (usbphyc->phys[i]->active)
-   return true;
+   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
+   if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
+   dev_err(usbphyc->dev, "PLL not reset\n");
 
-   return false;
+   return stm32_usbphyc_regulators_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 {
-   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-
-   /* Check if other phy port active */
-   if (stm32_usbphyc_has_one_phy_active(usbphyc))
+   /* Check if a phy port is still active or clk48 in use */
+   if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
return 0;
 
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
-
-   if (readl_relaxed(pll_reg) & PLLEN) {
-   dev_err(usbphyc->dev, "PLL not reset\n");
-   return -EIO;
-   }
-
-   return stm32_usbphyc_regulators_disable(usbphyc);
+   return __stm32_usbphyc_pll_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
@@ -208,39 +206,43 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
bool pllen = readl_relaxed(pll_reg) & PLLEN;
int ret;
 
-   /* Check if one phy port has already configured the pll */
-   if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
+   /*
+* Check if a phy port or clk48 prepare has configured the pll
+* and ensure the PLL is enabled
+*/
+   if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
return 0;
 
if (pllen) {
-   ret = stm32_usbphyc_pll_disable(usbphyc);
+   /*
+* PLL shouldn't be enabled without known consumer,
+* disable it and reinit n_pll_cons
+*/
+   dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
+
+   ret = __stm32_usbphyc_pll_disable(usbphyc);
if (ret)
return ret;
}
 
ret = stm32_usbphyc_regulators_enable(usbphyc);
if (ret)
-   return ret;
+

[PATCH 1/6] dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node

[Amelie Delaunay]

PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE
signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
parent node and not in phy children nodes.

Signed-off-by: Amelie Delaunay 
---
Note that even with bindings change, it doesn't break the backward
compatibility: old device trees are still compatible, USB is still
functional. Device trees will be updated with this new bindings
when approved.
---
 .../bindings/phy/phy-stm32-usbphyc.yaml   | 22 +--
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 0ba61979b970..46df6786727a 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -45,6 +45,12 @@ properties:
   "#size-cells":
 const: 0
 
+  vdda1v1-supply:
+description: regulator providing 1V1 power supply to the PLL block
+
+  vdda1v8-supply:
+description: regulator providing 1V8 power supply to the PLL block
+
 #Required child nodes:
 
 patternProperties:
@@ -61,12 +67,6 @@ patternProperties:
   phy-supply:
 description: regulator providing 3V3 power supply to the PHY.
 
-  vdda1v1-supply:
-description: regulator providing 1V1 power supply to the PLL block
-
-  vdda1v8-supply:
-description: regulator providing 1V8 power supply to the PLL block
-
   "#phy-cells":
 enum: [ 0x0, 0x1 ]
 
@@ -90,8 +90,6 @@ patternProperties:
 required:
   - reg
   - phy-supply
-  - vdda1v1-supply
-  - vdda1v8-supply
   - "#phy-cells"
 
 additionalProperties: false
@@ -102,6 +100,8 @@ required:
   - clocks
   - "#address-cells"
   - "#size-cells"
+  - vdda1v1-supply
+  - vdda1v8-supply
   - usb-phy@0
   - usb-phy@1
 
@@ -116,22 +116,20 @@ examples:
 reg = <0x5a006000 0x1000>;
 clocks = <&rcc USBPHY_K>;
 resets = <&rcc USBPHY_R>;
+vdda1v1-supply = <®11>;
+vdda1v8-supply = <®18>;
 #address-cells = <1>;
 #size-cells = <0>;
 
 usbphyc_port0: usb-phy@0 {
 reg = <0>;
 phy-supply = <&vdd_usb>;
-vdda1v1-supply = <®11>;
-vdda1v8-supply = <®18>;
 #phy-cells = <0>;
 };
 
 usbphyc_port1: usb-phy@1 {
 reg = <1>;
 phy-supply = <&vdd_usb>;
-vdda1v1-supply = <®11>;
-vdda1v8-supply = <®18>;
 #phy-cells = <1>;
 };
 };
-- 
2.17.1

[PATCH 4/6] phy: stm32: ensure pll is disabled before phys creation

[Amelie Delaunay]

To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 8ef97c8806ff..33367a325612 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -8,7 +8,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -334,7 +334,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;
struct phy_provider *phy_provider;
-   u32 version;
+   u32 pllen, version;
int ret, port = 0;
 
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
@@ -366,6 +366,19 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
ret = PTR_ERR(usbphyc->rst);
if (ret == -EPROBE_DEFER)
goto clk_disable;
+
+   stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, 
PLLEN);
+   }
+
+   /*
+* Wait for minimum width of powerdown pulse (ENABLE = Low):
+* we have to ensure the PLL is disabled before phys initialization.
+*/
+   if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
+  pllen, !(pllen & PLLEN), 5, 50)) {
+   dev_warn(usbphyc->dev, "PLL not reset\n");
+   ret = -EPROBE_DEFER;
+   goto clk_disable;
}
 
usbphyc->switch_setup = -EINVAL;
-- 
2.17.1

[PATCH 5/6] phy: stm32: ensure phy are no more active when removing the driver

[Amelie Delaunay]

To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 33367a325612..8b11d95b2c20 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -470,6 +470,12 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
 static int stm32_usbphyc_remove(struct platform_device *pdev)
 {
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
+   int port;
+
+   /* Ensure PHYs are not active, to allow PLL disabling */
+   for (port = 0; port < usbphyc->nphys; port++)
+   if (usbphyc->phys[port]->active)
+   stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 
clk_disable_unprepare(usbphyc->clk);
 
-- 
2.17.1

[PATCH 2/6] phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation

[Amelie Delaunay]

PLL block requires to be powered with 1v1 and 1v8 supplies to catch
ENABLE signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
node and not in phy children nodes.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 102 +
 1 file changed, 46 insertions(+), 56 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index a54317e96c41..c78a2c7947ce 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -58,7 +58,6 @@ struct pll_params {
 struct stm32_usbphyc_phy {
struct phy *phy;
struct stm32_usbphyc *usbphyc;
-   struct regulator_bulk_data supplies[NUM_SUPPLIES];
u32 index;
bool active;
 };
@@ -70,6 +69,7 @@ struct stm32_usbphyc {
struct reset_control *rst;
struct stm32_usbphyc_phy **phys;
int nphys;
+   struct regulator_bulk_data supplies[NUM_SUPPLIES];
int switch_setup;
 };
 
@@ -153,10 +153,30 @@ static bool stm32_usbphyc_has_one_phy_active(struct 
stm32_usbphyc *usbphyc)
return false;
 }
 
+static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
+{
+   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+
+   /* Check if other phy port active */
+   if (stm32_usbphyc_has_one_phy_active(usbphyc))
+   return 0;
+
+   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
+   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
+   udelay(PLL_PWR_DOWN_TIME_US);
+
+   if (readl_relaxed(pll_reg) & PLLEN) {
+   dev_err(usbphyc->dev, "PLL not reset\n");
+   return -EIO;
+   }
+
+   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+}
+
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 {
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-   bool pllen = (readl_relaxed(pll_reg) & PLLEN);
+   bool pllen = readl_relaxed(pll_reg) & PLLEN;
int ret;
 
/* Check if one phy port has already configured the pll */
@@ -164,46 +184,35 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return 0;
 
if (pllen) {
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
+   ret = stm32_usbphyc_pll_disable(usbphyc);
+   if (ret)
+   return ret;
}
 
-   ret = stm32_usbphyc_pll_init(usbphyc);
+   ret = regulator_bulk_enable(NUM_SUPPLIES, usbphyc->supplies);
if (ret)
return ret;
 
-   stm32_usbphyc_set_bits(pll_reg, PLLEN);
+   ret = stm32_usbphyc_pll_init(usbphyc);
+   if (ret)
+   goto reg_disable;
 
+   stm32_usbphyc_set_bits(pll_reg, PLLEN);
/* Wait for maximum lock time */
udelay(PLL_LOCK_TIME_US);
 
if (!(readl_relaxed(pll_reg) & PLLEN)) {
dev_err(usbphyc->dev, "PLLEN not set\n");
-   return -EIO;
+   ret = -EIO;
+   goto reg_disable;
}
 
return 0;
-}
-
-static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
-{
-   void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
-
-   /* Check if other phy port active */
-   if (stm32_usbphyc_has_one_phy_active(usbphyc))
-   return 0;
 
-   stm32_usbphyc_clr_bits(pll_reg, PLLEN);
-   /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
-   udelay(PLL_PWR_DOWN_TIME_US);
+reg_disable:
+   regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
 
-   if (readl_relaxed(pll_reg) & PLLEN) {
-   dev_err(usbphyc->dev, "PLL not reset\n");
-   return -EIO;
-   }
-
-   return 0;
+   return ret;
 }
 
 static int stm32_usbphyc_phy_init(struct phy *phy)
@@ -231,25 +240,9 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return stm32_usbphyc_pll_disable(usbphyc);
 }
 
-static int stm32_usbphyc_phy_power_on(struct phy *phy)
-{
-   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
-
-   return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
-}
-
-static int stm32_usbphyc_phy_power_off(struct phy *phy)
-{
-   struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
-
-   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
-}
-
 static const struct phy_ops stm32_usbphyc_phy_ops = {
.init 

[PATCH 3/6] phy: stm32: replace regulator_bulk* by multiple regulator_*

[Amelie Delaunay]

Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.

Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 69 ++
 1 file changed, 52 insertions(+), 17 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index c78a2c7947ce..8ef97c8806ff 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -36,13 +36,6 @@
 #define MINREV GENMASK(3, 0)
 #define MAJREV GENMASK(7, 4)
 
-static const char * const supplies_names[] = {
-   "vdda1v1",  /* 1V1 */
-   "vdda1v8",  /* 1V8 */
-};
-
-#define NUM_SUPPLIES   ARRAY_SIZE(supplies_names)
-
 #define PLL_LOCK_TIME_US   100
 #define PLL_PWR_DOWN_TIME_US   5
 #define PLL_FVCO_MHZ   2880
@@ -69,7 +62,8 @@ struct stm32_usbphyc {
struct reset_control *rst;
struct stm32_usbphyc_phy **phys;
int nphys;
-   struct regulator_bulk_data supplies[NUM_SUPPLIES];
+   struct regulator *vdda1v1;
+   struct regulator *vdda1v8;
int switch_setup;
 };
 
@@ -83,6 +77,41 @@ static inline void stm32_usbphyc_clr_bits(void __iomem *reg, 
u32 bits)
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
 }
 
+static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
+{
+   int ret;
+
+   ret = regulator_enable(usbphyc->vdda1v1);
+   if (ret)
+   return ret;
+
+   ret = regulator_enable(usbphyc->vdda1v8);
+   if (ret)
+   goto vdda1v1_disable;
+
+   return 0;
+
+vdda1v1_disable:
+   regulator_disable(usbphyc->vdda1v1);
+
+   return ret;
+}
+
+static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
+{
+   int ret;
+
+   ret = regulator_disable(usbphyc->vdda1v8);
+   if (ret)
+   return ret;
+
+   ret = regulator_disable(usbphyc->vdda1v1);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 struct pll_params *pll_params)
 {
@@ -170,7 +199,7 @@ static int stm32_usbphyc_pll_disable(struct stm32_usbphyc 
*usbphyc)
return -EIO;
}
 
-   return regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+   return stm32_usbphyc_regulators_disable(usbphyc);
 }
 
 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
@@ -189,7 +218,7 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return ret;
}
 
-   ret = regulator_bulk_enable(NUM_SUPPLIES, usbphyc->supplies);
+   ret = stm32_usbphyc_regulators_enable(usbphyc);
if (ret)
return ret;
 
@@ -210,7 +239,7 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc 
*usbphyc)
return 0;
 
 reg_disable:
-   regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+   stm32_usbphyc_regulators_disable(usbphyc);
 
return ret;
 }
@@ -306,7 +335,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
struct device_node *child, *np = dev->of_node;
struct phy_provider *phy_provider;
u32 version;
-   int ret, i, port = 0;
+   int ret, port = 0;
 
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
if (!usbphyc)
@@ -348,13 +377,19 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
goto clk_disable;
}
 
-   for (i = 0; i < NUM_SUPPLIES; i++)
-   usbphyc->supplies[i].supply = supplies_names[i];
+   usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
+   if (IS_ERR(usbphyc->vdda1v1)) {
+   ret = PTR_ERR(usbphyc->vdda1v1);
+   if (ret != -EPROBE_DEFER)
+   dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
+   goto clk_disable;
+   }
 
-   ret = devm_regulator_bulk_get(dev, NUM_SUPPLIES, usbphyc->supplies);
-   if (ret) {
+   usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
+   if (IS_ERR(usbphyc->vdda1v8)) {
+   ret = PTR_ERR(usbphyc->vdda1v8);
if (ret != -EPROBE_DEFER)
-   dev_err(dev, "failed to get regulators: %d\n", ret);
+   dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
goto clk_disable;
}
 
-- 
2.17.1

[PATCH 0/6] STM32 USBPHYC PLL management rework

[Amelie Delaunay]

STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
supplies. To ensure a good behavior of the PLL, during boot, runtime and
suspend/resume sequences, this series reworks its management to fix regulators
issues and improve PLL status reliability.

Amelie Delaunay (6):
  dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node
  phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation
  phy: stm32: replace regulator_bulk* by multiple regulator_*
  phy: stm32: ensure pll is disabled before phys creation
  phy: stm32: ensure phy are no more active when removing the driver
  phy: stm32: rework PLL Lock detection

 .../bindings/phy/phy-stm32-usbphyc.yaml   |  22 +-
 drivers/phy/st/phy-stm32-usbphyc.c| 222 +++---
 2 files changed, 153 insertions(+), 91 deletions(-)

-- 
2.17.1

[PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS

[Amelie Delaunay]

STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN)
to Single (32-bit accesses on AHB), which is not recommended, according
to STM32MP157 Reference manual [1].
This patch sets Burst length/type (HBSTLEN) so that bus transactions
target 16x32 bit accesses. This improves OTG controller performance.

[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149

Signed-off-by: Amelie Delaunay 
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 267543c3dc38..0df693319f0a 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -177,6 +177,7 @@ static void dwc2_set_stm32mp15_fsotg_params(struct 
dwc2_hsotg *hsotg)
p->i2c_enable = false;
p->activate_stm_fs_transceiver = true;
p->activate_stm_id_vb_detection = true;
+   p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 }
 
@@ -189,6 +190,7 @@ static void dwc2_set_stm32mp15_hsotg_params(struct 
dwc2_hsotg *hsotg)
p->host_rx_fifo_size = 440;
p->host_nperio_tx_fifo_size = 256;
p->host_perio_tx_fifo_size = 256;
+   p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 }
 
-- 
2.17.1

[PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

[Amelie Delaunay]

Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 4900.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.

To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.

Signed-off-by: Amelie Delaunay 
---
 drivers/usb/dwc2/params.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct 
dwc2_hsotg *hsotg)
p->host_perio_tx_fifo_size = 256;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+   p->lpm = false;
+   p->lpm_clock_gating = false;
+   p->besl = false;
+   p->hird_threshold_en = false;
 }
 
 const struct of_device_id dwc2_of_match_table[] = {
-- 
2.17.1

[PATCH 0/3] STM32MP15 OTG params updates

[Amelie Delaunay]

This patchset brings some updates on STM32MP15 OTG HS and FS.
It sets ahbcfg parameter for both HS and FS as the value reported by the
hardware is not recommended.
It also disables Link Power Management on OTG HS because with some Host
controllers (at least seen with some USB 3.2 Gen2 controllers), OTG doesn't
succeed to exit L1 state.
It also enables FS/LS PHY clock selection when the Core is in FS Host mode,
to have 6MHz PHY clock when the connected device is LS, and 48Mhz PHY clock
otherwise. 

Amelie Delaunay (3):
  usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
  usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
  usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

 drivers/usb/dwc2/params.c | 8 
 1 file changed, 8 insertions(+)

-- 
2.17.1

[PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG

[Amelie Delaunay]

When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.

Signed-off-by: Amelie Delaunay 
---
 drivers/usb/dwc2/params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 0df693319f0a..9e5dd7f3f2f6 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct 
dwc2_hsotg *hsotg)
p->activate_stm_id_vb_detection = true;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+   p->host_support_fs_ls_low_power = true;
+   p->host_ls_low_power_phy_clk = true;
 }
 
 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
-- 
2.17.1

[PATCH 3/4] dmaengine: stm32-dma: take address into account when computing max width

[Amelie Delaunay]

DMA_SxPAR or DMA_SxM0AR/M1AR registers have to be aligned on PSIZE or MSIZE
respectively. This means that bus width needs to be forced to 1 byte when
computed width is not aligned with address.

Signed-off-by: Amelie Delaunay 
---
 drivers/dma/stm32-dma.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 62501e5d9e9d..f54ecb123a52 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -264,9 +264,11 @@ static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 }
 
 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
+  dma_addr_t buf_addr,
   u32 threshold)
 {
enum dma_slave_buswidth max_width;
+   u64 addr = buf_addr;
 
if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -277,6 +279,9 @@ static enum dma_slave_buswidth stm32_dma_get_max_width(u32 
buf_len,
   max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
max_width = max_width >> 1;
 
+   if (do_div(addr, max_width))
+   max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+
return max_width;
 }
 
@@ -707,7 +712,7 @@ static void stm32_dma_issue_pending(struct dma_chan *c)
 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
enum dma_transfer_direction direction,
enum dma_slave_buswidth *buswidth,
-   u32 buf_len)
+   u32 buf_len, dma_addr_t buf_addr)
 {
enum dma_slave_buswidth src_addr_width, dst_addr_width;
int src_bus_width, dst_bus_width;
@@ -739,7 +744,8 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan 
*chan,
return dst_burst_size;
 
/* Set memory data size */
-   src_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
+   src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
+fifoth);
chan->mem_width = src_addr_width;
src_bus_width = stm32_dma_get_width(chan, src_addr_width);
if (src_bus_width < 0)
@@ -788,7 +794,8 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan 
*chan,
return src_burst_size;
 
/* Set memory data size */
-   dst_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
+   dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
+fifoth);
chan->mem_width = dst_addr_width;
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
if (dst_bus_width < 0)
@@ -876,7 +883,8 @@ static struct dma_async_tx_descriptor 
*stm32_dma_prep_slave_sg(
 
for_each_sg(sgl, sg, sg_len, i) {
ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
-  sg_dma_len(sg));
+  sg_dma_len(sg),
+  sg_dma_address(sg));
if (ret < 0)
goto err;
 
@@ -944,7 +952,8 @@ static struct dma_async_tx_descriptor 
*stm32_dma_prep_dma_cyclic(
return NULL;
}
 
-   ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
+   ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len,
+  buf_addr);
if (ret < 0)
return NULL;
 
-- 
2.17.1

[PATCH 4/4] dmaengine: stm32-mdma: rework interrupt handler

[Amelie Delaunay]

To avoid multiple entries in MDMA interrupt handler for each flag&interrupt
enable, manage all flags set at once.

Signed-off-by: Amelie Delaunay 
---
 drivers/dma/stm32-mdma.c | 64 +---
 1 file changed, 34 insertions(+), 30 deletions(-)

diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 29e5e30524bb..e4637ec786d3 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1346,7 +1346,7 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void 
*devid)
 {
struct stm32_mdma_device *dmadev = devid;
struct stm32_mdma_chan *chan = devid;
-   u32 reg, id, ien, status, flag;
+   u32 reg, id, ccr, ien, status;
 
/* Find out which channel generates the interrupt */
status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
@@ -1368,67 +1368,71 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void 
*devid)
 
chan = &dmadev->chan[id];
if (!chan) {
-   dev_dbg(mdma2dev(dmadev), "MDMA channel not initialized\n");
-   goto exit;
+   dev_warn(mdma2dev(dmadev), "MDMA channel not initialized\n");
+   return IRQ_NONE;
}
 
/* Handle interrupt for the channel */
spin_lock(&chan->vchan.lock);
-   status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
-   ien = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id));
-   ien &= STM32_MDMA_CCR_IRQ_MASK;
-   ien >>= 1;
+   status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
+   /* Mask Channel ReQuest Active bit which can be set in case of MEM2MEM 
*/
+   status &= ~STM32_MDMA_CISR_CRQA;
+   ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
+   ien = (ccr & STM32_MDMA_CCR_IRQ_MASK) >> 1;
 
if (!(status & ien)) {
spin_unlock(&chan->vchan.lock);
-   dev_dbg(chan2dev(chan),
-   "spurious it (status=0x%04x, ien=0x%04x)\n",
-   status, ien);
+   dev_warn(chan2dev(chan),
+"spurious it (status=0x%04x, ien=0x%04x)\n",
+status, ien);
return IRQ_NONE;
}
 
-   flag = __ffs(status & ien);
-   reg = STM32_MDMA_CIFCR(chan->id);
+   reg = STM32_MDMA_CIFCR(id);
 
-   switch (1 << flag) {
-   case STM32_MDMA_CISR_TEIF:
-   id = chan->id;
-   status = readl_relaxed(dmadev->base + STM32_MDMA_CESR(id));
-   dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n", status);
+   if (status & STM32_MDMA_CISR_TEIF) {
+   dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n",
+   readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)));
stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF);
-   break;
+   status &= ~STM32_MDMA_CISR_TEIF;
+   }
 
-   case STM32_MDMA_CISR_CTCIF:
+   if (status & STM32_MDMA_CISR_CTCIF) {
stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF);
+   status &= ~STM32_MDMA_CISR_CTCIF;
stm32_mdma_xfer_end(chan);
-   break;
+   }
 
-   case STM32_MDMA_CISR_BRTIF:
+   if (status & STM32_MDMA_CISR_BRTIF) {
stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF);
-   break;
+   status &= ~STM32_MDMA_CISR_BRTIF;
+   }
 
-   case STM32_MDMA_CISR_BTIF:
+   if (status & STM32_MDMA_CISR_BTIF) {
stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF);
+   status &= ~STM32_MDMA_CISR_BTIF;
chan->curr_hwdesc++;
if (chan->desc && chan->desc->cyclic) {
if (chan->curr_hwdesc == chan->desc->count)
chan->curr_hwdesc = 0;
vchan_cyclic_callback(&chan->desc->vdesc);
}
-   break;
+   }
 
-   case STM32_MDMA_CISR_TCIF:
+   if (status & STM32_MDMA_CISR_TCIF) {
stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF);
-   break;
+   status &= ~STM32_MDMA_CISR_TCIF;
+   }
 
-   default:
-   dev_err(chan2dev(chan), "it %d unhandled (status=0x%04x)\n",
-   1 << flag, status);
+   if (status) {
+   stm32_mdma_set_bits(dmadev, reg, status);
+   dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
+   if (!(ccr & STM32_MDMA_CCR_EN))
+   dev_err(chan2dev(chan), "chan disabled by HW\n");
}
 
spin_unlock(&chan->vchan.lock);
 
-exit:
return IRQ_HANDLED;
 }
 
-- 
2.17.1

[PATCH 1/4] dmaengine: stm32-dma: rework irq handler to manage error before xfer events

[Amelie Delaunay]

To better understand error that can be detected by the DMA controller,
manage the error flags before the transfer flags.
This way, it is possible to know if the FIFO error flag is set for an
over/underrun condition or a FIFO level error.
When a FIFO over/underrun condition occurs, the data is not lost because
peripheral request is not acknowledged by the stream until the over/
underrun condition is cleared. If this acknowledge takes too much time,
the peripheral itself may detect an over/underrun condition of its internal
buffer and data might be lost.
That's why in case the FIFO error flag is set, we check if the channel is
disabled or not, and if a Transfer Complete flag is set, which means that
the channel is disabled because of the end of transfer.
Because channel is disabled by hardware either by a FIFO level error, or by
an end of transfer.

Signed-off-by: Amelie Delaunay 
---
 drivers/dma/stm32-dma.c | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index d0055d2f0b9a..55a6bd381219 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -648,21 +648,12 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void 
*devid)
scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 
-   if (status & STM32_DMA_TCI) {
-   stm32_dma_irq_clear(chan, STM32_DMA_TCI);
-   if (scr & STM32_DMA_SCR_TCIE)
-   stm32_dma_handle_chan_done(chan);
-   status &= ~STM32_DMA_TCI;
-   }
-   if (status & STM32_DMA_HTI) {
-   stm32_dma_irq_clear(chan, STM32_DMA_HTI);
-   status &= ~STM32_DMA_HTI;
-   }
if (status & STM32_DMA_FEI) {
stm32_dma_irq_clear(chan, STM32_DMA_FEI);
status &= ~STM32_DMA_FEI;
if (sfcr & STM32_DMA_SFCR_FEIE) {
-   if (!(scr & STM32_DMA_SCR_EN))
+   if (!(scr & STM32_DMA_SCR_EN) &&
+   !(status & STM32_DMA_TCI))
dev_err(chan2dev(chan), "FIFO Error\n");
else
dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
@@ -674,6 +665,19 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
if (sfcr & STM32_DMA_SCR_DMEIE)
dev_dbg(chan2dev(chan), "Direct mode overrun\n");
}
+
+   if (status & STM32_DMA_TCI) {
+   stm32_dma_irq_clear(chan, STM32_DMA_TCI);
+   if (scr & STM32_DMA_SCR_TCIE)
+   stm32_dma_handle_chan_done(chan);
+   status &= ~STM32_DMA_TCI;
+   }
+
+   if (status & STM32_DMA_HTI) {
+   stm32_dma_irq_clear(chan, STM32_DMA_HTI);
+   status &= ~STM32_DMA_HTI;
+   }
+
if (status) {
stm32_dma_irq_clear(chan, status);
dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
-- 
2.17.1

[PATCH 0/4] Bunch of improvements for STM32 DMA controllers

[Amelie Delaunay]

This series brings 3 patches for STM32 DMA and 1 for STM32 MDMA.
They increase the reliability and the efficiency of the transfers.

Amelie Delaunay (4):
  dmaengine: stm32-dma: rework irq handler to manage error before xfer
events
  dmaengine: stm32-dma: clean channel configuration when channel is
freed
  dmaengine: stm32-dma: take address into account when computing max
width
  dmaengine: stm32-mdma: rework interrupt handler

 drivers/dma/stm32-dma.c  | 47 +++--
 drivers/dma/stm32-mdma.c | 64 +---
 2 files changed, 65 insertions(+), 46 deletions(-)

-- 
2.17.1

[PATCH 2/4] dmaengine: stm32-dma: clean channel configuration when channel is freed

[Amelie Delaunay]

When dma_channel_release is called, it means that the channel won't be used
anymore with the configuration it had. To ensure a future client can safely
use the channel after it has been released, clean the configuration done
when channel was requested.

Signed-off-by: Amelie Delaunay 
---
 drivers/dma/stm32-dma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 55a6bd381219..62501e5d9e9d 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -1220,6 +1220,8 @@ static void stm32_dma_free_chan_resources(struct dma_chan 
*c)
pm_runtime_put(dmadev->ddev.dev);
 
vchan_free_chan_resources(to_virt_chan(c));
+   stm32_dma_clear_reg(&chan->chan_reg);
+   chan->threshold = 0;
 }
 
 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
-- 
2.17.1

[PATCH v2 1/1] dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema

[Amelie Delaunay]

Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
using json-schema.

Signed-off-by: Amelie Delaunay 
Reviewed-by: Rob Herring 
---
v2: add additionalProperties also for child nodes and Rob's Reviewed-by
---
 .../bindings/phy/phy-stm32-usbphyc.txt|  73 -
 .../bindings/phy/phy-stm32-usbphyc.yaml   | 138 ++
 2 files changed, 138 insertions(+), 73 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
deleted file mode 100644
index 725ae71ae653..
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-STMicroelectronics STM32 USB HS PHY controller
-
-The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
-switch. It controls PHY configuration and status, and the UTMI+ switch that
-selects either OTG or HOST controller for the second PHY port. It also sets
-PLL configuration.
-
-USBPHYC
-  |_ PLL
-  |
-  |_ PHY port#1 _ HOST controller
-  |_ |
-  |  / 1||
-  |_ PHY port#2 |   |
-  |  \_0||
-  |_ UTMI switch___|  OTG controller
-
-
-Phy provider node
-=
-
-Required properties:
-- compatible: must be "st,stm32mp1-usbphyc"
-- reg: address and length of the usb phy control register set
-- clocks: phandle + clock specifier for the PLL phy clock
-- #address-cells: number of address cells for phys sub-nodes, must be <1>
-- #size-cells: number of size cells for phys sub-nodes, must be <0>
-
-Optional properties:
-- assigned-clocks: phandle + clock specifier for the PLL phy clock
-- assigned-clock-parents: the PLL phy clock parent
-- resets: phandle + reset specifier
-
-Required nodes: one sub-node per port the controller provides.
-
-Phy sub-nodes
-==
-
-Required properties:
-- reg: phy port index
-- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
- see phy-bindings.txt in the same directory.
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
-- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
-  port#1 and must be <1> for PHY port#2, to select USB controller
-
-
-Example:
-   usbphyc: usb-phy@5a006000 {
-   compatible = "st,stm32mp1-usbphyc";
-   reg = <0x5a006000 0x1000>;
-   clocks = <&rcc_clk USBPHY_K>;
-   resets = <&rcc_rst USBPHY_R>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   usbphyc_port0: usb-phy@0 {
-   reg = <0>;
-   phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>
-   #phy-cells = <0>;
-   };
-
-   usbphyc_port1: usb-phy@1 {
-   reg = <1>;
-   phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>
-   #phy-cells = <1>;
-   };
-   };
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
new file mode 100644
index ..0ba61979b970
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 USB HS PHY controller binding
+
+description:
+
+  The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+  switch. It controls PHY configuration and status, and the UTMI+ switch that
+  selects either OTG or HOST controller for the second PHY port. It also sets
+  PLL configuration.
+
+  USBPHYC
+  |_ PLL
+  |
+  |_ PHY port#1 _ HOST controller
+  |   __ |
+  |  / 1||
+  |_ PHY port#2 ----|   |
+  |  \_0||
+  |_ UTMI switch___|  OTG controller
+

[PATCH 1/1] mfd: stmfx: remove .of_compatible from stmfx_cells for idd and ts

[Amelie Delaunay]

idd and ts features are not described in stmfx bindings. Remove the
.of_compatible field from relative mfd_cells to avoid having to add
corresponding disabled node in device trees using stmfx:
stmfx_idd: idd {
status = "disabled";
};
stmfx_ts: stmfx_ts {
status = "disabled";
};
Then, the warning "Failed to locate of_node [id: -1]" wont appear anymore.
.of_compatible could be added as soon as idd or ts bindings are described
and drivers available.

Signed-off-by: Amelie Delaunay 
---
 drivers/mfd/stmfx.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 988e2ba6dd0f..39b2fc952b7d 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -81,13 +81,11 @@ static struct mfd_cell stmfx_cells[] = {
.num_resources = ARRAY_SIZE(stmfx_pinctrl_resources),
},
{
-   .of_compatible = "st,stmfx-0300-idd",
.name = "stmfx-idd",
.resources = stmfx_idd_resources,
.num_resources = ARRAY_SIZE(stmfx_idd_resources),
},
{
-   .of_compatible = "st,stmfx-0300-ts",
.name = "stmfx-ts",
.resources = stmfx_ts_resources,
.num_resources = ARRAY_SIZE(stmfx_ts_resources),
-- 
2.17.1

Re: [PATCH 1/2] phy: stm32: don't print an error on probe deferral

[Amelie DELAUNAY]

On 11/16/20 10:50 AM, Vinod Koul wrote:

On 16-11-20, 09:02, Amelie DELAUNAY wrote:

Hi Vinod,

On 11/16/20 8:37 AM, Vinod Koul wrote:

On 10-11-20, 11:23, Amelie Delaunay wrote:

Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.


Applied all, thanks



I'm sorry for the mess, I sent a v2 for the patch 1/2:
https://lore.kernel.org/patchwork/patch/1336206/
Indeed, I forgot the "return" before dev_err_probe.


No worries, I have dropped this and picked v2.
Do check if the patches are fine.

Thanks for letting me know



All is fine now :) Thank you!

Re: [PATCH 1/2] phy: stm32: don't print an error on probe deferral

[Amelie DELAUNAY]

Hi Vinod,

On 11/16/20 8:37 AM, Vinod Koul wrote:

On 10-11-20, 11:23, Amelie Delaunay wrote:

Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.


Applied all, thanks



I'm sorry for the mess, I sent a v2 for the patch 1/2: 
https://lore.kernel.org/patchwork/patch/1336206/

Indeed, I forgot the "return" before dev_err_probe.

Do you want me to send a fix?

Regards,
Amelie

Re: [PATCH 1/1] mfd: stmfx: fix dev_err_probe call in stmfx_chip_init

[Amelie DELAUNAY]

On 11/13/20 11:09 AM, Lee Jones wrote:

On Tue, 10 Nov 2020, Amelie Delaunay wrote:


ret may be 0 so, dev_err_probe should be called only when ret is an error
code.

Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay 
---
  drivers/mfd/stmfx.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 5e680bfdf5c9..360fb4646688 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -329,12 +329,11 @@ static int stmfx_chip_init(struct i2c_client *client)
  
  	stmfx->vdd = devm_regulator_get_optional(&client->dev, "vdd");

ret = PTR_ERR_OR_ZERO(stmfx->vdd);
-   if (ret == -ENODEV) {
+   if (ret == -ENODEV)
stmfx->vdd = NULL;
-   } else {
+   else if (ret)
return dev_err_probe(&client->dev, ret,
 "Failed to get VDD regulator\n");
-   }


Probably nicer to keep all of the error handing in one area, like:

if (ret) {
if (ret == -ENODEV)
stmfx->vdd = NULL;
else
return dev_err_probe(&client->dev, ret,
 "Failed to get VDD regulator\n");
}

I'll let you make the call though.



Thanks for the review. I agree. Fixed in v2.

Regards,
Amelie

[PATCH v2 1/1] mfd: stmfx: fix dev_err_probe call in stmfx_chip_init

[Amelie Delaunay]

ret may be 0 so, dev_err_probe should be called only when ret is an error
code.

Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay 
---
v2: address Lee's comment about error handling area
---
 drivers/mfd/stmfx.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 5e680bfdf5c9..988e2ba6dd0f 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -329,11 +329,11 @@ static int stmfx_chip_init(struct i2c_client *client)
 
stmfx->vdd = devm_regulator_get_optional(&client->dev, "vdd");
ret = PTR_ERR_OR_ZERO(stmfx->vdd);
-   if (ret == -ENODEV) {
-   stmfx->vdd = NULL;
-   } else {
-   return dev_err_probe(&client->dev, ret,
-"Failed to get VDD regulator\n");
+   if (ret) {
+   if (ret == -ENODEV)
+   stmfx->vdd = NULL;
+   else
+   return dev_err_probe(&client->dev, ret, "Failed to get 
VDD regulator\n");
}
 
if (stmfx->vdd) {
-- 
2.17.1

[PATCH 1/1] ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151

[Amelie Delaunay]

Update mdma1 clients channel priority level following stm32-mdma bindings.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 719a4276a348..b95c46c82223 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1294,7 +1294,7 @@
interrupts = ;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
-   dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
+   dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@@ -1358,8 +1358,8 @@
reg = <0x58003000 0x1000>, <0x7000 0x1000>;
reg-names = "qspi", "qspi_mm";
interrupts = ;
-   dmas = <&mdma1 22 0x10 0x12 0x0 0x0>,
-  <&mdma1 22 0x10 0x18 0x0 0x0>;
+   dmas = <&mdma1 22 0x2 0x12 0x0 0x0>,
+  <&mdma1 22 0x2 0x18 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
-- 
2.17.1

[PATCH 1/2] ARM: dts: stm32: fix dmamux reg property on stm32mp151

[Amelie Delaunay]

Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 928e31db1526..719a4276a348 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1001,7 +1001,7 @@
 
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
-   reg = <0x48002000 0x1c>;
+   reg = <0x48002000 0x40>;
#dma-cells = <3>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
-- 
2.17.1

[PATCH 2/2] ARM: dts: stm32: fix dmamux reg property on stm32h743

[Amelie Delaunay]

Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32h743.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 7febe19e780d..b083afd0ebd6 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -274,7 +274,7 @@
 
dmamux1: dma-router@40020800 {
compatible = "st,stm32h7-dmamux";
-   reg = <0x40020800 0x1c>;
+   reg = <0x40020800 0x40>;
#dma-cells = <3>;
dma-channels = <16>;
dma-requests = <128>;
-- 
2.17.1

[PATCH 1/1] ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151

[Amelie Delaunay]

Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk
endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes).
This patch optimizes USB OTG FIFO sizes accordingly.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 6ffcf06dc0e8..928e31db1526 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1070,9 +1070,9 @@
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = ;
-   g-rx-fifo-size = <256>;
+   g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
-   g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+   g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
usb33d-supply = <&usb33>;
status = "disabled";
-- 
2.17.1

[PATCH v2 1/2] phy: stm32: don't print an error on probe deferral

[Amelie Delaunay]

Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Amelie Delaunay 
---
v2: add missing return
---
 drivers/phy/st/phy-stm32-usbphyc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 2b3639cba51a..3630f83dea53 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -328,11 +328,8 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
return PTR_ERR(usbphyc->base);
 
usbphyc->clk = devm_clk_get(dev, NULL);
-   if (IS_ERR(usbphyc->clk)) {
-   ret = PTR_ERR(usbphyc->clk);
-   dev_err(dev, "clk get failed: %d\n", ret);
-   return ret;
-   }
+   if (IS_ERR(usbphyc->clk))
+   return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk 
get_failed\n");
 
ret = clk_prepare_enable(usbphyc->clk);
if (ret) {
-- 
2.17.1

[PATCH 1/1] dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema

[Amelie Delaunay]

Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
using json-schema.

Signed-off-by: Amelie Delaunay 
---
 .../bindings/phy/phy-stm32-usbphyc.txt|  73 --
 .../bindings/phy/phy-stm32-usbphyc.yaml   | 136 ++
 2 files changed, 136 insertions(+), 73 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
deleted file mode 100644
index 725ae71ae653..
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-STMicroelectronics STM32 USB HS PHY controller
-
-The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
-switch. It controls PHY configuration and status, and the UTMI+ switch that
-selects either OTG or HOST controller for the second PHY port. It also sets
-PLL configuration.
-
-USBPHYC
-  |_ PLL
-  |
-  |_ PHY port#1 _ HOST controller
-  |_ |
-  |  / 1||
-  |_ PHY port#2 |   |
-  |  \_0||
-  |_ UTMI switch___|  OTG controller
-
-
-Phy provider node
-=
-
-Required properties:
-- compatible: must be "st,stm32mp1-usbphyc"
-- reg: address and length of the usb phy control register set
-- clocks: phandle + clock specifier for the PLL phy clock
-- #address-cells: number of address cells for phys sub-nodes, must be <1>
-- #size-cells: number of size cells for phys sub-nodes, must be <0>
-
-Optional properties:
-- assigned-clocks: phandle + clock specifier for the PLL phy clock
-- assigned-clock-parents: the PLL phy clock parent
-- resets: phandle + reset specifier
-
-Required nodes: one sub-node per port the controller provides.
-
-Phy sub-nodes
-==
-
-Required properties:
-- reg: phy port index
-- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
- see phy-bindings.txt in the same directory.
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
-- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
-  port#1 and must be <1> for PHY port#2, to select USB controller
-
-
-Example:
-   usbphyc: usb-phy@5a006000 {
-   compatible = "st,stm32mp1-usbphyc";
-   reg = <0x5a006000 0x1000>;
-   clocks = <&rcc_clk USBPHY_K>;
-   resets = <&rcc_rst USBPHY_R>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   usbphyc_port0: usb-phy@0 {
-   reg = <0>;
-   phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>
-   #phy-cells = <0>;
-   };
-
-   usbphyc_port1: usb-phy@1 {
-   reg = <1>;
-   phy-supply = <&vdd_usb>;
-   vdda1v1-supply = <®11>;
-   vdda1v8-supply = <®18>
-   #phy-cells = <1>;
-   };
-   };
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml 
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
new file mode 100644
index ..09064bbb68dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 USB HS PHY controller binding
+
+description:
+
+  The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+  switch. It controls PHY configuration and status, and the UTMI+ switch that
+  selects either OTG or HOST controller for the second PHY port. It also sets
+  PLL configuration.
+
+  USBPHYC
+  |_ PLL
+  |
+  |_ PHY port#1 _ HOST controller
+  |   __ |
+  |  / 1||
+  |_ PHY port#2 |   |
+  |  \_0||
+  |_ UTMI switch___|  OTG controller
+
+maintainers:
+  - Amelie Delaunay 
+
+properties:
+  compatible:
+const: st,stm32mp1-usbphyc
+
+  re

[PATCH 1/2] phy: stm32: don't print an error on probe deferral

[Amelie Delaunay]

Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index 2b3639cba51a..fe3085eec201 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -328,11 +328,8 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
return PTR_ERR(usbphyc->base);
 
usbphyc->clk = devm_clk_get(dev, NULL);
-   if (IS_ERR(usbphyc->clk)) {
-   ret = PTR_ERR(usbphyc->clk);
-   dev_err(dev, "clk get failed: %d\n", ret);
-   return ret;
-   }
+   if (IS_ERR(usbphyc->clk))
+   dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
 
ret = clk_prepare_enable(usbphyc->clk);
if (ret) {
-- 
2.17.1

[PATCH 2/2] phy: stm32: defer probe for reset controller

[Amelie Delaunay]

Change stm32-usbphyc driver to defer its probe when the expected reset
control has its probe operation deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Amelie Delaunay 
---
 drivers/phy/st/phy-stm32-usbphyc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c 
b/drivers/phy/st/phy-stm32-usbphyc.c
index fe3085eec201..f3f582a3ccdb 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -342,6 +342,10 @@ static int stm32_usbphyc_probe(struct platform_device 
*pdev)
reset_control_assert(usbphyc->rst);
udelay(2);
reset_control_deassert(usbphyc->rst);
+   } else {
+   ret = PTR_ERR(usbphyc->rst);
+   if (ret == -EPROBE_DEFER)
+   goto clk_disable;
}
 
usbphyc->switch_setup = -EINVAL;
-- 
2.17.1

[PATCH 1/1] mfd: stmfx: fix dev_err_probe call in stmfx_chip_init

[Amelie Delaunay]

ret may be 0 so, dev_err_probe should be called only when ret is an error
code.

Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay 
---
 drivers/mfd/stmfx.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 5e680bfdf5c9..360fb4646688 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -329,12 +329,11 @@ static int stmfx_chip_init(struct i2c_client *client)
 
stmfx->vdd = devm_regulator_get_optional(&client->dev, "vdd");
ret = PTR_ERR_OR_ZERO(stmfx->vdd);
-   if (ret == -ENODEV) {
+   if (ret == -ENODEV)
stmfx->vdd = NULL;
-   } else {
+   else if (ret)
return dev_err_probe(&client->dev, ret,
 "Failed to get VDD regulator\n");
-   }
 
if (stmfx->vdd) {
ret = regulator_enable(stmfx->vdd);
-- 
2.17.1

Re: [PATCH v5 1/5] dt-bindings: connector: add typec-power-opmode property to usb-connector

[Amelie DELAUNAY]

On 11/9/20 5:02 PM, Rob Herring wrote:

On Mon, Nov 9, 2020 at 9:54 AM Amelie DELAUNAY  wrote:


On 11/9/20 4:03 PM, Rob Herring wrote:

On Fri, Nov 6, 2020 at 10:58 AM Amelie Delaunay  wrote:


Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.

Signed-off-by: Amelie Delaunay 
---
Hi Bahdri, Rob,

I've added the exlusion with FRS property, but new FRS property name
should be use here so, be careful.

---
   .../bindings/connector/usb-connector.yaml | 24 +++
   1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 62781518aefc..a84464b3e1f2 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
 - device
 - dual

+  typec-power-opmode:
+description: Determines the power operation mode that the Type C connector
+  will support and will advertise through CC pins when it has no power
+  delivery support.
+  - "default" corresponds to default USB voltage and current defined by the
+USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+operation respectively.
+  - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+Type-C Cable and Connector specification, when Power Delivery is not
+supported.
+allOf:
+  - $ref: /schemas/types.yaml#definitions/string
+enum:
+  - default
+  - 1.5A
+  - 3.0A


Use the enums here. Unless you want to define it as actual current as
a numerical value.


If I understand your point correctly, I think I should remove allOf here
and stick with what is done to describe power-role and data-role
property. Right ?


No, use the numerical values like FRS:

+  "1" refers to default USB power level as described by "Table
6-14 Fixed Supply PDO - Sink".
+  "2" refers to 1.5A@5V.
+  "3" refers to 3.0A@5V.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2, 3]


But it changes the type-c class philosophy. There is already an API to 
convert string into enum, the same kind is used for data-role and 
power-role properties.

Moveover, FRS values doesn't fit with typec_pwr_opmode enum:
enum typec_pwr_opmode {
TYPEC_PWR_MODE_USB,
TYPEC_PWR_MODE_1_5A,
TYPEC_PWR_MODE_3_0A,
TYPEC_PWR_MODE_PD,
};

Regards
Amelie

Re: [PATCH v5 1/5] dt-bindings: connector: add typec-power-opmode property to usb-connector

[Amelie DELAUNAY]

On 11/9/20 4:03 PM, Rob Herring wrote:

On Fri, Nov 6, 2020 at 10:58 AM Amelie Delaunay  wrote:


Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.

Signed-off-by: Amelie Delaunay 
---
Hi Bahdri, Rob,

I've added the exlusion with FRS property, but new FRS property name
should be use here so, be careful.

---
  .../bindings/connector/usb-connector.yaml | 24 +++
  1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 62781518aefc..a84464b3e1f2 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
- device
- dual

+  typec-power-opmode:
+description: Determines the power operation mode that the Type C connector
+  will support and will advertise through CC pins when it has no power
+  delivery support.
+  - "default" corresponds to default USB voltage and current defined by the
+USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+operation respectively.
+  - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+Type-C Cable and Connector specification, when Power Delivery is not
+supported.
+allOf:
+  - $ref: /schemas/types.yaml#definitions/string
+enum:
+  - default
+  - 1.5A
+  - 3.0A


Use the enums here. Unless you want to define it as actual current as
a numerical value.


If I understand your point correctly, I think I should remove allOf here 
and stick with what is done to describe power-role and data-role 
property. Right ?


Regards,
Amelie


Rob

Re: [PATCH v4 2/5] dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller

[Amelie DELAUNAY]

On 11/6/20 5:17 PM, Rob Herring wrote:

On Fri, 06 Nov 2020 10:18:51 +0100, Amelie Delaunay wrote:

Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.

Signed-off-by: Amelie Delaunay 
---
  .../devicetree/bindings/usb/st,stusb160x.yaml | 85 +++
  1 file changed, 85 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml




My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/st,stusb160x.yaml:
 'additionalProperties' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/st,stusb160x.yaml:
 ignoring, error in schema:
warning: no schema found in file: 
./Documentation/devicetree/bindings/usb/st,stusb160x.yaml


See https://patchwork.ozlabs.org/patch/1395559

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

I already ran 'make dt_binding_check' but st-schema was not up to date, 
despite a not so old upgrade.
I note for next time to do the upgrade autotically before the 'make 
dt_binding_check'.


New version submitted.

Thanks,
Amelie

[PATCH v5 1/5] dt-bindings: connector: add typec-power-opmode property to usb-connector

[Amelie Delaunay]

Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.

Signed-off-by: Amelie Delaunay 
---
Hi Bahdri, Rob,

I've added the exlusion with FRS property, but new FRS property name
should be use here so, be careful.

---
 .../bindings/connector/usb-connector.yaml | 24 +++
 1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 62781518aefc..a84464b3e1f2 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
   - device
   - dual
 
+  typec-power-opmode:
+description: Determines the power operation mode that the Type C connector
+  will support and will advertise through CC pins when it has no power
+  delivery support.
+  - "default" corresponds to default USB voltage and current defined by the
+USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+operation respectively.
+  - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+Type-C Cable and Connector specification, when Power Delivery is not
+supported.
+allOf:
+  - $ref: /schemas/types.yaml#definitions/string
+enum:
+  - default
+  - 1.5A
+  - 3.0A
+
   # The following are optional properties for "usb-c-connector" with power
   # delivery support.
   source-pdos:
@@ -192,6 +210,12 @@ allOf:
 type:
   const: micro
 
+anyOf:
+  - not:
+  required:
+- typec-power-opmode
+- new-source-frs-typec-current
+
 additionalProperties: true
 
 examples:
-- 
2.17.1

[PATCH v5 4/5] ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx

[Amelie Delaunay]

This patch adds support for STUSB1600 USB Type-C port controller, used on
I2C4 on stm32mp15xx-dkx.
The default configuration on this board, on Type-C connector, is:
- Dual Power Role (DRP), so set power-role to "dual";
- Vbus limited to 500mA, so set typec-power-opmode to "default" (it means
  500mA in USB 2.0).
typec-power-opmode is used to reconfigure the STUSB1600 advertising of
current capability when its NVM is not in line with the board layout.
On stm32mp15xx-dkx, Vbus power source of STUSB1600 is 5V_VIN. So power
operation mode depends on the power supply used. To avoid any power
issues, it is better to limit Vbus to 500mA on this board.
ALERT# is the interrupt pin of STUSB1600. It needs an external pull-up, and
signal is active low.

USB OTG controller ID and Vbus signals are not connected on stm32mp15xx-dkx
boards, so disconnection are not detected.
Without DWC2 usb-role-switch:
- if you unplug the USB cable from the Type-C port, you have to manually
disconnect the USB gadget:
echo disconnect > 
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
- Then you can plug the USB cable again in the Type-C port, and manually
reconnect the USB gadget:
echo connect > 
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi |  7 ++
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi   | 30 
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index d84686e00370..d2e9e7ac3336 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1591,6 +1591,13 @@
};
};
 
+   stusb1600_pins_a: stusb1600-0 {
+   pins {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = ; /* UART4_TX */
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 93398cfae97e..ff324b151609 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -238,6 +238,30 @@
/delete-property/dmas;
/delete-property/dma-names;
 
+   stusb1600@28 {
+   compatible = "st,stusb1600";
+   reg = <0x28>;
+   interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+   interrupt-parent = <&gpioi>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&stusb1600_pins_a>;
+   status = "okay";
+   vdd-supply = <&vin>;
+
+   connector {
+   compatible = "usb-c-connector";
+   label = "USB-C";
+   power-role = "dual";
+   typec-power-opmode = "default";
+
+   port {
+   con_usbotg_hs_ep: endpoint {
+   remote-endpoint = <&usbotg_hs_ep>;
+   };
+   };
+   };
+   };
+
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
@@ -648,6 +672,12 @@
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
+
+   port {
+   usbotg_hs_ep: endpoint {
+   remote-endpoint = <&con_usbotg_hs_ep>;
+   };
+   };
 };
 
 &usbphyc {
-- 
2.17.1

[PATCH v5 0/5] STUSB1600 support on STM32MP15xx-DKx

[Amelie Delaunay]

This series adds missing bindings for Type-C typec-power-opmode property
and STUSB160x Type-C port controllers [1].
STUSB160x driver requires to get power operation mode via device tree,
that's why this series also adds the optional DT property
typec-power-opmode for usb-c-connector to select the power operation mode
capability.
Tested on stm32mp157c-dk2 [2], which has a Type-C connector managed by
STUSB1600, and connected to USB OTG controller. 

[1] 
https://www.st.com/en/interfaces-and-transceivers/usb-type-c-and-power-delivery-controllers.html
[2] https://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html


Amelie Delaunay (5):
  dt-bindings: connector: add typec-power-opmode property to
usb-connector
  dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
  usb: typec: stusb160x: fix power-opmode property with
typec-power-opmode
  ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
  ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller
support

---
Changes in v5:
- add additionalProperties to st,stusb160x yaml
- add Heikki reviewed-by on stusb160x driver patch 3/5
Changes in v4:
- power-opmode DT property renamed to typec-power-opmode and mutually
  exclusive condition with new-source-frs-typec-current added
- Due to DT property renaming, patch 3/5 is added to update stusb160x
  driver.
---
 .../bindings/connector/usb-connector.yaml | 24 +
 .../devicetree/bindings/usb/st,stusb160x.yaml | 87 +++
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi  |  7 ++
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi| 30 +++
 arch/arm/configs/multi_v7_defconfig   |  2 +
 drivers/usb/typec/stusb160x.c |  2 +-
 6 files changed, 151 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml

-- 
2.17.1

[PATCH v5 2/5] dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller

[Amelie Delaunay]

Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.

Signed-off-by: Amelie Delaunay 
---
 .../devicetree/bindings/usb/st,stusb160x.yaml | 87 +++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml

diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml 
b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml
new file mode 100644
index ..9a51efa9d101
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: STMicroelectronics STUSB160x Type-C controller bindings
+
+maintainers:
+  - Amelie Delaunay 
+
+properties:
+  compatible:
+enum:
+  - st,stusb1600
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  vdd-supply:
+description: main power supply (4.1V-22V)
+
+  vsys-supply:
+description: low power supply (3.0V-5.5V)
+
+  vconn-supply:
+description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
+  source or dual power role
+
+  connector:
+type: object
+
+allOf:
+  - $ref: ../connector/usb-connector.yaml
+
+properties:
+  compatible:
+const: usb-c-connector
+
+  power-role: true
+
+  typec-power-opmode: true
+
+required:
+  - compatible
+
+required:
+  - compatible
+  - reg
+  - connector
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+i2c4 {
+#address-cells = <1>;
+#size-cells = <0>;
+
+typec: stusb1600@28 {
+compatible = "st,stusb1600";
+reg = <0x28>;
+vdd-supply = <&vbus_drd>;
+vsys-supply = <&vdd_usb>;
+interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+interrupt-parent = <&gpioi>;
+
+typec_con: connector {
+compatible = "usb-c-connector";
+label = "USB-C";
+power-role = "dual";
+data-role = "dual";
+typec-power-opmode = "default";
+
+port {
+typec_con_ep: endpoint {
+remote-endpoint = <&usbotg_hs_ep>;
+};
+};
+};
+};
+};
+...
-- 
2.17.1

[PATCH v5 5/5] ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller support

[Amelie Delaunay]

Enable support for the STMicroelectronics STUSB160X USB Type-C port
controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as
modules.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index a611b0c1e540..47eed80268e2 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -829,6 +829,8 @@ CONFIG_USB_CONFIGFS_F_HID=y
 CONFIG_USB_CONFIGFS_F_UVC=y
 CONFIG_USB_CONFIGFS_F_PRINTER=y
 CONFIG_USB_ETH=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_STUSB160X=m
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
-- 
2.17.1

[PATCH v5 3/5] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie Delaunay]

Device tree property is named typec-power-opmode, not power-opmode.

Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller 
family")
Signed-off-by: Amelie Delaunay 
Reviewed-by: Heikki Krogerus 
---
 drivers/usb/typec/stusb160x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/typec/stusb160x.c b/drivers/usb/typec/stusb160x.c
index 2a618f02f4f1..d2175044 100644
--- a/drivers/usb/typec/stusb160x.c
+++ b/drivers/usb/typec/stusb160x.c
@@ -562,7 +562,7 @@ static int stusb160x_get_fw_caps(struct stusb160x *chip,
 * Supported power operation mode can be configured through device tree
 * else it is read from chip registers in stusb160x_get_caps.
 */
-   ret = fwnode_property_read_string(fwnode, "power-opmode", &cap_str);
+   ret = fwnode_property_read_string(fwnode, "typec-power-opmode", 
&cap_str);
if (!ret) {
ret = typec_find_pwr_opmode(cap_str);
/* Power delivery not yet supported */
-- 
2.17.1

[PATCH v4 4/5] ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx

[Amelie Delaunay]

This patch adds support for STUSB1600 USB Type-C port controller, used on
I2C4 on stm32mp15xx-dkx.
The default configuration on this board, on Type-C connector, is:
- Dual Power Role (DRP), so set power-role to "dual";
- Vbus limited to 500mA, so set typec-power-opmode to "default" (it means
  500mA in USB 2.0).
typec-power-opmode is used to reconfigure the STUSB1600 advertising of
current capability when its NVM is not in line with the board layout.
On stm32mp15xx-dkx, Vbus power source of STUSB1600 is 5V_VIN. So power
operation mode depends on the power supply used. To avoid any power
issues, it is better to limit Vbus to 500mA on this board.
ALERT# is the interrupt pin of STUSB1600. It needs an external pull-up, and
signal is active low.

USB OTG controller ID and Vbus signals are not connected on stm32mp15xx-dkx
boards, so disconnection are not detected.
Without DWC2 usb-role-switch:
- if you unplug the USB cable from the Type-C port, you have to manually
disconnect the USB gadget:
echo disconnect > 
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
- Then you can plug the USB cable again in the Type-C port, and manually
reconnect the USB gadget:
echo connect > 
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi |  7 ++
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi   | 30 
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index d84686e00370..d2e9e7ac3336 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1591,6 +1591,13 @@
};
};
 
+   stusb1600_pins_a: stusb1600-0 {
+   pins {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = ; /* UART4_TX */
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 93398cfae97e..ff324b151609 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -238,6 +238,30 @@
/delete-property/dmas;
/delete-property/dma-names;
 
+   stusb1600@28 {
+   compatible = "st,stusb1600";
+   reg = <0x28>;
+   interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+   interrupt-parent = <&gpioi>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&stusb1600_pins_a>;
+   status = "okay";
+   vdd-supply = <&vin>;
+
+   connector {
+   compatible = "usb-c-connector";
+   label = "USB-C";
+   power-role = "dual";
+   typec-power-opmode = "default";
+
+   port {
+   con_usbotg_hs_ep: endpoint {
+   remote-endpoint = <&usbotg_hs_ep>;
+   };
+   };
+   };
+   };
+
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
@@ -648,6 +672,12 @@
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
+
+   port {
+   usbotg_hs_ep: endpoint {
+   remote-endpoint = <&con_usbotg_hs_ep>;
+   };
+   };
 };
 
 &usbphyc {
-- 
2.17.1

[PATCH v4 5/5] ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller support

[Amelie Delaunay]

Enable support for the STMicroelectronics STUSB160X USB Type-C port
controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as
modules.

Signed-off-by: Amelie Delaunay 
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index a611b0c1e540..47eed80268e2 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -829,6 +829,8 @@ CONFIG_USB_CONFIGFS_F_HID=y
 CONFIG_USB_CONFIGFS_F_UVC=y
 CONFIG_USB_CONFIGFS_F_PRINTER=y
 CONFIG_USB_ETH=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_STUSB160X=m
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
-- 
2.17.1

[PATCH v4 2/5] dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller

[Amelie Delaunay]

Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.

Signed-off-by: Amelie Delaunay 
---
 .../devicetree/bindings/usb/st,stusb160x.yaml | 85 +++
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml

diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml 
b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml
new file mode 100644
index ..882450571db6
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: STMicroelectronics STUSB160x Type-C controller bindings
+
+maintainers:
+  - Amelie Delaunay 
+
+properties:
+  compatible:
+enum:
+  - st,stusb1600
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  vdd-supply:
+description: main power supply (4.1V-22V)
+
+  vsys-supply:
+description: low power supply (3.0V-5.5V)
+
+  vconn-supply:
+description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
+  source or dual power role
+
+  connector:
+type: object
+
+allOf:
+  - $ref: ../connector/usb-connector.yaml
+
+properties:
+  compatible:
+const: usb-c-connector
+
+  power-role: true
+
+  typec-power-opmode: true
+
+required:
+  - compatible
+
+required:
+  - compatible
+  - reg
+  - connector
+
+examples:
+  - |
+#include 
+i2c4 {
+#address-cells = <1>;
+#size-cells = <0>;
+
+typec: stusb1600@28 {
+compatible = "st,stusb1600";
+reg = <0x28>;
+vdd-supply = <&vbus_drd>;
+vsys-supply = <&vdd_usb>;
+interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+interrupt-parent = <&gpioi>;
+
+typec_con: connector {
+compatible = "usb-c-connector";
+label = "USB-C";
+power-role = "dual";
+data-role = "dual";
+typec-power-opmode = "default";
+
+port {
+typec_con_ep: endpoint {
+remote-endpoint = <&usbotg_hs_ep>;
+};
+};
+};
+};
+};
+...
-- 
2.17.1

[PATCH v4 3/5] usb: typec: stusb160x: fix power-opmode property with typec-power-opmode

[Amelie Delaunay]

Device tree property is named typec-power-opmode, not power-opmode.

Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller 
family")
Signed-off-by: Amelie Delaunay 
---
 drivers/usb/typec/stusb160x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/typec/stusb160x.c b/drivers/usb/typec/stusb160x.c
index 2a618f02f4f1..d2175044 100644
--- a/drivers/usb/typec/stusb160x.c
+++ b/drivers/usb/typec/stusb160x.c
@@ -562,7 +562,7 @@ static int stusb160x_get_fw_caps(struct stusb160x *chip,
 * Supported power operation mode can be configured through device tree
 * else it is read from chip registers in stusb160x_get_caps.
 */
-   ret = fwnode_property_read_string(fwnode, "power-opmode", &cap_str);
+   ret = fwnode_property_read_string(fwnode, "typec-power-opmode", 
&cap_str);
if (!ret) {
ret = typec_find_pwr_opmode(cap_str);
/* Power delivery not yet supported */
-- 
2.17.1

[PATCH v4 1/5] dt-bindings: connector: add typec-power-opmode property to usb-connector

[Amelie Delaunay]

Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.

Signed-off-by: Amelie Delaunay 
---
Hi Bahdri, Rob,

I've added the exlusion with FRS property, but new FRS property name
should be use here so, be careful.

---
 .../bindings/connector/usb-connector.yaml | 24 +++
 1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 62781518aefc..a84464b3e1f2 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
   - device
   - dual
 
+  typec-power-opmode:
+description: Determines the power operation mode that the Type C connector
+  will support and will advertise through CC pins when it has no power
+  delivery support.
+  - "default" corresponds to default USB voltage and current defined by the
+USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+operation respectively.
+  - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+Type-C Cable and Connector specification, when Power Delivery is not
+supported.
+allOf:
+  - $ref: /schemas/types.yaml#definitions/string
+enum:
+  - default
+  - 1.5A
+  - 3.0A
+
   # The following are optional properties for "usb-c-connector" with power
   # delivery support.
   source-pdos:
@@ -192,6 +210,12 @@ allOf:
 type:
   const: micro
 
+anyOf:
+  - not:
+  required:
+- typec-power-opmode
+- new-source-frs-typec-current
+
 additionalProperties: true
 
 examples:
-- 
2.17.1

[PATCH v4 0/5] STUSB1600 support on STM32MP15xx-DKx

[Amelie Delaunay]

This series adds missing bindings for Type-C typec-power-opmode property
and STUSB160x Type-C port controllers [1].
STUSB160x driver requires to get power operation mode via device tree,
that's why this series also adds the optional DT property
typec-power-opmode for usb-c-connector to select the power operation mode
capability.
Tested on stm32mp157c-dk2 [2], which has a Type-C connector managed by
STUSB1600, and connected to USB OTG controller. 

[1] 
https://www.st.com/en/interfaces-and-transceivers/usb-type-c-and-power-delivery-controllers.html
[2] https://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html

Amelie Delaunay (4):
  dt-bindings: connector: add power-opmode optional property to
usb-connector
  dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
  usb: typec: stusb160x: fix power-opmode property with
typec-power-opmode
  ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
  ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller
support

---
Changes in v4:
- power-opmode DT property renamed to typec-power-opmode and mutually
  exclusive condition with new-source-frs-typec-current added
- Due to DT property renaming, patch 3/5 is added to update stusb160x
  driver.
---
 .../bindings/connector/usb-connector.yaml | 24 ++
 .../devicetree/bindings/usb/st,stusb160x.yaml | 85 +++
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi  |  7 ++
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi| 30 +++
 arch/arm/configs/multi_v7_defconfig   |  2 +
 drivers/usb/typec/stusb160x.c |  2 +-
 6 files changed, 149 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml

-- 
2.17.1

Re: [RESEND PATCH v3 1/4] dt-bindings: connector: add power-opmode optional property to usb-connector

[Amelie DELAUNAY]

Hi Badhri,

On 11/6/20 4:10 AM, Badhri Jagan Sridharan wrote:

Hi Rob and Amelie,

With regards to discussions in this thread,
For https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com,
I can send in a patch to update the new-source-frs-typec-current property.
Amelie, If you are already planning to send that I am fine with that as well.
Let me know !

To summarize the changes for new-source-frs-typec-current would be,
1. Rename to frs-new-source-opmode
2. Use string values instead of u32 similar to typec-power-opmode.
Are these correct ?



You can send patches to rename the new-source-frq-typec-current property 
into frs-new-source-opmode, and update the tcpm as well. You can use the 
typec_find_pwr_opmode(), it will return

enum typec_pwr_opmode {
TYPEC_PWR_MODE_USB,
TYPEC_PWR_MODE_1_5A,
TYPEC_PWR_MODE_3_0A,
TYPEC_PWR_MODE_PD,
};
Then you have to translate it for FRS.

I'll send a new version of my series to document typec-power-opmode and 
update stusb160x driver and stm32mp15xx-dkx device tree accordingly.


Thanks,
Amelie



Thanks,
Badhri

On Thu, Nov 5, 2020 at 7:55 AM Rob Herring  wrote:


On Thu, Nov 5, 2020 at 6:24 AM Jun Li  wrote:


Amelie DELAUNAY  于2020年11月5日周四 下午7:36写道：


On 11/4/20 10:08 PM, Rob Herring wrote:

On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:



On 10/30/20 3:29 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY  wrote:




On 10/29/20 4:40 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:

Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.

Signed-off-by: Amelie Delaunay 
---
 .../bindings/connector/usb-connector.yaml  | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 728f82db073d..200d19c60fd5 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
   - device
   - dual

+  power-opmode:


I've acked this version:

https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com



frs is used for Fast Role Swap defined in USB PD spec.
I understand it allows to get the same information but I'm wondering why
the property name is limited to -frs- in this case. What about a
non-power delivery USB-C connector ?


I've got no idea. The folks that know USB-C and PD details need to get
together and work all this out. To me, it looks like the same thing...



It looks but...

The purpose of power-opmode property is to configure the USB-C controllers,
especially the non-PD USB-C controllers to determine the power operation
mode that the Type C connector will support and will advertise through CC
pins when it has no power delivery support, whatever the power role: Sink,
Source or Dual
The management of the property is the same that data-role and power-role
properties, and done by USB Type-C Connector Class.

new-source-frs-typec-current specifies initial current capability of the new
source when vSafe5V is applied during PD3.0 Fast Role Swap. So here, this
property is not applied at usb-c controller configuration level, but during
PD Fast Role Swap, so when the Sink become the Source.
Moreover, the related driver code says FRS can only be supported by DRP
ports. So new-source-frs-typec-current property, in addition to being
specific to PD, is also dedicated to DRP usb-c controller.
The property is managed by Type-C Port Controller Manager for PD.


But it's the same set of possible values, right? So we can align the
values at least.



USB Power Delivery FRS values are defined in
include/dt-bindings/usb/pd.h


I think this can be changed if both can be aligned.


to fit with drivers/usb/typec/tcpm/tcpm.c
frs_typec_current enum.

USB-C power operation mode values are defined in
include/linux/usb/typec.h with typec_pwr_opmode enum and matching with
string values of typec_pwr_opmodes tab.

USB PD requires USB-C.
USB-C doesn't requires USB PD.

drivers/usb/typec/tcpm/tcpm.c already used typec_pwr_opmode values.

USB PD specification Table 6-14 Fixed Supply PDO says:
Fast Role Swap required USB Type-C Current (see also [USB Type-C 2.0]):
Value | Description
   00b  | Fast Swap not supported (default)
   01b  | Default USB Power
   10b  | 1.5A @ 5V
   11b  | 3.0A @ 5V


This is the value in PDO of sink, the FRS property value(or after translated)
actually is used to compare with above value.

So I think both properties can share the same "value", maybe string
like below

   10 static const char * const typec_pwr_opmodes[] = {
   11 [TYPEC_PWR_MODE_USB]= "default",
   

Re: [RESEND PATCH v3 1/4] dt-bindings: connector: add power-opmode optional property to usb-connector

[Amelie DELAUNAY]

On 11/5/20 1:23 PM, Jun Li wrote:

Amelie DELAUNAY  于2020年11月5日周四 下午7:36写道：


On 11/4/20 10:08 PM, Rob Herring wrote:

On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:



On 10/30/20 3:29 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY  wrote:




On 10/29/20 4:40 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:

Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.

Signed-off-by: Amelie Delaunay 
---
 .../bindings/connector/usb-connector.yaml  | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 728f82db073d..200d19c60fd5 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
   - device
   - dual

+  power-opmode:


I've acked this version:

https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com



frs is used for Fast Role Swap defined in USB PD spec.
I understand it allows to get the same information but I'm wondering why
the property name is limited to -frs- in this case. What about a
non-power delivery USB-C connector ?


I've got no idea. The folks that know USB-C and PD details need to get
together and work all this out. To me, it looks like the same thing...



It looks but...

The purpose of power-opmode property is to configure the USB-C controllers,
especially the non-PD USB-C controllers to determine the power operation
mode that the Type C connector will support and will advertise through CC
pins when it has no power delivery support, whatever the power role: Sink,
Source or Dual
The management of the property is the same that data-role and power-role
properties, and done by USB Type-C Connector Class.

new-source-frs-typec-current specifies initial current capability of the new
source when vSafe5V is applied during PD3.0 Fast Role Swap. So here, this
property is not applied at usb-c controller configuration level, but during
PD Fast Role Swap, so when the Sink become the Source.
Moreover, the related driver code says FRS can only be supported by DRP
ports. So new-source-frs-typec-current property, in addition to being
specific to PD, is also dedicated to DRP usb-c controller.
The property is managed by Type-C Port Controller Manager for PD.


But it's the same set of possible values, right? So we can align the
values at least.



USB Power Delivery FRS values are defined in
include/dt-bindings/usb/pd.h


I think this can be changed if both can be aligned.


to fit with drivers/usb/typec/tcpm/tcpm.c
frs_typec_current enum.

USB-C power operation mode values are defined in
include/linux/usb/typec.h with typec_pwr_opmode enum and matching with
string values of typec_pwr_opmodes tab.

USB PD requires USB-C.
USB-C doesn't requires USB PD.

drivers/usb/typec/tcpm/tcpm.c already used typec_pwr_opmode values.

USB PD specification Table 6-14 Fixed Supply PDO says:
Fast Role Swap required USB Type-C Current (see also [USB Type-C 2.0]):
Value | Description
   00b  | Fast Swap not supported (default)
   01b  | Default USB Power
   10b  | 1.5A @ 5V
   11b  | 3.0A @ 5V


This is the value in PDO of sink, the FRS property value(or after translated)
actually is used to compare with above value.

So I think both properties can share the same "value", maybe string
like below

   10 static const char * const typec_pwr_opmodes[] = {
   11 [TYPEC_PWR_MODE_USB]= "default",
   12 [TYPEC_PWR_MODE_1_5A]   = "1.5A",
   13 [TYPEC_PWR_MODE_3_0A]   = "3.0A",



Note the *see also USB Type-C 2.0*.

USB Type-C specification 4.6.2.1 USB Type-C Current says:
The USB Type-C connector uses CC pins for configuration including an
ability for a Source to advertise to its port partner (Sink) the amount
of current it shall supply:
• Default is the as-configured for high-power operation current value as
defined by the USB Specification (500 mA for USB 2.0 ports; 900 mA or
1,500 mA for USB 3.2 ports in single-lane or dual-lane operation,
respectively)
• 1.5 A
• 3.0 A


Can we align the names in some way? power-opmode and frs-source-opmode
or ??


how about typec-power-opmode and frs-new-source-opmode



I agree with typec-power-opmode. And with string values. This way, 
typec_find_pwr_opmode is still usable to translate into TYPEC defines.






I let USB PD specialists answer.

*frs* property fits with USB PD specification, so with USB PD protocol.
*power-opmode fits with USB Type-C specification, so with USB-C hardware
support.


Are these 2 properties mutually exclusive?


I think yes.

thanks
Li Jun

If so, that should be
captured.

Re: [RESEND PATCH v3 1/4] dt-bindings: connector: add power-opmode optional property to usb-connector

[Amelie DELAUNAY]

On 11/4/20 10:08 PM, Rob Herring wrote:

On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:



On 10/30/20 3:29 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY  wrote:




On 10/29/20 4:40 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:

Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.

Signed-off-by: Amelie Delaunay 
---
.../bindings/connector/usb-connector.yaml  | 18 ++
1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 728f82db073d..200d19c60fd5 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
  - device
  - dual

+  power-opmode:


I've acked this version:

https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com



frs is used for Fast Role Swap defined in USB PD spec.
I understand it allows to get the same information but I'm wondering why
the property name is limited to -frs- in this case. What about a
non-power delivery USB-C connector ?


I've got no idea. The folks that know USB-C and PD details need to get
together and work all this out. To me, it looks like the same thing...



It looks but...

The purpose of power-opmode property is to configure the USB-C controllers,
especially the non-PD USB-C controllers to determine the power operation
mode that the Type C connector will support and will advertise through CC
pins when it has no power delivery support, whatever the power role: Sink,
Source or Dual
The management of the property is the same that data-role and power-role
properties, and done by USB Type-C Connector Class.

new-source-frs-typec-current specifies initial current capability of the new
source when vSafe5V is applied during PD3.0 Fast Role Swap. So here, this
property is not applied at usb-c controller configuration level, but during
PD Fast Role Swap, so when the Sink become the Source.
Moreover, the related driver code says FRS can only be supported by DRP
ports. So new-source-frs-typec-current property, in addition to being
specific to PD, is also dedicated to DRP usb-c controller.
The property is managed by Type-C Port Controller Manager for PD.


But it's the same set of possible values, right? So we can align the
values at least.



USB Power Delivery FRS values are defined in 
include/dt-bindings/usb/pd.h to fit with drivers/usb/typec/tcpm/tcpm.c 
frs_typec_current enum.


USB-C power operation mode values are defined in 
include/linux/usb/typec.h with typec_pwr_opmode enum and matching with 
string values of typec_pwr_opmodes tab.


USB PD requires USB-C.
USB-C doesn't requires USB PD.

drivers/usb/typec/tcpm/tcpm.c already used typec_pwr_opmode values.

USB PD specification Table 6-14 Fixed Supply PDO says:
Fast Role Swap required USB Type-C Current (see also [USB Type-C 2.0]):
Value | Description
 00b  | Fast Swap not supported (default)
 01b  | Default USB Power
 10b  | 1.5A @ 5V
 11b  | 3.0A @ 5V

Note the *see also USB Type-C 2.0*.

USB Type-C specification 4.6.2.1 USB Type-C Current says:
The USB Type-C connector uses CC pins for configuration including an 
ability for a Source to advertise to its port partner (Sink) the amount 
of current it shall supply:
• Default is the as-configured for high-power operation current value as 
defined by the USB Specification (500 mA for USB 2.0 ports; 900 mA or 
1,500 mA for USB 3.2 ports in single-lane or dual-lane operation, 
respectively)

• 1.5 A
• 3.0 A


Can we align the names in some way? power-opmode and frs-source-opmode
or ??



I let USB PD specialists answer.

*frs* property fits with USB PD specification, so with USB PD protocol.
*power-opmode fits with USB Type-C specification, so with USB-C hardware 
support.



Are these 2 properties mutually exclusive? If so, that should be
captured.


FRS is specific to products with Power Delivery Support.

power-opmode is dedicated to products with USB-C connector support.

Regards,
Amelie

Re: [RESEND PATCH v3 1/4] dt-bindings: connector: add power-opmode optional property to usb-connector

[Amelie DELAUNAY]

On 10/30/20 3:29 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY  wrote:




On 10/29/20 4:40 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:

Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.

Signed-off-by: Amelie Delaunay 
---
   .../bindings/connector/usb-connector.yaml  | 18 ++
   1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 728f82db073d..200d19c60fd5 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
 - device
 - dual

+  power-opmode:


I've acked this version:

https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com



frs is used for Fast Role Swap defined in USB PD spec.
I understand it allows to get the same information but I'm wondering why
the property name is limited to -frs- in this case. What about a
non-power delivery USB-C connector ?


I've got no idea. The folks that know USB-C and PD details need to get
together and work all this out. To me, it looks like the same thing...



It looks but...

The purpose of power-opmode property is to configure the USB-C 
controllers, especially the non-PD USB-C controllers to determine the 
power operation mode that the Type C connector will support and will 
advertise through CC pins when it has no power delivery support, 
whatever the power role: Sink, Source or Dual
The management of the property is the same that data-role and power-role 
properties, and done by USB Type-C Connector Class.


new-source-frs-typec-current specifies initial current capability of the 
new source when vSafe5V is applied during PD3.0 Fast Role Swap. So here, 
this property is not applied at usb-c controller configuration level, 
but during PD Fast Role Swap, so when the Sink become the Source.
Moreover, the related driver code says FRS can only be supported by DRP 
ports. So new-source-frs-typec-current property, in addition to being 
specific to PD, is also dedicated to DRP usb-c controller.

The property is managed by Type-C Port Controller Manager for PD.


And it's not just this, but the stream of USB-C additions that trickle in.


Moreover, power-opmode property support is already merged in typec class:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/usb/typec/class.c?h=v5.10-rc1&id=12f3467b0d28369d3add7a0deb65fdac9b503c90
and stusb160x driver uses it :(

So, do I need to modify stusb160x driver (and bindings) to take into
account this USB PD specific property?


If not documented, then it's not an ABI, so yes.


I have tried to document it since months ago
v1: https://lkml.org/lkml/2020/6/15/927
v2: https://lkml.org/lkml/2020/7/23/445 integrating your remarks
v2 RESENT: https://lkml.org/lkml/2020/9/2/174
v3: https://lkml.org/lkml/2020/9/24/306 integrated Li Jun remarks

Regards,
Amelie

Re: [RESEND PATCH v3 1/4] dt-bindings: connector: add power-opmode optional property to usb-connector

[Amelie DELAUNAY]

On 10/29/20 4:40 PM, Rob Herring wrote:

On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:

Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.

Signed-off-by: Amelie Delaunay 
---
  .../bindings/connector/usb-connector.yaml  | 18 ++
  1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml 
b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index 728f82db073d..200d19c60fd5 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -93,6 +93,24 @@ properties:
- device
- dual
  
+  power-opmode:


I've acked this version:

https://lore.kernel.org/r/20201020093627.256885-2-bad...@google.com



frs is used for Fast Role Swap defined in USB PD spec.
I understand it allows to get the same information but I'm wondering why 
the property name is limited to -frs- in this case. What about a 
non-power delivery USB-C connector ?


Moreover, power-opmode property support is already merged in typec class:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/usb/typec/class.c?h=v5.10-rc1&id=12f3467b0d28369d3add7a0deb65fdac9b503c90
and stusb160x driver uses it :(

So, do I need to modify stusb160x driver (and bindings) to take into 
account this USB PD specific property?


Regards,
Amelie


Please ack it if you are okay with it.

Rob



+description: Determines the power operation mode that the Type C connector
+  will support and will advertise through CC pins when it has no power
+  delivery support.
+  - "default" corresponds to default USB voltage and current defined by the
+USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+operation respectively.
+  - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+Type-C Cable and Connector specification, when Power Delivery is not
+supported.
+allOf:
+  - $ref: /schemas/types.yaml#definitions/string
+enum:
+  - default
+  - 1.5A
+  - 3.0A
+
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:
--
2.17.1