[PATCH] qmi_wwan: apply SET_DTR quirk to Sierra WP7607

[Beniamino Galvani]

The 1199:68C0 USB ID is reused by Sierra WP7607 which requires the DTR
quirk to be detected. Apply QMI_QUIRK_SET_DTR unconditionally as
already done for other IDs shared between different devices.

Signed-off-by: Beniamino Galvani 
---
 drivers/net/usb/qmi_wwan.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 735ad838e2ba..18af2f8eee96 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -1201,8 +1201,8 @@ static const struct usb_device_id products[] = {
{QMI_FIXED_INTF(0x114f, 0x68a2, 8)},/* Sierra Wireless MC7750 */
{QMI_FIXED_INTF(0x1199, 0x68a2, 8)},/* Sierra Wireless MC7710 in 
QMI mode */
{QMI_FIXED_INTF(0x1199, 0x68a2, 19)},   /* Sierra Wireless MC7710 in 
QMI mode */
-   {QMI_FIXED_INTF(0x1199, 0x68c0, 8)},/* Sierra Wireless 
MC7304/MC7354 */
-   {QMI_FIXED_INTF(0x1199, 0x68c0, 10)},   /* Sierra Wireless 
MC7304/MC7354 */
+   {QMI_QUIRK_SET_DTR(0x1199, 0x68c0, 8)}, /* Sierra Wireless 
MC7304/MC7354, WP76xx */
+   {QMI_QUIRK_SET_DTR(0x1199, 0x68c0, 10)},/* Sierra Wireless 
MC7304/MC7354 */
{QMI_FIXED_INTF(0x1199, 0x901c, 8)},/* Sierra Wireless EM7700 */
{QMI_FIXED_INTF(0x1199, 0x901f, 8)},/* Sierra Wireless EM7355 */
{QMI_FIXED_INTF(0x1199, 0x9041, 8)},/* Sierra Wireless 
MC7305/MC7355 */
-- 
2.20.1

Re: [PATCH] pinctrl: meson: fix gpio request disabling other modes

[Beniamino Galvani]

On Tue, Dec 06, 2016 at 03:08:16PM +0100, Neil Armstrong wrote:
> The pinctrl_gpio_request is called with the "full" gpio number, already
> containing the base, then meson_pmx_request_gpio is then called with the
> final pin number.
> Remove the base addition when calling meson_pmx_disable_other_groups.
> 
> Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
> CC: Beniamino Galvani 
> Signed-off-by: Neil Armstrong 

Acked-by: Beniamino Galvani 

[PATCH] pinctrl: meson: get rid of unneeded domain structures

[Beniamino Galvani]

The driver originally supported more domains (register ranges) per
pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make
driver independent from two-domain configuration") each device gets
assigned a single domain and we instantiate multiple pinctrl devices
in the DT.

Therefore, now the 'meson_domain' and 'meson_domain_data' structures
don't have any reason to exist and can be removed to make the model
simpler to understand. This commit doesn't change behavior.

Tested on a Odroid-C2.

Signed-off-by: Beniamino Galvani 
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c |  24 +---
 drivers/pinctrl/meson/pinctrl-meson.c  | 222 +++--
 drivers/pinctrl/meson/pinctrl-meson.h  |  52 ++-
 drivers/pinctrl/meson/pinctrl-meson8.c |  24 +---
 drivers/pinctrl/meson/pinctrl-meson8b.c|  24 +---
 5 files changed, 118 insertions(+), 228 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c 
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad..233c9c8 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -556,38 +556,28 @@ static struct meson_bank meson_gxbb_aobus_banks[] = {
BANK("AO",   PIN(GPIOAO_0, 0),  PIN(GPIOAO_13, 0), 0,  0,  0, 16,  0,  
0,  0, 16,  1,  0),
 };
 
-static struct meson_domain_data meson_gxbb_periphs_domain_data = {
+struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.name   = "periphs-banks",
-   .banks  = meson_gxbb_periphs_banks,
-   .num_banks  = ARRAY_SIZE(meson_gxbb_periphs_banks),
.pin_base   = 14,
-   .num_pins   = 120,
-};
-
-static struct meson_domain_data meson_gxbb_aobus_domain_data = {
-   .name   = "aobus-banks",
-   .banks  = meson_gxbb_aobus_banks,
-   .num_banks  = ARRAY_SIZE(meson_gxbb_aobus_banks),
-   .pin_base   = 0,
-   .num_pins   = 14,
-};
-
-struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.pins   = meson_gxbb_periphs_pins,
.groups = meson_gxbb_periphs_groups,
.funcs  = meson_gxbb_periphs_functions,
-   .domain_data= &meson_gxbb_periphs_domain_data,
+   .banks  = meson_gxbb_periphs_banks,
.num_pins   = ARRAY_SIZE(meson_gxbb_periphs_pins),
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs  = ARRAY_SIZE(meson_gxbb_periphs_functions),
+   .num_banks  = ARRAY_SIZE(meson_gxbb_periphs_banks),
 };
 
 struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
+   .name   = "aobus-banks",
+   .pin_base   = 0,
.pins   = meson_gxbb_aobus_pins,
.groups = meson_gxbb_aobus_groups,
.funcs  = meson_gxbb_aobus_functions,
-   .domain_data= &meson_gxbb_aobus_domain_data,
+   .banks  = meson_gxbb_aobus_banks,
.num_pins   = ARRAY_SIZE(meson_gxbb_aobus_pins),
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs  = ARRAY_SIZE(meson_gxbb_aobus_functions),
+   .num_banks  = ARRAY_SIZE(meson_gxbb_aobus_banks),
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c 
b/drivers/pinctrl/meson/pinctrl-meson.c
index 11623c6..9678599 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -21,9 +21,8 @@
  * domain which can't be powered off; the bank also uses a set of
  * registers different from the other banks.
  *
- * For each of the two power domains (regular and always-on) there are
- * 4 different register ranges that control the following properties
- * of the pins:
+ * For each pin controller there are 4 different register ranges that
+ * control the following properties of the pins:
  *  1) pin muxing
  *  2) pull enable/disable
  *  3) pull up/down
@@ -33,8 +32,8 @@
  * direction are the same and thus there are only 3 register ranges.
  *
  * Every pinmux group can be enabled by a specific bit in the first
- * register range of the domain; when all groups for a given pin are
- * disabled the pin acts as a GPIO.
+ * register range; when all groups for a given pin are disabled the
+ * pin acts as a GPIO.
  *
  * For the pull and GPIO configuration every bank uses a contiguous
  * set of bits in the register sets described above; the same register
@@ -66,21 +65,21 @@
 /**
  * meson_get_bank() - find the bank containing a given pin
  *
- * @domain:the domain containing the pin
+ * @pc:the pinctrl instance
  * @pin:   the pin number
  * @bank:  the found bank
  *
  * Return: 0 on success, a negative value on error
  */
-static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
+static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
  str

Re: [PATCH 4/8] Documentation: devicetree: Document Tronsmart vendor prefix

[Beniamino Galvani]

On Tue, Mar 01, 2016 at 12:53:55PM +0100, Andreas Färber wrote:
> Searching for it, I even found a similar 2014 patch from Beniamino
> Galvani (CC'ed), without any review replies.
> 
> I'll happily pick up one of the previous patches instead. Sorry, was in
> a hurry to clean this series up for Nicolas (Mini Mx) and to avoid any
> Odroid-C2 users duplicating my work.

Yeah, my patch was never merged for reasons that I don't remeber;
anyway I'm fine with your patch.

Beniamino

[PATCH v2] net: stmmac: add BQL support

[Beniamino Galvani]

Add support for Byte Queue Limits to the STMicro MAC driver.

Tested on a Amlogic S802 quad Cortex-A9 board, where the use of BQL
decreases the latency of a high priority ping from ~12ms to ~1ms when
the 100Mbit link is saturated by 20 TCP streams.

Signed-off-by: Beniamino Galvani 
---
Changes since v1:
 - don't access skb->len after the start of DMA transmission in
   stmmac_xmit(), to avoid potential use after free in case tx_lock is
   removed in the future

 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 118a427..1d74313 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1097,6 +1097,7 @@ static int init_dma_desc_rings(struct net_device *dev, 
gfp_t flags)
 
priv->dirty_tx = 0;
priv->cur_tx = 0;
+   netdev_reset_queue(priv->dev);
 
stmmac_clear_descriptors(priv);
 
@@ -1300,6 +1301,7 @@ static void stmmac_dma_operation_mode(struct stmmac_priv 
*priv)
 static void stmmac_tx_clean(struct stmmac_priv *priv)
 {
unsigned int txsize = priv->dma_tx_size;
+   unsigned int bytes_compl = 0, pkts_compl = 0;
 
spin_lock(&priv->tx_lock);
 
@@ -1356,6 +1358,8 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
priv->hw->mode->clean_desc3(priv, p);
 
if (likely(skb != NULL)) {
+   pkts_compl++;
+   bytes_compl += skb->len;
dev_consume_skb_any(skb);
priv->tx_skbuff[entry] = NULL;
}
@@ -1364,6 +1368,9 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
 
priv->dirty_tx++;
}
+
+   netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
+
if (unlikely(netif_queue_stopped(priv->dev) &&
 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
netif_tx_lock(priv->dev);
@@ -1418,6 +1425,7 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
 (i == txsize - 1));
priv->dirty_tx = 0;
priv->cur_tx = 0;
+   netdev_reset_queue(priv->dev);
priv->hw->dma->start_tx(priv->ioaddr);
 
priv->dev->stats.tx_errors++;
@@ -2048,6 +2056,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, 
struct net_device *dev)
if (!priv->hwts_tx_en)
skb_tx_timestamp(skb);
 
+   netdev_sent_queue(dev, skb->len);
priv->hw->dma->enable_dma_transmission(priv->ioaddr);
 
spin_unlock(&priv->tx_lock);
-- 
2.1.4

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[PATCH 3/3] ARM: dts: meson: add DTS file for MINIX NEO-X8

[Beniamino Galvani]

Add a DTS file for MINIX NEO-X8, a Meson8-based digital media player.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/meson8-minix-neo-x8.dts | 128 ++
 2 files changed, 129 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson8-minix-neo-x8.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91bd5bd..e9ffa5f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -177,6 +177,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
+dtb-$(CONFIG_MACH_MESON8) += meson8-minix-neo-x8.dtb
 dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
pxa910-dkb.dtb \
mmp2-brownstone.dtb
diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts 
b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
new file mode 100644
index 000..4f536bb
--- /dev/null
+++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2014 Beniamino Galvani 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include 
+#include "meson8.dtsi"
+
+/ {
+   model = "MINIX NEO-X8";
+   compatible = "minix,neo-x8", "amlogic,meson8";
+
+   aliases {
+   serial0 = &uart_AO;
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   blue {
+   label = "x8:blue:power";
+   gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
+&uart_AO {
+   status = "okay";
+   pinctrl-0 = <&uart_ao_a_pins>;
+   pinctrl-names = "default";
+};
+
+&i2c_AO {
+   status = "okay";
+   pinctrl-0 = <&i2c_ao_pins>;
+   pinctrl-names = "default";
+
+   pmic@32 {
+   compatible = "ricoh,rn5t618";
+   reg = <0x32>;
+
+   regulators {
+   };
+   };
+
+   rtc@51 {
+   compatible = "nxp,pcf8563";
+   reg = <0x51>;
+   };
+};
+
+&spifc {
+   status = "okay";
+   pinctrl-0 = <&spi_nor_pins>;
+   pinctrl-names = "default";
+
+   spi-flash@0 {
+   compatible = "mxicy,mx25l1606e";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   spi-max-frequency = <3000>;
+
+   partition@0 {
+   label = "boot";
+   reg = <0x0 0x10>;
+   };
+
+   partition@10 {
+   label = "env";
+ 

[PATCH 1/3] of: Add vendor prefix for MINIX

[Beniamino Galvani]

Add MINIX Technology Limited to the list of device tree vendor
prefixes. The company manufactures digital media players and mini-ITX
motherboards.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b1df0ad..09b01de 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -100,6 +100,7 @@ merrii  Merrii Technology Co., Ltd.
 micrel Micrel Inc.
 microchip  Microchip Technology Inc.
 micron Micron Technology Inc.
+minix  MINIX Technology Ltd.
 mitsubishi Mitsubishi Electric Corporation
 mosaixtech Mosaix Technologies, Inc.
 moxa   Moxa
-- 
2.1.4

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[PATCH 0/3] ARM: meson: add support for MINIX NEO-X8

[Beniamino Galvani]

This series adds support for MINIX NEO-X8, a digital media player
based on a Amlogic S802 (Meson8) SoC. It depends on the pinctrl
support for Meson8 submitted here:

  https://lkml.org/lkml/2015/1/17/87

Beniamino Galvani (3):
  of: Add vendor prefix for MINIX
  of: Define board compatible for MINIX NEO-X8
  ARM: dts: meson: add DTS file for MINIX NEO-X8

 Documentation/devicetree/bindings/arm/amlogic.txt  |   4 +
 .../devicetree/bindings/arm/geniatech.txt  |   5 -
 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/meson8-minix-neo-x8.dts  | 128 +
 5 files changed, 134 insertions(+), 5 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/geniatech.txt
 create mode 100644 arch/arm/boot/dts/meson8-minix-neo-x8.dts

-- 
2.1.4

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[PATCH 2/3] of: Define board compatible for MINIX NEO-X8

[Beniamino Galvani]

Document the board compatible property for MINIX NEO-X8, a
Meson8-based digital media player. While at it, move the other
existing Meson board compatible to amlogic.txt.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/arm/amlogic.txt   | 4 
 Documentation/devicetree/bindings/arm/geniatech.txt | 5 -
 2 files changed, 4 insertions(+), 5 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/geniatech.txt

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt 
b/Documentation/devicetree/bindings/arm/amlogic.txt
index 8fe8150..973884a 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -8,3 +8,7 @@ Boards with the Amlogic Meson6 SoC shall have the following 
properties:
 Boards with the Amlogic Meson8 SoC shall have the following properties:
   Required root node property:
 compatible: "amlogic,meson8";
+
+Board compatible values:
+  - "geniatech,atv1200"
+  - "minix,neo-x8"
diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt 
b/Documentation/devicetree/bindings/arm/geniatech.txt
deleted file mode 100644
index 74ccba4..000
--- a/Documentation/devicetree/bindings/arm/geniatech.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Geniatech platforms device tree bindings

-
-Geniatech ATV1200
-- compatible = "geniatech,atv1200"
-- 
2.1.4

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[PATCH v4 2/3] ARM: meson: select PINCTRL_MESON and ARCH_REQUIRE_GPIOLIB

[Beniamino Galvani]

Make sure that the Meson pinctrl driver is built whenever Meson
support is enabled.

Signed-off-by: Beniamino Galvani 
Acked-by: Linus Walleij 
---
 arch/arm/mach-meson/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 18301dc..0743e20 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -1,8 +1,11 @@
 menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
+   select ARCH_REQUIRE_GPIOLIB
select GENERIC_IRQ_CHIP
select ARM_GIC
select CACHE_L2X0
+   select PINCTRL
+   select PINCTRL_MESON
 
 if ARCH_MESON
 
-- 
2.1.4

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[PATCH v4 1/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani 
---
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/meson/Makefile |2 +
 drivers/pinctrl/meson/pinctrl-meson.c  |  761 ++
 drivers/pinctrl/meson/pinctrl-meson.h  |  209 ++
 drivers/pinctrl/meson/pinctrl-meson8.c | 1089 
 include/dt-bindings/gpio/meson8-gpio.h |  157 +
 7 files changed, 2227 insertions(+)
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e738cca..ee9f44a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
 
+config PINCTRL_MESON
+   bool
+   select PINMUX
+   select PINCONF
+   select GENERIC_PINCONF
+   select OF_GPIO
+   select REGMAP_MMIO
+
 config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6c28bd6..0475206 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91)+= pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_BCM2835)  += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_FALCON)   += pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_MESON)+= meson/
 obj-$(CONFIG_PINCTRL_PALMAS)   += pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000..eafc216
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
+obj-y  += pinctrl-meson8.o
+obj-y  += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c 
b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000..a2bf49c
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,761 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
+ * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
+ * each bank has a variable number of pins.
+ *
+ * The AO bank is special because it belongs to the Always-On power
+ * domain which can't be powered off; the bank also uses a set of
+ * registers different from the other banks.
+ *
+ * For each of the two power domains (regular and always-on) there are
+ * 4 different register ranges that control the following properties
+ * of the pins:
+ *  1) pin muxing
+ *  2) pull enable/disable
+ *  3) pull up/down
+ *  4) GPIO direction, output value, input value
+ *
+ * In some cases the register ranges for pull enable and pull
+ * direction are the same and thus there are only 3 register ranges.
+ *
+ * Every pinmux group can be enabled by a specific bit in the first
+ * register range of the domain; when all groups for a given pin are
+ * disabled the pin acts as a GPIO.
+ *
+ * For the pull and GPIO configuration every bank uses a contiguous
+ * set of bits in the register sets described above; the same register
+ * can be shared by more banks with different offsets.
+ *
+ * In addition to this there are some registers shared between all
+ * banks that control the IRQ functionality. This feature is not
+ * supported at the moment by the driver.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-meson.h"
+
+/**
+ * meson_get_bank() - find the bank containing a given pin
+ *
+ * @domain:the domain containing the pin
+ * @pin:   the pin number
+ * @bank:  the found bank
+ *
+ * Return: 0 on success, a negative value on error
+ */
+static int meson_get_bank(stru

[PATCH v4 3/3] ARM: dts: meson8: add pinctrl node

[Beniamino Galvani]

Add pinctrl node to the DTSI file for meson8 and sub-nodes for some
standard mux configurations.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8.dtsi | 68 +++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1f442a7..a2ddcb8 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 /include/ "meson.dtsi"
 
 / {
@@ -89,4 +90,71 @@
compatible = "fixed-clock";
clock-frequency = <14166>;
};
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e8 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull", "pull-enable", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_tx_ao_a", "uart_rx_ao_a";
+   function = "uart_ao";
+   };
+   };
+
+   i2c_ao_pins: i2c_mst_ao {
+   mux {
+   groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
+   function = "i2c_mst_ao";
+   };
+   };
+
+   spi_nor_pins: nor {
+   mux {
+   groups = "nor_d", "nor_q", "nor_c", "nor_cs";
+   function = "nor";
+   };
+   };
+
+   ir_recv_pins: remote {
+   mux {
+   groups = "remote_input";
+   function = "remote";
+   };
+   };
+
+   eth_pins: ethernet {
+   mux {
+   groups = "eth_tx_clk_50m", "eth_tx_en",
+"eth_txd1", "eth_txd0",
+"eth_rx_clk_in", "eth_rx_dv",
+"eth_rxd1", "eth_rxd0", "eth_mdio",
+"eth_mdc";
+   function = "ethernet";
+   };
+   };
+   };
+
 }; /* end of / */
-- 
2.1.4

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[PATCH v4 0/3] Amlogic Meson pinctrl driver

[Beniamino Galvani]

Hi,

this series adds a pinctrl driver for Amlogic Meson, providing common
code for all the SoCs of the family and configuration data specific
for Meson8.

DT binding documentation for the driver has already been merged and is
not included in the series. The first patch is for the pinctrl/devel
tree, the others for Carlo's meson tree.

Thanks,
Beniamino

Changes since v3 [ https://lkml.org/lkml/2014/11/16/171 ]
 - add 'static' to meson8 structs and arrays
 - use ERR_CAST() to avoid sparse warning in meson_map_resource()
 - declare group list as 'const char * const *'

Changes since v2 [ https://lkml.org/lkml/2014/10/14/423 ]
 - move modifications to mach-meson Kconfig to a separate patch
 - use regmap_mmio
 - use generic gpio xlate function
 - don't hardcode gpio base number
 - use gpiochip_add_pin_range()
 - add kerneldoc documentation
 - use plain module_platform_driver() instead of postcore_initcall
 - avoid unneeded copies of platform data

Changes since v1 [ https://lkml.org/lkml/2014/10/7/712 ]
 - added missing checks of return values
 - indentation fixes
 - added missing definitions of groups and functions for Meson8

Beniamino Galvani (3):
  pinctrl: add driver for Amlogic Meson SoCs
  ARM: meson: select PINCTRL_MESON and ARCH_REQUIRE_GPIOLIB
  ARM: dts: meson8: add pinctrl node

 arch/arm/boot/dts/meson8.dtsi  |   68 ++
 arch/arm/mach-meson/Kconfig|3 +
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/meson/Makefile |2 +
 drivers/pinctrl/meson/pinctrl-meson.c  |  761 ++
 drivers/pinctrl/meson/pinctrl-meson.h  |  209 ++
 drivers/pinctrl/meson/pinctrl-meson8.c | 1089 
 include/dt-bindings/gpio/meson8-gpio.h |  157 +
 9 files changed, 2298 insertions(+)
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

-- 
2.1.4

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Re: [PATCH v3 2/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

On Mon, Jan 12, 2015 at 01:00:16AM +0100, Linus Walleij wrote:
> Hi Beniamino,
> 
> sorry for the delay to merging Sören's patches.
> 
> Can you rebase this patch on top of the pin control "devel" branch:
> https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

I will rebase and submit the patch in the next days.

Thanks,
Beniamino
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Re: [PATCH net-next] net: stmmac: add BQL support

[Beniamino Galvani]

On Mon, Dec 29, 2014 at 09:42:01AM -0800, Dave Taht wrote:
> On Sun, Dec 28, 2014 at 1:48 PM, Beniamino Galvani  
> wrote:
> > On Sun, Dec 28, 2014 at 08:25:40AM -0800, Dave Taht wrote:
> >> On Sun, Dec 28, 2014 at 6:57 AM, Beniamino Galvani  
> >> wrote:
> >> > Add support for Byte Queue Limits to the STMicro MAC driver.
> >>
> >> Thank you!
> >>
> >> > Tested on a Amlogic S805 Cortex-A5 board, where the use of BQL
> >> > slightly decreases the ping latency from ~10ms to ~3ms when the
> >> > 100Mbps link is saturated by TCP streams. No difference is
> >> > observed at 1Gbps.
> >>
> >> I see the plural. With TSQ in place it is hard (without something like
> >> the rrul test driving multiple streams) to drive a driver to
> >> saturation with small numbers of flows. This was with pfifo_fast, not
> >> sch_fq, at 100mbit?
> >
> > Hi Dave,
> >
> > yes, this was with pfifo_fast and I used 4 iperf TCP streams. The total
> > throughput didn't seem to increase adding more streams.
> 
> >>
> >> Can this board actually drive a full gigabit in the first place? Until
> >> now most of the low end arm boards I have seen only came with
> >> a 100mbit mac, and the gig ones lacking offloads seemed to peak
> >> out at about 600mbit.
> >
> > I measured a throughput of 650mbit in rx and 600mbit in tx.
> 
> You might want to try the rrul test which tests both directions and
> latency at the same time.

I will try it, thanks.

> 
> In my case I have been trying to find a low-cost chip that could do soft
> rate limiting (htb) + fq_codel at up to 300mbit/sec, as that is about
> the peak speed
> we will be getting from cable modems, and these are horribly overbuffered,
> at these speeds too, with 1.2sec of bidirectional latency observed at
> 120mbit/12mbit.
> 
> I'm open to crazy ideas like trying to find a use for the gpu, etc, to
> get there.
> 
> >
> >>
> >> Under my christmas tree landed a quad core A5 (odroid-c1), also an
> >> xgene and zedboard - both of the latter are a-needing BQL,
> >> and I haven't booted the udroid yet. Hopefully it is the
> >> same driver you just improved.
> >
> > I'm using the odroid-c1 too, with this tree based on the recent
> > Amlogic mainline work:
> >
> >   https://github.com/bengal/linux/tree/meson8b
> 
> Oh, cool, thx!
> 
> > Unfortunately at the moment the support for the board is very basic
> > (for example, SMP is not working yet) but it's enough to do some NIC
> > tests.
> 
> Good to know. Have you looked at xmit_more yet?
> 
> http://lwn.net/Articles/615238/

I don't know if I have implemented it correctly, but I found that the
improvement with xmit_more is so small to be barely observable, maybe
because the cost for starting the hardware transmission is very low
(it's a single mmio write).

Beniamino
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Re: [PATCH net-next] net: stmmac: add BQL support

[Beniamino Galvani]

On Sun, Dec 28, 2014 at 11:48:14PM -0800, Florian Fainelli wrote:
> 2014-12-28 6:57 GMT-08:00 Beniamino Galvani :
> > Add support for Byte Queue Limits to the STMicro MAC driver.
> >
> > Tested on a Amlogic S805 Cortex-A5 board, where the use of BQL
> > slightly decreases the ping latency from ~10ms to ~3ms when the
> > 100Mbps link is saturated by TCP streams. No difference is
> > observed at 1Gbps.
> >
> > Signed-off-by: Beniamino Galvani 
> > ---
> 
> [snip]
> 
> > priv->dev->stats.tx_errors++;
> > @@ -2049,6 +2057,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, 
> > struct net_device *dev)
> > skb_tx_timestamp(skb);
> >
> > priv->hw->dma->enable_dma_transmission(priv->ioaddr);
> > +   netdev_sent_queue(dev, skb->len);
> 
> You are introducing a potential use after free here in case tx_lock is
> eliminated one day and your TX reclaim logic kicks in and frees the
> freshly transmitted SKB, it would be safer to just cache skb->len in a
> local variable, and use it here.

Ok, I will change this part; probably a simpler solution is to call
netdev_sent_queue() before enabling the DMA like in other drivers.

BTW, I'm not sure this lock is really needed, since it should be
possible to safely access the ring without locks from both the
transmit and the reclaim functions if the pointers are updated
carefully. So maybe it will be really removed one day.

Beniamino

> 
> >
> > spin_unlock(&priv->tx_lock);
> > return NETDEV_TX_OK;

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Re: [PATCH net-next] net: stmmac: add BQL support

[Beniamino Galvani]

On Sun, Dec 28, 2014 at 08:25:40AM -0800, Dave Taht wrote:
> On Sun, Dec 28, 2014 at 6:57 AM, Beniamino Galvani  
> wrote:
> > Add support for Byte Queue Limits to the STMicro MAC driver.
> 
> Thank you!
> 
> > Tested on a Amlogic S805 Cortex-A5 board, where the use of BQL
> > slightly decreases the ping latency from ~10ms to ~3ms when the
> > 100Mbps link is saturated by TCP streams. No difference is
> > observed at 1Gbps.
> 
> I see the plural. With TSQ in place it is hard (without something like
> the rrul test driving multiple streams) to drive a driver to
> saturation with small numbers of flows. This was with pfifo_fast, not
> sch_fq, at 100mbit?

Hi Dave,

yes, this was with pfifo_fast and I used 4 iperf TCP streams. The total
throughput didn't seem to increase adding more streams.

> 
> Can this board actually drive a full gigabit in the first place? Until
> now most of the low end arm boards I have seen only came with
> a 100mbit mac, and the gig ones lacking offloads seemed to peak
> out at about 600mbit.

I measured a throughput of 650mbit in rx and 600mbit in tx.

> 
> Under my christmas tree landed a quad core A5 (odroid-c1), also an
> xgene and zedboard - both of the latter are a-needing BQL,
> and I haven't booted the udroid yet. Hopefully it is the
> same driver you just improved.

I'm using the odroid-c1 too, with this tree based on the recent
Amlogic mainline work:

  https://github.com/bengal/linux/tree/meson8b

Unfortunately at the moment the support for the board is very basic
(for example, SMP is not working yet) but it's enough to do some NIC
tests.

Beniamino
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[PATCH net-next] net: stmmac: add BQL support

[Beniamino Galvani]

Add support for Byte Queue Limits to the STMicro MAC driver.

Tested on a Amlogic S805 Cortex-A5 board, where the use of BQL
slightly decreases the ping latency from ~10ms to ~3ms when the
100Mbps link is saturated by TCP streams. No difference is
observed at 1Gbps.

Signed-off-by: Beniamino Galvani 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 118a427..c5af3d8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1097,6 +1097,7 @@ static int init_dma_desc_rings(struct net_device *dev, 
gfp_t flags)
 
priv->dirty_tx = 0;
priv->cur_tx = 0;
+   netdev_reset_queue(priv->dev);
 
stmmac_clear_descriptors(priv);
 
@@ -1300,6 +1301,7 @@ static void stmmac_dma_operation_mode(struct stmmac_priv 
*priv)
 static void stmmac_tx_clean(struct stmmac_priv *priv)
 {
unsigned int txsize = priv->dma_tx_size;
+   unsigned int bytes_compl = 0, pkts_compl = 0;
 
spin_lock(&priv->tx_lock);
 
@@ -1356,6 +1358,8 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
priv->hw->mode->clean_desc3(priv, p);
 
if (likely(skb != NULL)) {
+   pkts_compl++;
+   bytes_compl += skb->len;
dev_consume_skb_any(skb);
priv->tx_skbuff[entry] = NULL;
}
@@ -1364,6 +1368,9 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
 
priv->dirty_tx++;
}
+
+   netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
+
if (unlikely(netif_queue_stopped(priv->dev) &&
 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
netif_tx_lock(priv->dev);
@@ -1418,6 +1425,7 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
 (i == txsize - 1));
priv->dirty_tx = 0;
priv->cur_tx = 0;
+   netdev_reset_queue(priv->dev);
priv->hw->dma->start_tx(priv->ioaddr);
 
priv->dev->stats.tx_errors++;
@@ -2049,6 +2057,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, 
struct net_device *dev)
skb_tx_timestamp(skb);
 
priv->hw->dma->enable_dma_transmission(priv->ioaddr);
+   netdev_sent_queue(dev, skb->len);
 
spin_unlock(&priv->tx_lock);
return NETDEV_TX_OK;
-- 
2.1.4

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Re: [PATCH v2] irqchip: mediatek: Use IS_ERR() instead of NULL pointer check

[Beniamino Galvani]

On Wed, Dec 10, 2014 at 07:53:13AM -0500, Jason Cooper wrote:
> On Wed, Dec 10, 2014 at 01:14:43PM +0100, Beniamino Galvani wrote:
> > On Wed, Dec 10, 2014 at 05:55:02PM +0800, Yingjoe Chen wrote:
> > > Beniamino reported a kernel oops caused by an invalid DT file for the
> > > mediatek interrupt polarity extension.
> > > 
> > > The reason is that the interrupt polarity support for mediatek chips
> > > merely checks for NULL pointer instead of a casted error return
> > > value in mtk_sysirq_of_init() so any other casted error value passes
> > > the NULL pointer check and causes a kernel panic when dereferenced.
> > > 
> > > Use IS_ERR() and return the error value via PTR_ERR().
> > > 
> > > Reported-and-tested-by: Beniamino Galvani 
> > 
> > Well, actually I only reported the bug and didn't do any test. Can the
> > "-and-tested" portion of the tag be dropped while applying the patch?
> 
> I'd prefer that it be tested before applying.  Would you mind confirming
> that the oops is gone with this patch applied?

Probably the commit message is misleading about this, but I don't own
any Mediatek device and never used the driver. I only reported [1] a
possible bug in the driver found through code analysis.

Anyway, I suppose that the tests done by Yingjoe are enough to get the
patch merged.

Beniamino

[1] https://lkml.org/lkml/2014/11/29/105
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Re: [PATCH v2] irqchip: mediatek: Use IS_ERR() instead of NULL pointer check

[Beniamino Galvani]

On Wed, Dec 10, 2014 at 05:55:02PM +0800, Yingjoe Chen wrote:
> Beniamino reported a kernel oops caused by an invalid DT file for the
> mediatek interrupt polarity extension.
> 
> The reason is that the interrupt polarity support for mediatek chips
> merely checks for NULL pointer instead of a casted error return
> value in mtk_sysirq_of_init() so any other casted error value passes
> the NULL pointer check and causes a kernel panic when dereferenced.
> 
> Use IS_ERR() and return the error value via PTR_ERR().
> 
> Reported-and-tested-by: Beniamino Galvani 

Well, actually I only reported the bug and didn't do any test. Can the
"-and-tested" portion of the tag be dropped while applying the patch?

Beniamino

> Signed-off-by: Yingjoe Chen 
> ---
>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-mtk-sysirq.c 
> b/drivers/irqchip/irq-mtk-sysirq.c
> index 7e342df..0b0d2c0 100644
> --- a/drivers/irqchip/irq-mtk-sysirq.c
> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> @@ -137,9 +137,9 @@ static int __init mtk_sysirq_of_init(struct device_node 
> *node,
>   return -ENOMEM;
>  
>   chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
> - if (!chip_data->intpol_base) {
> + if (IS_ERR(chip_data->intpol_base)) {
>   pr_err("mtk_sysirq: unable to map sysirq register\n");
> - ret = -ENOMEM;
> + ret = PTR_ERR(chip_data->intpol_base);
>   goto out_free;
>   }
>  
> -- 
> 1.8.1.1.dirty
> 
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Re: [PATCH v8 2/4] ARM: mediatek: Add sysirq interrupt polarity support

[Beniamino Galvani]

On Tue, Nov 25, 2014 at 04:04:20PM +0800, Yingjoe Chen wrote:
> Mediatek SoCs have interrupt polarity support in sysirq which
> allows to invert polarity for given interrupt. Add this support
> using hierarchy irq domain.
>
> [...]
> 
> +static int __init mtk_sysirq_of_init(struct device_node *node,
> +  struct device_node *parent)
> +{
> + struct irq_domain *domain, *domain_parent;
> + struct mtk_sysirq_chip_data *chip_data;
> + int ret = 0;
> +
> + domain_parent = irq_find_host(parent);
> + if (!domain_parent) {
> + pr_err("mtk_sysirq: interrupt-parent not found\n");
> + return -EINVAL;
> + }
> +
> + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> + if (!chip_data)
> + return -ENOMEM;
> +
> + chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
> + if (!chip_data->intpol_base) {

Hi,

you should use IS_ERR() to check the return value here.

Beniamino
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Re: [PATCH v3 2/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

On Thu, Nov 27, 2014 at 02:48:31PM +0100, Linus Walleij wrote:
> On Sun, Nov 16, 2014 at 9:14 PM, Beniamino Galvani  
> wrote:
> 
> > This is a driver for the pinmux and GPIO controller available in
> > Amlogic Meson SoCs. At the moment it only supports Meson8 devices,
> > however other SoC families like Meson6 and Meson8b (the Cortex-A5
> > variant) appear to be similar, with just different sets of banks and
> > registers.
> >
> > GPIO interrupts are not supported at the moment due to lack of
> > documentation.
> >
> > Signed-off-by: Beniamino Galvani 
> 
> This is dependent on Sören's patches I guess?
> 
> OK I'll merge this once we have that other code sorted out.

Yes, this depends on Soren's patches.

Thanks,
Beniamino
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Re: randconfig build error with next-20141126, in drivers/spi/spi-meson-spifc.c

[Beniamino Galvani]

On Wed, Nov 26, 2014 at 10:53:28AM -0700, Jim Davis wrote:
> Building with the attached random configuration file,
> 
> drivers/built-in.o: In function `meson_spifc_probe':
> spi-meson-spifc.c:(.text+0x14b4a8): undefined reference to
> `devm_regmap_init_mmio_clk'
> make: *** [vmlinux] Error 1

Hi,

I've just submitted a fix for the missing Kconfig dependency.

Thanks,
Beniamino
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[PATCH] ARM: dts: meson: enable Ethernet controller

[Beniamino Galvani]

Add a node for the Ethernet controller to Meson DTS file and
enable it on the Geniatech ATV1200 board.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi | 11 +++
 arch/arm/boot/dts/meson6-atv1200.dts |  4 
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 03bcff8..4704b95 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -143,5 +143,16 @@
#size-cells = <0>;
status = "disabled";
};
+
+   ethmac: ethernet@c941 {
+   compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+   reg = <0xc941 0x1
+  0xc1108108 0x4>;
+   interrupts = <0 8 1>;
+   interrupt-names = "macirq";
+   clocks = <&clk81>;
+   clock-names = "stmmaceth";
+   status = "disabled";
+   };
};
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts 
b/arch/arm/boot/dts/meson6-atv1200.dts
index d7d351a..1237faa 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -64,3 +64,7 @@
 &uart_AO {
status = "okay";
 };
+
+ðmac {
+   status = "okay";
+};
-- 
1.9.1

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[PATCH v3 1/4] spi: core: Add spi_transfer_is_last() helper

[Beniamino Galvani]

This adds the function spi_transfer_is_last() which can be used by
drivers to know whether a given transfer is the last one in the
current message.

Signed-off-by: Beniamino Galvani 
---
 include/linux/spi/spi.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 46d188a..a6ef2a8 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -1049,4 +1049,10 @@ spi_unregister_device(struct spi_device *spi)
 extern const struct spi_device_id *
 spi_get_device_id(const struct spi_device *sdev);
 
+static inline bool
+spi_transfer_is_last(struct spi_master *master, struct spi_transfer *xfer)
+{
+   return list_is_last(&xfer->transfer_list, &master->cur_msg->transfers);
+}
+
 #endif /* __LINUX_SPI_H */
-- 
1.9.1

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[PATCH v3 3/4] spi: meson: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.

The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, toggling a bit in a
dedicated register. The driver doesn't use those predefined commands
and relies only on custom transfers.

Signed-off-by: Beniamino Galvani 
---
 drivers/spi/Kconfig   |   7 +
 drivers/spi/Makefile  |   1 +
 drivers/spi/spi-meson-spifc.c | 462 ++
 3 files changed, 470 insertions(+)
 create mode 100644 drivers/spi/spi-meson-spifc.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 98de207..0373c37 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -308,6 +308,13 @@ config SPI_FSL_ESPI
  From MPC8536, 85xx platform uses the controller, and all P10xx,
  P20xx, P30xx,P40xx, P50xx uses this controller.
 
+config SPI_MESON_SPIFC
+   tristate "Amlogic Meson SPIFC controller"
+   depends on ARCH_MESON || COMPILE_TEST
+   help
+ This enables master mode support for the SPIFC (SPI flash
+ controller) available in Amlogic Meson SoCs.
+
 config SPI_OC_TINY
tristate "OpenCores tiny SPI"
depends on GPIOLIB
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 37dc2e7..6b9d2ac 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_GPIO)+= spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
+obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)  += spi-mpc52xx.o
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
new file mode 100644
index 000..f536476
--- /dev/null
+++ b/drivers/spi/spi-meson-spifc.c
@@ -0,0 +1,462 @@
+/*
+ * Driver for Amlogic Meson SPI flash controller (SPIFC)
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register map */
+#define REG_CMD0x00
+#define REG_ADDR   0x04
+#define REG_CTRL   0x08
+#define REG_CTRL1  0x0c
+#define REG_STATUS 0x10
+#define REG_CTRL2  0x14
+#define REG_CLOCK  0x18
+#define REG_USER   0x1c
+#define REG_USER1  0x20
+#define REG_USER2  0x24
+#define REG_USER3  0x28
+#define REG_USER4  0x2c
+#define REG_SLAVE  0x30
+#define REG_SLAVE1 0x34
+#define REG_SLAVE2 0x38
+#define REG_SLAVE3 0x3c
+#define REG_C0 0x40
+#define REG_B8 0x60
+#define REG_MAX0x7c
+
+/* register fields */
+#define CMD_USER   BIT(18)
+#define CTRL_ENABLE_AHBBIT(17)
+#define CLOCK_SOURCE   BIT(31)
+#define CLOCK_DIV_SHIFT12
+#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
+#define CLOCK_CNT_HIGH_SHIFT   6
+#define CLOCK_CNT_HIGH_MASK(0x3f << CLOCK_CNT_HIGH_SHIFT)
+#define CLOCK_CNT_LOW_SHIFT0
+#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
+#define USER_DIN_EN_MS BIT(0)
+#define USER_CMP_MODE  BIT(2)
+#define USER_UC_DOUT_SEL   BIT(27)
+#define USER_UC_DIN_SELBIT(28)
+#define USER_UC_MASK   ((BIT(5) - 1) << 27)
+#define USER1_BN_UC_DOUT_SHIFT 17
+#define USER1_BN_UC_DOUT_MASK  (0xff << 16)
+#define USER1_BN_UC_DIN_SHIFT  8
+#define USER1_BN_UC_DIN_MASK   (0xff << 8)
+#define USER4_CS_ACT   BIT(30)
+#define SLAVE_TRST_DONEBIT(4)
+#define SLAVE_OP_MODE  BIT(30)
+#define SLAVE_SW_RST   BIT(31)
+
+#define SPIFC_BUFFER_SIZE  64
+
+/**
+ * struct meson_spifc
+ * @master:the SPI master
+ * @regmap:regmap for device registers
+ * @clk:   input clock of the built-in baud rate generator
+ * @device:the device structure
+ */
+struct meson_spifc {
+   struct spi_master *master;
+   struct regmap *regmap;
+

[PATCH v3 4/4] ARM: dts: meson: add node for SPIFC

[Beniamino Galvani]

This adds a node for the SPI Flash Controller to the Amlogic Meson
DTS.

Signed-off-by: Beniamino Galvani 
Acked-by: Mark Brown 
---
 arch/arm/boot/dts/meson.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index b91e430..e26d37a 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -135,5 +135,14 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   spifc: spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <&clk81>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH v3 2/4] spi: meson: Add device tree bindings documentation for SPIFC

[Beniamino Galvani]

This adds documentation of device tree bindings for the Amlogic Meson
SPIFC (SPI Flash Controller).

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/spi/spi-meson.txt  | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt 
b/Documentation/devicetree/bindings/spi/spi-meson.txt
new file mode 100644
index 000..bb52a86
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-meson.txt
@@ -0,0 +1,22 @@
+Amlogic Meson SPI controllers
+
+* SPIFC (SPI Flash Controller)
+
+The Meson SPIFC is a controller optimized for communication with SPI
+NOR memories, without DMA support and a 64-byte unified transmit /
+receive buffer.
+
+Required properties:
+ - compatible: should be "amlogic,meson6-spifc"
+ - reg: physical base address and length of the controller registers
+ - clocks: phandle of the input clock for the baud rate generator
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+   spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
-- 
1.9.1

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[PATCH v3 0/4] spi: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

Hi,

this patchset adds a driver for the SPIFC (SPI flash controller)
available in Amlogic Meson6 and Meson8 SoCs. The driver has been
tested on a Meson8 based device to communicate with a Macronix
mx25l1606e serial flash.

Changes since v2 [ https://lkml.org/lkml/2014/11/17/669 ]:
 - introduce spi_transfer_is_last() helper instead of using a flag
   in spi_transfer structure
 - rebase DTS patch on arm-soc

Changes since v1 [ https://lkml.org/lkml/2014/11/9/35 ]:
 - decrease busy wait timeout
 - remove check on xfer->speed_hz value in meson_spifc_transfer_one()
 - implement transfer_one() instead of transfer_one_message()
 - remove useless memset of devdata
 - use fixed regmap config
 - implement PM operations
 - don't set master->bus_num
 - allow modular build of the driver

Beniamino Galvani (4):
  spi: core: Add spi_transfer_is_last() helper
  spi: meson: Add device tree bindings documentation for SPIFC
  spi: meson: Add support for Amlogic Meson SPIFC
  ARM: dts: meson: add node for SPIFC

 .../devicetree/bindings/spi/spi-meson.txt  |  22 +
 arch/arm/boot/dts/meson.dtsi   |   9 +
 drivers/spi/Kconfig|   7 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-meson-spifc.c  | 462 +
 include/linux/spi/spi.h|   6 +
 6 files changed, 507 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
 create mode 100644 drivers/spi/spi-meson-spifc.c

-- 
1.9.1

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Re: [PATCH v2 1/4] spi: Add 'last' flag to spi_transfer structure

[Beniamino Galvani]

On Tue, Nov 18, 2014 at 02:06:58PM +, Mark Brown wrote:
> It's incredibly sad to iterate through the entire list in order to find
> the last entry, especially given that it's a doubly linked list and this
> is a bit of a hot path.  We should look at the previous entry for the
> list head instead, or perhaps better yet by doing this as part of
> spi_validate() which already itereates over the entire list and is where
> we do other similar fixups.
> 
> Though looking at this I'm not sure that a flag is the best approach at
> all - why not just have the driver call list_is_last() in the transfer
> function or ideally provide an inline function that does that so that we
> can change the implementation later?

I didn't realize that the master structure passed to transfer_one()
has a reference to the current message and thus to the transfer
list. Then yes, the additional flag in the transfer structure probably
doesn't make much sense.

Would it be better to introduce something like:

static inline bool
spi_transfer_is_last(struct spi_master *master, struct spi_transfer *xfer)
{
return list_is_last(&xfer->transfer_list, &master->cur_msg->transfers);
}

or open code it in the driver?

Beniamino
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Re: [PATCH v3 3/3] ARM: dts: meson: add I2C controller nodes

[Beniamino Galvani]

On Tue, Nov 18, 2014 at 04:29:13PM +0100, Carlo Caione wrote:
> On Tue, Nov 18, 2014 at 4:19 PM, Wolfram Sang  wrote:
> > On Thu, Nov 13, 2014 at 08:32:03PM +0100, Beniamino Galvani wrote:
> >> Add nodes for I2C controllers A,B,AO, which are available in both
> >> Meson6 and Meson8.
> >>
> >> Signed-off-by: Beniamino Galvani 
> >> ---
> >
> > I usually don't take DTS patches. They should go via arm-soc. Please say
> > so if there are reasons I should take it.
> 
> I'll take them.

Thanks!

Beniamino
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[PATCH v3 1/3] media: rc: meson: document device tree bindings

[Beniamino Galvani]

This adds binding documentation for the infrared remote control
receiver available in Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/media/meson-ir.txt | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt

diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt 
b/Documentation/devicetree/bindings/media/meson-ir.txt
new file mode 100644
index 000..407848e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/meson-ir.txt
@@ -0,0 +1,14 @@
+* Amlogic Meson IR remote control receiver
+
+Required properties:
+ - compatible  : should be "amlogic,meson6-ir"
+ - reg : physical base address and length of the device registers
+ - interrupts  : a single specifier for the interrupt from the device
+
+Example:
+
+   ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   };
-- 
1.9.1

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[PATCH v3 2/3] media: rc: add driver for Amlogic Meson IR remote receiver

[Beniamino Galvani]

Amlogic Meson SoCs include a infrared remote control receiver that can
operate in two modes: "NEC" mode in which the hardware decodes frames
using the NEC IR protocol, and "general" mode in which the receiver
simply reports the duration of pulses and spaces for software
decoding.

This is a driver for the IR receiver that implements software decoding
of received frames.

Signed-off-by: Beniamino Galvani 
---
 MAINTAINERS |   1 +
 drivers/media/rc/Kconfig|  11 +++
 drivers/media/rc/Makefile   |   1 +
 drivers/media/rc/meson-ir.c | 216 
 4 files changed, 229 insertions(+)
 create mode 100644 drivers/media/rc/meson-ir.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 0662378..f1bc045 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ ARM/Amlogic MesonX SoC support
 M: Carlo Caione 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
+F: drivers/media/rc/meson-ir.c
 N: meson[x68]
 
 ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 1aea732..ddfab25 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -223,6 +223,17 @@ config IR_FINTEK
   To compile this driver as a module, choose M here: the
   module will be called fintek-cir.
 
+config IR_MESON
+   tristate "Amlogic Meson IR remote receiver"
+   depends on RC_CORE
+   depends on ARCH_MESON || COMPILE_TEST
+   ---help---
+  Say Y if you want to use the IR remote receiver available
+  on Amlogic Meson SoCs.
+
+  To compile this driver as a module, choose M here: the
+  module will be called meson-ir.
+
 config IR_NUVOTON
tristate "Nuvoton w836x7hg Consumer Infrared Transceiver"
depends on PNP
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 8f509e0..379a5c0 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_IR_IMON) += imon.o
 obj-$(CONFIG_IR_ITE_CIR) += ite-cir.o
 obj-$(CONFIG_IR_MCEUSB) += mceusb.o
 obj-$(CONFIG_IR_FINTEK) += fintek-cir.o
+obj-$(CONFIG_IR_MESON) += meson-ir.o
 obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
 obj-$(CONFIG_IR_ENE) += ene_ir.o
 obj-$(CONFIG_IR_REDRAT3) += redrat3.o
diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
new file mode 100644
index 000..fcc3b82
--- /dev/null
+++ b/drivers/media/rc/meson-ir.c
@@ -0,0 +1,216 @@
+/*
+ * Driver for Amlogic Meson IR remote receiver
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define DRIVER_NAME"meson-ir"
+
+#define IR_DEC_LDR_ACTIVE  0x00
+#define IR_DEC_LDR_IDLE0x04
+#define IR_DEC_LDR_REPEAT  0x08
+#define IR_DEC_BIT_0   0x0c
+#define IR_DEC_REG00x10
+#define IR_DEC_FRAME   0x14
+#define IR_DEC_STATUS  0x18
+#define IR_DEC_REG10x1c
+
+#define REG0_RATE_MASK (BIT(11) - 1)
+
+#define REG1_MODE_MASK (BIT(7) | BIT(8))
+#define REG1_MODE_NEC  (0 << 7)
+#define REG1_MODE_GENERAL  (2 << 7)
+
+#define REG1_TIME_IV_SHIFT 16
+#define REG1_TIME_IV_MASK  ((BIT(13) - 1) << REG1_TIME_IV_SHIFT)
+
+#define REG1_IRQSEL_MASK   (BIT(2) | BIT(3))
+#define REG1_IRQSEL_NEC_MODE   (0 << 2)
+#define REG1_IRQSEL_RISE_FALL  (1 << 2)
+#define REG1_IRQSEL_FALL   (2 << 2)
+#define REG1_IRQSEL_RISE   (3 << 2)
+
+#define REG1_RESET BIT(0)
+#define REG1_ENABLEBIT(15)
+
+#define STATUS_IR_DEC_IN   BIT(8)
+
+#define MESON_TRATE10  /* us */
+
+struct meson_ir {
+   void __iomem*reg;
+   struct rc_dev   *rc;
+   int irq;
+   spinlock_t  lock;
+};
+
+static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
+ u32 mask, u32 value)
+{
+   u32 data;
+
+   data = readl(ir->reg + reg);
+   data &= ~mask;
+   data |= (value & mask);
+   writel(data, ir->reg + reg);
+}
+
+static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
+{
+   struct meson_ir *ir = dev_id;
+   u32 duration;
+   DEFINE_IR_RAW_EVENT(rawir);
+
+   spin_lock(&ir->lock);
+
+   duration = readl(ir->reg + IR_DEC_REG1);
+   duration = (duration & REG1_TIME_IV_MASK) >> REG1_TIME_IV_SHIFT;
+  

[PATCH v3 3/3] ARM: dts: meson: add IR receiver node

[Beniamino Galvani]

This adds a node for the IR remote control receiver to the Amlogic
Meson DTS.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..6a37f15 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -106,5 +106,12 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   ir_receiver: ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH v3 0/3] media: rc: add support for Amlogic Meson IR receiver

[Beniamino Galvani]

Hi,

this is a driver for the infrared receiver available in Amlogic Meson6
and Meson8 SoCs. The device can operate in two modes: "NEC" mode in
which the hardware decodes frames using the NEC IR protocol, and
"general" mode in which the receiver simply reports the duration of
pulses and spaces for software decoding.

In order to have the maximum compatibility with different protocols
the driver implements software decoding.

Changes since v2 [ https://lkml.org/lkml/2014/10/12/149 ]:
 - avoid calling rc_free_device() twice in probe error path

Changes since v1 [ https://lkml.org/lkml/2014/11/9/20 ]:
 - added COMPILE_TEST to allow compilation for other architectures
 - added missing header files
 - removed bogus vendor, product and version assignments
 - added file path to Meson entry in MAINTAINERS
 - reordered patches

Beniamino Galvani (3):
  media: rc: meson: document device tree bindings
  media: rc: add driver for Amlogic Meson IR remote receiver
  ARM: dts: meson: add IR receiver node

 .../devicetree/bindings/media/meson-ir.txt |  14 ++
 MAINTAINERS|   1 +
 arch/arm/boot/dts/meson.dtsi   |   7 +
 drivers/media/rc/Kconfig   |  11 ++
 drivers/media/rc/Makefile  |   1 +
 drivers/media/rc/meson-ir.c| 216 +
 6 files changed, 250 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt
 create mode 100644 drivers/media/rc/meson-ir.c

-- 
1.9.1

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[PATCH v2 0/4] spi: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

Hi,

this patchset adds a driver for the SPIFC (SPI flash controller)
available in Amlogic Meson6 and Meson8 SoCs. The driver has been
tested on a Meson8 based device to communicate with a Macronix
mx25l1606e serial flash.

The first patch adds a field to the spi_transfer structure that allows
the driver to know in transfer_one() whether the transfer is the last
one and change CS accordingly, without the need to reimplement
transfer_one_message().

Changes since v1 [ https://lkml.org/lkml/2014/11/9/35 ]:
 - decrease busy wait timeout
 - remove check on xfer->speed_hz value in meson_spifc_transfer_one()
 - implement transfer_one() instead of transfer_one_message()
 - remove useless memset of devdata
 - use fixed regmap config
 - implement PM operations
 - don't set master->bus_num
 - allow modular build of the driver

Beniamino Galvani (4):
  spi: Add 'last' flag to spi_transfer structure
  spi: meson: Add device tree bindings documentation for SPIFC
  spi: meson: Add support for Amlogic Meson SPIFC
  ARM: dts: meson: add node for SPIFC

 .../devicetree/bindings/spi/spi-meson.txt  |  22 +
 arch/arm/boot/dts/meson.dtsi   |   9 +
 drivers/spi/Kconfig|   7 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-meson-spifc.c  | 461 +
 drivers/spi/spi.c  |   6 +
 include/linux/spi/spi.h|   2 +
 7 files changed, 508 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
 create mode 100644 drivers/spi/spi-meson-spifc.c

-- 
1.9.1

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[PATCH v2 1/4] spi: Add 'last' flag to spi_transfer structure

[Beniamino Galvani]

Some drivers need to know whether the current transfer is the last in
the message in order to properly handle CS. A common way to achieve
this is to reimplement transfer_one_message() but this leads to
undesirable code duplication.

This patch adds a 'last' field to the spi_transfer structure and
populates it before passing the structure to the driver.

Signed-off-by: Beniamino Galvani 
---
 drivers/spi/spi.c   | 6 ++
 include/linux/spi/spi.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ebcb33d..fc7f02d 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -887,6 +887,7 @@ static void spi_pump_messages(struct kthread_work *work)
 {
struct spi_master *master =
container_of(work, struct spi_master, pump_messages);
+   struct spi_transfer *xfer;
unsigned long flags;
bool was_busy = false;
int ret;
@@ -941,6 +942,11 @@ static void spi_pump_messages(struct kthread_work *work)
}
}
 
+   list_for_each_entry(xfer, &master->cur_msg->transfers, transfer_list) {
+   xfer->last = list_is_last(&xfer->transfer_list,
+ &master->cur_msg->transfers);
+   }
+
if (!was_busy)
trace_spi_master_busy(master);
 
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 46d188a..37f055a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -535,6 +535,7 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
  *  (SPI_NBITS_SINGLE) is used.
  * @rx_nbits: number of bits used for reading. If 0 the default
  *  (SPI_NBITS_SINGLE) is used.
+ * @last: whether the transfer is the last in the message.
  * @len: size of rx and tx buffers (in bytes)
  * @speed_hz: Select a speed other than the device default for this
  *  transfer. If 0 the default (from @spi_device) is used.
@@ -620,6 +621,7 @@ struct spi_transfer {
unsignedcs_change:1;
unsignedtx_nbits:3;
unsignedrx_nbits:3;
+   unsignedlast:1;
 #defineSPI_NBITS_SINGLE0x01 /* 1bit transfer */
 #defineSPI_NBITS_DUAL  0x02 /* 2bits transfer */
 #defineSPI_NBITS_QUAD  0x04 /* 4bits transfer */
-- 
1.9.1

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[PATCH v2 3/4] spi: meson: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.

The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, toggling a bit in a
dedicated register. The driver doesn't use those predefined commands
and relies only on custom transfers.

Signed-off-by: Beniamino Galvani 
---
 drivers/spi/Kconfig   |   7 +
 drivers/spi/Makefile  |   1 +
 drivers/spi/spi-meson-spifc.c | 461 ++
 3 files changed, 469 insertions(+)
 create mode 100644 drivers/spi/spi-meson-spifc.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 84e7c9e..70f20b9 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -301,6 +301,13 @@ config SPI_FSL_ESPI
  From MPC8536, 85xx platform uses the controller, and all P10xx,
  P20xx, P30xx,P40xx, P50xx uses this controller.
 
+config SPI_MESON_SPIFC
+   tristate "Amlogic Meson SPIFC controller"
+   depends on ARCH_MESON || COMPILE_TEST
+   help
+ This enables master mode support for the SPIFC (SPI flash
+ controller) available in Amlogic Meson SoCs.
+
 config SPI_OC_TINY
tristate "OpenCores tiny SPI"
depends on GPIOLIB
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 78f24ca..9b8a747 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
+obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)  += spi-mpc52xx.o
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
new file mode 100644
index 000..68be0e0
--- /dev/null
+++ b/drivers/spi/spi-meson-spifc.c
@@ -0,0 +1,461 @@
+/*
+ * Driver for Amlogic Meson SPI flash controller (SPIFC)
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register map */
+#define REG_CMD0x00
+#define REG_ADDR   0x04
+#define REG_CTRL   0x08
+#define REG_CTRL1  0x0c
+#define REG_STATUS 0x10
+#define REG_CTRL2  0x14
+#define REG_CLOCK  0x18
+#define REG_USER   0x1c
+#define REG_USER1  0x20
+#define REG_USER2  0x24
+#define REG_USER3  0x28
+#define REG_USER4  0x2c
+#define REG_SLAVE  0x30
+#define REG_SLAVE1 0x34
+#define REG_SLAVE2 0x38
+#define REG_SLAVE3 0x3c
+#define REG_C0 0x40
+#define REG_B8 0x60
+#define REG_MAX0x7c
+
+/* register fields */
+#define CMD_USER   BIT(18)
+#define CTRL_ENABLE_AHBBIT(17)
+#define CLOCK_SOURCE   BIT(31)
+#define CLOCK_DIV_SHIFT12
+#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
+#define CLOCK_CNT_HIGH_SHIFT   6
+#define CLOCK_CNT_HIGH_MASK(0x3f << CLOCK_CNT_HIGH_SHIFT)
+#define CLOCK_CNT_LOW_SHIFT0
+#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
+#define USER_DIN_EN_MS BIT(0)
+#define USER_CMP_MODE  BIT(2)
+#define USER_UC_DOUT_SEL   BIT(27)
+#define USER_UC_DIN_SELBIT(28)
+#define USER_UC_MASK   ((BIT(5) - 1) << 27)
+#define USER1_BN_UC_DOUT_SHIFT 17
+#define USER1_BN_UC_DOUT_MASK  (0xff << 16)
+#define USER1_BN_UC_DIN_SHIFT  8
+#define USER1_BN_UC_DIN_MASK   (0xff << 8)
+#define USER4_CS_ACT   BIT(30)
+#define SLAVE_TRST_DONEBIT(4)
+#define SLAVE_OP_MODE  BIT(30)
+#define SLAVE_SW_RST   BIT(31)
+
+#define SPIFC_BUFFER_SIZE  64
+
+/**
+ * struct meson_spifc
+ * @master:the SPI master
+ * @regmap:regmap for device registers
+ * @clk:   input clock of the built-in baud rate generator
+ * @device:the device structure
+ */
+struct meson_spifc {
+   struct spi_master *master;
+   struct regmap *regmap;
+   struct 

[PATCH v2 2/4] spi: meson: Add device tree bindings documentation for SPIFC

[Beniamino Galvani]

This adds documentation of device tree bindings for the Amlogic Meson
SPIFC (SPI Flash Controller).

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/spi/spi-meson.txt  | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt 
b/Documentation/devicetree/bindings/spi/spi-meson.txt
new file mode 100644
index 000..bb52a86
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-meson.txt
@@ -0,0 +1,22 @@
+Amlogic Meson SPI controllers
+
+* SPIFC (SPI Flash Controller)
+
+The Meson SPIFC is a controller optimized for communication with SPI
+NOR memories, without DMA support and a 64-byte unified transmit /
+receive buffer.
+
+Required properties:
+ - compatible: should be "amlogic,meson6-spifc"
+ - reg: physical base address and length of the controller registers
+ - clocks: phandle of the input clock for the baud rate generator
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+   spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
-- 
1.9.1

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[PATCH v2 4/4] ARM: dts: meson: add node for SPIFC

[Beniamino Galvani]

This adds a node for the SPI Flash Controller to the Amlogic Meson
DTS.

Signed-off-by: Beniamino Galvani 
Acked-by: Mark Brown 
---
 arch/arm/boot/dts/meson.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..d28b16e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -106,5 +106,14 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   spifc: spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <&clk81>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH v3 2/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. At the moment it only supports Meson8 devices,
however other SoC families like Meson6 and Meson8b (the Cortex-A5
variant) appear to be similar, with just different sets of banks and
registers.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani 
---
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/meson/Makefile |2 +
 drivers/pinctrl/meson/pinctrl-meson.c  |  761 ++
 drivers/pinctrl/meson/pinctrl-meson.h  |  209 ++
 drivers/pinctrl/meson/pinctrl-meson8.c | 1087 
 include/dt-bindings/gpio/meson8-gpio.h |  157 +
 7 files changed, 2225 insertions(+)
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d014f22..586227f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
 
+config PINCTRL_MESON
+   bool
+   select PINMUX
+   select PINCONF
+   select GENERIC_PINCONF
+   select OF_GPIO
+   select REGMAP_MMIO
+
 config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c030b3d..61486b2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91)+= pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_BCM2835)  += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_FALCON)   += pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_MESON)+= meson/
 obj-$(CONFIG_PINCTRL_PALMAS)   += pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000..eafc216
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
+obj-y  += pinctrl-meson8.o
+obj-y  += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c 
b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000..81f643e
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,761 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
+ * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
+ * each bank has a variable number of pins.
+ *
+ * The AO bank is special because it belongs to the Always-On power
+ * domain which can't be powered off; the bank also uses a set of
+ * registers different from the other banks.
+ *
+ * For each of the two power domains (regular and always-on) there are
+ * 4 different register ranges that control the following properties
+ * of the pins:
+ *  1) pin muxing
+ *  2) pull enable/disable
+ *  3) pull up/down
+ *  4) GPIO direction, output value, input value
+ *
+ * In some cases the register ranges for pull enable and pull
+ * direction are the same and thus there are only 3 register ranges.
+ *
+ * Every pinmux group can be enabled by a specific bit in the first
+ * register range of the domain; when all groups for a given pin are
+ * disabled the pin acts as a GPIO.
+ *
+ * For the pull and GPIO configuration every bank uses a contiguous
+ * set of bits in the register sets described above; the same register
+ * can be shared by more banks with different offsets.
+ *
+ * In addition to this there are some registers shared between all
+ * banks that control the IRQ functionality. This feature is not
+ * supported at the moment by the driver.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-meson.h"
+
+/**
+ * meson_get_bank() - find the bank containing a given pin
+ *
+ * @domain:the domain containing the pin
+ * @pin:   the pin number
+ * @bank:  the found bank
+ *
+ * Return: 0 on success, a negative value on error
+ */
+static int m

[PATCH v3 3/3] ARM: meson: select PINCTRL_MESON and ARCH_REQUIRE_GPIOLIB

[Beniamino Galvani]

Make sure that the Meson pinctrl driver is built whenever Meson
support is enabled.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/mach-meson/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 2c1154e..1828711 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -1,7 +1,10 @@
 menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
+   select ARCH_REQUIRE_GPIOLIB
select GENERIC_IRQ_CHIP
select ARM_GIC
+   select PINCTRL
+   select PINCTRL_MESON
 
 if ARCH_MESON
 
-- 
1.9.1

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[PATCH v3 0/3] Amlogic Meson pinctrl driver

[Beniamino Galvani]

Hi,

this is the third version of the pinctrl driver for Amlogic Meson. It
provides a common infrastructure than can be used by all the SoCs of
the family and configuration data specific for Meson8. Adding support
for other SoCs should be only matter of defining new pins and banks.

The driver uses generic DT properties for the definition of mux and
configuration nodes; since there is an ongoing effort to centralize
the parsing to generic code, I've reused the patch "pinctrl:
pinconf-generic: Infer map type from DT property" [1] posted a few
days ago by Soren Brinkmann. I will update the series if that patch is
going to change after the mailing list discussion.

[1] https://lkml.org/lkml/2014/11/3/704

Changes since v2 [ https://lkml.org/lkml/2014/10/14/423 ]
 - move modifications to mach-meson Kconfig to a separate patch
 - use regmap_mmio
 - use generic gpio xlate function
 - don't hardcode gpio base number
 - use gpiochip_add_pin_range()
 - add kerneldoc documentation
 - use plain module_platform_driver() instead of postcore_initcall
 - avoid unneeded copies of platform data

Changes since v1 [ https://lkml.org/lkml/2014/10/7/712 ]
 - added missing checks of return values
 - indentation fixes
 - added missing definitions of groups and functions for Meson8

Beniamino Galvani (3):
  pinctrl: meson: add device tree bindings documentation
  pinctrl: add driver for Amlogic Meson SoCs
  ARM: meson: select PINCTRL_MESON and ARCH_REQUIRE_GPIOLIB

 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  |   97 ++
 arch/arm/mach-meson/Kconfig|3 +
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/meson/Makefile |2 +
 drivers/pinctrl/meson/pinctrl-meson.c  |  761 ++
 drivers/pinctrl/meson/pinctrl-meson.h  |  209 
 drivers/pinctrl/meson/pinctrl-meson8.c | 1087 
 include/dt-bindings/gpio/meson8-gpio.h |  157 +++
 9 files changed, 2325 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

-- 
1.9.1

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[PATCH v3 1/3] pinctrl: meson: add device tree bindings documentation

[Beniamino Galvani]

Add device tree bindings documentation for Amlogic Meson pin and GPIO
controller.

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  | 97 ++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
new file mode 100644
index 000..9edd1ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -0,0 +1,97 @@
+== Amlogic Meson pinmux controller ==
+
+Required properties for the root node:
+ - compatible: "amlogic,meson8-pinctrl"
+ - reg: address and size of registers controlling irq functionality
+
+=== GPIO sub-nodes ===
+
+The 2 power domains of the controller (regular and always-on) are
+represented as sub-nodes and each of them acts as a GPIO controller.
+
+Required properties for sub-nodes are:
+ - reg: should contain address and size for mux, pull-enable, pull and
+   gpio register sets
+ - reg-names: an array of strings describing the "reg" entries. Must
+   contain "mux", "pull" and "gpio". "pull-enable" is optional and
+   when it is missing the "pull" registers are used instead
+ - gpio-controller: identifies the node as a gpio controller
+ - #gpio-cells: must be 2
+
+Valid sub-node names are:
+ - "banks" for the regular domain
+ - "ao-bank" for the always-on domain
+
+=== Other sub-nodes ===
+
+Child nodes without the "gpio-controller" represent some desired
+configuration for a pin or a group. Those nodes can be pinmux nodes or
+configuration nodes.
+
+Required properties for pinmux nodes are:
+ - groups: a list of pinmux groups. The list of all available groups
+   depends on the SoC and can be found in driver sources.
+ - function: the name of a function to activate for the specified set
+   of groups. The list of all available functions depends on the SoC
+   and can be found in driver sources.
+
+Required properties for configuration nodes:
+ - pins: a list of pin names
+
+Configuration nodes support the generic properties "bias-disable",
+"bias-pull-up" and "bias-pull-down", described in file
+pinctrl-bindings.txt
+
+=== Example ===
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e8 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull", "pull-enable", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   nand {
+   mux {
+   groups = "nand_io", "nand_io_ce0", 
"nand_io_ce1",
+"nand_io_rb0", "nand_ale", "nand_cle",
+"nand_wen_clk", "nand_ren_clk", 
"nand_dqs",
+"nand_ce2", "nand_ce3";
+   function = "nand";
+   };
+   };
+
+   uart_ao_a {
+   mux {
+   groups = "uart_tx_ao_a", "uart_rx_ao_a",
+"uart_cts_ao_a", "uart_rts_ao_a";
+   function = "uart_ao";
+   };
+
+   conf {
+   pins = "GPIOAO_0", "GPIOAO_1",
+  "GPIOAO_2", "GPIOAO_3";
+   bias-disable;
+   };
+   };
+   };
+
-- 
1.9.1

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[PATCH] clocksource: meson6: Select CLKSRC_MMIO

[Beniamino Galvani]

Select CLKSRC_MMIO when the meson6_timer driver is enabled since it
depends on clocksource MMIO functions.

Signed-off-by: Beniamino Galvani 
---
 drivers/clocksource/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9042060..f657a48 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -32,6 +32,7 @@ config ARMADA_370_XP_TIMER
 
 config MESON6_TIMER
bool
+   select CLKSRC_MMIO
 
 config ORION_TIMER
select CLKSRC_OF
-- 
1.9.1

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[PATCH v3 1/3] i2c: meson: add device tree bindings documentation

[Beniamino Galvani]

This commit adds device tree bindings documentation for the I2C bus
controller found on Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/i2c/i2c-meson.txt  | 24 ++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-meson.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt 
b/Documentation/devicetree/bindings/i2c/i2c-meson.txt
new file mode 100644
index 000..682f9a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-meson.txt
@@ -0,0 +1,24 @@
+Amlogic Meson I2C controller
+
+Required properties:
+ - compatible: must be "amlogic,meson6-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+
+Optional properties:
+- clock-frequency: the desired I2C bus clock frequency in Hz; in
+  absence of this property the default value is used (100 kHz).
+
+Examples:
+
+   i2c@c8100500 {
+   compatible = "amlogic,meson6-i2c";
+   reg = <0xc8100500 0x20>;
+   interrupts = <0 92 1>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
-- 
1.9.1

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[PATCH v3 0/3] i2c: add driver for Amlogic Meson I2C controller

[Beniamino Galvani]

Hi,

this patchset adds a driver for the I2C controller available in
Amlogic Meson SoCs. It has been tested on a Meson8 based board with
the following devices:
 - Ricoh RN5T618 PMIC
 - NXP PCF8564 RTC

Changes since v2:
 - fixed token generation for split reads
 - simplified meson_i2c_prepare_xfer()
 - added DTS patch

Changes since v1:
 - factored common code for token list setup

Beniamino Galvani (3):
  i2c: meson: add device tree bindings documentation
  i2c: add support for Amlogic Meson I2C controller
  ARM: dts: meson: add I2C controller nodes

 .../devicetree/bindings/i2c/i2c-meson.txt  |  24 +
 arch/arm/boot/dts/meson.dtsi   |  30 ++
 drivers/i2c/busses/Kconfig |   7 +
 drivers/i2c/busses/Makefile|   1 +
 drivers/i2c/busses/i2c-meson.c | 492 +
 5 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-meson.txt
 create mode 100644 drivers/i2c/busses/i2c-meson.c

-- 
1.9.1

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[PATCH v3 3/3] ARM: dts: meson: add I2C controller nodes

[Beniamino Galvani]

Add nodes for I2C controllers A,B,AO, which are available in both
Meson6 and Meson8.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..4f16aee 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -106,5 +106,35 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   i2c_AO: i2c@c8100500 {
+   compatible = "amlogic,meson6-i2c";
+   reg = <0xc8100500 0x20>;
+   interrupts = <0 92 1>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c_A: i2c@c1108500 {
+   compatible = "amlogic,meson6-i2c";
+   reg = <0xc1108500 0x20>;
+   interrupts = <0 21 1>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c_B: i2c@c11087c0 {
+   compatible = "amlogic,meson6-i2c";
+   reg = <0xc11087c0 0x20>;
+   interrupts = <0 128 1>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH v3 2/3] i2c: add support for Amlogic Meson I2C controller

[Beniamino Galvani]

This is a driver for the I2C controller found in Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 drivers/i2c/busses/Kconfig |   7 +
 drivers/i2c/busses/Makefile|   1 +
 drivers/i2c/busses/i2c-meson.c | 492 +
 3 files changed, 500 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-meson.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 917c358..b76fd31 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -553,6 +553,13 @@ config I2C_KEMPLD
  This driver can also be built as a module. If so, the module
  will be called i2c-kempld.
 
+config I2C_MESON
+   tristate "Amlogic Meson I2C controller"
+   depends on ARCH_MESON
+   help
+ If you say yes to this option, support will be included for the
+ I2C interface on the Amlogic Meson family of SoCs.
+
 config I2C_MPC
tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
depends on PPC
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 78d56c5..a3f2de9 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
 obj-$(CONFIG_I2C_KEMPLD)   += i2c-kempld.o
+obj-$(CONFIG_I2C_MESON)+= i2c-meson.o
 obj-$(CONFIG_I2C_MPC)  += i2c-mpc.o
 obj-$(CONFIG_I2C_MV64XXX)  += i2c-mv64xxx.o
 obj-$(CONFIG_I2C_MXS)  += i2c-mxs.o
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
new file mode 100644
index 000..5e176ad
--- /dev/null
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -0,0 +1,492 @@
+/*
+ * I2C bus driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Meson I2C register map */
+#define REG_CTRL   0x00
+#define REG_SLAVE_ADDR 0x04
+#define REG_TOK_LIST0  0x08
+#define REG_TOK_LIST1  0x0c
+#define REG_TOK_WDATA0 0x10
+#define REG_TOK_WDATA1 0x14
+#define REG_TOK_RDATA0 0x18
+#define REG_TOK_RDATA1 0x1c
+
+/* Control register fields */
+#define REG_CTRL_START BIT(0)
+#define REG_CTRL_ACK_IGNOREBIT(1)
+#define REG_CTRL_STATUSBIT(2)
+#define REG_CTRL_ERROR BIT(3)
+#define REG_CTRL_CLKDIV_SHIFT  12
+#define REG_CTRL_CLKDIV_MASK   ((BIT(10) - 1) << REG_CTRL_CLKDIV_SHIFT)
+
+#define I2C_TIMEOUT_MS 500
+#define DEFAULT_FREQ   10
+
+enum {
+   TOKEN_END = 0,
+   TOKEN_START,
+   TOKEN_SLAVE_ADDR_WRITE,
+   TOKEN_SLAVE_ADDR_READ,
+   TOKEN_DATA,
+   TOKEN_DATA_LAST,
+   TOKEN_STOP,
+};
+
+enum {
+   STATE_IDLE,
+   STATE_READ,
+   STATE_WRITE,
+   STATE_STOP,
+};
+
+/**
+ * struct meson_i2c - Meson I2C device private data
+ *
+ * @adap:  I2C adapter instance
+ * @dev:   Pointer to device structure
+ * @regs:  Base address of the device memory mapped registers
+ * @clk:   Pointer to clock structure
+ * @irq:   IRQ number
+ * @msg:   Pointer to the current I2C message
+ * @state: Current state in the driver state machine
+ * @last:  Flag set for the last message in the transfer
+ * @count: Number of bytes to be sent/received in current transfer
+ * @pos:   Current position in the send/receive buffer
+ * @error: Flag set when an error is received
+ * @lock:  To avoid race conditions between irq handler and xfer code
+ * @done:  Completion used to wait for transfer termination
+ * @frequency: Operating frequency of I2C bus clock
+ * @tokens:Sequence of tokens to be written to the device
+ * @num_tokens:Number of tokens
+ */
+struct meson_i2c {
+   struct i2c_adapter  adap;
+   struct device   *dev;
+   void __iomem*regs;
+   struct clk  *clk;
+   int irq;
+
+   struct i2c_msg  *msg;
+   int state;
+   boollast;
+   int count;
+   int pos;
+   int error;
+
+   spinlock_t  lock;
+   struct completion   done;
+   unsigned intfrequency;
+   u32 tokens[2];
+   int num_tokens;
+};
+
+static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
+  u32 val)
+{
+   u32 data;
+
+   data = readl(i2c->regs + reg);
+   data &= 

Re: [PATCH 2/3] spi: meson: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

On Mon, Nov 10, 2014 at 03:11:40PM +, Mark Brown wrote:
> On Sun, Nov 09, 2014 at 11:56:50PM +0100, Beniamino Galvani wrote:
> > On Sun, Nov 09, 2014 at 10:17:12AM +, Mark Brown wrote:
>
> > > I noticed that the handling of /CS was done in the spifc_txrx() function
> > > - will this do the right thing if the transfer needs to be split for the
> > > buffer size?
> 
> > It should. When the transfer gets split, CS is kept active for all the
> > chunks and the value of CS after that depends on the value of
> > cs_change.
> 
> Can you be more specific about how that works?  I'm just not seeing the
> code that handles this.

It's this:

static int meson_spifc_txrx(struct meson_spifc *spifc,
struct spi_transfer *xfer,
int offset, int len, bool last_xfer,
bool last_chunk)
{
bool keep_cs = true;

[...]

if (last_chunk) {
if (last_xfer)
keep_cs = xfer->cs_change;
else
keep_cs = !xfer->cs_change;
}

regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
   keep_cs ? USER4_CS_ACT : 0);

/* start transfer */
[...]
}

The USER4_CS_ACT bit specifies if CS must be kept active after the
transfer.

> > > > +   if (!ret && xfer->delay_usecs)
> > > > +   udelay(xfer->delay_usecs);
> 
> > > The core will do this for you if you implement this as transfer_one().
> 
> > Please correct me if I'm wrong, but I think that transfer_one() can't
> > be used in this case. The hardware doesn't support direct manipulation
> > of CS and allows only to specify if CS must be kept active after the
> > current transfer. So I need to know for each transfer if it's the last
> > and this can be achieved only implementing transfer_one_message().
> 
> This is already in a function that's operating at the transfer_one()
> level, the function is even called transfer_one() and besides it's
> clearly not something specific to this hardware so should be factored
> out into the core instead of open coded.

A way to simplify this at core level could be to add a 'last' flag to
the spi_transfer structure and populate it before calling
transfer_one_message(); in this way, drivers that need to know the
position of the transfer in the message in order to properly handle CS
can use the generic version of transfer_one_message() instead of
reimplementing it. It seems that other existing drivers probably can
benefit from this.

Beniamino
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Re: [PATCH v2 2/3] media: rc: add driver for Amlogic Meson IR remote receiver

[Beniamino Galvani]

On Sun, Nov 09, 2014 at 08:36:09PM +, Sean Young wrote:
> > [...]
> > +   dev_info(dev, "receiver initialized\n");
> > +
> > +   return 0;
> > +out_unreg:
> > +   rc_unregister_device(ir->rc);
> 
> rc_unregister_device() already calls rc_free_device().

Right, I will fix this.

Thanks,
Beniamino
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Re: [PATCH v2 1/2] i2c: add support for Amlogic Meson I2C controller

[Beniamino Galvani]

On Mon, Nov 10, 2014 at 03:44:41PM +0100, Wolfram Sang wrote:
> On Sun, Oct 05, 2014 at 10:17:11PM +0200, Beniamino Galvani wrote:
> > This is a driver for the I2C controller found in Amlogic Meson SoCs.
> > 
> > Signed-off-by: Beniamino Galvani 
> 
> Thanks. Looking very good already!
> 
> > +static void meson_i2c_prepare_xfer(struct meson_i2c *i2c, bool write)
> 
> Instead of the bool, maybe you could query i2c->state in the function?
> You decide, I am not forcing you to do this.

Seems reasonable, will do.

> 
> > +static u32 meson_i2c_func(struct i2c_adapter *adap)
> > +{
> > +   return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> > +}
> 
> Have you tested 0-byte transfers, too (i2cdetect -q)? What was your test
> scenario in general?

I did a test with i2cdetect and quick write commands appear to
work.

When I wrote the driver I tested it to communicate with the only I2C
device available on the board, a Ricoh RN5T618 PMIC.

Now I have access to a hardware with a PCF8564 RTC and just realized
that long reads don't work properly, so I'm going to submit a new
version of the patchset in the next days.

Thanks,
Beniamino
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Re: [PATCH 2/3] spi: meson: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

On Sun, Nov 09, 2014 at 10:17:12AM +, Mark Brown wrote:
> On Sun, Nov 09, 2014 at 10:25:12AM +0100, Beniamino Galvani wrote:
> 
> > +static int meson_spifc_wait_ready(struct meson_spifc *spifc)
> > +{
> > +   unsigned long deadline = jiffies + msecs_to_jiffies(1000);
> > +   u32 data;
> > +
> > +   do {
> > +   regmap_read(spifc->regmap, REG_SLAVE, &data);
> > +   if (data & SLAVE_TRST_DONE)
> > +   return 0;
> > +   cond_resched();
> > +   } while (time_before(jiffies, deadline));
> 
> This will busy wait for up to a second, that seems like a long time to
> busy wait.  We also appear to be using this for the entire duration of
> the transfer which could be a fairly long time even during normal
> operation if doing a large transfer such as a firmware download, or if
> the bus speed is low.

Yes, probably the timeout value is too long since the maximum length
of a basic transfer is 64 bytes. Can you suggest a reasonable value?

> 
> > +   meson_spifc_setup_speed(spifc, xfer->speed_hz ? xfer->speed_hz :
> > +   spi->max_speed_hz);
> > +
> 
> Please avoid the ternery operator, it does nothing for legibility and in
> this case it's not needed as the core will always ensure that there is a
> per-transfer speed set.

Ok.

> > +   while (done < xfer->len && !ret) {
> > +   len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE);
> > +   ret = meson_spifc_txrx(spifc, xfer, done, len,
> > +  last_xfer, done + len >= xfer->len);
> > +   done += len;
> > +   }
> 
> I noticed that the handling of /CS was done in the spifc_txrx() function
> - will this do the right thing if the transfer needs to be split for the
> buffer size?

It should. When the transfer gets split, CS is kept active for all the
chunks and the value of CS after that depends on the value of
cs_change.

> 
> > +   if (!ret && xfer->delay_usecs)
> > +   udelay(xfer->delay_usecs);
> 
> The core will do this for you if you implement this as transfer_one().

Please correct me if I'm wrong, but I think that transfer_one() can't
be used in this case. The hardware doesn't support direct manipulation
of CS and allows only to specify if CS must be kept active after the
current transfer. So I need to know for each transfer if it's the last
and this can be achieved only implementing transfer_one_message().

> 
> > +static int meson_spifc_transfer_one_message(struct spi_master *master,
> > +   struct spi_message *msg)
> 
> This appears to do nothing that the core won't do - just implement
> transfer_one() and remove this.
> 
> > +   spifc = spi_master_get_devdata(master);
> > +   memset(spifc, 0, sizeof(struct meson_spifc));
> 
> There should be no need for this memset.
> 
> > +   spifc_regmap_config.max_register = resource_size(res) - 4;
> > +   spifc_regmap_config.name = "amlogic,meson-spifc";
> 
> If you're dynamically initializing the structure you need to work with a
> copy of it rather than directly since there may be multiple instances.
> I'm not seeing a reason to override the regmap name here, this is only
> really intended for devices with multiple register maps.
> 
> > +   ret = clk_prepare_enable(spifc->clk);
> > +   if (ret) {
> > +   dev_err(spifc->dev, "can't prepare clock\n");
> > +   goto out_err;
> > +   }
> 
> You should really implement runtime PM operations to disable this when
> not in use and use auto_runtime_pm to make sure this happens.
> 
> > +   master->bus_num = pdev->id;
> 
> Leave this blank for DT only devices (and for non-DT devices this won't
> work if you get two different buses).

Ok, will do. Thanks for the review.

Beniamino

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[PATCH 3/3] ARM: dts: meson: add node for SPIFC

[Beniamino Galvani]

This adds a node for the SPI Flash Controller to the Amlogic Meson
DTS.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..d28b16e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -106,5 +106,14 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   spifc: spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <&clk81>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH 2/3] spi: meson: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.

The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, basically toggling a
bit in a dedicated register. The driver doesn't use those predefined
commands and relies only on custom transfers.

Signed-off-by: Beniamino Galvani 
---
 drivers/spi/Kconfig   |   7 +
 drivers/spi/Makefile  |   1 +
 drivers/spi/spi-meson-spifc.c | 411 ++
 3 files changed, 419 insertions(+)
 create mode 100644 drivers/spi/spi-meson-spifc.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 84e7c9e..3c98a9d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -301,6 +301,13 @@ config SPI_FSL_ESPI
  From MPC8536, 85xx platform uses the controller, and all P10xx,
  P20xx, P30xx,P40xx, P50xx uses this controller.
 
+config SPI_MESON_SPIFC
+   bool "Amlogic Meson SPIFC controller"
+   depends on ARCH_MESON
+   help
+ This enables master mode support for the SPIFC (SPI flash
+ controller) available in Amlogic Meson SoCs.
+
 config SPI_OC_TINY
tristate "OpenCores tiny SPI"
depends on GPIOLIB
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 78f24ca..9b8a747 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
+obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)  += spi-mpc52xx.o
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
new file mode 100644
index 000..a0ba5d8
--- /dev/null
+++ b/drivers/spi/spi-meson-spifc.c
@@ -0,0 +1,411 @@
+/*
+ * Driver for Amlogic Meson SPI flash controller (SPIFC)
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register map */
+#define REG_CMD0x00
+#define REG_ADDR   0x04
+#define REG_CTRL   0x08
+#define REG_CTRL1  0x0c
+#define REG_STATUS 0x10
+#define REG_CTRL2  0x14
+#define REG_CLOCK  0x18
+#define REG_USER   0x1c
+#define REG_USER1  0x20
+#define REG_USER2  0x24
+#define REG_USER3  0x28
+#define REG_USER4  0x2c
+#define REG_SLAVE  0x30
+#define REG_SLAVE1 0x34
+#define REG_SLAVE2 0x38
+#define REG_SLAVE3 0x3c
+#define REG_C0 0x40
+#define REG_B8 0x60
+
+/* register fields */
+#define CMD_USER   BIT(18)
+#define CTRL_ENABLE_AHBBIT(17)
+#define CLOCK_SOURCE   BIT(31)
+#define CLOCK_DIV_SHIFT12
+#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
+#define CLOCK_CNT_HIGH_SHIFT   6
+#define CLOCK_CNT_HIGH_MASK(0x3f << CLOCK_CNT_HIGH_SHIFT)
+#define CLOCK_CNT_LOW_SHIFT0
+#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
+#define USER_DIN_EN_MS BIT(0)
+#define USER_CMP_MODE  BIT(2)
+#define USER_UC_DOUT_SEL   BIT(27)
+#define USER_UC_DIN_SELBIT(28)
+#define USER_UC_MASK   ((BIT(5) - 1) << 27)
+#define USER1_BN_UC_DOUT_SHIFT 17
+#define USER1_BN_UC_DOUT_MASK  (0xff << 16)
+#define USER1_BN_UC_DIN_SHIFT  8
+#define USER1_BN_UC_DIN_MASK   (0xff << 8)
+#define USER4_CS_ACT   BIT(30)
+#define SLAVE_TRST_DONEBIT(4)
+#define SLAVE_OP_MODE  BIT(30)
+#define SLAVE_SW_RST   BIT(31)
+
+#define SPIFC_BUFFER_SIZE  64
+
+/**
+ * struct meson_spifc
+ * @master:the SPI master
+ * @regmap:regmap for device registers
+ * @clk:   input clock of the built-in baud rate generator
+ * @device:the device structure
+ */
+struct meson_spifc {
+   struct spi_master *master;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct device *dev;
+};
+
+static struct regmap_

[PATCH 1/3] spi: meson: Add device tree bindings documentation for SPIFC

[Beniamino Galvani]

This adds documentation of device tree bindings for the Amlogic Meson
SPIFC (SPI Flash Controller).

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/spi/spi-meson.txt  | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt 
b/Documentation/devicetree/bindings/spi/spi-meson.txt
new file mode 100644
index 000..bb52a86
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-meson.txt
@@ -0,0 +1,22 @@
+Amlogic Meson SPI controllers
+
+* SPIFC (SPI Flash Controller)
+
+The Meson SPIFC is a controller optimized for communication with SPI
+NOR memories, without DMA support and a 64-byte unified transmit /
+receive buffer.
+
+Required properties:
+ - compatible: should be "amlogic,meson6-spifc"
+ - reg: physical base address and length of the controller registers
+ - clocks: phandle of the input clock for the baud rate generator
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+   spi@c1108c80 {
+   compatible = "amlogic,meson6-spifc";
+   reg = <0xc1108c80 0x80>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
-- 
1.9.1

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[PATCH 0/3] spi: Add support for Amlogic Meson SPIFC

[Beniamino Galvani]

Hi,

this patchset adds a driver for the SPIFC (SPI flash controller)
available in Amlogic Meson6 and Meson8 SoCs. It doesn't support DMA
and has a 64-byte unified transmit/receive buffer.

The driver has been tested on a Meson8 based device to communicate
with a Macronix mx25l1606e serial flash.

Beniamino Galvani (3):
  spi: meson: Add device tree bindings documentation for SPIFC
  spi: meson: Add support for Amlogic Meson SPIFC
  ARM: dts: meson: add node for SPIFC

 .../devicetree/bindings/spi/spi-meson.txt  |  22 ++
 arch/arm/boot/dts/meson.dtsi   |   9 +
 drivers/spi/Kconfig|   7 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-meson-spifc.c  | 411 +
 5 files changed, 450 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
 create mode 100644 drivers/spi/spi-meson-spifc.c

-- 
1.9.1

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[PATCH v2 2/3] media: rc: add driver for Amlogic Meson IR remote receiver

[Beniamino Galvani]

Amlogic Meson SoCs include a infrared remote control receiver that can
operate in two modes: "NEC" mode in which the hardware decodes frames
using the NEC IR protocol, and "general" mode in which the receiver
simply reports the duration of pulses and spaces for software
decoding.

This is a driver for the IR receiver that implements software decoding
of received frames.

Signed-off-by: Beniamino Galvani 
---
 MAINTAINERS |   1 +
 drivers/media/rc/Kconfig|  11 +++
 drivers/media/rc/Makefile   |   1 +
 drivers/media/rc/meson-ir.c | 215 
 4 files changed, 228 insertions(+)
 create mode 100644 drivers/media/rc/meson-ir.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 0662378..f1bc045 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ ARM/Amlogic MesonX SoC support
 M: Carlo Caione 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
+F: drivers/media/rc/meson-ir.c
 N: meson[x68]
 
 ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 1aea732..ddfab25 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -223,6 +223,17 @@ config IR_FINTEK
   To compile this driver as a module, choose M here: the
   module will be called fintek-cir.
 
+config IR_MESON
+   tristate "Amlogic Meson IR remote receiver"
+   depends on RC_CORE
+   depends on ARCH_MESON || COMPILE_TEST
+   ---help---
+  Say Y if you want to use the IR remote receiver available
+  on Amlogic Meson SoCs.
+
+  To compile this driver as a module, choose M here: the
+  module will be called meson-ir.
+
 config IR_NUVOTON
tristate "Nuvoton w836x7hg Consumer Infrared Transceiver"
depends on PNP
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 8f509e0..379a5c0 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_IR_IMON) += imon.o
 obj-$(CONFIG_IR_ITE_CIR) += ite-cir.o
 obj-$(CONFIG_IR_MCEUSB) += mceusb.o
 obj-$(CONFIG_IR_FINTEK) += fintek-cir.o
+obj-$(CONFIG_IR_MESON) += meson-ir.o
 obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
 obj-$(CONFIG_IR_ENE) += ene_ir.o
 obj-$(CONFIG_IR_REDRAT3) += redrat3.o
diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
new file mode 100644
index 000..4d6aed1
--- /dev/null
+++ b/drivers/media/rc/meson-ir.c
@@ -0,0 +1,215 @@
+/*
+ * Driver for Amlogic Meson IR remote receiver
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define DRIVER_NAME"meson-ir"
+
+#define IR_DEC_LDR_ACTIVE  0x00
+#define IR_DEC_LDR_IDLE0x04
+#define IR_DEC_LDR_REPEAT  0x08
+#define IR_DEC_BIT_0   0x0c
+#define IR_DEC_REG00x10
+#define IR_DEC_FRAME   0x14
+#define IR_DEC_STATUS  0x18
+#define IR_DEC_REG10x1c
+
+#define REG0_RATE_MASK (BIT(11) - 1)
+
+#define REG1_MODE_MASK (BIT(7) | BIT(8))
+#define REG1_MODE_NEC  (0 << 7)
+#define REG1_MODE_GENERAL  (2 << 7)
+
+#define REG1_TIME_IV_SHIFT 16
+#define REG1_TIME_IV_MASK  ((BIT(13) - 1) << REG1_TIME_IV_SHIFT)
+
+#define REG1_IRQSEL_MASK   (BIT(2) | BIT(3))
+#define REG1_IRQSEL_NEC_MODE   (0 << 2)
+#define REG1_IRQSEL_RISE_FALL  (1 << 2)
+#define REG1_IRQSEL_FALL   (2 << 2)
+#define REG1_IRQSEL_RISE   (3 << 2)
+
+#define REG1_RESET BIT(0)
+#define REG1_ENABLEBIT(15)
+
+#define STATUS_IR_DEC_IN   BIT(8)
+
+#define MESON_TRATE10  /* us */
+
+struct meson_ir {
+   void __iomem*reg;
+   struct rc_dev   *rc;
+   int irq;
+   spinlock_t  lock;
+};
+
+static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
+ u32 mask, u32 value)
+{
+   u32 data;
+
+   data = readl(ir->reg + reg);
+   data &= ~mask;
+   data |= (value & mask);
+   writel(data, ir->reg + reg);
+}
+
+static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
+{
+   struct meson_ir *ir = dev_id;
+   u32 duration;
+   DEFINE_IR_RAW_EVENT(rawir);
+
+   spin_lock(&ir->lock);
+
+   duration = readl(ir->reg + IR_DEC_REG1);
+   duration = (duration & REG1_TIME_IV_MASK) >> REG1_TIME_IV_SHIFT;
+  

[PATCH v2 0/3] media: rc: add support for Amlogic Meson IR receiver

[Beniamino Galvani]

Hi,

this is a driver for the infrared receiver available in Amlogic Meson6
and Meson8 SoCs. The device can operate in two modes: "NEC" mode in
which the hardware decodes frames using the NEC IR protocol, and
"general" mode in which the receiver simply reports the duration of
pulses and spaces for software decoding.

In order to have the maximum compatibility with different protocols
the driver implements software decoding.

Changes since v1:
 - added COMPILE_TEST to allow compilation for other architectures
 - added missing header files
 - removed bogus vendor, product and version assignments
 - added file path to Meson entry in MAINTAINERS
 - reordered patches

Beniamino Galvani (3):
  media: rc: meson: document device tree bindings
  media: rc: add driver for Amlogic Meson IR remote receiver
  ARM: dts: meson: add IR receiver node

 .../devicetree/bindings/media/meson-ir.txt |  14 ++
 MAINTAINERS|   1 +
 arch/arm/boot/dts/meson.dtsi   |   7 +
 drivers/media/rc/Kconfig   |  11 ++
 drivers/media/rc/Makefile  |   1 +
 drivers/media/rc/meson-ir.c| 215 +
 6 files changed, 249 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt
 create mode 100644 drivers/media/rc/meson-ir.c

-- 
1.9.1

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[PATCH v2 3/3] ARM: dts: meson: add IR receiver node

[Beniamino Galvani]

This adds a node for the IR remote control receiver to the Amlogic
Meson DTS.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..6a37f15 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -106,5 +106,12 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   ir_receiver: ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   status = "disabled";
+   };
};
 }; /* end of / */
-- 
1.9.1

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[PATCH v2 1/3] media: rc: meson: document device tree bindings

[Beniamino Galvani]

This adds binding documentation for the infrared remote control
receiver available in Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/media/meson-ir.txt | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt

diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt 
b/Documentation/devicetree/bindings/media/meson-ir.txt
new file mode 100644
index 000..407848e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/meson-ir.txt
@@ -0,0 +1,14 @@
+* Amlogic Meson IR remote control receiver
+
+Required properties:
+ - compatible  : should be "amlogic,meson6-ir"
+ - reg : physical base address and length of the device registers
+ - interrupts  : a single specifier for the interrupt from the device
+
+Example:
+
+   ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   };
-- 
1.9.1

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Re: [PATCH v5 20/48] mfd: rn5t618: Register power-off handler with kernel power-off handler

[Beniamino Galvani]

On Thu, Nov 06, 2014 at 08:43:04AM -0800, Guenter Roeck wrote:
> Register with kernel power-off handler instead of setting pm_power_off
> directly. Register with low priority to reflect that the original code
> only sets pm_power_off if it was not already set.
> 
> Cc: Beniamino Galvani 
> Acked-by: Lee Jones 
> Signed-off-by: Guenter Roeck 
> ---
> v5:
> - Rebase to v3.18-rc3
> v4:
> - Do not use notifiers but internal functions and data structures to manage
>   the list of power-off handlers. Drop unused parameters from callbacks, and
>   make the power-off function type void
> v3:
> - Replace poweroff in all newly introduced variables and in text
>   with power_off or power-off as appropriate
> - Replace POWEROFF_PRIORITY_xxx with POWER_OFF_PRIORITY_xxx
> v2:
> - New patch
> 
>  drivers/mfd/rn5t618.c   | 28 
>  include/linux/mfd/rn5t618.h |  2 ++
>  2 files changed, 14 insertions(+), 16 deletions(-)

Tested-by: Beniamino Galvani 
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Re: [PATCH 1/3] media: rc: add driver for Amlogic Meson IR remote receiver

[Beniamino Galvani]

On Mon, Nov 03, 2014 at 11:14:10AM -0200, Mauro Carvalho Chehab wrote:
> Em Sun, 12 Oct 2014 22:01:53 +0200
> Beniamino Galvani  escreveu:
> 
> > Amlogic Meson SoCs include a infrared remote control receiver that can
> > operate in two modes: in "NEC" mode the hardware can decode frames
> > using the NEC IR protocol, while in "general" mode the receiver simply
> > reports the duration of pulses and spaces for software decoding.
> > 
> > This is a driver for the IR receiver that uses software decoding of
> > received frames.
> 
> There are a few checkpatch warnings there:
> 
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #71: 
> new file mode 100644
> 
> WARNING: Missing a blank line after declarations
> #151: FILE: drivers/media/rc/meson-ir.c:76:
> + u32 duration;
> + DEFINE_IR_RAW_EVENT(rawir);

Here the macro is actually a variable definition and so it makes sense
to group it with the other definitions without blank lines. I checked
other rc drivers and many of them have a similar pattern. Could we
consider the warning as a false positive?

> 
> WARNING: DT compatible string "amlogic,meson6-ir" appears un-documented -- 
> check ./Documentation/devicetree/bindings/
> #272: FILE: drivers/media/rc/meson-ir.c:197:
> + { .compatible = "amlogic,meson6-ir" },
> 
> total: 0 errors, 3 warnings, 238 lines checked
> 
> patches/lmml_26418_1_3_media_rc_add_driver_for_amlogic_meson_ir_remote_receiver.patch
>  has style problems, please review.
> 
> I'm seeing that the DT patches are there, after this one. The best
> would be to add them before in the series.
> 
> Please add also an entry at the MAINTAINERS file.

I'll reorder the patches and add the maintainer entry.

> 
> 
> > 
> > Signed-off-by: Beniamino Galvani 
> > ---
> >  drivers/media/rc/Kconfig|  11 +++
> >  drivers/media/rc/Makefile   |   1 +
> >  drivers/media/rc/meson-ir.c | 214 
> > 
> >  3 files changed, 226 insertions(+)
> >  create mode 100644 drivers/media/rc/meson-ir.c
> > 
> > diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
> > index 8ce0810..2d742e2 100644
> > --- a/drivers/media/rc/Kconfig
> > +++ b/drivers/media/rc/Kconfig
> > @@ -223,6 +223,17 @@ config IR_FINTEK
> >To compile this driver as a module, choose M here: the
> >module will be called fintek-cir.
> >  
> > +config IR_MESON
> > +   tristate "Amlogic Meson IR remote receiver"
> > +   depends on RC_CORE
> > +   depends on ARCH_MESON
> 
> Please add COMPILE_TEST too, as we want to be able to compile it on
> x86 and other archs, in order to check if the driver builds fine and
> to enable the static analyzers to look into this code.

Ok.

[...]

> > +
> > +   ir->rc->priv = ir;
> > +   ir->rc->input_name = DRIVER_NAME;
> > +   ir->rc->input_phys = DRIVER_NAME "/input0";
> > +   ir->rc->input_id.bustype = BUS_HOST;
> 
> > +   ir->rc->input_id.vendor = 0x0001;
> > +   ir->rc->input_id.product = 0x0001;
> > +   ir->rc->input_id.version = 0x0100;
> 
> I don't like very much the idea of filling it like that. From where those
> numbers came? Could you add a define for them somewhere?

I've seen that other drivers as gpio-ir-recv and sunxi-cir assign
those numbers to the fields of input_id but I couldn't find a
documentation of the meaning. If the assignments are not needed I will
drop them in the next version.

Beniamino
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Re: [PATCH 2/3] pinctrl: meson: add device tree bindings documentation

[Beniamino Galvani]

On Fri, Oct 24, 2014 at 01:53:28PM +0200, Linus Walleij wrote:
> On Tue, Oct 7, 2014 at 11:32 PM, Beniamino Galvani  
> wrote:
> 
> > Add device tree bindings documentation for Amlogic Meson pinmux and
> > GPIO controller.
> >
> > Signed-off-by: Beniamino Galvani 
> (...)
> > +Required properties for gpio sub-nodes:
> > + - reg: should contain address and size for mux, pull-enable, pull and
> > +   gpio register sets
> > + - reg-names: an array of strings describing the "reg" entries. Must
> > +   contain "mux", "pull" and "gpio". "pull-enable" is optional and
> > +   when it is missing the "pull" registers are used instead
> 
> So it seems segmenting the registers is done to sort of control the
> hardware versioning.
> 
> I think it's better to use the compatible string to indicate different
> versions of the hardware and then have just have one big
> regs to cover all registers.

The problem here is that the register ranges are not contiguous and
the holes in between are used by other devices, so I can't use a
single range.

> 
> > +Valid gpio sub-nodes name are:
> > + - "banks" for the standard banks
> > + - "ao-bank" for the AO bank which belong to the special always-on
> > +   power domain
> 
> I think it's unnecessary to split up banks, the compatible property
> should be enough to know how many banks this controller has
> and where they are located in relation to the base offset.

I wanted to avoid a reg property with a list of 7 ranges. Anyway, I
agree that the split seems a bit arbitrary; I'll remove it.

> > +Required properties for configuration nodes:
> > + - pins: the name of a pin group. The list of all available groups can
> > +   be found in driver sources.
> > + - function: the name of a function to activate for the specified set
> > +   of groups. The list of all available functions can be found in
> > +   driver sources.
> 
> This is interesting. I have established that for controllers mapping
> functions to groups we use
> "function" and "groups".
> 
> So for per-pin configuration, "function" and "pins" would be
> apropriate.

I will use "groups" instead of "pins" for the pinmux configuration.

Thanks!
Beniamino
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Re: [PATCH 1/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

On Tue, Oct 21, 2014 at 03:39:25PM +0200, Linus Walleij wrote:
> On Tue, Oct 7, 2014 at 11:32 PM, Beniamino Galvani  
> wrote:
> 
> Sorry for a quick and brief review, but should be enough for you to proceed
> to iterate the patch.
> 
> > This is a driver for the pinmux and GPIO controller available in
> > Amlogic Meson SoCs. At the moment it only supports Meson8 devices,
> > however other SoC families like Meson6 and Meson8b (the Cortex-A5
> > variant) appears to be similar, with just different sets of banks and
> > registers.
> >
> > GPIO interrupts are not supported at the moment due to lack of
> > documentation.
> >
> > Signed-off-by: Beniamino Galvani 
> 
> >  arch/arm/mach-meson/Kconfig|   3 +
> 
> Please don't mix up driver submission with platform enablement.
> Put this Kconfig fragment in a separate patch.

Ok, will do.

> 
> > +++ b/drivers/pinctrl/meson/pinctrl-meson.c
> (...)
> 
> > +static void meson_domain_set_bit(struct meson_domain *domain,
> > +void __iomem *addr, unsigned int bit,
> > +unsigned int value)
> > +{
> > +   unsigned long flags;
> > +   unsigned int data;
> > +
> > +   spin_lock_irqsave(&domain->lock, flags);
> > +   data = readl(addr);
> > +
> > +   if (value)
> > +   data |= BIT(bit);
> > +   else
> > +   data &= ~BIT(bit);
> > +
> > +   writel(data, addr);
> > +   spin_unlock_irqrestore(&domain->lock, flags);
> > +}
> 
> Looks like you are re-implementing mmio regmap. Take a look at
> devm_regmap_init_mmio() from 

I missed that, thanks.

> > +static int meson_get_pin_reg_and_bit(struct meson_domain *domain,
> > +unsigned pin, int reg_type,
> > +unsigned int *reg_num, unsigned int 
> > *bit)
> > +{
> > +   struct meson_bank *bank;
> > +   int i, found = 0;
> 
> bool found;
> 
> > +
> > +   for (i = 0; i < domain->data->num_banks; i++) {
> > +   bank = &domain->data->banks[i];
> > +   if (pin >= bank->first && pin <= bank->last) {
> > +   found = 1;
> > +   break;
> > +   }
> > +   }
> > +
> > +   if (!found)
> > +   return 1;
> 
> Can't you return a negative errorcode like everyone else?

Sure.

> 
> > +
> > +   *reg_num = bank->regs[reg_type].reg;
> > +   *bit = bank->regs[reg_type].bit + pin - bank->first;
> > +
> > +   return 0;
> > +}
> 
> This function is weird and could use some kerneldoc explanation
> to what it does I think.

Ok.

> 
> > +static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
> > + struct pinctrl_gpio_range *range,
> > + unsigned offset)
> > +{
> > +   struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
> > +
> > +   meson_pmx_disable_other_groups(pc, offset, -1);
> 
> Passing the argument -1 is usually a bit ambiguous.
> 
> > +
> > +   return 0;
> > +}
> 
> > +static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
> > +{
> > +   return container_of(chip, struct meson_domain, chip);
> > +}
> 
> I have a very vague idea what a "meson domain" is, can this be explained
> in some good place? Like in the struct meson_domain with
> kerneldoc...

Yes, below there is an explanation.

> 
> > +static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
> > +{
> > +   struct meson_domain *domain = to_meson_domain(chip);
> > +   void __iomem *addr;
> > +   unsigned int bit;
> > +
> > +   if (meson_gpio_calc_reg_and_bit(domain, chip->base + gpio, REG_IN,
> > +   &addr, &bit))
> > +   return 0;
> > +
> > +   return (readl(addr) >> bit) & 1;
> 
> Do it like this:
> 
> return !!(readl(addr) & BIT(bit));
> 
> > +static int meson_gpio_of_xlate(struct gpio_chip *chip,
> > +  const struct of_phandle_args *gpiospec,
> > +  u32 *flags)
> > +{
> > +   unsigned gpio = gpiospec->args[0];
> > +
> > +   if (gpio < chip->base || gpio >= chip->base + chip->ngpio)

[PATCH v2 2/3] pinctrl: meson: add device tree bindings documentation

[Beniamino Galvani]

Add device tree bindings documentation for Amlogic Meson pinmux and
GPIO controller.

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  | 79 ++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
new file mode 100644
index 000..6645fa6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -0,0 +1,79 @@
+* Amlogic Meson pinmux controller
+
+Pins are organized in banks; all banks except AO are controlled by the
+same set of registers, while the AO bank uses a dedicated register
+range. The device tree uses sub-nodes to represent set of banks which
+share the same address space.
+
+Required properties for the root node:
+ - compatible: "amlogic,meson8-pinctrl"
+ - reg: address and size of the common registers controlling gpio irq
+   functionality
+
+Required properties for gpio sub-nodes:
+ - reg: should contain address and size for mux, pull-enable, pull and
+   gpio register sets
+ - reg-names: an array of strings describing the "reg" entries. Must
+   contain "mux", "pull" and "gpio". "pull-enable" is optional and
+   when it is missing the "pull" registers are used instead
+ - gpio-controller: identifies the node as a gpio controller
+ - #gpio-cells: must be 2
+
+Valid gpio sub-nodes name are:
+ - "banks" for the standard banks
+ - "ao-bank" for the AO bank which belong to the special always-on
+   power domain
+
+Required properties for configuration nodes:
+ - pins: the name of a pin group. The list of all available groups can
+   be found in driver sources.
+ - function: the name of a function to activate for the specified set
+   of groups. The list of all available functions can be found in
+   driver sources.
+
+Example:
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e4 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull-enable", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   nand {
+   nand {
+   pins = "nand_io", "nand_io_ce0", "nand_io_ce1",
+  "nand_io_rb0", "nand_ale", "nand_cle",
+  "nand_wen_clk", "nand_ren_clk", 
"nand_dqs",
+  "nand_ce2", "nand_ce3";
+   function = "nand";
+   };
+   };
+
+   uart_ao_a: uart_ao_a {
+   uart_ao_a {
+   pins = "uart_tx_ao_a", "uart_rx_ao_a";
+  "uart_cts_ao_a", "uart_rts_ao_a";
+   function = "uart_ao";
+   };
+   };
+   };
-- 
1.9.1

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[PATCH v2 3/3] ARM: dts: meson8: add pinctrl and gpio nodes

[Beniamino Galvani]

Add pinctrl node to meson8.dtsi and gpio-leds node to
meson8-vega-s89e.dts

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8-vega-s89e.dts | 16 +++-
 arch/arm/boot/dts/meson8.dtsi  | 35 ++
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8-vega-s89e.dts 
b/arch/arm/boot/dts/meson8-vega-s89e.dts
index 950998f..70a05c1 100644
--- a/arch/arm/boot/dts/meson8-vega-s89e.dts
+++ b/arch/arm/boot/dts/meson8-vega-s89e.dts
@@ -45,7 +45,9 @@
 
 
 /dts-v1/;
-/include/ "meson8.dtsi"
+#include "meson8.dtsi"
+#include 
+#include 
 
 / {
model = "Tronsmart Vega S89 Elite";
@@ -58,8 +60,20 @@
memory {
reg = <0x4000 0x8000>;
};
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   power {
+   gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "none";
+   };
+   };
+
 };
 
 &uart_AO {
status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart_ao_a>;
 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 42e4026..c82f597 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -85,4 +85,39 @@
compatible = "fixed-clock";
clock-frequency = <14166>;
};
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e4 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull-enable", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   uart_ao_a: uart_ao_a {
+   uart_ao_a {
+   pins = "uart_tx_ao_a", "uart_rx_ao_a";
+   function = "uart_ao";
+   };
+   };
+   };
+
 }; /* end of / */
-- 
1.9.1

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[PATCH v2 1/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. At the moment it only supports Meson8 devices,
however other SoC families like Meson6 and Meson8b (the Cortex-A5
variant) appear to be similar, with just different sets of banks and
registers.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/mach-meson/Kconfig|   3 +
 drivers/pinctrl/Kconfig|   8 +
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/meson/Makefile |   2 +
 drivers/pinctrl/meson/pinctrl-meson.c  | 824 +
 drivers/pinctrl/meson/pinctrl-meson.h  | 217 +
 drivers/pinctrl/meson/pinctrl-meson8.c | 534 +
 include/dt-bindings/gpio/meson8-gpio.h | 155 +++
 8 files changed, 1744 insertions(+)
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b289e8e..7c2988d 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -2,6 +2,9 @@ menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
select GENERIC_IRQ_CHIP
select ARM_GIC
+   select PINCTRL
+   select PINCTRL_MESON
+   select ARCH_REQUIRE_GPIOLIB
 
 if ARCH_MESON
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de..22b05e1 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
 
+config PINCTRL_MESON
+   bool "Amlogic Meson pin controller driver"
+   depends on ARCH_MESON
+   select PINMUX
+   select PINCONF
+   select GENERIC_PINCONF
+   select OF_GPIO
+
 config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d3..7b22f89 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_FALCON)   += pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_MESON)+= meson/
 obj-$(CONFIG_PINCTRL_PALMAS)   += pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000..03a90b4
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
+obj-y  += pinctrl-meson.o
+obj-y  += pinctrl-meson8.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c 
b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000..a02f50bc
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,824 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-meson.h"
+
+static void meson_domain_set_bit(struct meson_domain *domain,
+void __iomem *addr, unsigned int bit,
+unsigned int value)
+{
+   unsigned long flags;
+   unsigned int data;
+
+   spin_lock_irqsave(&domain->lock, flags);
+   data = readl(addr);
+
+   if (value)
+   data |= BIT(bit);
+   else
+   data &= ~BIT(bit);
+
+   writel(data, addr);
+   spin_unlock_irqrestore(&domain->lock, flags);
+}
+
+static struct meson_domain *meson_pinctrl_get_domain(struct meson_pinctrl *pc,
+int pin)
+{
+   struct meson_domain *domain;
+   int i, j;
+
+   for (i = 0; i < pc->num_domains; i++) {
+   domain = &pc->domains[i];
+   for (j = 0; j < domain->data->num_banks; j++) {
+   if (pin >= domain->data->banks[j].first &&
+   pin < domain->data->banks[j

[PATCH v2 0/3] Pinctrl driver for Amlogic Meson SoCs

[Beniamino Galvani]

Hi,

this series introduces a driver for Amlogic Meson pinctrl and GPIOs,
adding the basic infrastructure for all the SoCs of the Meson family
and configuration data specific for Meson8.

I tested the pinmux and GPIO functionalities on a Tronsmart Vega S89e
TV box and everything seems to work, however I'm not so familiar with
the pinctrl subsystem and thus any feedback is very welcome.

Changes since v1 [https://lkml.org/lkml/2014/10/7/712]
 - added missing checks of return values
 - indentation fixes
 - added missing definitions of groups and functions for Meson8

Beniamino Galvani (3):
  pinctrl: add driver for Amlogic Meson SoCs
  pinctrl: meson: add device tree bindings documentation
  ARM: dts: meson8: add pinctrl and gpio nodes

 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  |  79 ++
 arch/arm/boot/dts/meson8-vega-s89e.dts |  16 +-
 arch/arm/boot/dts/meson8.dtsi  |  35 +
 arch/arm/mach-meson/Kconfig|   3 +
 drivers/pinctrl/Kconfig|   8 +
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/meson/Makefile |   2 +
 drivers/pinctrl/meson/pinctrl-meson.c  | 824 +
 drivers/pinctrl/meson/pinctrl-meson.h  | 217 ++
 drivers/pinctrl/meson/pinctrl-meson8.c | 534 +
 include/dt-bindings/gpio/meson8-gpio.h | 155 
 11 files changed, 1873 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

-- 
1.9.1

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[PATCH 2/3] media: rc: meson: document device tree bindings

[Beniamino Galvani]

This adds binding documentation for the infrared remote control
receiver available in Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/media/meson-ir.txt | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt

diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt 
b/Documentation/devicetree/bindings/media/meson-ir.txt
new file mode 100644
index 000..407848e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/meson-ir.txt
@@ -0,0 +1,14 @@
+* Amlogic Meson IR remote control receiver
+
+Required properties:
+ - compatible  : should be "amlogic,meson6-ir"
+ - reg : physical base address and length of the device registers
+ - interrupts  : a single specifier for the interrupt from the device
+
+Example:
+
+   ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   };
-- 
1.9.1

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[PATCH 3/3] ARM: dts: meson: add dts nodes for IR receiver

[Beniamino Galvani]

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi   | 7 +++
 arch/arm/boot/dts/meson8-vega-s89e.dts | 6 ++
 arch/arm/boot/dts/meson8.dtsi  | 7 +++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 7d27f12..a14461c 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -108,5 +108,12 @@
clocks = <&clk81>;
status = "disabled";
};
+
+   ir_receiver: ir-receiver@c8100480 {
+   compatible= "amlogic,meson6-ir";
+   reg = <0xc8100480 0x20>;
+   interrupts = <0 15 1>;
+   status = "disabled";
+   };
};
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson8-vega-s89e.dts 
b/arch/arm/boot/dts/meson8-vega-s89e.dts
index 70a05c1..5ea54c8 100644
--- a/arch/arm/boot/dts/meson8-vega-s89e.dts
+++ b/arch/arm/boot/dts/meson8-vega-s89e.dts
@@ -77,3 +77,9 @@
pinctrl-names = "default";
pinctrl-0 = <&uart_ao_a>;
 };
+
+&ir_receiver {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&ir_pins>;
+};
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 59c3af0..ea98ed3 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -122,6 +122,13 @@
function = "uart_ao";
};
};
+
+   ir_pins: ir_pins {
+   ir_pins {
+   pins = "remote_input";
+   function = "remote";
+   };
+   };
};
 
 }; /* end of / */
-- 
1.9.1

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[PATCH 1/3] media: rc: add driver for Amlogic Meson IR remote receiver

[Beniamino Galvani]

Amlogic Meson SoCs include a infrared remote control receiver that can
operate in two modes: in "NEC" mode the hardware can decode frames
using the NEC IR protocol, while in "general" mode the receiver simply
reports the duration of pulses and spaces for software decoding.

This is a driver for the IR receiver that uses software decoding of
received frames.

Signed-off-by: Beniamino Galvani 
---
 drivers/media/rc/Kconfig|  11 +++
 drivers/media/rc/Makefile   |   1 +
 drivers/media/rc/meson-ir.c | 214 
 3 files changed, 226 insertions(+)
 create mode 100644 drivers/media/rc/meson-ir.c

diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 8ce0810..2d742e2 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -223,6 +223,17 @@ config IR_FINTEK
   To compile this driver as a module, choose M here: the
   module will be called fintek-cir.
 
+config IR_MESON
+   tristate "Amlogic Meson IR remote receiver"
+   depends on RC_CORE
+   depends on ARCH_MESON
+   ---help---
+  Say Y if you want to use the IR remote receiver available
+  on Amlogic Meson SoCs.
+
+  To compile this driver as a module, choose M here: the
+  module will be called meson-ir.
+
 config IR_NUVOTON
tristate "Nuvoton w836x7hg Consumer Infrared Transceiver"
depends on PNP
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 0989f94..06859bf 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_IR_IMON) += imon.o
 obj-$(CONFIG_IR_ITE_CIR) += ite-cir.o
 obj-$(CONFIG_IR_MCEUSB) += mceusb.o
 obj-$(CONFIG_IR_FINTEK) += fintek-cir.o
+obj-$(CONFIG_IR_MESON) += meson-ir.o
 obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
 obj-$(CONFIG_IR_ENE) += ene_ir.o
 obj-$(CONFIG_IR_REDRAT3) += redrat3.o
diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
new file mode 100644
index 000..0900ece
--- /dev/null
+++ b/drivers/media/rc/meson-ir.c
@@ -0,0 +1,214 @@
+/*
+ * Driver for Amlogic Meson IR remote receiver
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define DRIVER_NAME"meson-ir"
+
+#define IR_DEC_LDR_ACTIVE  0x00
+#define IR_DEC_LDR_IDLE0x04
+#define IR_DEC_LDR_REPEAT  0x08
+#define IR_DEC_BIT_0   0x0c
+#define IR_DEC_REG00x10
+#define IR_DEC_FRAME   0x14
+#define IR_DEC_STATUS  0x18
+#define IR_DEC_REG10x1c
+
+#define REG0_RATE_MASK (BIT(11) - 1)
+
+#define REG1_MODE_MASK (BIT(7) | BIT(8))
+#define REG1_MODE_NEC  (0 << 7)
+#define REG1_MODE_GENERAL  (2 << 7)
+
+#define REG1_TIME_IV_SHIFT 16
+#define REG1_TIME_IV_MASK  ((BIT(13) - 1) << REG1_TIME_IV_SHIFT)
+
+#define REG1_IRQSEL_MASK   (BIT(2) | BIT(3))
+#define REG1_IRQSEL_NEC_MODE   (0 << 2)
+#define REG1_IRQSEL_RISE_FALL  (1 << 2)
+#define REG1_IRQSEL_FALL   (2 << 2)
+#define REG1_IRQSEL_RISE   (3 << 2)
+
+#define REG1_RESET BIT(0)
+#define REG1_ENABLEBIT(15)
+
+#define STATUS_IR_DEC_IN   BIT(8)
+
+#define MESON_TRATE10  /* us */
+
+struct meson_ir {
+   void __iomem*reg;
+   struct rc_dev   *rc;
+   int irq;
+   spinlock_t  lock;
+};
+
+static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
+ u32 mask, u32 value)
+{
+   u32 data;
+
+   data = readl(ir->reg + reg);
+   data &= ~mask;
+   data |= (value & mask);
+   writel(data, ir->reg + reg);
+}
+
+static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
+{
+   struct meson_ir *ir = dev_id;
+   u32 duration;
+   DEFINE_IR_RAW_EVENT(rawir);
+
+   spin_lock(&ir->lock);
+
+   duration = readl(ir->reg + IR_DEC_REG1);
+   duration = (duration & REG1_TIME_IV_MASK) >> REG1_TIME_IV_SHIFT;
+   rawir.duration = US_TO_NS(duration * MESON_TRATE);
+
+   rawir.pulse = !!(readl(ir->reg + IR_DEC_STATUS) & STATUS_IR_DEC_IN);
+
+   ir_raw_event_store_with_filter(ir->rc, &rawir);
+   ir_raw_event_handle(ir->rc);
+
+   spin_unlock(&ir->lock);
+
+   return IRQ_HANDLED;
+}
+
+static int meson_ir_probe(struct platform_device *pdev)
+{
+   struct device *dev = &pdev->dev;
+   struct device_node *node = dev->of_node;
+   struct resource *r

[PATCH 0/3] media: rc: add support for Amlogic Meson IR receiver

[Beniamino Galvani]

Hi,

this is a driver for the IR receiver available in Amlogic Meson6 and
Meson8 SoCs. The device can operate in two modes: in "NEC" mode the
hardware can decode frames using the NEC IR protocol, while in
"general" mode the receiver simply reports the duration of pulses and
spaces for software decoding.

In order to have the maximum compatibility with different protocols
the driver implements software decoding.

The third patch (dts files) depends on some other patchsets [1][2]
that are still under review, so at the moment is not meant to be
merged.

[1] https://lkml.org/lkml/2014/10/5/162
[2] https://lkml.org/lkml/2014/10/7/712

Beniamino Galvani (3):
  media: rc: add driver for Amlogic Meson IR remote receiver
  media: rc: meson: document device tree bindings
  ARM: dts: meson: add dts nodes for IR receiver

 .../devicetree/bindings/media/meson-ir.txt |  14 ++
 arch/arm/boot/dts/meson.dtsi   |   7 +
 arch/arm/boot/dts/meson8-vega-s89e.dts |   6 +
 arch/arm/boot/dts/meson8.dtsi  |   7 +
 drivers/media/rc/Kconfig   |  11 ++
 drivers/media/rc/Makefile  |   1 +
 drivers/media/rc/meson-ir.c| 214 +
 7 files changed, 260 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/meson-ir.txt
 create mode 100644 drivers/media/rc/meson-ir.c

-- 
1.9.1

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[PATCH] regulator: rn5t618: Convert to new style DT parsing

[Beniamino Galvani]

Use the simplified DT parsing method to remove some duplicated
code.

Since this is a MFD subdevice and its device object doesn't have an
associated DT node, the configuration instance used to register the
regulators has been changed to point to the parent device.

Signed-off-by: Beniamino Galvani 
---
 drivers/regulator/rn5t618-regulator.c | 51 +++
 1 file changed, 4 insertions(+), 47 deletions(-)

diff --git a/drivers/regulator/rn5t618-regulator.c 
b/drivers/regulator/rn5t618-regulator.c
index e58d79a..b85ceb8 100644
--- a/drivers/regulator/rn5t618-regulator.c
+++ b/drivers/regulator/rn5t618-regulator.c
@@ -31,6 +31,8 @@ static struct regulator_ops rn5t618_reg_ops = {
 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \
[RN5T618_##rid] = { \
.name   = #rid, \
+   .of_match   = of_match_ptr(#rid),   \
+   .regulators_node = of_match_ptr("regulators"),  \
.id = RN5T618_##rid,\
.type   = REGULATOR_VOLTAGE,\
.owner  = THIS_MODULE,  \
@@ -60,60 +62,15 @@ static struct regulator_desc rn5t618_regulators[] = {
REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 90, 350, 25000),
 };
 
-static struct of_regulator_match rn5t618_matches[] = {
-   [RN5T618_DCDC1] = { .name = "DCDC1" },
-   [RN5T618_DCDC2] = { .name = "DCDC2" },
-   [RN5T618_DCDC3] = { .name = "DCDC3" },
-   [RN5T618_LDO1]  = { .name = "LDO1" },
-   [RN5T618_LDO2]  = { .name = "LDO2" },
-   [RN5T618_LDO3]  = { .name = "LDO3" },
-   [RN5T618_LDO4]  = { .name = "LDO4" },
-   [RN5T618_LDO5]  = { .name = "LDO5" },
-   [RN5T618_LDORTC1]   = { .name = "LDORTC1" },
-   [RN5T618_LDORTC2]   = { .name = "LDORTC2" },
-};
-
-static int rn5t618_regulator_parse_dt(struct platform_device *pdev)
-{
-   struct device_node *np, *regulators;
-   int ret;
-
-   np = of_node_get(pdev->dev.parent->of_node);
-   if (!np)
-   return 0;
-
-   regulators = of_get_child_by_name(np, "regulators");
-   if (!regulators) {
-   dev_err(&pdev->dev, "regulators node not found\n");
-   return -EINVAL;
-   }
-
-   ret = of_regulator_match(&pdev->dev, regulators, rn5t618_matches,
-ARRAY_SIZE(rn5t618_matches));
-   of_node_put(regulators);
-   if (ret < 0) {
-   dev_err(&pdev->dev, "error parsing regulator init data: %d\n",
-   ret);
-   }
-
-   return 0;
-}
-
 static int rn5t618_regulator_probe(struct platform_device *pdev)
 {
struct rn5t618 *rn5t618 = dev_get_drvdata(pdev->dev.parent);
struct regulator_config config = { };
struct regulator_dev *rdev;
-   int ret, i;
-
-   ret = rn5t618_regulator_parse_dt(pdev);
-   if (ret)
-   return ret;
+   int i;
 
for (i = 0; i < RN5T618_REG_NUM; i++) {
-   config.dev = &pdev->dev;
-   config.init_data = rn5t618_matches[i].init_data;
-   config.of_node = rn5t618_matches[i].of_node;
+   config.dev = pdev->dev.parent;
config.regmap = rn5t618->regmap;
 
rdev = devm_regulator_register(&pdev->dev,
-- 
1.9.1

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[PATCH 2/3] pinctrl: meson: add device tree bindings documentation

[Beniamino Galvani]

Add device tree bindings documentation for Amlogic Meson pinmux and
GPIO controller.

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  | 80 ++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
new file mode 100644
index 000..dd573d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -0,0 +1,80 @@
+* Amlogic Meson pinmux controller
+
+Pins are organized in banks; all banks except AO are controlled by the
+same set of registers, while the AO bank uses a dedicated register
+range. The device tree uses sub-nodes to represent set of banks which
+share the same address space.
+
+Required properties for the root node:
+ - compatible: "amlogic,meson8-pinctrl"
+ - reg: address and size of the common registers controlling gpio irq
+   functionality
+
+Required properties for gpio sub-nodes:
+ - reg: should contain address and size for mux, pull-enable, pull and
+   gpio register sets
+ - reg-names: an array of strings describing the "reg" entries. Must
+   contain "mux", "pull" and "gpio". "pull-enable" is optional and
+   when it is missing the "pull" registers are used instead
+ - gpio-controller: identifies the node as a gpio controller
+ - #gpio-cells: must be 2
+
+Valid gpio sub-nodes name are:
+ - "banks" for the standard banks
+ - "ao-bank" for the AO bank which belong to the special always-on
+   power domain
+
+Required properties for configuration nodes:
+ - pins: the name of a pin group. The list of all available groups can
+   be found in driver sources.
+ - function: the name of a function to activate for the specified set
+   of groups. The list of all available functions can be found in
+   driver sources.
+
+Example:
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e4 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull-enable", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   nand {
+   nand {
+   pins = "nand_io", "nand_io_ce0", "nand_io_ce1",
+  "nand_io_rb0", "nand_ale", "nand_cle",
+  "nand_wen_clk", "nand_ren_clk", 
"nand_dqs",
+  "nand_ce2", "nand_ce3";
+   function = "nand";
+   };
+   };
+
+   uart_ao_a: uart_ao_a {
+   uart_ao_a {
+   pins = "uart_tx_ao_a", "uart_rx_ao_a";
+  "uart_cts_ao_a", "uart_rts_ao_a";
+   function = "uart_ao";
+   };
+   };
+   };
+
-- 
1.9.1

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[PATCH 1/3] pinctrl: add driver for Amlogic Meson SoCs

[Beniamino Galvani]

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. At the moment it only supports Meson8 devices,
however other SoC families like Meson6 and Meson8b (the Cortex-A5
variant) appears to be similar, with just different sets of banks and
registers.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/mach-meson/Kconfig|   3 +
 drivers/pinctrl/Kconfig|   8 +
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/meson/Makefile |   2 +
 drivers/pinctrl/meson/pinctrl-meson.c  | 823 +
 drivers/pinctrl/meson/pinctrl-meson.h  | 217 +
 drivers/pinctrl/meson/pinctrl-meson8.c | 374 +++
 include/dt-bindings/gpio/meson8-gpio.h | 155 +++
 8 files changed, 1583 insertions(+)
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 18301dc..a09d3f6 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -3,6 +3,9 @@ menuconfig ARCH_MESON
select GENERIC_IRQ_CHIP
select ARM_GIC
select CACHE_L2X0
+   select PINCTRL
+   select PINCTRL_MESON
+   select ARCH_REQUIRE_GPIOLIB
 
 if ARCH_MESON
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de..22b05e1 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
 
+config PINCTRL_MESON
+   bool "Amlogic Meson pin controller driver"
+   depends on ARCH_MESON
+   select PINMUX
+   select PINCONF
+   select GENERIC_PINCONF
+   select OF_GPIO
+
 config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d3..7b22f89 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_FALCON)   += pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_MESON)+= meson/
 obj-$(CONFIG_PINCTRL_PALMAS)   += pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000..03a90b4
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
+obj-y  += pinctrl-meson.o
+obj-y  += pinctrl-meson8.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c 
b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000..876102d
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,823 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-meson.h"
+
+static void meson_domain_set_bit(struct meson_domain *domain,
+void __iomem *addr, unsigned int bit,
+unsigned int value)
+{
+   unsigned long flags;
+   unsigned int data;
+
+   spin_lock_irqsave(&domain->lock, flags);
+   data = readl(addr);
+
+   if (value)
+   data |= BIT(bit);
+   else
+   data &= ~BIT(bit);
+
+   writel(data, addr);
+   spin_unlock_irqrestore(&domain->lock, flags);
+}
+
+static struct meson_domain *meson_pinctrl_get_domain(struct meson_pinctrl *pc,
+  int pin)
+{
+   struct meson_domain *domain;
+   int i, j;
+
+   for (i = 0; i < pc->num_domains; i++) {
+   domain = &pc->domains[i];
+   for (j = 0; j < domain->data->num_banks; j++) {
+   if (pin >= domain->data->banks[j].first &&
+   pin < domain->data->banks[j].last)
+   return domain;
+

[PATCH 3/3] ARM: dts: meson8: add pinctrl and gpio nodes

[Beniamino Galvani]

Add pinctrl node to meson8.dtsi and gpio-leds node to
meson8-vega-s89e.dts

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8-vega-s89e.dts | 16 +++-
 arch/arm/boot/dts/meson8.dtsi  | 35 ++
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/meson8-vega-s89e.dts 
b/arch/arm/boot/dts/meson8-vega-s89e.dts
index 950998f..70a05c1 100644
--- a/arch/arm/boot/dts/meson8-vega-s89e.dts
+++ b/arch/arm/boot/dts/meson8-vega-s89e.dts
@@ -45,7 +45,9 @@
 
 
 /dts-v1/;
-/include/ "meson8.dtsi"
+#include "meson8.dtsi"
+#include 
+#include 
 
 / {
model = "Tronsmart Vega S89 Elite";
@@ -58,8 +60,20 @@
memory {
reg = <0x4000 0x8000>;
};
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   power {
+   gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "none";
+   };
+   };
+
 };
 
 &uart_AO {
status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart_ao_a>;
 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1f442a7..59c3af0 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -89,4 +89,39 @@
compatible = "fixed-clock";
clock-frequency = <14166>;
};
+
+   pinctrl: pinctrl@c1109880 {
+   compatible = "amlogic,meson8-pinctrl";
+   reg = <0xc1109880 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   gpio: banks@c11080b0 {
+   reg = <0xc11080b0 0x28>,
+ <0xc11080e4 0x18>,
+ <0xc1108120 0x18>,
+ <0xc1108030 0x30>;
+   reg-names = "mux", "pull-enable", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpio_ao: ao-bank@c1108030 {
+   reg = <0xc8100014 0x4>,
+ <0xc810002c 0x4>,
+ <0xc8100024 0x8>;
+   reg-names = "mux", "pull", "gpio";
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   uart_ao_a: uart_ao_a {
+   uart_ao_a {
+   pins = "uart_tx_ao_a", "uart_rx_ao_a";
+   function = "uart_ao";
+   };
+   };
+   };
+
 }; /* end of / */
-- 
1.9.1

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[PATCH 0/3] Pinctrl driver for Amlogic Meson SoCs

[Beniamino Galvani]

Hi,

this series introduces a driver for Amlogic Meson pinctrl and GPIOs,
adding the basic infrastructure for all the SoCs of the Meson family
and configuration data specific for the Meson8.

The last patch depends on a previous series that adds meson8 device
tree files and can be found here:

http://lwn.net/Articles/615033/

I tested the pinmux and GPIO functionalities on a Tronsmart Vega S89e
TV box and everything seems to work, however I'm not so familiar with
the pinctrl subsystem and thus any feedback is very welcome.

Beniamino Galvani (3):
  pinctrl: add driver for Amlogic Meson SoCs
  pinctrl: meson: add device tree bindings documentation
  ARM: dts: meson8: add pinctrl and gpio nodes

 .../devicetree/bindings/pinctrl/meson,pinctrl.txt  |  80 ++
 arch/arm/boot/dts/meson8-vega-s89e.dts |  16 +-
 arch/arm/boot/dts/meson8.dtsi  |  35 +
 arch/arm/mach-meson/Kconfig|   3 +
 drivers/pinctrl/Kconfig|   8 +
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/meson/Makefile |   2 +
 drivers/pinctrl/meson/pinctrl-meson.c  | 823 +
 drivers/pinctrl/meson/pinctrl-meson.h  | 217 ++
 drivers/pinctrl/meson/pinctrl-meson8.c | 374 ++
 include/dt-bindings/gpio/meson8-gpio.h | 155 
 11 files changed, 1713 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
 create mode 100644 drivers/pinctrl/meson/Makefile
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson8.c
 create mode 100644 include/dt-bindings/gpio/meson8-gpio.h

-- 
1.9.1

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[PATCH v2 6/7] ARM: meson: document meson8 compatible properties

[Beniamino Galvani]

Add device tree bindings documentation for Amlogic Meson8 SoCs.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/arm/amlogic.txt | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt 
b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7eece72..8fe8150 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -2,7 +2,9 @@ Amlogic MesonX device tree bindings
 ---
 
 Boards with the Amlogic Meson6 SoC shall have the following properties:
+  Required root node property:
+compatible: "amlogic,meson6"
 
-Required root node property:
-
-compatible = "amlogic,meson6";
+Boards with the Amlogic Meson8 SoC shall have the following properties:
+  Required root node property:
+compatible: "amlogic,meson8";
-- 
1.9.1

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[PATCH v2 3/7] ARM: dts: add dts for Tronsmart S89 Elite TV box

[Beniamino Galvani]

This adds a dts for the Tronsmart S89 Elite, a set-top box based on
the Amlogic S802 SoC with a 8GiB NAND flash, USB ports, 10/100 Mbps
Ethernet adapter, WiFi, HDMI and a micro SD slot.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8-vega-s89e.dts | 65 ++
 1 file changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson8-vega-s89e.dts

diff --git a/arch/arm/boot/dts/meson8-vega-s89e.dts 
b/arch/arm/boot/dts/meson8-vega-s89e.dts
new file mode 100644
index 000..950998f
--- /dev/null
+++ b/arch/arm/boot/dts/meson8-vega-s89e.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2014 Beniamino Galvani 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+/dts-v1/;
+/include/ "meson8.dtsi"
+
+/ {
+   model = "Tronsmart Vega S89 Elite";
+   compatible = "tronsmart,vega-s89e", "amlogic,meson8";
+
+   aliases {
+   serial0 = &uart_AO;
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+};
+
+&uart_AO {
+   status = "okay";
+};
-- 
1.9.1

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[PATCH v2 1/7] ARM: meson: add meson8 support

[Beniamino Galvani]

Add a MACH_MESON8 symbol and add "amlogic,meson8" to the list of
compatible strings for the Meson DT machine to support devices based
on the Meson8 family of SoCs.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/mach-meson/Kconfig | 5 +
 arch/arm/mach-meson/meson.c | 8 
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 2c1154e..b289e8e 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -10,4 +10,9 @@ config MACH_MESON6
default ARCH_MESON
select MESON6_TIMER
 
+config MACH_MESON8
+   bool "Amlogic Meson8 SoCs support"
+   default ARCH_MESON
+   select MESON6_TIMER
+
 endif
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
index 5ee064f..8f42d8f 100644
--- a/arch/arm/mach-meson/meson.c
+++ b/arch/arm/mach-meson/meson.c
@@ -16,12 +16,12 @@
 #include 
 #include 
 
-static const char * const m6_common_board_compat[] = {
+static const char * const meson_common_board_compat[] = {
"amlogic,meson6",
+   "amlogic,meson8",
NULL,
 };
 
-DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
-   .dt_compat  = m6_common_board_compat,
+DT_MACHINE_START(MESON, "Amlogic Meson platform")
+   .dt_compat  = meson_common_board_compat,
 MACHINE_END
-
-- 
1.9.1

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[PATCH v2 7/7] ARM: meson: enable L2 cache

[Beniamino Galvani]

This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson.dtsi  | 7 +++
 arch/arm/boot/dts/meson6.dtsi | 2 ++
 arch/arm/boot/dts/meson8.dtsi | 4 
 arch/arm/mach-meson/Kconfig   | 1 +
 arch/arm/mach-meson/meson.c   | 2 ++
 5 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 55feb14..7d27f12 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
 / {
interrupt-parent = <&gic>;
 
+   L2: l2-cache-controller@c420 {
+   compatible = "arm,pl310-cache";
+   reg = <0xc420 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
gic: interrupt-controller@c4301000 {
compatible = "arm,cortex-a9-gic";
reg = <0xc4301000 0x1000>,
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba4912..8b33be1 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x200>;
};
 
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x201>;
};
};
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 42e4026..1f442a7 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -58,24 +58,28 @@
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x200>;
};
 
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x201>;
};
 
cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x202>;
};
 
cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+   next-level-cache = <&L2>;
reg = <0x203>;
};
};
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b289e8e..18301dc 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
select GENERIC_IRQ_CHIP
select ARM_GIC
+   select CACHE_L2X0
 
 if ARCH_MESON
 
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
index 8f42d8f..5d6affe 100644
--- a/arch/arm/mach-meson/meson.c
+++ b/arch/arm/mach-meson/meson.c
@@ -24,4 +24,6 @@ static const char * const meson_common_board_compat[] = {
 
 DT_MACHINE_START(MESON, "Amlogic Meson platform")
.dt_compat  = meson_common_board_compat,
+   .l2c_aux_val= 0,
+   .l2c_aux_mask   = ~0,
 MACHINE_END
-- 
1.9.1

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[PATCH v2 2/7] ARM: dts: add dtsi for Amlogic Meson8 SoCs

[Beniamino Galvani]

This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8.dtsi | 88 +++
 1 file changed, 88 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson8.dtsi

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000..42e4026
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2014 Carlo Caione 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "meson.dtsi"
+
+/ {
+   model = "Amlogic Meson8 SoC";
+   compatible = "amlogic,meson8";
+
+   interrupt-parent = <&gic>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x200>;
+   };
+
+   cpu@201 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x201>;
+   };
+
+   cpu@202 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x202>;
+   };
+
+   cpu@203 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x203>;
+   };
+   };
+
+   clk81: clk@0 {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <14166>;
+   };
+}; /* end of / */
-- 
1.9.1

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[PATCH v2 4/7] of: add vendor prefix for Tronsmart

[Beniamino Galvani]

This adds Tronsmart to the list of device tree vendor prefixes.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c681434..92a1798 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -141,6 +141,7 @@ tlm Trusted Logic Mobility
 toradexToradex AG
 toshibaToshiba Corporation
 toumaz Toumaz
+tronsmart  Tronsmart
 usiUniversal Scientifc Industrial Co., Ltd.
 v3 V3 Semiconductor
 variscite  Variscite Ltd.
-- 
1.9.1

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[PATCH v2 5/7] ARM: document Tronsmart compatible properties

[Beniamino Galvani]

Document device tree bindings for Tronsmart devices.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/arm/tronsmart.txt | 7 +++
 1 file changed, 7 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tronsmart.txt

diff --git a/Documentation/devicetree/bindings/arm/tronsmart.txt 
b/Documentation/devicetree/bindings/arm/tronsmart.txt
new file mode 100644
index 000..bd29d60
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tronsmart.txt
@@ -0,0 +1,7 @@
+Tronsmart Platforms Device Tree Bindings
+---
+
+Vega S89 Elite TV box
+
+Required root node properties:
+- compatible = "tronsmart,vega-s89e";
-- 
1.9.1

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[PATCH v2 0/7] ARM: meson: add support for Meson8

[Beniamino Galvani]

Hi,

this patchset introduces support for Amlogic Meson8, which is a family
of quad-core Cortex-A9 SoCs used in tablets and set-top boxes.

Changes since v1:
 - reused the existing DT machine definition and renamed it to be more
   generic
 - added L2 cache support

Beniamino Galvani (7):
  ARM: meson: add meson8 support
  ARM: dts: add dtsi for Amlogic Meson8 SoCs
  ARM: dts: add dts for Tronsmart S89 Elite TV box
  of: add vendor prefix for Tronsmart
  ARM: document Tronsmart compatible properties
  ARM: meson: document meson8 compatible properties
  ARM: meson: enable L2 cache

 Documentation/devicetree/bindings/arm/amlogic.txt  |  8 +-
 .../devicetree/bindings/arm/tronsmart.txt  |  7 ++
 .../devicetree/bindings/vendor-prefixes.txt|  1 +
 arch/arm/boot/dts/meson.dtsi   |  7 ++
 arch/arm/boot/dts/meson6.dtsi  |  2 +
 arch/arm/boot/dts/meson8-vega-s89e.dts | 65 +++
 arch/arm/boot/dts/meson8.dtsi  | 92 ++
 arch/arm/mach-meson/Kconfig|  6 ++
 arch/arm/mach-meson/meson.c| 10 ++-
 9 files changed, 191 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tronsmart.txt
 create mode 100644 arch/arm/boot/dts/meson8-vega-s89e.dts
 create mode 100644 arch/arm/boot/dts/meson8.dtsi

-- 
1.9.1

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[PATCH v2 2/2] i2c: meson: add device tree bindings documentation

[Beniamino Galvani]

This commit adds device tree bindings documentation for the I2C bus
controller found on Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 .../devicetree/bindings/i2c/i2c-meson.txt  | 24 ++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-meson.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt 
b/Documentation/devicetree/bindings/i2c/i2c-meson.txt
new file mode 100644
index 000..682f9a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-meson.txt
@@ -0,0 +1,24 @@
+Amlogic Meson I2C controller
+
+Required properties:
+ - compatible: must be "amlogic,meson6-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+
+Optional properties:
+- clock-frequency: the desired I2C bus clock frequency in Hz; in
+  absence of this property the default value is used (100 kHz).
+
+Examples:
+
+   i2c@c8100500 {
+   compatible = "amlogic,meson6-i2c";
+   reg = <0xc8100500 0x20>;
+   interrupts = <0 92 1>;
+   clocks = <&clk81>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
-- 
1.9.1

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[PATCH v2 1/2] i2c: add support for Amlogic Meson I2C controller

[Beniamino Galvani]

This is a driver for the I2C controller found in Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani 
---
 drivers/i2c/busses/Kconfig |   7 +
 drivers/i2c/busses/Makefile|   1 +
 drivers/i2c/busses/i2c-meson.c | 492 +
 3 files changed, 500 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-meson.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2e45ae3..b8e8f63 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -530,6 +530,13 @@ config I2C_KEMPLD
  This driver can also be built as a module. If so, the module
  will be called i2c-kempld.
 
+config I2C_MESON
+   tristate "Amlogic Meson I2C controller"
+   depends on ARCH_MESON
+   help
+ If you say yes to this option, support will be included for the
+ I2C interface on the Amlogic Meson family of SoCs.
+
 config I2C_MPC
tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
depends on PPC
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..c7ed7f12 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
 obj-$(CONFIG_I2C_KEMPLD)   += i2c-kempld.o
+obj-$(CONFIG_I2C_MESON)+= i2c-meson.o
 obj-$(CONFIG_I2C_MPC)  += i2c-mpc.o
 obj-$(CONFIG_I2C_MV64XXX)  += i2c-mv64xxx.o
 obj-$(CONFIG_I2C_MXS)  += i2c-mxs.o
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
new file mode 100644
index 000..5e4f13b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -0,0 +1,492 @@
+/*
+ * I2C bus driver for Amlogic Meson SoCs
+ *
+ * Copyright (C) 2014 Beniamino Galvani 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Meson I2C register map */
+#define REG_CTRL   0x00
+#define REG_SLAVE_ADDR 0x04
+#define REG_TOK_LIST0  0x08
+#define REG_TOK_LIST1  0x0c
+#define REG_TOK_WDATA0 0x10
+#define REG_TOK_WDATA1 0x14
+#define REG_TOK_RDATA0 0x18
+#define REG_TOK_RDATA1 0x1c
+
+/* Control register fields */
+#define REG_CTRL_START BIT(0)
+#define REG_CTRL_ACK_IGNOREBIT(1)
+#define REG_CTRL_STATUSBIT(2)
+#define REG_CTRL_ERROR BIT(3)
+#define REG_CTRL_CLKDIV_SHIFT  12
+#define REG_CTRL_CLKDIV_MASK   ((BIT(10) - 1) << REG_CTRL_CLKDIV_SHIFT)
+
+#define I2C_TIMEOUT_MS 500
+#define DEFAULT_FREQ   10
+
+enum {
+   TOKEN_END = 0,
+   TOKEN_START,
+   TOKEN_SLAVE_ADDR_WRITE,
+   TOKEN_SLAVE_ADDR_READ,
+   TOKEN_DATA,
+   TOKEN_DATA_LAST,
+   TOKEN_STOP,
+};
+
+enum {
+   STATE_IDLE,
+   STATE_READ,
+   STATE_WRITE,
+   STATE_STOP,
+};
+
+/**
+ * struct meson_i2c - Meson I2C device private data
+ *
+ * @adap:  I2C adapter instance
+ * @dev:   Pointer to device structure
+ * @regs:  Base address of the device memory mapped registers
+ * @clk:   Pointer to clock structure
+ * @irq:   IRQ number
+ * @msg:   Pointer to the current I2C message
+ * @state: Current state in the driver state machine
+ * @last:  Flag set for the last message in the transfer
+ * @count: Number of bytes to be sent/received in current transfer
+ * @pos:   Current position in the send/receive buffer
+ * @error: Flag set when an error is received
+ * @lock:  To avoid race conditions between irq handler and xfer code
+ * @done:  Completion used to wait for transfer termination
+ * @frequency: Operating frequency of I2C bus clock
+ * @tokens:Sequence of tokens to be written to the device
+ * @num_tokens:Number of tokens
+ */
+struct meson_i2c {
+   struct i2c_adapter  adap;
+   struct device   *dev;
+   void __iomem*regs;
+   struct clk  *clk;
+   int irq;
+
+   struct i2c_msg  *msg;
+   int state;
+   boollast;
+   int count;
+   int pos;
+   int error;
+
+   spinlock_t  lock;
+   struct completion   done;
+   unsigned intfrequency;
+   u32 tokens[2];
+   int num_tokens;
+};
+
+static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
+  u32 val)
+{
+   u32 data;
+
+   data = readl(i2c->regs + reg);
+   data &= 

[PATCH v2 0/2] i2c: add driver for Amlogic Meson I2C controller

[Beniamino Galvani]

Hi,

this patchset adds a driver for the I2C controller available in
Amlogic Meson SoCs and has been tested on a Tronsmart Vega S89E TV box
to communicate with a Ricoh RN5T618 PMIC.

Changes since v1:
 - factored common code for token list setup

Beniamino Galvani (2):
  i2c: add support for Amlogic Meson I2C controller
  i2c: meson: add device tree bindings documentation

 .../devicetree/bindings/i2c/i2c-meson.txt  |  24 +
 drivers/i2c/busses/Kconfig |   7 +
 drivers/i2c/busses/Makefile|   1 +
 drivers/i2c/busses/i2c-meson.c | 492 +
 4 files changed, 524 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-meson.txt
 create mode 100644 drivers/i2c/busses/i2c-meson.c

-- 
1.9.1

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Re: [PATCH 1/6] ARM: meson: add meson8 machine definition

[Beniamino Galvani]

On Thu, Oct 02, 2014 at 11:28:14AM +0200, Arnd Bergmann wrote:
> On Wednesday 01 October 2014 23:29:41 Beniamino Galvani wrote:
> >  DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
> > .dt_compat  = m6_common_board_compat,
> >  MACHINE_END
> >  
> > +DT_MACHINE_START(MESON8, "Amlogic Meson8 platform")
> > +   .dt_compat  = m8_common_board_compat,
> > +MACHINE_END
> 
> One more thing: since this is a cortex-a9, don't you have to enable
> the l2x0 cache controller explicitly? I think you need a
> ".l2c_aux_mask   = ~0," entry here.

Will do, thanks.

Beniamino
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Re: [PATCH 1/6] ARM: meson: add meson8 machine definition

[Beniamino Galvani]

On Thu, Oct 02, 2014 at 11:24:54AM +0200, Arnd Bergmann wrote:
> On Wednesday 01 October 2014 23:29:41 Beniamino Galvani wrote:
> > 
> > +static const char * const m8_common_board_compat[] = {
> > +   "amlogic,meson8",
> > +   NULL,
> > +};
> > +
> >  DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
> > .dt_compat  = m6_common_board_compat,
> >  MACHINE_END
> >  
> > +DT_MACHINE_START(MESON8, "Amlogic Meson8 platform")
> > +   .dt_compat  = m8_common_board_compat,
> > +MACHINE_END
> > 
> 
> I'd just add the meson8 string to the m6_common_board_compat list and
> rename it.

>From what I've seen so far the two families are very similar and share
most of the IP cores, so a unique DT machine is a good idea.

Does the MACH_MESON8 Kconfig symbol still make sense or can I drop it
and rename MACH_MESON6 to MACH_MESON?

Beniamino

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[PATCH 1/6] ARM: meson: add meson8 machine definition

[Beniamino Galvani]

This patch adds a machine definition for Amlogic Meson8 SoCs.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/mach-meson/Kconfig | 5 +
 arch/arm/mach-meson/meson.c | 8 
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 2c1154e..b289e8e 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -10,4 +10,9 @@ config MACH_MESON6
default ARCH_MESON
select MESON6_TIMER
 
+config MACH_MESON8
+   bool "Amlogic Meson8 SoCs support"
+   default ARCH_MESON
+   select MESON6_TIMER
+
 endif
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
index 5ee064f..e95d6ae 100644
--- a/arch/arm/mach-meson/meson.c
+++ b/arch/arm/mach-meson/meson.c
@@ -21,7 +21,15 @@ static const char * const m6_common_board_compat[] = {
NULL,
 };
 
+static const char * const m8_common_board_compat[] = {
+   "amlogic,meson8",
+   NULL,
+};
+
 DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
.dt_compat  = m6_common_board_compat,
 MACHINE_END
 
+DT_MACHINE_START(MESON8, "Amlogic Meson8 platform")
+   .dt_compat  = m8_common_board_compat,
+MACHINE_END
-- 
1.9.1

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[PATCH 0/6] ARM: add machine and dts files for Amlogic Meson8

[Beniamino Galvani]

Hi,

this patchset introduces a machine definition and dts files for
Amlogic Meson8, which is a family of quad-core Cortex-A9 SoCs used in
tablets and set-top boxes.

Beniamino Galvani (6):
  ARM: meson: add meson8 machine definition
  ARM: dts: add dtsi for Amlogic Meson8 SoCs
  ARM: dts: add dts for Tronsmart S89 Elite TV box
  of: add vendor prefix for Tronsmart
  ARM: document Tronsmart compatible properties
  ARM: meson: document meson8 compatible properties

 Documentation/devicetree/bindings/arm/amlogic.txt  |  8 +-
 .../devicetree/bindings/arm/tronsmart.txt  |  7 ++
 .../devicetree/bindings/vendor-prefixes.txt|  1 +
 arch/arm/boot/dts/meson8-vega-s89e.dts | 65 
 arch/arm/boot/dts/meson8.dtsi  | 90 ++
 arch/arm/mach-meson/Kconfig|  5 ++
 arch/arm/mach-meson/meson.c|  8 ++
 7 files changed, 181 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tronsmart.txt
 create mode 100644 arch/arm/boot/dts/meson8-vega-s89e.dts
 create mode 100644 arch/arm/boot/dts/meson8.dtsi

-- 
1.9.1

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[PATCH 3/6] ARM: dts: add dts for Tronsmart S89 Elite TV box

[Beniamino Galvani]

This adds a dts for the Tronsmart S89 Elite, a set-top box based on
the Amlogic S802 SoC with a 8GiB NAND flash, USB ports, 10/100 Mbps
Ethernet adapter, WiFi, HDMI and a micro SD slot.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8-vega-s89e.dts | 65 ++
 1 file changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson8-vega-s89e.dts

diff --git a/arch/arm/boot/dts/meson8-vega-s89e.dts 
b/arch/arm/boot/dts/meson8-vega-s89e.dts
new file mode 100644
index 000..93c3dfd
--- /dev/null
+++ b/arch/arm/boot/dts/meson8-vega-s89e.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2014 Beniamino Galvani 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.   
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+/dts-v1/;
+/include/ "meson8.dtsi"
+
+/ {
+   model = "Tronsmart Vega S89 Elite";
+   compatible = "tronsmart,vega-s89e", "amlogic,meson8";
+
+   aliases {
+   serial0 = &uart_AO;
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+};
+
+&uart_AO {
+   status = "okay";
+};
-- 
1.9.1

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[PATCH 5/6] ARM: document Tronsmart compatible properties

[Beniamino Galvani]

Document device tree bindings for Tronsmart devices.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/arm/tronsmart.txt | 7 +++
 1 file changed, 7 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tronsmart.txt

diff --git a/Documentation/devicetree/bindings/arm/tronsmart.txt 
b/Documentation/devicetree/bindings/arm/tronsmart.txt
new file mode 100644
index 000..bd29d60
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tronsmart.txt
@@ -0,0 +1,7 @@
+Tronsmart Platforms Device Tree Bindings
+---
+
+Vega S89 Elite TV box
+
+Required root node properties:
+- compatible = "tronsmart,vega-s89e";
-- 
1.9.1

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[PATCH 6/6] ARM: meson: document meson8 compatible properties

[Beniamino Galvani]

Add device tree bindings documentation for Amlogic Meson8 SoCs.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/arm/amlogic.txt | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt 
b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7eece72..8fe8150 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -2,7 +2,9 @@ Amlogic MesonX device tree bindings
 ---
 
 Boards with the Amlogic Meson6 SoC shall have the following properties:
+  Required root node property:
+compatible: "amlogic,meson6"
 
-Required root node property:
-
-compatible = "amlogic,meson6";
+Boards with the Amlogic Meson8 SoC shall have the following properties:
+  Required root node property:
+compatible: "amlogic,meson8";
-- 
1.9.1

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[PATCH 4/6] of: add vendor prefix for Tronsmart

[Beniamino Galvani]

This adds Tronsmart to the list of device tree vendor prefixes.

Signed-off-by: Beniamino Galvani 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c681434..92a1798 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -141,6 +141,7 @@ tlm Trusted Logic Mobility
 toradexToradex AG
 toshibaToshiba Corporation
 toumaz Toumaz
+tronsmart  Tronsmart
 usiUniversal Scientifc Industrial Co., Ltd.
 v3 V3 Semiconductor
 variscite  Variscite Ltd.
-- 
1.9.1

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[PATCH 2/6] ARM: dts: add dtsi for Amlogic Meson8 SoCs

[Beniamino Galvani]

Add a dtsi for the Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the
frequency of clk81.

Signed-off-by: Beniamino Galvani 
---
 arch/arm/boot/dts/meson8.dtsi | 90 +++
 1 file changed, 90 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson8.dtsi

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000..7b3fc1e
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2014 Carlo Caione 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "meson.dtsi"
+
+/ {
+   model = "Amlogic Meson8 SoC";
+   compatible = "amlogic,meson8";
+
+   interrupt-parent = <&gic>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x200>;
+   };
+
+   cpu@201 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x201>;
+   };
+
+   cpu@202 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x202>;
+   };
+
+   cpu@203 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x203>;
+   };
+   };
+
+   clk81: clk@0 {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <14166>;
+   };
+}; /* end of / */
-- 
1.9.1

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Re: [PATCH v3] watchdog: add driver for Ricoh RN5T618 watchdog

[Beniamino Galvani]

On Mon, Sep 29, 2014 at 01:24:11PM +0100, Lee Jones wrote:
> On Mon, 29 Sep 2014, Beniamino Galvani wrote:
> 
> > On Mon, Sep 29, 2014 at 08:58:45AM +0100, Lee Jones wrote:
> > > I'm not sure why a) this patch was sent to me in the first place and
> > > b) why anyone would think this should go in through MFD?
> > > 
> > 
> > Hi Lee,
> > 
> > from a previous mail [1] I (wrongly) assumed that this was going
> > through the MFD tree. If this is not the case, Wim, can you pick the
> > patch?
> > 
> > Beniamino
> > 
> > [1] https://lkml.org/lkml/2014/9/4/124
> 
> Okay, I see what's happened.
> 
> So actually if there are interdependencies between this and the other
> patches in the set, which I think there are, then you should have kept
> this in the set with the others.  Sending as an independent patch is
> not the correct thing to do.
> 
> Can you resend this, as a patch-set with all of the Acks you have
> acquired please.  I will then take the set as a whole.

The original series had 4 patches:

- MFD core support
- regulator driver
- watchdog driver
- dts documentation

As explained in the submission comment, all patches except watchdog
one have already been applied (1 and 4 to MFD tree, 2 to
regulator). Only the watchdog support is missing and it doesn't have
compilation dependencies to other patches (the watchdog driver can't
be enabled without the MFD core support).

Do you want me to resend the entire patchset or should this go in
through watchdog?

Beniamino
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Re: [PATCH v3] watchdog: add driver for Ricoh RN5T618 watchdog

[Beniamino Galvani]

On Mon, Sep 29, 2014 at 08:58:45AM +0100, Lee Jones wrote:
> I'm not sure why a) this patch was sent to me in the first place and
> b) why anyone would think this should go in through MFD?
> 

Hi Lee,

from a previous mail [1] I (wrongly) assumed that this was going
through the MFD tree. If this is not the case, Wim, can you pick the
patch?

Beniamino

[1] https://lkml.org/lkml/2014/9/4/124

> > You have my Acked-by or Signbed-off-by on this one.
> > I believe this goes via the mfd tree.
> 
> Wim,
> 
> When you Ack something, you should add your full Acked-by string.
> 
> Patches should only be Signed-off(-by) when you are part of the
> distribution path i.e. when you send patches to another Maintainer
> and/or Linus.
> 
> > > This adds a driver for the watchdog timer available in Ricoh RN5T618
> > > PMIC. The device supports a programmable expiration time of 1, 8, 32
> > > or 128 seconds.
> > > 
> > > Signed-off-by: Beniamino Galvani 
> > > Reviewed-by: Guenter Roeck 
> > > ---
> > > 
> > > Hi,
> > > 
> > > this is the third version of Ricoh RN5T618 watchdog driver. The other
> > > patches of the original series adding MFD and regulator support have
> > > already been merged.
> > > 
> > > Changes since v2 (http://lwn.net/Articles/61/ ):
> > >   - rename 'heartbeat' module parameter to 'timeout'
> > >   - change parameter type to uint
> > > 
> > > Changes since v1:
> > >   - initialized heartbeat parameter to 0 instead of -1
> > >   - simplified code path in set_timeout function
> > >   - fixed module unloading
> > >   - made 'time' unsigned in struct rn5t618_wdt_map
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