RE: [v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
> -Original Message- > From: Marc Zyngier > Sent: 2021年1月28日 17:02 > To: Biwen Li (OSS) > Cc: mark.rutl...@arm.com; Leo Li ; t...@linutronix.de; > linux-kernel@vger.kernel.org; Jiafei Pan ; > linux-arm-ker...@lists.infradead.org; Ran Wang > Subject: Re: [v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to > remove call trace > > On 2021-01-28 02:37, Biwen Li (OSS) wrote: > >> -Original Message- > >> From: Marc Zyngier > >> Sent: 2021年1月27日 19:38 > >> To: Biwen Li (OSS) > >> Cc: mark.rutl...@arm.com; Leo Li ; > >> t...@linutronix.de; ja...@lakedaemon.net; > >> linux-kernel@vger.kernel.org; Jiafei Pan ; > >> linux-arm-ker...@lists.infradead.org; Ran Wang ; > >> Biwen Li > >> Subject: Re: [v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE > >> to remove call trace > >> > >> On 2021-01-27 08:58, Biwen Li wrote: > >> > From: Biwen Li > >> > > >> > Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow, ... > >> > [ 45.605239] Unbalanced IRQ 120 wake disable > >> > [ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800 > >> > irq_set_irq_wake+0x154/0x1a0 > >> > ... > >> > [ 45.645141] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--) > >> > [ 45.651144] pc : irq_set_irq_wake+0x154/0x1a0 > >> > [ 45.655497] lr : irq_set_irq_wake+0x154/0x1a0 > >> > ... > >> > [ 45.742825] Call trace: > >> > [ 45.745268] irq_set_irq_wake+0x154/0x1a0 > >> > [ 45.749278] ds3232_resume+0x38/0x50 > >> > > >> > On ls2088ardb: > >> > In suspend progress(# echo mem > /sys/power/state), > >> > > >> > pm_suspend()->suspend_devices_and_enter()->dpm_suspend()->device_susp > >> e > >> > nd() > >> > ->ds3232_suspend()->enable_irq_wake()->irq_set_irq_wake() > >> > ->set_irq_wake_real(), return -ENXIO, there get > >> > "Cannot set wakeup source" in ds3232_suspend(). > >> > > >> > In resume progress(wakeup by flextimer) > >> > dpm_resume_end()->dpm_resume() > >> > ->device_resume()->ds3232_resume() > >> > ->disable_irq_wake()->irq_set_irq_wake() > >> > ->set_irq_wake_real(), there get > >> > kernel call trace(Unbalanced IRQ 120 wake > >> > disable) > >> > >> This is again paraphrasing the stack trace instead of explaining the > >> problem it fixes. How about: > >> > >> "The ls-extirq driver doesn't implement the irq_set_wake() > >> callback, while being wake-up capable. This results in > >> ugly behaviours across suspend/resume cycles. > >> > >> Advertise this by adding IRQCHIP_SKIP_SET_WAKE to the irqchip > >> flags" > >> > >> The subject line should be fixed along the same lines, and a Fixes: > >> tag added. > > Okay, got it. Thanks. Will update in v3. > > ... and v3 still doesn't have a Fixes: tag. > > Frankly, if you can't be bothered to do this, why should I worry about your > platform being broken? Oh, sorry. Don't know how to add a fixes? Any suggestions? Thanks. > > M. > -- > Jazz is not dead. It just smells funny...
[v3] irqchip: ls-extirq: add IRQCHIP_SKIP_SET_WAKE to the irqchip flags
From: Biwen Li
The ls-extirq driver doesn't implement the irq_set_wake()
callback, while being wake-up capable. This results in
ugly behaviours across suspend/resume cycles.
Advertise this by adding IRQCHIP_SKIP_SET_WAKE to
the irqchip flags
Signed-off-by: Biwen Li
---
Change in v3:
- update description
Change in v2:
- Update description
drivers/irqchip/irq-ls-extirq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 564e6de0bd8e..3c6ed7b4744d 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -65,7 +65,7 @@ static struct irq_chip ls_extirq_chip = {
.irq_set_type = ls_extirq_set_type,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_affinity = irq_chip_set_affinity_parent,
- .flags = IRQCHIP_SET_TYPE_MASKED,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_SKIP_SET_WAKE,
};
static int
--
2.17.1
RE: [v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
> -Original Message- > From: Marc Zyngier > Sent: 2021年1月27日 19:38 > To: Biwen Li (OSS) > Cc: mark.rutl...@arm.com; Leo Li ; t...@linutronix.de; > ja...@lakedaemon.net; linux-kernel@vger.kernel.org; Jiafei Pan > ; linux-arm-ker...@lists.infradead.org; Ran Wang > ; Biwen Li > Subject: Re: [v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to > remove call trace > > On 2021-01-27 08:58, Biwen Li wrote: > > From: Biwen Li > > > > Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow, ... > > [ 45.605239] Unbalanced IRQ 120 wake disable > > [ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800 > > irq_set_irq_wake+0x154/0x1a0 > > ... > > [ 45.645141] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--) > > [ 45.651144] pc : irq_set_irq_wake+0x154/0x1a0 > > [ 45.655497] lr : irq_set_irq_wake+0x154/0x1a0 > > ... > > [ 45.742825] Call trace: > > [ 45.745268] irq_set_irq_wake+0x154/0x1a0 > > [ 45.749278] ds3232_resume+0x38/0x50 > > > > On ls2088ardb: > > In suspend progress(# echo mem > /sys/power/state), > > > pm_suspend()->suspend_devices_and_enter()->dpm_suspend()->device_suspe > > nd() > > ->ds3232_suspend()->enable_irq_wake()->irq_set_irq_wake() > > ->set_irq_wake_real(), return -ENXIO, there get > > "Cannot set wakeup source" in ds3232_suspend(). > > > > In resume progress(wakeup by flextimer) > > dpm_resume_end()->dpm_resume() > > ->device_resume()->ds3232_resume() > > ->disable_irq_wake()->irq_set_irq_wake() > > ->set_irq_wake_real(), there get > > kernel call trace(Unbalanced IRQ 120 wake > > disable) > > This is again paraphrasing the stack trace instead of explaining the problem > it > fixes. How about: > > "The ls-extirq driver doesn't implement the irq_set_wake() > callback, while being wake-up capable. This results in > ugly behaviours across suspend/resume cycles. > > Advertise this by adding IRQCHIP_SKIP_SET_WAKE to the irqchip > flags" > > The subject line should be fixed along the same lines, and a Fixes: tag added. Okay, got it. Thanks. Will update in v3. > > M. > -- > Jazz is not dead. It just smells funny...
[PATCH] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
From: Biwen Li
Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow,
...
[ 45.605239] Unbalanced IRQ 120 wake disable
[ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800
irq_set_irq_wake+0x154/0x1a0
...
[ 45.645141] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--)
[ 45.651144] pc : irq_set_irq_wake+0x154/0x1a0
[ 45.655497] lr : irq_set_irq_wake+0x154/0x1a0
...
[ 45.742825] Call trace:
[ 45.745268] irq_set_irq_wake+0x154/0x1a0
[ 45.749278] ds3232_resume+0x38/0x50
On ls2088ardb:
In suspend progress(# echo mem > /sys/power/state),
pm_suspend()->suspend_devices_and_enter()->dpm_suspend()->device_suspend()
->ds3232_suspend()->enable_irq_wake()->irq_set_irq_wake()
->set_irq_wake_real(), return -ENXIO, there get
"Cannot set wakeup source" in ds3232_suspend().
In resume progress(wakeup by flextimer)
dpm_resume_end()->dpm_resume()
->device_resume()->ds3232_resume()
->disable_irq_wake()->irq_set_irq_wake()
->set_irq_wake_real(), there get
kernel call trace(Unbalanced IRQ 120 wake
disable)
Signed-off-by: Biwen Li
---
Change in v2:
- update description
drivers/irqchip/irq-ls-extirq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 564e6de0bd8e..3c6ed7b4744d 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -65,7 +65,7 @@ static struct irq_chip ls_extirq_chip = {
.irq_set_type = ls_extirq_set_type,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_affinity = irq_chip_set_affinity_parent,
- .flags = IRQCHIP_SET_TYPE_MASKED,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_SKIP_SET_WAKE,
};
static int
--
2.17.1
[v2] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
From: Biwen Li
Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow,
...
[ 45.605239] Unbalanced IRQ 120 wake disable
[ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800
irq_set_irq_wake+0x154/0x1a0
...
[ 45.645141] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--)
[ 45.651144] pc : irq_set_irq_wake+0x154/0x1a0
[ 45.655497] lr : irq_set_irq_wake+0x154/0x1a0
...
[ 45.742825] Call trace:
[ 45.745268] irq_set_irq_wake+0x154/0x1a0
[ 45.749278] ds3232_resume+0x38/0x50
On ls2088ardb:
In suspend progress(# echo mem > /sys/power/state),
pm_suspend()->suspend_devices_and_enter()->dpm_suspend()->device_suspend()
->ds3232_suspend()->enable_irq_wake()->irq_set_irq_wake()
->set_irq_wake_real(), return -ENXIO, there get
"Cannot set wakeup source" in ds3232_suspend().
In resume progress(wakeup by flextimer)
dpm_resume_end()->dpm_resume()
->device_resume()->ds3232_resume()
->disable_irq_wake()->irq_set_irq_wake()
->set_irq_wake_real(), there get
kernel call trace(Unbalanced IRQ 120 wake
disable)
Signed-off-by: Biwen Li
---
Change in v2:
- update description
drivers/irqchip/irq-ls-extirq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 564e6de0bd8e..3c6ed7b4744d 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -65,7 +65,7 @@ static struct irq_chip ls_extirq_chip = {
.irq_set_type = ls_extirq_set_type,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_affinity = irq_chip_set_affinity_parent,
- .flags = IRQCHIP_SET_TYPE_MASKED,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_SKIP_SET_WAKE,
};
static int
--
2.17.1
RE: [PATCH] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
-Original Message- From: Marc Zyngier Sent: 2021年1月26日 22:01 To: Biwen Li (OSS) Cc: mark.rutl...@arm.com; Leo Li ; t...@linutronix.de; linux-kernel@vger.kernel.org; Jiafei Pan ; linux-arm-ker...@lists.infradead.org; Ran Wang ; Biwen Li Subject: Re: [PATCH] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace On 2021-01-26 11:00, Biwen Li wrote: > From: Biwen Li > > Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow, [useless trace] More importantly, what is the bug that you are fixing? [Biwen] Sure, will update the description. M. -- Jazz is not dead. It just smells funny...
[PATCH] irqchip: ls-extirq: add flag IRQCHIP_SKIP_SET_WAKE to remove call trace
From: Biwen Li
Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow,
[ 45.605239] Unbalanced IRQ 120 wake disable
[ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800
irq_set_irq_wake+0x154/0x1a0
[ 45.617965] Modules linked in: fsl_jr_uio caam_jr caamkeyblob_desc
crypto_engine rng_core dpaa2_caam caamhash_desc caamalg_desc crct10dif_ce
libdes caam error lm90 ina2xx
[ 45.633222] CPU: 0 PID: 1124 Comm: sh Not tainted 5.10.9 #1
[ 45.638789] Hardware name: Freescale Layerscape 2088A RDB Board (DT)
[ 45.645141] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--)
[ 45.651144] pc : irq_set_irq_wake+0x154/0x1a0
[ 45.655497] lr : irq_set_irq_wake+0x154/0x1a0
[ 45.659847] sp : 800012a83b00
[ 45.663156] x29: 800012a83b00 x28:
[ 45.668469] x27: 0008 x26: a74bd9d22cf0
[ 45.673781] x25: 000a5a1768a7 x24: a74bda672e6c
[ 45.679092] x23: x22: 62f7f2a08000
[ 45.684404] x21: ffea x20: 0078
[ 45.689715] x19: 62f7f00b3e00 x18: 0030
[ 45.695026] x17: x16: 0001
[ 45.700337] x15: 62f7f2a08460 x14:
[ 45.705648] x13: a74bda6733f8 x12: 080d
[ 45.710959] x11: 02af x10: a74bda6cb3f8
[ 45.716270] x9 : f000 x8 : a74bda6733f8
[ 45.721581] x7 : a74bda6cb3f8 x6 :
[ 45.726892] x5 : x4 :
[ 45.732203] x3 : x2 : a74bda673378
[ 45.737514] x1 : f27fea81bfee7700 x0 :
[ 45.742825] Call trace:
[ 45.745268] irq_set_irq_wake+0x154/0x1a0
[ 45.749278] ds3232_resume+0x38/0x50
[ 45.752853] dpm_run_callback.constprop.0+0x3c/0xe4
[ 45.757727] device_resume+0x88/0x180
[ 45.761385] dpm_resume+0xe8/0x220
[ 45.764782] dpm_resume_end+0x18/0x30
[ 45.768447] suspend_devices_and_enter+0x1a4/0x5a0
[ 45.773235] pm_suspend+0x2e0/0x34c
[ 45.776720] state_store+0x8c/0x110
[ 45.780205] kobj_attr_store+0x1c/0x30
[ 45.783955] sysfs_kf_write+0x48/0x60
[ 45.787613] kernfs_fop_write+0xfc/0x220
[ 45.791539] vfs_write+0xf0/0x2a4
[ 45.794849] ksys_write+0x6c/0x100
[ 45.798248] __arm64_sys_write+0x20/0x30
[ 45.802173] el0_svc_common.constprop.0+0x78/0x1a0
[ 45.806960] do_el0_svc+0x24/0x90
[ 45.810271] el0_svc+0x14/0x20
[ 45.813320] el0_sync_handler+0x1a4/0x1b0
[ 45.817326] el0_sync+0x174/0x180
[ 45.820635] ---[ end trace ae76f63f1f1791a1 ]---
Signed-off-by: Biwen Li
---
drivers/irqchip/irq-ls-extirq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 564e6de0bd8e..3c6ed7b4744d 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -65,7 +65,7 @@ static struct irq_chip ls_extirq_chip = {
.irq_set_type = ls_extirq_set_type,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_affinity = irq_chip_set_affinity_parent,
- .flags = IRQCHIP_SET_TYPE_MASKED,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_SKIP_SET_WAKE,
};
static int
--
2.17.1
RE: [v2 1/2] rtc: pcf2127: properly set flag WD_CD for rtc chips(pcf2129, pca2129)
Hi Alexandre,
Any comments?
Regards,
Biwen Li
> -Original Message-
> From: Biwen Li
> Sent: 2020年12月2日 11:19
> To: Leo Li ; alexandre.bell...@bootlin.com; Anson
> Huang ; Aisheng Dong
> Cc: linux-kernel@vger.kernel.org; Jiafei Pan ;
> linux-...@vger.kernel.org; Biwen Li
> Subject: [v2 1/2] rtc: pcf2127: properly set flag WD_CD for rtc chips(pcf2129,
> pca2129)
>
> From: Biwen Li
>
> Properly set flag WD_CD for rtc chips(pcf2129, pca2129)
>
> Signed-off-by: Biwen Li
> ---
> Change in v2:
> - set flag WD_CD according to compatible
>
> drivers/rtc/rtc-pcf2127.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index
> 03c9cb6b0b6e..a5418b657c50 100644
> --- a/drivers/rtc/rtc-pcf2127.c
> +++ b/drivers/rtc/rtc-pcf2127.c
> @@ -620,6 +620,10 @@ static int pcf2127_probe(struct device *dev, struct
> regmap *regmap,
>* Watchdog timer enabled and reset pin /RST activated when timed out.
>* Select 1Hz clock source for watchdog timer.
>* Note: Countdown timer disabled and not available.
> + * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
> + * of register watchdg_tim_ctl. The bit[6] is labeled
> + * as T. Bits labeled as T must always be written with
> + * logic 0.
>*/
> ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
>PCF2127_BIT_WD_CTL_CD1 |
> @@ -627,7 +631,8 @@ static int pcf2127_probe(struct device *dev, struct
> regmap *regmap,
>PCF2127_BIT_WD_CTL_TF1 |
>PCF2127_BIT_WD_CTL_TF0,
>PCF2127_BIT_WD_CTL_CD1 |
> - PCF2127_BIT_WD_CTL_CD0 |
> + (device_property_match_string(dev,
> "compatible",
> "nxp,pcf2127")
> + ? (PCF2127_BIT_WD_CTL_CD0) : (0)) |
>PCF2127_BIT_WD_CTL_TF1);
> if (ret) {
> dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
> --
> 2.17.1
[irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 9898a59358d7cb925f63bb77bd40224d1bc4857e Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/9898a59358d7cb925f63bb77bd40224d1bc4857e Author:Biwen Li AuthorDate:Mon, 30 Nov 2020 18:15:15 +08:00 Committer: Marc Zyngier CommitterDate: Fri, 11 Dec 2020 14:45:21 dt-bindings: interrupt-controller: update bindings for supporting more SoCs Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li Signed-off-by: Marc Zyngier Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201130101515.27431-11-biwen...@oss.nxp.com --- Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad780..4d47df1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. - interrupt-controller: Identifies the node as an interrupt controller - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG. + the SCFG or the External Interrupt Control Register (IRQCR) in + the ISC. - interrupt-map: Specifies the mapping from external interrupts to GIC interrupts. - interrupt-map-mask: Must be <0x 0>.
RE: [PATCH] gpio: mpc8xxx: resolve coverity warnings
>
> On Thu, Dec 3, 2020 at 9:07 AM Biwen Li (OSS) wrote:
> >
> > > On Thu, Dec 3, 2020 at 8:31 AM Biwen Li wrote:
> > > >
> > > > From: Biwen Li
> > > >
> > > > Resolve coverity warnings as follows,
> > > > cond_at_most: Checking gpio >= 28U implies that gpio may be up
> > > > to 27 on the false branch.
> > > > overrun-call: Overrunning callees array of size 3 by passing
> > > > argument gpio (which evaluates to 27)
> > > > in call to *mpc8xxx_gc->direction_output
> > > >
> > > > cond_at_least: Checking gpio <= 3U implies that gpio is at least 4
> > > > on
> > > > the false branch.
> > > > overrun-call: Overrunning callee's array of size 3 by passing
> > > > argument
> > > > gpio (which evaluates to 4) in call to
> > > > *mpc8xxx_gc->direction_output
> > > >
> > > > Signed-off-by: Biwen Li
> > > > ---
> > > > drivers/gpio/gpio-mpc8xxx.c | 5 +++--
> > > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpio/gpio-mpc8xxx.c
> > > > b/drivers/gpio/gpio-mpc8xxx.c index a6c2bbdcaa10..12c9a91d87b7
> > > > 100644
> > > > --- a/drivers/gpio/gpio-mpc8xxx.c
> > > > +++ b/drivers/gpio/gpio-mpc8xxx.c
> > > > @@ -3,6 +3,7 @@
> > > > *
> > > > * Copyright (C) 2008 Peter Korsgaard
> > > > * Copyright (C) 2016 Freescale Semiconductor Inc.
> > > > + * Copyright 2020 NXP
> > >
> > > A copyright notice on a two-line change is a bit too much, don't you
> > > think?
> > Okay, got it. Will remove it in v2.
> > >
> > > > *
> > > > * This file is licensed under the terms of the GNU General Public
> > > > License
> > > > * version 2. This program is licensed "as is" without any
> > > > warranty of any @@ -80,7 +81,7 @@ static int
> > > > mpc5121_gpio_dir_out(struct gpio_chip *gc, {
> > > > struct mpc8xxx_gpio_chip *mpc8xxx_gc =
> gpiochip_get_data(gc);
> > > > /* GPIO 28..31 are input only on MPC5121 */
> > > > - if (gpio >= 28)
> > > > + if (gpio >= 28U)
> > > > return -EINVAL;
> > >
> > > I don't really understand the commit message but looking at the code
> > > is even more confusing. What are you fixing here actually?
> > Try to fix code warning that generated by coverity scan tool(static
> > code analysis tool)
>
> Please explain what benefit there is to using 28U over 28. No tool is perfect,
> that's why you should try to understand what it is it's trying to fix. I
> don't see any
> reason this code could fail.
This code couldn't fail.
The variable gpio is unsigned int type, prefer to append "U" for unsigned typed
values, this makes is clearer also when comparing values and variables.
>
> Bartosz
>
> > >
> > > Bartosz
> > >
> > > >
> > > > return mpc8xxx_gc->direction_output(gc, gpio, val); @@
> > > > -91,7
> > > > +92,7 @@ static int mpc5125_gpio_dir_out(struct gpio_chip *gc, {
> > > > struct mpc8xxx_gpio_chip *mpc8xxx_gc =
> gpiochip_get_data(gc);
> > > > /* GPIO 0..3 are input only on MPC5125 */
> > > > - if (gpio <= 3)
> > > > + if (gpio <= 3U)
> > > > return -EINVAL;
> > > >
> > > > return mpc8xxx_gc->direction_output(gc, gpio, val);
> > > > --
> > > > 2.17.1
> > > >
RE: [PATCH] gpio: mpc8xxx: resolve coverity warnings
> On Thu, Dec 3, 2020 at 8:31 AM Biwen Li wrote:
> >
> > From: Biwen Li
> >
> > Resolve coverity warnings as follows,
> > cond_at_most: Checking gpio >= 28U implies that gpio may be up
> > to 27 on the false branch.
> > overrun-call: Overrunning callees array of size 3 by passing
> > argument gpio (which evaluates to 27)
> > in call to *mpc8xxx_gc->direction_output
> >
> > cond_at_least: Checking gpio <= 3U implies that gpio is at least 4 on
> > the false branch.
> > overrun-call: Overrunning callee's array of size 3 by passing argument
> > gpio (which evaluates to 4) in call to
> > *mpc8xxx_gc->direction_output
> >
> > Signed-off-by: Biwen Li
> > ---
> > drivers/gpio/gpio-mpc8xxx.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
> > index a6c2bbdcaa10..12c9a91d87b7 100644
> > --- a/drivers/gpio/gpio-mpc8xxx.c
> > +++ b/drivers/gpio/gpio-mpc8xxx.c
> > @@ -3,6 +3,7 @@
> > *
> > * Copyright (C) 2008 Peter Korsgaard
> > * Copyright (C) 2016 Freescale Semiconductor Inc.
> > + * Copyright 2020 NXP
>
> A copyright notice on a two-line change is a bit too much, don't you think?
Okay, got it. Will remove it in v2.
>
> > *
> > * This file is licensed under the terms of the GNU General Public License
> > * version 2. This program is licensed "as is" without any warranty
> > of any @@ -80,7 +81,7 @@ static int mpc5121_gpio_dir_out(struct
> > gpio_chip *gc, {
> > struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
> > /* GPIO 28..31 are input only on MPC5121 */
> > - if (gpio >= 28)
> > + if (gpio >= 28U)
> > return -EINVAL;
>
> I don't really understand the commit message but looking at the code is even
> more confusing. What are you fixing here actually?
Try to fix code warning that generated by coverity scan tool(static code
analysis tool)
>
> Bartosz
>
> >
> > return mpc8xxx_gc->direction_output(gc, gpio, val); @@ -91,7
> > +92,7 @@ static int mpc5125_gpio_dir_out(struct gpio_chip *gc, {
> > struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
> > /* GPIO 0..3 are input only on MPC5125 */
> > - if (gpio <= 3)
> > + if (gpio <= 3U)
> > return -EINVAL;
> >
> > return mpc8xxx_gc->direction_output(gc, gpio, val);
> > --
> > 2.17.1
> >
[PATCH] gpio: mpc8xxx: resolve coverity warnings
From: Biwen Li
Resolve coverity warnings as follows,
cond_at_most: Checking gpio >= 28U implies that gpio may be up
to 27 on the false branch.
overrun-call: Overrunning callees array of size 3 by passing
argument gpio (which evaluates to 27)
in call to *mpc8xxx_gc->direction_output
cond_at_least: Checking gpio <= 3U implies that gpio is at least 4 on
the false branch.
overrun-call: Overrunning callee's array of size 3 by passing argument
gpio (which evaluates to 4) in call to *mpc8xxx_gc->direction_output
Signed-off-by: Biwen Li
---
drivers/gpio/gpio-mpc8xxx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index a6c2bbdcaa10..12c9a91d87b7 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2008 Peter Korsgaard
* Copyright (C) 2016 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -80,7 +81,7 @@ static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
/* GPIO 28..31 are input only on MPC5121 */
- if (gpio >= 28)
+ if (gpio >= 28U)
return -EINVAL;
return mpc8xxx_gc->direction_output(gc, gpio, val);
@@ -91,7 +92,7 @@ static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
/* GPIO 0..3 are input only on MPC5125 */
- if (gpio <= 3)
+ if (gpio <= 3U)
return -EINVAL;
return mpc8xxx_gc->direction_output(gc, gpio, val);
--
2.17.1
[v2 1/2] rtc: pcf2127: properly set flag WD_CD for rtc chips(pcf2129, pca2129)
From: Biwen Li
Properly set flag WD_CD for rtc chips(pcf2129, pca2129)
Signed-off-by: Biwen Li
---
Change in v2:
- set flag WD_CD according to compatible
drivers/rtc/rtc-pcf2127.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 03c9cb6b0b6e..a5418b657c50 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -620,6 +620,10 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
* Watchdog timer enabled and reset pin /RST activated when timed out.
* Select 1Hz clock source for watchdog timer.
* Note: Countdown timer disabled and not available.
+* For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
+* of register watchdg_tim_ctl. The bit[6] is labeled
+* as T. Bits labeled as T must always be written with
+* logic 0.
*/
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
PCF2127_BIT_WD_CTL_CD1 |
@@ -627,7 +631,8 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
PCF2127_BIT_WD_CTL_TF1 |
PCF2127_BIT_WD_CTL_TF0,
PCF2127_BIT_WD_CTL_CD1 |
-PCF2127_BIT_WD_CTL_CD0 |
+(device_property_match_string(dev,
"compatible", "nxp,pcf2127")
+ ? (PCF2127_BIT_WD_CTL_CD0) : (0)) |
PCF2127_BIT_WD_CTL_TF1);
if (ret) {
dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
--
2.17.1
[v2 2/2] rtc: pcf2127: clear these flags TSF1, TSF2 before enabling interrupt generation
From: Biwen Li
Clear these flags TSF1, TSF2 before enabling interrupt generation
Signed-off-by: Biwen Li
---
Change in v2:
- clear flag TSF2
drivers/rtc/rtc-pcf2127.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index a5418b657c50..7e3fc70ac5f9 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -659,7 +659,7 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
/*
* Enable timestamp function and store timestamp of first trigger
-* event until TSF1 and TFS2 interrupt flags are cleared.
+* event until TSF1 and TSF2 interrupt flags are cleared.
*/
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
PCF2127_BIT_TS_CTRL_TSOFF |
@@ -671,6 +671,31 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
return ret;
}
+ /*
+* Clear TSF1 field of ctrl1 register and TSF2
+* field of ctrl2 register to clear interrupt
+* before enabling interrupt generation when
+* timestamp flag set. Unless the flag TSF1 won't
+* be cleared and get the interrupt storm.
+*/
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+PCF2127_BIT_CTRL1_TSF1,
+0);
+ if (ret) {
+ dev_err(dev, "%s: control and status register 1 (ctrl1)
failed, ret = 0x%x\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
+PCF2127_BIT_CTRL2_TSF2,
+0);
+ if (ret) {
+ dev_err(dev, "%s: control and status register 2 (ctrl2)
failed, ret = 0x%x\n",
+ __func__, ret);
+ return ret;
+ }
+
/*
* Enable interrupt generation when TSF1 or TSF2 timestamp flags
* are set. Interrupt signal is an open-drain output and can be
--
2.17.1
RE: [PATCH] rtc: pcf2127: clear the flag TSF1 before enabling interrupt generation
>
> Hi,
>
> On 01/12/2020 16:47:46+0800, Biwen Li wrote:
> > From: Biwen Li
> >
> > - clear the flag TSF1 before enabling interrupt generation
> > - properly set flag WD_CD for rtc chips(pcf2129, pca2129)
> >
>
> This change has to be a separate patch.
Sure, np. Will separate the patch in v2.
>
> > Signed-off-by: Biwen Li
> > ---
> > drivers/rtc/rtc-pcf2127.c | 21 -
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
> > index 07a5630ec841..0a45e2512258 100644
> > --- a/drivers/rtc/rtc-pcf2127.c
> > +++ b/drivers/rtc/rtc-pcf2127.c
> > @@ -601,6 +601,10 @@ static int pcf2127_probe(struct device *dev, struct
> regmap *regmap,
> > * Watchdog timer enabled and reset pin /RST activated when timed out.
> > * Select 1Hz clock source for watchdog timer.
> > * Note: Countdown timer disabled and not available.
> > +* For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
> > +* of register watchdg_tim_ctl. The bit[6] is labeled
> > +* as T. Bits labeled as T must always be written with
> > +* logic 0.
> > */
> > ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
> > PCF2127_BIT_WD_CTL_CD1 |
> > @@ -608,7 +612,7 @@ static int pcf2127_probe(struct device *dev, struct
> regmap *regmap,
> > PCF2127_BIT_WD_CTL_TF1 |
> > PCF2127_BIT_WD_CTL_TF0,
> > PCF2127_BIT_WD_CTL_CD1 |
> > -PCF2127_BIT_WD_CTL_CD0 |
> > +has_nvmem ? (PCF2127_BIT_WD_CTL_CD0) : (0) |
>
> I don't like that because has_nvmem has nothing to do with
> PCF2127_BIT_WD_CTL_CD0 and nothing guarantees that we won't ever get an
> RTC without RST but with NVRAM and that willprobbly be overlooked.
Okay, got it. Will correct it in v2.
>
> > PCF2127_BIT_WD_CTL_TF1);
> > if (ret) {
> > dev_err(dev, "%s: watchdog config (wd_ctl) failed\n",
> > __func__); @@
> > -659,6 +663,21 @@ static int pcf2127_probe(struct device *dev, struct
> regmap *regmap,
> > return ret;
> > }
> >
> > + /*
> > +* Clear TSF1 field of ctrl1 register to clear interrupt
> > +* before enabling interrupt generation when
> > +* timestamp flag set. Unless the flag TSF1 won't
> > +* be cleared and the interrupt(INT pin) is
> > +* triggered continueously.
> > +*/
> > + ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
> > +PCF2127_BIT_CTRL1_TSF1,
> > +0);
> > + if (ret) {
> > + dev_err(dev, "%s: control and status register 1 (ctrl1)
> > failed, ret =
> 0x%x\n",
> > + __func__, ret);
> > + return ret;
> > + }
>
> Doing that means ignoring timestamps taken while the system is offline.
> It also doesn't fully solve the issue because you are not clearing TSF2 here
> and
> also it never gets cleared by the driver later on so I guess you will get the
> interrupt storm once a timestamp is taken.
Okay, got it. Thanks. Will clear TSF2 flag in v2.
>
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
[PATCH] rtc: pcf2127: clear the flag TSF1 before enabling interrupt generation
From: Biwen Li
- clear the flag TSF1 before enabling interrupt generation
- properly set flag WD_CD for rtc chips(pcf2129, pca2129)
Signed-off-by: Biwen Li
---
drivers/rtc/rtc-pcf2127.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 07a5630ec841..0a45e2512258 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -601,6 +601,10 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
* Watchdog timer enabled and reset pin /RST activated when timed out.
* Select 1Hz clock source for watchdog timer.
* Note: Countdown timer disabled and not available.
+* For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
+* of register watchdg_tim_ctl. The bit[6] is labeled
+* as T. Bits labeled as T must always be written with
+* logic 0.
*/
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
PCF2127_BIT_WD_CTL_CD1 |
@@ -608,7 +612,7 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
PCF2127_BIT_WD_CTL_TF1 |
PCF2127_BIT_WD_CTL_TF0,
PCF2127_BIT_WD_CTL_CD1 |
-PCF2127_BIT_WD_CTL_CD0 |
+has_nvmem ? (PCF2127_BIT_WD_CTL_CD0) : (0) |
PCF2127_BIT_WD_CTL_TF1);
if (ret) {
dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
@@ -659,6 +663,21 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
return ret;
}
+ /*
+* Clear TSF1 field of ctrl1 register to clear interrupt
+* before enabling interrupt generation when
+* timestamp flag set. Unless the flag TSF1 won't
+* be cleared and the interrupt(INT pin) is
+* triggered continueously.
+*/
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+PCF2127_BIT_CTRL1_TSF1,
+0);
+ if (ret) {
+ dev_err(dev, "%s: control and status register 1 (ctrl1)
failed, ret = 0x%x\n",
+ __func__, ret);
+ return ret;
+ }
/*
* Enable interrupt generation when TSF1 or TSF2 timestamp flags
* are set. Interrupt signal is an open-drain output and can be
--
2.17.1
[v4 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v4:
- remove copyright to fix corrupt
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 0464b8aa4bc4..573e6659cff8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -311,6 +311,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[v4 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node
From: Biwen Li
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li
---
Change in v4:
- none
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = < 6
IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v4 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
From: Biwen Li Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li --- Change in v4: - none Change in v3: - remove robust information Change in v2: - update reg property - update compatible property .../bindings/interrupt-controller/fsl,ls-extirq.txt | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad7801e8cf..4d47df1a5c91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. - interrupt-controller: Identifies the node as an interrupt controller - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG. + the SCFG or the External Interrupt Control Register (IRQCR) in + the ISC. - interrupt-map: Specifies the mapping from external interrupts to GIC interrupts. - interrupt-map-mask: Must be <0x 0>. -- 2.17.1
[v4 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li
---
Change in v4:
- none
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..f3bab76797fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = < 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v4 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v4:
- remove copyright to fix corrupt
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 83072da6f6c6..36f3c069529c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -664,6 +664,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,lx2160a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,lx2160a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v4 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v4:
- none
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index bf72918fe545..4fdbc6468ce0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -277,6 +277,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v4 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v4:
- remove copyright to fix corrupt
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index ff5805206a28..a2fcd475088b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -220,6 +220,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v4 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node
From: Hou Zhiqiang
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang
---
Change in v4:
- none
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = < 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v4 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on ls1088ardb
Signed-off-by: Biwen Li
---
Change in v4:
- none
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..89c40d3f9a50 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -51,8 +51,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU),
active low */
+ interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.17.1
[v4 03/11] arm64: dts: ls1046a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v4:
- remove copyright to fix corrupt
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 1fa39bacff4b..4565a1fe366b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -314,6 +314,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq",
"fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[v4 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA.
- get mask value directly according to compatible property of DT
and remove confused code(bit_reverse field of struct ls_extirq_data,
no need this field for SoC LS1021A. Because the register
LS1021A_SCFGREVCR is initialized to 0x by the relative rcw)
Signed-off-by: Hou Zhiqiang
Signed-off-by: Biwen Li
---
Change in v4:
- fix warning when checking patch
- simplify code
- update commit message
Change in v3:
- cleanup code
- remove robust copyright
Change in v2:
- add despcription of bit reverse
- update copyright
drivers/irqchip/irq-ls-extirq.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 4d1179fed77c..f94f974a8764 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -18,7 +18,7 @@
struct ls_extirq_data {
struct regmap *syscon;
u32 intpcr;
- boolbit_reverse;
+ boolis_ls1021a_or_ls1043a;
u32 nirq;
struct irq_fwspec map[MAXIRQ];
};
@@ -30,7 +30,7 @@ ls_extirq_set_type(struct irq_data *data, unsigned int type)
irq_hw_number_t hwirq = data->hwirq;
u32 value, mask;
- if (priv->bit_reverse)
+ if (priv->is_ls1021a_or_ls1043a)
mask = 1U << (31 - hwirq);
else
mask = 1U << hwirq;
@@ -174,14 +174,8 @@ ls_extirq_of_init(struct device_node *node, struct
device_node *parent)
if (ret)
goto out;
- if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
- u32 revcr;
-
- ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR, );
- if (ret)
- goto out;
- priv->bit_reverse = (revcr != 0);
- }
+ priv->is_ls1021a_or_ls1043a = of_device_is_compatible(node,
"fsl,ls1021a-extirq") ||
+ of_device_is_compatible(node,
"fsl,ls1043a-extirq");
domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
_domain_ops, priv);
@@ -195,3 +189,5 @@ ls_extirq_of_init(struct device_node *node, struct
device_node *parent)
}
IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init);
--
2.17.1
RE: [EXT] Re: [v3 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
>
> On 2020-11-30 03:30, Biwen Li wrote:
> > From: Hou Zhiqiang
> >
> > Add an new IRQ chip declaration for LS1043A and LS1088A
> > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> > - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >
> > Signed-off-by: Hou Zhiqiang
> > Signed-off-by: Biwen Li
> > ---
> > Change in v3:
> > - cleanup code
> > - remove robust copyright
> >
> > Change in v2:
> > - add despcription of bit reverse
> > - update copyright
> >
> > drivers/irqchip/irq-ls-extirq.c | 17 +++--
> > 1 file changed, 7 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-ls-extirq.c
> > b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..47804ce78b21
> > 100644
> > --- a/drivers/irqchip/irq-ls-extirq.c
> > +++ b/drivers/irqchip/irq-ls-extirq.c
> > @@ -18,7 +18,7 @@
> > struct ls_extirq_data {
> > struct regmap *syscon;
> > u32 intpcr;
> > - boolbit_reverse;
> > + boolis_ls1021a_or_ls1043a;
> > u32 nirq;
> > struct irq_fwspec map[MAXIRQ];
> > };
> > @@ -30,7 +30,7 @@ ls_extirq_set_type(struct irq_data *data, unsigned
> > int type)
> > irq_hw_number_t hwirq = data->hwirq;
> > u32 value, mask;
> >
> > - if (priv->bit_reverse)
> > + if (priv->is_ls1021a_or_ls1043a)
> > mask = 1U << (31 - hwirq);
> > else
> > mask = 1U << hwirq;
> > @@ -174,14 +174,9 @@ ls_extirq_of_init(struct device_node *node,
> > struct device_node *parent)
> > if (ret)
> > goto out;
> >
> > - if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
> > - u32 revcr;
> > -
> > - ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR,
> );
> > - if (ret)
> > - goto out;
> > - priv->bit_reverse = (revcr != 0);
> > - }
>
> This isn't explained in the commit message. You are changing the way you infer
> some properties, and that's not innocent. Please describe all important
> changes
> in the commit message.
Sure, will update commit message for this.
>
> > + if (of_device_is_compatible(node, "fsl,ls1021a-extirq") || \
>
> Spurious trailing \?
Don't need it, will remove it in v4.
>
> > + of_device_is_compatible(node, "fsl,ls1043a-extirq"))
> > + priv->is_ls1021a_or_ls1043a = true;
>
> Which is better written as:
>
> priv->is_ls1021a_or_ls1043a = (of_device_is_compatible(node,
> "fsl,ls1021a-extirq") ||
>
> of_device_is_compatible(node, "fsl,ls1043a-extirq"));
Sure, np. Will update it in v4.
> >
> > domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq,
> node,
> > _domain_ops, priv);
> @@
> > -195,3 +190,5 @@ ls_extirq_of_init(struct device_node *node, struct
> > device_node *parent) }
> >
> > IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq",
> > ls_extirq_of_init);
> > +IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq",
> > ls_extirq_of_init);
> > +IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq",
> > ls_extirq_of_init);
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
RE: [v10] i2c: imx: support slave mode for imx I2C driver
> >
> > The patch supports slave mode for imx I2C driver
> >
> > Signed-off-by: Biwen Li
>
> Thank you for your work!
>
> Acked-by: Oleksij Rempel
>
> @Wolfram, Christian Eggers I2SR_IAL patches should go before this one.
Hi Wolfram,
Any progress?
Regards,
Biwen Li
>
> > ---
> > Change in v10:
> > - totally remove CONFIG_I2C_SLAVE
> > - replace api with i2c_imx_clart_irq()
> > - remove robust code
> > - place pm_runtime_get in i2c_imx_slave_init()
> > to i2c_imx_reg_slave()
> > - apply the patch on top of this patch set:
> > [PATCH v6 0/3] i2c: imx: Fix handling of arbitration loss
> > https://lkml.org/lkml/2020/10/9/407
> >
> > Change in v9:
> > - remove #ifdef after select I2C_SLAVE by default
> >
> > Change in v8:
> > - fix build issue
> >
> > Change in v7:
> > - support auto switch mode between master and slave
> > - enable interrupt when idle in slave mode
> > - remove #ifdef
> >
> > Change in v6:
> > - delete robust logs and comments
> > - not read status register again in master isr.
> >
> > Change in v5:
> > - fix a bug that cannot determine in what mode(master mode or
> > slave mode)
> >
> > Change in v4:
> > - add MACRO CONFIG_I2C_SLAVE to fix compilation issue
> >
> > Change in v3:
> > - support layerscape and i.mx platform
> >
> > Change in v2:
> > - remove MACRO CONFIG_I2C_SLAVE
> >
> > drivers/i2c/busses/Kconfig | 1 +
> > drivers/i2c/busses/i2c-imx.c | 219
> > +++
> > 2 files changed, 196 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index a97a9d058198..e2ad62481f25 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -675,6 +675,7 @@ config I2C_IMG
> > config I2C_IMX
> > tristate "IMX I2C interface"
> > depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE
> > + select I2C_SLAVE
> > help
> > Say Y here if you want to use the IIC bus controller on
> > the Freescale i.MX/MXC, Layerscape or ColdFire processors.
> > diff --git a/drivers/i2c/busses/i2c-imx.c
> > b/drivers/i2c/busses/i2c-imx.c index e6f8d6e45a15..a8e8af57e33f 100644
> > --- a/drivers/i2c/busses/i2c-imx.c
> > +++ b/drivers/i2c/busses/i2c-imx.c
> > @@ -17,6 +17,7 @@
> > * Copyright (C) 2008 Darius Augulis
> > *
> > * Copyright 2013 Freescale Semiconductor, Inc.
> > + * Copyright 2020 NXP
> > *
> > */
> >
> > @@ -73,6 +74,11 @@
> > #define IMX_I2C_I2SR 0x03/* i2c status */
> > #define IMX_I2C_I2DR 0x04/* i2c transfer data */
> >
> > +/*
> > + * All of the layerscape series SoCs support IBIC register.
> > + */
> > +#define IMX_I2C_IBIC 0x05/* i2c bus interrupt config */
> > +
> > #define IMX_I2C_REGSHIFT 2
> > #define VF610_I2C_REGSHIFT 0
> >
> > @@ -91,6 +97,7 @@
> > #define I2CR_MSTA 0x20
> > #define I2CR_IIEN 0x40
> > #define I2CR_IEN 0x80
> > +#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
> >
> > /* register bits different operating codes definition:
> > * 1) I2SR: Interrupt flags clear operation differ between SoCs:
> > @@ -201,6 +208,7 @@ struct imx_i2c_struct {
> > struct pinctrl_state *pinctrl_pins_gpio;
> >
> > struct imx_i2c_dma *dma;
> > + struct i2c_client *slave;
> > };
> >
> > static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -265,6
> > +273,11 @@ static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
> > return i2c_imx->hwdata->devtype == IMX1_I2C; }
> >
> > +static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) {
> > + return i2c_imx->hwdata->devtype == VF610_I2C; }
> > +
> > static inline void imx_i2c_write_reg(unsigned int val,
> > struct imx_i2c_struct *i2c_imx, unsigned int reg) { @@ -277,6
> > +290,27 @@ static inline unsigned char imx_i2c_read_reg(struct
> imx_i2c_struct *i2c_imx,
> > return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); }
> >
> > +static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx,
> > +unsigned int bits) {
> > + unsigned int temp;
> > +
> > + /*
> > +* i2sr_clr_opcode is the value to cl
[v3 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..f3bab76797fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = < 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v3 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
From: Biwen Li Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li --- Change in v3: - remove robust information Change in v2: - update reg property - update compatible property .../bindings/interrupt-controller/fsl,ls-extirq.txt | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad7801e8cf..4d47df1a5c91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. - interrupt-controller: Identifies the node as an interrupt controller - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG. + the SCFG or the External Interrupt Control Register (IRQCR) in + the ISC. - interrupt-map: Specifies the mapping from external interrupts to GIC interrupts. - interrupt-map-mask: Must be <0x 0>. -- 2.17.1
[v3 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index d247e4228d60..095298a84f4e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -664,6 +664,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,lx2160a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,lx2160a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v3 03/11] arm64: dts: ls1046a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..dff3ee84c294 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -314,6 +314,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq",
"fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[v3 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node
From: Biwen Li
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = < 6
IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v3 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..f75aa2ce4e2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -154,6 +154,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v3 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..12fe8f079c28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -206,6 +206,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v3 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node
From: Hou Zhiqiang
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang
---
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = < 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v3 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on ls1088ardb
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..89c40d3f9a50 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -51,8 +51,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU),
active low */
+ interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.17.1
[v3 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v3:
- none
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..38a6d951ecc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -311,6 +311,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[v3 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
Signed-off-by: Hou Zhiqiang
Signed-off-by: Biwen Li
---
Change in v3:
- cleanup code
- remove robust copyright
Change in v2:
- add despcription of bit reverse
- update copyright
drivers/irqchip/irq-ls-extirq.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 4d1179fed77c..47804ce78b21 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -18,7 +18,7 @@
struct ls_extirq_data {
struct regmap *syscon;
u32 intpcr;
- boolbit_reverse;
+ boolis_ls1021a_or_ls1043a;
u32 nirq;
struct irq_fwspec map[MAXIRQ];
};
@@ -30,7 +30,7 @@ ls_extirq_set_type(struct irq_data *data, unsigned int type)
irq_hw_number_t hwirq = data->hwirq;
u32 value, mask;
- if (priv->bit_reverse)
+ if (priv->is_ls1021a_or_ls1043a)
mask = 1U << (31 - hwirq);
else
mask = 1U << hwirq;
@@ -174,14 +174,9 @@ ls_extirq_of_init(struct device_node *node, struct
device_node *parent)
if (ret)
goto out;
- if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
- u32 revcr;
-
- ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR, );
- if (ret)
- goto out;
- priv->bit_reverse = (revcr != 0);
- }
+ if (of_device_is_compatible(node, "fsl,ls1021a-extirq") || \
+ of_device_is_compatible(node, "fsl,ls1043a-extirq"))
+ priv->is_ls1021a_or_ls1043a = true;
domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
_domain_ops, priv);
@@ -195,3 +190,5 @@ ls_extirq_of_init(struct device_node *node, struct
device_node *parent)
}
IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init);
--
2.17.1
RE: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> > > >>> Where did you get this information that the register on LS1043 > > > >>> and > > > >>> LS1046 is bit reversed? I cannot find such information in the RM. > > > >>> And does this mean all other SCFG registers are also bit reversed? > > > >>> If this is some information that is not covered by the RM, we > > > >>> probably should clarify it in the code and the commit message. > > > >> Hi Leo, > > > >> > > > >> I directly use the same logic to write the bit(field IRQ0~11INTP) > > > >> of the register SCFG_INTPCR in LS1043A and LS1046A. > > > >> Such as, > > > >> if I want to control the polarity of IRQ0(field IRQ0INTP, IRQ0 is > > > >> active low) of LS1043A/LS1046A, then I just need write a value 1 > > > >> << (31 - 0) > > > to it. > > > >> The logic depends on register's definition in LS1043A/LS1046A's RM. > > > > > > > > Ok. The SCFG_SCFGREVCR seems to be a one-off fixup only existed > > > > on > > > LS1021. And it is mandatory to be bit_reversed according to the RM > > > which is already taken care of in the RCW. So the bit reversed case > > > should be the only case supported otherwise a lot of other places > > > for SCFG access should be failed. > > > > > > > > I think we should remove the bit_reverse thing all together from > > > > the driver > > > for good. This will prevent future confusion. Rasmus, what do you think? > > > > > > Yes, all the ls1021a-derived boards I know of do have something like > > > > > > # Initialize bit reverse of SCFG registers > > > 09570200 > > > > > > in their pre-boot-loader config file. And yes, the RM does say > > > > > > This register must be written 0x_ as a part of > > > initialization sequence before writing to any other SCFG > > > register. > > > > > > but nowhere does it say "or else...", nor a little honest addendum > > > "because we accidentally released broken silicon with this > > > misfeature _and_ wrong POR value". > > > > Yeah. I do think they messed up at the beginning when trying to integrate > the big endian registers on little endian core. It is good that we are doing > it > correctly in later SoCs. > > > > > > > > Can we have an official statement from NXP stating that SCFGREVCR is > > > a hardware design bug? And can you send it through a time-machine so > > > I had it three years ago avoiding the whole "fsl,bit-reverse > > > device-tree-property, no, read the register if you're on a ls1021a and > > > decide" > hullabaloo. > > > > I'm not sure if it is possible to update the related documents right now > > for this. > But definitely it was not your fault to have introduced this in the driver > due to > the confusion from document. My suggestion to remove it is just to prevent > this from causing more confusions in the future as this driver is used on more > SoCs. > > Hi Biwen, > > Would you send a new version of this patch? Thanks. Hi Leo, sure, np. > > Regards, > Leo
[v10] i2c: imx: support slave mode for imx I2C driver
From: Biwen Li
The patch supports slave mode for imx I2C driver
Signed-off-by: Biwen Li
---
Change in v10:
- totally remove CONFIG_I2C_SLAVE
- replace api with i2c_imx_clart_irq()
- remove robust code
- place pm_runtime_get in i2c_imx_slave_init()
to i2c_imx_reg_slave()
- apply the patch on top of this patch set:
[PATCH v6 0/3] i2c: imx: Fix handling of arbitration loss
https://lkml.org/lkml/2020/10/9/407
Change in v9:
- remove #ifdef after select I2C_SLAVE by default
Change in v8:
- fix build issue
Change in v7:
- support auto switch mode between master and slave
- enable interrupt when idle in slave mode
- remove #ifdef
Change in v6:
- delete robust logs and comments
- not read status register again in master isr.
Change in v5:
- fix a bug that cannot determine in what mode(master mode or
slave mode)
Change in v4:
- add MACRO CONFIG_I2C_SLAVE to fix compilation issue
Change in v3:
- support layerscape and i.mx platform
Change in v2:
- remove MACRO CONFIG_I2C_SLAVE
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-imx.c | 219 +++
2 files changed, 196 insertions(+), 24 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a97a9d058198..e2ad62481f25 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -675,6 +675,7 @@ config I2C_IMG
config I2C_IMX
tristate "IMX I2C interface"
depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE
+ select I2C_SLAVE
help
Say Y here if you want to use the IIC bus controller on
the Freescale i.MX/MXC, Layerscape or ColdFire processors.
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index e6f8d6e45a15..a8e8af57e33f 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -17,6 +17,7 @@
* Copyright (C) 2008 Darius Augulis
*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
*/
@@ -73,6 +74,11 @@
#define IMX_I2C_I2SR 0x03/* i2c status */
#define IMX_I2C_I2DR 0x04/* i2c transfer data */
+/*
+ * All of the layerscape series SoCs support IBIC register.
+ */
+#define IMX_I2C_IBIC 0x05/* i2c bus interrupt config */
+
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
@@ -91,6 +97,7 @@
#define I2CR_MSTA 0x20
#define I2CR_IIEN 0x40
#define I2CR_IEN 0x80
+#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
/* register bits different operating codes definition:
* 1) I2SR: Interrupt flags clear operation differ between SoCs:
@@ -201,6 +208,7 @@ struct imx_i2c_struct {
struct pinctrl_state *pinctrl_pins_gpio;
struct imx_i2c_dma *dma;
+ struct i2c_client *slave;
};
static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -265,6 +273,11 @@ static inline int is_imx1_i2c(struct imx_i2c_struct
*i2c_imx)
return i2c_imx->hwdata->devtype == IMX1_I2C;
}
+static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
+{
+ return i2c_imx->hwdata->devtype == VF610_I2C;
+}
+
static inline void imx_i2c_write_reg(unsigned int val,
struct imx_i2c_struct *i2c_imx, unsigned int reg)
{
@@ -277,6 +290,27 @@ static inline unsigned char imx_i2c_read_reg(struct
imx_i2c_struct *i2c_imx,
return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
}
+static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int
bits)
+{
+ unsigned int temp;
+
+ /*
+* i2sr_clr_opcode is the value to clear all interrupts. Here we want to
+* clear only , so we write ~i2sr_clr_opcode with just
+* toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
+*/
+ temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
+}
+
+/* Set up i2c controller register and i2c status register to default value. */
+static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
+{
+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
+ i2c_imx, IMX_I2C_I2CR);
+ i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
+}
+
/* Functions for DMA support */
static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
dma_addr_t phy_addr)
@@ -412,19 +446,6 @@ static void i2c_imx_dma_free(struct imx_i2c_struct
*i2c_imx)
dma->chan_using = NULL;
}
-static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int
bits)
-{
- unsigned int temp;
-
- /*
-* i2sr_clr_opcode is the value to clear all interrupts. Here we want to
-* clear only , so we write ~i2sr_clr_op
RE: [v9 1/2] i2c: imx: support slave mode for imx I2C driver
> Hi,
>
> On Mon, Nov 02, 2020 at 04:21:01PM +0800, Biwen Li wrote:
> > From: Biwen Li
> >
> > The patch supports slave mode for imx I2C driver
> >
> > Signed-off-by: Biwen Li
> > ---
> > Change in v9:
> > - remove #ifdef after select I2C_SLAVE by default
> >
> > Change in v8:
> > - fix build issue
> >
> > Change in v7:
> > - support auto switch mode between master and slave
> > - enable interrupt when idle in slave mode
> > - remove #ifdef
> >
> > Change in v6:
> > - delete robust logs and comments
> > - not read status register again in master isr.
> >
> > Change in v5:
> > - fix a bug that cannot determine in what mode(master mode or
> > slave mode)
> >
> > Change in v4:
> > - add MACRO CONFIG_I2C_SLAVE to fix compilation issue
> >
> > Change in v3:
> > - support layerscape and i.mx platform
> >
> > Change in v2:
> > - remove MACRO CONFIG_I2C_SLAVE
> >
> > drivers/i2c/busses/i2c-imx.c | 213
> > ---
> > 1 file changed, 199 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-imx.c
> > b/drivers/i2c/busses/i2c-imx.c index c98529c76348..098e2c8a0fc7 100644
> > --- a/drivers/i2c/busses/i2c-imx.c
> > +++ b/drivers/i2c/busses/i2c-imx.c
> > @@ -17,6 +17,7 @@
> > * Copyright (C) 2008 Darius Augulis
> > *
> > * Copyright 2013 Freescale Semiconductor, Inc.
> > + * Copyright 2020 NXP
> > *
> > */
> >
> > @@ -72,6 +73,7 @@
> > #define IMX_I2C_I2CR 0x02/* i2c control */
> > #define IMX_I2C_I2SR 0x03/* i2c status */
> > #define IMX_I2C_I2DR 0x04/* i2c transfer data */
> > +#define IMX_I2C_IBIC 0x05/* i2c transfer data */
>
> This register is not documented in the imx6sdl or imx8mm. Which chip
> support this register? If all, please provide more descriptive and correct
> comment "i2c transfer data" seems to be just copy/paste artifact.
All of the layerscape series SoCs support this register.
>
> >
> > #define IMX_I2C_REGSHIFT 2
> > #define VF610_I2C_REGSHIFT 0
> > @@ -91,6 +93,7 @@
> > #define I2CR_MSTA 0x20
> > #define I2CR_IIEN 0x40
> > #define I2CR_IEN 0x80
> > +#define IBIC_BIIE 0x80 // Bus idle interrupt enable
>
> Please use C style comments.
Sure, np.
>
> If it is "Bus idle interrupt enable", then we should handle this interrupt
> some
> how?
Yes, have dealt with the idle interrupt in i2c_imx_slave_isr(), as follows,
} else if (!(ctl & I2CR_MTX)) { /* Receive mode */
if (status & I2SR_IBB) { /* No STOP signal detected */
value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_WRITE_RECEIVED, );
} else { /* STOP signal is detected */
dev_dbg(_imx->adapter.dev,
"STOP signal detected");
i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, );
}
>
> >
> > /* register bits different operating codes definition:
> > * 1) I2SR: Interrupt flags clear operation differ between SoCs:
> > @@ -201,6 +204,7 @@ struct imx_i2c_struct {
> > struct pinctrl_state *pinctrl_pins_gpio;
> >
> > struct imx_i2c_dma *dma;
> > + struct i2c_client *slave;
> > };
> >
> > static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -277,6
> > +281,14 @@ static inline unsigned char imx_i2c_read_reg(struct
> imx_i2c_struct *i2c_imx,
> > return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); }
> >
> > +/* Set up i2c controller register and i2c status register to default
> > +value. */ static void i2c_imx_reset_regs(struct imx_i2c_struct
> > +*i2c_imx) {
> > + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
> > + i2c_imx, IMX_I2C_I2CR);
> > + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> > +IMX_I2C_I2SR);
>
> i.MX and Vybrid have different IMX_I2C_I2SR logic. w1c vs w0c.
Yes, the field i2sr_clr_opcode resolved the differentiation.
>
> Please apply your patches on top of this patch set:
> https://lkml.org/lkml/2020/10/2/607
Okay, np.
>
> > +}
> > +
> > /* Functions for DMA support */
> > static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
> >
RE: [v9 2/2] i2c: imx: select I2C_SLAVE by default
> Hi, > > it makes no sense to have separate patch for it Okay, got it. I will merge it. > > On Mon, Nov 02, 2020 at 04:21:02PM +0800, Biwen Li wrote: > > From: Biwen Li > > > > Select I2C_SLAVE by default > > > > Signed-off-by: Biwen Li > > --- > > Change in v9: > > - none > > > > drivers/i2c/busses/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig > > index a4f473ef4e5c..d3d9a61db76e 100644 > > --- a/drivers/i2c/busses/Kconfig > > +++ b/drivers/i2c/busses/Kconfig > > @@ -675,6 +675,7 @@ config I2C_IMG > > config I2C_IMX > > tristate "IMX I2C interface" > > depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE > > + select I2C_SLAVE > > help > > Say Y here if you want to use the IIC bus controller on > > the Freescale i.MX/MXC, Layerscape or ColdFire processors. > > -- > > 2.17.1 > > > > > > -- > Pengutronix e.K. | > | > Steuerwalder Str. 21 | http://www.pengutronix.de/ > | > 31137 Hildesheim, Germany | Phone: > +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: > +49-5121-206917- |
RE: [v9 1/2] i2c: imx: support slave mode for imx I2C driver
Hi Oleksij, Wolfram,
Any comments?
Regards,
Biwen Li
> From: Biwen Li
>
> The patch supports slave mode for imx I2C driver
>
> Signed-off-by: Biwen Li
> ---
> Change in v9:
> - remove #ifdef after select I2C_SLAVE by default
>
> Change in v8:
> - fix build issue
>
> Change in v7:
> - support auto switch mode between master and slave
> - enable interrupt when idle in slave mode
> - remove #ifdef
>
> Change in v6:
> - delete robust logs and comments
> - not read status register again in master isr.
>
> Change in v5:
> - fix a bug that cannot determine in what mode(master mode or
> slave mode)
>
> Change in v4:
> - add MACRO CONFIG_I2C_SLAVE to fix compilation issue
>
> Change in v3:
> - support layerscape and i.mx platform
>
> Change in v2:
> - remove MACRO CONFIG_I2C_SLAVE
>
> drivers/i2c/busses/i2c-imx.c | 213
> ---
> 1 file changed, 199 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index
> c98529c76348..098e2c8a0fc7 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -17,6 +17,7 @@
> * Copyright (C) 2008 Darius Augulis
> *
> * Copyright 2013 Freescale Semiconductor, Inc.
> + * Copyright 2020 NXP
> *
> */
>
> @@ -72,6 +73,7 @@
> #define IMX_I2C_I2CR 0x02/* i2c control */
> #define IMX_I2C_I2SR 0x03/* i2c status */
> #define IMX_I2C_I2DR 0x04/* i2c transfer data */
> +#define IMX_I2C_IBIC 0x05/* i2c transfer data */
>
> #define IMX_I2C_REGSHIFT 2
> #define VF610_I2C_REGSHIFT 0
> @@ -91,6 +93,7 @@
> #define I2CR_MSTA0x20
> #define I2CR_IIEN0x40
> #define I2CR_IEN 0x80
> +#define IBIC_BIIE0x80 // Bus idle interrupt enable
>
> /* register bits different operating codes definition:
> * 1) I2SR: Interrupt flags clear operation differ between SoCs:
> @@ -201,6 +204,7 @@ struct imx_i2c_struct {
> struct pinctrl_state *pinctrl_pins_gpio;
>
> struct imx_i2c_dma *dma;
> + struct i2c_client *slave;
> };
>
> static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -277,6 +281,14
> @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct
> *i2c_imx,
> return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); }
>
> +/* Set up i2c controller register and i2c status register to default
> +value. */ static void i2c_imx_reset_regs(struct imx_i2c_struct
> +*i2c_imx) {
> + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
> + i2c_imx, IMX_I2C_I2CR);
> + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> +IMX_I2C_I2SR); }
> +
> /* Functions for DMA support */
> static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
> dma_addr_t phy_addr)
> @@ -614,20 +626,188 @@ static void i2c_imx_stop(struct imx_i2c_struct
> *i2c_imx, bool atomic)
> imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); }
>
> +/*
> + * Enable bus idle interrupts
> + * Note: IBIC register will be cleared after disabled i2c module.
> + */
> +static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) {
> + unsigned int temp;
> +
> + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
> + temp |= IBIC_BIIE;
> + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); }
> +
> +static void i2c_imx_clr_if_bit(unsigned int status, struct
> +imx_i2c_struct *i2c_imx) {
> + status &= ~I2SR_IIF;
> + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> +
> +/* Clear arbitration lost bit */
> +static void i2c_imx_clr_al_bit(unsigned int status, struct
> +imx_i2c_struct *i2c_imx) {
> + status &= ~I2SR_IAL;
> + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
> + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> +
> +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
> + unsigned int status, unsigned int ctl) {
> + u8 value;
> +
> + if (status & I2SR_IAL) { /* Arbitration lost */
> + i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
> + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
> + if (status & I2SR_SRW) { /* Master wants to read from us*/
> + dev_dbg(_imx->adapter.dev, "read requested");
> + i2c_slave
[v9 2/2] i2c: imx: select I2C_SLAVE by default
From: Biwen Li Select I2C_SLAVE by default Signed-off-by: Biwen Li --- Change in v9: - none drivers/i2c/busses/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a4f473ef4e5c..d3d9a61db76e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -675,6 +675,7 @@ config I2C_IMG config I2C_IMX tristate "IMX I2C interface" depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE + select I2C_SLAVE help Say Y here if you want to use the IIC bus controller on the Freescale i.MX/MXC, Layerscape or ColdFire processors. -- 2.17.1
[v9 1/2] i2c: imx: support slave mode for imx I2C driver
From: Biwen Li
The patch supports slave mode for imx I2C driver
Signed-off-by: Biwen Li
---
Change in v9:
- remove #ifdef after select I2C_SLAVE by default
Change in v8:
- fix build issue
Change in v7:
- support auto switch mode between master and slave
- enable interrupt when idle in slave mode
- remove #ifdef
Change in v6:
- delete robust logs and comments
- not read status register again in master isr.
Change in v5:
- fix a bug that cannot determine in what mode(master mode or
slave mode)
Change in v4:
- add MACRO CONFIG_I2C_SLAVE to fix compilation issue
Change in v3:
- support layerscape and i.mx platform
Change in v2:
- remove MACRO CONFIG_I2C_SLAVE
drivers/i2c/busses/i2c-imx.c | 213 ---
1 file changed, 199 insertions(+), 14 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index c98529c76348..098e2c8a0fc7 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -17,6 +17,7 @@
* Copyright (C) 2008 Darius Augulis
*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
*/
@@ -72,6 +73,7 @@
#define IMX_I2C_I2CR 0x02/* i2c control */
#define IMX_I2C_I2SR 0x03/* i2c status */
#define IMX_I2C_I2DR 0x04/* i2c transfer data */
+#define IMX_I2C_IBIC 0x05/* i2c transfer data */
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
@@ -91,6 +93,7 @@
#define I2CR_MSTA 0x20
#define I2CR_IIEN 0x40
#define I2CR_IEN 0x80
+#define IBIC_BIIE 0x80 // Bus idle interrupt enable
/* register bits different operating codes definition:
* 1) I2SR: Interrupt flags clear operation differ between SoCs:
@@ -201,6 +204,7 @@ struct imx_i2c_struct {
struct pinctrl_state *pinctrl_pins_gpio;
struct imx_i2c_dma *dma;
+ struct i2c_client *slave;
};
static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -277,6 +281,14 @@ static inline unsigned char imx_i2c_read_reg(struct
imx_i2c_struct *i2c_imx,
return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
}
+/* Set up i2c controller register and i2c status register to default value. */
+static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
+{
+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
+ i2c_imx, IMX_I2C_I2CR);
+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
IMX_I2C_I2SR);
+}
+
/* Functions for DMA support */
static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
dma_addr_t phy_addr)
@@ -614,20 +626,188 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx,
bool atomic)
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
}
+/*
+ * Enable bus idle interrupts
+ * Note: IBIC register will be cleared after disabled i2c module.
+ */
+static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
+{
+ unsigned int temp;
+
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
+ temp |= IBIC_BIIE;
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
+}
+
+static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IIF;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+/* Clear arbitration lost bit */
+static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IAL;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
+unsigned int status, unsigned int ctl)
+{
+ u8 value;
+
+ if (status & I2SR_IAL) { /* Arbitration lost */
+ i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
+ } else if (status & I2SR_IAAS) { /* Addressed as a slave */
+ if (status & I2SR_SRW) { /* Master wants to read from us*/
+ dev_dbg(_imx->adapter.dev, "read requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_READ_REQUESTED, );
+
+ /* Slave transmit */
+ ctl |= I2CR_MTX;
+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
+
+ /* Send data */
+ imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
+ } else { /* Master wants to write to us */
+ dev_dbg(_imx->adapter.dev, "write requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_WRITE_R
RE: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> > > > > > Caution: EXT Email > > > > > > On 27/10/2020 05.46, Biwen Li wrote: > > > > From: Hou Zhiqiang > > > > > > > > Add an new IRQ chip declaration for LS1043A and LS1088A > > > > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. > SCFG_INTPCR[31:0] > > > > of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit > > > > reverse) > > > > > > s/defaultly/by default/ I suppose. But what does that mean? Is it > > > still configurable, just now through some undocumented register? If > > > that register still exists, does it now have a reset value of > > > all-ones as opposed to the ls1021 case? If it's not configurable, > > > then describing the situation as "by default" is confusing and > > > wrong, it should just say "On LS1043A, LS1046A, SCFG_INTPCR is > > > stored/read bit- > > reversed." > > Okay, got it. Will update it in v3. Thanks. > > Hi Biwen, > > Where did you get this information that the register on LS1043 and LS1046 is > bit > reversed? I cannot find such information in the RM. And does this mean all > other SCFG registers are also bit reversed? If this is some information that > is > not covered by the RM, we probably should clarify it in the code and the > commit > message. Hi Leo, I directly use the same logic to write the bit(field IRQ0~11INTP) of the register SCFG_INTPCR in LS1043A and LS1046A. Such as, if I want to control the polarity of IRQ0(field IRQ0INTP, IRQ0 is active low) of LS1043A/LS1046A, then I just need write a value 1 << (31 - 0) to it. The logic depends on register's definition in LS1043A/LS1046A's RM. Regards, Biwen > > Regards, > Leo > > > > > > > > > > > - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > > > > > > > > Signed-off-by: Hou Zhiqiang > > > > Signed-off-by: Biwen Li > > > > --- > > > > Change in v2: > > > > - add despcription of bit reverse > > > > - update copyright > > > > > > > > drivers/irqchip/irq-ls-extirq.c | 10 +- > > > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/irqchip/irq-ls-extirq.c > > > > b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..9587bc2607fc > > > > 100644 > > > > --- a/drivers/irqchip/irq-ls-extirq.c > > > > +++ b/drivers/irqchip/irq-ls-extirq.c > > > > @@ -1,5 +1,8 @@ > > > > // SPDX-License-Identifier: GPL-2.0 > > > > - > > > > +/* > > > > + * Author: Rasmus Villemoes > > > > > > If I wanted my name splattered all over the files I touch or add, > > > I'd add it myself, TYVM. The git history is plenty fine for > > > recording authorship as far as I'm concerned, and I absolutely abhor > > > having to skip over any kind of legalese boilerplate when opening a file. > > Okay, got it. Will drop it in v3. Thanks. > > > > > > Rasmus
RE: [v8] i2c: imx: support slave mode for imx I2C driver
> > > +/*
> > > + * Enable bus idle interrupts
> > > + * Note: IBIC register will be cleared after disabled i2c module.
> > > + */
> > > +static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) {
> > > + unsigned int temp;
> > > +
> > > + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
> > > + temp |= IBIC_BIIE;
> > > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); }
> > > +
> > > +static void i2c_imx_clr_if_bit(unsigned int status, struct
> > > +imx_i2c_struct *i2c_imx) {
> > > + status &= ~I2SR_IIF;
> > > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > > +
> > > +/* Clear arbitration lost bit */
> > > +static void i2c_imx_clr_al_bit(unsigned int status, struct
> > > +imx_i2c_struct *i2c_imx) {
> > > + status &= ~I2SR_IAL;
> > > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
> > > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > > +
> > > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> >
> > Last year (to be more precise Date: Fri, 6 Dec 2019 08:38:20 +0100),
> > Sascha asked you to make I2C_SLAVE support not optional.
> > In the V7 of this patch you even tried to do so...
> > Please, patch drivers/i2c/busses/Kconfig and add "select I2C_SLAVE" to
> > the I2C_IMX node.
> Sure, np. Will add it in v4.
Correct it, it's v9.
> >
> > > +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
> > > + unsigned int status, unsigned int ctl) {
> > > + u8 value;
> > > +
> > > + if (status & I2SR_IAL) { /* Arbitration lost */
> > > + i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
> > > + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
> > > + if (status & I2SR_SRW) { /* Master wants to read from us*/
> > > + dev_dbg(_imx->adapter.dev, "read requested");
> > > + i2c_slave_event(i2c_imx->slave,
> > > I2C_SLAVE_READ_REQUESTED,
> > );
> > > +
RE: [v8] i2c: imx: support slave mode for imx I2C driver
> > +/*
> > + * Enable bus idle interrupts
> > + * Note: IBIC register will be cleared after disabled i2c module.
> > + */
> > +static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) {
> > + unsigned int temp;
> > +
> > + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
> > + temp |= IBIC_BIIE;
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); }
> > +
> > +static void i2c_imx_clr_if_bit(unsigned int status, struct
> > +imx_i2c_struct *i2c_imx) {
> > + status &= ~I2SR_IIF;
> > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > +
> > +/* Clear arbitration lost bit */
> > +static void i2c_imx_clr_al_bit(unsigned int status, struct
> > +imx_i2c_struct *i2c_imx) {
> > + status &= ~I2SR_IAL;
> > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > +
> > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>
> Last year (to be more precise Date: Fri, 6 Dec 2019 08:38:20 +0100), Sascha
> asked you to make I2C_SLAVE support not optional.
> In the V7 of this patch you even tried to do so...
> Please, patch drivers/i2c/busses/Kconfig and add "select I2C_SLAVE" to the
> I2C_IMX node.
Sure, np. Will add it in v4.
>
> > +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
> > +unsigned int status, unsigned int ctl) {
> > + u8 value;
> > +
> > + if (status & I2SR_IAL) { /* Arbitration lost */
> > + i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
> > + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
> > + if (status & I2SR_SRW) { /* Master wants to read from us*/
> > + dev_dbg(_imx->adapter.dev, "read requested");
> > + i2c_slave_event(i2c_imx->slave,
> > I2C_SLAVE_READ_REQUESTED,
> );
> > +
RE: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> >> On 2020-10-27 04:46, Biwen Li wrote: > >> > From: Hou Zhiqiang > >> > > >> > Add an new IRQ chip declaration for LS1043A and LS1088A > >> > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. > >> > SCFG_INTPCR[31:0] > >> > of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit > >> > reverse) > >> > - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > >> > > >> > Signed-off-by: Hou Zhiqiang > >> > Signed-off-by: Biwen Li > >> > >> You clearly couldn't be bothered to read what I wrote in my earlier > >> replies. I'm thus ignoring this series... > > Okay, got it. > >> > >> > --- > >> > Change in v2: > >> > - add despcription of bit reverse > >> > - update copyright > >> > > >> > drivers/irqchip/irq-ls-extirq.c | 10 +- > >> > 1 file changed, 9 insertions(+), 1 deletion(-) > >> > > >> > diff --git a/drivers/irqchip/irq-ls-extirq.c > >> > b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..9587bc2607fc > >> > 100644 > >> > --- a/drivers/irqchip/irq-ls-extirq.c > >> > +++ b/drivers/irqchip/irq-ls-extirq.c > >> > @@ -1,5 +1,8 @@ > >> > // SPDX-License-Identifier: GPL-2.0 > >> > - > >> > +/* > >> > + * Author: Rasmus Villemoes > >> > + * Copyright 2020 NXP > >> > >> ... specially when you keep attributing someone else's copyright to > >> NXP. > > Then I don't know how to add the copyright, any suggestions? > > Simple. You don't add anything. NXP's copyright doesn't apply to this file > before this patch, and your changes are so trivial that they don't really > warrant > a mention. Furthermore, the git history already keeps track of who did what. Okay, got it. Thanks. > > M. > -- > Jazz is not dead. It just smells funny...
RE: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> > On 2020-10-27 04:46, Biwen Li wrote: > > From: Hou Zhiqiang > > > > Add an new IRQ chip declaration for LS1043A and LS1088A > > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. > > SCFG_INTPCR[31:0] > > of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit > > reverse) > > - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > > > > Signed-off-by: Hou Zhiqiang > > Signed-off-by: Biwen Li > > You clearly couldn't be bothered to read what I wrote in my earlier replies. > I'm > thus ignoring this series... Okay, got it. > > > --- > > Change in v2: > > - add despcription of bit reverse > > - update copyright > > > > drivers/irqchip/irq-ls-extirq.c | 10 +- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-ls-extirq.c > > b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..9587bc2607fc > > 100644 > > --- a/drivers/irqchip/irq-ls-extirq.c > > +++ b/drivers/irqchip/irq-ls-extirq.c > > @@ -1,5 +1,8 @@ > > // SPDX-License-Identifier: GPL-2.0 > > - > > +/* > > + * Author: Rasmus Villemoes > > + * Copyright 2020 NXP > > ... specially when you keep attributing someone else's copyright to NXP. Then I don't know how to add the copyright, any suggestions? > > M. > -- > Jazz is not dead. It just smells funny...
RE: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> > Caution: EXT Email > > On 27/10/2020 05.46, Biwen Li wrote: > > From: Hou Zhiqiang > > > > Add an new IRQ chip declaration for LS1043A and LS1088A > > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. SCFG_INTPCR[31:0] > > of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit > > reverse) > > s/defaultly/by default/ I suppose. But what does that mean? Is it still > configurable, just now through some undocumented register? If that register > still exists, does it now have a reset value of all-ones as opposed to the > ls1021 > case? If it's not configurable, then describing the situation as "by default" > is > confusing and wrong, it should just say "On LS1043A, LS1046A, SCFG_INTPCR > is stored/read bit-reversed." Okay, got it. Will update it in v3. Thanks. > > > > - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > > > > Signed-off-by: Hou Zhiqiang > > Signed-off-by: Biwen Li > > --- > > Change in v2: > > - add despcription of bit reverse > > - update copyright > > > > drivers/irqchip/irq-ls-extirq.c | 10 +- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-ls-extirq.c > > b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..9587bc2607fc > > 100644 > > --- a/drivers/irqchip/irq-ls-extirq.c > > +++ b/drivers/irqchip/irq-ls-extirq.c > > @@ -1,5 +1,8 @@ > > // SPDX-License-Identifier: GPL-2.0 > > - > > +/* > > + * Author: Rasmus Villemoes > > If I wanted my name splattered all over the files I touch or add, I'd add it > myself, > TYVM. The git history is plenty fine for recording authorship as far as I'm > concerned, and I absolutely abhor having to skip over any kind of legalese > boilerplate when opening a file. Okay, got it. Will drop it in v3. Thanks. > > Rasmus
[v2 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..f75aa2ce4e2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -154,6 +154,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v2 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node
From: Biwen Li
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li
---
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = < 6
IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v2 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index d247e4228d60..095298a84f4e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -664,6 +664,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,lx2160a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,lx2160a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v2 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
From: Biwen Li Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li --- Change in v2: - update reg property - update compatible property .../bindings/interrupt-controller/fsl,ls-extirq.txt| 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad7801e8cf..0d635c24ef8b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,12 +9,17 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. SCFG_INTPCR[31:0] of these SoCs + is stored/read as SCFG_INTPCR[0:31] defaultly(bit reverse). + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. + - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. - interrupt-controller: Identifies the node as an interrupt controller - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG. + the SCFG or the External Interrupt Control Register (IRQCR) in + the ISC. - interrupt-map: Specifies the mapping from external interrupts to GIC interrupts. - interrupt-map-mask: Must be <0x 0>. -- 2.17.1
[v2 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li
---
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..f3bab76797fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = < 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v2 03/11] arm64: dts: ls1046a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..dff3ee84c294 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -314,6 +314,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq",
"fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[v2 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on ls1088ardb
Signed-off-by: Biwen Li
---
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..89c40d3f9a50 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -51,8 +51,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU),
active low */
+ interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.17.1
[v2 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node
From: Hou Zhiqiang
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang
---
Change in v2:
- none
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = < 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[v2 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..12fe8f079c28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -206,6 +206,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
From: Hou Zhiqiang Add an new IRQ chip declaration for LS1043A and LS1088A - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. SCFG_INTPCR[31:0] of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit reverse) - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA Signed-off-by: Hou Zhiqiang Signed-off-by: Biwen Li --- Change in v2: - add despcription of bit reverse - update copyright drivers/irqchip/irq-ls-extirq.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..9587bc2607fc 100644 --- a/drivers/irqchip/irq-ls-extirq.c +++ b/drivers/irqchip/irq-ls-extirq.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 - +/* + * Author: Rasmus Villemoes + * Copyright 2020 NXP + */ #define pr_fmt(fmt) "irq-ls-extirq: " fmt #include @@ -183,6 +186,9 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) priv->bit_reverse = (revcr != 0); } + if (of_device_is_compatible(node, "fsl,ls1043a-extirq")) + priv->bit_reverse = true; + domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node, _domain_ops, priv); if (!domain) @@ -195,3 +201,5 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init); -- 2.17.1
[v2 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
Change in v2:
- none
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..38a6d951ecc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -311,6 +311,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external > interrupt > > On 26/10/2020 09.44, Marc Zyngier wrote: > > On 2020-10-26 08:01, Biwen Li wrote: > >> From: Hou Zhiqiang > >> > >> Add an new IRQ chip declaration for LS1043A and LS1088A > >> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A > >> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > > > > Three things: > > - This commit message doesn't describe the bit_reverse change > > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't mention > anything about bit reversal for the scfg registers - they don't seem to have > the > utter nonsense that is SCFG_SCFGREVCR, but perhaps, instead of removing it, > that has just become a hard-coded part of the IP. Yeah, you are right, I will update it in v2. > > Also, IANAL etc., but > > >> +// Copyright 2019-2020 NXP > > really? Seems to be a bit of a stretch. > > At the very least, cc'ing the original author and only person to ever touch > that > file would have been appreciated. Okay, it's my fault, I will update it, thanks. > > Rasmus
RE: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
> > -Original Message- > > From: Marc Zyngier > > Sent: Monday, October 26, 2020 4:23 AM > > To: Rasmus Villemoes > > Cc: Biwen Li (OSS) ; shawn...@kernel.org; > > robh...@kernel.org; mark.rutl...@arm.com; Leo Li ; > > Z.q. Hou ; t...@linutronix.de; > > ja...@lakedaemon.net; devicet...@vger.kernel.org; linux- > > ker...@vger.kernel.org; Jiafei Pan ; Xiaobo Xie > > ; linux-arm-ker...@lists.infradead.org; Biwen Li > > > > Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A > > external interrupt > > > > On 2020-10-26 09:06, Rasmus Villemoes wrote: > > > On 26/10/2020 09.44, Marc Zyngier wrote: > > >> On 2020-10-26 08:01, Biwen Li wrote: > > >>> From: Hou Zhiqiang > > >>> > > >>> Add an new IRQ chip declaration for LS1043A and LS1088A > > >>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A > > >>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA > > >> > > >> Three things: > > >> - This commit message doesn't describe the bit_reverse change > > > > > > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't > > > mention anything about bit reversal for the scfg registers - they > > > don't seem to have the utter nonsense that is SCFG_SCFGREVCR, but > > > perhaps, instead of removing it, that has just become a hard-coded > > > part of the IP. > > > > > > Also, IANAL etc., but > > > > > >>> +// Copyright 2019-2020 NXP > > > > > > really? Seems to be a bit of a stretch. > > > > > > At the very least, cc'ing the original author and only person to > > > ever touch that file would have been appreciated. > > > > Huh. Well spotted. That's definitely not on. > > NXP people, please talk to your legal department. > > We do have an internal policy to require developer adding/updating NXP > copyright on non-trivial changes. I'm not sure if this change should be > considered trivial, but adding copyright claim on a file without prior > copyright > claims could causing confusion like in this case. One potential solution is > to > add a more specific description on the NXP change together with the copyright > claim. But maybe an easier solution is to add Rasmus your Copyright claim > first if you are ok with it. Yes, added a wrong Copyright. > > Regards, > Leo
[v8] i2c: imx: support slave mode for imx I2C driver
From: Biwen Li
The patch supports slave mode for imx I2C driver
Signed-off-by: Biwen Li
---
Change in v8:
- fix build issue
Change in v7:
- support auto switch mode between master and slave
- enable interrupt when idle in slave mode
- remove #ifdef
Change in v6:
- delete robust logs and comments
- not read status register again in master isr.
Change in v5:
- fix a bug that cannot determine in what mode(master mode or
slave mode)
Change in v4:
- add MACRO CONFIG_I2C_SLAVE to fix compilation issue
Change in v3:
- support layerscape and i.mx platform
Change in v2:
- remove MACRO CONFIG_I2C_SLAVE
drivers/i2c/busses/i2c-imx.c | 227 ---
1 file changed, 213 insertions(+), 14 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0ab5381aa012..9721ef8649ad 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -17,6 +17,7 @@
* Copyright (C) 2008 Darius Augulis
*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
*/
@@ -72,6 +73,7 @@
#define IMX_I2C_I2CR 0x02/* i2c control */
#define IMX_I2C_I2SR 0x03/* i2c status */
#define IMX_I2C_I2DR 0x04/* i2c transfer data */
+#define IMX_I2C_IBIC 0x05/* i2c transfer data */
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
@@ -91,6 +93,7 @@
#define I2CR_MSTA 0x20
#define I2CR_IIEN 0x40
#define I2CR_IEN 0x80
+#define IBIC_BIIE 0x80 // Bus idle interrupt enable
/* register bits different operating codes definition:
* 1) I2SR: Interrupt flags clear operation differ between SoCs:
@@ -201,6 +204,7 @@ struct imx_i2c_struct {
struct pinctrl_state *pinctrl_pins_gpio;
struct imx_i2c_dma *dma;
+ struct i2c_client *slave;
};
static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -277,6 +281,14 @@ static inline unsigned char imx_i2c_read_reg(struct
imx_i2c_struct *i2c_imx,
return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
}
+/* Set up i2c controller register and i2c status register to default value. */
+static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
+{
+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
+ i2c_imx, IMX_I2C_I2CR);
+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
IMX_I2C_I2SR);
+}
+
/* Functions for DMA support */
static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
dma_addr_t phy_addr)
@@ -614,20 +626,200 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx,
bool atomic)
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
}
+/*
+ * Enable bus idle interrupts
+ * Note: IBIC register will be cleared after disabled i2c module.
+ */
+static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
+{
+ unsigned int temp;
+
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
+ temp |= IBIC_BIIE;
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
+}
+
+static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IIF;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+/* Clear arbitration lost bit */
+static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IAL;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
+unsigned int status, unsigned int ctl)
+{
+ u8 value;
+
+ if (status & I2SR_IAL) { /* Arbitration lost */
+ i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
+ } else if (status & I2SR_IAAS) { /* Addressed as a slave */
+ if (status & I2SR_SRW) { /* Master wants to read from us*/
+ dev_dbg(_imx->adapter.dev, "read requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_READ_REQUESTED, );
+
+ /* Slave transmit */
+ ctl |= I2CR_MTX;
+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
+
+ /* Send data */
+ imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
+ } else { /* Master wants to write to us */
+ dev_dbg(_imx->adapter.dev, "write requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_WRITE_REQUESTED, );
+
+ /* Slave receive */
+
[RESEND 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..12fe8f079c28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -206,6 +206,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[RESEND 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..38a6d951ecc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -311,6 +311,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[RESEND 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node
From: Hou Zhiqiang
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = < 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
From: Hou Zhiqiang Add an new IRQ chip declaration for LS1043A and LS1088A - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA Signed-off-by: Hou Zhiqiang Signed-off-by: Biwen Li --- drivers/irqchip/irq-ls-extirq.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..564e6de0bd8e 100644 --- a/drivers/irqchip/irq-ls-extirq.c +++ b/drivers/irqchip/irq-ls-extirq.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// Copyright 2019-2020 NXP #define pr_fmt(fmt) "irq-ls-extirq: " fmt @@ -183,6 +184,9 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) priv->bit_reverse = (revcr != 0); } + if (of_device_is_compatible(node, "fsl,ls1043a-extirq")) + priv->bit_reverse = true; + domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node, _domain_ops, priv); if (!domain) @@ -195,3 +199,5 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init); -- 2.17.1
[RESEND 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
From: Biwen Li Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li --- .../bindings/interrupt-controller/fsl,ls-extirq.txt | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad7801e8cf..90ef8917ac02 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,12 +9,16 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. + - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. - interrupt-controller: Identifies the node as an interrupt controller - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG. + the SCFG or the External Interrupt Control Register (IRQCR) in + the ISC. - interrupt-map: Specifies the mapping from external interrupts to GIC interrupts. - interrupt-map-mask: Must be <0x 0>. -- 2.17.1
[RESEND 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index d247e4228d60..095298a84f4e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -664,6 +664,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,lx2160a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,lx2160a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[RESEND 03/11] arm64: dts: ls1046a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..dff3ee84c294 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -314,6 +314,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq",
"fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[RESEND 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node
From: Biwen Li
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = < 6
IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[RESEND 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..f75aa2ce4e2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -154,6 +154,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[RESEND 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..f3bab76797fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = < 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[RESEND 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on ls1088ardb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..89c40d3f9a50 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -51,8 +51,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU),
active low */
+ interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.17.1
[PATCH 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 22d0308eb13b..05f977974d11 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = < 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[PATCH 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 3944ef16ec60..cf1af8b8cd5f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -153,6 +153,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[PATCH 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node
From: Biwen Li
Fix interrupt line for RTC node on ls1088ardb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..89c40d3f9a50 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -51,8 +51,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU),
active low */
+ interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.17.1
[PATCH 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 33 ++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 36a799554620..c8b583cb2b9f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai
*
@@ -205,6 +205,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[PATCH 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node
From: Hou Zhiqiang
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = < 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[PATCH 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node
From: Biwen Li
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = < 6
IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
[PATCH 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c084c7a4b6a6..59c4365a51e0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -230,6 +230,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
[PATCH 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt
From: Hou Zhiqiang Add an new IRQ chip declaration for LS1043A and LS1088A - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA Signed-off-by: Hou Zhiqiang Signed-off-by: Biwen Li --- drivers/irqchip/irq-ls-extirq.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c index 4d1179fed77c..564e6de0bd8e 100644 --- a/drivers/irqchip/irq-ls-extirq.c +++ b/drivers/irqchip/irq-ls-extirq.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// Copyright 2019-2020 NXP #define pr_fmt(fmt) "irq-ls-extirq: " fmt @@ -183,6 +184,9 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) priv->bit_reverse = (revcr != 0); } + if (of_device_is_compatible(node, "fsl,ls1043a-extirq")) + priv->bit_reverse = true; + domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node, _domain_ops, priv); if (!domain) @@ -195,3 +199,5 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init); +IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init); -- 2.17.1
[PATCH 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index ae1b113ab162..8de845c08d0d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -540,6 +540,37 @@
little-endian;
};
+ isc: syscon@1f7 {
+ compatible = "fsl,lx2160a-isc", "syscon";
+ reg = <0x0 0x1f7 0x0 0x1>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f7 0x1>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,lx2160a-extirq",
"fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 0
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 1
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 2
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 3
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 5
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 6
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 7
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 8
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 9
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 10
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 11
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
+ };
+
tmu: tmu@1f8 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
--
2.17.1
[PATCH 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
From: Biwen Li Update bindings for Layerscape external irqs, support more SoCs(LS1043A, LS1046A, LS1088A, LS208xA, LX216xA) Signed-off-by: Biwen Li --- .../bindings/interrupt-controller/fsl,ls-extirq.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt index f0ad7801e8cf..6c55eb25cf93 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -1,6 +1,7 @@ * Freescale Layerscape external IRQs -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A +LS1088A, LS208xA, LX216xA) support inverting the polarity of certain external interrupt lines. The device node must be a child of the node representing the @@ -8,6 +9,9 @@ Supplemental Configuration Unit (SCFG). Required properties: - compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". + "fsl,ls1043a-extirq": for LS1043A, LS1046A. + "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. + - #interrupt-cells: Must be 2. The first element is the index of the external interrupt line. The second element is the trigger type. - #address-cells: Must be 0. -- 2.17.1
[PATCH 03/11] arm64: dts: ls1046a: add DT node for external interrupt lines
From: Biwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index d4c1da3d4bde..5580aa0430d4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu
*/
@@ -233,6 +233,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x157 0x0 0x1>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x157 0x1>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq",
"fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 GIC_SPI 133
IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 GIC_SPI 135
IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 GIC_SPI 136
IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 GIC_SPI 137
IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 GIC_SPI 147
IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 GIC_SPI 150
IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 GIC_SPI 151
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x 0x0>;
+ };
};
crypto: crypto@170 {
--
2.17.1
RE: [PATCH] hwmon: add support for SMSC EMC2305/03/02/01 fan controller
> > On Mon, Sep 28, 2020 at 06:43:26PM +0800, Biwen Li wrote: > > From: Reinhard Pfau > > > > Add support for SMSC EMC2305, EMC2303, EMC2302, EMC2301 fan controller > > chips. > > The driver primary supports the EMC2305 chip which provides RPM-based > > PWM control and monitoring for up to 5 fans. > > > > According to the SMSC data sheets the EMC2303, EMC2302 and EMC2301 > > chips have basically the same functionality and register layout, but > > support less fans and (in case of EMC2302 and EMC2301) less possible I2C > addresses. > > The driver supports them, too. > > > > The driver supports configuration via devicetree. This can also be > > used to restrict the fans exposed via sysfs (see doc for details). > > > > Signed-off-by: Reinhard Pfau > > Signed-off-by: Biwen Li > > --- > > .../devicetree/bindings/hwmon/emc2305.txt | 33 + > > Split to a separate patch and should be in DT schema format. > checkpatch.pl will tell you both of these things. Okay, got it, thanks. > > > Documentation/hwmon/emc2305.rst | 34 + > > MAINTAINERS | 8 + > > drivers/hwmon/Kconfig | 10 + > > drivers/hwmon/Makefile| 1 + > > drivers/hwmon/emc2305.c | 689 > ++ > > 6 files changed, 775 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/hwmon/emc2305.txt > > create mode 100644 Documentation/hwmon/emc2305.rst create mode > > 100644 drivers/hwmon/emc2305.c
[v7] i2c: imx: support slave mode for imx I2C driver
From: Biwen Li
The patch supports slave mode for imx I2C driver
Signed-off-by: Biwen Li
---
Change in v7:
- support auto switch mode between master and slave
- enable interrupt when idle in slave mode
- remove #ifdef
Change in v6:
- delete robust logs and comments
- not read status register again in master isr.
Change in v5:
- fix a bug that cannot determine in what mode(master mode or
slave mode)
Change in v4:
- add MACRO CONFIG_I2C_SLAVE to fix compilation issue
Change in v3:
- support layerscape and i.mx platform
Change in v2:
- remove MACRO CONFIG_I2C_SLAVE
drivers/i2c/busses/i2c-imx.c | 213 ---
1 file changed, 199 insertions(+), 14 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0ab5381aa012..0d62b09ee967 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -17,6 +17,7 @@
* Copyright (C) 2008 Darius Augulis
*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
*/
@@ -72,6 +73,7 @@
#define IMX_I2C_I2CR 0x02/* i2c control */
#define IMX_I2C_I2SR 0x03/* i2c status */
#define IMX_I2C_I2DR 0x04/* i2c transfer data */
+#define IMX_I2C_IBIC 0x05/* i2c transfer data */
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
@@ -91,6 +93,7 @@
#define I2CR_MSTA 0x20
#define I2CR_IIEN 0x40
#define I2CR_IEN 0x80
+#define IBIC_BIIE 0x80 // Bus idle interrupt enable
/* register bits different operating codes definition:
* 1) I2SR: Interrupt flags clear operation differ between SoCs:
@@ -201,6 +204,7 @@ struct imx_i2c_struct {
struct pinctrl_state *pinctrl_pins_gpio;
struct imx_i2c_dma *dma;
+ struct i2c_client *slave;
};
static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -277,6 +281,14 @@ static inline unsigned char imx_i2c_read_reg(struct
imx_i2c_struct *i2c_imx,
return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
}
+/* Set up i2c controller register and i2c status register to default value. */
+static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
+{
+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
+ i2c_imx, IMX_I2C_I2CR);
+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
IMX_I2C_I2SR);
+}
+
/* Functions for DMA support */
static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
dma_addr_t phy_addr)
@@ -614,20 +626,110 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx,
bool atomic)
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
}
+/*
+ * Enable bus idle interrupts
+ * Note: IBIC register will be cleared after disabled i2c module.
+ */
+static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
+{
+ unsigned int temp;
+
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
+ temp |= IBIC_BIIE;
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
+}
+
+static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IIF;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+/* Clear arbitration lost bit */
+static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct
*i2c_imx)
+{
+ status &= ~I2SR_IAL;
+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
+}
+
+static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
+unsigned int status, unsigned int ctl)
+{
+ u8 value;
+
+ if (status & I2SR_IAL) { /* Arbitration lost */
+ i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx);
+ } else if (status & I2SR_IAAS) { /* Addressed as a slave */
+ if (status & I2SR_SRW) { /* Master wants to read from us*/
+ dev_dbg(_imx->adapter.dev, "read requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_READ_REQUESTED, );
+
+ /* Slave transmit */
+ ctl |= I2CR_MTX;
+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
+
+ /* Send data */
+ imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
+ } else { /* Master wants to write to us */
+ dev_dbg(_imx->adapter.dev, "write requested");
+ i2c_slave_event(i2c_imx->slave,
I2C_SLAVE_WRITE_REQUESTED, );
+
+ /* Slave receive */
+ ctl &= ~I2CR_MTX;
+ imx_i2c_write_reg(ctl, i2
RE: [PATCH] hwmon: add support for SMSC EMC2305/03/02/01 fan controller
> > + > > + hwmon_dev = devm_hwmon_device_register_with_groups(>dev, > > + client->name, data, > > + data->groups); > > New drivers must use "[devm_]hwmon_device_register_with_info" to register > with the hwmon subsystem. Hi Guenter, Got it, thanks. Best Regards, Biwen Li > > Guenter
RE: [PATCH] hwmon: add support for SMSC EMC2305/03/02/01 fan controller
Hi All, The patch has a problem as follows, root@localhost:~# cat /sys/class/hwmon/hwmon0/pwm1 [ 103.150689] Unable to handle kernel paging request at virtual address 00329c100026 [ 103.158651] Mem abort info: [ 103.161443] ESR = 0x9604 [ 103.164486] EC = 0x25: DABT (current EL), IL = 32 bits [ 103.169789] SET = 0, FnV = 0 [ 103.172835] EA = 0, S1PTW = 0 [ 103.175963] Data abort info: [ 103.178841] ISV = 0, ISS = 0x0004 [ 103.182672] CM = 0, WnR = 0 [ 103.185640] [00329c100026] address between user and kernel address ranges [ 103.192778] Internal error: Oops: 9604 [#1] PREEMPT SMP [ 103.198337] Modules linked in: emc2305 [ 103.202076] CPU: 3 PID: 940 Comm: cat Not tainted 5.4.3-00011-gd80981868cef-dirty #7 [ 103.209805] Hardware name: NXP Layerscape LX2160ABLUEBOX3 (DT) [ 103.215625] pstate: 6005 (nZCv daif -PAN -UAO) [ 103.220409] pc : i2c_smbus_xfer+0x50/0x110 [ 103.220409] pc : i2c_smbus_xfer+0x50/0x110 [ 103.224494] lr : i2c_smbus_read_byte_data+0x40/0x70 [ 103.229357] sp : 800010abbb50 [ 103.232659] x29: 800010abbb50 x28: 0026d7fb6480 [ 103.237958] x27: 0026d7fb6480 x26: 0026d5329be8 [ 103.243256] x25: 800010abbbc6 x24: 0002 [ 103.248555] x23: 0032 x22: 0001 [ 103.253854] x21: x20: [ 103.259152] x19: 0026d8011404 x18: [ 103.264451] x17: x16: aea1e5532f08 [ 103.269749] x15: x14: [ 103.275047] x13: x12: [ 103.280346] x11: x10: [ 103.285645] x9 : x8 : 0026d3f1d000 [ 103.290943] x7 : aea1e6919000 x6 : 800010abbbc6 [ 103.296241] x5 : 0002 x4 : 0032 [ 103.301540] x3 : 0001 x2 : d5329c100026 [ 103.306839] x1 : 0002 x0 : 0026d8011404 [ 103.312137] Call trace: [ 103.314572] i2c_smbus_xfer+0x50/0x110 [ 103.318308] i2c_smbus_read_byte_data+0x40/0x70 [ 103.322829] read_u8_from_i2c+0x24/0x60 [emc2305] [ 103.327520] emc2305_update_fan+0x9c/0x158 [emc2305] [ 103.332472] pwm_enable_show+0x1c/0x50 [emc2305] [ 103.337078] dev_attr_show+0x20/0x60 [ 103.340643] sysfs_kf_seq_show+0xbc/0x148 [ 103.344640] kernfs_seq_show+0x28/0x30 [ 103.348377] seq_read+0xcc/0x4c8 [ 103.351592] kernfs_fop_read+0x140/0x200 [ 103.355503] __vfs_read+0x18/0x38 [ 103.358804] vfs_read+0x98/0x188 [ 103.362020] ksys_read+0x68/0xf8 [ 103.365235] __arm64_sys_read+0x18/0x20 [ 103.369059] el0_svc_common.constprop.2+0x64/0x160 [ 103.373837] el0_svc_handler+0x20/0x80 [ 103.377573] el0_svc+0x8/0xc [ 103.380442] Code: 54000368 f9401262 52800041 aa1303e0 (f9400042) [ 103.386523] ---[ end trace 0f9e87c54e49a984 ]--- Any comments about this? Welcome for your comments. > > From: Reinhard Pfau > > Add support for SMSC EMC2305, EMC2303, EMC2302, EMC2301 fan > controller chips. > The driver primary supports the EMC2305 chip which provides RPM-based > PWM control and monitoring for up to 5 fans. > > According to the SMSC data sheets the EMC2303, EMC2302 and EMC2301 > chips have basically the same functionality and register layout, but support > less > fans and (in case of EMC2302 and EMC2301) less possible I2C addresses. > The driver supports them, too. > > The driver supports configuration via devicetree. This can also be used to > restrict the fans exposed via sysfs (see doc for details). > > Signed-off-by: Reinhard Pfau > Signed-off-by: Biwen Li > --- > .../devicetree/bindings/hwmon/emc2305.txt | 33 + > Documentation/hwmon/emc2305.rst | 34 + > MAINTAINERS | 8 + > drivers/hwmon/Kconfig | 10 + > drivers/hwmon/Makefile| 1 + > drivers/hwmon/emc2305.c | 689 > ++ > 6 files changed, 775 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/hwmon/emc2305.txt > create mode 100644 Documentation/hwmon/emc2305.rst create mode > 100644 drivers/hwmon/emc2305.c > > diff --git a/Documentation/devicetree/bindings/hwmon/emc2305.txt > b/Documentation/devicetree/bindings/hwmon/emc2305.txt > new file mode 100644 > index ..73165120b88a > --- /dev/null > +++ b/Documentation/devicetree/bindings/hwmon/emc2305.txt > @@ -0,0 +1,33 @@ > +EMC2305 (I2C) > + > +This device is a RPM-based PWM Fan Speed Controller for up to 5 fans. > +Each fan can beconfigured individually: > + > + - The PWM mode: > +0: PWM is disabled > +3: RPM based PWM > + > + - The fan divisor (for RPM mesaurement) > + 1, 2 ,4 or 8 > + > + - The target RPM speed (for RPM based PWM mode) > + max 16000 (according to data
[PATCH] hwmon: add support for SMSC EMC2305/03/02/01 fan controller
From: Reinhard Pfau
Add support for SMSC EMC2305, EMC2303, EMC2302, EMC2301 fan controller
chips.
The driver primary supports the EMC2305 chip which provides RPM-based
PWM control and monitoring for up to 5 fans.
According to the SMSC data sheets the EMC2303, EMC2302 and EMC2301 chips
have basically the same functionality and register layout, but support
less fans and (in case of EMC2302 and EMC2301) less possible I2C addresses.
The driver supports them, too.
The driver supports configuration via devicetree. This can also be used
to restrict the fans exposed via sysfs (see doc for details).
Signed-off-by: Reinhard Pfau
Signed-off-by: Biwen Li
---
.../devicetree/bindings/hwmon/emc2305.txt | 33 +
Documentation/hwmon/emc2305.rst | 34 +
MAINTAINERS | 8 +
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile| 1 +
drivers/hwmon/emc2305.c | 689 ++
6 files changed, 775 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/emc2305.txt
create mode 100644 Documentation/hwmon/emc2305.rst
create mode 100644 drivers/hwmon/emc2305.c
diff --git a/Documentation/devicetree/bindings/hwmon/emc2305.txt
b/Documentation/devicetree/bindings/hwmon/emc2305.txt
new file mode 100644
index ..73165120b88a
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/emc2305.txt
@@ -0,0 +1,33 @@
+EMC2305 (I2C)
+
+This device is a RPM-based PWM Fan Speed Controller for up to 5 fans.
+Each fan can beconfigured individually:
+
+ - The PWM mode:
+0: PWM is disabled
+3: RPM based PWM
+
+ - The fan divisor (for RPM mesaurement)
+ 1, 2 ,4 or 8
+
+ - The target RPM speed (for RPM based PWM mode)
+ max 16000 (according to data sheet)
+
+
+ - The /emc2305 node
+
+ Required properties:
+
+ - compatible : must be "smsc,emc2305"
+ - reg : I2C bus address of the device
+ - #address-cells : must be <1>
+ - #size-cells : must be <0>
+
+ Example EMC2305 node:
+
+ emc2305@2C {
+ compatible = "smsc,emc2305";
+ reg = <0x2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ }
diff --git a/Documentation/hwmon/emc2305.rst b/Documentation/hwmon/emc2305.rst
new file mode 100644
index ..d0cebae09ffd
--- /dev/null
+++ b/Documentation/hwmon/emc2305.rst
@@ -0,0 +1,34 @@
+Kernel driver emc2305
+=
+
+Supported chips:
+ * SMSC EMC2305, EMC2303, EMC2302, EMC2301
+Adresses scanned: I2C 0x2c, 0x2d, 0x2e, 0x2f, 0x4c, 0x4d
+Prefixes: 'emc2305', 'emc2303', 'emc2302', 'emc2301'
+Datasheet: Publicly available at the MICROCHIP website :
+http://ww1.microchip.com/downloads/en/DeviceDoc/2305.pdf
+
+Authors:
+Reinhard Pfau, Guntermann & Drunck GmbH
+Biwen Li
+
+Description
+---
+
+The SMSC EMC2305 is a fan controller for up to 5 fans.
+The EMC2303 has the same functionality but supports only up to 3 fans.
+
+The EMC2302 supports 2 fans and the EMC2301 1 fan. These chips support less
+possible I2C addresses.
+
+Fan rotation speeds are reported in RPM.
+The driver supports the RPM based PWM control to keep a fan at a desired speed.
+To enable this function for a fan, write 3 to pwm_enable and the desired
+fan speed to fan_target.
+
+
+Devicetree
+--
+
+Configuration is also possible via devicetree:
+Documentation/devicetree/bindings/hwmon/emc2305.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index b526b8a66f8a..a506e8071259 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15013,6 +15013,14 @@ S: Maintained
F: Documentation/hwmon/emc2103.rst
F: drivers/hwmon/emc2103.c
+SMSC EMC2305 HARDWARE MONITOR DRIVER
+M: Biwen Li
+L: lm-sens...@lm-sensors.org
+S: Maintained
+F: Documentation/hwmon/emc2305
+F: Documentation/devicetree/bindings/hwmon/emc2305.txt
+F: drivers/hwmon/emc2305.c
+
SMSC SCH5627 HARDWARE MONITOR DRIVER
M: Hans de Goede
L: linux-hw...@vger.kernel.org
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 2fa4666d5b07..5ab3e975517a 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1457,6 +1457,16 @@ config SENSORS_EMC2103
This driver can also be built as a module. If so, the module
will be called emc2103.
+config SENSORS_EMC2305
+ tristate "SMSC EMC2305"
+ depends on I2C
+ help
+ If you say yes here you get support for the SMSC EMC2305
+ fan controller chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called emc2305.
+
config SENSORS_EMC6W201
tristate "SMSC EMC6W201"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index b033e6733b56..b6377d32a2c9 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -60,6 +60,
RE: [EXT] Re: [PATCH 2/5] arm64: dts: lx2160a-rdb: remove useless property of rtc
>
>
>
> > -Original Message-
> > From: Biwen Li
> > Sent: Monday, September 21, 2020 10:13 PM
> > To: Shawn Guo ; Biwen Li (OSS)
> >
> > Cc: alexandre.bell...@bootlin.com; Leo Li ;
> > robh...@kernel.org; mark.rutl...@arm.com; devicet...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; Jiafei Pan ; linux-
> > r...@vger.kernel.org
> > Subject: RE: [EXT] Re: [PATCH 2/5] arm64: dts: lx2160a-rdb: remove
> > useless property of rtc
> >
> > >
> > > Caution: EXT Email
> > >
> > > On Tue, Sep 15, 2020 at 03:32:10PM +0800, Biwen Li wrote:
> > > > From: Biwen Li
> > > >
> > > > Remove useless property interrupts of rtc
> > > >
> > > > Signed-off-by: Biwen Li
> > > > ---
> > > > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 --
> > > > 1 file changed, 2 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > index dce79018d397..e9e982176e07 100644
> > > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > @@ -171,8 +171,6 @@
> > > > rtc@51 {
> > > > compatible = "nxp,pcf2129";
> > > > reg = <0x51>;
> > > > - // IRQ10_B
> > > > - interrupts = <0 150 0x4>;
> > >
> > > If it's a correct description of hardware, I do not see why we would
> > > need to remove it.
> > Hi Shawn,
> >
> > Don't need use the interrupt, only read time from rtc.
>
> User probably will choose to use the alarm feature of the RTC and need the
> interrupt property. Is there any issue when the interrupt property is
> present?
Generic interrupt controller on layerscape only support IRQ_TYPE_LEVEL_HIGH
and IRQ_TYPE_EDGE_RISING(except SoC LS1043A, LS1046A),
Not support IRQ_TYPE_LEVEL_LOW,
In drivers/rtc/rtc-pcf2127.c
ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
pcf2127_rtc_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
dev_name(dev), dev);
>
> >
> > Best Regards,
> > Biwen Li
> > >
> > > Shawn
> > >
> > > > };
> > > > };
> > > >
> > > > --
> > > > 2.17.1
> > > >
RE: [EXT] Re: [PATCH 2/5] arm64: dts: lx2160a-rdb: remove useless property of rtc
>
> Caution: EXT Email
>
> On Tue, Sep 15, 2020 at 03:32:10PM +0800, Biwen Li wrote:
> > From: Biwen Li
> >
> > Remove useless property interrupts of rtc
> >
> > Signed-off-by: Biwen Li
> > ---
> > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > index dce79018d397..e9e982176e07 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -171,8 +171,6 @@
> > rtc@51 {
> > compatible = "nxp,pcf2129";
> > reg = <0x51>;
> > - // IRQ10_B
> > - interrupts = <0 150 0x4>;
>
> If it's a correct description of hardware, I do not see why we would need to
> remove it.
Hi Shawn,
Don't need use the interrupt, only read time from rtc.
Best Regards,
Biwen Li
>
> Shawn
>
> > };
> > };
> >
> > --
> > 2.17.1
> >
RE: [EXT] Re: rtc: fsl-ftm-alarm: add shutdown interface
>
> Hi,
>
> On 30/03/2020 18:44:01+0200, Alexandre Belloni wrote:
> > On 30/03/2020 20:26:16+0800, Biwen Li wrote:
> > > From: Biwen Li
> > >
> > > Add shutdown interface
> > >
> > > Signed-off-by: Biwen Li
> > > ---
> > > drivers/rtc/rtc-fsl-ftm-alarm.c | 10 ++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/drivers/rtc/rtc-fsl-ftm-alarm.c
> > > b/drivers/rtc/rtc-fsl-ftm-alarm.c index d7fa6c16f47b..118a775e8316
> > > 100644
> > > --- a/drivers/rtc/rtc-fsl-ftm-alarm.c
> > > +++ b/drivers/rtc/rtc-fsl-ftm-alarm.c
> > > @@ -307,6 +307,15 @@ static int ftm_rtc_probe(struct platform_device
> *pdev)
> > > return 0;
> > > }
> > >
> > > +static void ftm_rtc_shutdown(struct platform_device *pdev) {
> > > + struct ftm_rtc *rtc = platform_get_drvdata(pdev);
> > > +
> > > + ftm_irq_acknowledge(rtc);
> > > + ftm_irq_disable(rtc);
> > > + ftm_clean_alarm(rtc);
> >
> > If the alarm is able to start the platform, then you probably don't
> > want to disable the alarm on shutdown.
> >
>
> I realise you never replied to that question. Is that patch still of interest?
Hi Alex, you can drop it. Thanks.
Best Regards,
Biwen Li
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbootlin.c
> om%2Fdata=02%7C01%7Cbiwen.li%40nxp.com%7Cd688030894714bca7
> 5c708d8596210ec%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63
> 7357625013809281sdata=pOBMmsxi7DVlywuLZ2LOLVgK4r4GtvW1PYq1
> p9JVv74%3Dreserved=0
[PATCH 1/5] rtc: pcf2127: fix a bug when not specify interrupts property
From: Biwen Li
Fix a bug when not specify interrupts property in dts
as follows,
rtc-pcf2127-i2c 1-0051: failed to request alarm irq
rtc-pcf2127-i2c: probe of 1-0051 failed with error -22
Signed-off-by: Biwen Li
---
drivers/rtc/rtc-pcf2127.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index ed6316992cbb..07a5630ec841 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -559,7 +559,7 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
pcf2127->rtc->uie_unsupported = 1;
- if (alarm_irq >= 0) {
+ if (alarm_irq > 0) {
ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
pcf2127_rtc_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
@@ -570,7 +570,7 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
}
}
- if (alarm_irq >= 0 || device_property_read_bool(dev, "wakeup-source")) {
+ if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
device_init_wakeup(dev, true);
pcf2127->rtc->ops = _rtc_alrm_ops;
}
--
2.17.1
[PATCH 2/5] arm64: dts: lx2160a-rdb: remove useless property of rtc
From: Biwen Li
Remove useless property interrupts of rtc
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index dce79018d397..e9e982176e07 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -171,8 +171,6 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
};
};
--
2.17.1
[PATCH 3/5] arm64: dts: ls1088a-rdb: remove useless property of rtc
From: Biwen Li
Remove useless property interrupts of rtc
Signed-off-by: Biwen Li
---
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index f651f4a5a54b..b543389155b0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -51,8 +51,6 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- /* IRQ10_B */
- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
--
2.17.1
