Re: [linux-sunxi] [PATCH] arm64: dts: allwinner: h6: beelink-gs1: Remove ext. 32 kHz osc reference
Hi Jernej,
On Tue, 30 Mar 2021 at 20:42, Jernej Skrabec wrote:
>
> Although every Beelink GS1 seems to have external 32768 Hz oscillator,
> it works only on one from four tested. There are more reports of RTC
> issues elsewhere, like Armbian forum.
>
> One Beelink GS1 owner read RTC osc status register on Android which
> shipped with the box. Reported value indicated problems with external
> oscillator.
>
> In order to fix RTC and related issues (HDMI-CEC and suspend/resume with
> Crust) on all boards, switch to internal oscillator.
>
> Fixes: 32507b868119 ("arm64: dts: allwinner: h6: Move ext. oscillator to
> board DTs")
> Signed-off-by: Jernej Skrabec
Tested-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index 669d39fc716a..6249e9e02928 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -289,10 +289,6 @@ sw {
> };
> };
>
> -&rtc {
> - clocks = <&ext_osc32k>;
> -};
> -
> &spdif {
> status = "okay";
> };
> --
> 2.31.0
>
> --
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Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU
Hi Andre,
I try to review this, and compare against the vendor Kernel
On Wed, 2 Dec 2020 at 14:54, Andre Przywara wrote:
>
> While the clocks are fairly similar to the H6, many differ in tiny
> details, so a separate clock driver seems indicated.
>
> Derived from the H6 clock driver, and adjusted according to the manual.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/clk/sunxi-ng/Kconfig|7 +-
> drivers/clk/sunxi-ng/Makefile |1 +
> drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1134 +++
> drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 58 +
> include/dt-bindings/clock/sun50i-h616-ccu.h | 110 ++
> include/dt-bindings/reset/sun50i-h616-ccu.h | 67 ++
> 6 files changed, 1376 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index ce5f5847d5d3..cd46d8853876 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> +config SUN50I_H616_CCU
> + bool "Support for the Allwinner H616 CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
> config SUN50I_H6_R_CCU
> - bool "Support for the Allwinner H6 PRCM CCU"
> + bool "Support for the Allwinner H6 and H616 PRCM CCU"
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 3eb5cff40eac..96c324306d97 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
> obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
> obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
> +obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
> obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
> obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
> obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> new file mode 100644
> index ..3fbb258f0354
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Arm Ltd.
> + * Based on the H6 CCU driver, which is:
> + * Copyright (c) 2017 Icenowy Zheng
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun50i-h616.h"
> +
> +/*
> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
> + * P should only be used for output frequencies lower than 288 MHz.
> + *
> + * For now we can just model it as a multiplier clock, and force P to /1.
> + *
> + * The M factor is present in the register's description, but not in the
> + * frequency formula, and it's documented as "M is only used for backdoor
> + * testing", so it's not modelled and then force to 0.
> + */
> +#define SUN50I_H616_PLL_CPUX_REG 0x000
> +static struct ccu_mult pll_cpux_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .common = {
> + .reg= 0x000,
> + .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
> + &ccu_mult_ops,
> + CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
> +#define SUN50I_H616_PLL_DDR0_REG 0x010
> +static struct ccu_nkmp pll_ddr0_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
> + .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
> + .common = {
> + .reg= 0x010,
> + .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
> + &ccu_nkmp_ops,
> + CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +#define SUN50I_H616_PLL_DDR1_REG 0x018
> +static struct ccu_nk
Re: [linux-sunxi] Re: [PATCH 3/3] arm64: allwinner: dts: a64: add DT for PineTab developer sample
Hi Maxime On Tue, 1 Dec 2020 at 11:35, Maxime Ripard wrote: > > On Sat, Nov 28, 2020 at 10:07:27PM +0100, Clément Péron wrote: > > Hi Maxime, Icenowy, > > > > On Sat, 28 Nov 2020 at 12:59, Icenowy Zheng wrote: > > > > > > > > > > > > 于 2020年11月28日 GMT+08:00 下午7:54:04, "Clément Péron" > > > 写到: > > > >Hi Icenowy, > > > > > > > >On Sat, 28 Nov 2020 at 12:28, Icenowy Zheng wrote: > > > >> > > > >> 在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道： > > > >> > On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote: > > > >> > > > > > > > Okay. But I'm not satisfied with a non-public sample > > > >> > > > > > > > occupies > > > >> > > > > > > > the pinetab name. Is rename it to pinetab-dev and add a > > > >> > > > > > > > pinetab-retail okay? > > > >> > > > > > > > > > >> > > > > > > To me, naming the production version anything but > > > >"pinetab" > > > >> > > > > > > isn't > > > >> > > > > > > satisfying either. > > > >> > > > > > > > > >> > > > > > I understand where you're coming from, but the point I was > > > >> > > > > > making my > > > >> > > > > > previous mail is precisely that it's not really possible. > > > >> > > > > > > > > >> > > > > > You want to name the early adopter version _the_ production > > > >> > > > > > version. Let's assume the hardware changes again between > > > >the > > > >> > > > > > early > > > >> > > > > > adopter and mass-production version. Which one will be > > > >_the_ > > > >> > > > > > production version? The early-adopter or the mass-produced > > > >> > > > > > one? > > > >> > > > > > > > > >> > > > > > There's really no good answer here, and both would suck in > > > >> > > > > > their > > > >> > > > > > own way. The only way to deal with this is to simply avoid > > > >> > > > > > defining one version as the one true board, and just > > > >loading > > > >> > > > > > the > > > >> > > > > > proper DT in u-boot based on whatever clue we have of the > > > >> > > > > > hardware > > > >> > > > > > revision. > > > >> > > > > Then will it be okay to rename current pinetab DT to > > > >> > > > > pinetab-sample and then introduce new DTs all with suffixes? > > > >> > > > > > > >> > > > No. From my previous mail: > > > >> > > > > > >> > > It can be seen as dropping the PineTab DT and introduce new DTs > > > >> > > with > > > >> > > suffix. > > > >> > > > > > >> > > Do we have rule that we cannot drop boards? > > > >> > > > > >> > Are you really arguing that removing a DT and then adding an > > > >> > identical > > > >> > one under a different name is not renaming it? > > > >> > > > >> Then we can just keep confusing name? > > > > > > > >Sorry maybe I missed some information > > > >But why don't you do like pinephone? > > > > > > They're the same board revision with different LCD panels. > > > > I just ask Pine64 about this and here is the reply : > > "The PineTab LCD panel change was a last minutes before production > > starts that vendor advise us switch over to new LCD controller due to > > EoL concern". > > > > "Pine64 communication" is not so bad we just need to ask and they reply :) > > > > So the issue is not that the Product was not finalized but that one > > component arrives in EoL. > > This could also happens during a running production. > > Like you said, it can happen pretty much any time, for any reason, so > the intent doesn't really matter here. Agree, that was more to support Pin64 guys here. As pinetab compatible can't be reused maybe somethings like this : sun50i-a64-pinetab.dtsi sun50i-a64-pinetab-1.0-early-adopter.dtb sun50i-a64-pinetab-1.0.dtb or sun50i-a64-pinetab-retail.dtb. But retail is like prod it's not explicit. What do you think ? Clement > > Maxime
Re: [PATCH 1/2] cpufreq: sun50i: add a100 cpufreq support
Hi Shuosheng,
On Sun, 6 Dec 2020 at 21:49, Clément Péron wrote:
>
> Hi Shuosheng,
>
> On 04/12/2020 08:09, Shuosheng Huang wrote:
> > Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> > let us use efuse_xlate to extract the differentiated part.
>
> So you introduce 2 modifications here.
> In this case it's better to have 2 patches.
> One to introduce the efuse_xlate
> And one to introduce the A100 support.
>
> Regards,
> Clement
>
> >
> > Signed-off-by: Shuosheng Huang
> > ---
> > drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> > drivers/cpufreq/sun50i-cpufreq-nvmem.c | 81 --
> > 2 files changed, 64 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> > b/drivers/cpufreq/cpufreq-dt-platdev.c
> > index 3776d960f405..2ebf5d9cb616 100644
> > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > @@ -102,6 +102,7 @@ static const struct of_device_id whitelist[]
> > __initconst = {
> >*/
> > static const struct of_device_id blacklist[] __initconst = {
> > { .compatible = "allwinner,sun50i-h6", },
> > + { .compatible = "allwinner,sun50i-a100", },
> >
> > { .compatible = "calxeda,highbank", },
> > { .compatible = "calxeda,ecx-2000", },
> > diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > index 9907a165135b..044e44a763f5 100644
> > --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > @@ -21,21 +21,63 @@
> >
> > #define NVMEM_MASK 0x7
> > #define NVMEM_SHIFT 5
> > +#define SUN50I_A100_NVMEM_MASK 0xf
> > +#define SUN50I_A100_NVMEM_SHIFT 12
> > +
> > +#define SUN50I_H6_NVMEM_MASK 0x7
> > +#define SUN50I_H6_NVMEM_SHIFT5
> > +
> > +struct sunxi_cpufreq_soc_data {
> > + u32 (*efuse_xlate)(void *efuse);
Maybe it's better to pass the speedbin_nvmem.
And call nvmem_cell_read_u16 or nvmem_cell_read_u32 regarding the SoC.
But I'm not a Maintainer.
Clement
> > +};
> >
> > static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
> >
> > +static u32 sun50i_a100_efuse_xlate(void *efuse)
> > +{
> > + u32 efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &
> > + SUN50I_A100_NVMEM_MASK;
> > +
> > + switch (efuse_value) {
> > + case 0b100:
> > + return 2;
> > + case 0b010:
> > + return 1;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > +static u32 sun50i_h6_efuse_xlate(void *efuse)
> > +{
> > + u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
> > + SUN50I_H6_NVMEM_MASK;
> > +
> > + /*
> > + * We treat unexpected efuse values as if the SoC was from
> > + * the slowest bin. Expected efuse values are 1-3, slowest
> > + * to fastest.
> > + */
> > + if (efuse_value >= 1 && efuse_value <= 3)
> > + return efuse_value - 1;
> > + else
> > + return 0;
> > +}
> > +
> > /**
> >* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
> > + * @soc_data: pointer to sunxi_cpufreq_soc_data context
> >* @versions: Set to the value parsed from efuse
> >*
> >* Returns 0 if success.
> >*/
> > -static int sun50i_cpufreq_get_efuse(u32 *versions)
> > +static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data
> > *soc_data,
> > + u32 *versions)
> > {
> > struct nvmem_cell *speedbin_nvmem;
> > struct device_node *np;
> > struct device *cpu_dev;
> > - u32 *speedbin, efuse_value;
> > + u32 *speedbin;
> > size_t len;
> > int ret;
> >
> > @@ -68,17 +110,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
> > if (IS_ERR(speedbin))
> > return PTR_ERR(speedbin);
> >
> > - efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
> > -
> > - /*
> > - * We treat unexpected efuse values as if the SoC was from
> > - * the slowest bin. Expected efuse values are 1-3, slowest
> > - * to fastest.
> > -
Re: [PATCH 1/2] cpufreq: sun50i: add a100 cpufreq support
Hi Shuosheng,
On 04/12/2020 08:09, Shuosheng Huang wrote:
Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
let us use efuse_xlate to extract the differentiated part.
So you introduce 2 modifications here.
In this case it's better to have 2 patches.
One to introduce the efuse_xlate
And one to introduce the A100 support.
Regards,
Clement
Signed-off-by: Shuosheng Huang
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 81 --
2 files changed, 64 insertions(+), 18 deletions(-)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3776d960f405..2ebf5d9cb616 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = {
*/
static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "allwinner,sun50i-h6", },
+ { .compatible = "allwinner,sun50i-a100", },
{ .compatible = "calxeda,highbank", },
{ .compatible = "calxeda,ecx-2000", },
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 9907a165135b..044e44a763f5 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -21,21 +21,63 @@
#define NVMEM_MASK 0x7
#define NVMEM_SHIFT 5
+#define SUN50I_A100_NVMEM_MASK 0xf
+#define SUN50I_A100_NVMEM_SHIFT12
+
+#define SUN50I_H6_NVMEM_MASK 0x7
+#define SUN50I_H6_NVMEM_SHIFT 5
+
+struct sunxi_cpufreq_soc_data {
+ u32 (*efuse_xlate)(void *efuse);
+};
static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+static u32 sun50i_a100_efuse_xlate(void *efuse)
+{
+ u32 efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &
+ SUN50I_A100_NVMEM_MASK;
+
+ switch (efuse_value) {
+ case 0b100:
+ return 2;
+ case 0b010:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static u32 sun50i_h6_efuse_xlate(void *efuse)
+{
+ u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
+ SUN50I_H6_NVMEM_MASK;
+
+ /*
+* We treat unexpected efuse values as if the SoC was from
+* the slowest bin. Expected efuse values are 1-3, slowest
+* to fastest.
+*/
+ if (efuse_value >= 1 && efuse_value <= 3)
+ return efuse_value - 1;
+ else
+ return 0;
+}
+
/**
* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
+ * @soc_data: pointer to sunxi_cpufreq_soc_data context
* @versions: Set to the value parsed from efuse
*
* Returns 0 if success.
*/
-static int sun50i_cpufreq_get_efuse(u32 *versions)
+static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data
*soc_data,
+ u32 *versions)
{
struct nvmem_cell *speedbin_nvmem;
struct device_node *np;
struct device *cpu_dev;
- u32 *speedbin, efuse_value;
+ u32 *speedbin;
size_t len;
int ret;
@@ -68,17 +110,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
if (IS_ERR(speedbin))
return PTR_ERR(speedbin);
- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
-
- /*
-* We treat unexpected efuse values as if the SoC was from
-* the slowest bin. Expected efuse values are 1-3, slowest
-* to fastest.
-*/
- if (efuse_value >= 1 && efuse_value <= 3)
- *versions = efuse_value - 1;
- else
- *versions = 0;
+ *versions = soc_data->efuse_xlate(speedbin);
kfree(speedbin);
return 0;
@@ -86,18 +118,23 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
{
+ const struct of_device_id *match;
struct opp_table **opp_tables;
char name[MAX_NAME_LEN];
unsigned int cpu;
u32 speed = 0;
int ret;
+ match = dev_get_platdata(&pdev->dev);
+ if (!match)
+ return -EINVAL;
+
opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables),
GFP_KERNEL);
if (!opp_tables)
return -ENOMEM;
- ret = sun50i_cpufreq_get_efuse(&speed);
+ ret = sun50i_cpufreq_get_efuse(match->data, &speed);
if (ret)
return ret;
@@ -163,8 +200,17 @@ static struct platform_driver sun50i_cpufreq_driver = {
},
};
+static const struct sunxi_cpufreq_soc_data sun50i_a100_data = {
+ .efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
+static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
+ .efuse_xlate = sun50i_h6_efuse_xlate,
+};
+
static const struct of_device_id sun50i_cpuf
Re: [linux-sunxi] [PATCH 8/8] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
Hi Andre,
On Wed, 2 Dec 2020 at 14:54, Andre Przywara wrote:
>
> The OrangePi Zero 2 is a development board with the new H616 SoC.
>
> It features the usual connectors used on those small boards, and comes
> with the AXP305, which seems to be compatible with the AXP805.
>
> For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm64/boot/dts/allwinner/Makefile| 1 +
> .../allwinner/sun50i-h616-orangepi-zero2.dts | 228 ++
> 2 files changed, 229 insertions(+)
> create mode 100644
> arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile
> b/arch/arm64/boot/dts/allwinner/Makefile
> index 211d1e9d4701..0cf8299b1ce7 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> new file mode 100644
> index ..814f5b4fec7c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> @@ -0,0 +1,228 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2020 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-h616.dtsi"
> +
> +#include
> +#include
> +
> +/ {
> + model = "OrangePi Zero2";
> + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
You need to add this compatible to the sunxi.yaml boards list
> +
> + aliases {
> + ethernet0 = &emac0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + power {
> + label = "orangepi:red:power";
label is deprecated
function = LED_FUNCTION_POWER;
color = ;
> + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
> + default-state = "on";
> + };
> +
> + status {
> + label = "orangepi:green:status";
same here
function = LED_FUNCTION_STATUS;
color = ;
> + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
> + };
> + };
> +
> + reg_vcc5v: vcc5v {
> + /* board wide 5V supply directly from the USB-C socket */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-5v";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + regulator-always-on;
> + };
> +
> + reg_usb1_vbus: usb1-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usb1-vbus";
Could you add reg_vcc5v as vin-supply.
This doesn't change anything but will be a better description of the HW.
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + enable-active-high;
> + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
> + status = "okay";
> + };
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +/* USB 2 & 3 are on headers only. */
> +
> +&emac0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ext_rgmii_pins>;
> + phy-mode = "rgmii";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-supply = <®_dcdce>;
> + allwinner,rx-delay-ps = <3100>;
> + allwinner,tx-delay-ps = <700>;
> + status = "okay";
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdce>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&r_i2c {
> + status = "okay";
> +
> + axp305: pmic@36 {
> + compatible = "x-powers,axp305", "x-powers,axp805",
> +"x-powers,axp806";
> + reg = <0x36>;
> +
> + /* dummy interrupt to appease the driver for now */
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + x-powers,self-working-mode;
> + vina-supply = <®_vcc5v>;
> + vinb-supply = <®_vcc5v>;
>
Re: [linux-sunxi] [PATCH 2/8] pinctrl: sunxi: Add support for the Allwinner H616 pin controller
Hi Andre,
On Wed, 2 Dec 2020 at 14:54, Andre Przywara wrote:
>
> Port A is used for an internal connection to some analogue circuitry
> which looks like an AC200 IP (as in the H6), though this is not
> mentioned in the manual.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/pinctrl/sunxi/Kconfig | 5 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 549
> 3 files changed, 555 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 593293584ecc..73e88ce71a48 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -119,4 +119,9 @@ config PINCTRL_SUN50I_H6_R
> default ARM64 && ARCH_SUNXI
> select PINCTRL_SUNXI
>
> +config PINCTRL_SUN50I_H616
> + bool "Support for the Allwinner H616 PIO"
> + default ARM64 && ARCH_SUNXI
> + select PINCTRL_SUNXI
> +
> endif
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 8b7ff0dc3bdf..5359327a3c8f 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -23,5 +23,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_V3S) +=
> pinctrl-sun8i-v3s.o
> obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
> obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
> obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
> +obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
> obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
> obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
> b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
> new file mode 100644
> index ..734f63eb08dd
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
> @@ -0,0 +1,549 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Allwinner H616 SoC pinctrl driver.
> + *
> + * Copyright (C) 2020 Arm Ltd.
> + * based on the H6 pinctrl driver
> + * Copyright (C) 2017 Icenowy Zheng
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin h616_pins[] = {
> + /* Internal connection to the AC200 part */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
> + SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
> + SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
> + SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
> + SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
> + SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
> + SUNXI_FUNCTION(0x2, "pwm5")),
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
> + SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PC_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PC_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
> + SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
>
Re: [linux-sunxi] Re: [PATCH 3/3] arm64: allwinner: dts: a64: add DT for PineTab developer sample
Hi Icenowy, On Sat, 28 Nov 2020 at 12:28, Icenowy Zheng wrote: > > 在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道： > > On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote: > > > > > > > > Okay. But I'm not satisfied with a non-public sample > > > > > > > > occupies > > > > > > > > the pinetab name. Is rename it to pinetab-dev and add a > > > > > > > > pinetab-retail okay? > > > > > > > > > > > > > > To me, naming the production version anything but "pinetab" > > > > > > > isn't > > > > > > > satisfying either. > > > > > > > > > > > > I understand where you're coming from, but the point I was > > > > > > making my > > > > > > previous mail is precisely that it's not really possible. > > > > > > > > > > > > You want to name the early adopter version _the_ production > > > > > > version. Let's assume the hardware changes again between the > > > > > > early > > > > > > adopter and mass-production version. Which one will be _the_ > > > > > > production version? The early-adopter or the mass-produced > > > > > > one? > > > > > > > > > > > > There's really no good answer here, and both would suck in > > > > > > their > > > > > > own way. The only way to deal with this is to simply avoid > > > > > > defining one version as the one true board, and just loading > > > > > > the > > > > > > proper DT in u-boot based on whatever clue we have of the > > > > > > hardware > > > > > > revision. > > > > > Then will it be okay to rename current pinetab DT to > > > > > pinetab-sample and then introduce new DTs all with suffixes? > > > > > > > > No. From my previous mail: > > > > > > It can be seen as dropping the PineTab DT and introduce new DTs > > > with > > > suffix. > > > > > > Do we have rule that we cannot drop boards? > > > > Are you really arguing that removing a DT and then adding an > > identical > > one under a different name is not renaming it? > > Then we can just keep confusing name? Sorry maybe I missed some information But why don't you do like pinephone? sun50i-a64-pinetab-1.0.dts sun50i-a64-pinetab-1.1.dts -dev is also a confusing name I think, as the board has been already shipped. Regards, Clement > > If we do so, how can we mark the new DT as "the user should use this > one"? > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > To view this discussion on the web, visit > https://groups.google.com/d/msgid/linux-sunxi/1666a61f6ea3e7d573795f9000a0b096c7b7dee0.camel%40aosc.io.
Re: [linux-sunxi] Re: [PATCH 3/3] arm64: allwinner: dts: a64: add DT for PineTab developer sample
Hi Maxime, Icenowy, On Sat, 28 Nov 2020 at 12:59, Icenowy Zheng wrote: > > > > 于 2020年11月28日 GMT+08:00 下午7:54:04, "Clément Péron" 写到: > >Hi Icenowy, > > > >On Sat, 28 Nov 2020 at 12:28, Icenowy Zheng wrote: > >> > >> 在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道： > >> > On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote: > >> > > > > > > > Okay. But I'm not satisfied with a non-public sample > >> > > > > > > > occupies > >> > > > > > > > the pinetab name. Is rename it to pinetab-dev and add a > >> > > > > > > > pinetab-retail okay? > >> > > > > > > > >> > > > > > > To me, naming the production version anything but > >"pinetab" > >> > > > > > > isn't > >> > > > > > > satisfying either. > >> > > > > > > >> > > > > > I understand where you're coming from, but the point I was > >> > > > > > making my > >> > > > > > previous mail is precisely that it's not really possible. > >> > > > > > > >> > > > > > You want to name the early adopter version _the_ production > >> > > > > > version. Let's assume the hardware changes again between > >the > >> > > > > > early > >> > > > > > adopter and mass-production version. Which one will be > >_the_ > >> > > > > > production version? The early-adopter or the mass-produced > >> > > > > > one? > >> > > > > > > >> > > > > > There's really no good answer here, and both would suck in > >> > > > > > their > >> > > > > > own way. The only way to deal with this is to simply avoid > >> > > > > > defining one version as the one true board, and just > >loading > >> > > > > > the > >> > > > > > proper DT in u-boot based on whatever clue we have of the > >> > > > > > hardware > >> > > > > > revision. > >> > > > > Then will it be okay to rename current pinetab DT to > >> > > > > pinetab-sample and then introduce new DTs all with suffixes? > >> > > > > >> > > > No. From my previous mail: > >> > > > >> > > It can be seen as dropping the PineTab DT and introduce new DTs > >> > > with > >> > > suffix. > >> > > > >> > > Do we have rule that we cannot drop boards? > >> > > >> > Are you really arguing that removing a DT and then adding an > >> > identical > >> > one under a different name is not renaming it? > >> > >> Then we can just keep confusing name? > > > >Sorry maybe I missed some information > >But why don't you do like pinephone? > > They're the same board revision with different LCD panels. I just ask Pine64 about this and here is the reply : "The PineTab LCD panel change was a last minutes before production starts that vendor advise us switch over to new LCD controller due to EoL concern". "Pine64 communication" is not so bad we just need to ask and they reply :) So the issue is not that the Product was not finalized but that one component arrives in EoL. This could also happens during a running production. Regards, Clement > > And the major problem is that the DT for samples is already submitted > under the name "PineTab". > > >sun50i-a64-pinetab-1.0.dts > >sun50i-a64-pinetab-1.1.dts > > > >-dev is also a confusing name I think, as the board has been already > >shipped. > > > >Regards, > >Clement > > > > > >> > >> If we do so, how can we mark the new DT as "the user should use this > >> one"? > >> > >> -- > >> You received this message because you are subscribed to the Google > >Groups "linux-sunxi" group. > >> To unsubscribe from this group and stop receiving emails from it, > >send an email to linux-sunxi+unsubscr...@googlegroups.com. > >> To view this discussion on the web, visit > >https://groups.google.com/d/msgid/linux-sunxi/1666a61f6ea3e7d573795f9000a0b096c7b7dee0.camel%40aosc.io.
Re: devfreq and panfrost on Allwinner H6
HI Tomeu, On Wed, 7 Oct 2020 at 19:49, Clément Péron wrote: > > Hi Tomeu, > > On Wed, 7 Oct 2020 at 10:58, Tomeu Vizoso wrote: > > > > Hi Clément, > > > > Have just noticed that my Pine H64 board hangs when I try to set the > > performance governor for the GPU devfreq. > > > > Is this a known bug? > Yes it is. > > I try to summarize everything in this message: > https://lkml.org/lkml/2020/8/3/153 Finally got it working with Jernej's help by setting a fixed frequency to the GPU PLL. https://github.com/clementperon/linux/commits/h6_gpu_devfreq # glmark2-es2-drm --off-screen === glmark2 2020.04 === OpenGL Information GL_VENDOR: Panfrost GL_RENDERER: Mali T720 (Panfrost) GL_VERSION:OpenGL ES 3.0 Mesa 20.2.2 === [build] use-vbo=false: FPS: 182 FrameTime: 5.495 ms [build] use-vbo=true: FPS: 528 FrameTime: 1.894 ms [texture] texture-filter=nearest: FPS: 604 FrameTime: 1.656 ms [texture] texture-filter=linear: FPS: 599 FrameTime: 1.669 ms [texture] texture-filter=mipmap: FPS: 581 FrameTime: 1.721 ms [shading] shading=gouraud: FPS: 418 FrameTime: 2.392 ms [shading] shading=blinn-phong-inf: FPS: 386 FrameTime: 2.591 ms [shading] shading=phong: FPS: 325 FrameTime: 3.077 ms [shading] shading=cel: FPS: 308 FrameTime: 3.247 ms [bump] bump-render=high-poly: FPS: 214 FrameTime: 4.673 ms [bump] bump-render=normals: FPS: 518 FrameTime: 1.931 ms [bump] bump-render=height: FPS: 501 FrameTime: 1.996 ms [effect2d] kernel=0,1,0;1,-4,1;0,1,0;: FPS: 295 FrameTime: 3.390 ms [effect2d] kernel=1,1,1,1,1;1,1,1,1,1;1,1,1,1,1;: FPS: 82 FrameTime: 12.195 ms [pulsar] light=false:quads=5:texture=false: FPS: 507 FrameTime: 1.972 ms [desktop] blur-radius=5:effect=blur:passes=1:separable=true:windows=4: FPS: 46 FrameTime: 21.739 ms [desktop] effect=shadow:windows=4: FPS: 172 FrameTime: 5.814 ms [buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction=0.5:update-method=map: FPS: 34 FrameTime: 29.412 ms [buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction=0.5:update-method=subdata: FPS: 33 FrameTime: 30.303 ms [buffer] columns=200:interleave=true:update-dispersion=0.9:update-fraction=0.5:update-method=map: FPS: 40 FrameTime: 25.000 ms [ideas] speed=duration: FPS: 66 FrameTime: 15.152 ms [jellyfish] : FPS: 158 FrameTime: 6.329 ms [terrain] : FPS: 12 FrameTime: 83.333 ms [shadow] : FPS: 211 FrameTime: 4.739 ms [refract] : FPS: 45 FrameTime: 22.222 ms [conditionals] fragment-steps=0:vertex-steps=0: FPS: 654 FrameTime: 1.529 ms [conditionals] fragment-steps=5:vertex-steps=0: FPS: 296 FrameTime: 3.378 ms [conditionals] fragment-steps=0:vertex-steps=5: FPS: 645 FrameTime: 1.550 ms [function] fragment-complexity=low:fragment-steps=5: FPS: 468 FrameTime: 2.137 ms [function] fragment-complexity=medium:fragment-steps=5: FPS: 289 FrameTime: 3.460 ms [loop] fragment-loop=false:fragment-steps=5:vertex-steps=5: FPS: 459 FrameTime: 2.179 ms [loop] fragment-steps=5:fragment-uniform=false:vertex-steps=5: FPS: 460 FrameTime: 2.174 ms [loop] fragment-steps=5:fragment-uniform=true:vertex-steps=5: FPS: 218 FrameTime: 4.587 ms === glmark2 Score: 313 === Regards, Clement > > Clement > > > > > Thanks, > > > > Tomeu
Re: [PATCH v4 09/22] arm64: dts: allwinner: h6: Add HDMI audio node
Hi Maxime,
On Mon, 2 Nov 2020 at 11:21, Maxime Ripard wrote:
>
> On Sun, Nov 01, 2020 at 04:27:05PM +0100, Clément Péron wrote:
> > On Wed, 30 Sep 2020 at 12:19, Maxime Ripard wrote:
> > >
> > > On Mon, Sep 28, 2020 at 04:27:42PM +0200, Clément Péron wrote:
> > > > On Mon, 28 Sep 2020 at 10:43, Maxime Ripard wrote:
> > > > >
> > > > > On Mon, Sep 21, 2020 at 08:37:09PM +0200, Jernej Škrabec wrote:
> > > > > > Dne ponedeljek, 21. september 2020 ob 19:23:49 CEST je Clément Péron
> > > > > > napisal(a):
> > > > > > > Hi Maxime,
> > > > > > >
> > > > > > > On Mon, 21 Sep 2020 at 15:59, Maxime Ripard
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > On Mon, Sep 21, 2020 at 12:27:18PM +0200, Clément Péron wrote:
> > > > > > > > > From: Jernej Skrabec
> > > > > > > > >
> > > > > > > > > Add a simple-soundcard to link audio between HDMI and I2S.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Jernej Skrabec
> > > > > > > > > Signed-off-by: Marcus Cooper
> > > > > > > > > Signed-off-by: Clément Péron
> > > > > > > > > ---
> > > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33
> > > > > > > > >
> > > > > > > > > 1 file changed, 33 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > b/arch/arm64/
> > > > > > boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > index 28c77d6872f6..a8853ee7885a 100644
> > > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > @@ -67,6 +67,25 @@ de: display-engine {
> > > > > > > > > status = "disabled";
> > > > > > > > > };
> > > > > > > > >
> > > > > > > > > + hdmi_sound: hdmi-sound {
> > > > > > > > > + compatible = "simple-audio-card";
> > > > > > > > > + simple-audio-card,format = "i2s";
> > > > > > > > > + simple-audio-card,name = "sun50i-h6-hdmi";
> > > > > > > > > + simple-audio-card,mclk-fs = <128>;
> > > > > > > > > + simple-audio-card,frame-inversion;
> > > > > > > > > + status = "disabled";
> > > > > > > > > +
> > > > > > > > > + simple-audio-card,codec {
> > > > > > > > > + sound-dai = <&hdmi>;
> > > > > > > > > + };
> > > > > > > > > +
> > > > > > > > > + simple-audio-card,cpu {
> > > > > > > > > + sound-dai = <&i2s1>;
> > > > > > > > > + dai-tdm-slot-num = <2>;
> > > > > > > > > + dai-tdm-slot-width = <32>;
> > > > > > > >
> > > > > > > > It looks weird to have both some TDM setup here, and yet the
> > > > > > > > format in
> > > > > > > > i2s?
> >
> >
> > I was looking at sound documentation regarding how I can properly
> > write the multi-lane I2S support.
> > And I think we made a wrong interpretation here.
> >
> > TDM slot-num and slot-width are not referencing the format called PCM
> > or DSP_A / DSP_B.
> > But really the physical time division representation of a format.
> >
> > For example Amlogic do the following representation for Multi-lane I2S:
> >
> > dai-link-7 {
> > sound-dai = <&tdmif_b>;
> > dai-format = "i2s";
> > dai-tdm-slot-tx-mask-0 = <1 1>;
> > dai-tdm-slot-tx-mask-1 = <1 1>;
> > dai-tdm-slot-tx-mask-2 = <1 1>;
> > dai-tdm-slot-tx-mask-3 = <1 1>;
> > mclk-fs = <256>;
> >
> > codec {
> > sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
> > };
> > };
> >
> > So i think for 2 channels HDMI using the simple sound card with TDM
> > property is not a hack but the correct way to represent it.
> >
> > Do you agree ?
> >
> > If so, can I resend the simple sound card for HDMI audio ?
>
> I mean, it's not less weird :)
>
> And like I said before we still have the option to write a card driver
> ourselves that doesn't take anything from the DT beside the phandle of
> the i2s controller and the HDMI controller.
>
> If it's a fixed configuration, I'm not sure why we bother trying to make
> it dynamic in the DT.
Ok I see what you mean here, as the link is hardcoded in the SoC it's
a better representation to hardcode it in the sound card driver than
having it dynamically represented in each board device-tree.
Sounds correct for me,
Thanks :)
>
> Maxime
ASoC: Question regarding device-tree multi-lane I2S for Allwinner SoC
Hi device-tree and sound Maintainers,
I have a question regarding multi-lane i2S representation.
On the Allwinner SoC the I2S/PCM Interface can handle up to four lanes
as output or input.
For each lane we can enable up to sixteen slots.
And for each output slot we can choose which slot to map.
The only representation I found is for Amlogic device-tree they did
the following sound node :
/* 8ch hdmi interface */
dai-link-7 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
This kind of representation gives the information that 2 slots should
be enabled as TX per lane but don't give which slot to map.
I was thinking about a representation per lane but maybe it's a bit
complicated ?
dai-format = "dsp_a";
dai-tdm-slot-width = <32>;
// Lane 0 : Output 8 channels 0-7 using TDM
dai-tdm-slot-tx-mask-0 = <1 1 1 1 1 1 1 1>;
dai-tdm-slot-chmap-0 = <0 1 2 3 4 5 6 7>;
// Lane 1 : Output 3 channels 5-7 using TDM
dai-tdm-slot-tx-mask-1 = <1 1 1>;
dai-tdm-slot-chmap-1 = <5 6 7>;
I will only start to support HDMI, so 4 I2S lanes for now it should
look like this
dai-format = "i2s";
dai-tdm-slot-width = <32>;
frame-inversion;
// Lane 0 : Output channels 0,1
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-chmap-0 = <0 1>;
// Lane 1: Output channels 2,3
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-chmap-1 = <2 3>;
// Lane 2: Output channels 4,5
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-chmap-2 = <4 5>;
// Lane 3: Output channels 6,7
dai-tdm-slot-tx-mask-3 = <1 1>;
dai-tdm-slot-chmap-3 = <6 7>;
What do you think? Do you have any remark / idea about this ?
Thanks for your help
Clement
Re: [PATCH v4 09/22] arm64: dts: allwinner: h6: Add HDMI audio node
Hi Maxime,
On Wed, 30 Sep 2020 at 12:19, Maxime Ripard wrote:
>
> On Mon, Sep 28, 2020 at 04:27:42PM +0200, Clément Péron wrote:
> > On Mon, 28 Sep 2020 at 10:43, Maxime Ripard wrote:
> > >
> > > On Mon, Sep 21, 2020 at 08:37:09PM +0200, Jernej Škrabec wrote:
> > > > Dne ponedeljek, 21. september 2020 ob 19:23:49 CEST je Clément Péron
> > > > napisal(a):
> > > > > Hi Maxime,
> > > > >
> > > > > On Mon, 21 Sep 2020 at 15:59, Maxime Ripard wrote:
> > > > > >
> > > > > > On Mon, Sep 21, 2020 at 12:27:18PM +0200, Clément Péron wrote:
> > > > > > > From: Jernej Skrabec
> > > > > > >
> > > > > > > Add a simple-soundcard to link audio between HDMI and I2S.
> > > > > > >
> > > > > > > Signed-off-by: Jernej Skrabec
> > > > > > > Signed-off-by: Marcus Cooper
> > > > > > > Signed-off-by: Clément Péron
> > > > > > > ---
> > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33
> > > > > > >
> > > > > > > 1 file changed, 33 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > b/arch/arm64/
> > > > boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > index 28c77d6872f6..a8853ee7885a 100644
> > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > @@ -67,6 +67,25 @@ de: display-engine {
> > > > > > > status = "disabled";
> > > > > > > };
> > > > > > >
> > > > > > > + hdmi_sound: hdmi-sound {
> > > > > > > + compatible = "simple-audio-card";
> > > > > > > + simple-audio-card,format = "i2s";
> > > > > > > + simple-audio-card,name = "sun50i-h6-hdmi";
> > > > > > > + simple-audio-card,mclk-fs = <128>;
> > > > > > > + simple-audio-card,frame-inversion;
> > > > > > > + status = "disabled";
> > > > > > > +
> > > > > > > + simple-audio-card,codec {
> > > > > > > + sound-dai = <&hdmi>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + simple-audio-card,cpu {
> > > > > > > + sound-dai = <&i2s1>;
> > > > > > > + dai-tdm-slot-num = <2>;
> > > > > > > + dai-tdm-slot-width = <32>;
> > > > > >
> > > > > > It looks weird to have both some TDM setup here, and yet the format
> > > > > > in
> > > > > > i2s?
I was looking at sound documentation regarding how I can properly
write the multi-lane I2S support.
And I think we made a wrong interpretation here.
TDM slot-num and slot-width are not referencing the format called PCM
or DSP_A / DSP_B.
But really the physical time division representation of a format.
For example Amlogic do the following representation for Multi-lane I2S:
dai-link-7 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
So i think for 2 channels HDMI using the simple sound card with TDM
property is not a hack but the correct way to represent it.
Do you agree ?
If so, can I resend the simple sound card for HDMI audio ?
Thanks,
Clement
> > > > >
> > > > > Yes, I agree I will check if it's really needed.
> > > >
> > > > I think this was explained before.
> > >
> > > Possibly, but this should be in a comment or at least the commit log
> > >
> > > > Anyway, this is needed to force width to 32, no matter actual sample
> > > > width. That's a requirement of HDMI codec. I believe Marcus Cooper
> > > > have another codec which also needs fixed width.
> > > >
> > > > There is no similar property for I2S, so TDM one is used here.
> > >
> > > Except it's really dedicated to the TDM mode and doesn't really make
> > > much sense here.
> > >
> > > If we have special requirements like this on the codec setup, that
> > > sounds like a good justification for creating a custom codec instead of
> > > shoehorning it into simple-card
> >
> > When all the remarks are fixed would it be possible to merge the rest
> > of the series without the dts changes ?
> >
> > I will propose another series to introduce a dedicated codec for that.
>
> Yeah, sure
>
> Maxime
Re: [PATCH v10 01/15] ASoC: sun4i-i2s: Fix lrck_period computation for I2S justified mode
Hi Maxime,
On Fri, 30 Oct 2020 at 17:11, Maxime Ripard wrote:
>
> On Fri, Oct 30, 2020 at 03:46:34PM +0100, Clément Péron wrote:
> > Left and Right justified mode are computed using the same formula
> > as DSP_A and DSP_B mode.
> > Which is wrong and the user manual explicitly says:
> >
> > LRCK_PERDIOD:
> > PCM Mode: Number of BCLKs within (Left + Right) channel width.
> > I2S/Left-Justified/Right-Justified Mode: Number of BCLKs within each
> > individual channel width(Left or Right)
> >
> > Fix this by using the same formula as the I2S mode.
> >
> > Fixes: 7ae7834ec446 ("ASoC: sun4i-i2s: Add support for DSP formats")
> > Signed-off-by: Clément Péron
>
> Acked-by: Maxime Ripard
Thanks for the ACK
just noticed that the case was not properly sorted.
Do you agree that sorting like this is better ?
case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
If I have to push a new series I will fix it
Regards,
Clement
> Thanks!
> Maxime
Re: [PATCH v10 14/15] dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility
Hi Mark,
On Fri, 30 Oct 2020 at 19:19, Mark Brown wrote:
>
> On Fri, Oct 30, 2020 at 03:46:47PM +0100, Clément Péron wrote:
> > Like A83T the Allwinner H3 doesn't have the DMA reception available for
> > some audio interfaces.
>
> Please if you're going to mix dts updates in with subsystem changes like
> this keep the bits for different subsystems grouped, this makes it much
> easier to handle things.
>
> Please submit patches using subject lines reflecting the style for the
> subsystem, this makes it easier for people to identify relevant patches.
> Look at what existing commits in the area you're changing are doing and
> make sure your subject lines visually resemble what they're doing.
> There's no need to resubmit to fix this alone.
Sorry i have based the commit log on this file regarding the previous
commit and it was these:
5c7404bb30bc ("dt-bindings: Change maintainer address")
eb5b12843b06 ("dt-bindings: sound: sun4i-i2s: Document that the RX
channel can be missing")
0a0ca8e94ca3 ("dt-bindings: sound: Convert Allwinner I2S binding to YAML")
But basically for the next dt-bindings change you will prefer somethings like:
"ASoC: dt-bindings: sun4i-i2s: Document H3 with missing RX channel possibility"
Regards,
Clement
[PATCH v10 08/15] ASoC: sun4i-i2s: Fix setting of FIFO modes
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 003610c0badf..4f5cd850752d 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -596,6 +596,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
return ret;
}
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -924,13 +931,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
return ret;
}
- /* Set significant bits in our FIFOs */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
- SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
-
i2s->format = fmt;
return 0;
--
2.25.1
[PATCH v10 10/15] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible
From: Jernej Skrabec H6 I2S is very similar to H3, except that it supports up to 16 channels and thus few registers have fields on different position. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Acked-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 112ae00d63c1..606ad2d884a8 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -24,6 +24,7 @@ properties: - items: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s + - const: allwinner,sun50i-h6-i2s reg: maxItems: 1 @@ -59,6 +60,7 @@ allOf: - allwinner,sun8i-a83t-i2s - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s + - allwinner,sun50i-h6-i2s then: required: -- 2.25.1
[PATCH v10 14/15] dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility
Like A83T the Allwinner H3 doesn't have the DMA reception available for some audio interfaces. As it's already documented for A83T convert this to an enum and add the H3 interface. Acked-by: Rob Herring Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 606ad2d884a8..a16e37b01e1d 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -70,7 +70,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun8i-a83t-i2s +enum: + - allwinner,sun8i-a83t-i2s + - allwinner,sun8i-h3-i2s then: properties: -- 2.25.1
[PATCH v10 15/15] arm: dts: sunxi: h3/h5: Add I2S2 node
From: Marcus Cooper
Add H3/H5 I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 22d533d18992..9be13378d4df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -662,6 +662,19 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-codec";
--
2.25.1
[PATCH v10 07/15] ASoC: sun4i-i2s: Fix sun8i volatile regs
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 786731191d90..003610c0badf 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1162,12 +1162,19 @@ static bool sun8i_i2s_rd_reg(struct device *dev,
unsigned int reg)
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
- if (reg == SUN8I_I2S_INT_STA_REG)
+ switch (reg) {
+ case SUN4I_I2S_FIFO_CTRL_REG:
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ case SUN8I_I2S_FIFO_TX_REG:
+ case SUN8I_I2S_INT_STA_REG:
return true;
- if (reg == SUN8I_I2S_FIFO_TX_REG)
- return false;
- return sun4i_i2s_volatile_reg(dev, reg);
+ default:
+ return false;
+ }
}
static const struct reg_default sun4i_i2s_reg_defaults[] = {
--
2.25.1
[PATCH v10 09/15] ASoC: sun4i-i2s: fix coding-style for callback definition
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 4f5cd850752d..4b8ca5be0a29 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -180,7 +180,7 @@ struct sun4i_i2s_quirks {
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned intnum_mclk_dividers;
- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
@@ -192,7 +192,7 @@ struct sun4i_i2s_quirks {
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
- int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
--
2.25.1
[PATCH v10 11/15] arm64: dts: allwinner: h6: Add I2S1 node
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 28c77d6872f6..d915aeb13297 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -609,6 +609,19 @@ mdio: mdio {
};
};
+ i2s1: i2s@5091000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x05091000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
--
2.25.1
[PATCH v10 12/15] arm64: dts: allwinner: a64: Add I2S2 node
From: Marcus Cooper
Add the I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dc238814013c..51cc30e84e26 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -846,6 +846,20 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+"allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 27>, <&dma 27>;
+ status = "disabled";
+ };
+
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-codec-i2s";
--
2.25.1
[PATCH v10 13/15] arm64: defconfig: Enable Allwinner i2s driver
Enable Allwinner I2S driver for arm64 defconfig. Acked-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..3f89f427a355 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m -- 2.25.1
[PATCH v10 00/15] Add Allwinner H3/H5/H6/A64 HDMI audio
Hi, This series add H6 I2S support and the I2S node missing to support HDMI audio in different Allwinner SoC. As we first use some TDM property to make the I2S working with the simple soundcard. We have now drop this simple sound card and a proper dedicated soundcard will be introduce later. This make the title of this series wrong now but to be able to follow the previous release I keep the same name. Regards, Clement Change since v9: - fix lrck_period computation for I2S justified mode Change since v8: - move the comment near the function prototype - collect Maxime Ripard tags Change since v7: - rebase on next-20201026 - comment about slots and slot_width Change since v6: - move set_channel_cfg() in first position - convert return value to decimal Change since v5: - Drop HDMI simple soundcard - Collect Chen-Yu Tsai tags - Configure channels from 9 to 15. - Remove DMA RX for H3/H5 - Fix Documentation for H3/H5 Change since v4: - add more comment on get_wss() and set_channel_cfg() patch - merge soundcard and DAI HDMI patches Change since v3: - add Samuel Holland patch to reconfigure FIFO_TX_REG when suspend is enabled - readd inversion to H6 LRCK sun50i_h6_i2s_set_soc_fmt() - Fix get_wss() for sun4i - Add a commit to fix checkpatch warning Change since v2: - rebase on next-20200918 - drop revert LRCK polarity patch - readd simple-audio-card,frame-inversion in dts - Add patch for changing set_chan_cfg params Change since v1: - rebase on next-20200828 - add revert LRCK polarity - remove all simple-audio-card,frame-inversion in dts - add Ondrej patches for Orange Pi board - Add arm64 defconfig patch Clément Péron (7): ASoC: sun4i-i2s: Fix lrck_period computation for I2S justified mode ASoC: sun4i-i2s: Change set_chan_cfg() params ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit ASoC: sun4i-i2s: Fix sun8i volatile regs ASoC: sun4i-i2s: fix coding-style for callback definition arm64: defconfig: Enable Allwinner i2s driver dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility Jernej Skrabec (3): ASoC: sun4i-i2s: Add support for H6 I2S dt-bindings: ASoC: sun4i-i2s: Add H6 compatible arm64: dts: allwinner: h6: Add I2S1 node Marcus Cooper (4): ASoC: sun4i-i2s: Set sign extend sample ASoC: sun4i-i2s: Add 20 and 24 bit support arm64: dts: allwinner: a64: Add I2S2 node arm: dts: sunxi: h3/h5: Add I2S2 node Samuel Holland (1): ASoC: sun4i-i2s: Fix setting of FIFO modes .../sound/allwinner,sun4i-a10-i2s.yaml| 6 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi| 13 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 + arch/arm64/configs/defconfig | 1 + sound/soc/sunxi/sun4i-i2s.c | 388 +++--- 6 files changed, 378 insertions(+), 57 deletions(-) -- 2.25.1
[PATCH v10 06/15] ASoC: sun4i-i2s: Add 20 and 24 bit support
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 46e4da18c27f..786731191d90 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -600,6 +600,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1081,6 +1084,10 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+SNDRV_PCM_FMTBIT_S20_LE | \
+SNDRV_PCM_FMTBIT_S24_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1088,14 +1095,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
--
2.25.1
[PATCH v10 01/15] ASoC: sun4i-i2s: Fix lrck_period computation for I2S justified mode
Left and Right justified mode are computed using the same formula
as DSP_A and DSP_B mode.
Which is wrong and the user manual explicitly says:
LRCK_PERDIOD:
PCM Mode: Number of BCLKs within (Left + Right) channel width.
I2S/Left-Justified/Right-Justified Mode: Number of BCLKs within each
individual channel width(Left or Right)
Fix this by using the same formula as the I2S mode.
Fixes: 7ae7834ec446 ("ASoC: sun4i-i2s: Add support for DSP formats")
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index f23ff29e7c1d..a994b5cf87b3 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -450,11 +450,11 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
- case SND_SOC_DAIFMT_LEFT_J:
- case SND_SOC_DAIFMT_RIGHT_J:
lrck_period = params_physical_width(params) * slots;
break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_I2S:
lrck_period = params_physical_width(params);
break;
--
2.25.1
[PATCH v10 05/15] ASoC: sun4i-i2s: Set sign extend sample
From: Marcus Cooper On the newer SoCs such as the H3 and A64 this is set by default to transfer a 0 after each sample in each slot. However the A10 and A20 SoCs that this driver was developed on had a default setting where it padded the audio gain with zeros. This isn't a problem while we have only support for 16bit audio but with larger sample resolution rates in the pipeline then SEXT bits should be cleared so that they also pad at the LSB. Without this the audio gets distorted. Set sign extend sample for all the sunxi generations even if they are not affected. This will keep consistency and avoid relying on default. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 17 + 1 file changed, 17 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 6ee9c2995b4f..46e4da18c27f 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -48,6 +48,9 @@ #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) #define SUN4I_I2S_FMT1_REG 0x08 +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) + #define SUN4I_I2S_FIFO_TX_REG 0x0c #define SUN4I_I2S_FIFO_RX_REG 0x10 @@ -105,6 +108,9 @@ #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL(0 << 7) +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) + #define SUN8I_I2S_INT_STA_REG 0x0c #define SUN8I_I2S_FIFO_TX_REG 0x20 @@ -686,6 +692,7 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, } regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + return 0; } @@ -788,6 +795,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } @@ -890,6 +902,11 @@ static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } -- 2.25.1
[PATCH v10 04/15] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit
We are actually using a complex formula to just return a bunch of
simple values. Also this formula is wrong for sun4i when calling
get_wss() the function return 4 instead of 3.
Replace this with a simpler switch case.
Also drop the i2s params which is unused and return a simple int as
returning an error code could be out of range for an s8 and there is
no optim to return a s8 here.
Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation")
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 69 +++--
1 file changed, 44 insertions(+), 25 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 24b3137afbc2..6ee9c2995b4f 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -175,8 +175,8 @@ struct sun4i_i2s_quirks {
unsigned intnum_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
- s8 (*get_sr)(const struct sun4i_i2s *, int);
- s8 (*get_wss)(const struct sun4i_i2s *, int);
+ int (*get_sr)(unsigned int width);
+ int (*get_wss)(unsigned int width);
/*
* In the set_chan_cfg() function pointer:
@@ -387,37 +387,56 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return 0;
}
-static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_sr(unsigned int width)
{
- if (width < 16 || width > 24)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_wss(unsigned int width)
{
- if (width < 16 || width > 32)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ case 32:
+ return 3;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
+static int sun8i_i2s_get_sr_wss(unsigned int width)
{
- if (width % 4)
- return -EINVAL;
-
- if (width < 8 || width > 32)
- return -EINVAL;
+ switch (width) {
+ case 8:
+ return 1;
+ case 12:
+ return 2;
+ case 16:
+ return 3;
+ case 20:
+ return 4;
+ case 24:
+ return 5;
+ case 28:
+ return 6;
+ case 32:
+ return 7;
+ }
- return (width - 8) / 4 + 1;
+ return -EINVAL;
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
@@ -582,11 +601,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
}
i2s->playback_dma_data.addr_width = width;
- sr = i2s->variant->get_sr(i2s, word_size);
+ sr = i2s->variant->get_sr(word_size);
if (sr < 0)
return -EINVAL;
- wss = i2s->variant->get_wss(i2s, slot_width);
+ wss = i2s->variant->get_wss(slot_width);
if (wss < 0)
return -EINVAL;
--
2.25.1
[PATCH v10 02/15] ASoC: sun4i-i2s: Change set_chan_cfg() params
As slots and slot_width can be set manually using set_tdm().
These values are then kept in sun4i_i2s struct.
So we need to check if these values are set or not.
This is not done actually and will trigger a bug.
For example, if we set to the simple soundcard in the device-tree
dai-tdm-slot-width = <32> and then start a stream using S16_LE,
currently we would calculate BCLK for 32-bit slots, but program
lrck_period for 16-bit slots, making the sample rate double what we
expected.
To fix this, we need to check if these values are set or not but as
this logic is already done by the caller. Avoid duplicating this
logic and just pass the required values as params to set_chan_cfg().
Suggested-by: Samuel Holland
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index a994b5cf87b3..4ff2068779fd 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -162,8 +162,15 @@ struct sun4i_i2s_quirks {
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
- int (*set_chan_cfg)(const struct sun4i_i2s *,
- const struct snd_pcm_hw_params *);
+
+ /*
+* In the set_chan_cfg() function pointer:
+* @slots: channels per frame + padding slots, regardless of format
+* @slot_width: bits per sample + padding bits, regardless of format
+*/
+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width);
int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
};
@@ -399,10 +406,9 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s
*i2s, int width)
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x3210);
@@ -419,15 +425,11 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
}
static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
- unsigned int slots = channels;
unsigned int lrck_period;
- if (i2s->slots)
- slots = i2s->slots;
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
@@ -450,13 +452,13 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
- lrck_period = params_physical_width(params) * slots;
+ lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_I2S:
- lrck_period = params_physical_width(params);
+ lrck_period = slot_width;
break;
default:
@@ -482,7 +484,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
unsigned int word_size = params_width(params);
unsigned int slot_width = params_physical_width(params);
unsigned int channels = params_channels(params);
+
unsigned int slots = channels;
+
int ret, sr, wss;
u32 width;
@@ -492,7 +496,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
if (i2s->slot_width)
slot_width = i2s->slot_width;
- ret = i2s->variant->set_chan_cfg(i2s, params);
+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
if (ret < 0) {
dev_err(dai->dev, "Invalid channel configuration\n");
return ret;
--
2.25.1
[PATCH v10 03/15] ASoC: sun4i-i2s: Add support for H6 I2S
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 222
1 file changed, 222 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 4ff2068779fd..24b3137afbc2 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -124,6 +124,21 @@
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan)((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
struct sun4i_i2s;
/**
@@ -476,6 +491,60 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -703,6 +772,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+* DAI clock polarity
+*
+* The setup for LRCK contradicts the datasheet, but under a
+* scope it's clear that the LRCK polarity is reversed
+* compared to the expected polarity on the bus.
+*/
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+
Re: [PATCH v9 01/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
Hi Samuel
On Fri, 30 Oct 2020 at 02:20, Samuel Holland wrote:
>
> On 10/27/20 4:43 PM, Clément Péron wrote:
> > Hi Pierre-Louis,
> >
> > On Tue, 27 Oct 2020 at 19:59, Pierre-Louis Bossart
> > wrote:
> >>
> >>
> >>> @@ -452,11 +454,11 @@ static int sun8i_i2s_set_chan_cfg(const struct
> >>> sun4i_i2s *i2s,
> >>> case SND_SOC_DAIFMT_DSP_B:
> >>> case SND_SOC_DAIFMT_LEFT_J:
> >>> case SND_SOC_DAIFMT_RIGHT_J:
> >>> - lrck_period = params_physical_width(params) * slots;
> >>> + lrck_period = slot_width * slots;
> >>> break;
> >>>
> >>> case SND_SOC_DAIFMT_I2S:
> >>> - lrck_period = params_physical_width(params);
> >>> + lrck_period = slot_width;
> >>> break;
> >>
> >> Aren't I2S, LEFT_J and RIGHT_J pretty much the same in terms of lrclk
> >> rate/period? the only thing that can change is the polarity, no?
> >>
> >> Not sure why it's handled differently here?
> >
> > I just had a look at the User Manual for H3 and H6 and I didn't find
> > any reason why LEFT_J and RIGHT_J should be computed in a different
> > way as I2S.
>
> Yes, and the manual explicitly groups LEFT_J and RIGHT_J with I2S when
> describing this field:
>
>PCM Mode: Number of BCLKs within (Left + Right) channel width.
>I2S/Left-Justified/Right-Justified Mode: Number of BCLKs within each
> individual channel width(Left or Right)
>
> So I agree that the code is wrong here.
Thanks, I will send a fix in the v10.
Regards,
Clement
>
> Regards,
> Samuel
>
> > Also the commit introducing this doesn't mention it.
> > 7ae7834ec446 ("ASoC: sun4i-i2s: Add support for DSP formats")
> >
> > I can't test it with my board but if nobody complains about it, I will
> > introduce a fix for this in the next version and change this also for
> > H6.
> >
> > Thanks for your review,
> > Clement
> >
>
Re: [PATCH v9 01/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
Hi Pierre-Louis,
On Tue, 27 Oct 2020 at 19:59, Pierre-Louis Bossart
wrote:
>
>
> > @@ -452,11 +454,11 @@ static int sun8i_i2s_set_chan_cfg(const struct
> > sun4i_i2s *i2s,
> > case SND_SOC_DAIFMT_DSP_B:
> > case SND_SOC_DAIFMT_LEFT_J:
> > case SND_SOC_DAIFMT_RIGHT_J:
> > - lrck_period = params_physical_width(params) * slots;
> > + lrck_period = slot_width * slots;
> > break;
> >
> > case SND_SOC_DAIFMT_I2S:
> > - lrck_period = params_physical_width(params);
> > + lrck_period = slot_width;
> > break;
>
> Aren't I2S, LEFT_J and RIGHT_J pretty much the same in terms of lrclk
> rate/period? the only thing that can change is the polarity, no?
>
> Not sure why it's handled differently here?
I just had a look at the User Manual for H3 and H6 and I didn't find
any reason why LEFT_J and RIGHT_J should be computed in a different
way as I2S.
Also the commit introducing this doesn't mention it.
7ae7834ec446 ("ASoC: sun4i-i2s: Add support for DSP formats")
I can't test it with my board but if nobody complains about it, I will
introduce a fix for this in the next version and change this also for
H6.
Thanks for your review,
Clement
[PATCH v9 11/14] arm64: dts: allwinner: a64: Add I2S2 node
From: Marcus Cooper
Add the I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dc238814013c..51cc30e84e26 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -846,6 +846,20 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+"allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 27>, <&dma 27>;
+ status = "disabled";
+ };
+
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-codec-i2s";
--
2.25.1
[PATCH v9 14/14] arm: dts: sunxi: h3/h5: Add I2S2 node
From: Marcus Cooper
Add H3/H5 I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 22d533d18992..9be13378d4df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -662,6 +662,19 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-codec";
--
2.25.1
[PATCH v9 12/14] arm64: defconfig: Enable Allwinner i2s driver
Enable Allwinner I2S driver for arm64 defconfig. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..3f89f427a355 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m -- 2.25.1
[PATCH v9 09/14] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible
From: Jernej Skrabec H6 I2S is very similar to H3, except that it supports up to 16 channels and thus few registers have fields on different position. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Acked-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 112ae00d63c1..606ad2d884a8 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -24,6 +24,7 @@ properties: - items: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s + - const: allwinner,sun50i-h6-i2s reg: maxItems: 1 @@ -59,6 +60,7 @@ allOf: - allwinner,sun8i-a83t-i2s - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s + - allwinner,sun50i-h6-i2s then: required: -- 2.25.1
[PATCH v9 02/14] ASoC: sun4i-i2s: Add support for H6 I2S
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 222
1 file changed, 222 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 7c1f57eb2462..9aa837d4fe99 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -124,6 +124,21 @@
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan)((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
struct sun4i_i2s;
/**
@@ -476,6 +491,60 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -703,6 +772,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+* DAI clock polarity
+*
+* The setup for LRCK contradicts the datasheet, but under a
+* scope it's clear that the LRCK polarity is reversed
+* compared to the expected polarity on the bus.
+*/
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+
[PATCH v9 10/14] arm64: dts: allwinner: h6: Add I2S1 node
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 28c77d6872f6..d915aeb13297 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -609,6 +609,19 @@ mdio: mdio {
};
};
+ i2s1: i2s@5091000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x05091000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
--
2.25.1
[PATCH v9 03/14] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit
We are actually using a complex formula to just return a bunch of
simple values. Also this formula is wrong for sun4i when calling
get_wss() the function return 4 instead of 3.
Replace this with a simpler switch case.
Also drop the i2s params which is unused and return a simple int as
returning an error code could be out of range for an s8 and there is
no optim to return a s8 here.
Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation")
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 69 +++--
1 file changed, 44 insertions(+), 25 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 9aa837d4fe99..073ee60da011 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -175,8 +175,8 @@ struct sun4i_i2s_quirks {
unsigned intnum_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
- s8 (*get_sr)(const struct sun4i_i2s *, int);
- s8 (*get_wss)(const struct sun4i_i2s *, int);
+ int (*get_sr)(unsigned int width);
+ int (*get_wss)(unsigned int width);
/*
* In the set_chan_cfg() function pointer:
@@ -387,37 +387,56 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return 0;
}
-static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_sr(unsigned int width)
{
- if (width < 16 || width > 24)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_wss(unsigned int width)
{
- if (width < 16 || width > 32)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ case 32:
+ return 3;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
+static int sun8i_i2s_get_sr_wss(unsigned int width)
{
- if (width % 4)
- return -EINVAL;
-
- if (width < 8 || width > 32)
- return -EINVAL;
+ switch (width) {
+ case 8:
+ return 1;
+ case 12:
+ return 2;
+ case 16:
+ return 3;
+ case 20:
+ return 4;
+ case 24:
+ return 5;
+ case 28:
+ return 6;
+ case 32:
+ return 7;
+ }
- return (width - 8) / 4 + 1;
+ return -EINVAL;
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
@@ -582,11 +601,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
}
i2s->playback_dma_data.addr_width = width;
- sr = i2s->variant->get_sr(i2s, word_size);
+ sr = i2s->variant->get_sr(word_size);
if (sr < 0)
return -EINVAL;
- wss = i2s->variant->get_wss(i2s, slot_width);
+ wss = i2s->variant->get_wss(slot_width);
if (wss < 0)
return -EINVAL;
--
2.25.1
[PATCH v9 01/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
As slots and slot_width can be set manually using set_tdm().
These values are then kept in sun4i_i2s struct.
So we need to check if these values are set or not.
This is not done actually and will trigger a bug.
For example, if we set to the simple soundcard in the device-tree
dai-tdm-slot-width = <32> and then start a stream using S16_LE,
currently we would calculate BCLK for 32-bit slots, but program
lrck_period for 16-bit slots, making the sample rate double what we
expected.
To fix this, we need to check if these values are set or not but as
this logic is already done by the caller. Avoid duplicating this
logic and just pass the required values as params to set_chan_cfg().
Suggested-by: Samuel Holland
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index f23ff29e7c1d..7c1f57eb2462 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -162,8 +162,15 @@ struct sun4i_i2s_quirks {
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
- int (*set_chan_cfg)(const struct sun4i_i2s *,
- const struct snd_pcm_hw_params *);
+
+ /*
+* In the set_chan_cfg() function pointer:
+* @slots: channels per frame + padding slots, regardless of format
+* @slot_width: bits per sample + padding bits, regardless of format
+*/
+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width);
int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
};
@@ -399,10 +406,9 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s
*i2s, int width)
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x3210);
@@ -419,15 +425,11 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
}
static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
- unsigned int slots = channels;
unsigned int lrck_period;
- if (i2s->slots)
- slots = i2s->slots;
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
@@ -452,11 +454,11 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
case SND_SOC_DAIFMT_DSP_B:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
- lrck_period = params_physical_width(params) * slots;
+ lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_I2S:
- lrck_period = params_physical_width(params);
+ lrck_period = slot_width;
break;
default:
@@ -482,7 +484,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
unsigned int word_size = params_width(params);
unsigned int slot_width = params_physical_width(params);
unsigned int channels = params_channels(params);
+
unsigned int slots = channels;
+
int ret, sr, wss;
u32 width;
@@ -492,7 +496,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
if (i2s->slot_width)
slot_width = i2s->slot_width;
- ret = i2s->variant->set_chan_cfg(i2s, params);
+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
if (ret < 0) {
dev_err(dai->dev, "Invalid channel configuration\n");
return ret;
--
2.25.1
[PATCH v9 04/14] ASoC: sun4i-i2s: Set sign extend sample
From: Marcus Cooper On the newer SoCs such as the H3 and A64 this is set by default to transfer a 0 after each sample in each slot. However the A10 and A20 SoCs that this driver was developed on had a default setting where it padded the audio gain with zeros. This isn't a problem while we have only support for 16bit audio but with larger sample resolution rates in the pipeline then SEXT bits should be cleared so that they also pad at the LSB. Without this the audio gets distorted. Set sign extend sample for all the sunxi generations even if they are not affected. This will keep consistency and avoid relying on default. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 17 + 1 file changed, 17 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 073ee60da011..9f9d3e7baad0 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -48,6 +48,9 @@ #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) #define SUN4I_I2S_FMT1_REG 0x08 +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) + #define SUN4I_I2S_FIFO_TX_REG 0x0c #define SUN4I_I2S_FIFO_RX_REG 0x10 @@ -105,6 +108,9 @@ #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL(0 << 7) +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) + #define SUN8I_I2S_INT_STA_REG 0x0c #define SUN8I_I2S_FIFO_TX_REG 0x20 @@ -686,6 +692,7 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, } regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + return 0; } @@ -788,6 +795,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } @@ -890,6 +902,11 @@ static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } -- 2.25.1
[PATCH v9 06/14] ASoC: sun4i-i2s: Fix sun8i volatile regs
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 39b56d0de1fd..83537538f8ee 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1162,12 +1162,19 @@ static bool sun8i_i2s_rd_reg(struct device *dev,
unsigned int reg)
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
- if (reg == SUN8I_I2S_INT_STA_REG)
+ switch (reg) {
+ case SUN4I_I2S_FIFO_CTRL_REG:
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ case SUN8I_I2S_FIFO_TX_REG:
+ case SUN8I_I2S_INT_STA_REG:
return true;
- if (reg == SUN8I_I2S_FIFO_TX_REG)
- return false;
- return sun4i_i2s_volatile_reg(dev, reg);
+ default:
+ return false;
+ }
}
static const struct reg_default sun4i_i2s_reg_defaults[] = {
--
2.25.1
[PATCH v9 07/14] ASoC: sun4i-i2s: Fix setting of FIFO modes
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 83537538f8ee..6a3207245ae2 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -596,6 +596,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
return ret;
}
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -924,13 +931,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
return ret;
}
- /* Set significant bits in our FIFOs */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
- SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
-
i2s->format = fmt;
return 0;
--
2.25.1
[PATCH v9 00/14] Add Allwinner H3/H5/H6/A64 HDMI audio
Hi, This series add H6 I2S support and the I2S node missing to support HDMI audio in different Allwinner SoC. As we first use some TDM property to make the I2S working we the simple soundcard. We have now drop this simple sound card and a proper dedicated soundcard will be introduce later. This make the title of this series wrong now :/. Regards, Clement Change since v8: - move the comment near the function prototype - collect Maxime Ripard tags Change since v7: - rebase on next-20201026 - comment about slots and slot_width Change since v6: - move set_channel_cfg() in first position - convert return value to decimal Change since v5: - Drop HDMI simple soundcard - Collect Chen-Yu Tsai tags - Configure channels from 9 to 15. - Remove DMA RX for H3/H5 - Fix Documentation for H3/H5 Change since v4: - add more comment on get_wss() and set_channel_cfg() patch - merge soundcard and DAI HDMI patches Change since v3: - add Samuel Holland patch to reconfigure FIFO_TX_REG when suspend is enabled - readd inversion to H6 LRCK sun50i_h6_i2s_set_soc_fmt() - Fix get_wss() for sun4i - Add a commit to fix checkpatch warning Change since v2: - rebase on next-20200918 - drop revert LRCK polarity patch - readd simple-audio-card,frame-inversion in dts - Add patch for changing set_chan_cfg params Change since v1: - rebase on next-20200828 - add revert LRCK polarity - remove all simple-audio-card,frame-inversion in dts - add Ondrej patches for Orange Pi board - Add arm64 defconfig patch Clément Péron (6): ASoC: sun4i-i2s: Change set_chan_cfg() params ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit ASoC: sun4i-i2s: Fix sun8i volatile regs ASoC: sun4i-i2s: fix coding-style for callback definition arm64: defconfig: Enable Allwinner i2s driver dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility Jernej Skrabec (3): ASoC: sun4i-i2s: Add support for H6 I2S dt-bindings: ASoC: sun4i-i2s: Add H6 compatible arm64: dts: allwinner: h6: Add I2S1 node Marcus Cooper (4): ASoC: sun4i-i2s: Set sign extend sample ASoc: sun4i-i2s: Add 20 and 24 bit support arm64: dts: allwinner: a64: Add I2S2 node arm: dts: sunxi: h3/h5: Add I2S2 node Samuel Holland (1): ASoC: sun4i-i2s: Fix setting of FIFO modes .../sound/allwinner,sun4i-a10-i2s.yaml| 6 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi| 13 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 + arch/arm64/configs/defconfig | 1 + sound/soc/sunxi/sun4i-i2s.c | 384 +++--- 6 files changed, 376 insertions(+), 55 deletions(-) -- 2.25.1
[PATCH v9 08/14] ASoC: sun4i-i2s: fix coding-style for callback definition
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 6a3207245ae2..4cf8a67efa4f 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -180,7 +180,7 @@ struct sun4i_i2s_quirks {
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned intnum_mclk_dividers;
- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
@@ -192,7 +192,7 @@ struct sun4i_i2s_quirks {
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
- int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
--
2.25.1
[PATCH v9 05/14] ASoc: sun4i-i2s: Add 20 and 24 bit support
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 9f9d3e7baad0..39b56d0de1fd 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -600,6 +600,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1081,6 +1084,10 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+SNDRV_PCM_FMTBIT_S20_LE | \
+SNDRV_PCM_FMTBIT_S24_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1088,14 +1095,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
--
2.25.1
[PATCH v9 13/14] dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility
Like A83T the Allwinner H3 doesn't have the DMA reception available for some audio interfaces. As it's already documented for A83T convert this to an enum and add the H3 interface. Acked-by: Rob Herring Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 606ad2d884a8..a16e37b01e1d 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -70,7 +70,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun8i-a83t-i2s +enum: + - allwinner,sun8i-a83t-i2s + - allwinner,sun8i-h3-i2s then: properties: -- 2.25.1
[PATCH v8 01/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
As slots and slot_width can be set manually using set_tdm().
These values are then kept in sun4i_i2s struct.
So we need to check if these values are set or not.
This is not done actually and will trigger a bug.
For example, if we set to the simple soundcard in the device-tree
dai-tdm-slot-width = <32> and then start a stream using S16_LE,
currently we would calculate BCLK for 32-bit slots, but program
lrck_period for 16-bit slots, making the sample rate double what we
expected.
To fix this, we need to check if these values are set or not but as
this logic is already done by the caller. Avoid duplicating this
logic and just pass the required values as params to set_chan_cfg().
Suggested-by: Samuel Holland
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index f23ff29e7c1d..6c10f810b114 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -162,8 +162,9 @@ struct sun4i_i2s_quirks {
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
- int (*set_chan_cfg)(const struct sun4i_i2s *,
- const struct snd_pcm_hw_params *);
+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width);
int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
};
@@ -399,10 +400,9 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s
*i2s, int width)
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x3210);
@@ -419,15 +419,11 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
}
static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
- unsigned int slots = channels;
unsigned int lrck_period;
- if (i2s->slots)
- slots = i2s->slots;
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
@@ -452,11 +448,11 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
case SND_SOC_DAIFMT_DSP_B:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
- lrck_period = params_physical_width(params) * slots;
+ lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_I2S:
- lrck_period = params_physical_width(params);
+ lrck_period = slot_width;
break;
default:
@@ -480,9 +476,16 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int word_size = params_width(params);
- unsigned int slot_width = params_physical_width(params);
unsigned int channels = params_channels(params);
+
+ /*
+* Here and in set_chan_cfg(), "slots" means channels per frame +
+* padding slots, regardless of format. "slot_width" means bits
+* per sample + padding bits, regardless of format.
+*/
unsigned int slots = channels;
+ unsigned int slot_width = params_physical_width(params);
+
int ret, sr, wss;
u32 width;
@@ -492,7 +495,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
if (i2s->slot_width)
slot_width = i2s->slot_width;
- ret = i2s->variant->set_chan_cfg(i2s, params);
+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
if (ret < 0) {
dev_err(dai->dev, "Invalid channel configuration\n");
return ret;
--
2.25.1
[PATCH v8 03/14] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit
We are actually using a complex formula to just return a bunch of
simple values. Also this formula is wrong for sun4i when calling
get_wss() the function return 4 instead of 3.
Replace this with a simpler switch case.
Also drop the i2s params which is unused and return a simple int as
returning an error code could be out of range for an s8 and there is
no optim to return a s8 here.
Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation")
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 69 +++--
1 file changed, 44 insertions(+), 25 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 5bec7fbd0b30..70a2ec99f444 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -175,8 +175,8 @@ struct sun4i_i2s_quirks {
unsigned intnum_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
- s8 (*get_sr)(const struct sun4i_i2s *, int);
- s8 (*get_wss)(const struct sun4i_i2s *, int);
+ int (*get_sr)(unsigned int width);
+ int (*get_wss)(unsigned int width);
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
@@ -381,37 +381,56 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return 0;
}
-static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_sr(unsigned int width)
{
- if (width < 16 || width > 24)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_wss(unsigned int width)
{
- if (width < 16 || width > 32)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ case 32:
+ return 3;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
+static int sun8i_i2s_get_sr_wss(unsigned int width)
{
- if (width % 4)
- return -EINVAL;
-
- if (width < 8 || width > 32)
- return -EINVAL;
+ switch (width) {
+ case 8:
+ return 1;
+ case 12:
+ return 2;
+ case 16:
+ return 3;
+ case 20:
+ return 4;
+ case 24:
+ return 5;
+ case 28:
+ return 6;
+ case 32:
+ return 7;
+ }
- return (width - 8) / 4 + 1;
+ return -EINVAL;
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
@@ -581,11 +600,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
}
i2s->playback_dma_data.addr_width = width;
- sr = i2s->variant->get_sr(i2s, word_size);
+ sr = i2s->variant->get_sr(word_size);
if (sr < 0)
return -EINVAL;
- wss = i2s->variant->get_wss(i2s, slot_width);
+ wss = i2s->variant->get_wss(slot_width);
if (wss < 0)
return -EINVAL;
--
2.25.1
[PATCH v8 14/14] arm: dts: sunxi: h3/h5: Add I2S2 node
From: Marcus Cooper
Add H3/H5 I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 22d533d18992..9be13378d4df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -662,6 +662,19 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-codec";
--
2.25.1
[PATCH v8 11/14] arm64: dts: allwinner: a64: Add I2S2 node
From: Marcus Cooper
Add the I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dc238814013c..51cc30e84e26 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -846,6 +846,20 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+"allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 27>, <&dma 27>;
+ status = "disabled";
+ };
+
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-codec-i2s";
--
2.25.1
[PATCH v8 13/14] dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility
Like A83T the Allwinner H3 doesn't have the DMA reception available for some audio interfaces. As it's already documented for A83T convert this to an enum and add the H3 interface. Acked-by: Rob Herring Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 606ad2d884a8..a16e37b01e1d 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -70,7 +70,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun8i-a83t-i2s +enum: + - allwinner,sun8i-a83t-i2s + - allwinner,sun8i-h3-i2s then: properties: -- 2.25.1
[PATCH v8 07/14] ASoC: sun4i-i2s: Fix setting of FIFO modes
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index dee8688f0d37..703327dc8606 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -595,6 +595,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
return ret;
}
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -923,13 +930,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
return ret;
}
- /* Set significant bits in our FIFOs */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
- SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
-
i2s->format = fmt;
return 0;
--
2.25.1
[PATCH v8 09/14] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible
From: Jernej Skrabec H6 I2S is very similar to H3, except that it supports up to 16 channels and thus few registers have fields on different position. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Acked-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 112ae00d63c1..606ad2d884a8 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -24,6 +24,7 @@ properties: - items: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s + - const: allwinner,sun50i-h6-i2s reg: maxItems: 1 @@ -59,6 +60,7 @@ allOf: - allwinner,sun8i-a83t-i2s - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s + - allwinner,sun50i-h6-i2s then: required: -- 2.25.1
[PATCH v8 12/14] arm64: defconfig: Enable Allwinner i2s driver
Enable Allwinner I2S driver for arm64 defconfig. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..3f89f427a355 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m -- 2.25.1
[PATCH v8 04/14] ASoC: sun4i-i2s: Set sign extend sample
From: Marcus Cooper On the newer SoCs such as the H3 and A64 this is set by default to transfer a 0 after each sample in each slot. However the A10 and A20 SoCs that this driver was developed on had a default setting where it padded the audio gain with zeros. This isn't a problem while we have only support for 16bit audio but with larger sample resolution rates in the pipeline then SEXT bits should be cleared so that they also pad at the LSB. Without this the audio gets distorted. Set sign extend sample for all the sunxi generations even if they are not affected. This will keep consistency and avoid relying on default. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 17 + 1 file changed, 17 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 70a2ec99f444..beaca56a44ae 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -48,6 +48,9 @@ #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) #define SUN4I_I2S_FMT1_REG 0x08 +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) + #define SUN4I_I2S_FIFO_TX_REG 0x0c #define SUN4I_I2S_FIFO_RX_REG 0x10 @@ -105,6 +108,9 @@ #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL(0 << 7) +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) + #define SUN8I_I2S_INT_STA_REG 0x0c #define SUN8I_I2S_FIFO_TX_REG 0x20 @@ -685,6 +691,7 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, } regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + return 0; } @@ -787,6 +794,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } @@ -889,6 +901,11 @@ static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } -- 2.25.1
[PATCH v8 05/14] ASoc: sun4i-i2s: Add 20 and 24 bit support
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index beaca56a44ae..eee1e64cd8f4 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -599,6 +599,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1080,6 +1083,10 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+SNDRV_PCM_FMTBIT_S20_LE | \
+SNDRV_PCM_FMTBIT_S24_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1087,14 +1094,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
--
2.25.1
[PATCH v8 06/14] ASoC: sun4i-i2s: Fix sun8i volatile regs
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index eee1e64cd8f4..dee8688f0d37 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1161,12 +1161,19 @@ static bool sun8i_i2s_rd_reg(struct device *dev,
unsigned int reg)
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
- if (reg == SUN8I_I2S_INT_STA_REG)
+ switch (reg) {
+ case SUN4I_I2S_FIFO_CTRL_REG:
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ case SUN8I_I2S_FIFO_TX_REG:
+ case SUN8I_I2S_INT_STA_REG:
return true;
- if (reg == SUN8I_I2S_FIFO_TX_REG)
- return false;
- return sun4i_i2s_volatile_reg(dev, reg);
+ default:
+ return false;
+ }
}
static const struct reg_default sun4i_i2s_reg_defaults[] = {
--
2.25.1
[PATCH v8 02/14] ASoC: sun4i-i2s: Add support for H6 I2S
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 222
1 file changed, 222 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 6c10f810b114..5bec7fbd0b30 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -124,6 +124,21 @@
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan)((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
struct sun4i_i2s;
/**
@@ -470,6 +485,60 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -702,6 +771,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+* DAI clock polarity
+*
+* The setup for LRCK contradicts the datasheet, but under a
+* scope it's clear that the LRCK polarity is reversed
+* compared to the expected polarity on the bus.
+*/
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
[PATCH v8 08/14] ASoC: sun4i-i2s: fix coding-style for callback definition
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 703327dc8606..08e9e71f455f 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -180,13 +180,13 @@ struct sun4i_i2s_quirks {
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned intnum_mclk_dividers;
- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
- int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
--
2.25.1
[PATCH v8 10/14] arm64: dts: allwinner: h6: Add I2S1 node
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 28c77d6872f6..d915aeb13297 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -609,6 +609,19 @@ mdio: mdio {
};
};
+ i2s1: i2s@5091000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x05091000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
--
2.25.1
[PATCH v8 00/14] Add Allwinner H3/H5/H6/A64 HDMI audio
Hi, This is the same as v7 but rebased on next-20201026 and added a comment about slots and slot_width. A proper sound card will be introduced later. This was tested on H6 only. Regards, Clement Change since v7: - rebase on next-20201026 - comment about slots and slot_width Change since v6: - move set_channel_cfg() in first position - convert return value to decimal Change since v5: - Drop HDMI simple soundcard - Collect Chen-Yu Tsai tags - Configure channels from 9 to 15. - Remove DMA RX for H3/H5 - Fix Documentation for H3/H5 Change since v4: - add more comment on get_wss() and set_channel_cfg() patch - merge soundcard and DAI HDMI patches Change since v3: - add Samuel Holland patch to reconfigure FIFO_TX_REG when suspend is enabled - readd inversion to H6 LRCK sun50i_h6_i2s_set_soc_fmt() - Fix get_wss() for sun4i - Add a commit to fix checkpatch warning Change since v2: - rebase on next-20200918 - drop revert LRCK polarity patch - readd simple-audio-card,frame-inversion in dts - Add patch for changing set_chan_cfg params Change since v1: - rebase on next-20200828 - add revert LRCK polarity - remove all simple-audio-card,frame-inversion in dts - add Ondrej patches for Orange Pi board - Add arm64 defconfig patch Clément Péron (6): ASoC: sun4i-i2s: Change set_chan_cfg() params ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit ASoC: sun4i-i2s: Fix sun8i volatile regs ASoC: sun4i-i2s: fix coding-style for callback definition arm64: defconfig: Enable Allwinner i2s driver dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility Jernej Skrabec (3): ASoC: sun4i-i2s: Add support for H6 I2S dt-bindings: ASoC: sun4i-i2s: Add H6 compatible arm64: dts: allwinner: h6: Add I2S1 node Marcus Cooper (4): ASoC: sun4i-i2s: Set sign extend sample ASoc: sun4i-i2s: Add 20 and 24 bit support arm64: dts: allwinner: a64: Add I2S2 node arm: dts: sunxi: h3/h5: Add I2S2 node Samuel Holland (1): ASoC: sun4i-i2s: Fix setting of FIFO modes .../sound/allwinner,sun4i-a10-i2s.yaml| 6 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi| 13 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 + arch/arm64/configs/defconfig | 1 + sound/soc/sunxi/sun4i-i2s.c | 385 +++--- 6 files changed, 376 insertions(+), 56 deletions(-) -- 2.25.1
Re: [linux-sunxi] [PATCH 02/10] ARM: dts: sun6i: a31-hummingbird: Enable RGMII RX/TX delay on Ethernet PHY
Hi,
On Sat, 24 Oct 2020 at 20:39, Icenowy Zheng wrote:
>
>
>
> 于 2020年10月25日 GMT+08:00 上午2:30:35, "Jernej Škrabec"
> 写到:
> >Dne sobota, 24. oktober 2020 ob 19:51:06 CEST je Icenowy Zheng
> >napisal(a):
> >> 在 2020-10-25星期日的 00:25 +0800，Chen-Yu Tsai写道：
> >>
> >> > From: Chen-Yu Tsai
> >> >
> >> > The Ethernet PHY on the A31 Hummingbird has the RX and TX delays
> >> > enabled on the PHY, using pull-ups on the RXDLY and TXDLY pins.
> >> >
> >> > Fix the phy-mode description to correct reflect this so that the
> >> > implementation doesn't reconfigure the delays incorrectly. This
> >> > happened with commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e
> >> > rx/tx delay config").
> >>
> >> Personally I think they should revert this commit, and consider other
> >> solution.
> >>
> >> This commit breaks everything.
> >>
> >
> >Previously broken driver allowed inproper DT to work, so you have to
> >fix
> >everything eventually.
>
> There is no "improper DT" if it's already shipped, DT should suffer driver
> change, not changed to match driver.
>
> I think at least Fedora tends to ship a DT with a system image that will
> not get updated when kernel gets updated.
I think we are missing a phy-mode saying use RGMII but don't change
the delay set by the hardware.
Or maybe introduce a phy-mode='rgmii-noid' to explicitly disable the
RX/TD delay using software bits
and use phy-mode='rgmii' to keep the delay set by the hardware.
Clement
>
> >
> >Plus side, there is no need to have hack for Pine64 Plus ethernet
> >anymore.
> >
> >Best regards,
> >Jernej
> >
> >> (Although the patch on individual DT patches are technically correct)
> >>
> >> > Fixes: c220aec2bb79 ("ARM: dts: sun6i: Add Merrii A31 Hummingbird
> >> > support")
> >> > Signed-off-by: Chen-Yu Tsai
> >> > ---
> >> >
> >> > arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
> >> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >> >
> >> > diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
> >> > b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
> >> > index 049e6ab3cf56..73de34ae37fd 100644
> >> > --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
> >> > +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
> >> > @@ -154,7 +154,7 @@ &gmac {
> >> >
> >> >pinctrl-names = "default";
> >> >pinctrl-0 = <&gmac_rgmii_pins>;
> >> >phy-handle = <&phy1>;
> >> >
> >> > - phy-mode = "rgmii";
> >> > + phy-mode = "rgmii-id";
> >> >
> >> >status = "okay";
> >> >
> >> > };
>
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an
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> To view this discussion on the web, visit
> https://groups.google.com/d/msgid/linux-sunxi/9D317C52-5F28-41A9-80DA-DBADA142B042%40aosc.io.
Re: [PATCH] arm64: dts: allwinner: beelink-gs1: Enable both RGMII RX/TX delay
Hi,
On Sun, 18 Oct 2020 at 19:24, Clément Péron wrote:
>
> Before the commit:
> net: phy: realtek: fix rtl8211e rx/tx delay config
bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config")
With the hash for reference it's better :)
Clement
>
> The software overwrite for RX/TX delays of the RTL8211e were not
> working properly and the Beelink GS1 had both RX/TX delay of RGMII
> interface set using pull-up on the TXDLY and RXDLY pins.
>
> Now that these delays are working properly they overwrite the HW
> config and set this to 'rgmii' meaning no delay on both RX/TX.
> This makes the ethernet of this board not working anymore.
>
> Set the phy-mode to 'rgmii-id' meaning RGMII with RX/TX delays
> in the device-tree to keep the correct configuration.
>
> Fixes: 089bee8dd119 ("arm64: dts: allwinner: h6: Introduce Beelink GS1 board")
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index a364cb4e5b3f..6ab53860e447 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -99,7 +99,7 @@ &ehci0 {
> &emac {
> pinctrl-names = "default";
> pinctrl-0 = <&ext_rgmii_pins>;
> - phy-mode = "rgmii";
> + phy-mode = "rgmii-id";
> phy-handle = <&ext_rgmii_phy>;
> phy-supply = <®_aldo2>;
> status = "okay";
> --
> 2.25.1
>
Re: [PATCH v2] arm64: dts: allwinner: beelink-gs1: Update LED power node
HI Maxime,
On Mon, 12 Oct 2020 at 13:22, Maxime Ripard wrote:
>
> Hi!
>
> On Sun, Oct 11, 2020 at 11:22:37PM +0200, Clément Péron wrote:
> > Beelink GS1 LED trigger a warning when running dtbs_check.
> >
> > Update the node with a valid pattern property.
> >
> > Also add the function and the color of the LED and drop the
> > label which is deprecated.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > index 3f7ceeb1a767..a364cb4e5b3f 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > @@ -7,6 +7,7 @@
> > #include "sun50i-h6-cpu-opp.dtsi"
> >
> > #include
> > +#include
> >
> > / {
> > model = "Beelink GS1";
> > @@ -43,8 +44,9 @@ ext_osc32k: ext_osc32k_clk {
> > leds {
> > compatible = "gpio-leds";
> >
> > - power {
> > - label = "beelink:white:power";
> > + led-0 {
> > + function = LED_FUNCTION_POWER;
> > + color = ;
> > gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
> > default-state = "on";
> > };
>
> Doesn't that also change the sysfs file that LED is exposed to the userspace
> with?
Indeed the previous led sysfs:
/sys/class/leds/beelink:white:power/
is now
/sys/class/leds/white:power/
Do you want me to keep the label property to avoid this sysfs change ?
Regards,
Clement
>
> Maxime
[PATCH] arm64: dts: allwinner: beelink-gs1: Enable both RGMII RX/TX delay
Before the commit:
net: phy: realtek: fix rtl8211e rx/tx delay config
The software overwrite for RX/TX delays of the RTL8211e were not
working properly and the Beelink GS1 had both RX/TX delay of RGMII
interface set using pull-up on the TXDLY and RXDLY pins.
Now that these delays are working properly they overwrite the HW
config and set this to 'rgmii' meaning no delay on both RX/TX.
This makes the ethernet of this board not working anymore.
Set the phy-mode to 'rgmii-id' meaning RGMII with RX/TX delays
in the device-tree to keep the correct configuration.
Fixes: 089bee8dd119 ("arm64: dts: allwinner: h6: Introduce Beelink GS1 board")
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index a364cb4e5b3f..6ab53860e447 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -99,7 +99,7 @@ &ehci0 {
&emac {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_aldo2>;
status = "okay";
--
2.25.1
Re: [PATCH] dt-bindings: sound: sun8i-a33-codec: Add Allwinner A64 codec compatible fallback
Hi Maxime and all, On Mon, 12 Oct 2020 at 09:50, Maxime Ripard wrote: > > Hi! > > On Sun, Oct 11, 2020 at 11:15:42PM +0200, Clément Péron wrote: > > make dtbs_check report a warning because the documentation > > for the A64 codec compatible is missing. > > > > The A64 codec compatible is actually a simple fallback to the A33. > > > > Reflect this in the dt-bindings Documentation. > > > > Signed-off-by: Clément Péron > > This patch is already in the ASoC tree and linux-next: I was indeed on top of sunxi/for-next and not linux-next/master I will test on top of linux-next for the next ones. Sorry for the duplicate patch and the noise :(. Clement > > https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git/commit/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml?id=cef305d4eb0733f25215793ed30b056a7db9bb62 > > Maxime
[PATCH v2] arm64: dts: allwinner: beelink-gs1: Update LED power node
Beelink GS1 LED trigger a warning when running dtbs_check.
Update the node with a valid pattern property.
Also add the function and the color of the LED and drop the
label which is deprecated.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..a364cb4e5b3f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -7,6 +7,7 @@
#include "sun50i-h6-cpu-opp.dtsi"
#include
+#include
/ {
model = "Beelink GS1";
@@ -43,8 +44,9 @@ ext_osc32k: ext_osc32k_clk {
leds {
compatible = "gpio-leds";
- power {
- label = "beelink:white:power";
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
default-state = "on";
};
--
2.25.1
Re: [PATCH] arm64: dts: allwinner: beelink-gs1: Update LED power node
Hi,
On Sun, 11 Oct 2020 at 23:14, Clément Péron wrote:
>
> Beelink GS1 LED trigger a warning when running dtbs_check.
>
> Update the node with a valid pattern property.
>
> Also add the function and the color of the LED and drop the
> label which is deprecated.
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index 3f7ceeb1a767..f506d6fa8017 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -7,6 +7,7 @@
> #include "sun50i-h6-cpu-opp.dtsi"
>
> #include
> +#include
>
> / {
> model = "Beelink GS1";
> @@ -43,8 +44,9 @@ ext_osc32k: ext_osc32k_clk {
> leds {
> compatible = "gpio-leds";
>
> - power {
> - label = "beelink:white:power";
> + led-0 {
> + function = LED_FUNCTION_POWER;
> + color = LED_COLOR_ID_WHITE;
color = ;
Sorry, I will send a v2.
Clement
> gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
> default-state = "on";
> };
> --
> 2.25.1
>
[PATCH] dt-bindings: sound: sun8i-a33-codec: Add Allwinner A64 codec compatible fallback
make dtbs_check report a warning because the documentation for the A64 codec compatible is missing. The A64 codec compatible is actually a simple fallback to the A33. Reflect this in the dt-bindings Documentation. Signed-off-by: Clément Péron --- .../bindings/sound/allwinner,sun8i-a33-codec.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 55d28268d2f4..e78a22496e7c 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -15,7 +15,11 @@ properties: const: 0 compatible: -const: allwinner,sun8i-a33-codec +oneOf: + - const: allwinner,sun8i-a33-codec + - items: +- const: allwinner,sun50i-a64-codec +- const: allwinner,sun8i-a33-codec reg: maxItems: 1 -- 2.25.1
[PATCH] arm64: dts: allwinner: pinetab: Drop unnecessary address/size-cells information
make dtbs_check warm about unknown address/size-cells property in the
pinetab device-tree.
This is because these information are not necessary.
Drop them.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
index 3ab0f0347bc9..0494bfaf2ffa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
@@ -122,9 +122,6 @@ &csi {
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
bus-width = <8>;
--
2.25.1
[PATCH] arm64: dts: allwinner: beelink-gs1: Update LED power node
Beelink GS1 LED trigger a warning when running dtbs_check.
Update the node with a valid pattern property.
Also add the function and the color of the LED and drop the
label which is deprecated.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..f506d6fa8017 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -7,6 +7,7 @@
#include "sun50i-h6-cpu-opp.dtsi"
#include
+#include
/ {
model = "Beelink GS1";
@@ -43,8 +44,9 @@ ext_osc32k: ext_osc32k_clk {
leds {
compatible = "gpio-leds";
- power {
- label = "beelink:white:power";
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = LED_COLOR_ID_WHITE;
gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
default-state = "on";
};
--
2.25.1
[PATCH v7 12/14] arm64: defconfig: Enable Allwinner i2s driver
Enable Allwinner I2S driver for arm64 defconfig. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 63003ec116ee..9a3c3bbe60e4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -696,6 +696,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m -- 2.25.1
[PATCH v7 13/14] dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility
Like A83T the Allwinner H3 doesn't have the DMA reception available for some audio interfaces. As it's already documented for A83T convert this to an enum and add the H3 interface. Acked-by: Rob Herring Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 606ad2d884a8..a16e37b01e1d 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -70,7 +70,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun8i-a83t-i2s +enum: + - allwinner,sun8i-a83t-i2s + - allwinner,sun8i-h3-i2s then: properties: -- 2.25.1
[PATCH v7 14/14] arm: dts: sunxi: h3/h5: Add I2S2 node
From: Marcus Cooper
Add H3/H5 I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 22d533d18992..9be13378d4df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -662,6 +662,19 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-codec";
--
2.25.1
[PATCH v7 11/14] arm64: dts: allwinner: a64: Add I2S2 node
From: Marcus Cooper
Add the I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dc238814013c..51cc30e84e26 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -846,6 +846,20 @@ i2s1: i2s@1c22400 {
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+"allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 27>, <&dma 27>;
+ status = "disabled";
+ };
+
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-codec-i2s";
--
2.25.1
[PATCH v7 08/14] ASoC: sun4i-i2s: fix coding-style for callback definition
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index e7b9dcbf82db..b2923d4c03af 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -180,13 +180,13 @@ struct sun4i_i2s_quirks {
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned intnum_mclk_dividers;
- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
- int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
--
2.25.1
[PATCH v7 06/14] ASoC: sun4i-i2s: Fix sun8i volatile regs
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index d5eba58ff207..3fc0bd818539 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1154,12 +1154,19 @@ static bool sun8i_i2s_rd_reg(struct device *dev,
unsigned int reg)
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
- if (reg == SUN8I_I2S_INT_STA_REG)
+ switch (reg) {
+ case SUN4I_I2S_FIFO_CTRL_REG:
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ case SUN8I_I2S_FIFO_TX_REG:
+ case SUN8I_I2S_INT_STA_REG:
return true;
- if (reg == SUN8I_I2S_FIFO_TX_REG)
- return false;
- return sun4i_i2s_volatile_reg(dev, reg);
+ default:
+ return false;
+ }
}
static const struct reg_default sun4i_i2s_reg_defaults[] = {
--
2.25.1
[PATCH v7 04/14] ASoC: sun4i-i2s: Set sign extend sample
From: Marcus Cooper On the newer SoCs such as the H3 and A64 this is set by default to transfer a 0 after each sample in each slot. However the A10 and A20 SoCs that this driver was developed on had a default setting where it padded the audio gain with zeros. This isn't a problem while we have only support for 16bit audio but with larger sample resolution rates in the pipeline then SEXT bits should be cleared so that they also pad at the LSB. Without this the audio gets distorted. Set sign extend sample for all the sunxi generations even if they are not affected. This will keep consistency and avoid relying on default. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 17 + 1 file changed, 17 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index f1fdb9a0ba54..0b242f4615fe 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -48,6 +48,9 @@ #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) #define SUN4I_I2S_FMT1_REG 0x08 +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) + #define SUN4I_I2S_FIFO_TX_REG 0x0c #define SUN4I_I2S_FIFO_RX_REG 0x10 @@ -105,6 +108,9 @@ #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL(0 << 7) +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) + #define SUN8I_I2S_INT_STA_REG 0x0c #define SUN8I_I2S_FIFO_TX_REG 0x20 @@ -678,6 +684,7 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, } regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + return 0; } @@ -780,6 +787,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } @@ -882,6 +894,11 @@ static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } -- 2.25.1
[PATCH v7 10/14] arm64: dts: allwinner: h6: Add I2S1 node
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 28c77d6872f6..d915aeb13297 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -609,6 +609,19 @@ mdio: mdio {
};
};
+ i2s1: i2s@5091000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x05091000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
--
2.25.1
[PATCH v7 03/14] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit
We are actually using a complex formula to just return a bunch of
simple values. Also this formula is wrong for sun4i when calling
get_wss() the function return 4 instead of 3.
Replace this with a simpler switch case.
Also drop the i2s params which is unused and return a simple int as
returning an error code could be out of range for an s8 and there is
no optim to return a s8 here.
Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation")
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 69 +++--
1 file changed, 44 insertions(+), 25 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 1f577dbc20a6..f1fdb9a0ba54 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -175,8 +175,8 @@ struct sun4i_i2s_quirks {
unsigned intnum_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
- s8 (*get_sr)(const struct sun4i_i2s *, int);
- s8 (*get_wss)(const struct sun4i_i2s *, int);
+ int (*get_sr)(unsigned int width);
+ int (*get_wss)(unsigned int width);
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
@@ -381,37 +381,56 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return 0;
}
-static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_sr(unsigned int width)
{
- if (width < 16 || width > 24)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
+static int sun4i_i2s_get_wss(unsigned int width)
{
- if (width < 16 || width > 32)
- return -EINVAL;
-
- if (width % 4)
- return -EINVAL;
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ case 32:
+ return 3;
+ }
- return (width - 16) / 4;
+ return -EINVAL;
}
-static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
+static int sun8i_i2s_get_sr_wss(unsigned int width)
{
- if (width % 4)
- return -EINVAL;
-
- if (width < 8 || width > 32)
- return -EINVAL;
+ switch (width) {
+ case 8:
+ return 1;
+ case 12:
+ return 2;
+ case 16:
+ return 3;
+ case 20:
+ return 4;
+ case 24:
+ return 5;
+ case 28:
+ return 6;
+ case 32:
+ return 7;
+ }
- return (width - 8) / 4 + 1;
+ return -EINVAL;
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
@@ -574,11 +593,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
}
i2s->playback_dma_data.addr_width = width;
- sr = i2s->variant->get_sr(i2s, word_size);
+ sr = i2s->variant->get_sr(word_size);
if (sr < 0)
return -EINVAL;
- wss = i2s->variant->get_wss(i2s, slot_width);
+ wss = i2s->variant->get_wss(slot_width);
if (wss < 0)
return -EINVAL;
--
2.25.1
[PATCH v7 02/14] ASoC: sun4i-i2s: Add support for H6 I2S
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 222
1 file changed, 222 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index bfbd4207d075..1f577dbc20a6 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -124,6 +124,21 @@
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan)((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
struct sun4i_i2s;
/**
@@ -470,6 +485,60 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -695,6 +764,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s
*i2s,
return 0;
}
+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+* DAI clock polarity
+*
+* The setup for LRCK contradicts the datasheet, but under a
+* scope it's clear that the LRCK polarity is reversed
+* compared to the expected polarity on the bus.
+*/
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
[PATCH v7 05/14] ASoc: sun4i-i2s: Add 20 and 24 bit support
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 0b242f4615fe..d5eba58ff207 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -592,6 +592,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1073,6 +1076,10 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+SNDRV_PCM_FMTBIT_S20_LE | \
+SNDRV_PCM_FMTBIT_S24_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1080,14 +1087,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
--
2.25.1
[PATCH v7 01/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
As slots and slot_width can be set manually using set_tdm().
These values are then kept in sun4i_i2s struct.
So we need to check if these values are set or not.
This is not done actually and will trigger a bug.
For example, if we set to the simple soundcard in the device-tree
dai-tdm-slot-width = <32> and then start a stream using S16_LE,
currently we would calculate BCLK for 32-bit slots, but program
lrck_period for 16-bit slots, making the sample rate double what we
expected.
To fix this, we need to check if these values are set or not but as
this logic is already done by the caller. Avoid duplicating this
logic and just pass the required values as params to set_chan_cfg().
Suggested-by: Samuel Holland
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index f23ff29e7c1d..bfbd4207d075 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -162,8 +162,9 @@ struct sun4i_i2s_quirks {
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
- int (*set_chan_cfg)(const struct sun4i_i2s *,
- const struct snd_pcm_hw_params *);
+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width);
int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
};
@@ -399,10 +400,9 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s
*i2s, int width)
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x3210);
@@ -419,15 +419,11 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
}
static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
- const struct snd_pcm_hw_params *params)
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
{
- unsigned int channels = params_channels(params);
- unsigned int slots = channels;
unsigned int lrck_period;
- if (i2s->slots)
- slots = i2s->slots;
-
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
@@ -452,11 +448,11 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s
*i2s,
case SND_SOC_DAIFMT_DSP_B:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
- lrck_period = params_physical_width(params) * slots;
+ lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_I2S:
- lrck_period = params_physical_width(params);
+ lrck_period = slot_width;
break;
default:
@@ -492,7 +488,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
if (i2s->slot_width)
slot_width = i2s->slot_width;
- ret = i2s->variant->set_chan_cfg(i2s, params);
+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
if (ret < 0) {
dev_err(dai->dev, "Invalid channel configuration\n");
return ret;
--
2.25.1
[PATCH v7 07/14] ASoC: sun4i-i2s: Fix setting of FIFO modes
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 3fc0bd818539..e7b9dcbf82db 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -588,6 +588,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
return ret;
}
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -916,13 +923,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
return ret;
}
- /* Set significant bits in our FIFOs */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
- SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
-
i2s->format = fmt;
return 0;
--
2.25.1
[PATCH v7 00/14] Add Allwinner H3/H5/H6/A64 HDMI audio
Hi, Just some minor changes compare to v6. As explain in v6 there is no more HDMI soundcard, I will try to introduce a dedicated Allwinner soundcard in a next series. Clément Change since v6: - move set_channel_cfg() in first position - convert return value to decimal Change since v5: - Drop HDMI simple soundcard - Collect Chen-Yu Tsai tags - Configure channels from 9 to 15. - Remove DMA RX for H3/H5 - Fix Documentation for H3/H5 Change since v4: - add more comment on get_wss() and set_channel_cfg() patch - merge soundcard and DAI HDMI patches Change since v3: - add Samuel Holland patch to reconfigure FIFO_TX_REG when suspend is enabled - readd inversion to H6 LRCK sun50i_h6_i2s_set_soc_fmt() - Fix get_wss() for sun4i - Add a commit to fix checkpatch warning Change since v2: - rebase on next-20200918 - drop revert LRCK polarity patch - readd simple-audio-card,frame-inversion in dts - Add patch for changing set_chan_cfg params Change since v1: - rebase on next-20200828 - add revert LRCK polarity - remove all simple-audio-card,frame-inversion in dts - add Ondrej patches for Orange Pi board - Add arm64 defconfig patch Clément Péron (6): ASoC: sun4i-i2s: Change set_chan_cfg() params ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit ASoC: sun4i-i2s: Fix sun8i volatile regs ASoC: sun4i-i2s: fix coding-style for callback definition arm64: defconfig: Enable Allwinner i2s driver dt-bindings: sound: sun4i-i2s: Document H3 with missing RX channel possibility Jernej Skrabec (3): ASoC: sun4i-i2s: Add support for H6 I2S dt-bindings: ASoC: sun4i-i2s: Add H6 compatible arm64: dts: allwinner: h6: Add I2S1 node Marcus Cooper (4): ASoC: sun4i-i2s: Set sign extend sample ASoc: sun4i-i2s: Add 20 and 24 bit support arm64: dts: allwinner: a64: Add I2S2 node arm: dts: sunxi: h3/h5: Add I2S2 node Samuel Holland (1): ASoC: sun4i-i2s: Fix setting of FIFO modes .../sound/allwinner,sun4i-a10-i2s.yaml| 6 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi| 13 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 + arch/arm64/configs/defconfig | 1 + sound/soc/sunxi/sun4i-i2s.c | 376 +++--- 6 files changed, 368 insertions(+), 55 deletions(-) -- 2.25.1
[PATCH v7 09/14] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible
From: Jernej Skrabec H6 I2S is very similar to H3, except that it supports up to 16 channels and thus few registers have fields on different position. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Acked-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 112ae00d63c1..606ad2d884a8 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -24,6 +24,7 @@ properties: - items: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s + - const: allwinner,sun50i-h6-i2s reg: maxItems: 1 @@ -59,6 +60,7 @@ allOf: - allwinner,sun8i-a83t-i2s - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s + - allwinner,sun50i-h6-i2s then: required: -- 2.25.1
Re: [PATCH v2] arm64: dts: allwinner: h6: add eMMC voltage property for Beelink GS1
Hi Maxime,
Adding linux-sunxi and Jernej Skrabec to this discussion.
On Thu, 8 Oct 2020 at 17:10, Maxime Ripard wrote:
>
> Hi Clément,
>
> On Mon, Oct 05, 2020 at 08:47:19PM +0200, Clément Péron wrote:
> > On Mon, 5 Oct 2020 at 11:21, Maxime Ripard wrote:
> > >
> > > Hi Clément,
> > >
> > > On Sat, Oct 03, 2020 at 11:20:01AM +0200, Clément Péron wrote:
> > > > Sunxi MMC driver can't distinguish at runtime what's the I/O voltage
> > > > for HS200 mode.
> > >
> > > Unfortunately, that's not true (or at least, that's not related to your
> > > patch).
> > >
> > > > Add a property in the device-tree to notify MMC core about this
> > > > configuration.
> > > >
> > > > Fixes: 089bee8dd119 ("arm64: dts: allwinner: h6: Introduce Beelink GS1
> > > > board")
> > > > Signed-off-by: Clément Péron
> > > > ---
> > > > arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > > > b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > > > index 049c21718846..3f20d2c9 100644
> > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > > > @@ -145,6 +145,7 @@ &mmc2 {
> > > > vqmmc-supply = <®_bldo2>;
> > > > non-removable;
> > > > cap-mmc-hw-reset;
> > > > + mmc-hs200-1_8v;
> > > > bus-width = <8>;
> > > > status = "okay";
> > > > };
> > >
> > > I'm not really sure what you're trying to fix here, but as far as MMC
> > > goes, eMMC's can support io voltage of 3.3, 1.8 and 1.2V. Modes up until
> > > HS DDR (50MHz in DDR) will use an IO voltage of 3.3V, higher speed modes
> > > (HS200 and HS400) supporting 1.8V and 1.2V.
> >
> > Some users report that the eMMC is not working properly on their
> > Beelink GS1 boards.
> >
> > > The mmc-hs200-1_8v property states that the MMC controller supports the
> > > HS200 mode at 1.8V. Now, I can only assume that since BLDO2 is set up at
> > > 1.8V then otherwise, the MMC core will rightfully decide to use the
> > > highest supported mode. In this case, since the driver sets it, it would
> > > be HS-DDR at 3.3V, which won't work with that fixed regulator.
> > >
> > > I can only assume that enabling HS200 at 1.8V only fixes the issue you
> > > have because otherwise it would use HS-DDR at 3.3V, ie not actually
> > > fixing the issue but sweeping it under the rug.
> > >
> > > Trying to add mmc-ddr-1_8v would be a good idea
> >
> > Thanks for the explanation, this is indeed the correct one.
> > So It looks like the SDIO controller has an issue on some boards when
> > using HS-DDR mode.
> >
> > Is this patch acceptable with the proper commit log?
>
> If HS-DDR works, yes, but I assume it doesn't?
After discussing with Jernej about this issue, I understood that:
- Automatic delay calibration is not implemented
- We also miss some handling of DDR related bits in control register
So none of H5/H6 boards should actually work.
(Some 'lucky' boards seem to work enough to switch to HS200 mode...)
To "fix" this the H5 disable the HS-DDR mode in sunxi mmc driver :
https://github.com/torvalds/linux/blob/master/drivers/mmc/host/sunxi-mmc.c#L1409
I'm not sure about A64 but it looks like the property "mmc-hs200-1_8v"
for the PineBook shows the same issue.
The proper way would of course be to implement the missing feature
mentioned above.
But this could take some time and as the eMMC driver is actually
broken wouldn't it be better to disable the HS-DDR for H6 in the mmc
driver like it's done for H5 ?
Regards,
Clement
>
> Maxime
Re: devfreq and panfrost on Allwinner H6
Hi Tomeu, On Wed, 7 Oct 2020 at 10:58, Tomeu Vizoso wrote: > > Hi Clément, > > Have just noticed that my Pine H64 board hangs when I try to set the > performance governor for the GPU devfreq. > > Is this a known bug? Yes it is. I try to summarize everything in this message: https://lkml.org/lkml/2020/8/3/153 Clement > > Thanks, > > Tomeu
[PATCH] dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
Recently introduced Allwinner A100 pinctrl block has 7 interrupts. This trig a warning when running dtb_checks: sun50i-a100-allwinner-perf1.dt.yaml: pinctrl@300b000: interrupts: [...] is too long From schema: .../allwinner,sun4i-a10-pinctrl.yaml Fix this by allowing up to 7 interrupts. Signed-off-by: Clément Péron --- .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 34a17d5c6135..5240487dfe50 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -61,7 +61,7 @@ properties: interrupts: minItems: 1 -maxItems: 5 +maxItems: 7 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. -- 2.25.1
Re: [PATCH v2] arm64: dts: allwinner: h6: add eMMC voltage property for Beelink GS1
Hi Maxime,
On Mon, 5 Oct 2020 at 11:21, Maxime Ripard wrote:
>
> Hi Clément,
>
> On Sat, Oct 03, 2020 at 11:20:01AM +0200, Clément Péron wrote:
> > Sunxi MMC driver can't distinguish at runtime what's the I/O voltage
> > for HS200 mode.
>
> Unfortunately, that's not true (or at least, that's not related to your
> patch).
>
> > Add a property in the device-tree to notify MMC core about this
> > configuration.
> >
> > Fixes: 089bee8dd119 ("arm64: dts: allwinner: h6: Introduce Beelink GS1
> > board")
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > index 049c21718846..3f20d2c9 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> > @@ -145,6 +145,7 @@ &mmc2 {
> > vqmmc-supply = <®_bldo2>;
> > non-removable;
> > cap-mmc-hw-reset;
> > + mmc-hs200-1_8v;
> > bus-width = <8>;
> > status = "okay";
> > };
>
> I'm not really sure what you're trying to fix here, but as far as MMC
> goes, eMMC's can support io voltage of 3.3, 1.8 and 1.2V. Modes up until
> HS DDR (50MHz in DDR) will use an IO voltage of 3.3V, higher speed modes
> (HS200 and HS400) supporting 1.8V and 1.2V.
Some users report that the eMMC is not working properly on their
Beelink GS1 boards.
>
> The mmc-hs200-1_8v property states that the MMC controller supports the
> HS200 mode at 1.8V. Now, I can only assume that since BLDO2 is set up at
> 1.8V then otherwise, the MMC core will rightfully decide to use the
> highest supported mode. In this case, since the driver sets it, it would
> be HS-DDR at 3.3V, which won't work with that fixed regulator.
>
> I can only assume that enabling HS200 at 1.8V only fixes the issue you
> have because otherwise it would use HS-DDR at 3.3V, ie not actually
> fixing the issue but sweeping it under the rug.
>
> Trying to add mmc-ddr-1_8v would be a good idea
Thanks for the explanation, this is indeed the correct one.
So It looks like the SDIO controller has an issue on some boards when
using HS-DDR mode.
Is this patch acceptable with the proper commit log?
It looks like the same issue is happening on A64 Pinebook board.
Thanks
Clement
>
> Maxime
Re: [PATCH v6 03/14] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be more explicit
Hi Maxime,
On Mon, 5 Oct 2020 at 14:14, Maxime Ripard wrote:
>
> On Sat, Oct 03, 2020 at 04:19:39PM +0200, Clément Péron wrote:
> > We are actually using a complex formula to just return a bunch of
> > simple values. Also this formula is wrong for sun4i when calling
> > get_wss() the function return 4 instead of 3.
> >
> > Replace this with a simpler switch case.
> >
> > Also drop the i2s params which is unused and return a simple int as
> > returning an error code could be out of range for an s8 and there is
> > no optim to return a s8 here.
> >
> > Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation")
> > Reviewed-by: Chen-Yu Tsai
> > Signed-off-by: Clément Péron
> > ---
> > sound/soc/sunxi/sun4i-i2s.c | 69 +++--
> > 1 file changed, 44 insertions(+), 25 deletions(-)
> >
> > diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
> > index 1f577dbc20a6..8e497fb3de09 100644
> > --- a/sound/soc/sunxi/sun4i-i2s.c
> > +++ b/sound/soc/sunxi/sun4i-i2s.c
> > @@ -175,8 +175,8 @@ struct sun4i_i2s_quirks {
> > unsigned intnum_mclk_dividers;
> >
> > unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
> > - s8 (*get_sr)(const struct sun4i_i2s *, int);
> > - s8 (*get_wss)(const struct sun4i_i2s *, int);
> > + int (*get_sr)(unsigned int width);
> > + int (*get_wss)(unsigned int width);
> > int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
> > unsigned int channels, unsigned int slots,
> > unsigned int slot_width);
> > @@ -381,37 +381,56 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai
> > *dai,
> > return 0;
> > }
> >
> > -static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
> > +static int sun4i_i2s_get_sr(unsigned int width)
> > {
> > - if (width < 16 || width > 24)
> > - return -EINVAL;
> > -
> > - if (width % 4)
> > - return -EINVAL;
> > + switch (width) {
> > + case 16:
> > + return 0x0;
> > + case 20:
> > + return 0x1;
> > + case 24:
> > + return 0x2;
> > + }
> >
> > - return (width - 16) / 4;
> > + return -EINVAL;
> > }
> >
> > -static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
> > +static int sun4i_i2s_get_wss(unsigned int width)
> > {
> > - if (width < 16 || width > 32)
> > - return -EINVAL;
> > -
> > - if (width % 4)
> > - return -EINVAL;
> > + switch (width) {
> > + case 16:
> > + return 0x0;
> > + case 20:
> > + return 0x1;
> > + case 24:
> > + return 0x2;
> > + case 32:
> > + return 0x3;
> > + }
>
> Like I said in the previous version, I'm not really sure why we need to
> use the hexadecimal representation here?
I'm not sure if there is a convention when to use hexa or when not to use it.
But these figures are taken from the User Manual where register
descriptions are written in Base 2 and default values are written in
Base 16.
It's easier to read them and check that the code follows the documentation, no ?
Indeed with 2 bits this doesn't change anything.
Do you want me to change them in decimal ?
Clement
>
> Maxime
Re: [PATCH v6 02/14] ASoC: sun4i-i2s: Change set_chan_cfg() params
Hi Maxime,
On Mon, 5 Oct 2020 at 14:13, Maxime Ripard wrote:
>
> On Sat, Oct 03, 2020 at 04:19:38PM +0200, Clément Péron wrote:
> > As slots and slot_width can be set manually using set_tdm().
> > These values are then kept in sun4i_i2s struct.
> > So we need to check if these values are setted or not
> > in the struct.
> >
> > Avoid to check for this logic in set_chan_cfg(). This will
> > duplicate the same check instead pass the required values
> > as params to set_chan_cfg().
> >
> > This will also avoid a bug when we will enable 20/24bits support,
> > i2s->slot_width is not actually used in the lrck_period computation.
> >
> > Suggested-by: Samuel Holland
> > Signed-off-by: Clément Péron
> > ---
> > sound/soc/sunxi/sun4i-i2s.c | 36 ++--
> > 1 file changed, 14 insertions(+), 22 deletions(-)
> >
> > diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
> > index c5ccd423e6d3..1f577dbc20a6 100644
> > --- a/sound/soc/sunxi/sun4i-i2s.c
> > +++ b/sound/soc/sunxi/sun4i-i2s.c
> > @@ -177,8 +177,9 @@ struct sun4i_i2s_quirks {
> > unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
> > s8 (*get_sr)(const struct sun4i_i2s *, int);
> > s8 (*get_wss)(const struct sun4i_i2s *, int);
> > - int (*set_chan_cfg)(const struct sun4i_i2s *,
> > - const struct snd_pcm_hw_params *);
> > + int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
> > + unsigned int channels, unsigned int slots,
> > + unsigned int slot_width);
> > int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
> > };
> >
> > @@ -414,10 +415,9 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s
> > *i2s, int width)
> > }
> >
> > static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
> > - const struct snd_pcm_hw_params *params)
> > + unsigned int channels, unsigned int slots,
> > + unsigned int slot_width)
> > {
> > - unsigned int channels = params_channels(params);
> > -
> > /* Map the channels for playback and capture */
> > regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
> > regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x3210);
> > @@ -434,15 +434,11 @@ static int sun4i_i2s_set_chan_cfg(const struct
> > sun4i_i2s *i2s,
> > }
> >
> > static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
> > - const struct snd_pcm_hw_params *params)
> > + unsigned int channels, unsigned int slots,
> > + unsigned int slot_width)
> > {
> > - unsigned int channels = params_channels(params);
> > - unsigned int slots = channels;
> > unsigned int lrck_period;
> >
> > - if (i2s->slots)
> > - slots = i2s->slots;
> > -
> > /* Map the channels for playback and capture */
> > regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
> > regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
> > @@ -467,11 +463,11 @@ static int sun8i_i2s_set_chan_cfg(const struct
> > sun4i_i2s *i2s,
> > case SND_SOC_DAIFMT_DSP_B:
> > case SND_SOC_DAIFMT_LEFT_J:
> > case SND_SOC_DAIFMT_RIGHT_J:
> > - lrck_period = params_physical_width(params) * slots;
> > + lrck_period = slot_width * slots;
> > break;
> >
> > case SND_SOC_DAIFMT_I2S:
> > - lrck_period = params_physical_width(params);
> > + lrck_period = slot_width;
> > break;
> >
> > default:
> > @@ -490,15 +486,11 @@ static int sun8i_i2s_set_chan_cfg(const struct
> > sun4i_i2s *i2s,
> > }
> >
> > static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
> > - const struct snd_pcm_hw_params *params)
> > + unsigned int channels, unsigned int
> > slots,
> > + unsigned int slot_width)
> > {
> > - unsigned int channels = params_channels(params);
> > - unsigned int slots = channels;
> > unsigned int lrck_period;
> >
> > - if (i2s->slots)
> > - slots = i2s->slots;
&g
[PATCH v6 10/14] arm64: dts: allwinner: h6: Add I2S1 node
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 28c77d6872f6..d915aeb13297 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -609,6 +609,19 @@ mdio: mdio {
};
};
+ i2s1: i2s@5091000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x05091000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
--
2.25.1
[PATCH v6 12/14] arm64: defconfig: Enable Allwinner i2s driver
Enable Allwinner I2S driver for arm64 defconfig. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 63003ec116ee..9a3c3bbe60e4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -696,6 +696,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m -- 2.25.1
[PATCH v6 08/14] ASoC: sun4i-i2s: fix coding-style for callback definition
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index fef68146d648..86266879d4bc 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -180,13 +180,13 @@ struct sun4i_i2s_quirks {
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned intnum_mclk_dividers;
- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
- int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
--
2.25.1
[PATCH v6 07/14] ASoC: sun4i-i2s: Fix setting of FIFO modes
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 92671eb94db9..fef68146d648 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -588,6 +588,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
return ret;
}
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -916,13 +923,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
return ret;
}
- /* Set significant bits in our FIFOs */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
- SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
-
i2s->format = fmt;
return 0;
--
2.25.1
[PATCH v6 05/14] ASoc: sun4i-i2s: Add 20 and 24 bit support
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 73103673643a..ba7514849b73 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -592,6 +592,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1073,6 +1076,10 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+SNDRV_PCM_FMTBIT_S20_LE | \
+SNDRV_PCM_FMTBIT_S24_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1080,14 +1087,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
--
2.25.1
[PATCH v6 04/14] ASoC: sun4i-i2s: Set sign extend sample
From: Marcus Cooper On the newer SoCs such as the H3 and A64 this is set by default to transfer a 0 after each sample in each slot. However the A10 and A20 SoCs that this driver was developed on had a default setting where it padded the audio gain with zeros. This isn't a problem while we have only support for 16bit audio but with larger sample resolution rates in the pipeline then SEXT bits should be cleared so that they also pad at the LSB. Without this the audio gets distorted. Set sign extend sample for all the sunxi generations even if they are not affected. This will keep consistency and avoid relying on default. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 17 + 1 file changed, 17 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 8e497fb3de09..73103673643a 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -48,6 +48,9 @@ #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) #define SUN4I_I2S_FMT1_REG 0x08 +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) + #define SUN4I_I2S_FIFO_TX_REG 0x0c #define SUN4I_I2S_FIFO_RX_REG 0x10 @@ -105,6 +108,9 @@ #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL(0 << 7) +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) + #define SUN8I_I2S_INT_STA_REG 0x0c #define SUN8I_I2S_FIFO_TX_REG 0x20 @@ -678,6 +684,7 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, } regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + return 0; } @@ -780,6 +787,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } @@ -882,6 +894,11 @@ static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, val); + /* Set sign extension to pad out LSB with 0 */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, + SUN8I_I2S_FMT1_REG_SEXT_MASK, + SUN8I_I2S_FMT1_REG_SEXT(0)); + return 0; } -- 2.25.1
