[v7,0/2] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v7:
1. [v7,1/2] remove "mediatek,reset-bit" property from 
mediatek-syscon-reset.yaml in [v6,1/3]
2. [v7,2/2] use the flag "MTK_SYSCON_RESET_FLAG" to determine whether to call 
"mtk_syscon_reset",
which integrate assert and deassert together.
3. The patch "[v6,3/3] reset-controller:ti:force the write operation when 
assert or deassert" has been applied

v6:
fix the format error of mediatek-syscon-reset.yaml

v5:
1. revert ti-syscon-reset.txt, and add a new mediatek reset binding.
2. split the patch [v4, 3/4] with the change to force write and the
change to integrate assert and deassert together.
3. separate the dts patch from this patch sets

v4:
fix typos on v3 commit message.

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.

v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct 
value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/


Crystal Guo (2):
  dt-binding: reset-controller: mediatek: add YAML schemas
  reset-controller: ti: introduce an integrated reset handler

 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 drivers/reset/reset-ti-syscon.c   | 39 ++
 2 files changed, 90 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

[v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset
management, and is suitable for Mediatek SoCs.

Signed-off-by: Crystal Guo 
---
 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 1 file changed, 51 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml 
b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index ..85d241cdb0ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+  - Crystal Guo 
+
+description:
+  The bindings describe the reset-controller for Mediatek SoCs,
+  which is based on TI reset controller. For more detail, please
+  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+  compatible:
+const: mediatek,syscon-reset
+
+  '#reset-cells':
+const: 1
+
+  ti,reset-bits:
+description: >
+  Contains the reset control register information, please refer to
+  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+  - compatible
+  - '#reset-cells'
+  - ti,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+infracfg: infracfg@10001000 {
+compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+reg = <0 0x10001000>;
+#clock-cells = <1>;
+
+infracfg_rst: reset-controller {
+compatible = "mediatek,syscon-reset";
+#reset-cells = <1>;
+ti,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+>;
+};
+};
-- 
2.18.0

[v7,2/2] reset-controller: ti: introduce an integrated reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 39 +
 1 file changed, 39 insertions(+)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 218370faf37b..a30cb17362a4 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,15 +15,24 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include 
 
+#define MTK_SYSCON_RESET_FLAG  BIT(0)
+#define MT_RESET_DURATION  10
+
+struct mediatek_reset_data {
+   unsigned int flag;
+};
+
 /**
  * struct ti_syscon_reset_control - reset control structure
  * @assert_offset: reset assert control register offset from syscon base
@@ -56,6 +65,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   const struct mediatek_reset_data *reset_data;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -158,9 +168,32 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int mtk_syscon_reset(struct reset_controller_dev *rcdev, unsigned long 
id)
+{
+   int ret;
+
+   ret = ti_syscon_reset_assert(rcdev, id);
+   if (ret)
+   return ret;
+   usleep_range(MT_RESET_DURATION, MT_RESET_DURATION * 2);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+}
+
+static int ti_syscon_reset(struct reset_controller_dev *rcdev, unsigned long 
id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+
+   if (data->reset_data && data->reset_data->flag & MTK_SYSCON_RESET_FLAG)
+   return mtk_syscon_reset(rcdev, id);
+   else
+   return -ENOTSUPP;
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
+   .reset  = ti_syscon_reset,
.status = ti_syscon_reset_status,
 };
 
@@ -182,6 +215,7 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
 
+   data->reset_data = of_device_get_match_data(>dev);
list = of_get_property(np, "ti,reset-bits", );
if (!list || (size / sizeof(*list)) % 7 != 0) {
dev_err(dev, "invalid DT reset description\n");
@@ -217,8 +251,13 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
return devm_reset_controller_register(dev, >rcdev);
 }
 
+static const struct mediatek_reset_data mtk_reset_data = {
+   .flag = MTK_SYSCON_RESET_FLAG,
+};
+
 static const struct of_device_id ti_syscon_reset_of_match[] = {
{ .compatible = "ti,syscon-reset", },
+   { .compatible = "mediatek,syscon-reset", .data = _reset_data},
{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);
-- 
2.18.0

Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

On Thu, 2020-12-03 at 15:41 +0800, Philipp Zabel wrote:
> Hi,
> 
> On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote:
> > Add a YAML documentation for Mediatek, which uses ti reset-controller
> > driver directly. The TI reset controller provides a common reset
> > management, and is suitable for Mediatek SoCs.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
> >  1 file changed, 51 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml 
> > b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> > new file mode 100644
> > index ..7871550c3c69
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> > @@ -0,0 +1,51 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Reset Controller
> > +
> > +maintainers:
> > +  - Crystal Guo 
> > +
> > +description:
> > +  The bindings describe the reset-controller for Mediatek SoCs,
> > +  which is based on TI reset controller. For more detail, please
> > +  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> > +
> > +properties:
> > +  compatible:
> > +const: mediatek,syscon-reset
> > +
> > +  '#reset-cells':
> > +const: 1
> > +
> > +  mediatek,reset-bits:
> > +description: >
> > +  Contains the reset control register information, please refer to
> > +  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> 
> I would really like some input from Rob on this, in v4 he asked not to
> repeat 'ti,reset-bits'.
> 
> regards
> Philipp


Hi Rob,

Can you give some suggestions on this document
"mediatek-syscon-reset.yaml", many thanks~

regards
Crystal Guo

Re: [v6,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

On Mon, 2020-12-21 at 08:59 +0800, Nicolas Boichat wrote:
> On Mon, Nov 16, 2020 at 8:27 PM Crystal Guo  wrote:
> >
> > Hi Maintainers,
> >
> > Gentle pin for this patch.
> >
> > Thanks
> >
> > On Wed, 2020-10-14 at 21:19 +0800, Crystal Guo wrote:
> > > update mtk-wdt document for MT8192 platform
> 
> Rob: I assume your input is required here? Any chance we could have
> your ack/review on this trivial patch? It seems like the series is
> blocked pending on a review of this patch -- and I don't think it has
> been reviewed before.
> 
> Thanks,
> 
> 

Hi Maintainers,

Just a gentle ping, can you help to review or give some suggestions
about this patch set?

Many thanks.

> > >
> > > Signed-off-by: Crystal Guo 
> > > ---
> > >  Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> > > b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > > index 45eedc2c3141..e36ba60de829 100644
> > > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > > @@ -12,6 +12,7 @@ Required properties:
> > >   "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> > >   "mediatek,mt8183-wdt": for MT8183
> > >   "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> > > + "mediatek,mt8192-wdt": for MT8192
> > >
> > >  - reg : Specifies base physical address and size of the registers.
> > >
> >
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [v6,2/3] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Mon, 2020-11-30 at 18:35 +0800, Ikjoon Jang wrote:
> On Wed, Sep 30, 2020 at 10:21:58AM +0800, Crystal Guo wrote:
> > Introduce ti_syscon_reset() to integrate assert and deassert together.
> > If some modules need do serialized assert and deassert operations
> > to reset itself, reset_control_reset can be called for convenience.
> > 
> > Such as reset-qcom-aoss.c, it integrates assert and deassert together
> > by 'reset' method. MTK Socs also need this method to perform reset.
> > 
> > Signed-off-by: Crystal Guo 
> 
> Reviewed-by: Ikjoon Jang 
> 
> > ---
> >  drivers/reset/reset-ti-syscon.c | 40 -
> >  1 file changed, 39 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/reset/reset-ti-syscon.c 
> > b/drivers/reset/reset-ti-syscon.c
> > index a2635c21db7f..5d1f8306cd4f 100644
> > --- a/drivers/reset/reset-ti-syscon.c
> > +++ b/drivers/reset/reset-ti-syscon.c
> > @@ -15,15 +15,22 @@
> >   * GNU General Public License for more details.
> >   */
> >  
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> >  
> >  #include 
> >  
> > +struct mediatek_reset_data {
> > +   unsigned char *reset_bits;
> > +   unsigned int reset_duration_us;
> > +};
> > +
> >  /**
> >   * struct ti_syscon_reset_control - reset control structure
> >   * @assert_offset: reset assert control register offset from syscon base
> > @@ -56,6 +63,7 @@ struct ti_syscon_reset_data {
> > struct regmap *regmap;
> > struct ti_syscon_reset_control *controls;
> > unsigned int nr_controls;
> > +   const struct mediatek_reset_data *reset_data;
> >  };
> >  
> >  #define to_ti_syscon_reset_data(rcdev) \
> > @@ -158,9 +166,29 @@ static int ti_syscon_reset_status(struct 
> > reset_controller_dev *rcdev,
> > !(control->flags & STATUS_SET);
> >  }
> >  
> > +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > +   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
> > +   int ret;
> > +
> > +   if (data->reset_data) {
> > +   ret = ti_syscon_reset_assert(rcdev, id);
> > +   if (ret)
> > +   return ret;
> > +   usleep_range(data->reset_data->reset_duration_us,
> > +   data->reset_data->reset_duration_us * 2);
> > +
> 
> There are many users using assert() and deassert() seperately
> without any delay between them.
> 
> If there's a timing requirement between assertion and deassertion,
> shouldn't there be a same amount of delay in assert?

The "reset_duration_us" is an optional configuration to make the reset
operation more generic, which was added based on Philipp's comment in
[v2,4/6].

Thanks,
Crystal
> 
> > +   return ti_syscon_reset_deassert(rcdev, id);
> > +   } else {
> > +   return -ENOTSUPP;
> > +   }
> > +}
> > +
> >  static const struct reset_control_ops ti_syscon_reset_ops = {
> > .assert = ti_syscon_reset_assert,
> > .deassert   = ti_syscon_reset_deassert,
> > +   .reset  = ti_syscon_reset,
> > .status = ti_syscon_reset_status,
> >  };
> >  
> > @@ -182,7 +210,11 @@ static int ti_syscon_reset_probe(struct 
> > platform_device *pdev)
> > if (IS_ERR(regmap))
> > return PTR_ERR(regmap);
> >  
> > -   list = of_get_property(np, "ti,reset-bits", );
> > +   data->reset_data = of_device_get_match_data(>dev);
> > +   if (data->reset_data)
> > +   list = of_get_property(np, data->reset_data->reset_bits, );
> > +   else
> > +   list = of_get_property(np, "ti,reset-bits", );
> > if (!list || (size / sizeof(*list)) % 7 != 0) {
> > dev_err(dev, "invalid DT reset description\n");
> > return -EINVAL;
> > @@ -217,8 +249,14 @@ static int ti_syscon_reset_probe(struct 
> > platform_device *pdev)
> > return devm_reset_controller_register(dev, >rcdev);
> >  }
> >  
> > +static const struct mediatek_reset_data mtk_reset_data = {
> > +   .reset_bits = "mediatek,reset-bits",
> > +   .reset_duration_us = 10,
> > +};
> > +
> >  static const struct of_device_id ti_syscon_reset_of_match[] = {
> > { .compatible = "ti,syscon-reset", },
> > +   { .compatible = "mediatek,syscon-reset", .data = _reset_data},
> > { /* sentinel */ },
> >  };
> >  MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);

Re: [v6, 3/3] reset-controller: ti: force the write operation when assert or deassert

[Crystal Guo]

On Mon, 2020-11-30 at 19:13 +0800, Ikjoon Jang wrote:
> On Wed, Sep 30, 2020 at 10:21:59AM +0800, Crystal Guo wrote:
> > Force the write operation in case the read already happens
> > to return the correct value.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  drivers/reset/reset-ti-syscon.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/reset/reset-ti-syscon.c 
> > b/drivers/reset/reset-ti-syscon.c
> > index 5d1f8306cd4f..c34394f1e9e2 100644
> > --- a/drivers/reset/reset-ti-syscon.c
> > +++ b/drivers/reset/reset-ti-syscon.c
> > @@ -97,7 +97,7 @@ static int ti_syscon_reset_assert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->assert_bit);
> > value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
> > value);
> > +   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
> > value);
> >  }
> 
> I don't think there are no reset controllers with cached regmap,
> thus I don't think this is needed.
> Are there any specific reasons behind this, what I've missed here?
> 
> We need to be sure that all other devices using this driver
> should have no side effects on write.
> 
> I can think of a weird controller doing unwanted things internally
> on every write disregarding the current state. (or is this overly
> paranoid?)
> 
The specific reason is that, the clear bit may keep the same value with
the set bit, but the clear operation can be only be completed by writing
1 to the clear bit, not just with the current fake state "1".

> >  
> >  /**
> > @@ -128,7 +128,7 @@ static int ti_syscon_reset_deassert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->deassert_bit);
> > value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
> > value);
> > +   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
> > value);
> >  }
> >  
> >  /**

Re: [v6,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

Hi Maintainers,

Gentle pin for this patch.

Thanks

On Wed, 2020-10-14 at 21:19 +0800, Crystal Guo wrote:
> update mtk-wdt document for MT8192 platform
> 
> Signed-off-by: Crystal Guo 
> ---
>  Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> index 45eedc2c3141..e36ba60de829 100644
> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> @@ -12,6 +12,7 @@ Required properties:
>   "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
>   "mediatek,mt8183-wdt": for MT8183
>   "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> + "mediatek,mt8192-wdt": for MT8192
>  
>  - reg : Specifies base physical address and size of the registers.
>  

Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

Hi Maintainers,

Gentle ping for this patch set.

Many thanks
Crystal

On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote:
> Add a YAML documentation for Mediatek, which uses ti reset-controller
> driver directly. The TI reset controller provides a common reset
> management, and is suitable for Mediatek SoCs.
> 
> Signed-off-by: Crystal Guo 
> ---
>  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
>  1 file changed, 51 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> 
> diff --git 
> a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml 
> b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> new file mode 100644
> index ..7871550c3c69
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Reset Controller
> +
> +maintainers:
> +  - Crystal Guo 
> +
> +description:
> +  The bindings describe the reset-controller for Mediatek SoCs,
> +  which is based on TI reset controller. For more detail, please
> +  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +properties:
> +  compatible:
> +const: mediatek,syscon-reset
> +
> +  '#reset-cells':
> +const: 1
> +
> +  mediatek,reset-bits:
> +description: >
> +  Contains the reset control register information, please refer to
> +  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +required:
> +  - compatible
> +  - '#reset-cells'
> +  - mediatek,reset-bits
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +#include 
> +infracfg: infracfg@10001000 {
> +compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> +reg = <0 0x10001000>;
> +#clock-cells = <1>;
> +
> +infracfg_rst: reset-controller {
> +compatible = "mediatek,syscon-reset";
> +#reset-cells = <1>;
> +mediatek,reset-bits = <
> +   0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | 
> STATUS_NONE)
> +>;
> +};
> +};

[v6,4/4] watchdog: mt8192: add wdt support

[Crystal Guo]

Add support for watchdog device found in MT8192 SoC

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 drivers/watchdog/mtk_wdt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393f609d..aef0c2db6a11 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt8192_data = {
+   .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = _data },
+   { .compatible = "mediatek,mt8192-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
2.18.0

[v6,1/4] dt-binding: mediatek: watchdog: fix the description of compatible

[Crystal Guo]

The watchdog driver for MT2712 and MT8183 relies on DT data, so
the fallback compatible MT6589 won't work.

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd3f1ad..45eedc2c3141 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,13 +4,13 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
-- 
2.18.0

[v6,3/4] dt-binding: mt8192: add toprgu reset-controller head file

[Crystal Guo]

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Acked-by: Guenter Roeck 
---
 .../reset-controller/mt8192-resets.h  | 30 +++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h 
b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index ..be9a7ca245b9
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang 
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8192_TOPRGU_MM_SW_RST1
+#define MT8192_TOPRGU_MFG_SW_RST   2
+#define MT8192_TOPRGU_VENC_SW_RST  3
+#define MT8192_TOPRGU_VDEC_SW_RST  4
+#define MT8192_TOPRGU_IMG_SW_RST   5
+#define MT8192_TOPRGU_MD_SW_RST7
+#define MT8192_TOPRGU_CONN_SW_RST  9
+#define MT8192_TOPRGU_CONN_MCU_SW_RST  12
+#define MT8192_TOPRGU_IPU0_SW_RST  14
+#define MT8192_TOPRGU_IPU1_SW_RST  15
+#define MT8192_TOPRGU_AUDIO_SW_RST 17
+#define MT8192_TOPRGU_CAMSYS_SW_RST18
+#define MT8192_TOPRGU_MJC_SW_RST   19
+#define MT8192_TOPRGU_C2K_S2_SW_RST20
+#define MT8192_TOPRGU_C2K_SW_RST   21
+#define MT8192_TOPRGU_PERI_SW_RST  22
+#define MT8192_TOPRGU_PERI_AO_SW_RST   23
+
+#define MT8192_TOPRGU_SW_RST_NUM   23
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0

[v6,0/4] watchdog: mt8192: add wdt support

[Crystal Guo]

This patches aim to add watchdog support for MT8192.

change in v6:
1. add change log.
2. remove Reviewed-by tag on[v5,2/4]


change in v5:
fix typos on mt8192-reset.h (https://patchwork.kernel.org/patch/11697493/)


change in v4:
just revise v3 commit messages.
[v4,1/5] fix the description of compatible is Reviewed-by: Matthias and Guenter.
[v4,2/5] update watchdog device node for mt8183 is Acked-by: Guenter, and will
be applied to v5.9-next/dts64.
[v4,4/5] add toprgu reset-controller head file for MT8192 platform is 
Reviewed-by: Matthias,
and Acked-by: Guenter.
[v4,5/5] add support for watchdog device found in MT8192 SoC is Reviewed-by: 
Matthias and Guenter.


change in v3:
1. separate [v2,1/3] to fix the original mt2712 and mt8183 compatibles and add 
new board as:
[v3,1/5] fix mt2712 and mt8183 description of compatible, since mt2712
and mt8183 also provide sub-system software reset features, but mt6589 not
support this feature. (Reviewed-by: Matthias)
[v3,2/5] update watchdog device node for mt8183
[v3,3/5] update mtk-wdt document for MT8192 platform
2. [v3, 4/5] is same as [v2,2/3] (Reviewed-by: Matthias)
3. modify the commit message of [v2,3/3]
[v3,5/5] add support for watchdog device found in MT8192 SoC(Reviewed-by: 
Matthias and Guenter)


v2 changes:
Abandon V1 changes,and add the following changes:
[v2,1/3] update mtk-wdt document for mt2712, mt8183 and mt8192.
[v2,2/3] add toprgu reset-controller head file for MT8192 platform 
(Reviewed-by: Matthias)
[v2,3/3] add support for watchdog device found in MT8192 SoC( Reviewed-by: 
Matthias)


v1 changes:
Instead of submit the mt8192-reset.h, get the number of
reset bits from dtsi directly.

Crystal Guo (4):
  dt-binding: mediatek: watchdog: fix the description of compatible
  dt-binding: mediatek: mt8192: update mtk-wdt document
  dt-binding: mt8192: add toprgu reset-controller head file
  watchdog: mt8192: add wdt support

 .../devicetree/bindings/watchdog/mtk-wdt.txt  |  5 ++--
 drivers/watchdog/mtk_wdt.c|  6 
 .../reset-controller/mt8192-resets.h  | 30 +++
 3 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

[v6,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

update mtk-wdt document for MT8192 platform

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 45eedc2c3141..e36ba60de829 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+   "mediatek,mt8192-wdt": for MT8192
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
2.18.0

Re: [v5,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

On Fri, 2020-10-02 at 17:28 +0800, Matthias Brugger wrote:
> 
> On 29/09/2020 05:20, Crystal Guo wrote:
> > update mtk-wdt document for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo 
> > Reviewed-by: Matthias Brugger 
> > Reviewed-by: Guenter Roeck 
> 
> You added Guenters Reviewed-by in v4 of this series, but I don't see that on 
> Guenter provided this tag. In the future please make sure that you don't add 
> tags to your patches that were not provided. This creates great confusion.
> 
> Regards,
> Matthias
> 

Hi Guenter,

Should I remove the "Reviewed-by:Guenter" tag, and re-submit this patch
for your review, or keeping the status quo and wait for Wim's comment?

Thanks
Crystal
> > ---
> >   Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> > b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > index 45eedc2c3141..e36ba60de829 100644
> > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > @@ -12,6 +12,7 @@ Required properties:
> > "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> > "mediatek,mt8183-wdt": for MT8183
> > "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> > +   "mediatek,mt8192-wdt": for MT8192
> >   
> >   - reg : Specifies base physical address and size of the registers.
> >   
> > 

Re: [v5,0/4] watchdog: mt8192: add wdt support

[Crystal Guo]

On Fri, 2020-10-02 at 22:41 +0800, Guenter Roeck wrote:
> On 10/2/20 2:51 AM, Matthias Brugger wrote:
> > 
> > 
> > On 01/10/2020 17:16, Guenter Roeck wrote:
> >> On Thu, Oct 01, 2020 at 04:23:02PM +0200, Matthias Brugger wrote:
> >>> Hi Crystal,
> >>>
> >>> It seems you forgot to send the email to one of the maintainers, Wim.
> >>> Please make sure you add all the maintainers from get_maintainers.pl when
> >>> you send a series.
> >>>
> >>> Regards,
> >>> Matthias
> >>>
> >>> On 29/09/2020 05:20, Crystal Guo wrote:
> >>>> v5 changes:
> >>>> fix typos on:
> >>>> https://patchwork.kernel.org/patch/11697493/
> >>>>
> >>>> v4 changes:
> >>>> revise commit messages.
> >>>>
> >>>> v3 changes:
> >>>> https://patchwork.kernel.org/patch/11692731/
> >>>> https://patchwork.kernel.org/patch/11692767/
> >>>> https://patchwork.kernel.org/patch/11692729/
> >>>> https://patchwork.kernel.org/patch/11692771/
> >>>> https://patchwork.kernel.org/patch/11692733/
> >>
> >> This is less than helpful. It doesn't tell me anything. It expects me to
> >> go back to the earlier versions, download them, and run a diff, to figure
> >> out what changed. That means the patch or patch series ends at the bottom
> >> of my pile of patches to review. Which, as it happens, is quite deep.
> >>
> >> I will review this and similar patches without change log after (and only
> >> after) I have reviewed all other patches in my queue.
> >>
> > 
> > I understand your comments on hard to understand change log. But I think 
> > you acted to quick to put this series to the end of your queue. I'll try to 
> > explain:
> > 
> > In v4 you gave your Acked-by and Reviewed-by for the patches that in this 
> > series are 3/4 [1] and 4/4 [2] respectively. You also gave your Reviewed-by 
> > for 1/4 [3].
> > 
> > In v4 you stated that you wanted to wait for a review from Rob for the 
> > binding changes. Obviously it's up to you to handle that the way you want. 
> > From my point of view these are rather trivial changes.
> > 
> 
> That may be correct, but I am not a DT expert, and it happened often enough
> that I approved a DT change and Rob later raised concerns that I don't do it
> anymore.
> 
> > In 1/4 are deleting compatible fallbacks in the bindings, as the driver 
> > provides SoC specific platform data, which you reviewed.
> > 
> > One can argue that this will break older devicetree bindings because the 
> > driver using the fallback would work except for the topgru reset 
> > controller. But I think this is the job of the maintainer of the driver as 
> > Rob won't be able to look into all the driver code to decide if any change 
> > to the bindings is backward compatible. With your Reviewed-by I understand 
> > that you are OK with this change. As SoC maintainer I'm fine with the 
> > change. MT2701 is a SoC that's not available to the general public. MT8183 
> > is available, but only on chromebooks and I don't expect anybody to use an 
> > older kernel without watchdog driver support for mt8183 (enablement is 
> > still ongoing). Actually I took the DTS counter part already through my 
> > tree, which was an error, as we now have a DTS which does not hold to the 
> > binding description (until and if you accept 1/4).
> > 
> > The only patch missing patch is now 2/4, where Crystal added your 
> > Reviewed-by which you never gave. But it just adds the compatible to the 
> > binding for a driver you already gave your Reviewed-by. So I think this the 
> > series actually just fall through the cracks.
> > 
> > Sorry for the long mail, but if you got until here, I hope I was able to 
> > convince you to just merge the series :)
> > 
> 
> If my Reviewed-by is indeed in all patches, as you state, even if I didn't 
> give it
> to some of those and the submitter just added it (is that acceptable nowadays 
> ?),
> there should be no problem and Wim should pick up the series. And if the 
> submitter
> had bothered to write a proper change log instead of expecting me to do the 
> work
> I would have noticed right away.
> 
> No, this was very appropriately put to the end of my review queue.
> 
> Guenter

Sorry to cause you trouble, I will pay attention to these points in the
future. 

Crystal

Re: [v5,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

On Tue, 2020-09-29 at 23:48 +0800, Rob Herring wrote:
> On Tue, 29 Sep 2020 21:46:40 +0800, Crystal Guo wrote:
> > Add a YAML documentation for Mediatek, which uses ti reset-controller
> > driver directly. The TI reset controller provides a common reset management,
> > and is suitable for Mediatek SoCs.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
> >  1 file changed, 51 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> > 
> 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.example.dt.yaml:
>  example-0: infracfg@10001000:reg:0: [0, 268439552, 0, 4096] is too long
>   From schema: 
> /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
> 
> 
> See https://patchwork.ozlabs.org/patch/1373428
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
> 
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master 
> --upgrade
> 
> Please check and re-submit.
> 

Thanks for your remind, re-submit at:
https://patchwork.kernel.org/patch/11807721/

[v6,3/3] reset-controller: ti: force the write operation when assert or deassert

[Crystal Guo]

Force the write operation in case the read already happens
to return the correct value.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 5d1f8306cd4f..c34394f1e9e2 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -97,7 +97,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev 
*rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
value);
 }
 
 /**
@@ -128,7 +128,7 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
value);
 }
 
 /**
-- 
2.18.0

[v6,2/3] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 40 -
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..5d1f8306cd4f 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,15 +15,22 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include 
 
+struct mediatek_reset_data {
+   unsigned char *reset_bits;
+   unsigned int reset_duration_us;
+};
+
 /**
  * struct ti_syscon_reset_control - reset control structure
  * @assert_offset: reset assert control register offset from syscon base
@@ -56,6 +63,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   const struct mediatek_reset_data *reset_data;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -158,9 +166,29 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+   int ret;
+
+   if (data->reset_data) {
+   ret = ti_syscon_reset_assert(rcdev, id);
+   if (ret)
+   return ret;
+   usleep_range(data->reset_data->reset_duration_us,
+   data->reset_data->reset_duration_us * 2);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+   } else {
+   return -ENOTSUPP;
+   }
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
+   .reset  = ti_syscon_reset,
.status = ti_syscon_reset_status,
 };
 
@@ -182,7 +210,11 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
 
-   list = of_get_property(np, "ti,reset-bits", );
+   data->reset_data = of_device_get_match_data(>dev);
+   if (data->reset_data)
+   list = of_get_property(np, data->reset_data->reset_bits, );
+   else
+   list = of_get_property(np, "ti,reset-bits", );
if (!list || (size / sizeof(*list)) % 7 != 0) {
dev_err(dev, "invalid DT reset description\n");
return -EINVAL;
@@ -217,8 +249,14 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
return devm_reset_controller_register(dev, >rcdev);
 }
 
+static const struct mediatek_reset_data mtk_reset_data = {
+   .reset_bits = "mediatek,reset-bits",
+   .reset_duration_us = 10,
+};
+
 static const struct of_device_id ti_syscon_reset_of_match[] = {
{ .compatible = "ti,syscon-reset", },
+   { .compatible = "mediatek,syscon-reset", .data = _reset_data},
{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);
-- 
2.18.0

[v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset
management, and is suitable for Mediatek SoCs.

Signed-off-by: Crystal Guo 
---
 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 1 file changed, 51 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml 
b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index ..7871550c3c69
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+  - Crystal Guo 
+
+description:
+  The bindings describe the reset-controller for Mediatek SoCs,
+  which is based on TI reset controller. For more detail, please
+  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+  compatible:
+const: mediatek,syscon-reset
+
+  '#reset-cells':
+const: 1
+
+  mediatek,reset-bits:
+description: >
+  Contains the reset control register information, please refer to
+  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+  - compatible
+  - '#reset-cells'
+  - mediatek,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+infracfg: infracfg@10001000 {
+compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+reg = <0 0x10001000>;
+#clock-cells = <1>;
+
+infracfg_rst: reset-controller {
+compatible = "mediatek,syscon-reset";
+#reset-cells = <1>;
+mediatek,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+>;
+};
+};
-- 
2.18.0

[v6,0/3] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v6:
fix the format error of mediatek-syscon-reset.yaml

v5:
1. revert ti-syscon-reset.txt, and add a new mediatek reset binding.
2. split the patch [v4, 3/4] with the change to force write and the
change to integrate assert and deassert together.
3. separate the dts patch from this patch sets

v4:
fix typos on v3 commit message.

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.

v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct 
value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/

Crystal Guo (3):
  dt-binding: reset-controller: mediatek: add YAML schemas
  reset-controller: ti: introduce a new reset handler
  reset-controller: ti: force the write operation when assert or
deassert

 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 drivers/reset/reset-ti-syscon.c   | 44 ++--
 2 files changed, 92 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

Re: [v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Mon, 2020-09-14 at 22:00 +0800, Crystal Guo wrote:
> On Fri, 2020-09-11 at 22:44 +0800, Suman Anna wrote:
> > On 9/11/20 9:26 AM, Philipp Zabel wrote:
> > > Hi Crystal,
> > > 
> > > On Fri, 2020-09-11 at 14:07 +0800, Crystal Guo wrote:
> > > [...]
> > >> Should I add the SoC-specific data as follows?
> > >> This may also modify the ti original code, is it OK?
> > >>
> > >> +   data->reset_data = of_device_get_match_data(>dev);
> > >> +
> > >> +   list = of_get_property(np, data->reset_data->reset_bits, );
> > >>
> > >> +static const struct common_reset_data ti_reset_data = {
> > >> +   .reset_op_available = false,
> > >> +   .reset_bits = "ti, reset-bits",
> > > ^
> > > That space doesn't belong there.
> > > 
> > >> +};
> > >> +
> > >> +static const struct common_reset_data mediatek_reset_data = {
> > >> +   .reset_op_available = true,
> > >> +   .reset_bits = "mediatek, reset-bits",
> > >> +};
> > > 
> > > I understand Robs comments as meaning "ti,reset-bits" should have been
> > > called "reset-bits" in the first place, and you shouldn't repeat adding
> > > the vendor prefix, as that is implied by the compatible. So this should
> > > probably be just "reset-bits".
> > 
> > Hmm, not sure about that. I think Rob wants the reset data itself to be 
> > added in
> > the driver as is being done on some other SoCs (eg: like in 
> > reset-qcom-pdc.c).
> > 
> > regards
> > Suman
> > 
> Hi Rob,
> 
> Can you help to comment about this point?
> Modify "ti,reset-bits" to "reset-bits" or add "mediatek,reset-bits" ?
> 
> Many thanks~
> Crystal
> 
> > > 
> > > Otherwise this looks like it should work.
> > > 
> > > regards
> > > Philipp
> > > 
> > 

Dears,

I have uploaded the changes at
https://patchwork.kernel.org/cover/11805937/
Please help me to review, many thanks~~

regards
Crystal
> 

[v5,0/3] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v5:
1. revert ti-syscon-reset.txt, and add a new mediatek reset binding.
2. split the patch [v4, 3/4] with the change to force write and the
change to integrate assert and deassert together.
3. separate the dts patch from this patch sets

v4:
fix typos on v3 commit message.

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.

v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct 
value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/

Crystal Guo (3):
  dt-binding: reset-controller: mediatek: add YAML schemas
  reset-controller: ti: introduce a new reset handler
  reset-controller: ti: force the write operation when assert or
deassert

 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 drivers/reset/reset-ti-syscon.c   | 44 ++--
 2 files changed, 92 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

[v5,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset management,
and is suitable for Mediatek SoCs.

Signed-off-by: Crystal Guo 
---
 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++
 1 file changed, 51 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml 
b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index ..dab630e95a0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+  - Crystal Guo 
+
+description:
+  The bindings describe the reset-controller for Mediatek SoCs,
+  which is based on TI reset controller. For more detail, please
+  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+  compatible:
+const: mediatek,syscon-reset
+
+  '#reset-cells':
+const: 1
+
+  mediatek,reset-bits:
+description: >
+  Contains the reset control register information, please refer to
+  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+  - compatible
+  - '#reset-cells'
+  - mediatek,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+infracfg: infracfg@10001000 {
+compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+reg = <0 0x10001000 0 0x1000>;
+#clock-cells = <1>;
+
+infracfg_rst: reset-controller {
+compatible = "mediatek,syscon-reset";
+#reset-cells = <1>;
+mediatek,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+>;
+};
+};
-- 
2.18.0

[v5,3/3] reset-controller: ti: force the write operation when assert or deassert

[Crystal Guo]

Force the write operation in case the read already happens
to return the correct value.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 5d1f8306cd4f..c34394f1e9e2 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -97,7 +97,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev 
*rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
value);
 }
 
 /**
@@ -128,7 +128,7 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
value);
 }
 
 /**
-- 
2.18.0

[v5,2/3] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 40 -
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..5d1f8306cd4f 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,15 +15,22 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include 
 
+struct mediatek_reset_data {
+   unsigned char *reset_bits;
+   unsigned int reset_duration_us;
+};
+
 /**
  * struct ti_syscon_reset_control - reset control structure
  * @assert_offset: reset assert control register offset from syscon base
@@ -56,6 +63,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   const struct mediatek_reset_data *reset_data;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -158,9 +166,29 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+   int ret;
+
+   if (data->reset_data) {
+   ret = ti_syscon_reset_assert(rcdev, id);
+   if (ret)
+   return ret;
+   usleep_range(data->reset_data->reset_duration_us,
+   data->reset_data->reset_duration_us * 2);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+   } else {
+   return -ENOTSUPP;
+   }
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
+   .reset  = ti_syscon_reset,
.status = ti_syscon_reset_status,
 };
 
@@ -182,7 +210,11 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
 
-   list = of_get_property(np, "ti,reset-bits", );
+   data->reset_data = of_device_get_match_data(>dev);
+   if (data->reset_data)
+   list = of_get_property(np, data->reset_data->reset_bits, );
+   else
+   list = of_get_property(np, "ti,reset-bits", );
if (!list || (size / sizeof(*list)) % 7 != 0) {
dev_err(dev, "invalid DT reset description\n");
return -EINVAL;
@@ -217,8 +249,14 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
return devm_reset_controller_register(dev, >rcdev);
 }
 
+static const struct mediatek_reset_data mtk_reset_data = {
+   .reset_bits = "mediatek,reset-bits",
+   .reset_duration_us = 10,
+};
+
 static const struct of_device_id ti_syscon_reset_of_match[] = {
{ .compatible = "ti,syscon-reset", },
+   { .compatible = "mediatek,syscon-reset", .data = _reset_data},
{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);
-- 
2.18.0

[v5,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

update mtk-wdt document for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 45eedc2c3141..e36ba60de829 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+   "mediatek,mt8192-wdt": for MT8192
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
2.18.0

[v5,4/4] watchdog: mt8192: add wdt support

[Crystal Guo]

Add support for watchdog device found in MT8192 SoC

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 drivers/watchdog/mtk_wdt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393f609d..aef0c2db6a11 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt8192_data = {
+   .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = _data },
+   { .compatible = "mediatek,mt8192-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
2.18.0

[v5,1/4] dt-binding: mediatek: watchdog: fix the description of compatible

[Crystal Guo]

The watchdog driver for MT2712 and MT8183 relies on DT data, so
the fallback compatible MT6589 won't work.

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd3f1ad..45eedc2c3141 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,13 +4,13 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
-- 
2.18.0

[v5,0/4] watchdog: mt8192: add wdt support

[Crystal Guo]

v5 changes:
fix typos on:
https://patchwork.kernel.org/patch/11697493/

v4 changes:
revise commit messages.

v3 changes:
https://patchwork.kernel.org/patch/11692731/
https://patchwork.kernel.org/patch/11692767/
https://patchwork.kernel.org/patch/11692729/
https://patchwork.kernel.org/patch/11692771/
https://patchwork.kernel.org/patch/11692733/

Crystal Guo (4):
  dt-binding: mediatek: watchdog: fix the description of compatible
  dt-binding: mediatek: mt8192: update mtk-wdt document
  dt-binding: mt8192: add toprgu reset-controller head file
  watchdog: mt8192: add wdt support

 .../devicetree/bindings/watchdog/mtk-wdt.txt   |  5 ++--
 drivers/watchdog/mtk_wdt.c |  6 +
 .../dt-bindings/reset-controller/mt8192-resets.h   | 30 ++
 3 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

[v5,3/4] dt-binding: mt8192: add toprgu reset-controller head file

[Crystal Guo]

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Acked-by: Guenter Roeck 
---
 .../reset-controller/mt8192-resets.h  | 30 +++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h 
b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index ..be9a7ca245b9
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang 
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8192_TOPRGU_MM_SW_RST1
+#define MT8192_TOPRGU_MFG_SW_RST   2
+#define MT8192_TOPRGU_VENC_SW_RST  3
+#define MT8192_TOPRGU_VDEC_SW_RST  4
+#define MT8192_TOPRGU_IMG_SW_RST   5
+#define MT8192_TOPRGU_MD_SW_RST7
+#define MT8192_TOPRGU_CONN_SW_RST  9
+#define MT8192_TOPRGU_CONN_MCU_SW_RST  12
+#define MT8192_TOPRGU_IPU0_SW_RST  14
+#define MT8192_TOPRGU_IPU1_SW_RST  15
+#define MT8192_TOPRGU_AUDIO_SW_RST 17
+#define MT8192_TOPRGU_CAMSYS_SW_RST18
+#define MT8192_TOPRGU_MJC_SW_RST   19
+#define MT8192_TOPRGU_C2K_S2_SW_RST20
+#define MT8192_TOPRGU_C2K_SW_RST   21
+#define MT8192_TOPRGU_PERI_SW_RST  22
+#define MT8192_TOPRGU_PERI_AO_SW_RST   23
+
+#define MT8192_TOPRGU_SW_RST_NUM   23
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0

Re: [v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Fri, 2020-09-11 at 22:44 +0800, Suman Anna wrote:
> On 9/11/20 9:26 AM, Philipp Zabel wrote:
> > Hi Crystal,
> > 
> > On Fri, 2020-09-11 at 14:07 +0800, Crystal Guo wrote:
> > [...]
> >> Should I add the SoC-specific data as follows?
> >> This may also modify the ti original code, is it OK?
> >>
> >> +   data->reset_data = of_device_get_match_data(>dev);
> >> +
> >> +   list = of_get_property(np, data->reset_data->reset_bits, );
> >>
> >> +static const struct common_reset_data ti_reset_data = {
> >> +   .reset_op_available = false,
> >> +   .reset_bits = "ti, reset-bits",
> > ^
> > That space doesn't belong there.
> > 
> >> +};
> >> +
> >> +static const struct common_reset_data mediatek_reset_data = {
> >> +   .reset_op_available = true,
> >> +   .reset_bits = "mediatek, reset-bits",
> >> +};
> > 
> > I understand Robs comments as meaning "ti,reset-bits" should have been
> > called "reset-bits" in the first place, and you shouldn't repeat adding
> > the vendor prefix, as that is implied by the compatible. So this should
> > probably be just "reset-bits".
> 
> Hmm, not sure about that. I think Rob wants the reset data itself to be added 
> in
> the driver as is being done on some other SoCs (eg: like in reset-qcom-pdc.c).
> 
> regards
> Suman
> 
Hi Rob,

Can you help to comment about this point?
Modify "ti,reset-bits" to "reset-bits" or add "mediatek,reset-bits" ?

Many thanks~
Crystal

> > 
> > Otherwise this looks like it should work.
> > 
> > regards
> > Philipp
> > 
> 

Re: [v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Fri, 2020-09-11 at 10:52 +0800, Suman Anna wrote:
> On 9/10/20 9:42 PM, Crystal Guo wrote:
> > On Wed, 2020-09-09 at 23:39 +0800, Suman Anna wrote:
> >> On 9/8/20 9:57 PM, Crystal Guo wrote:
> >>> On Thu, 2020-09-03 at 07:40 +0800, Suman Anna wrote:
> >>>> Hi Crystal,
> >>>>
> >>>> On 8/16/20 10:03 PM, Crystal Guo wrote:
> >>>>> Introduce ti_syscon_reset() to integrate assert and deassert together.
> >>>>> If some modules need do serialized assert and deassert operations
> >>>>> to reset itself, reset_control_reset can be called for convenience.
> >>>>
> >>>> There are multiple changes in this same patch. I think you should split 
> >>>> this
> >>>> functionality away from the change for the regmap_update_bits() to
> >>>> regmap_write_bits(), similar to what you have done in your v2 Patch 4.
> >>>>
> >>>
> >>> Thanks for your suggestion.
> >>> I will split this patch in the next version.
> >>>
> >>>>>
> >>>>> Such as reset-qcom-aoss.c, it integrates assert and deassert together
> >>>>> by 'reset' method. MTK Socs also need this method to perform reset.
> >>>>>
> >>>>> Signed-off-by: Crystal Guo 
> >>>>> ---
> >>>>>  drivers/reset/reset-ti-syscon.c | 26 --
> >>>>>  1 file changed, 24 insertions(+), 2 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/reset/reset-ti-syscon.c 
> >>>>> b/drivers/reset/reset-ti-syscon.c
> >>>>> index a2635c21db7f..08289342f9af 100644
> >>>>> --- a/drivers/reset/reset-ti-syscon.c
> >>>>> +++ b/drivers/reset/reset-ti-syscon.c
> >>>>> @@ -15,6 +15,7 @@
> >>>>>   * GNU General Public License for more details.
> >>>>>   */
> >>>>>  
> >>>>> +#include 
> >>>>>  #include 
> >>>>>  #include 
> >>>>>  #include 
> >>>>> @@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
> >>>>> struct regmap *regmap;
> >>>>> struct ti_syscon_reset_control *controls;
> >>>>> unsigned int nr_controls;
> >>>>> +   unsigned int reset_duration_us;
> >>>>>  };
> >>>>>  
> >>>>>  #define to_ti_syscon_reset_data(rcdev) \
> >>>>> @@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct 
> >>>>> reset_controller_dev *rcdev,
> >>>>> mask = BIT(control->assert_bit);
> >>>>> value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >>>>>  
> >>>>> -   return regmap_update_bits(data->regmap, control->assert_offset, 
> >>>>> mask, value);
> >>>>> +   return regmap_write_bits(data->regmap, control->assert_offset, 
> >>>>> mask, value);
> >>>>>  }
> >>>>>  
> >>>>>  /**
> >>>>> @@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct 
> >>>>> reset_controller_dev *rcdev,
> >>>>> mask = BIT(control->deassert_bit);
> >>>>> value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >>>>>  
> >>>>> -   return regmap_update_bits(data->regmap, 
> >>>>> control->deassert_offset, mask, value);
> >>>>> +   return regmap_write_bits(data->regmap, 
> >>>>> control->deassert_offset, mask, value);
> >>>>>  }
> >>>>>  
> >>>>>  /**
> >>>>> @@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct 
> >>>>> reset_controller_dev *rcdev,
> >>>>> !(control->flags & STATUS_SET);
> >>>>>  }
> >>>>>  
> >>>>> +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> >>>>> + unsigned long id)
> >>>>> +{
> >>>>> +   struct ti_syscon_reset_data *data = 
> >>>>> to_ti_syscon_reset_data(rcdev);
> >>>>> +   int ret;
> >>>>> +
> >>>>> +   ret = ti_syscon_reset_assert(rcdev, id);

Re: [v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Wed, 2020-09-09 at 23:39 +0800, Suman Anna wrote:
> On 9/8/20 9:57 PM, Crystal Guo wrote:
> > On Thu, 2020-09-03 at 07:40 +0800, Suman Anna wrote:
> >> Hi Crystal,
> >>
> >> On 8/16/20 10:03 PM, Crystal Guo wrote:
> >>> Introduce ti_syscon_reset() to integrate assert and deassert together.
> >>> If some modules need do serialized assert and deassert operations
> >>> to reset itself, reset_control_reset can be called for convenience.
> >>
> >> There are multiple changes in this same patch. I think you should split 
> >> this
> >> functionality away from the change for the regmap_update_bits() to
> >> regmap_write_bits(), similar to what you have done in your v2 Patch 4.
> >>
> > 
> > Thanks for your suggestion.
> > I will split this patch in the next version.
> > 
> >>>
> >>> Such as reset-qcom-aoss.c, it integrates assert and deassert together
> >>> by 'reset' method. MTK Socs also need this method to perform reset.
> >>>
> >>> Signed-off-by: Crystal Guo 
> >>> ---
> >>>  drivers/reset/reset-ti-syscon.c | 26 --
> >>>  1 file changed, 24 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/reset/reset-ti-syscon.c 
> >>> b/drivers/reset/reset-ti-syscon.c
> >>> index a2635c21db7f..08289342f9af 100644
> >>> --- a/drivers/reset/reset-ti-syscon.c
> >>> +++ b/drivers/reset/reset-ti-syscon.c
> >>> @@ -15,6 +15,7 @@
> >>>   * GNU General Public License for more details.
> >>>   */
> >>>  
> >>> +#include 
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>> @@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
> >>>   struct regmap *regmap;
> >>>   struct ti_syscon_reset_control *controls;
> >>>   unsigned int nr_controls;
> >>> + unsigned int reset_duration_us;
> >>>  };
> >>>  
> >>>  #define to_ti_syscon_reset_data(rcdev)   \
> >>> @@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct 
> >>> reset_controller_dev *rcdev,
> >>>   mask = BIT(control->assert_bit);
> >>>   value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >>>  
> >>> - return regmap_update_bits(data->regmap, control->assert_offset, mask, 
> >>> value);
> >>> + return regmap_write_bits(data->regmap, control->assert_offset, mask, 
> >>> value);
> >>>  }
> >>>  
> >>>  /**
> >>> @@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct 
> >>> reset_controller_dev *rcdev,
> >>>   mask = BIT(control->deassert_bit);
> >>>   value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >>>  
> >>> - return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
> >>> value);
> >>> + return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
> >>> value);
> >>>  }
> >>>  
> >>>  /**
> >>> @@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct 
> >>> reset_controller_dev *rcdev,
> >>>   !(control->flags & STATUS_SET);
> >>>  }
> >>>  
> >>> +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> >>> +   unsigned long id)
> >>> +{
> >>> + struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
> >>> + int ret;
> >>> +
> >>> + ret = ti_syscon_reset_assert(rcdev, id);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + if (data->reset_duration_us)
> >>> + usleep_range(data->reset_duration_us, data->reset_duration_us * 
> >>> 2);
> >>> +
> >>> + return ti_syscon_reset_deassert(rcdev, id);
> >>
> >> I echo Philipp's comments [1] from your original v1 series about this. We 
> >> don't
> >> need a property to distinguish this, but you could add a flag using match 
> >> data
> >> and Mediatek compatible, and use that within this function, or optionally 
> >> set
> >> this ops based on compatible (whatever is preferred by Philipp).
> >>
> >> regards
> >> Suman
> >>
> >> [1] https://patchwork.kernel.org/comment/23519193/
> >>

Re: [v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

On Thu, 2020-09-03 at 07:40 +0800, Suman Anna wrote:
> Hi Crystal,
> 
> On 8/16/20 10:03 PM, Crystal Guo wrote:
> > Introduce ti_syscon_reset() to integrate assert and deassert together.
> > If some modules need do serialized assert and deassert operations
> > to reset itself, reset_control_reset can be called for convenience.
> 
> There are multiple changes in this same patch. I think you should split this
> functionality away from the change for the regmap_update_bits() to
> regmap_write_bits(), similar to what you have done in your v2 Patch 4.
> 

Thanks for your suggestion.
I will split this patch in the next version.

> > 
> > Such as reset-qcom-aoss.c, it integrates assert and deassert together
> > by 'reset' method. MTK Socs also need this method to perform reset.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  drivers/reset/reset-ti-syscon.c | 26 --
> >  1 file changed, 24 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/reset/reset-ti-syscon.c 
> > b/drivers/reset/reset-ti-syscon.c
> > index a2635c21db7f..08289342f9af 100644
> > --- a/drivers/reset/reset-ti-syscon.c
> > +++ b/drivers/reset/reset-ti-syscon.c
> > @@ -15,6 +15,7 @@
> >   * GNU General Public License for more details.
> >   */
> >  
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
> > struct regmap *regmap;
> > struct ti_syscon_reset_control *controls;
> > unsigned int nr_controls;
> > +   unsigned int reset_duration_us;
> >  };
> >  
> >  #define to_ti_syscon_reset_data(rcdev) \
> > @@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->assert_bit);
> > value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
> > value);
> > +   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
> > value);
> >  }
> >  
> >  /**
> > @@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->deassert_bit);
> > value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
> > value);
> > +   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
> > value);
> >  }
> >  
> >  /**
> > @@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct 
> > reset_controller_dev *rcdev,
> > !(control->flags & STATUS_SET);
> >  }
> >  
> > +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > +   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
> > +   int ret;
> > +
> > +   ret = ti_syscon_reset_assert(rcdev, id);
> > +   if (ret)
> > +   return ret;
> > +
> > +   if (data->reset_duration_us)
> > +   usleep_range(data->reset_duration_us, data->reset_duration_us * 
> > 2);
> > +
> > +   return ti_syscon_reset_deassert(rcdev, id);
> 
> I echo Philipp's comments [1] from your original v1 series about this. We 
> don't
> need a property to distinguish this, but you could add a flag using match data
> and Mediatek compatible, and use that within this function, or optionally set
> this ops based on compatible (whatever is preferred by Philipp).
> 
> regards
> Suman
> 
> [1] https://patchwork.kernel.org/comment/23519193/
> 
Hi Suman, Philipp

Which method would you recommend more?
1. like v2 patch, but assign the flag "data->assert_deassert_together"
directly (maybe rename "assert_deassert_together" to
"reset_op_available")

2. use Mediatek compatible to decide the reset handler available or not.

Thanks
Crystal

> > +}
> > +
> >  static const struct reset_control_ops ti_syscon_reset_ops = {
> > .assert = ti_syscon_reset_assert,
> > .deassert   = ti_syscon_reset_deassert,
> > +   .reset  = ti_syscon_reset,
> > .status = ti_syscon_reset_status,
> >  };
> >  
> > @@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device 
> > *pdev)
> > controls[i].flags = be32_to_cpup(list++);
> > }
> >  
> > +   of_property_read_u32(pdev->dev.of_node, "reset-duration-us",
> > +   >reset_duration_us);
> > +
> > data->rcdev.ops = _syscon_reset_ops;
> > data->rcdev.owner = THIS_MODULE;
> > data->rcdev.of_node = np;
> > 
> 

Re: [v4,4/4] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

On Thu, 2020-09-03 at 07:29 +0800, Suman Anna wrote:
> Hi Crystal,
> 
> On 8/16/20 10:03 PM, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo 
> 
> I understand you are posting these together for complete reference, but driver
> subsystem maintainers typically don't pick dts patches. In anycase, can you
> clarify if your registers are self-clearing registers?
> 
> regards
> Suman
> 
Hi Suman,

Thanks for your reply.
Our reset registers are not self-clearing, it needs to set the clear bit
to 1 to clear the related bit.
And should I separate this dts patch from the patch sets?

regards
Crystal
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 931e1ca17220..a0cb9904706b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -10,6 +10,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  / {
> > compatible = "mediatek,mt8192";
> > @@ -219,9 +220,17 @@
> > };
> >  
> > infracfg: infracfg@10001000 {
> > -   compatible = "mediatek,mt8192-infracfg", "syscon";
> > +   compatible = "mediatek,mt8192-infracfg", "syscon", 
> > "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > +   infracfg_rst: reset-controller {
> > +   compatible = "mediatek,infra-reset", 
> > "ti,syscon-reset";
> > +   #reset-cells = <1>;
> > +   ti,reset-bits = <
> > +   0x140 15 0x144 15 0 0 (ASSERT_SET | 
> > DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> > +   >;
> > +   };
> > };
> >  
> > pericfg: pericfg@10003000 {
> > 
> 

Re: [v4,0/4] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

Hi Rob, Philipp, Matthias and all

Gentle ping for this patch set.

Thanks
Crystal

> 
> -Original Message-
> From: Crystal Guo [mailto:crystal@mediatek.com]
> Sent: Monday, August 17, 2020 11:03 AM
> To: p.za...@pengutronix.de; robh...@kernel.org; matthias@gmail.com
> Cc: srv_heupstream; linux-media...@lists.infradead.org; 
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; 
> devicet...@vger.kernel.org; s-a...@ti.com; a...@ti.com; Seiya Wang (王迺君); 
> Stanley Chu (朱原陞); Yingjoe Chen (陳英洲); Fan Chen (陳凡); Yong Liang (梁勇)
> Subject: [v4,0/4] introduce TI reset controller for MT8192 SoC
> 
> v4:
> fix typos on v3 commit message.
> 
> v3:
> 1. revert v2 changes.
> 2. add 'reset-duration-us' property to declare a minimum delay, which needs 
> to be waited between assert and deassert.
> 3. add 'mediatek,infra-reset' to compatible.
> 
> 
> v2 changes:
> https://patchwork.kernel.org/patch/11697371/
> 1. add 'assert-deassert-together' property to introduce a new reset handler, 
> which allows device to do serialized assert and deassert operations in a 
> single step by 'reset' method.
> 2. add 'update-force' property to introduce force-update method, which forces 
> the write operation in case the read already happens to return the correct 
> value.
> 3. add 'generic-reset' to compatible
> 
> v1 changes:
> https://patchwork.kernel.org/patch/11690523/
> https://patchwork.kernel.org/patch/11690527/
> 
> Crystal Guo (4):
>   dt-binding: reset-controller: ti: add reset-duration-us property
>   dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to
> compatible
>   reset-controller: ti: introduce a new reset handler
>   arm64: dts: mt8192: add infracfg_rst node
> 
>  .../bindings/reset/ti-syscon-reset.txt|  6 +
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 11 +++-
>  drivers/reset/reset-ti-syscon.c   | 26 +--
>  3 files changed, 40 insertions(+), 3 deletions(-)
> 
> 
> *MEDIATEK Confidential/Internal Use*

Re: [v4,2/4] dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to compatible

[Crystal Guo]

On Wed, 2020-08-26 at 03:02 +0800, Rob Herring wrote:
> On Mon, Aug 17, 2020 at 11:03:22AM +0800, Crystal Guo wrote:
> > The TI syscon reset controller provides a common reset management,
> > and is suitable for MTK SoCs. Add compatible 'mediatek,infra-reset',
> > which denotes to use ti reset-controller driver directly.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
> > b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > index ab041032339b..5a0e9365b51b 100644
> > --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > @@ -25,6 +25,7 @@ Required properties:
> > "ti,k2l-pscrst"
> > "ti,k2hk-pscrst"
> > "ti,syscon-reset"
> > +   "mediatek,infra-reset", "ti,syscon-reset"
> 
> You need your own binding doc. If you can use the same driver then fine, 
> but that's a separate issue. There's also reset-simple driver if you 
> have just array of 32-bit registers with a bit per reset.
> 
> Don't repeat 'ti,reset-bits' either.

Do you mean I should add a Mediatek reset binding doc, although Mediatek
reuse the TI reset controller directly?

Best Regards
Crystal
> 
> >   - #reset-cells: Should be 1. Please see the reset consumer 
> > node below
> >   for usage details
> >   - ti,reset-bits   : Contains the reset control register information
> > -- 
> > 2.18.0

Re: [v4,1/4] dt-binding: reset-controller: ti: add reset-duration-us property

[Crystal Guo]

On Wed, 2020-08-26 at 01:42 +0800, Rob Herring wrote:
> On Mon, Aug 17, 2020 at 11:03:21AM +0800, Crystal Guo wrote:
> > introduce 'reset' method to allow device do serialized assert and
> > deassert operations in a single step, which needs a minimum delay
> > to be waited between assert and deassert.
> 
> Why is Mediatek adding to a TI binding?

TI reset-controller provides a common reset management,
and is suitable for Mediatek SoCs, thus Mediatek wants to reuse this
driver for reset.

> 
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >  Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 5 +
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
> > b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > index 86945502ccb5..ab041032339b 100644
> > --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> > @@ -59,6 +59,11 @@ Required properties:
> >  Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
> >  common reset controller usage by consumers.
> >  
> > +Optional properties:
> > +- reset-duration-us: When do serialized assert and deassert operations, 
> > minimum delay in microseconds
> > +is needed to be waited between an assert and a deassert to reset the 
> > device. This value can be 0, 0 means
> > +that such a delay is not needed.
> 
> This goes in the reset controller node or each consumer? For the latter, 
> it should be a cell in 'resets' if you need this. But really, I think 
> the reset controller should enforce some minimum time that works for all 
> consumers. Surely having a minimum time per reset isn't really needed.
> 
> Rob

'reset-duration-us' will be in the reset controller node, and it's
optional. If minimum delay is needed to be waited between an assert and
a deassert to reset the device, this property will be set.Otherwise no
need to set this property.

Best Regards
Crystal

[v4,1/4] dt-binding: reset-controller: ti: add reset-duration-us property

[Crystal Guo]

introduce 'reset' method to allow device do serialized assert and
deassert operations in a single step, which needs a minimum delay
to be waited between assert and deassert.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 86945502ccb5..ab041032339b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -59,6 +59,11 @@ Required properties:
 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
 common reset controller usage by consumers.
 
+Optional properties:
+- reset-duration-us: When do serialized assert and deassert operations, 
minimum delay in microseconds
+is needed to be waited between an assert and a deassert to reset the device. 
This value can be 0, 0 means
+that such a delay is not needed.
+
 Example:
 
 The following example demonstrates a syscon node, the reset controller node
-- 
2.18.0

[v4,2/4] dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to compatible

[Crystal Guo]

The TI syscon reset controller provides a common reset management,
and is suitable for MTK SoCs. Add compatible 'mediatek,infra-reset',
which denotes to use ti reset-controller driver directly.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index ab041032339b..5a0e9365b51b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,k2l-pscrst"
"ti,k2hk-pscrst"
"ti,syscon-reset"
+   "mediatek,infra-reset", "ti,syscon-reset"
  - #reset-cells: Should be 1. Please see the reset consumer 
node below
  for usage details
  - ti,reset-bits   : Contains the reset control register information
-- 
2.18.0

[v4,0/4] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v4:
fix typos on v3 commit message.

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.


v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct 
value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/

Crystal Guo (4):
  dt-binding: reset-controller: ti: add reset-duration-us property
  dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to
compatible
  reset-controller: ti: introduce a new reset handler
  arm64: dts: mt8192: add infracfg_rst node

 .../bindings/reset/ti-syscon-reset.txt|  6 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 11 +++-
 drivers/reset/reset-ti-syscon.c   | 26 +--
 3 files changed, 40 insertions(+), 3 deletions(-)

[v4,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..08289342f9af 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   unsigned int reset_duration_us;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev 
*rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
value);
 }
 
 /**
@@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
value);
 }
 
 /**
@@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+   int ret;
+
+   ret = ti_syscon_reset_assert(rcdev, id);
+   if (ret)
+   return ret;
+
+   if (data->reset_duration_us)
+   usleep_range(data->reset_duration_us, data->reset_duration_us * 
2);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
+   .reset  = ti_syscon_reset,
.status = ti_syscon_reset_status,
 };
 
@@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
controls[i].flags = be32_to_cpup(list++);
}
 
+   of_property_read_u32(pdev->dev.of_node, "reset-duration-us",
+   >reset_duration_us);
+
data->rcdev.ops = _syscon_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.of_node = np;
-- 
2.18.0

[v4,4/4] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

add infracfg_rst node which is for MT8192 platform

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca17220..a0cb9904706b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "mediatek,mt8192";
@@ -219,9 +220,17 @@
};
 
infracfg: infracfg@10001000 {
-   compatible = "mediatek,mt8192-infracfg", "syscon";
+   compatible = "mediatek,mt8192-infracfg", "syscon", 
"simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+   infracfg_rst: reset-controller {
+   compatible = "mediatek,infra-reset", 
"ti,syscon-reset";
+   #reset-cells = <1>;
+   ti,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | 
DEASSERT_SET | STATUS_NONE) /* 0: pcie */
+   >;
+   };
};
 
pericfg: pericfg@10003000 {
-- 
2.18.0

[v3,1/4] dt-binding: reset-controller: ti: add reset-duration-us property

[Crystal Guo]

introduce 'reset' method to allow device do serialized assert and
deassert operations in a single step, which needs a minimum delay
to be waited between assert and deassert.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 86945502ccb5..ab041032339b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -59,6 +59,11 @@ Required properties:
 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
 common reset controller usage by consumers.
 
+Optional properties:
+- reset-duration-us: When do serialized assert and deassert operations, 
minimum delay in microseconds
+is needed to be waited between an assert and a deassert to reset the device. 
This value can be 0, 0 means
+that such a delay is not needed.
+
 Example:
 
 The following example demonstrates a syscon node, the reset controller node
-- 
2.18.0

[v3,3/4] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..08289342f9af 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   unsigned int reset_duration_us;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev 
*rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
value);
 }
 
 /**
@@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
value);
 }
 
 /**
@@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+   int ret;
+
+   ret = ti_syscon_reset_assert(rcdev, id);
+   if (ret)
+   return ret;
+
+   if (data->reset_duration_us)
+   usleep_range(data->reset_duration_us, data->reset_duration_us * 
2);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
+   .reset  = ti_syscon_reset,
.status = ti_syscon_reset_status,
 };
 
@@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
controls[i].flags = be32_to_cpup(list++);
}
 
+   of_property_read_u32(pdev->dev.of_node, "reset-duration-us",
+   >reset_duration_us);
+
data->rcdev.ops = _syscon_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.of_node = np;
-- 
2.18.0

[v4,4/4] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

add infracfg_rst node which is for MT8192 platform

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca17220..a0cb9904706b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "mediatek,mt8192";
@@ -219,9 +220,17 @@
};
 
infracfg: infracfg@10001000 {
-   compatible = "mediatek,mt8192-infracfg", "syscon";
+   compatible = "mediatek,mt8192-infracfg", "syscon", 
"simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+   infracfg_rst: reset-controller {
+   compatible = "mediatek,infra-reset", 
"ti,syscon-reset";
+   #reset-cells = <1>;
+   ti,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | 
DEASSERT_SET | STATUS_NONE) /* 0: pcie */
+   >;
+   };
};
 
pericfg: pericfg@10003000 {
-- 
2.18.0

[v3,2/4] dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to compatible

[Crystal Guo]

The TI syscon reset controller provides a common reset management,
and is suitable for MTK SoCs. Add compatible 'mediatek,infra-reset',
which denotes to use ti reset-controller driver directly.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index ab041032339b..5a0e9365b51b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,k2l-pscrst"
"ti,k2hk-pscrst"
"ti,syscon-reset"
+   "mediatek,infra-reset", "ti,syscon-reset"
  - #reset-cells: Should be 1. Please see the reset consumer 
node below
  for usage details
  - ti,reset-bits   : Contains the reset control register information
-- 
2.18.0

[v3,0/6] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.

v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct 
value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/

Crystal Guo (4):
  dt-binding: reset-controller: ti: add reset-duration-us property
  dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to
compatible
  reset-controller: ti: introduce a new reset handler
  arm64: dts: mt8192: add infracfg_rst node

 .../bindings/reset/ti-syscon-reset.txt|  6 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 11 +++-
 drivers/reset/reset-ti-syscon.c   | 26 +--
 3 files changed, 40 insertions(+), 3 deletions(-)

Re: [v2,5/6] reset-controller: ti: Introduce force-update method

[Crystal Guo]

On Tue, 2020-08-04 at 15:03 +0800, Philipp Zabel wrote:
> Hi Crystal,
> 
> On Mon, 2020-08-03 at 14:15 +0800, Crystal Guo wrote:
> > Introduce force-update method for assert and deassert interface,
> > which force the write operation in case the read already happens
> > to return the correct value.
> > 
> > Signed-off-by: Crystal Guo 
> 
> Added Suman and Andrew for confirmation: I think writing unconditionally
> can't break any existing user. Just changing to regmap_write_bits()
> instead of adding the update-force property as in v1 should be fine.
> 
> regards
> Philipp
> 
Hi Suman, Andrew,

Can you help to give some suggestions about this change.
Is this can be changed to write unconditionally, or should I add a
update-force property to force the write operation.

Best regards
Crystal.

> > ---
> >  drivers/reset/reset-ti-syscon.c | 15 +--
> >  1 file changed, 13 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/reset/reset-ti-syscon.c 
> > b/drivers/reset/reset-ti-syscon.c
> > index 1c74bcb9a6c3..f4baf78afd14 100644
> > --- a/drivers/reset/reset-ti-syscon.c
> > +++ b/drivers/reset/reset-ti-syscon.c
> > @@ -57,6 +57,7 @@ struct ti_syscon_reset_data {
> > struct ti_syscon_reset_control *controls;
> > unsigned int nr_controls;
> > bool assert_deassert_together;
> > +   bool update_force;
> >  };
> >  
> >  #define to_ti_syscon_reset_data(rcdev) \
> > @@ -90,7 +91,10 @@ static int ti_syscon_reset_assert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->assert_bit);
> > value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
> > value);
> > +   if (data->update_force)
> > +   return regmap_write_bits(data->regmap, control->assert_offset, 
> > mask, value);
> > +   else
> > +   return regmap_update_bits(data->regmap, control->assert_offset, 
> > mask, value);
> >  }
> >  
> >  /**
> > @@ -121,7 +125,10 @@ static int ti_syscon_reset_deassert(struct 
> > reset_controller_dev *rcdev,
> > mask = BIT(control->deassert_bit);
> > value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >  
> > -   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
> > value);
> > +   if (data->update_force)
> > +   return regmap_write_bits(data->regmap, 
> > control->deassert_offset, mask, value);
> > +   else
> > +   return regmap_update_bits(data->regmap, 
> > control->deassert_offset, mask, value);
> >  }
> >  
> >  /**
> > @@ -223,6 +230,10 @@ static int ti_syscon_reset_probe(struct 
> > platform_device *pdev)
> > data->assert_deassert_together = true;
> > else
> > data->assert_deassert_together = false;
> > +   if (of_property_read_bool(np, "update-force"))
> > +   data->update_force = true;
> > +   else
> > +   data->update_force = false;
> >  
> > data->rcdev.ops = _syscon_reset_ops;
> > data->rcdev.owner = THIS_MODULE;
> > -- 
> > 2.18.0

[v4,2/5] arm64: dts: mt8183: update watchdog device node

[Crystal Guo]

The watchdog driver for MT8183 relies on DT data, so the fallback
compatible MT6589 won't work, need to update watchdog device node
to sync with watchdog dt-binding document.

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 1e03c849dc5d..f8d835746ab8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -310,8 +310,7 @@
};
 
watchdog: watchdog@10007000 {
-   compatible = "mediatek,mt8183-wdt",
-"mediatek,mt6589-wdt";
+   compatible = "mediatek,mt8183-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
-- 
2.18.0

[v4,4/5] dt-binding: mt8192: add toprgu reset-controller head file

[Crystal Guo]

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
---
 .../reset-controller/mt8192-resets.h  | 30 +++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h 
b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index ..84fee34f1c32
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang 
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8183_TOPRGU_MM_SW_RST1
+#define MT8183_TOPRGU_MFG_SW_RST   2
+#define MT8183_TOPRGU_VENC_SW_RST  3
+#define MT8183_TOPRGU_VDEC_SW_RST  4
+#define MT8183_TOPRGU_IMG_SW_RST   5
+#define MT8183_TOPRGU_MD_SW_RST7
+#define MT8183_TOPRGU_CONN_SW_RST  9
+#define MT8183_TOPRGU_CONN_MCU_SW_RST  12
+#define MT8183_TOPRGU_IPU0_SW_RST  14
+#define MT8183_TOPRGU_IPU1_SW_RST  15
+#define MT8183_TOPRGU_AUDIO_SW_RST 17
+#define MT8183_TOPRGU_CAMSYS_SW_RST18
+#define MT8192_TOPRGU_MJC_SW_RST   19
+#define MT8192_TOPRGU_C2K_S2_SW_RST20
+#define MT8192_TOPRGU_C2K_SW_RST   21
+#define MT8192_TOPRGU_PERI_SW_RST  22
+#define MT8192_TOPRGU_PERI_AO_SW_RST   23
+
+#define MT8192_TOPRGU_SW_RST_NUM   23
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0

[v4,1/5] dt-binding: mediatek: watchdog: fix the description of compatible

[Crystal Guo]

The watchdog driver for MT2712 and MT8183 relies on DT data, so
the fallback compatible MT6589 won't work.

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd3f1ad..45eedc2c3141 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,13 +4,13 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
-- 
2.18.0

[v4,3/5] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

update mtk-wdt document for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
Reviewed-by: Guenter Roeck 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 45eedc2c3141..e36ba60de829 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+   "mediatek,mt8192-wdt": for MT8192
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
2.18.0

[v4,0/5] watchdog: mt8192: add wdt support

[Crystal Guo]

v4 changes:
revise commit messages.

v3 changes:
https://patchwork.kernel.org/patch/11692731/
https://patchwork.kernel.org/patch/11692767/
https://patchwork.kernel.org/patch/11692729/
https://patchwork.kernel.org/patch/11692771/
https://patchwork.kernel.org/patch/11692733/

Crystal Guo (5):
  dt-binding: mediatek: watchdog: fix the description of compatible
  arm64: dts: mt8183: update watchdog device node
  dt-binding: mediatek: mt8192: update mtk-wdt document
  dt-binding: mt8192: add toprgu reset-controller head file
  watchdog: mt8192: add wdt support

 .../devicetree/bindings/watchdog/mtk-wdt.txt  |  5 ++--
 arch/arm64/boot/dts/mediatek/mt8183.dtsi  |  3 +-
 drivers/watchdog/mtk_wdt.c|  6 
 .../reset-controller/mt8192-resets.h  | 30 +++
 4 files changed, 40 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

[v4,5/5] watchdog: mt8192: add wdt support

[Crystal Guo]

Add support for watchdog device found in MT8192 SoC

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
---
 drivers/watchdog/mtk_wdt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393f609d..aef0c2db6a11 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt8192_data = {
+   .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = _data },
+   { .compatible = "mediatek,mt8192-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
2.18.0

[v2,4/6] reset-controller: ti: introduce a new reset handler

[Crystal Guo]

Add ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Change-Id: I9046992b115a46f3594de57fa89c6a2de9957d49
---
 drivers/reset/reset-ti-syscon.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..1c74bcb9a6c3 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -56,6 +56,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+   bool assert_deassert_together;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -158,10 +159,24 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+
+   if (data->assert_deassert_together) {
+   ti_syscon_reset_assert(rcdev, id);
+   return ti_syscon_reset_deassert(rcdev, id);
+   } else {
+   return -ENOTSUPP;
+   }
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
.status = ti_syscon_reset_status,
+   .reset  = ti_syscon_reset,
 };
 
 static int ti_syscon_reset_probe(struct platform_device *pdev)
@@ -204,6 +219,11 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
controls[i].flags = be32_to_cpup(list++);
}
 
+   if (of_property_read_bool(np, "assert-deassert-together"))
+   data->assert_deassert_together = true;
+   else
+   data->assert_deassert_together = false;
+
data->rcdev.ops = _syscon_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.of_node = np;
-- 
2.18.0

[v2,3/6] dt-binding: reset-controller: ti: add generic-reset to compatible

[Crystal Guo]

The TI syscon reset controller provides a common reset management,
and should be suitable for other SOCs. Add compatible "generic-reset",
which denotes to use a common reset-controller driver.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index d551161ae785..e36d3631eab2 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,k2l-pscrst"
"ti,k2hk-pscrst"
"ti,syscon-reset"
+   "generic-reset", "ti,syscon-reset"
  - #reset-cells: Should be 1. Please see the reset consumer 
node below
  for usage details
  - ti,reset-bits   : Contains the reset control register information
-- 
2.18.0

[v2,5/6] reset-controller: ti: Introduce force-update method

[Crystal Guo]

Introduce force-update method for assert and deassert interface,
which force the write operation in case the read already happens
to return the correct value.

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 1c74bcb9a6c3..f4baf78afd14 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -57,6 +57,7 @@ struct ti_syscon_reset_data {
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
bool assert_deassert_together;
+   bool update_force;
 };
 
 #define to_ti_syscon_reset_data(rcdev) \
@@ -90,7 +91,10 @@ static int ti_syscon_reset_assert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   if (data->update_force)
+   return regmap_write_bits(data->regmap, control->assert_offset, 
mask, value);
+   else
+   return regmap_update_bits(data->regmap, control->assert_offset, 
mask, value);
 }
 
 /**
@@ -121,7 +125,10 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   if (data->update_force)
+   return regmap_write_bits(data->regmap, 
control->deassert_offset, mask, value);
+   else
+   return regmap_update_bits(data->regmap, 
control->deassert_offset, mask, value);
 }
 
 /**
@@ -223,6 +230,10 @@ static int ti_syscon_reset_probe(struct platform_device 
*pdev)
data->assert_deassert_together = true;
else
data->assert_deassert_together = false;
+   if (of_property_read_bool(np, "update-force"))
+   data->update_force = true;
+   else
+   data->update_force = false;
 
data->rcdev.ops = _syscon_reset_ops;
data->rcdev.owner = THIS_MODULE;
-- 
2.18.0

[v2,0/6] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/

Crystal Guo (6):
  dt-binding: reset-controller: ti: add assert-deassert-together
property
  dt-binding: reset-controller: ti: add update-force property
  dt-binding: reset-controller: ti: add generic-reset to compatible
  reset-controller: ti: introduce a new reset handler
  reset-controller: ti: Introduce force-update method
  arm64: dts: mt8192: add infracfg_rst node

 .../bindings/reset/ti-syscon-reset.txt|  5 +++
 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 13 ++-
 drivers/reset/reset-ti-syscon.c   | 35 +--
 3 files changed, 50 insertions(+), 3 deletions(-)

[v2,6/6] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

add infracfg_rst node which is for MT8192 platform

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca17220..c97eff3aa48d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "mediatek,mt8192";
@@ -219,9 +220,19 @@
};
 
infracfg: infracfg@10001000 {
-   compatible = "mediatek,mt8192-infracfg", "syscon";
+   compatible = "mediatek,mt8192-infracfg", "syscon", 
"simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+   infracfg_rst: reset-controller {
+   compatible = "generic-reset", "ti,syscon-reset";
+   #reset-cells = <1>;
+   ti,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | 
DEASSERT_SET | STATUS_NONE) /* 0: pcie */
+   >;
+   assert-deassert-together;
+   update-force;
+   };
};
 
pericfg: pericfg@10003000 {
-- 
2.18.0

[v2,2/6] dt-binding: reset-controller: ti: add update-force property

[Crystal Guo]

add update-force property to force the write operation
in case the read already happens to return the correct value.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 903d1979942f..d551161ae785 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -61,6 +61,7 @@ common reset controller usage by consumers.
 
 Optional properties:
 - assert-deassert-together: Allow device to do serialized assert and deassert 
operations in a single step by 'reset' method.
+- update-force: Force the write operation in case the read already happens to 
return the correct value.
 
 Example:
 
-- 
2.18.0

[v2,1/6] dt-binding: reset-controller: ti: add assert-deassert-together property

[Crystal Guo]

add assert-deassert-together property to allow device to do serialized
assert and deassert operations in a single step by 'reset' method.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 
b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 86945502ccb5..903d1979942f 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -59,6 +59,9 @@ Required properties:
 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
 common reset controller usage by consumers.
 
+Optional properties:
+- assert-deassert-together: Allow device to do serialized assert and deassert 
operations in a single step by 'reset' method.
+
 Example:
 
 The following example demonstrates a syscon node, the reset controller node
-- 
2.18.0

[v3,3/5] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

update mtk-wdt document for MT8192 platform

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 45eedc2..e36ba60 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+   "mediatek,mt8192-wdt": for MT8192
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
1.8.1.1.dirty

add watchdog support for mt8192

[Crystal Guo]

v3 changes:
1.separate fixing compatibles description and adding new board with two patches.
2.update mt8183 DTSI for sync with the binding, while mt2712 DTSI has no 
watchdog node,
thus not update it together.


v2 changes:
https://patchwork.kernel.org/patch/11690729/
https://patchwork.kernel.org/patch/11690731/
https://patchwork.kernel.org/patch/11690719/


v1 changes:
https://patchwork.kernel.org/patch/11680495/
https://patchwork.kernel.org/patch/11680497/

Crystal Guo (5):
  dt-binding: mediatek: watchdog: fix the description of compatible
  arm64: dts: mt8183: update watchdog device node
  dt-binding: mediatek: mt8192: update mtk-wdt document
  dt-binding: mt8192: add toprgu reset-controller head file
  watchdog: mt8192: add wdt support

 .../devicetree/bindings/watchdog/mtk-wdt.txt   |  5 ++--
 arch/arm64/boot/dts/mediatek/mt8183.dtsi   |  3 +--
 drivers/watchdog/mtk_wdt.c |  6 +
 .../dt-bindings/reset-controller/mt8192-resets.h   | 30 ++
 4 files changed, 40 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

[v3,5/5] watchdog: mt8192: add wdt support

[Crystal Guo]

Add support for watchdog device found in MT8192 SoC

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
---
 drivers/watchdog/mtk_wdt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..aef0c2d 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -76,6 +77,10 @@ struct mtk_wdt_data {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt8192_data = {
+   .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
{ .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = _data },
+   { .compatible = "mediatek,mt8192-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
1.8.1.1.dirty

[v3,2/5] arm64: dts: mt8183: update watchdog device node

[Crystal Guo]

update watchdog device node for MT8183

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 1e03c84..f8d8357 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -310,8 +310,7 @@
};
 
watchdog: watchdog@10007000 {
-   compatible = "mediatek,mt8183-wdt",
-"mediatek,mt6589-wdt";
+   compatible = "mediatek,mt8183-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
-- 
1.8.1.1.dirty

[v3,4/5] dt-binding: mt8192: add toprgu reset-controller head file

[Crystal Guo]

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo 
Reviewed-by: Matthias Brugger 
---
 .../dt-bindings/reset-controller/mt8192-resets.h   | 30 ++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h 
b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index 000..84fee34
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang 
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8183_TOPRGU_MM_SW_RST1
+#define MT8183_TOPRGU_MFG_SW_RST   2
+#define MT8183_TOPRGU_VENC_SW_RST  3
+#define MT8183_TOPRGU_VDEC_SW_RST  4
+#define MT8183_TOPRGU_IMG_SW_RST   5
+#define MT8183_TOPRGU_MD_SW_RST7
+#define MT8183_TOPRGU_CONN_SW_RST  9
+#define MT8183_TOPRGU_CONN_MCU_SW_RST  12
+#define MT8183_TOPRGU_IPU0_SW_RST  14
+#define MT8183_TOPRGU_IPU1_SW_RST  15
+#define MT8183_TOPRGU_AUDIO_SW_RST 17
+#define MT8183_TOPRGU_CAMSYS_SW_RST18
+#define MT8192_TOPRGU_MJC_SW_RST   19
+#define MT8192_TOPRGU_C2K_S2_SW_RST20
+#define MT8192_TOPRGU_C2K_SW_RST   21
+#define MT8192_TOPRGU_PERI_SW_RST  22
+#define MT8192_TOPRGU_PERI_AO_SW_RST   23
+
+#define MT8192_TOPRGU_SW_RST_NUM   23
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
1.8.1.1.dirty

[v3,1/5] dt-binding: mediatek: watchdog: fix the description of compatible

[Crystal Guo]

Besides watchdog, mt2712 and nt8183 also provide sub-system software
reset features. But mt6589 not support this feature

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd..45eedc2 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,13 +4,13 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
-- 
1.8.1.1.dirty

Re: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface

[Crystal Guo]

On Wed, 2020-07-29 at 16:02 +0800, Philipp Zabel wrote:
> Hi Crystal, Matthias,
> 
> On Wed, 2020-07-29 at 09:48 +0200, Matthias Brugger wrote:
> > 
> > On 29/07/2020 09:39, Crystal Guo wrote:
> > > Add ti_syscon_reset() to integrate assert and deassert together,
> > > and change return value of the reset assert and deassert interface
> > > from regmap_update_bits to regmap_write_bits.
> > > 
> > > when clear bit is already 1, regmap_update_bits can not write 1 to it 
> > > again.
> > > Some IC has the feature that, when set bit is 1, the clear bit change
> > > to 1 together. It will truly clear bit to 0 by write 1 to the clear bit
> > > 
> > > Signed-off-by: Crystal Guo 
> > > ---
> > >   drivers/reset/reset-ti-syscon.c | 13 +++--
> > >   1 file changed, 11 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/reset/reset-ti-syscon.c 
> > > b/drivers/reset/reset-ti-syscon.c
> > > index a2635c2..5a8ec8f 100644
> > > --- a/drivers/reset/reset-ti-syscon.c
> > > +++ b/drivers/reset/reset-ti-syscon.c
> > > @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct 
> > > reset_controller_dev *rcdev,
> > >   mask = BIT(control->assert_bit);
> > >   value = (control->flags & ASSERT_SET) ? mask : 0x0;
> > >   
> > > - return regmap_update_bits(data->regmap, control->assert_offset, mask, 
> > > value);
> > > + return regmap_write_bits(data->regmap, control->assert_offset, mask, 
> > > value);
> > 
> > Nack, this will break the driver for the other devices.
> 
> I don't think this will break the driver for existing hardware.
> regmap_write_bits() is the same as regmap_update_bits(), it just forces
> the write in case the read already happens to return the correct value.
> Of course it would be good to check that this actually works.

Yes, regmap_write_bits() is the same as regmap_update_bits(), it would
not affect existed users. Or should I use a property to separate
regmap_write_bits() and regmap_update_bits() ?

> 
> > The kernel has to work not just for your SoC but for all devices of all 
> > architectures. You can't just hack something up, that will work on your 
> > specific 
> > SoC.
> > 
> > Regards,
> > Matthias 
> > 

This TI driver was intend to be a generic reset controller
(https://lore.kernel.org/patchwork/cover/683585/), so this patch may
not just work on a specific SoC.

Thanks,
Crystal

> > >   }
> > >   
> > >   /**
> > > @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct 
> > > reset_controller_dev *rcdev,
> > >   mask = BIT(control->deassert_bit);
> > >   value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> > >   
> > > - return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
> > > value);
> > > + return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
> > > value);
> > >   }
> > >   
> > >   /**
> > > @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct 
> > > reset_controller_dev *rcdev,
> > >   !(control->flags & STATUS_SET);
> > >   }
> > >   
> > > +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> > > +unsigned long id)
> > > +{
> > > + ti_syscon_reset_assert(rcdev, id);
> > > +
> > > + return ti_syscon_reset_deassert(rcdev, id);
> > > +}
> > > +
> 
> I'm unsure about this one, though. This is an incompatible change. At
> the very least this would have to be optional depending on compatible.
> 
> regards
> Philipp

I will add a property to make this change be optional, thanks for you
advice.

Thanks,
Crystal

Re: [v2,1/3] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

On Wed, 2020-07-29 at 18:18 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 12:02, Crystal Guo wrote:
> > update mtk-wdt document for MT8192 platform
> 
> 
> should be two patches. one fixing the compatibles and second adding new board.
> 
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >   Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
> >   1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> > b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > index 4dd36bd..e36ba60 100644
> > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > @@ -4,14 +4,15 @@ Required properties:
> >   
> >   - compatible should contain:
> > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
> > -   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
> > +   "mediatek,mt2712-wdt": for MT2712
> > "mediatek,mt6589-wdt": for MT6589
> > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
> > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
> > "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
> > "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> > -   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
> > +   "mediatek,mt8183-wdt": for MT8183
> 
> We will need to update the DTSI in a seperate patch as well.

Yes, this patch is based on
https://patchwork.kernel.org/patch/11690401/ , which modify description
for mt2712 and mt8183.

> 
> > "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> > +   "mediatek,mt8192-wdt": for MT8192
> >   
> >   - reg : Specifies base physical address and size of the registers.
> >   
> > 

[v2,1/3] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

update mtk-wdt document for MT8192 platform

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd..e36ba60 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,14 +4,15 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+   "mediatek,mt8192-wdt": for MT8192
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
1.8.1.1.dirty

[v2,3/3] watchdog: mt8192: add wdt support

[Crystal Guo]

add driver setting to support mt8192 wdt

Signed-off-by: Crystal Guo 
---
 drivers/watchdog/mtk_wdt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..aef0c2d 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -76,6 +77,10 @@ struct mtk_wdt_data {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt8192_data = {
+   .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
{ .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = _data },
+   { .compatible = "mediatek,mt8192-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
1.8.1.1.dirty

[v2,0/3] add watchdog support for mt8192

[Crystal Guo]

v1 changes:
https://patchwork.kernel.org/patch/11680495/
https://patchwork.kernel.org/patch/11680497/

Crystal Guo (3):
  dt-binding: mediatek: mt8192: update mtk-wdt document
  dt-binding: mt8192: add toprgu reset-controller head file
  watchdog: mt8192: add wdt support

 .../devicetree/bindings/watchdog/mtk-wdt.txt   |  5 ++--
 drivers/watchdog/mtk_wdt.c |  6 +
 .../dt-bindings/reset-controller/mt8192-resets.h   | 30 ++
 3 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

[v2,2/3] dt-binding: mt8192: add toprgu reset-controller head file

[Crystal Guo]

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo 
---
 .../dt-bindings/reset-controller/mt8192-resets.h   | 30 ++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h 
b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index 000..be9a7ca
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang 
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8192_TOPRGU_MM_SW_RST1
+#define MT8192_TOPRGU_MFG_SW_RST   2
+#define MT8192_TOPRGU_VENC_SW_RST  3
+#define MT8192_TOPRGU_VDEC_SW_RST  4
+#define MT8192_TOPRGU_IMG_SW_RST   5
+#define MT8192_TOPRGU_MD_SW_RST7
+#define MT8192_TOPRGU_CONN_SW_RST  9
+#define MT8192_TOPRGU_CONN_MCU_SW_RST  12
+#define MT8192_TOPRGU_IPU0_SW_RST  14
+#define MT8192_TOPRGU_IPU1_SW_RST  15
+#define MT8192_TOPRGU_AUDIO_SW_RST 17
+#define MT8192_TOPRGU_CAMSYS_SW_RST18
+#define MT8192_TOPRGU_MJC_SW_RST   19
+#define MT8192_TOPRGU_C2K_S2_SW_RST20
+#define MT8192_TOPRGU_C2K_SW_RST   21
+#define MT8192_TOPRGU_PERI_SW_RST  22
+#define MT8192_TOPRGU_PERI_AO_SW_RST   23
+
+#define MT8192_TOPRGU_SW_RST_NUM   23
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
1.8.1.1.dirty

Re: [v2,2/3] dt-bindings: watchdog: add a new head file for toprgu reset-controllers

[Crystal Guo]

On Wed, 2020-07-29 at 16:15 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 10:11, Crystal Guo wrote:
> > On Wed, 2020-07-29 at 15:42 +0800, Matthias Brugger wrote:
> >> Hi Crystal,
> >>
> >> On 29/07/2020 08:30, Crystal Guo wrote:
> >>> merge all the reset numbers in one head file.
> >>>
> >>> Signed-off-by: Crystal Guo 
> >>> ---
> >>>include/dt-bindings/reset-controller/mtk-resets.h | 13 +
> >>>1 file changed, 13 insertions(+)
> >>>create mode 100644 include/dt-bindings/reset-controller/mtk-resets.h
> >>>
> >>> diff --git a/include/dt-bindings/reset-controller/mtk-resets.h 
> >>> b/include/dt-bindings/reset-controller/mtk-resets.h
> >>> new file mode 100644
> >>> index 000..d73a4ba
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/reset-controller/mtk-resets.h
> >>> @@ -0,0 +1,13 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +/*
> >>> + * Copyright (C) 2020 Mediatek Inc.
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MTK
> >>> +#define _DT_BINDINGS_RESET_CONTROLLER_MTK
> >>> +
> >>> +#define MT2712_TOPRGU_SW_RST_NUM 11
> >>> +#define MT8183_TOPRGU_SW_RST_NUM19
> >>
> >> Maybe I didn't explain myself properly. We want to have all resets in one 
> >> file
> >> and do not want to have the resets for the watchdog in a different file. 
> >> That
> >> means I don't thin your patch is correct and the effort should be 
> >> abandoned.
> >>
> >> Regards,
> >> Matthias
> > 
> > Do you mean to keep the current way unchanged? For example, with a new
> > SOC 8192, should add a new head file mt8192_resets.h for the resets
> > numbers.
> > 
> 
> Exactly.
> 
> Regards,
> Matthias

OK, but the dt-binding mtk-wdt.txt still need to update, please help me
to review, many thanks~

Re: [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 09:39, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +-
> >   1 file changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index b16dbbd..adc6239 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -217,9 +217,17 @@
> > };
> >   
> > infracfg: infracfg@10001000 {
> > -   compatible = "mediatek,mt8192-infracfg", "syscon";
> > +   compatible = "mediatek,mt8192-infracfg", "syscon", 
> > "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > +   infracfg_rst: reset-controller {
> > +   compatible = "ti,syscon-reset";
> > +   #reset-cells = <1>;
> > +   ti,reset-bits = <
> > +   0x140 15 0x144 15 0 0 (ASSERT_SET | 
> > DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> 
> You have Texas Instruments hardware inside infracfg? Are you sure?
> 
TI reset-controller driver is a common driver, MTK SOC has the similar
control flow, thus can reuse it.

> > +   >;
> > +   };
> > };
> >   
> > pericfg: pericfg@10003000 {
> > 

Re: [v2,2/3] dt-bindings: watchdog: add a new head file for toprgu reset-controllers

[Crystal Guo]

On Wed, 2020-07-29 at 15:42 +0800, Matthias Brugger wrote:
> Hi Crystal,
> 
> On 29/07/2020 08:30, Crystal Guo wrote:
> > merge all the reset numbers in one head file.
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >   include/dt-bindings/reset-controller/mtk-resets.h | 13 +
> >   1 file changed, 13 insertions(+)
> >   create mode 100644 include/dt-bindings/reset-controller/mtk-resets.h
> > 
> > diff --git a/include/dt-bindings/reset-controller/mtk-resets.h 
> > b/include/dt-bindings/reset-controller/mtk-resets.h
> > new file mode 100644
> > index 000..d73a4ba
> > --- /dev/null
> > +++ b/include/dt-bindings/reset-controller/mtk-resets.h
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2020 Mediatek Inc.
> > + *
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MTK
> > +#define _DT_BINDINGS_RESET_CONTROLLER_MTK
> > +
> > +#define MT2712_TOPRGU_SW_RST_NUM   11
> > +#define MT8183_TOPRGU_SW_RST_NUM19
> 
> Maybe I didn't explain myself properly. We want to have all resets in one 
> file 
> and do not want to have the resets for the watchdog in a different file. That 
> means I don't thin your patch is correct and the effort should be abandoned.
> 
> Regards,
> Matthias

Do you mean to keep the current way unchanged? For example, with a new
SOC 8192, should add a new head file mt8192_resets.h for the resets
numbers.

[PATCH 0/2] adjust the reset assert and deassert interface

[Crystal Guo]

1. adjust the reset assert and deassert interface
to make it more compatible.
2. add infracfg_rst device node.

Crystal Guo (2):
  reset-controller: ti: adjust the reset assert and deassert interface
  arm64: dts: mt8192: add infracfg_rst node

 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +-
 drivers/reset/reset-ti-syscon.c  | 13 +++--
 2 files changed, 20 insertions(+), 3 deletions(-)

[PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface

[Crystal Guo]

Add ti_syscon_reset() to integrate assert and deassert together,
and change return value of the reset assert and deassert interface
from regmap_update_bits to regmap_write_bits.

when clear bit is already 1, regmap_update_bits can not write 1 to it again.
Some IC has the feature that, when set bit is 1, the clear bit change
to 1 together. It will truly clear bit to 0 by write 1 to the clear bit

Signed-off-by: Crystal Guo 
---
 drivers/reset/reset-ti-syscon.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c2..5a8ec8f 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev 
*rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->assert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->assert_offset, mask, 
value);
 }
 
 /**
@@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct 
reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-   return regmap_update_bits(data->regmap, control->deassert_offset, mask, 
value);
+   return regmap_write_bits(data->regmap, control->deassert_offset, mask, 
value);
 }
 
 /**
@@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct 
reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+  unsigned long id)
+{
+   ti_syscon_reset_assert(rcdev, id);
+
+   return ti_syscon_reset_deassert(rcdev, id);
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert   = ti_syscon_reset_deassert,
.status = ti_syscon_reset_status,
+   .reset  = ti_syscon_reset,
 };
 
 static int ti_syscon_reset_probe(struct platform_device *pdev)
-- 
1.8.1.1.dirty

[PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node

[Crystal Guo]

add infracfg_rst node which is for MT8192 platform

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index b16dbbd..adc6239 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -217,9 +217,17 @@
};
 
infracfg: infracfg@10001000 {
-   compatible = "mediatek,mt8192-infracfg", "syscon";
+   compatible = "mediatek,mt8192-infracfg", "syscon", 
"simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+   infracfg_rst: reset-controller {
+   compatible = "ti,syscon-reset";
+   #reset-cells = <1>;
+   ti,reset-bits = <
+   0x140 15 0x144 15 0 0 (ASSERT_SET | 
DEASSERT_SET | STATUS_NONE) /* 0: pcie */
+   >;
+   };
};
 
pericfg: pericfg@10003000 {
-- 
1.8.1.1.dirty

[v2,2/3] dt-bindings: watchdog: add a new head file for toprgu reset-controllers

[Crystal Guo]

merge all the reset numbers in one head file.

Signed-off-by: Crystal Guo 
---
 include/dt-bindings/reset-controller/mtk-resets.h | 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mtk-resets.h

diff --git a/include/dt-bindings/reset-controller/mtk-resets.h 
b/include/dt-bindings/reset-controller/mtk-resets.h
new file mode 100644
index 000..d73a4ba
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mtk-resets.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Mediatek Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MTK
+#define _DT_BINDINGS_RESET_CONTROLLER_MTK
+
+#define MT2712_TOPRGU_SW_RST_NUM   11
+#define MT8183_TOPRGU_SW_RST_NUM19
+
+#endif
-- 
1.8.1.1.dirty

[v2,1/3] dt-bindings: watchdog: modify description for mt2712 and mt8183

[Crystal Guo]

Besides watchdog, mt2712 and mt8183 also provide sub-system software
reset features. But mt6589 not support this feature.

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd..45eedc2 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,13 +4,13 @@ Required properties:
 
 - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
-   "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+   "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
-   "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+   "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
-- 
1.8.1.1.dirty

[v3,3/3] watchdog: mtk_wdt: merge all the reset numbers in one head file

[Crystal Guo]

mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM.
Instead of resubmit a new mt8xxx-reset.h for a new IC, merge all
the reset numbers in one head file.

Signed-off-by: Crystal Guo 
---
 drivers/watchdog/mtk_wdt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..5000a49 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -9,8 +9,7 @@
  * Based on sunxi_wdt.c
  */
 
-#include 
-#include 
+#include 
 #include 
 #include 
 #include 
-- 
1.8.1.1.dirty

[v2,0/3] mtk_wdt: merge all the reset numbers in one head file

[Crystal Guo]

This series patches merge all the reset numbers in one head file

v2 changes:
merge all the reset numbers in one head file,
instead of pass the reset number via DTS (v1). 

v1 changes:
https://patchwork.kernel.org/patch/11688915/
https://patchwork.kernel.org/patch/11688925/
https://patchwork.kernel.org/patch/11688923/

Crystal Guo (3):
  dt-bindings: watchdog: modify description for mt2712 and mt8183
  dt-bindings: watchdog: add a new head file for toprgu reset-controllers
  watchdog: mtk_wdt: merge all the reset numbers in one head file

  Documentation/devicetree/bindings/watchdog/mtk-wdt.txt |  4 ++--
  drivers/watchdog/mtk_wdt.c |  3 +--
  include/dt-bindings/reset-controller/mtk-resets.h  | 13 +
  3 files changed, 16 insertions(+), 4 deletions(-)
  create mode 100644 include/dt-bindings/reset-controller/mtk-resets.h

[PATCH 1/3] watchdog: mtk_wdt: remove mt8xxx-resets.h

[Crystal Guo]

mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM.
Instead of resubmit the mt8xxx-reset.h for a new IC, get the number
of reset bits from dtsi is more easier to maintain.

Signed-off-by: Crystal Guo 
---
 drivers/watchdog/mtk_wdt.c | 26 +-
 1 file changed, 5 insertions(+), 21 deletions(-)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..adc88c2 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -9,8 +9,6 @@
  * Based on sunxi_wdt.c
  */
 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -64,18 +62,6 @@ struct mtk_wdt_dev {
struct reset_controller_dev rcdev;
 };
 
-struct mtk_wdt_data {
-   int toprgu_sw_rst_num;
-};
-
-static const struct mtk_wdt_data mt2712_data = {
-   .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
-};
-
-static const struct mtk_wdt_data mt8183_data = {
-   .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
-};
-
 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
   unsigned long id, bool assert)
 {
@@ -248,7 +234,7 @@ static int mtk_wdt_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
struct mtk_wdt_dev *mtk_wdt;
-   const struct mtk_wdt_data *wdt_data;
+   u32 toprgu_sw_rst_num;
int err;
 
mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
@@ -284,10 +270,10 @@ static int mtk_wdt_probe(struct platform_device *pdev)
dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
 mtk_wdt->wdt_dev.timeout, nowayout);
 
-   wdt_data = of_device_get_match_data(dev);
-   if (wdt_data) {
-   err = toprgu_register_reset_controller(pdev,
-  
wdt_data->toprgu_sw_rst_num);
+   err = of_property_read_u32(pdev->dev.of_node, "rst-num",
+   _sw_rst_num);
+   if (!err) {
+   err = toprgu_register_reset_controller(pdev, toprgu_sw_rst_num);
if (err)
return err;
}
@@ -319,9 +305,7 @@ static int mtk_wdt_resume(struct device *dev)
 #endif
 
 static const struct of_device_id mtk_wdt_dt_ids[] = {
-   { .compatible = "mediatek,mt2712-wdt", .data = _data },
{ .compatible = "mediatek,mt6589-wdt" },
-   { .compatible = "mediatek,mt8183-wdt", .data = _data },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
-- 
1.8.1.1.dirty

[PATCH 2/3] dt-bindings: watchdog: Add rst-num property

[Crystal Guo]

Add rst-num property and update example

Signed-off-by: Crystal Guo 
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd..df19a4d 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -18,6 +18,7 @@ Required properties:
 Optional properties:
 - timeout-sec: contains the watchdog timeout in seconds.
 - #reset-cells: Should be 1.
+- rst-num: the number of reset bits in toprgu.
 
 Example:
 
@@ -26,5 +27,6 @@ watchdog: watchdog@10007000 {
 "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
timeout-sec = <10>;
+   rst-num = <23>;
#reset-cells = <1>;
 };
-- 
1.8.1.1.dirty

[PATCH 3/3] arm64: dts: mt8183: Add rst-num property

[Crystal Guo]

Add rst-num property in watchdog node

Signed-off-by: Crystal Guo 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7b781eb..decf156 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -332,6 +332,7 @@
compatible = "mediatek,mt8183-wdt",
 "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
+   rst-num = <19>;
#reset-cells = <1>;
};
 
-- 
1.8.1.1.dirty

Re: [PATCH 3/4] watchdog: mt8192: add wdt support

[Crystal Guo]

On Fri, 2020-07-24 at 06:00 +0800, Matthias Brugger wrote:
> 
> On 23/07/2020 11:07, Seiya Wang wrote:
> > From: Crystal Guo 
> > 
> > add driver setting to support mt8192 wdt
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >   drivers/watchdog/mtk_wdt.c | 5 +
> >   1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> > index d6a6393f609d..ad23596170af 100644
> > --- a/drivers/watchdog/mtk_wdt.c
> > +++ b/drivers/watchdog/mtk_wdt.c
> > @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = {
> > .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> >   };
> >   
> > +static const struct mtk_wdt_data mt8192_data = {
> > +   .toprgu_sw_rst_num = 23,
> 
> Should be defined in include/dt-bindings/reset-controller/mt8192-resets.h

mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM, may be
it's more easier to maintain by define it at OF data directly, instead
of resubmit the mt8xxx-reset.h and add
"include/dt-bindings/reset-controller/mt8xxx-resets.h" at mtk_wdt.c.

Regards
Crystal Guo

> 
> > +};
> > +
> >   static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> >unsigned long id, bool assert)
> >   {
> > @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
> > { .compatible = "mediatek,mt2712-wdt", .data = _data },
> > { .compatible = "mediatek,mt6589-wdt" },
> > { .compatible = "mediatek,mt8183-wdt", .data = _data },
> > +   { .compatible = "mediatek,mt8192-wdt", .data = _data },
> > { /* sentinel */ }
> >   };
> >   MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
> > 

Re: [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document

[Crystal Guo]

On Fri, 2020-07-24 at 06:02 +0800, Matthias Brugger wrote:
> 
> On 23/07/2020 23:29, Rob Herring wrote:
> > On Thu, Jul 23, 2020 at 05:07:31PM +0800, Seiya Wang wrote:
> >> From: Crystal Guo 
> >>
> >> update mtk-wdt document for MT8192 platform
> >>
> >> Signed-off-by: Crystal Guo 
> >> ---
> >>   Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> >> b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> index 4dd36bd3f1ad..d760ca8a630e 100644
> >> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> @@ -12,6 +12,8 @@ Required properties:
> >>"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> >>"mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
> >>"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> >> +  "mediatek,mt8192-wdt": for MT8192
> >> +
> > 
> > So, not compatible with "mediatek,mt6589-wdt"? Is so, perhaps summarize
> > what the differences are.
> > 
> 
> Hm, looks to me as if the binding description for mt2712 and mt8183 isn't 
> correct, as we have a OF data just as we have for mt8192 now. Could you fix 
> this 
> in a separate patch?
> 
> Regards,
> Matthias
> 
> Besides watchdog, mt8192 toprgu module also provide sub-system software reset 
> features.
> mt2712 and mt8183 are same as mt8192. But mt6589 not support sub-system 
> software reset.
> 
> >>   
> >>   - reg : Specifies base physical address and size of the registers.
> >>   
> >> -- 
> >> 2.14.1