RE: [PATCH v3] clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
Hi Anson,
Please see my below comments.
Best regards,
Fancy Fang
-Original Message-
From: Anson Huang
Sent: Tuesday, October 15, 2019 11:28 AM
To: Fancy Fang ; sb...@kernel.org; shawn...@kernel.org
Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
linux-kernel@vger.kernel.org; mturque...@baylibre.com; s.ha...@pengutronix.de;
ker...@pengutronix.de; dl-linux-imx
Subject: RE: [PATCH v3] clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL
clock
Hi, Fancy
> Subject: [PATCH v3] clk: imx7ulp: do not export out
> IMX7ULP_CLK_MIPI_PLL clock
>
> The mipi pll clock comes from the MIPI PHY PLL output, so it should
> not be a fixed clock.
>
> MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock
> for transferring the pixel data out and its output clock is configured
> according to the display mode.
>
> So it should be used only for MIPI DSI and not be exported out for
> other usages.
>
> Signed-off-by: Fancy Fang
> ---
> ChangeLog v2->v3:
> * Keep 'IMX7ULP_CLK_MIPI_PLL' macro definition.
>
> ChangeLog v1->v2:
> * Keep other clock indexes unchanged as Shawn suggested.
>
> Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
> drivers/clk/imx/clk-imx7ulp.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> index a4f8cd478f92..93d89adb7afe 100644
> --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> @@ -82,7 +82,6 @@ pcc2: pcc2@403f {
><&scg1 IMX7ULP_CLK_APLL_PFD0>,
><&scg1 IMX7ULP_CLK_UPLL>,
><&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
> - <&scg1 IMX7ULP_CLK_MIPI_PLL>,
><&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
><&scg1 IMX7ULP_CLK_ROSC>,
><&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
> diff --git a/drivers/clk/imx/clk-imx7ulp.c
> b/drivers/clk/imx/clk-imx7ulp.c index 2022d9bead91..459b120b71d5
> 100644
> --- a/drivers/clk/imx/clk-imx7ulp.c
> +++ b/drivers/clk/imx/clk-imx7ulp.c
> @@ -28,7 +28,7 @@ static const char * const scs_sels[]=
> { "dummy", "sosc", "sirc", "firc", "dumm
> static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
> static const char * const nic_sels[] = { "firc", "ddr_clk", };
> static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
> "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
> -static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk",
> "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk",
> "spll_bus_clk", };
> +static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk",
> "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk",
> "spll_bus_clk", };
The reference manual does have mpll as clock option, so do you mean it will NOT
be supported anymore, is mpll used inside MIPI PHY?
[FF] Yes. The mpll comes from the MIPI PHY PLL which is an internal PLL clock
in MIPI space. And besides, this clock frequency can be changed or disabled
dynamically when you change display mode or disable display. So it should not
be used as other peripherals's root clock. This is why I want to hide this mpll
from other peripherals to make things easier to be handled.
Anson
> static const char * const arm_sels[] = { "divcore", "dummy",
> "dummy", "hsrun_divcore", };
>
> /* used by sosc/sirc/firc/ddr/spll/apll dividers */ @@ -75,7 +75,6 @@
> static void __init imx7ulp_clk_scg1_init(struct device_node *np)
> clks[IMX7ULP_CLK_SOSC] =
> imx_obtain_fixed_clk_hw(np, "sosc");
> clks[IMX7ULP_CLK_SIRC] =
> imx_obtain_fixed_clk_hw(np, "sirc");
> clks[IMX7ULP_CLK_FIRC] =
> imx_obtain_fixed_clk_hw(np, "firc");
> - clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np,
> "mpll");
> clks[IMX7ULP_CLK_UPLL] =
> imx_obtain_fixed_clk_hw(np, "upll");
>
> /* SCG1 */
> --
> 2.17.1
[PATCH v3] clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang
---
ChangeLog v2->v3:
* Keep 'IMX7ULP_CLK_MIPI_PLL' macro definition.
ChangeLog v1->v2:
* Keep other clock indexes unchanged as Shawn suggested.
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
drivers/clk/imx/clk-imx7ulp.c | 3 +--
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f92..93d89adb7afe 100644
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f {
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 2022d9bead91..459b120b71d5 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy",
"sosc", "sirc", "firc", "dumm
static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
static const char * const arm_sels[] = { "divcore", "dummy",
"dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node
*np)
clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
- clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
/* SCG1 */
--
2.17.1
[PATCH v2] clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang
---
ChangeLog v1->v2:
* Keep other clock indexes unchanged as Shawn suggested.
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
drivers/clk/imx/clk-imx7ulp.c | 3 +--
include/dt-bindings/clock/imx7ulp-clock.h | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f92..93d89adb7afe 100644
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f {
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 995a4ad10904..936c39f767df 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy",
"sosc", "sirc", "firc", "dumm
static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
static const char * const arm_sels[] = { "divcore", "dummy",
"dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node
*np)
clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
- clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
/* SCG1 */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h
b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c81..a39b0c40cb41 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,7 +49,6 @@
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
-#define IMX7ULP_CLK_MIPI_PLL 39
#define IMX7ULP_CLK_SIRC 40
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
--
2.17.1
[PATCH v2] clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang
---
ChangeLog v1->v2:
* Keep other clock indexes unchanged as Shawn suggested.
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
drivers/clk/imx/clk-imx7ulp.c | 3 +--
include/dt-bindings/clock/imx7ulp-clock.h | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f92..93d89adb7afe 100644
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f {
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 995a4ad10904..936c39f767df 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy",
"sosc", "sirc", "firc", "dumm
static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
static const char * const arm_sels[] = { "divcore", "dummy",
"dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node
*np)
clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
- clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
/* SCG1 */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h
b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c81..a39b0c40cb41 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,7 +49,6 @@
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
-#define IMX7ULP_CLK_MIPI_PLL 39
#define IMX7ULP_CLK_SIRC 40
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
--
2.17.1
[PATCH 2/2] clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang
---
.../devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
drivers/clk/imx/clk-imx7ulp.c | 3 +--
include/dt-bindings/clock/imx7ulp-clock.h | 15 +++
3 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f92..93d89adb7afe 100644
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f {
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 2022d9bead91..459b120b71d5 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy",
"sosc", "sirc", "firc", "dumm
static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
static const char * const arm_sels[] = { "divcore", "dummy",
"dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node
*np)
clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
- clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
/* SCG1 */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h
b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c81..f8d34fb4378f 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,15 +49,14 @@
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
-#define IMX7ULP_CLK_MIPI_PLL 39
-#define IMX7ULP_CLK_SIRC 40
-#define IMX7ULP_CLK_SOSC_BUS_CLK 41
-#define IMX7ULP_CLK_FIRC_BUS_CLK 42
-#define IMX7ULP_CLK_SPLL_BUS_CLK 43
-#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
-#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
+#define IMX7ULP_CLK_SIRC 39
+#define IMX7ULP_CLK_SOSC_BUS_CLK 40
+#define IMX7ULP_CLK_FIRC_BUS_CLK 41
+#define IMX7ULP_CLK_SPLL_BUS_CLK 42
+#define IMX7ULP_CLK_HSRUN_SYS_SEL 43
+#define IMX7ULP_CLK_HSRUN_CORE_DIV 44
-#define IMX7ULP_CLK_SCG1_END 46
+#define IMX7ULP_CLK_SCG1_END 45
/* PCC2 */
#define IMX7ULP_CLK_DMA1 0
--
2.17.1
[PATCH 1/2] ARM: dts: imx7ulp: remove mipi pll clock node
According to the IMX7ULP reference manual, the mipi pll
clock comes from the MIPI PHY PLL output. So it should
not be defined as a fixed clock. So remove this clock
node and all the references to it.
Signed-off-by: Fancy Fang
---
arch/arm/boot/dts/imx7ulp.dtsi | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 6859a3a83750..a7e4004bf428 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -87,13 +87,6 @@
#clock-cells = <0>;
};
- mpll: clock-mpll {
- compatible = "fixed-clock";
- clock-frequency = <48000>;
- clock-output-names = "mpll";
- #clock-cells = <0>;
- };
-
ahbbridge0: bus@4000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -258,9 +251,9 @@
compatible = "fsl,imx7ulp-scg1";
reg = <0x403e 0x1>;
clocks = <&rosc>, <&sosc>, <&sirc>,
-<&firc>, <&upll>, <&mpll>;
+<&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
- "firc", "upll", "mpll";
+ "firc", "upll";
#clock-cells = <1>;
};
@@ -276,13 +269,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
assigned-clock-parents = <&scg1
IMX7ULP_CLK_SOSC_BUS_CLK>;
@@ -309,13 +301,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
};
--
2.17.1
[RESEND PATCH 2/2] clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'
Rename 'share_count_dcss' to 'share_count_disp', since the
DCSS module does not exist on imx8mm platform. So rename it
to avoid any unnecessary confusion.
Signed-off-by: Fancy Fang
---
drivers/clk/imx/clk-imx8mm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 42f1227a4952..42cb33edf8e5 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -22,7 +22,7 @@ static u32 share_count_sai3;
static u32 share_count_sai4;
static u32 share_count_sai5;
static u32 share_count_sai6;
-static u32 share_count_dcss;
+static u32 share_count_disp;
static u32 share_count_pdm;
static u32 share_count_nand;
@@ -644,10 +644,10 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk",
"vpu_g2", base + 0x45a0, 0);
clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk",
"pdm", base + 0x45b0, 0, &share_count_pdm);
clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk",
"ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
- clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk",
"disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
- clks[IMX8MM_CLK_DISP_AXI_ROOT] =
imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0,
&share_count_dcss);
- clks[IMX8MM_CLK_DISP_APB_ROOT] =
imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0,
&share_count_dcss);
- clks[IMX8MM_CLK_DISP_RTRM_ROOT] =
imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0,
&share_count_dcss);
+ clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk",
"disp_dc8000", base + 0x45d0, 0, &share_count_disp);
+ clks[IMX8MM_CLK_DISP_AXI_ROOT] =
imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0,
&share_count_disp);
+ clks[IMX8MM_CLK_DISP_APB_ROOT] =
imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0,
&share_count_disp);
+ clks[IMX8MM_CLK_DISP_RTRM_ROOT] =
imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0,
&share_count_disp);
clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk",
"usdhc3", base + 0x45e0, 0);
clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root",
base + 0x4620, 0);
clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk",
"vpu_bus", base + 0x4630, 0);
--
2.17.1
[RESEND PATCH 1/2] clk: imx8mm: rename lcdif pixel clock
Rename 'lcdif' pixel clock related names to 'disp' names, since:
First, the lcdif pixel clock is not supplied to LCDIF controller
directly, but to some LPCG clock in display mix. So rename it to
'disp' pixel clock is more accurate.
Second, in the imx8mn CCM specification which is designed after
imx8mm, this same pixel root clock name has been modified from
'LCDIF_PIXEL_CLK_ROOT' to 'DISPLAY_PIXEL_CLK_ROOT'.
Signed-off-by: Fancy Fang
---
drivers/clk/imx/clk-imx8mm.c | 4 ++--
include/dt-bindings/clock/imx8mm-clock.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75df994d..42f1227a4952 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -210,7 +210,7 @@ static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m",
"sys_pll2_200m", "sys_p
static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_disp_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out",
"audio_pll2_out", "video_pll1_out",
@@ -535,7 +535,7 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy",
imx8mm_pcie1_phy_sels, base + 0xa380);
clks[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux",
imx8mm_pcie1_aux_sels, base + 0xa400);
clks[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel",
imx8mm_dc_pixel_sels, base + 0xa480);
- clks[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel",
imx8mm_lcdif_pixel_sels, base + 0xa500);
+ clks[IMX8MM_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel",
imx8mm_disp_pixel_sels, base + 0xa500);
clks[IMX8MM_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mm_sai1_sels,
base + 0xa580);
clks[IMX8MM_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mm_sai2_sels,
base + 0xa600);
clks[IMX8MM_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mm_sai3_sels,
base + 0xa680);
diff --git a/include/dt-bindings/clock/imx8mm-clock.h
b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c686f3ef..91ef77efebd9 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -119,7 +119,7 @@
#define IMX8MM_CLK_PCIE1_PHY 104
#define IMX8MM_CLK_PCIE1_AUX 105
#define IMX8MM_CLK_DC_PIXEL106
-#define IMX8MM_CLK_LCDIF_PIXEL 107
+#define IMX8MM_CLK_DISP_PIXEL 107
#define IMX8MM_CLK_SAI1108
#define IMX8MM_CLK_SAI2109
#define IMX8MM_CLK_SAI3110
--
2.17.1
[PATCH 1/2] clk: imx8mm: rename lcdif pixel clock
Rename 'lcdif' pixel clock related names to 'disp' names, since:
First, the lcdif pixel clock is not supplied to LCDIF controller
directly, but to some LPCG clock in display mix. So rename it to
'disp' pixel clock is more accurate.
Second, in the imx8mn CCM specification which is designed after
imx8mm, this same pixel root clock name has been modified from
'LCDIF_PIXEL_CLK_ROOT' to 'DISPLAY_PIXEL_CLK_ROOT'.
Signed-off-by: Fancy Fang
---
drivers/clk/imx/clk-imx8mm.c | 4 ++--
include/dt-bindings/clock/imx8mm-clock.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75df994d..42f1227a4952 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -210,7 +210,7 @@ static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m",
"sys_pll2_200m", "sys_p
static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_disp_pixel_sels[] = {"osc_24m", "video_pll1_out",
"audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out",
"audio_pll2_out", "video_pll1_out",
@@ -535,7 +535,7 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy",
imx8mm_pcie1_phy_sels, base + 0xa380);
clks[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux",
imx8mm_pcie1_aux_sels, base + 0xa400);
clks[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel",
imx8mm_dc_pixel_sels, base + 0xa480);
- clks[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel",
imx8mm_lcdif_pixel_sels, base + 0xa500);
+ clks[IMX8MM_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel",
imx8mm_disp_pixel_sels, base + 0xa500);
clks[IMX8MM_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mm_sai1_sels,
base + 0xa580);
clks[IMX8MM_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mm_sai2_sels,
base + 0xa600);
clks[IMX8MM_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mm_sai3_sels,
base + 0xa680);
diff --git a/include/dt-bindings/clock/imx8mm-clock.h
b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c686f3ef..91ef77efebd9 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -119,7 +119,7 @@
#define IMX8MM_CLK_PCIE1_PHY 104
#define IMX8MM_CLK_PCIE1_AUX 105
#define IMX8MM_CLK_DC_PIXEL106
-#define IMX8MM_CLK_LCDIF_PIXEL 107
+#define IMX8MM_CLK_DISP_PIXEL 107
#define IMX8MM_CLK_SAI1108
#define IMX8MM_CLK_SAI2109
#define IMX8MM_CLK_SAI3110
--
2.17.1
[PATCH 2/2] clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'
Rename 'share_count_dcss' to 'share_count_disp', since the
DCSS module does not exist on imx8mm platform. So rename it
to avoid any unnecessary confusion.
Signed-off-by: Fancy Fang
---
drivers/clk/imx/clk-imx8mm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 42f1227a4952..42cb33edf8e5 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -22,7 +22,7 @@ static u32 share_count_sai3;
static u32 share_count_sai4;
static u32 share_count_sai5;
static u32 share_count_sai6;
-static u32 share_count_dcss;
+static u32 share_count_disp;
static u32 share_count_pdm;
static u32 share_count_nand;
@@ -644,10 +644,10 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk",
"vpu_g2", base + 0x45a0, 0);
clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk",
"pdm", base + 0x45b0, 0, &share_count_pdm);
clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk",
"ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
- clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk",
"disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
- clks[IMX8MM_CLK_DISP_AXI_ROOT] =
imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0,
&share_count_dcss);
- clks[IMX8MM_CLK_DISP_APB_ROOT] =
imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0,
&share_count_dcss);
- clks[IMX8MM_CLK_DISP_RTRM_ROOT] =
imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0,
&share_count_dcss);
+ clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk",
"disp_dc8000", base + 0x45d0, 0, &share_count_disp);
+ clks[IMX8MM_CLK_DISP_AXI_ROOT] =
imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0,
&share_count_disp);
+ clks[IMX8MM_CLK_DISP_APB_ROOT] =
imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0,
&share_count_disp);
+ clks[IMX8MM_CLK_DISP_RTRM_ROOT] =
imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0,
&share_count_disp);
clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk",
"usdhc3", base + 0x45e0, 0);
clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root",
base + 0x4620, 0);
clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk",
"vpu_bus", base + 0x4630, 0);
--
2.17.1
RE: [PATCH] reset: Add driver for dispmix reset
Hi Philipp, Thanks for your comments. And please see my answers below. -Original Message- From: Philipp Zabel Sent: Tuesday, June 25, 2019 10:57 PM To: Fancy Fang ; shawn...@kernel.org; s.ha...@pengutronix.de Cc: feste...@gmail.com; ker...@pengutronix.de; linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; dl-linux-imx Subject: Re: [PATCH] reset: Add driver for dispmix reset Hi Fancy, thank you for the patch. I have a few questions below. On Tue, 2019-06-25 at 05:54 +, Fancy Fang wrote: > This is an reset driver to implement a reset controller device DISPMIX > on IMX8MM and IMX8MN platforms. Dispmix reset is used to reset or > enable related buses and clks for the submodules in DISPMIX. Unfortunately DISPMIX is not very well documented, so forgive my ignorance. It looks to me like some of those bits don't control reset lines, but are used to gate clocks. Especially the i.MX8MN DISPMIX bits with clock enable bits and corresponding resets look like this should just be a clock controller that automatically (de)asserts the resets as necessary when clocks are enabled. The same goes for the clock soft enable bits on i.MX8MM. If those bits actually control clock gates, they should not be described as reset controls in the device tree. [FF] Make sense. The functions provided by the "dispmix reset" is more likely to be a combination of a clock gating module and a reset control than a standard reset controller. The reason why I choose reset framework to implement this device is that: First, this module is named as "dispmix reset" in the dispmix's design spec, so it gives me the first impression that it should be acted as a reset controller. And I'll check this with the IC designer Second, the "dispmix reset" is separated from the CCM LPCG module which is used as the only clock controller device for the whole platform. So the CCM clock driver seems cannot cover this device. Last, the "dispmix reset" is shared by all the submodules in the dispmix, so I abstract this device to be a reset controller driver to simplify the 'reset' logic for all the submodules drivers. If using clock framework to cover this device, another driver needs to be implemented. I'll take a close look at it to see if this can happen. > All the dispmix resets are divided into three subgroups: > sft_rstn, clk_en and mipi_rst, and each of them contains several reset > lines to control several different modules on and off in DISPMIX which > doesn't require the standard reset flow, but only line assert and > deassert operations. > > Signed-off-by: Fancy Fang > --- > .../bindings/reset/nxp,dispmix-clk-en.txt | 58 +++ > .../bindings/reset/nxp,dispmix-mipi-rst.txt | 57 +++ > .../bindings/reset/nxp,dispmix-sft-rstn.txt | 58 +++ > drivers/reset/Kconfig | 9 + > drivers/reset/Makefile| 1 + > drivers/reset/reset-dispmix.c | 399 ++ > include/dt-bindings/reset/imx8mm-dispmix.h| 49 +++ > include/dt-bindings/reset/imx8mn-dispmix.h| 47 +++ > 8 files changed, 678 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt > create mode 100644 > Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt > create mode 100644 > Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt > create mode 100644 drivers/reset/reset-dispmix.c create mode 100644 > include/dt-bindings/reset/imx8mm-dispmix.h > create mode 100644 include/dt-bindings/reset/imx8mn-dispmix.h > > diff --git > a/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt > b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt > new file mode 100644 > index ..4375039eb072 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt > @@ -0,0 +1,58 @@ > +NXP Display Mix clk-en Reset Controller > +=== > + > +This binding describes a reset controller device that is used to > +enable or disable the internal clocks for all the submodules(such as, > +LCDIF, MIPI DSI, MIPI CSI, ISI and etc) included by the Display Mix > +subsystem on IMX8MM and IMX8MN platforms. Like sft-rstn, only assert > +and deassert functions are required for submodule internal clocks > +enable or disable, ^^ See, doesn't this sound like it should be a clock driver? [FF] As described above. > +that means the clk-en can be treated as a real reset controller. > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- com
[PATCH] reset: Add driver for dispmix reset
This is an reset driver to implement a reset controller
device DISPMIX on IMX8MM and IMX8MN platforms. Dispmix
reset is used to reset or enable related buses and clks
for the submodules in DISPMIX.
All the dispmix resets are divided into three subgroups:
sft_rstn, clk_en and mipi_rst, and each of them contains
several reset lines to control several different modules
on and off in DISPMIX which doesn't require the standard
reset flow, but only line assert and deassert operations.
Signed-off-by: Fancy Fang
---
.../bindings/reset/nxp,dispmix-clk-en.txt | 58 +++
.../bindings/reset/nxp,dispmix-mipi-rst.txt | 57 +++
.../bindings/reset/nxp,dispmix-sft-rstn.txt | 58 +++
drivers/reset/Kconfig | 9 +
drivers/reset/Makefile| 1 +
drivers/reset/reset-dispmix.c | 399 ++
include/dt-bindings/reset/imx8mm-dispmix.h| 49 +++
include/dt-bindings/reset/imx8mn-dispmix.h| 47 +++
8 files changed, 678 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt
create mode 100644
Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt
create mode 100644
Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt
create mode 100644 drivers/reset/reset-dispmix.c
create mode 100644 include/dt-bindings/reset/imx8mm-dispmix.h
create mode 100644 include/dt-bindings/reset/imx8mn-dispmix.h
diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt
b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt
new file mode 100644
index ..4375039eb072
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt
@@ -0,0 +1,58 @@
+NXP Display Mix clk-en Reset Controller
+===
+
+This binding describes a reset controller device that is used to enable
+or disable the internal clocks for all the submodules(such as, LCDIF,
+MIPI DSI, MIPI CSI, ISI and etc) included by the Display Mix subsystem
+on IMX8MM and IMX8MN platforms. Like sft-rstn, only assert and deassert
+functions are required for submodule internal clocks enable or disable,
+that means the clk-en can be treated as a real reset controller.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "fsl,imx8mm-dispmix-clk-en" or
+ "fsl,imx8mn-dispmix-clk-en".
+- reg: should be register base and length as documented in the datasheet.
+- clocks: phandle and clock specifier to disp apb clock for register access.
+- clock-names: should be "disp-apb".
+- power-domains: phandle to dispmix power domain.
+- reset-cells: 1, see below.
+
+example:
+
+ dispmix_clk_en: dispmix-clk-en@32e28004 {
+ compatible = "fsl,imx8mn-dispmix-clk-en";
+ reg = <0x0 0x32e28004 0x0 0x4>;
+ clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+ clock-names = "disp-apb";
+ power-domains = <&dispmix_pd>;
+ #reset-cells = <1>;
+ };
+
+Specifying clk-en control of devices
+
+
+Device nodes in Display Mix should specify the reset channel required in
+their "resets" property, containing a phandle to the clk-en device node
+and an index to specify which channel to use, as described in
+Documentation/devicetree/bindings/reset/reset.txt.
+
+example:
+
+ lcdif_resets: lcdif-resets {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #reset-cells = <0>;
+
+ lcdif-clk-enable {
+ compatible = "lcdif,clk-enable";
+ resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>,
+<&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>;
+ };
+ };
+
+Macro definitions for the supported reset channels can be found in:
+include/dt-bindings/reset/imx8mm-dispmix.h and
+include/dt-bindings/reset/imx8mn-dispmix.h.
diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt
b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt
new file mode 100644
index ..c47bfd4842ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt
@@ -0,0 +1,57 @@
+NXP Display Mix mipi-rst Reset Controller
+=
+
+This binding describes a reset controller device that is used to reset
+or de-reset the MIPI DPHY master direction(for MIPI DSI) and slave
+direction(for MIPI CSI) included by the Display Mix subsystem on IMX8MM
+and IMX8MN platforms. Like sft-rstn, only assert and deassert functions
+are required for PHY reset or de-reset.
+
+Please also refer to reset.txt in this directory for commo
[PATCH v2] [media] videobuf-dma-contig: set vm_pgoff to be zero to pass the sanity check in vm_iomap_memory().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
Reviewed-by: Marek Szyprowski
Reviewed-by: Hans Verkuil
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..e02353e 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,6 +305,15 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ /* the "vm_pgoff" is just used in v4l2 to find the
+* corresponding buffer data structure which is allocated
+* earlier and it does not mean the offset from the physical
+* buffer start address as usual. So set it to 0 to pass
+* the sanity check in vm_iomap_memory().
+*/
+ vma->vm_pgoff = 0;
+
retval = vm_iomap_memory(vma, mem->dma_handle, size);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
--
1.9.1
--
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[PATCH v2] [media] videobuf-dma-contig: set vm_pgoff to be zero to pass the sanity check in vm_iomap_memory().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
Reviewed-by: Marek Szyprowski
Reviewed-by: Hans Verkuil
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..e02353e 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,6 +305,15 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ /* the "vm_pgoff" is just used in v4l2 to find the
+* corresponding buffer data structure which is allocated
+* earlier and it does not mean the offset from the physical
+* buffer start address as usual. So set it to 0 to pass
+* the sanity check in vm_iomap_memory().
+*/
+ vma->vm_pgoff = 0;
+
retval = vm_iomap_memory(vma, mem->dma_handle, size);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
--
1.9.1
--
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[PATCH v2] [media] videobuf-dma-contig: set vm_pgoff to be zero to pass the sanity check in vm_iomap_memory().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
Reviewed-by: Marek Szyprowski
Reviewed-by: Hans Verkuil
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..e02353e 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,6 +305,15 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ /* the "vm_pgoff" is just used in v4l2 to find the
+* corresponding buffer data structure which is allocated
+* earlier and it does not mean the offset from the physical
+* buffer start address as usual. So set it to 0 to pass
+* the sanity check in vm_iomap_memory().
+*/
+ vma->vm_pgoff = 0;
+
retval = vm_iomap_memory(vma, mem->dma_handle, size);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] [media] videobuf-dma-contig: replace vm_iomap_memory() with remap_pfn_range().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..8bd9889 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,7 +305,9 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- retval = vm_iomap_memory(vma, mem->dma_handle, size);
+ retval = remap_pfn_range(vma, vma->vm_start,
+mem->dma_handle >> PAGE_SHIFT,
+size, vma->vm_page_prot);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
retval);
--
1.9.1
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang
Signed-off-by: Robby Cai
Acked-by: Shawn Guo
---
arch/arm/mach-imx/clk-imx6sl.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 43261ea..d730dfa 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -47,7 +47,8 @@ static const char *csi_lcdif_sels[] = { "mmdc",
"pll2_pfd2", "pll3_120m", "pll3_
static const char *usdhc_sels[]= { "pll2_pfd2", "pll2_pfd0", };
static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3",
"pll4_audio_div", "dummy", };
static const char *perclk_sels[] = { "ipg", "osc", };
-static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
+static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
static const char *gpu2d_ovg_sels[]= { "pll3_pfd1", "pll3_usb_otg",
"pll2_bus", "pll2_pfd2", };
static const char *gpu2d_sels[]= { "pll2_pfd2",
"pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char *lcdif_pix_sels[]= { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
@@ -251,8 +252,8 @@ static void __init imx6sl_clocks_init(struct device_node
*ccm_node)
clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel",
base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels),
imx_cscmr1_fixup);
clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel",
base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels),
imx_cscmr1_fixup);
clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel",
base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels),
imx_cscmr1_fixup);
- clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel",
base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
- clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel",
base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
+ clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel",
base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
+ clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel",
base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
clks[IMX6SL_CLK_GPU2D_OVG_SEL]= imx_clk_mux("gpu2d_ovg_sel",
base + 0x18, 4, 2, gpu2d_ovg_sels,ARRAY_SIZE(gpu2d_ovg_sels));
clks[IMX6SL_CLK_GPU2D_SEL]= imx_clk_mux("gpu2d_sel",
base + 0x18, 8, 2, gpu2d_sels,ARRAY_SIZE(gpu2d_sels));
clks[IMX6SL_CLK_LCDIF_PIX_SEL]= imx_clk_mux("lcdif_pix_sel",
base + 0x38, 6, 3, lcdif_pix_sels,ARRAY_SIZE(lcdif_pix_sels));
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] [media] videobuf-dma-contig: replace vm_iomap_memory() with remap_pfn_range().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..8bd9889 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,7 +305,9 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- retval = vm_iomap_memory(vma, mem->dma_handle, size);
+ retval = remap_pfn_range(vma, vma->vm_start,
+mem->dma_handle >> PAGE_SHIFT,
+size, vma->vm_page_prot);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
retval);
--
1.9.1
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang
Signed-off-by: Robby Cai
Acked-by: Shawn Guo
---
arch/arm/mach-imx/clk-imx6sl.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 43261ea..d730dfa 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -47,7 +47,8 @@ static const char *csi_lcdif_sels[] = { "mmdc",
"pll2_pfd2", "pll3_120m", "pll3_
static const char *usdhc_sels[]= { "pll2_pfd2", "pll2_pfd0", };
static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3",
"pll4_audio_div", "dummy", };
static const char *perclk_sels[] = { "ipg", "osc", };
-static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
+static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
static const char *gpu2d_ovg_sels[]= { "pll3_pfd1", "pll3_usb_otg",
"pll2_bus", "pll2_pfd2", };
static const char *gpu2d_sels[]= { "pll2_pfd2",
"pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char *lcdif_pix_sels[]= { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
@@ -251,8 +252,8 @@ static void __init imx6sl_clocks_init(struct device_node
*ccm_node)
clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel",
base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels),
imx_cscmr1_fixup);
clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel",
base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels),
imx_cscmr1_fixup);
clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel",
base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels),
imx_cscmr1_fixup);
- clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel",
base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
- clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel",
base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
+ clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel",
base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
+ clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel",
base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
clks[IMX6SL_CLK_GPU2D_OVG_SEL]= imx_clk_mux("gpu2d_ovg_sel",
base + 0x18, 4, 2, gpu2d_ovg_sels,ARRAY_SIZE(gpu2d_ovg_sels));
clks[IMX6SL_CLK_GPU2D_SEL]= imx_clk_mux("gpu2d_sel",
base + 0x18, 8, 2, gpu2d_sels,ARRAY_SIZE(gpu2d_sels));
clks[IMX6SL_CLK_LCDIF_PIX_SEL]= imx_clk_mux("lcdif_pix_sel",
base + 0x38, 6, 3, lcdif_pix_sels,ARRAY_SIZE(lcdif_pix_sels));
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] [media] videobuf-dma-contig: replace vm_iomap_memory() with remap_pfn_range().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Signed-off-by: Fancy Fang
---
drivers/media/v4l2-core/videobuf-dma-contig.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index bf80f0f..8bd9889 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -305,7 +305,9 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
/* Try to remap memory */
size = vma->vm_end - vma->vm_start;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- retval = vm_iomap_memory(vma, mem->dma_handle, size);
+ retval = remap_pfn_range(vma, vma->vm_start,
+mem->dma_handle >> PAGE_SHIFT,
+size, vma->vm_page_prot);
if (retval) {
dev_err(q->dev, "mmap: remap failed with error %d. ",
retval);
--
1.9.1
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