[PATCH V4 24/27] clocksource: add C-SKY SMP timer
This timer is used by SMP system and use mfcr/mtcr instruction
to access the regs.
Changelog:
- Support csky mp timer alpha version.
- Just use low-counter with 32bit width as clocksource.
- Coding convention with upstream feed-back.
Signed-off-by: Guo Ren
---
drivers/clocksource/csky_mptimer.c | 178 +
1 file changed, 178 insertions(+)
create mode 100644 drivers/clocksource/csky_mptimer.c
diff --git a/drivers/clocksource/csky_mptimer.c
b/drivers/clocksource/csky_mptimer.c
new file mode 100644
index 000..da2b239
--- /dev/null
+++ b/drivers/clocksource/csky_mptimer.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define PTIM_CCVR "cr<3, 14>"
+#define PTIM_CTLR "cr<0, 14>"
+#define PTIM_LVR "cr<6, 14>"
+#define PTIM_TSR "cr<1, 14>"
+
+static int csky_mptimer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ mtcr(PTIM_LVR, delta);
+
+ return 0;
+}
+
+static int csky_mptimer_shutdown(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+static int csky_mptimer_oneshot(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 1);
+
+ return 0;
+}
+
+static int csky_mptimer_oneshot_stopped(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct timer_of, csky_to) = {
+ .flags = TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERCPU |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = csky_mptimer_shutdown,
+ .set_state_oneshot = csky_mptimer_oneshot,
+ .set_state_oneshot_stopped = csky_mptimer_oneshot_stopped,
+ .set_next_event = csky_mptimer_set_next_event,
+ },
+ .of_irq = {
+ .flags = IRQF_TIMER,
+ .percpu = 1,
+ },
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev)
+{
+ struct timer_of *to = this_cpu_ptr(_to);
+
+ mtcr(PTIM_TSR, 0);
+
+ to->clkevt.event_handler(>clkevt);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * clock event for percpu
+ */
+static int csky_mptimer_starting_cpu(unsigned int cpu)
+{
+ struct timer_of *to = per_cpu_ptr(_to, cpu);
+
+ to->clkevt.cpumask = cpumask_of(cpu);
+
+ clockevents_config_and_register(>clkevt, timer_of_rate(to), 2,
ULONG_MAX);
+
+ enable_percpu_irq(timer_of_irq(to), 0);
+
+ return 0;
+}
+
+static int csky_mptimer_dying_cpu(unsigned int cpu)
+{
+ struct timer_of *to = per_cpu_ptr(_to, cpu);
+
+ disable_percpu_irq(timer_of_irq(to));
+
+ return 0;
+}
+
+/*
+ * clock source
+ */
+static u64 sched_clock_read(void)
+{
+ return (u64) mfcr(PTIM_CCVR);
+}
+
+static u64 clksrc_read(struct clocksource *c)
+{
+ return (u64) mfcr(PTIM_CCVR);
+}
+
+struct clocksource csky_clocksource = {
+ .name = "csky",
+ .rating = 400,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = clksrc_read,
+};
+
+#define CPUHP_AP_CSKY_TIMER_STARTING CPUHP_AP_DUMMY_TIMER_STARTING
+
+static int __init csky_mptimer_init(struct device_node *np)
+{
+ int ret, cpu;
+ struct timer_of *to;
+ int rate = 0;
+ int irq = 0;
+
+ /*
+* Csky_mptimer is designed for C-SKY SMP multi-processors and
+* every core has it's own private irq and regs for clkevt and
+* clksrc.
+*
+* The regs is accessed by cpu instruction: mfcr/mtcr instead of
+* mmio map style. So we needn't mmio-address in dts, but we still
+* need to give clk and irq number.
+*
+* We use private irq for the mptimer and irq number is the same
+* for every core. So we use request_percpu_irq() in timer_of_init.
+*/
+
+ for_each_possible_cpu(cpu) {
+ to = per_cpu_ptr(_to, cpu);
+
+ if (cpu == 0) {
+ to->flags |= TIMER_OF_IRQ;
+ to->of_irq.handler = timer_interrupt;
+
+ ret = timer_of_init(np, to);
+ if (ret)
+ return ret;
+
+ rate= timer_of_rate(to);
+ irq = to->of_irq.irq;
+ } else {
+ ret = timer_of_init(np, to);
+ if (ret)
+ re
[PATCH V4 14/27] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 398
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 669 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..821fca0
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+ return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memor
[PATCH V4 14/27] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 398
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 669 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..821fca0
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+ return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memor
[PATCH V4 21/27] dt-bindings: interrupt-controller: C-SKY APB intc
Signed-off-by: Guo Ren
---
.../interrupt-controller/csky,apb-intc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
new file mode 100644
index 000..dbe55f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
@@ -0,0 +1,45 @@
+==
+C-SKY APB Interrupt Controller
+==
+
+C-SKY APB Interrupt Controller is a simple soc interrupt controller
+on the apb bus and we only use it as root irq controller.
+
+ - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq
nums.
+ - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
+ - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq
nums.
+
+=
+intc node bindings definition
+=
+
+Description: Describes APB interrupt controller
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,apb-intc"
+ "csky,dual-apb-intc"
+ "csky,gx6605s-intc"
+- #interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+ - reg
+ Usage: required
+ Value type:
+Definition: in soc from cpu view
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller@50 {
+ compatible = "csky,apb-intc";
+ #interrupt-cells = <1>;
+ reg = <0x0050 0x400>;
+ interrupt-controller;
+ };
--
2.7.4
[PATCH V4 21/27] dt-bindings: interrupt-controller: C-SKY APB intc
Signed-off-by: Guo Ren
---
.../interrupt-controller/csky,apb-intc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
new file mode 100644
index 000..dbe55f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
@@ -0,0 +1,45 @@
+==
+C-SKY APB Interrupt Controller
+==
+
+C-SKY APB Interrupt Controller is a simple soc interrupt controller
+on the apb bus and we only use it as root irq controller.
+
+ - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq
nums.
+ - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
+ - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq
nums.
+
+=
+intc node bindings definition
+=
+
+Description: Describes APB interrupt controller
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,apb-intc"
+ "csky,dual-apb-intc"
+ "csky,gx6605s-intc"
+- #interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+ - reg
+ Usage: required
+ Value type:
+Definition: in soc from cpu view
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller@50 {
+ compatible = "csky,apb-intc";
+ #interrupt-cells = <1>;
+ reg = <0x0050 0x400>;
+ interrupt-controller;
+ };
--
2.7.4
[PATCH V4 16/27] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..522c73f
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,234 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+ if (cpu >= NR_CPUS)
+ continue;
+
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+volatile unsigned int secondary_hint;
+volatile unsigned int secondary_ccr;
+volatile unsigned int secondary_stack;
+
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+{
+ unsigned int tmp;
+
+ secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
+
+ secondary_hint = mfcr("cr31");
+
+ secondary_ccr = mfcr("cr18");
+
+ /* Flush dcache */
+ mtcr("cr17", 0x22);
+
+ /* Enable cpu in SMP reset ctrl reg */
+ tmp = mfcr(&q
[PATCH V4 15/27] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..10b9028
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel (char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..499f7ef
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..3ef91ee
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memo
[PATCH V4 17/27] csky: Misc headers
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/reg_ops.h | 26 +++
arch/csky/abiv1/inc/abi/regdef.h | 25 +++
arch/csky/abiv2/inc/abi/reg_ops.h | 17 ++
arch/csky/abiv2/inc/abi/regdef.h | 26 +++
arch/csky/boot/dts/qemu.dts| 77 +
arch/csky/include/asm/bitops.h | 281 +
arch/csky/include/asm/checksum.h | 54 +++
arch/csky/include/asm/compat.h | 11 ++
arch/csky/include/asm/reg_ops.h| 22 +++
arch/csky/include/uapi/asm/byteorder.h | 9 ++
arch/csky/kernel/asm-offsets.c | 85 ++
11 files changed, 633 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv1/inc/abi/regdef.h
create mode 100644 arch/csky/abiv2/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv2/inc/abi/regdef.h
create mode 100644 arch/csky/boot/dts/qemu.dts
create mode 100644 arch/csky/include/asm/bitops.h
create mode 100644 arch/csky/include/asm/checksum.h
create mode 100644 arch/csky/include/asm/compat.h
create mode 100644 arch/csky/include/asm/reg_ops.h
create mode 100644 arch/csky/include/uapi/asm/byteorder.h
create mode 100644 arch/csky/kernel/asm-offsets.c
diff --git a/arch/csky/abiv1/inc/abi/reg_ops.h
b/arch/csky/abiv1/inc/abi/reg_ops.h
new file mode 100644
index 000..c5d2ff4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/reg_ops.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+#define cprcr(reg) \
+({ \
+ unsigned int tmp; \
+ asm volatile("cprcr %0, "reg"\n":"=b"(tmp));\
+ tmp;\
+})
+
+#define cpwcr(reg, val)\
+({ \
+ asm volatile("cpwcr %0, "reg"\n"::"b"(val));\
+})
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr30");
+}
+
+static inline unsigned int mfcr_ccr2(void){return 0;}
+
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv1/inc/abi/regdef.h b/arch/csky/abiv1/inc/abi/regdef.h
new file mode 100644
index 000..cc4cebd
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/regdef.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r1
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[9]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-0 |
+ * S CPID VEC TM
+ *
+ *S: Super Mode
+ * CPID: Coprocessor id, only 15 for MMU
+ * VEC: Exception Number
+ * TM: Trace Mode
+ */
+#define DEFAULT_PSR_VALUE 0x8f00
+
+#define SYSTRACE_SAVENUM 2
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/abiv2/inc/abi/reg_ops.h
b/arch/csky/abiv2/inc/abi/reg_ops.h
new file mode 100644
index 000..ffe4fc9
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/reg_ops.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr31");
+}
+
+static inline unsigned int mfcr_ccr2(void)
+{
+ return mfcr("cr23");
+}
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv2/inc/abi/regdef.h b/arch/csky/abiv2/inc/abi/regdef.h
new file mode 100644
index 000..676e74a
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/regdef.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r7
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[3]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 |
+ * S VEC TMMM
+ *
+ * S: Super Mode
+ * VEC: Exception Number
+ * TM: Trace Mode
+ * MM: Memory unaligned addr access
+ */
+#define DEFAULT_PSR_VALUE 0x8200
+
+#define SYSTRACE_SAVENUM 5
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
new file mode 100644
index 000..c6643b1
--- /dev/null
+++ b/arch/csky/boot/dts/qemu.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+/ {
+ compatible = "csky,qemu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path =
+ };
+
+ memory@0 {
+
[PATCH V4 19/27] dt-bindings: timer: gx6605s SOC timer
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
new file mode 100644
index 000..230a9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
@@ -0,0 +1,42 @@
+=
+gx6605s SOC Timer
+=
+
+The timer is used in gx6605s soc as system timer and the driver
+contain clk event and clk source.
+
+==
+timer node bindings definition
+==
+
+Description: Describes gx6605s SOC timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,gx6605s-timer"
+ - reg
+ Usage: required
+ Value type:
+ Definition: in soc from cpu view
+ - clocks
+ Usage: required
+ Value type: phandle + clock specifier cells
+ Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+
+Examples:
+-
+
+ timer0: timer@20a000 {
+ compatible = "csky,gx6605s-timer";
+ reg = <0x0020a000 0x400>;
+ clocks = <_apb_clk>;
+ interrupts = <10>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V4 16/27] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..522c73f
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,234 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+ if (cpu >= NR_CPUS)
+ continue;
+
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+volatile unsigned int secondary_hint;
+volatile unsigned int secondary_ccr;
+volatile unsigned int secondary_stack;
+
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+{
+ unsigned int tmp;
+
+ secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
+
+ secondary_hint = mfcr("cr31");
+
+ secondary_ccr = mfcr("cr18");
+
+ /* Flush dcache */
+ mtcr("cr17", 0x22);
+
+ /* Enable cpu in SMP reset ctrl reg */
+ tmp = mfcr(&q
[PATCH V4 15/27] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..10b9028
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel (char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..499f7ef
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..3ef91ee
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memo
[PATCH V4 17/27] csky: Misc headers
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/reg_ops.h | 26 +++
arch/csky/abiv1/inc/abi/regdef.h | 25 +++
arch/csky/abiv2/inc/abi/reg_ops.h | 17 ++
arch/csky/abiv2/inc/abi/regdef.h | 26 +++
arch/csky/boot/dts/qemu.dts| 77 +
arch/csky/include/asm/bitops.h | 281 +
arch/csky/include/asm/checksum.h | 54 +++
arch/csky/include/asm/compat.h | 11 ++
arch/csky/include/asm/reg_ops.h| 22 +++
arch/csky/include/uapi/asm/byteorder.h | 9 ++
arch/csky/kernel/asm-offsets.c | 85 ++
11 files changed, 633 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv1/inc/abi/regdef.h
create mode 100644 arch/csky/abiv2/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv2/inc/abi/regdef.h
create mode 100644 arch/csky/boot/dts/qemu.dts
create mode 100644 arch/csky/include/asm/bitops.h
create mode 100644 arch/csky/include/asm/checksum.h
create mode 100644 arch/csky/include/asm/compat.h
create mode 100644 arch/csky/include/asm/reg_ops.h
create mode 100644 arch/csky/include/uapi/asm/byteorder.h
create mode 100644 arch/csky/kernel/asm-offsets.c
diff --git a/arch/csky/abiv1/inc/abi/reg_ops.h
b/arch/csky/abiv1/inc/abi/reg_ops.h
new file mode 100644
index 000..c5d2ff4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/reg_ops.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+#define cprcr(reg) \
+({ \
+ unsigned int tmp; \
+ asm volatile("cprcr %0, "reg"\n":"=b"(tmp));\
+ tmp;\
+})
+
+#define cpwcr(reg, val)\
+({ \
+ asm volatile("cpwcr %0, "reg"\n"::"b"(val));\
+})
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr30");
+}
+
+static inline unsigned int mfcr_ccr2(void){return 0;}
+
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv1/inc/abi/regdef.h b/arch/csky/abiv1/inc/abi/regdef.h
new file mode 100644
index 000..cc4cebd
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/regdef.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r1
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[9]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-0 |
+ * S CPID VEC TM
+ *
+ *S: Super Mode
+ * CPID: Coprocessor id, only 15 for MMU
+ * VEC: Exception Number
+ * TM: Trace Mode
+ */
+#define DEFAULT_PSR_VALUE 0x8f00
+
+#define SYSTRACE_SAVENUM 2
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/abiv2/inc/abi/reg_ops.h
b/arch/csky/abiv2/inc/abi/reg_ops.h
new file mode 100644
index 000..ffe4fc9
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/reg_ops.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr31");
+}
+
+static inline unsigned int mfcr_ccr2(void)
+{
+ return mfcr("cr23");
+}
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv2/inc/abi/regdef.h b/arch/csky/abiv2/inc/abi/regdef.h
new file mode 100644
index 000..676e74a
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/regdef.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r7
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[3]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 |
+ * S VEC TMMM
+ *
+ * S: Super Mode
+ * VEC: Exception Number
+ * TM: Trace Mode
+ * MM: Memory unaligned addr access
+ */
+#define DEFAULT_PSR_VALUE 0x8200
+
+#define SYSTRACE_SAVENUM 5
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
new file mode 100644
index 000..c6643b1
--- /dev/null
+++ b/arch/csky/boot/dts/qemu.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+/ {
+ compatible = "csky,qemu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path =
+ };
+
+ memory@0 {
+
[PATCH V4 19/27] dt-bindings: timer: gx6605s SOC timer
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
new file mode 100644
index 000..230a9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
@@ -0,0 +1,42 @@
+=
+gx6605s SOC Timer
+=
+
+The timer is used in gx6605s soc as system timer and the driver
+contain clk event and clk source.
+
+==
+timer node bindings definition
+==
+
+Description: Describes gx6605s SOC timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,gx6605s-timer"
+ - reg
+ Usage: required
+ Value type:
+ Definition: in soc from cpu view
+ - clocks
+ Usage: required
+ Value type: phandle + clock specifier cells
+ Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+
+Examples:
+-
+
+ timer0: timer@20a000 {
+ compatible = "csky,gx6605s-timer";
+ reg = <0x0020a000 0x400>;
+ clocks = <_apb_clk>;
+ interrupts = <10>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V4 13/27] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 28
arch/csky/abiv2/memcmp.S | 151 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memcpy.c | 40 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 29
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/platform.c | 17 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 40 +
21 files changed, 1482 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..6e26b7e
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..60d4fc4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
[PATCH V4 13/27] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 28
arch/csky/abiv2/memcmp.S | 151 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memcpy.c | 40 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 29
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/platform.c | 17 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 40 +
21 files changed, 1482 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..6e26b7e
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..60d4fc4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
[PATCH V4 12/27] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9eef4a1 --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 252 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->
[PATCH V4 11/27] csky: Atomic operations
Signed-off-by: Guo Ren
---
arch/csky/include/asm/atomic.h | 215 +
arch/csky/include/asm/cmpxchg.h| 70
arch/csky/include/asm/spinlock.h | 286 +
arch/csky/include/asm/spinlock_types.h | 35
arch/csky/kernel/atomic.S | 86 ++
5 files changed, 692 insertions(+)
create mode 100644 arch/csky/include/asm/atomic.h
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/atomic.h b/arch/csky/include/asm/atomic.h
new file mode 100644
index 000..82a124e
--- /dev/null
+++ b/arch/csky/include/asm/atomic.h
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_ATOMIC_H
+#define __ASM_CSKY_ATOMIC_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+
+#define __atomic_add_unless __atomic_add_unless
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ unsigned long tmp, ret;
+
+ smp_mb();
+
+ asm volatile (
+ "1: ldex.w %0, (%3) \n"
+ " mov %1, %0 \n"
+ " cmpne %0, %4 \n"
+ " bf 2f \n"
+ " add %0, %2 \n"
+ " stex.w %0, (%3) \n"
+ " bez %0, 1b \n"
+ "2: \n"
+ : "=" (tmp), "=" (ret)
+ : "r" (a), "r"(>counter), "r"(u)
+ : "memory");
+
+ if (ret != u)
+ smp_mb();
+
+ return ret;
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ unsigned long tmp; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%2) \n"\
+ " " #op " %0, %1 \n"\
+ " stex.w %0, (%2) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+}
+
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " " #op " %0, %2 \n"\
+ " mov %1, %0 \n"\
+ " stex.w %0, (%3) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp), "=" (ret) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+ \
+ return ret; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v)
\
+{ \
+ unsigned long tmp, ret; \
+
[PATCH V4 12/27] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9eef4a1 --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 252 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->
[PATCH V4 11/27] csky: Atomic operations
Signed-off-by: Guo Ren
---
arch/csky/include/asm/atomic.h | 215 +
arch/csky/include/asm/cmpxchg.h| 70
arch/csky/include/asm/spinlock.h | 286 +
arch/csky/include/asm/spinlock_types.h | 35
arch/csky/kernel/atomic.S | 86 ++
5 files changed, 692 insertions(+)
create mode 100644 arch/csky/include/asm/atomic.h
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/atomic.h b/arch/csky/include/asm/atomic.h
new file mode 100644
index 000..82a124e
--- /dev/null
+++ b/arch/csky/include/asm/atomic.h
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_ATOMIC_H
+#define __ASM_CSKY_ATOMIC_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+
+#define __atomic_add_unless __atomic_add_unless
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ unsigned long tmp, ret;
+
+ smp_mb();
+
+ asm volatile (
+ "1: ldex.w %0, (%3) \n"
+ " mov %1, %0 \n"
+ " cmpne %0, %4 \n"
+ " bf 2f \n"
+ " add %0, %2 \n"
+ " stex.w %0, (%3) \n"
+ " bez %0, 1b \n"
+ "2: \n"
+ : "=" (tmp), "=" (ret)
+ : "r" (a), "r"(>counter), "r"(u)
+ : "memory");
+
+ if (ret != u)
+ smp_mb();
+
+ return ret;
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ unsigned long tmp; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%2) \n"\
+ " " #op " %0, %1 \n"\
+ " stex.w %0, (%2) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+}
+
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " " #op " %0, %2 \n"\
+ " mov %1, %0 \n"\
+ " stex.w %0, (%3) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp), "=" (ret) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+ \
+ return ret; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v)
\
+{ \
+ unsigned long tmp, ret; \
+
[PATCH V3 09/27] csky: VDSO and rt_sigreturn
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17 +
arch/csky/abiv2/inc/abi/vdso.h | 24
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 85 ++
4 files changed, 138 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..a99f0e4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..2b5f43b
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_VDSO_H
+#define __ABI_CSKY_VDSO_H
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..b275440
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..55ed68b
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err) panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
--
2.7.4
[PATCH V3 09/27] csky: VDSO and rt_sigreturn
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17 +
arch/csky/abiv2/inc/abi/vdso.h | 24
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 85 ++
4 files changed, 138 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..a99f0e4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..2b5f43b
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_VDSO_H
+#define __ABI_CSKY_VDSO_H
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..b275440
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..55ed68b
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err) panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
--
2.7.4
[PATCH V3 08/27] csky: Process management and Signal
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 281 +
arch/csky/abiv2/inc/abi/fpu.h | 66 ++
arch/csky/include/asm/mmu_context.h | 148 ++
arch/csky/include/asm/processor.h | 120 +++
arch/csky/include/asm/switch_to.h | 35
arch/csky/include/asm/thread_info.h | 74 +++
arch/csky/include/uapi/asm/sigcontext.h | 13 ++
arch/csky/kernel/process.c | 134
arch/csky/kernel/signal.c | 350
arch/csky/kernel/time.c | 11 +
10 files changed, 1232 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/switch_to.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..8de6b2b
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs * regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1) return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault) return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault) return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2) return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST)
+ {
+ index = (tinstr >> 16) & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2) return 0;
+
+ regx = *(>a0 + index);
+
+ if(tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2) return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs * regs)
+{
+ int sig;
+ unsigned int fesr;
+ siginfo_t info;
+
+ fesr = mfcr("cr<2, 2>");
+
+ if(fesr & FPE_ILLE){
+ info.si_code = ILL_ILLOPC;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_IDC){
+ info.si_code = ILL_ILLOPN;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_FEC){
+ sig = SIGFPE;
+ if(fesr & FPE_IOC){
+ info.si_code = FPE_FLTINV;
+ }
+ else if(fesr & FPE_DZC){
+ info.si_code = FPE_FLTDIV;
+ }
+ else if(fesr & FPE_UFC){
+ info.si_code = FPE_FLTUND;
+ }
+ else if(fesr & FPE_OFC){
+ info.si_code = FPE_FLTOVF;
+ }
+ else if(fesr & FPE_IXC){
+ info.si_code = FPE_FLTRES;
+ }
+ else {
+ info.si_code = NSIGFPE;
+ }
+ }
+ else {
+ info.si_code = NSIGFPE;
+ sig = SIGFPE;
+ }
+ info.si_signo = SI
[PATCH V3 08/27] csky: Process management and Signal
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 281 +
arch/csky/abiv2/inc/abi/fpu.h | 66 ++
arch/csky/include/asm/mmu_context.h | 148 ++
arch/csky/include/asm/processor.h | 120 +++
arch/csky/include/asm/switch_to.h | 35
arch/csky/include/asm/thread_info.h | 74 +++
arch/csky/include/uapi/asm/sigcontext.h | 13 ++
arch/csky/kernel/process.c | 134
arch/csky/kernel/signal.c | 350
arch/csky/kernel/time.c | 11 +
10 files changed, 1232 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/switch_to.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..8de6b2b
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs * regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1) return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault) return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault) return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2) return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST)
+ {
+ index = (tinstr >> 16) & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2) return 0;
+
+ regx = *(>a0 + index);
+
+ if(tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2) return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs * regs)
+{
+ int sig;
+ unsigned int fesr;
+ siginfo_t info;
+
+ fesr = mfcr("cr<2, 2>");
+
+ if(fesr & FPE_ILLE){
+ info.si_code = ILL_ILLOPC;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_IDC){
+ info.si_code = ILL_ILLOPN;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_FEC){
+ sig = SIGFPE;
+ if(fesr & FPE_IOC){
+ info.si_code = FPE_FLTINV;
+ }
+ else if(fesr & FPE_DZC){
+ info.si_code = FPE_FLTDIV;
+ }
+ else if(fesr & FPE_UFC){
+ info.si_code = FPE_FLTUND;
+ }
+ else if(fesr & FPE_OFC){
+ info.si_code = FPE_FLTOVF;
+ }
+ else if(fesr & FPE_IXC){
+ info.si_code = FPE_FLTRES;
+ }
+ else {
+ info.si_code = NSIGFPE;
+ }
+ }
+ else {
+ info.si_code = NSIGFPE;
+ sig = SIGFPE;
+ }
+ info.si_signo = SI
[PATCH V3 16/27] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..522c73f
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,234 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+ if (cpu >= NR_CPUS)
+ continue;
+
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+volatile unsigned int secondary_hint;
+volatile unsigned int secondary_ccr;
+volatile unsigned int secondary_stack;
+
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+{
+ unsigned int tmp;
+
+ secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
+
+ secondary_hint = mfcr("cr31");
+
+ secondary_ccr = mfcr("cr18");
+
+ /* Flush dcache */
+ mtcr("cr17", 0x22);
+
+ /* Enable cpu in SMP reset ctrl reg */
+ tmp = mfcr(&q
[PATCH V3 10/27] csky: IRQ handling
Signed-off-by: Guo Ren
---
arch/csky/include/asm/irq.h | 8 +++
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 21 +
3 files changed, 78 insertions(+)
create mode 100644 arch/csky/include/asm/irq.h
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irq.h b/arch/csky/include/asm/irq.h
new file mode 100644
index 000..f8ce7f4
--- /dev/null
+++ b/arch/csky/include/asm/irq.h
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQ_H
+#define __ASM_CSKY_IRQ_H
+
+#include
+
+#endif /* __ASM_CSKY_IRQ_H */
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..bd55b21
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n":::"memory");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n":::"memory");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n":::"memory");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..798a2ba
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V3 16/27] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..522c73f
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,234 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+ if (cpu >= NR_CPUS)
+ continue;
+
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+volatile unsigned int secondary_hint;
+volatile unsigned int secondary_ccr;
+volatile unsigned int secondary_stack;
+
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+{
+ unsigned int tmp;
+
+ secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
+
+ secondary_hint = mfcr("cr31");
+
+ secondary_ccr = mfcr("cr18");
+
+ /* Flush dcache */
+ mtcr("cr17", 0x22);
+
+ /* Enable cpu in SMP reset ctrl reg */
+ tmp = mfcr(&q
[PATCH V3 10/27] csky: IRQ handling
Signed-off-by: Guo Ren
---
arch/csky/include/asm/irq.h | 8 +++
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 21 +
3 files changed, 78 insertions(+)
create mode 100644 arch/csky/include/asm/irq.h
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irq.h b/arch/csky/include/asm/irq.h
new file mode 100644
index 000..f8ce7f4
--- /dev/null
+++ b/arch/csky/include/asm/irq.h
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQ_H
+#define __ASM_CSKY_IRQ_H
+
+#include
+
+#endif /* __ASM_CSKY_IRQ_H */
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..bd55b21
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n":::"memory");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n":::"memory");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n":::"memory");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..798a2ba
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V3 15/27] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..10b9028
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel (char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..499f7ef
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..3ef91ee
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memo
[PATCH V3 15/27] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..10b9028
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel (char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..499f7ef
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..3ef91ee
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memo
[PATCH V3 05/27] csky: System Call
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 69 +
arch/csky/include/asm/syscalls.h| 14
arch/csky/include/uapi/asm/unistd.h | 10 ++
arch/csky/kernel/syscall.c | 42 ++
arch/csky/kernel/syscall_table.c| 13 +++
5 files changed, 148 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..8966739
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,69 @@
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+}
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..c478830
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..6fc1448
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#define __ARCH_WANT_SYS_CLONE
+#include
+
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/csky/kernel/syscall.c b/arch/csky/kernel/syscall.c
new file mode 100644
index 000..3f38a28
--- /dev/null
+++ b/arch/csky/kernel/syscall.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
+{
+ struct thread_info *ti = task_thread_info(current);
+ struct pt_regs *reg = current_pt_regs();
+
+ reg->tls = addr;
+ ti->tp_value = addr;
+
+ return 0;
+}
+
+SYSCALL_DEFINE6(mmap2,
+ unsigned long, addr,
+ unsigned long, len,
+ unsigned long, prot,
+ unsigned long, flags,
+ unsigned long, fd,
+ off_t, offset)
+{
+ if (unlikely(offset & (~PAGE_MASK >> 12)))
+ return -EINVAL;
+
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - 12));
+}
+
+/*
+ * for abiv1 the 64bits args should be even th, So we need mov the advice
forward.
+ */
+SYSCALL_DEFINE4(csky_fadvise64_64,
+ int, fd,
+ int, advice,
+ loff_t, offset,
+ loff_t, len)
+{
+ return ksys_fadvise64_64(fd, offset, len, advice);
+}
diff --git a/arch/cs
[PATCH V3 05/27] csky: System Call
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 69 +
arch/csky/include/asm/syscalls.h| 14
arch/csky/include/uapi/asm/unistd.h | 10 ++
arch/csky/kernel/syscall.c | 42 ++
arch/csky/kernel/syscall_table.c| 13 +++
5 files changed, 148 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..8966739
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,69 @@
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+}
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..c478830
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..6fc1448
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#define __ARCH_WANT_SYS_CLONE
+#include
+
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/csky/kernel/syscall.c b/arch/csky/kernel/syscall.c
new file mode 100644
index 000..3f38a28
--- /dev/null
+++ b/arch/csky/kernel/syscall.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
+{
+ struct thread_info *ti = task_thread_info(current);
+ struct pt_regs *reg = current_pt_regs();
+
+ reg->tls = addr;
+ ti->tp_value = addr;
+
+ return 0;
+}
+
+SYSCALL_DEFINE6(mmap2,
+ unsigned long, addr,
+ unsigned long, len,
+ unsigned long, prot,
+ unsigned long, flags,
+ unsigned long, fd,
+ off_t, offset)
+{
+ if (unlikely(offset & (~PAGE_MASK >> 12)))
+ return -EINVAL;
+
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - 12));
+}
+
+/*
+ * for abiv1 the 64bits args should be even th, So we need mov the advice
forward.
+ */
+SYSCALL_DEFINE4(csky_fadvise64_64,
+ int, fd,
+ int, advice,
+ loff_t, offset,
+ loff_t, len)
+{
+ return ksys_fadvise64_64(fd, offset, len, advice);
+}
diff --git a/arch/cs
[PATCH V3 12/27] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9eef4a1 --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 252 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->
[PATCH V3 12/27] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9eef4a1 --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 252 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->
[PATCH V3 14/27] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 398
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 669 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..821fca0
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+ return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memor
[PATCH V3 14/27] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 398
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 669 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..821fca0
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+ return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memor
[PATCH V3 19/27] dt-bindings: timer: gx6605s SOC timer
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
new file mode 100644
index 000..230a9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
@@ -0,0 +1,42 @@
+=
+gx6605s SOC Timer
+=
+
+The timer is used in gx6605s soc as system timer and the driver
+contain clk event and clk source.
+
+==
+timer node bindings definition
+==
+
+Description: Describes gx6605s SOC timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,gx6605s-timer"
+ - reg
+ Usage: required
+ Value type:
+ Definition: in soc from cpu view
+ - clocks
+ Usage: required
+ Value type: phandle + clock specifier cells
+ Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+
+Examples:
+-
+
+ timer0: timer@20a000 {
+ compatible = "csky,gx6605s-timer";
+ reg = <0x0020a000 0x400>;
+ clocks = <_apb_clk>;
+ interrupts = <10>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 19/27] dt-bindings: timer: gx6605s SOC timer
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
new file mode 100644
index 000..230a9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
@@ -0,0 +1,42 @@
+=
+gx6605s SOC Timer
+=
+
+The timer is used in gx6605s soc as system timer and the driver
+contain clk event and clk source.
+
+==
+timer node bindings definition
+==
+
+Description: Describes gx6605s SOC timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,gx6605s-timer"
+ - reg
+ Usage: required
+ Value type:
+ Definition: in soc from cpu view
+ - clocks
+ Usage: required
+ Value type: phandle + clock specifier cells
+ Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+
+Examples:
+-
+
+ timer0: timer@20a000 {
+ compatible = "csky,gx6605s-timer";
+ reg = <0x0020a000 0x400>;
+ clocks = <_apb_clk>;
+ interrupts = <10>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 01/27] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 231 + arch/csky/Kconfig.debug| 14 ++ arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 10 ++ arch/csky/boot/Makefile| 24 arch/csky/boot/dts/Makefile| 13 ++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 69 ++ arch/csky/include/uapi/asm/Kbuild | 33 + arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 518 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..c6508b4 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,231 @@ +config CSKY + def_bool y + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_USE_BUILTIN_BSWAP + select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2 + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select DMA_NONCOHERENT_OPS + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_UCMPDI2 + select GENERIC_ALLOCATOR + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_C_RECORDMCOUNT + select HAVE_DMA_API_DEBUG + select HAVE_DMA_CONTIGUOUS + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_FPUV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP, CPU needs "ldex" instrcutions to atomic operations. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause an illegal + instruction exception. + In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config MMU + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TIME_LOW_RES + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config CPU_TLB_SIZE + int + default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if (CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if (CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if (CPU_CK610) + default "5" if (CPU_CK807 || CPU_CK810) + default "6" if (CPU_CK860) + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY
[PATCH V3 07/27] csky: MMU and page table management
- abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
- abiv2 CPUs are all PIPT cache and they could support highmem.
Here is our memory layout plan:
Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB)
Pkmap: 0xff80 – 0xffc0 (4 MB)
Vmalloc : 0xf020 – 0xff00 (238 MB)
Lowmem : 0x8000 – 0xc000 (1GB)
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
page-table for it.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/ckmmu.h| 74
arch/csky/abiv1/inc/abi/page.h | 26 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 36
arch/csky/abiv1/mmap.c | 65 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 87 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 37
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 26 +++
arch/csky/include/asm/highmem.h| 50 ++
arch/csky/include/asm/mmu.h| 11 ++
arch/csky/include/asm/page.h | 101 +++
arch/csky/include/asm/pgalloc.h| 108
arch/csky/include/asm/pgtable.h| 299 +
arch/csky/include/asm/segment.h| 18 ++
arch/csky/include/asm/shmparam.h | 10 ++
arch/csky/mm/dma-mapping.c | 254
arch/csky/mm/highmem.c | 195 +
arch/csky/mm/init.c| 118 +
arch/csky/mm/ioremap.c | 48 ++
20 files changed, 1587 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..5954ebb
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void tlb_invalid_indexed(void)
+{
+ cpwcr("cpcr8", 0x0200);
+}
+
+static inline void setup_pgd(unsigned long pgd, bool kernel)
+{
+ cpwcr("cpcr29", pgd);
+}
+
+static inline unsigned long get_pgd(void)
+{
+ return cprcr("cpcr29");
+}
+#endif /* __ASM_CSKY_CKMMUV1_H */
diff --git a/arch/csky/abiv1/inc/abi/page.h b/arch/csky/abiv1/inc/abi/page.h
new file mode 100644
index 000..b0d2122
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/page.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+extern unsigned long shm_align_mask;
+extern void flush_dcache_page(struct page *);
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+ unsigned long addr2)
+{
+ return (addr1 ^ addr2) & shm_align_mask;
+}
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
[PATCH V3 23/27] clocksource: add gx6605s SOC system timer
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren
---
drivers/clocksource/timer-gx6605s.c | 150
1 file changed, 150 insertions(+)
create mode 100644 drivers/clocksource/timer-gx6605s.c
diff --git a/drivers/clocksource/timer-gx6605s.c
b/drivers/clocksource/timer-gx6605s.c
new file mode 100644
index 000..10194c9
--- /dev/null
+++ b/drivers/clocksource/timer-gx6605s.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define CLKSRC_OFFSET 0x40
+
+#define TIMER_STATUS 0x00
+#define TIMER_VALUE0x04
+#define TIMER_CONTRL 0x10
+#define TIMER_CONFIG 0x20
+#define TIMER_DIV 0x24
+#define TIMER_INI 0x28
+
+#define GX6605S_STATUS_CLR BIT(0)
+#define GX6605S_CONTRL_RST BIT(0)
+#define GX6605S_CONTRL_START BIT(1)
+#define GX6605S_CONFIG_EN BIT(0)
+#define GX6605S_CONFIG_IRQ_EN BIT(1)
+
+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
+{
+ struct clock_event_device *ce = (struct clock_event_device *) dev;
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* reset and stop counter */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* enable with irq and start */
+ writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, base +
TIMER_CONFIG);
+
+ return 0;
+}
+
+static int gx6605s_timer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* use reset to pause timer */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* config next timeout value */
+ writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ return 0;
+}
+
+static int gx6605s_timer_shutdown(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(0, base + TIMER_CONTRL);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = gx6605s_timer_shutdown,
+ .set_state_oneshot = gx6605s_timer_set_oneshot,
+ .set_next_event = gx6605s_timer_set_next_event,
+ .cpumask= cpu_possible_mask,
+ },
+ .of_irq = {
+ .handler= gx6605s_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace gx6605s_sched_clock_read(void)
+{
+ void __iomem *base;
+
+ base = timer_of_base() + CLKSRC_OFFSET;
+
+ return (u64) readl_relaxed(base + TIMER_VALUE);
+}
+
+static void gx6605s_clkevt_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ clockevents_config_and_register(, timer_of_rate(), 2,
ULONG_MAX);
+}
+
+static int gx6605s_clksrc_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_INI);
+
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
+
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate());
+
+ return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
timer_of_rate(),
+200, 32, clocksource_mmio_readl_up);
+}
+
+static int __init gx6605s_timer_init(struct device_node *np)
+{
+ int ret;
+
+ /*
+* The timer driver is for nationalchip gx6605s SOC and there are two
same timer
+* in gx6605s. We use one for clkevt and another for clksrc.
+*
+* The timer is mmio map to access, so we need give mmio addres in dts.
+*
+* It provides a 32bit countup timer and interrupt will be caused by
count-overflow.
+* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
+*
+* The counter at 0x0 offset is clock event.
+* The counter at 0x40 offset is clock source.
+
[PATCH V3 22/27] dt-bindings: interrupt-controller: C-SKY SMP intc
Signed-off-by: Guo Ren
---
.../bindings/interrupt-controller/csky,mpintc.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
new file mode 100644
index 000..49d1658
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
@@ -0,0 +1,40 @@
+===
+C-SKY Multi-processors Interrupt Controller
+===
+
+C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
+SMP soc, and it also could be used in non-SMP system.
+
+Interrupt number definition:
+
+ 0-15 : software irq, and we use 15 as our IPI_IRQ.
+ 16-31 : private irq, and we use 16 as the co-processor timer.
+ 31-1024: common irq for soc ip.
+
+=
+intc node bindings definition
+=
+
+ Description: Describes SMP interrupt controller
+
+ PROPERTIES
+
+- compatible
+ Usage: required
+Value type:
+Definition: must be "csky,mpintc"
+- interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller {
+ compatible = "csky,mpintc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
--
2.7.4
[PATCH V3 20/27] dt-bindings: timer: C-SKY Multi-processor timer
Signed-off-by: Guo Ren
---
.../devicetree/bindings/timer/csky,mptimer.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/csky,mptimer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt
b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
new file mode 100644
index 000..0d7369f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
@@ -0,0 +1,46 @@
+
+C-SKY Multi-processors Timer
+
+
+C-SKY multi-processors timer is designed for C-SKY SMP system and the
+regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
+
+ - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
+ - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
+ - PTIM_CCVR "cr<3, 14>" Current counter value reg.
+ - PTIM_LVR "cr<6, 14>" Window value reg to triger next event.
+
+==
+timer node bindings definition
+==
+
+Description: Describes SMP timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,mptimer"
+ - clocks
+ Usage: required
+ Value type:
+Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+- interrupt-parent:
+Usage: required
+ Value type:
+Definition: must be interrupt controller node
+
+Examples:
+-
+
+ timer: timer {
+ compatible = "csky,mptimer";
+ clocks = <_apb_clk>;
+ interrupts = <16>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 01/27] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 231 + arch/csky/Kconfig.debug| 14 ++ arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 10 ++ arch/csky/boot/Makefile| 24 arch/csky/boot/dts/Makefile| 13 ++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 69 ++ arch/csky/include/uapi/asm/Kbuild | 33 + arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 518 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..c6508b4 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,231 @@ +config CSKY + def_bool y + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_USE_BUILTIN_BSWAP + select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2 + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select DMA_NONCOHERENT_OPS + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_UCMPDI2 + select GENERIC_ALLOCATOR + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_C_RECORDMCOUNT + select HAVE_DMA_API_DEBUG + select HAVE_DMA_CONTIGUOUS + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_FPUV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP, CPU needs "ldex" instrcutions to atomic operations. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause an illegal + instruction exception. + In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config MMU + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TIME_LOW_RES + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config CPU_TLB_SIZE + int + default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if (CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if (CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if (CPU_CK610) + default "5" if (CPU_CK807 || CPU_CK810) + default "6" if (CPU_CK860) + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY
[PATCH V3 07/27] csky: MMU and page table management
- abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
- abiv2 CPUs are all PIPT cache and they could support highmem.
Here is our memory layout plan:
Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB)
Pkmap: 0xff80 – 0xffc0 (4 MB)
Vmalloc : 0xf020 – 0xff00 (238 MB)
Lowmem : 0x8000 – 0xc000 (1GB)
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
page-table for it.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/ckmmu.h| 74
arch/csky/abiv1/inc/abi/page.h | 26 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 36
arch/csky/abiv1/mmap.c | 65 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 87 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 37
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 26 +++
arch/csky/include/asm/highmem.h| 50 ++
arch/csky/include/asm/mmu.h| 11 ++
arch/csky/include/asm/page.h | 101 +++
arch/csky/include/asm/pgalloc.h| 108
arch/csky/include/asm/pgtable.h| 299 +
arch/csky/include/asm/segment.h| 18 ++
arch/csky/include/asm/shmparam.h | 10 ++
arch/csky/mm/dma-mapping.c | 254
arch/csky/mm/highmem.c | 195 +
arch/csky/mm/init.c| 118 +
arch/csky/mm/ioremap.c | 48 ++
20 files changed, 1587 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..5954ebb
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void tlb_invalid_indexed(void)
+{
+ cpwcr("cpcr8", 0x0200);
+}
+
+static inline void setup_pgd(unsigned long pgd, bool kernel)
+{
+ cpwcr("cpcr29", pgd);
+}
+
+static inline unsigned long get_pgd(void)
+{
+ return cprcr("cpcr29");
+}
+#endif /* __ASM_CSKY_CKMMUV1_H */
diff --git a/arch/csky/abiv1/inc/abi/page.h b/arch/csky/abiv1/inc/abi/page.h
new file mode 100644
index 000..b0d2122
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/page.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+extern unsigned long shm_align_mask;
+extern void flush_dcache_page(struct page *);
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+ unsigned long addr2)
+{
+ return (addr1 ^ addr2) & shm_align_mask;
+}
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
[PATCH V3 23/27] clocksource: add gx6605s SOC system timer
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren
---
drivers/clocksource/timer-gx6605s.c | 150
1 file changed, 150 insertions(+)
create mode 100644 drivers/clocksource/timer-gx6605s.c
diff --git a/drivers/clocksource/timer-gx6605s.c
b/drivers/clocksource/timer-gx6605s.c
new file mode 100644
index 000..10194c9
--- /dev/null
+++ b/drivers/clocksource/timer-gx6605s.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define CLKSRC_OFFSET 0x40
+
+#define TIMER_STATUS 0x00
+#define TIMER_VALUE0x04
+#define TIMER_CONTRL 0x10
+#define TIMER_CONFIG 0x20
+#define TIMER_DIV 0x24
+#define TIMER_INI 0x28
+
+#define GX6605S_STATUS_CLR BIT(0)
+#define GX6605S_CONTRL_RST BIT(0)
+#define GX6605S_CONTRL_START BIT(1)
+#define GX6605S_CONFIG_EN BIT(0)
+#define GX6605S_CONFIG_IRQ_EN BIT(1)
+
+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
+{
+ struct clock_event_device *ce = (struct clock_event_device *) dev;
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* reset and stop counter */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* enable with irq and start */
+ writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, base +
TIMER_CONFIG);
+
+ return 0;
+}
+
+static int gx6605s_timer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* use reset to pause timer */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* config next timeout value */
+ writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ return 0;
+}
+
+static int gx6605s_timer_shutdown(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(0, base + TIMER_CONTRL);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = gx6605s_timer_shutdown,
+ .set_state_oneshot = gx6605s_timer_set_oneshot,
+ .set_next_event = gx6605s_timer_set_next_event,
+ .cpumask= cpu_possible_mask,
+ },
+ .of_irq = {
+ .handler= gx6605s_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace gx6605s_sched_clock_read(void)
+{
+ void __iomem *base;
+
+ base = timer_of_base() + CLKSRC_OFFSET;
+
+ return (u64) readl_relaxed(base + TIMER_VALUE);
+}
+
+static void gx6605s_clkevt_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ clockevents_config_and_register(, timer_of_rate(), 2,
ULONG_MAX);
+}
+
+static int gx6605s_clksrc_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_INI);
+
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
+
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate());
+
+ return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
timer_of_rate(),
+200, 32, clocksource_mmio_readl_up);
+}
+
+static int __init gx6605s_timer_init(struct device_node *np)
+{
+ int ret;
+
+ /*
+* The timer driver is for nationalchip gx6605s SOC and there are two
same timer
+* in gx6605s. We use one for clkevt and another for clksrc.
+*
+* The timer is mmio map to access, so we need give mmio addres in dts.
+*
+* It provides a 32bit countup timer and interrupt will be caused by
count-overflow.
+* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
+*
+* The counter at 0x0 offset is clock event.
+* The counter at 0x40 offset is clock source.
+
[PATCH V3 22/27] dt-bindings: interrupt-controller: C-SKY SMP intc
Signed-off-by: Guo Ren
---
.../bindings/interrupt-controller/csky,mpintc.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
new file mode 100644
index 000..49d1658
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
@@ -0,0 +1,40 @@
+===
+C-SKY Multi-processors Interrupt Controller
+===
+
+C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
+SMP soc, and it also could be used in non-SMP system.
+
+Interrupt number definition:
+
+ 0-15 : software irq, and we use 15 as our IPI_IRQ.
+ 16-31 : private irq, and we use 16 as the co-processor timer.
+ 31-1024: common irq for soc ip.
+
+=
+intc node bindings definition
+=
+
+ Description: Describes SMP interrupt controller
+
+ PROPERTIES
+
+- compatible
+ Usage: required
+Value type:
+Definition: must be "csky,mpintc"
+- interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller {
+ compatible = "csky,mpintc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
--
2.7.4
[PATCH V3 20/27] dt-bindings: timer: C-SKY Multi-processor timer
Signed-off-by: Guo Ren
---
.../devicetree/bindings/timer/csky,mptimer.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/csky,mptimer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt
b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
new file mode 100644
index 000..0d7369f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
@@ -0,0 +1,46 @@
+
+C-SKY Multi-processors Timer
+
+
+C-SKY multi-processors timer is designed for C-SKY SMP system and the
+regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
+
+ - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
+ - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
+ - PTIM_CCVR "cr<3, 14>" Current counter value reg.
+ - PTIM_LVR "cr<6, 14>" Window value reg to triger next event.
+
+==
+timer node bindings definition
+==
+
+Description: Describes SMP timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,mptimer"
+ - clocks
+ Usage: required
+ Value type:
+Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+- interrupt-parent:
+Usage: required
+ Value type:
+Definition: must be interrupt controller node
+
+Examples:
+-
+
+ timer: timer {
+ compatible = "csky,mptimer";
+ clocks = <_apb_clk>;
+ interrupts = <16>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 04/27] csky: Exception handling
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 331 +
arch/csky/abiv1/inc/abi/entry.h | 159
arch/csky/abiv2/inc/abi/entry.h | 157
arch/csky/include/asm/traps.h | 39
arch/csky/include/asm/unistd.h | 3 +
arch/csky/kernel/cpu-probe.c| 78
arch/csky/kernel/entry.S| 396
arch/csky/kernel/traps.c| 168 +
arch/csky/mm/fault.c| 220 ++
9 files changed, 1551 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..b8764d2
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count = 0;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "ldb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static volatile int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "stb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx
[PATCH V3 06/27] csky: Cache and TLB routines
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 50
arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++
arch/csky/abiv1/inc/abi/tlb.h | 11 ++
arch/csky/abiv2/cacheflush.c | 54 +
arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++
arch/csky/abiv2/inc/abi/tlb.h | 12 ++
arch/csky/include/asm/barrier.h | 45 +++
arch/csky/include/asm/cache.h | 28 +
arch/csky/include/asm/cacheflush.h| 8 ++
arch/csky/include/asm/io.h| 23
arch/csky/include/asm/tlb.h | 19 +++
arch/csky/include/asm/tlbflush.h | 22
arch/csky/include/uapi/asm/cachectl.h | 13 +++
arch/csky/mm/cachev1.c| 126
arch/csky/mm/cachev2.c| 79 +
arch/csky/mm/syscache.c | 28 +
arch/csky/mm/tlb.c| 214 ++
17 files changed, 811 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv1/inc/abi/tlb.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/inc/abi/tlb.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..4c6fede
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wb_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t
*pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..ba5071e
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma,page,pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+#define flush_cache_range(mm,start,end)cache_wbinv_range(start, end)
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+#define flush_icache_user_range(vma,pg,adr,len)cache_wbinv_range(adr,
adr + len)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+ icache_inv_all(); \
+}while(0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+}while(0)
+
+#define flush_dcache_mmap_lock(mapping)do{}while(0)
+#define flush_dcache_mmap_unlock(mapping) do{}while(0)
+
+#endif /* __ABI_CSKY_CACHE
[PATCH V3 04/27] csky: Exception handling
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 331 +
arch/csky/abiv1/inc/abi/entry.h | 159
arch/csky/abiv2/inc/abi/entry.h | 157
arch/csky/include/asm/traps.h | 39
arch/csky/include/asm/unistd.h | 3 +
arch/csky/kernel/cpu-probe.c| 78
arch/csky/kernel/entry.S| 396
arch/csky/kernel/traps.c| 168 +
arch/csky/mm/fault.c| 220 ++
9 files changed, 1551 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..b8764d2
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count = 0;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "ldb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static volatile int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "stb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx
[PATCH V3 06/27] csky: Cache and TLB routines
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 50
arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++
arch/csky/abiv1/inc/abi/tlb.h | 11 ++
arch/csky/abiv2/cacheflush.c | 54 +
arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++
arch/csky/abiv2/inc/abi/tlb.h | 12 ++
arch/csky/include/asm/barrier.h | 45 +++
arch/csky/include/asm/cache.h | 28 +
arch/csky/include/asm/cacheflush.h| 8 ++
arch/csky/include/asm/io.h| 23
arch/csky/include/asm/tlb.h | 19 +++
arch/csky/include/asm/tlbflush.h | 22
arch/csky/include/uapi/asm/cachectl.h | 13 +++
arch/csky/mm/cachev1.c| 126
arch/csky/mm/cachev2.c| 79 +
arch/csky/mm/syscache.c | 28 +
arch/csky/mm/tlb.c| 214 ++
17 files changed, 811 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv1/inc/abi/tlb.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/inc/abi/tlb.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..4c6fede
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wb_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t
*pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..ba5071e
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma,page,pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+#define flush_cache_range(mm,start,end)cache_wbinv_range(start, end)
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+#define flush_icache_user_range(vma,pg,adr,len)cache_wbinv_range(adr,
adr + len)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+ icache_inv_all(); \
+}while(0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+}while(0)
+
+#define flush_dcache_mmap_lock(mapping)do{}while(0)
+#define flush_dcache_mmap_unlock(mapping) do{}while(0)
+
+#endif /* __ABI_CSKY_CACHE
[PATCH V3 03/27] csky: Kernel booting
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 78 +
arch/csky/kernel/setup.c | 150 +
arch/csky/kernel/vmlinux.lds.S | 64 ++
3 files changed, 292 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..80bb9c6
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ SETUP_MMU a3
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.alls
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ SETUP_MMU a3
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..44606fa
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ if (max_low_pfn == 0)
+ max_low_pfn = max_pfn;
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
min_low_pfn;
+ zhole_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
+ if(memblock.memory.cnt > 1) {
+ size = PFN_DOWN(memblock_size_of_REG1());
+ highstart_pfn = PFN_DOWN(memblock_start_of_REG1());
+ } else {
+ size = max_pfn - min_low_pfn - PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ highstart_pfn = min_low_pfn + PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ }
+
+ if (size > 0)
+ zone_size[ZONE_HIGHMEM] = size;
+
+ highend_pfn = max_pfn;
+#endif
+
[PATCH V3 03/27] csky: Kernel booting
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 78 +
arch/csky/kernel/setup.c | 150 +
arch/csky/kernel/vmlinux.lds.S | 64 ++
3 files changed, 292 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..80bb9c6
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ SETUP_MMU a3
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.alls
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ SETUP_MMU a3
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..44606fa
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ if (max_low_pfn == 0)
+ max_low_pfn = max_pfn;
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
min_low_pfn;
+ zhole_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
+ if(memblock.memory.cnt > 1) {
+ size = PFN_DOWN(memblock_size_of_REG1());
+ highstart_pfn = PFN_DOWN(memblock_start_of_REG1());
+ } else {
+ size = max_pfn - min_low_pfn - PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ highstart_pfn = min_low_pfn + PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ }
+
+ if (size > 0)
+ zone_size[ZONE_HIGHMEM] = size;
+
+ highend_pfn = max_pfn;
+#endif
+
[PATCH V3 18/27] dt-bindings: csky CPU Bindings
Signed-off-by: Guo Ren
---
Documentation/devicetree/bindings/csky/cpus.txt | 70 +
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/csky/cpus.txt
diff --git a/Documentation/devicetree/bindings/csky/cpus.txt
b/Documentation/devicetree/bindings/csky/cpus.txt
new file mode 100644
index 000..ee3901d
--- /dev/null
+++ b/Documentation/devicetree/bindings/csky/cpus.txt
@@ -0,0 +1,70 @@
+==
+C-SKY CPU Bindings
+==
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Only SMP system need to care about the cpus node and single processor
+needn't define cpus node at all.
+
+=
+cpus and cpu node bindings definition
+=
+
+- cpus node
+
+Description: Container of cpu nodes
+
+The node name must be "cpus".
+
+A cpus node must define the following properties:
+
+- #address-cells
+Usage: required
+Value type:
+Definition: must be set to 1
+- #size-cells
+Usage: required
+Value type:
+Definition: must be set to 0
+
+- cpu node
+
+Description: Describes one of SMP cores
+
+PROPERTIES
+
+- device_type
+Usage: required
+Value type:
+Definition: must be "cpu"
+- reg
+Usage: required
+Value type:
+Definition: CPU index
+- status:
+Usage: required
+Value type:
+Definition: "ok" means enable the cpu-core
+"disabled" means disable the cpu-core
+
+Example:
+
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "ok";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "ok";
+ };
+ };
--
2.7.4
[PATCH V3 18/27] dt-bindings: csky CPU Bindings
Signed-off-by: Guo Ren
---
Documentation/devicetree/bindings/csky/cpus.txt | 70 +
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/csky/cpus.txt
diff --git a/Documentation/devicetree/bindings/csky/cpus.txt
b/Documentation/devicetree/bindings/csky/cpus.txt
new file mode 100644
index 000..ee3901d
--- /dev/null
+++ b/Documentation/devicetree/bindings/csky/cpus.txt
@@ -0,0 +1,70 @@
+==
+C-SKY CPU Bindings
+==
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Only SMP system need to care about the cpus node and single processor
+needn't define cpus node at all.
+
+=
+cpus and cpu node bindings definition
+=
+
+- cpus node
+
+Description: Container of cpu nodes
+
+The node name must be "cpus".
+
+A cpus node must define the following properties:
+
+- #address-cells
+Usage: required
+Value type:
+Definition: must be set to 1
+- #size-cells
+Usage: required
+Value type:
+Definition: must be set to 0
+
+- cpu node
+
+Description: Describes one of SMP cores
+
+PROPERTIES
+
+- device_type
+Usage: required
+Value type:
+Definition: must be "cpu"
+- reg
+Usage: required
+Value type:
+Definition: CPU index
+- status:
+Usage: required
+Value type:
+Definition: "ok" means enable the cpu-core
+"disabled" means disable the cpu-core
+
+Example:
+
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "ok";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "ok";
+ };
+ };
--
2.7.4
[PATCH V4 00/27] C-SKY(csky) Linux Kernel Port
mp; fpr_set f57266f csky: bugfix fpu_fpe_helper excute mtcr mfcr. c676669 csky: bugfix ave is default enable on reset. d40d34d csky: remove unused sc_mask in sigcontext.h. 274b7a2 csky: redesign the signal's api 7501771 csky: bugfix forget restore usp. 923e2ca csky: re-struct the pt_regs for regset. 2a1e499 csky: fixup config. ada81ec csky: bugfix abiv1 compile error. e34acb9 csky: bugfix abiv1 couldn't support -mno-stack-size. ec53560 csky: change irq map, reserve soft_irq_irq space. c7576f7 csky: bugfix modpost warning with -mno-stack-size c8ff9d4 csky: support csky mp timer alpha version. deabaaf csky: update .gitignore. 574815c csky: bugfix compile error with abiv1 in 4.15 0b426a7 csky: bugfix format of cpu verion id. 083435f csky: irq-csky-v2 alpha init. 21209e5 csky: add .gitignore 73e19b4 csky: remove FMFS_FPU_REGS/FMTS_FPU_REGS 07e8fac csky: add fpu regset in ptrace.c cac779d csky: add CSKY_VECIRQ_LEGENCY for SOC bug. 54bab1d csky: move usp into pt_regs. b167422 csky: support regset for ptrace. a098d4c csky: remove ARCH_WANT_IPC_PARSE_VERSION fe61a84 csky: add timer-of support. 27702e2 csky: bugfix boot error. ebe3edb csky: bugfix gx6605s boot failed - add __HEAD to head.section for head.S - move INIT_SECTION together to fix compile warning. 7138cae csky: coding convension for timer-nationalchip.c fa7f9bb csky: use ffs instead of fls. ddc9e81 csky: change to generic irq chip for irq-csky.c e9be8b9 irqchip: add generic irq chip for irq-nationalchip 2ee83fe csky: add set_handle_irq(), ref from openrisc & arm. 74181d6 csky: use irq_domain_add_linear instead of leagcy. fa45ae4 csky: bugfix setup stroge order for uncached. eb8030f csky: add HIGHMEM config in Kconfig 4f983d4 csky: remove "default n" in Kconfig 2467575 csky: use asm-generic/signal.h 77438e5 csky: coding conventions for irq.c 2e4a2b4 csky: optimize the cache flush ops. 96e1c58 csky: add CONFIG_CPU_ASID_BITS. 9339666 csky: add cprcr() cpwcr() for abiv1 ff05be4 csky: add THREAD_SHIFT define in asm/page.h 52ab022 csky: add mfcr() mtcr() in asm/reg_ops.h bdcd8f3 csky: revert back Kconfig select. 590c7e6 csky: bugfix compile error with CONFIG_AUDIT 1989292 csky: revert some back with cleanup unistd.h f1454fe csky: cleanup unistd.h 5d2985f csky: cleanup Kconfig and Makefile. 423d97e csky: cancel subdirectories cae2af4 csky: use asm-generic/fcntl.h Guo Ren (27): csky: Build infrastructure csky: defconfig csky: Kernel booting csky: Exception handling csky: System Call csky: Cache and TLB routines csky: MMU and page table management csky: Process management and Signal csky: VDSO and rt_sigreturn csky: IRQ handling csky: Atomic operations csky: ELF and module probe csky: Library functions csky: User access csky: Debug and Ptrace GDB csky: SMP support csky: Misc headers dt-bindings: csky CPU Bindings dt-bindings: timer: gx6605s SOC timer dt-bindings: timer: C-SKY Multi-processor timer dt-bindings: interrupt-controller: C-SKY APB intc dt-bindings: interrupt-controller: C-SKY SMP intc clocksource: add gx6605s SOC system timer clocksource: add C-SKY SMP timer clocksource: add C-SKY timers' build infrastructure irqchip: add C-SKY irqchip drivers dt-bindings: Add vendor prefix for csky Documentation/devicetree/bindings/csky/cpus.txt| 70 .../interrupt-controller/csky,apb-intc.txt | 45 +++ .../bindings/interrupt-controller/csky,mpintc.txt | 40 +++ .../bindings/timer/csky,gx6605s-timer.txt | 42 +++ .../devicetree/bindings/timer/csky,mptimer.txt | 46 +++ .../devicetree/bindings/vendor-prefixes.txt| 1 + arch/csky/Kconfig | 231 arch/csky/Kconfig.debug| 14 + arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 + arch/csky/abiv1/alignment.c| 331 + arch/csky/abiv1/bswapdi.c | 18 + arch/csky/abiv1/bswapsi.c | 14 + arch/csky/abiv1/cacheflush.c | 50 +++ arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++ arch/csky/abiv1/inc/abi/ckmmu.h| 74 arch/csky/abiv1/inc/abi/entry.h| 159 arch/csky/abiv1/inc/abi/page.h | 26 ++ arch/csky/abiv1/inc/abi/pgtable-bits.h | 36 ++ arch/csky/abiv1/inc/abi/reg_ops.h | 26 ++ arch/csky/abiv1/inc/abi/regdef.h | 25 ++ arch/csky/abiv1/inc/abi/string.h | 13 + arch/csky/abiv1/inc/abi/tlb.h | 11 + arch/csky/abiv1/inc/abi/vdso.h | 17 + arch/csky/abiv1/memcpy.S | 344 ++ arch/csky/abiv1/memset.c | 37 ++ arch/csky/abiv1/mmap.c | 65 arch/csky/abiv1/strksyms.c
[PATCH V3 02/27] csky: defconfig
Signed-off-by: Guo Ren --- arch/csky/configs/defconfig | 61 + 1 file changed, 61 insertions(+) create mode 100644 arch/csky/configs/defconfig diff --git a/arch/csky/configs/defconfig b/arch/csky/configs/defconfig new file mode 100644 index 000..7ef4289 --- /dev/null +++ b/arch/csky/configs/defconfig @@ -0,0 +1,61 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="csky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_CPU_CK807=y +CONFIG_CPU_HAS_FPU=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_CSKY_MPTIMER=y +CONFIG_GX6605S_TIMER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y -- 2.7.4
[PATCH V4 00/27] C-SKY(csky) Linux Kernel Port
mp; fpr_set f57266f csky: bugfix fpu_fpe_helper excute mtcr mfcr. c676669 csky: bugfix ave is default enable on reset. d40d34d csky: remove unused sc_mask in sigcontext.h. 274b7a2 csky: redesign the signal's api 7501771 csky: bugfix forget restore usp. 923e2ca csky: re-struct the pt_regs for regset. 2a1e499 csky: fixup config. ada81ec csky: bugfix abiv1 compile error. e34acb9 csky: bugfix abiv1 couldn't support -mno-stack-size. ec53560 csky: change irq map, reserve soft_irq_irq space. c7576f7 csky: bugfix modpost warning with -mno-stack-size c8ff9d4 csky: support csky mp timer alpha version. deabaaf csky: update .gitignore. 574815c csky: bugfix compile error with abiv1 in 4.15 0b426a7 csky: bugfix format of cpu verion id. 083435f csky: irq-csky-v2 alpha init. 21209e5 csky: add .gitignore 73e19b4 csky: remove FMFS_FPU_REGS/FMTS_FPU_REGS 07e8fac csky: add fpu regset in ptrace.c cac779d csky: add CSKY_VECIRQ_LEGENCY for SOC bug. 54bab1d csky: move usp into pt_regs. b167422 csky: support regset for ptrace. a098d4c csky: remove ARCH_WANT_IPC_PARSE_VERSION fe61a84 csky: add timer-of support. 27702e2 csky: bugfix boot error. ebe3edb csky: bugfix gx6605s boot failed - add __HEAD to head.section for head.S - move INIT_SECTION together to fix compile warning. 7138cae csky: coding convension for timer-nationalchip.c fa7f9bb csky: use ffs instead of fls. ddc9e81 csky: change to generic irq chip for irq-csky.c e9be8b9 irqchip: add generic irq chip for irq-nationalchip 2ee83fe csky: add set_handle_irq(), ref from openrisc & arm. 74181d6 csky: use irq_domain_add_linear instead of leagcy. fa45ae4 csky: bugfix setup stroge order for uncached. eb8030f csky: add HIGHMEM config in Kconfig 4f983d4 csky: remove "default n" in Kconfig 2467575 csky: use asm-generic/signal.h 77438e5 csky: coding conventions for irq.c 2e4a2b4 csky: optimize the cache flush ops. 96e1c58 csky: add CONFIG_CPU_ASID_BITS. 9339666 csky: add cprcr() cpwcr() for abiv1 ff05be4 csky: add THREAD_SHIFT define in asm/page.h 52ab022 csky: add mfcr() mtcr() in asm/reg_ops.h bdcd8f3 csky: revert back Kconfig select. 590c7e6 csky: bugfix compile error with CONFIG_AUDIT 1989292 csky: revert some back with cleanup unistd.h f1454fe csky: cleanup unistd.h 5d2985f csky: cleanup Kconfig and Makefile. 423d97e csky: cancel subdirectories cae2af4 csky: use asm-generic/fcntl.h Guo Ren (27): csky: Build infrastructure csky: defconfig csky: Kernel booting csky: Exception handling csky: System Call csky: Cache and TLB routines csky: MMU and page table management csky: Process management and Signal csky: VDSO and rt_sigreturn csky: IRQ handling csky: Atomic operations csky: ELF and module probe csky: Library functions csky: User access csky: Debug and Ptrace GDB csky: SMP support csky: Misc headers dt-bindings: csky CPU Bindings dt-bindings: timer: gx6605s SOC timer dt-bindings: timer: C-SKY Multi-processor timer dt-bindings: interrupt-controller: C-SKY APB intc dt-bindings: interrupt-controller: C-SKY SMP intc clocksource: add gx6605s SOC system timer clocksource: add C-SKY SMP timer clocksource: add C-SKY timers' build infrastructure irqchip: add C-SKY irqchip drivers dt-bindings: Add vendor prefix for csky Documentation/devicetree/bindings/csky/cpus.txt| 70 .../interrupt-controller/csky,apb-intc.txt | 45 +++ .../bindings/interrupt-controller/csky,mpintc.txt | 40 +++ .../bindings/timer/csky,gx6605s-timer.txt | 42 +++ .../devicetree/bindings/timer/csky,mptimer.txt | 46 +++ .../devicetree/bindings/vendor-prefixes.txt| 1 + arch/csky/Kconfig | 231 arch/csky/Kconfig.debug| 14 + arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 + arch/csky/abiv1/alignment.c| 331 + arch/csky/abiv1/bswapdi.c | 18 + arch/csky/abiv1/bswapsi.c | 14 + arch/csky/abiv1/cacheflush.c | 50 +++ arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++ arch/csky/abiv1/inc/abi/ckmmu.h| 74 arch/csky/abiv1/inc/abi/entry.h| 159 arch/csky/abiv1/inc/abi/page.h | 26 ++ arch/csky/abiv1/inc/abi/pgtable-bits.h | 36 ++ arch/csky/abiv1/inc/abi/reg_ops.h | 26 ++ arch/csky/abiv1/inc/abi/regdef.h | 25 ++ arch/csky/abiv1/inc/abi/string.h | 13 + arch/csky/abiv1/inc/abi/tlb.h | 11 + arch/csky/abiv1/inc/abi/vdso.h | 17 + arch/csky/abiv1/memcpy.S | 344 ++ arch/csky/abiv1/memset.c | 37 ++ arch/csky/abiv1/mmap.c | 65 arch/csky/abiv1/strksyms.c
[PATCH V3 02/27] csky: defconfig
Signed-off-by: Guo Ren --- arch/csky/configs/defconfig | 61 + 1 file changed, 61 insertions(+) create mode 100644 arch/csky/configs/defconfig diff --git a/arch/csky/configs/defconfig b/arch/csky/configs/defconfig new file mode 100644 index 000..7ef4289 --- /dev/null +++ b/arch/csky/configs/defconfig @@ -0,0 +1,61 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="csky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_CPU_CK807=y +CONFIG_CPU_HAS_FPU=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_CSKY_MPTIMER=y +CONFIG_GX6605S_TIMER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y -- 2.7.4
[PATCH V3 13/27] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 28
arch/csky/abiv2/memcmp.S | 151 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memcpy.c | 40 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 29
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/platform.c | 17 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 40 +
21 files changed, 1482 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..6e26b7e
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..60d4fc4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
[PATCH V3 13/27] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 28
arch/csky/abiv2/memcmp.S | 151 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memcpy.c | 40 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 29
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/platform.c | 17 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 40 +
21 files changed, 1482 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..6e26b7e
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..60d4fc4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
Re: [PATCH V3 10/26] csky: IRQ handling
On Thu, Sep 06, 2018 at 03:39:01PM +0200, Thomas Gleixner wrote:
> On Wed, 5 Sep 2018, Guo Ren wrote:
>
> > +static void (*handle_arch_irq)(struct pt_regs *regs) = NULL;
> > +
> > +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
> > +{
> > + if (handle_arch_irq)
> > + return;
> > +
> > + handle_arch_irq = handle_irq;
> > +}
>
> Please don't introduce yet another variant of that. Please use
> CONFIG_GENERIC_IRQ_MULTI_HANDLER which provides that in the generic code.
Ok.
>
> Btw, some of your patches have tab vs. space inconsistencies, e.g.
>
> +siginfo_t info;
> + int fault;
> + unsigned long address = mmu_meh & PAGE_MASK
Thx, I'll re-check.
Best Regards
Guo Ren
Re: [PATCH V3 10/26] csky: IRQ handling
On Thu, Sep 06, 2018 at 03:39:01PM +0200, Thomas Gleixner wrote:
> On Wed, 5 Sep 2018, Guo Ren wrote:
>
> > +static void (*handle_arch_irq)(struct pt_regs *regs) = NULL;
> > +
> > +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
> > +{
> > + if (handle_arch_irq)
> > + return;
> > +
> > + handle_arch_irq = handle_irq;
> > +}
>
> Please don't introduce yet another variant of that. Please use
> CONFIG_GENERIC_IRQ_MULTI_HANDLER which provides that in the generic code.
Ok.
>
> Btw, some of your patches have tab vs. space inconsistencies, e.g.
>
> +siginfo_t info;
> + int fault;
> + unsigned long address = mmu_meh & PAGE_MASK
Thx, I'll re-check.
Best Regards
Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 04:13:35PM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 2:55 PM Guo Ren wrote: > > > > On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > > > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > Similarly, an MMIO read may be used to see if a DMA has completed > > > and the device register tells you that the DMA has left the device, > > > but without a barrier, the CPU may have prefetched the DMA > > > data while waiting for the MMIO-read to complete. The __io_ar() > > > barrier() in asm-generic/io.h prevents the compiler from reordering > > > the two reads, but if an weakly ordered read (in coherent DMA buffer) > > > can bypass a strongly ordered read (MMIO), then it's still still > > > broken. > > __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So > > I got rmb() here not barrier(). > > > > Only __io_br() is barrier(). > > Ah right, I misremembered the defaults. It's probably ok then. Thx for the review and comments. These let me re-consider the mmio issues and help to improve the csky asm/io.h in future. > > > > > > - How does endianess work? Are there any buses that flip bytes around > > > > > when running big-endian, or do you always do that in software? > > > > Currently we only support little-endian and soc will follow it. > > > > > > Ok, that makes it easier. If you think that you won't even need big-endian > > > support in the long run, you could also remove your asm/byteorder.h > > > header. If you're not sure, it doesn't hurt to keep it of course. > > Em... I'm not sure, so let me keep it for a while. > > Ok. I think overall the trend is to be little-endian only for most > architectures: powerpc64 moved from big-endian only to little-endian > by default, ARM rarely uses big-endian (basically only for legacy > applications ported from BE MIPS or ppc), and all new architectures > we added in the last years are little-endian (OpenRISC being the > main exception). Good news, I really don't want to support big-endian and it makes CI double. Best Regards Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 04:13:35PM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 2:55 PM Guo Ren wrote: > > > > On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > > > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > Similarly, an MMIO read may be used to see if a DMA has completed > > > and the device register tells you that the DMA has left the device, > > > but without a barrier, the CPU may have prefetched the DMA > > > data while waiting for the MMIO-read to complete. The __io_ar() > > > barrier() in asm-generic/io.h prevents the compiler from reordering > > > the two reads, but if an weakly ordered read (in coherent DMA buffer) > > > can bypass a strongly ordered read (MMIO), then it's still still > > > broken. > > __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So > > I got rmb() here not barrier(). > > > > Only __io_br() is barrier(). > > Ah right, I misremembered the defaults. It's probably ok then. Thx for the review and comments. These let me re-consider the mmio issues and help to improve the csky asm/io.h in future. > > > > > > - How does endianess work? Are there any buses that flip bytes around > > > > > when running big-endian, or do you always do that in software? > > > > Currently we only support little-endian and soc will follow it. > > > > > > Ok, that makes it easier. If you think that you won't even need big-endian > > > support in the long run, you could also remove your asm/byteorder.h > > > header. If you're not sure, it doesn't hurt to keep it of course. > > Em... I'm not sure, so let me keep it for a while. > > Ok. I think overall the trend is to be little-endian only for most > architectures: powerpc64 moved from big-endian only to little-endian > by default, ARM rarely uses big-endian (basically only for legacy > applications ported from BE MIPS or ppc), and all new architectures > we added in the last years are little-endian (OpenRISC being the > main exception). Good news, I really don't want to support big-endian and it makes CI double. Best Regards Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Fri, Sep 07, 2018 at 10:13:13AM -0500, Rob Herring wrote:
> On Thu, Sep 6, 2018 at 8:05 AM Arnd Bergmann wrote:
> >
> > On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> > >
> > > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > > >
> > > > > Signed-off-by: Guo Ren
> > > > > +
> > > > > + intc: interrupt-controller {
> > > >
> > > > Needs a unit-address.
> > > Ok, change it to:
> > > intc: interrupt-controller@0x0050 {
> >
> > The unit address has no leading 0x or leading zeroes, so
> > interrupt-controller@500000
>
> Please build your dts files with W=12 and it will tell you this and
> other errors. And then update any examples based on that.
Got it, thx for the tip.
Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Fri, Sep 07, 2018 at 10:13:13AM -0500, Rob Herring wrote:
> On Thu, Sep 6, 2018 at 8:05 AM Arnd Bergmann wrote:
> >
> > On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> > >
> > > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > > >
> > > > > Signed-off-by: Guo Ren
> > > > > +
> > > > > + intc: interrupt-controller {
> > > >
> > > > Needs a unit-address.
> > > Ok, change it to:
> > > intc: interrupt-controller@0x0050 {
> >
> > The unit address has no leading 0x or leading zeroes, so
> > interrupt-controller@500000
>
> Please build your dts files with W=12 and it will tell you this and
> other errors. And then update any examples based on that.
Got it, thx for the tip.
Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > > > Can you describe how C-Sky hardware implements MMIO? > > Our mmio is uncachable and strong-order address, so there is no need > > barriers for access these io addr. > > > > #define ioremap_wc ioremap_nocache > > #define ioremap_wt ioremap_nocache > > > > Current ioremap_wc and ioremap_wt implementation are too simple and > > we'll improve it in future. > > > > > In particular: > > > > > > - Is a read from uncached memory always serialized with DMA, and with > > > other CPUs doing MMIO access to a different address? > > CPU use ld.w to get data from uncached strong order memory. > > Other CPUs use the same mmio vaddr to access the uncachable strong order > > memory paddr. > > Ok, but what about the DMA? The most common requirement for > serialization here is with a DMA transfer, where you first write > into a buffer in memory, then write to an MMIO register to trigger > a DMA-load, and then the device reads the data from memory. > Without a barrier before the MMIO, the data may still be in a > store queue of the CPU, and the DMA gets stale data. > > Similarly, an MMIO read may be used to see if a DMA has completed > and the device register tells you that the DMA has left the device, > but without a barrier, the CPU may have prefetched the DMA > data while waiting for the MMIO-read to complete. The __io_ar() > barrier() in asm-generic/io.h prevents the compiler from reordering > the two reads, but if an weakly ordered read (in coherent DMA buffer) > can bypass a strongly ordered read (MMIO), then it's still still > broken. __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So I got rmb() here not barrier(). Only __io_br() is barrier(). > > > - How does endianess work? Are there any buses that flip bytes around > > > when running big-endian, or do you always do that in software? > > Currently we only support little-endian and soc will follow it. > > Ok, that makes it easier. If you think that you won't even need big-endian > support in the long run, you could also remove your asm/byteorder.h > header. If you're not sure, it doesn't hurt to keep it of course. Em... I'm not sure, so let me keep it for a while. Best Regards Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > > > Can you describe how C-Sky hardware implements MMIO? > > Our mmio is uncachable and strong-order address, so there is no need > > barriers for access these io addr. > > > > #define ioremap_wc ioremap_nocache > > #define ioremap_wt ioremap_nocache > > > > Current ioremap_wc and ioremap_wt implementation are too simple and > > we'll improve it in future. > > > > > In particular: > > > > > > - Is a read from uncached memory always serialized with DMA, and with > > > other CPUs doing MMIO access to a different address? > > CPU use ld.w to get data from uncached strong order memory. > > Other CPUs use the same mmio vaddr to access the uncachable strong order > > memory paddr. > > Ok, but what about the DMA? The most common requirement for > serialization here is with a DMA transfer, where you first write > into a buffer in memory, then write to an MMIO register to trigger > a DMA-load, and then the device reads the data from memory. > Without a barrier before the MMIO, the data may still be in a > store queue of the CPU, and the DMA gets stale data. > > Similarly, an MMIO read may be used to see if a DMA has completed > and the device register tells you that the DMA has left the device, > but without a barrier, the CPU may have prefetched the DMA > data while waiting for the MMIO-read to complete. The __io_ar() > barrier() in asm-generic/io.h prevents the compiler from reordering > the two reads, but if an weakly ordered read (in coherent DMA buffer) > can bypass a strongly ordered read (MMIO), then it's still still > broken. __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So I got rmb() here not barrier(). Only __io_br() is barrier(). > > > - How does endianess work? Are there any buses that flip bytes around > > > when running big-endian, or do you always do that in software? > > Currently we only support little-endian and soc will follow it. > > Ok, that makes it easier. If you think that you won't even need big-endian > support in the long run, you could also remove your asm/byteorder.h > header. If you're not sure, it doesn't hurt to keep it of course. Em... I'm not sure, so let me keep it for a while. Best Regards Guo Ren
Re: [PATCH V3 17/26] csky: Misc headers
On Fri, Sep 07, 2018 at 10:01:03AM +0200, Arnd Bergmann wrote:
> On Fri, Sep 7, 2018 at 7:17 AM Guo Ren wrote:
> >
> > On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
> > >
> > > > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > > > new file mode 100644
> > > > index 000..d36e4cd
> > > > --- /dev/null
> > > > +++ b/arch/csky/boot/dts/qemu.dts
> > > > @@ -0,0 +1,77 @@
> > > > +/dts-v1/;
> > > > +/ {
> > > > + compatible = "csky,qemu";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + interrupt-parent = <>;
> > >
> > > Ideally, qemu would supply a dtb file that matches the current
> > > configuration,
> > > as we do for instance on the ARM 'virt' machine. This allows you
> > > much more flexibility in running all kinds of options, as well as
> > > extending
> > > qemu later with new features.
> > So, I should remove qemu.dts in next version patch?
>
> It's up to you really. If you won't have a version of qemu that can do this
> by itself, it may make sense to keep it around for a while. You might
> want to include the version of your current qemu port is based on
> qemu-2.x but not upstream, you could include a qemu-2.x.dts file
> here, and have the future 3.x port provide its own.
Ok, thx for the tips.
Guo Ren
Re: [PATCH V3 17/26] csky: Misc headers
On Fri, Sep 07, 2018 at 10:01:03AM +0200, Arnd Bergmann wrote:
> On Fri, Sep 7, 2018 at 7:17 AM Guo Ren wrote:
> >
> > On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
> > >
> > > > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > > > new file mode 100644
> > > > index 000..d36e4cd
> > > > --- /dev/null
> > > > +++ b/arch/csky/boot/dts/qemu.dts
> > > > @@ -0,0 +1,77 @@
> > > > +/dts-v1/;
> > > > +/ {
> > > > + compatible = "csky,qemu";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + interrupt-parent = <>;
> > >
> > > Ideally, qemu would supply a dtb file that matches the current
> > > configuration,
> > > as we do for instance on the ARM 'virt' machine. This allows you
> > > much more flexibility in running all kinds of options, as well as
> > > extending
> > > qemu later with new features.
> > So, I should remove qemu.dts in next version patch?
>
> It's up to you really. If you won't have a version of qemu that can do this
> by itself, it may make sense to keep it around for a while. You might
> want to include the version of your current qemu port is based on
> qemu-2.x but not upstream, you could include a qemu-2.x.dts file
> here, and have the future 3.x port provide its own.
Ok, thx for the tips.
Guo Ren
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Thu, Sep 06, 2018 at 10:02:29AM +0800, Guo Ren wrote: > On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote: > > On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote: > > > > > > Signed-off-by: Guo Ren > > > --- > > > .../bindings/timer/csky,gx6605s-timer.txt | 46 > > > ++ > > > 1 file changed, 46 insertions(+) > Ok, change to "timer0: timer@0x0020a000" Ok, change to "timer0: timer@20a000"
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Thu, Sep 06, 2018 at 10:02:29AM +0800, Guo Ren wrote: > On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote: > > On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote: > > > > > > Signed-off-by: Guo Ren > > > --- > > > .../bindings/timer/csky,gx6605s-timer.txt | 46 > > > ++ > > > 1 file changed, 46 insertions(+) > Ok, change to "timer0: timer@0x0020a000" Ok, change to "timer0: timer@20a000"
Re: [PATCH V3 00/26] C-SKY(csky) Linux Kernel Port
On Thu, Sep 06, 2018 at 07:08:18PM -0700, Guenter Roeck wrote: > Hi, > > On Wed, Sep 05, 2018 at 08:07:39PM +0800, Guo Ren wrote: > > This is the 3th version patchset to add the Linux kernel port for > > C-SKY(csky). > > Thanks to everyone who provided feedback on the previous version. > > > > This patchset adds architecture support to Linux for C-SKY's 32-bit embedded > > CPU cores and the patches are based on linux-4.18.4 > > > > There are two ABI versions with several CPU cores in this patchset: > > ABIv1: ck610 (16-bit instruction, 32-bit data path, VIPT Cache ...) > > ABIv2: ck807 ck810 ck860 (16/32-bit variable length instruction, PIPT > > Cache, > > SMP ...) > > > > My key question is about upstream toolchain support. > The buildroot clone tells me > > $ git describe csky/master > 2017.11-2111-ge9cc5a5 > > and > > $ git log --oneline origin/master..csky/master | wc >11807436 57104 > > with > $ git remote -v > csky https://gitlab.com/c-sky/buildroot.git > origingit://git.buildroot.net/buildroot > > So it looks like there are more thasn a thousand patches on top of > buildroot. Adding an architecture to buildroot should only take a > single patch, or maybe a few, but not more than a thousand. > This strongly suggests that a lot of changes are not upstream > but only available in the buildroot clone. csky https://gitlab.com/c-sky/buildroot.git is our CI environment based on buildroot and it's so miscellaneous. We won't upstream it directly and we'll prepare another patch set for buildroot.org update after kernel, glibc upstreamed. > When are we going to see all those changes in upstream gcc, binutils, > and qemu ? I don't really want to dig through more than a thousand > patches in a buildroot clone to find out details about the status > of upstream toolchain support. Ok, you want to use upstream gcc, binutils to build the kernel. I'll give the tips in next version patch. Best Regards Guo Ren
Re: [PATCH V3 00/26] C-SKY(csky) Linux Kernel Port
On Thu, Sep 06, 2018 at 07:08:18PM -0700, Guenter Roeck wrote: > Hi, > > On Wed, Sep 05, 2018 at 08:07:39PM +0800, Guo Ren wrote: > > This is the 3th version patchset to add the Linux kernel port for > > C-SKY(csky). > > Thanks to everyone who provided feedback on the previous version. > > > > This patchset adds architecture support to Linux for C-SKY's 32-bit embedded > > CPU cores and the patches are based on linux-4.18.4 > > > > There are two ABI versions with several CPU cores in this patchset: > > ABIv1: ck610 (16-bit instruction, 32-bit data path, VIPT Cache ...) > > ABIv2: ck807 ck810 ck860 (16/32-bit variable length instruction, PIPT > > Cache, > > SMP ...) > > > > My key question is about upstream toolchain support. > The buildroot clone tells me > > $ git describe csky/master > 2017.11-2111-ge9cc5a5 > > and > > $ git log --oneline origin/master..csky/master | wc >11807436 57104 > > with > $ git remote -v > csky https://gitlab.com/c-sky/buildroot.git > origingit://git.buildroot.net/buildroot > > So it looks like there are more thasn a thousand patches on top of > buildroot. Adding an architecture to buildroot should only take a > single patch, or maybe a few, but not more than a thousand. > This strongly suggests that a lot of changes are not upstream > but only available in the buildroot clone. csky https://gitlab.com/c-sky/buildroot.git is our CI environment based on buildroot and it's so miscellaneous. We won't upstream it directly and we'll prepare another patch set for buildroot.org update after kernel, glibc upstreamed. > When are we going to see all those changes in upstream gcc, binutils, > and qemu ? I don't really want to dig through more than a thousand > patches in a buildroot clone to find out details about the status > of upstream toolchain support. Ok, you want to use upstream gcc, binutils to build the kernel. I'll give the tips in next version patch. Best Regards Guo Ren
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Thu, Sep 06, 2018 at 03:03:16PM +0200, Arnd Bergmann wrote:
> > INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
>
> It that reliable? I remember a similar situation with some registers on ARM
> that are usually identified through a special CPU register, but in some
> cases the SoC integrator put the wrong address in there, so we need to
> look up the address in DT anyway.
Yes, it's reliable. This interrupt is combined with CPU and not on AXI
or APB. Soc just give a hole in the address space and tell the CPU where
the address is with 20 wire-signals.
Guo Ren
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Thu, Sep 06, 2018 at 03:03:16PM +0200, Arnd Bergmann wrote:
> > INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
>
> It that reliable? I remember a similar situation with some registers on ARM
> that are usually identified through a special CPU register, but in some
> cases the SoC integrator put the wrong address in there, so we need to
> look up the address in DT anyway.
Yes, it's reliable. This interrupt is combined with CPU and not on AXI
or APB. Soc just give a hole in the address space and tell the CPU where
the address is with 20 wire-signals.
Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Thu, Sep 06, 2018 at 03:05:38PM +0200, Arnd Bergmann wrote:
> On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> >
> > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > >
> > > > Signed-off-by: Guo Ren
> > > > +
> > > > + intc: interrupt-controller {
> > >
> > > Needs a unit-address.
> > Ok, change it to:
> > intc: interrupt-controller@0x00500000 {
>
> The unit address has no leading 0x or leading zeroes, so
> interrupt-controller@50
Ok
Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Thu, Sep 06, 2018 at 03:05:38PM +0200, Arnd Bergmann wrote:
> On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> >
> > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > >
> > > > Signed-off-by: Guo Ren
> > > > +
> > > > + intc: interrupt-controller {
> > >
> > > Needs a unit-address.
> > Ok, change it to:
> > intc: interrupt-controller@0x00500000 {
>
> The unit address has no leading 0x or leading zeroes, so
> interrupt-controller@50
Ok
Guo Ren
Re: [PATCH V3 17/26] csky: Misc headers
On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > new file mode 100644
> > index 000..d36e4cd
> > --- /dev/null
> > +++ b/arch/csky/boot/dts/qemu.dts
> > @@ -0,0 +1,77 @@
> > +/dts-v1/;
> > +/ {
> > + compatible = "csky,qemu";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupt-parent = <>;
>
> Ideally, qemu would supply a dtb file that matches the current configuration,
> as we do for instance on the ARM 'virt' machine. This allows you
> much more flexibility in running all kinds of options, as well as extending
> qemu later with new features.
So, I should remove qemu.dts in next version patch?
> > +
> > + timer0: timer@0xd000 {
> > + compatible = "snps,dw-apb-timer";
> > + reg = <0xd000 0x1000>;
> > + clocks = <_apb>;
> > + clock-names = "timer";
> > + interrupts = <1>;
> > + };
> > +
> > + timer1: timer@0xd014 {
>
> Drop the leading '0x' in the unit-address here (in all devices)
Ok
Re: [PATCH V3 17/26] csky: Misc headers
On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > new file mode 100644
> > index 000..d36e4cd
> > --- /dev/null
> > +++ b/arch/csky/boot/dts/qemu.dts
> > @@ -0,0 +1,77 @@
> > +/dts-v1/;
> > +/ {
> > + compatible = "csky,qemu";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupt-parent = <>;
>
> Ideally, qemu would supply a dtb file that matches the current configuration,
> as we do for instance on the ARM 'virt' machine. This allows you
> much more flexibility in running all kinds of options, as well as extending
> qemu later with new features.
So, I should remove qemu.dts in next version patch?
> > +
> > + timer0: timer@0xd000 {
> > + compatible = "snps,dw-apb-timer";
> > + reg = <0xd000 0x1000>;
> > + clocks = <_apb>;
> > + clock-names = "timer";
> > + interrupts = <1>;
> > + };
> > +
> > + timer1: timer@0xd014 {
>
> Drop the leading '0x' in the unit-address here (in all devices)
Ok
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 05:50:02PM +0200, Geert Uytterhoeven wrote: > On Thu, Sep 6, 2018 at 4:25 PM Arnd Bergmann wrote: > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > --- /dev/null > > > +++ b/arch/csky/abiv1/memset.c > > > @@ -0,0 +1,38 @@ > > > + if ((long)d & 0x3) > > > + while (l--) *d++ = ch; > > while ((uintptr_t)d & 0x3) && l--) > *d++ =ch; > > and remove the else below? Ok > > > + *(((long *)d)+3) = tmp; > > s/long/u32/ Ok Thx Guo Ren
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 05:50:02PM +0200, Geert Uytterhoeven wrote: > On Thu, Sep 6, 2018 at 4:25 PM Arnd Bergmann wrote: > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > --- /dev/null > > > +++ b/arch/csky/abiv1/memset.c > > > @@ -0,0 +1,38 @@ > > > + if ((long)d & 0x3) > > > + while (l--) *d++ = ch; > > while ((uintptr_t)d & 0x3) && l--) > *d++ =ch; > > and remove the else below? Ok > > > + *(((long *)d)+3) = tmp; > > s/long/u32/ Ok Thx Guo Ren
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 04:24:59PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > --- /dev/null
> > +++ b/arch/csky/abiv1/memset.c
> > @@ -0,0 +1,38 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
> > +#include
> > +
> > +void *memset(void *dest, int c, size_t l)
> > +{
> > + char *d = dest;
> > + int ch = c;
> > + int tmp;
> > +
> > + if ((long)d & 0x3)
> > + while (l--) *d++ = ch;
> > + else {
> > + ch &= 0xff;
> > + tmp = (ch | ch << 8 | ch << 16 | ch << 24);
> > +
> > + while (l >= 16) {
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
> > + l -= 16;
> > + d += 16;
> > + }
> > +
> > + while (l > 3) {
> > + *(((long *)d)) = tmp;
> > + d = d + 4;
> > + l -= 4;
> > + }
> > +
> > + while (l) {
> > + *d++ = ch;
> > + l--;
> > + }
> > + }
> > + return dest;
> > +}
>
> I see that we have a trivial memset() implementation in lib/string.c, but
> yours
> seems to be better optimized. Where did you get it from?
We write it for our ck610 to improve the performance, but I think a lot
of other arch done it in asm style.
> Is this a version
> that works particularly well on C-Sky, or is this a generic optimized memset
> that others could use as well?
We only test it on C-SKY, but I think it will also work better on other
arch CPU than current lib/string.c memset implement.
I see that in lib/string.c:
void *memset(void *s, int c, size_t count)
{
char *xs = s;
while (count--)
*xs++ = c;
return s;
}
The most problem is "char *xs;" and it will cause "st.b" in asm.
"st.b" is very slow.
Our key improvement is:
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
It will cause SOC AXI burst transfer.
> In the latter case, we could add it to
> lib/string.c and let architectures select it in place of the triivial version.
Good idea.
Guo Ren
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 04:24:59PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > --- /dev/null
> > +++ b/arch/csky/abiv1/memset.c
> > @@ -0,0 +1,38 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
> > +#include
> > +
> > +void *memset(void *dest, int c, size_t l)
> > +{
> > + char *d = dest;
> > + int ch = c;
> > + int tmp;
> > +
> > + if ((long)d & 0x3)
> > + while (l--) *d++ = ch;
> > + else {
> > + ch &= 0xff;
> > + tmp = (ch | ch << 8 | ch << 16 | ch << 24);
> > +
> > + while (l >= 16) {
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
> > + l -= 16;
> > + d += 16;
> > + }
> > +
> > + while (l > 3) {
> > + *(((long *)d)) = tmp;
> > + d = d + 4;
> > + l -= 4;
> > + }
> > +
> > + while (l) {
> > + *d++ = ch;
> > + l--;
> > + }
> > + }
> > + return dest;
> > +}
>
> I see that we have a trivial memset() implementation in lib/string.c, but
> yours
> seems to be better optimized. Where did you get it from?
We write it for our ck610 to improve the performance, but I think a lot
of other arch done it in asm style.
> Is this a version
> that works particularly well on C-Sky, or is this a generic optimized memset
> that others could use as well?
We only test it on C-SKY, but I think it will also work better on other
arch CPU than current lib/string.c memset implement.
I see that in lib/string.c:
void *memset(void *s, int c, size_t count)
{
char *xs = s;
while (count--)
*xs++ = c;
return s;
}
The most problem is "char *xs;" and it will cause "st.b" in asm.
"st.b" is very slow.
Our key improvement is:
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
It will cause SOC AXI burst transfer.
> In the latter case, we could add it to
> lib/string.c and let architectures select it in place of the triivial version.
Good idea.
Guo Ren
Re: [PATCH V3 09/26] csky: VDSO and rt_sigreturn
On Thu, Sep 06, 2018 at 04:02:42PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +
> > + /*
> > +* __NR_rt_sigreturn must be 173
> > +* Because gcc/config/csky/linux-unwind.h use hard code to parse
> > rt_sigframe.
> > +*/
> > + err = setup_vdso_page(vdso->rt_signal_retcode);
> > + if (err) panic("Cannot set signal return code, err: %x.", err);
>
> __NR_rt_sigreturn is 139
Yes, we've changed to use asm-generic define, and I forgot to update the
comment.
Guo Ren
Re: [PATCH V3 09/26] csky: VDSO and rt_sigreturn
On Thu, Sep 06, 2018 at 04:02:42PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +
> > + /*
> > +* __NR_rt_sigreturn must be 173
> > +* Because gcc/config/csky/linux-unwind.h use hard code to parse
> > rt_sigframe.
> > +*/
> > + err = setup_vdso_page(vdso->rt_signal_retcode);
> > + if (err) panic("Cannot set signal return code, err: %x.", err);
>
> __NR_rt_sigreturn is 139
Yes, we've changed to use asm-generic define, and I forgot to update the
comment.
Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h > > new file mode 100644 > > index 000..fcb2142 > > --- /dev/null > > +++ b/arch/csky/include/asm/io.h > > @@ -0,0 +1,23 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. > > +#ifndef __ASM_CSKY_IO_H > > +#define __ASM_CSKY_IO_H > > + > > +#include > > +#include > > +#include > > + > > +extern void __iomem *ioremap(phys_addr_t offset, size_t size); > > + > > +extern void iounmap(void *addr); > > + > > +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, > > + size_t size, unsigned long flags); > > + > > +#define ioremap_nocache(phy, sz) ioremap(phy, sz) > > +#define ioremap_wc ioremap_nocache > > +#define ioremap_wt ioremap_nocache > > + > > +#include > > It is very unusual for an architecture to not need special handling in > asm/io.h, > to do the proper barriers etc. > > Can you describe how C-Sky hardware implements MMIO? Our mmio is uncachable and strong-order address, so there is no need barriers for access these io addr. #define ioremap_wc ioremap_nocache #define ioremap_wt ioremap_nocache Current ioremap_wc and ioremap_wt implementation are too simple and we'll improve it in future. > In particular: > > - Is a read from uncached memory always serialized with DMA, and with > other CPUs doing MMIO access to a different address? CPU use ld.w to get data from uncached strong order memory. Other CPUs use the same mmio vaddr to access the uncachable strong order memory paddr. > - How does endianess work? Are there any buses that flip bytes around > when running big-endian, or do you always do that in software? Currently we only support little-endian and soc will follow it. Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h > > new file mode 100644 > > index 000..fcb2142 > > --- /dev/null > > +++ b/arch/csky/include/asm/io.h > > @@ -0,0 +1,23 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. > > +#ifndef __ASM_CSKY_IO_H > > +#define __ASM_CSKY_IO_H > > + > > +#include > > +#include > > +#include > > + > > +extern void __iomem *ioremap(phys_addr_t offset, size_t size); > > + > > +extern void iounmap(void *addr); > > + > > +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, > > + size_t size, unsigned long flags); > > + > > +#define ioremap_nocache(phy, sz) ioremap(phy, sz) > > +#define ioremap_wc ioremap_nocache > > +#define ioremap_wt ioremap_nocache > > + > > +#include > > It is very unusual for an architecture to not need special handling in > asm/io.h, > to do the proper barriers etc. > > Can you describe how C-Sky hardware implements MMIO? Our mmio is uncachable and strong-order address, so there is no need barriers for access these io addr. #define ioremap_wc ioremap_nocache #define ioremap_wt ioremap_nocache Current ioremap_wc and ioremap_wt implementation are too simple and we'll improve it in future. > In particular: > > - Is a read from uncached memory always serialized with DMA, and with > other CPUs doing MMIO access to a different address? CPU use ld.w to get data from uncached strong order memory. Other CPUs use the same mmio vaddr to access the uncachable strong order memory paddr. > - How does endianess work? Are there any buses that flip bytes around > when running big-endian, or do you always do that in software? Currently we only support little-endian and soc will follow it. Guo Ren
Re: [PATCH V3 05/26] csky: System Call
On Thu, Sep 06, 2018 at 04:10:49PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +SYSCALL_DEFINE6(mmap2,
> > + unsigned long, addr,
> > + unsigned long, len,
> > + unsigned long, prot,
> > + unsigned long, flags,
> > + unsigned long, fd,
> > + off_t, offset)
> > +{
> > + if (unlikely(offset & (~PAGE_MASK >> 12)))
> > + return -EINVAL;
> > + return sys_mmap_pgoff(addr, len, prot, flags, fd,
> > + offset >> (PAGE_SHIFT - 12));
> > +}
>
> Please call ksys_mmap_pgoff() instead of sys_mmap_pgoff() here.
Ok.
> The prototype in include/asm-generic/syscalls.h uses 'unsigned long'
> for the last argument as well, not off_t.
Ok, unsigned long for last argument.
> > +struct mmap_arg_struct {
> > + unsigned long addr;
> > + unsigned long len;
> > + unsigned long prot;
> > + unsigned long flags;
> > + unsigned long fd;
> > + unsigned long offset;
> > +};
> > +
> > +SYSCALL_DEFINE1(mmap,
> > + struct mmap_arg_struct *, arg)
>
> Something is still wrong here, there should be no way to
> call sys_mmap(), since it's not in the syscall table.
You are right, remove it.
> > + return sys_fadvise64_64(fd, offset, len, advice);
> > +}
>
> And call ksys_fadvise64_64() here.
Ok.
Guo Ren
Re: [PATCH V3 05/26] csky: System Call
On Thu, Sep 06, 2018 at 04:10:49PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +SYSCALL_DEFINE6(mmap2,
> > + unsigned long, addr,
> > + unsigned long, len,
> > + unsigned long, prot,
> > + unsigned long, flags,
> > + unsigned long, fd,
> > + off_t, offset)
> > +{
> > + if (unlikely(offset & (~PAGE_MASK >> 12)))
> > + return -EINVAL;
> > + return sys_mmap_pgoff(addr, len, prot, flags, fd,
> > + offset >> (PAGE_SHIFT - 12));
> > +}
>
> Please call ksys_mmap_pgoff() instead of sys_mmap_pgoff() here.
Ok.
> The prototype in include/asm-generic/syscalls.h uses 'unsigned long'
> for the last argument as well, not off_t.
Ok, unsigned long for last argument.
> > +struct mmap_arg_struct {
> > + unsigned long addr;
> > + unsigned long len;
> > + unsigned long prot;
> > + unsigned long flags;
> > + unsigned long fd;
> > + unsigned long offset;
> > +};
> > +
> > +SYSCALL_DEFINE1(mmap,
> > + struct mmap_arg_struct *, arg)
>
> Something is still wrong here, there should be no way to
> call sys_mmap(), since it's not in the syscall table.
You are right, remove it.
> > + return sys_fadvise64_64(fd, offset, len, advice);
> > +}
>
> And call ksys_fadvise64_64() here.
Ok.
Guo Ren
Re: [PATCH V3 02/26] csky: defconfig
On Thu, Sep 06, 2018 at 03:58:51PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > Signed-off-by: Guo Ren > > --- > > arch/csky/configs/defconfig | 76 > > + > > +CONFIG_USELIB=y > > CONFIG_USELIB seems misplaced here, very few architectures can even > call that, and it's not in the asm-generic/unistd.h file. Ok, remove it. > > +CONFIG_RELAY=y > > relay is selected by drivers that need it, you should not need to turn > it on here. Ok, remove it. > > +CONFIG_SYSCTL_SYSCALL=y > > Also not in the asm-generic syscall table. We should probably hide the > CONFIG_USELIB and CONFIG_SYSCTL_SYSCALL options so they > only appear on architectures that can use them (patches welcome). Ok, remove it. > > > +CONFIG_KALLSYMS_ALL=y > > While useful for debugging, this is also something I would not expect > in the defconfig file Ok, remove it. > > +CONFIG_USERFAULTFD=y > > Probably not needed either, unless you have a specific use > case. Ok, remove it. > > +CONFIG_EMBEDDED=y > > This (and CONFIG_EXPERT) is mostly there to expose options > that are otherwise hidden for good reasons. Is there any option > you tweak that depends on this? If not, then remove this as well. Ok, remove it. > > +CONFIG_PROFILING=y > > This is only for oprofile, which new architectures should generally > no longer implement. Better implement PERF only. Ok, remove it and we will only implement perf in future. > > +CONFIG_BLK_DEV_INTEGRITY=y > > This is also fairly unusual. Ok, remove it. > > +CONFIG_EXT2_FS=y > > +CONFIG_EXT2_FS_XATTR=y > > +CONFIG_EXT2_FS_POSIX_ACL=y > > +CONFIG_EXT2_FS_SECURITY=y > > +CONFIG_EXT3_FS=y > > +CONFIG_EXT3_FS_POSIX_ACL=y > > +CONFIG_EXT3_FS_SECURITY=y > > Better enable only EXT4 and drop EXT2/EXT3. Ok. > > +CONFIG_UNUSED_SYMBOLS=y > > You should only need this to work around bugs, so > I'd turn it off. Ok, remove it. Guo Ren
Re: [PATCH V3 02/26] csky: defconfig
On Thu, Sep 06, 2018 at 03:58:51PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > Signed-off-by: Guo Ren > > --- > > arch/csky/configs/defconfig | 76 > > + > > +CONFIG_USELIB=y > > CONFIG_USELIB seems misplaced here, very few architectures can even > call that, and it's not in the asm-generic/unistd.h file. Ok, remove it. > > +CONFIG_RELAY=y > > relay is selected by drivers that need it, you should not need to turn > it on here. Ok, remove it. > > +CONFIG_SYSCTL_SYSCALL=y > > Also not in the asm-generic syscall table. We should probably hide the > CONFIG_USELIB and CONFIG_SYSCTL_SYSCALL options so they > only appear on architectures that can use them (patches welcome). Ok, remove it. > > > +CONFIG_KALLSYMS_ALL=y > > While useful for debugging, this is also something I would not expect > in the defconfig file Ok, remove it. > > +CONFIG_USERFAULTFD=y > > Probably not needed either, unless you have a specific use > case. Ok, remove it. > > +CONFIG_EMBEDDED=y > > This (and CONFIG_EXPERT) is mostly there to expose options > that are otherwise hidden for good reasons. Is there any option > you tweak that depends on this? If not, then remove this as well. Ok, remove it. > > +CONFIG_PROFILING=y > > This is only for oprofile, which new architectures should generally > no longer implement. Better implement PERF only. Ok, remove it and we will only implement perf in future. > > +CONFIG_BLK_DEV_INTEGRITY=y > > This is also fairly unusual. Ok, remove it. > > +CONFIG_EXT2_FS=y > > +CONFIG_EXT2_FS_XATTR=y > > +CONFIG_EXT2_FS_POSIX_ACL=y > > +CONFIG_EXT2_FS_SECURITY=y > > +CONFIG_EXT3_FS=y > > +CONFIG_EXT3_FS_POSIX_ACL=y > > +CONFIG_EXT3_FS_SECURITY=y > > Better enable only EXT4 and drop EXT2/EXT3. Ok. > > +CONFIG_UNUSED_SYMBOLS=y > > You should only need this to work around bugs, so > I'd turn it off. Ok, remove it. Guo Ren
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Wed, Sep 05, 2018 at 07:45:12PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/interrupt-controller/csky,mpintc.txt | 40
> > ++
> > 1 file changed, 40 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > new file mode 100644
> > index 000..49d1658
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > @@ -0,0 +1,40 @@
> > +===
> > +C-SKY Multi-processors Interrupt Controller
> > +===
> > +
> > +C-SKY Multi-processors Interrupt Controller is designed for
> > ck807/ck810/ck860
> > +SMP soc, and it also could be used in non-SMP system.
>
> How is it accessed? No mmio registers?
Mmio reg base is got from cpu-coprocessor register and I'll detail
it here in next version patch.
csky_mpintc_init(struct device_node *node, struct device_node *parent)
{
...
INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Wed, Sep 05, 2018 at 07:45:12PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/interrupt-controller/csky,mpintc.txt | 40
> > ++
> > 1 file changed, 40 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > new file mode 100644
> > index 000..49d1658
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > @@ -0,0 +1,40 @@
> > +===
> > +C-SKY Multi-processors Interrupt Controller
> > +===
> > +
> > +C-SKY Multi-processors Interrupt Controller is designed for
> > ck807/ck810/ck860
> > +SMP soc, and it also could be used in non-SMP system.
>
> How is it accessed? No mmio registers?
Mmio reg base is got from cpu-coprocessor register and I'll detail
it here in next version patch.
csky_mpintc_init(struct device_node *node, struct device_node *parent)
{
...
INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../interrupt-controller/csky,apb-intc.txt | 45
> > ++
> > 1 file changed, 45 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > new file mode 100644
> > index 000..faa482c
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > @@ -0,0 +1,45 @@
> > +==
> > +C-SKY APB Interrupt Controller
> > +==
> > +
> > +C-SKY APB Interrupt Controller is a simple soc interrupt controller
> > +on the apb bus and we only use it as root irq controller.
> > +
> > + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64
> > irq nums.
> > + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
>
> Can't this be described in DT as 2 csky,apb-intc nodes?
In detail, dual-apb-intc is not the same as two apb-intc, so I still want to
name them
separately, so I will keep this and it is clearer.
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,apb-intc"
> > + "csky,dual-apb-intc"
> > + "csky,gx6605s-intc"
> > +- interrupt-cells
>
> #interrupt-cells
Yes, I forgot #.
- #interrupt-cells
> > +Usage: required
> > +Value type:
> > +Definition: must be <1>
>
> No edge or level configuration?
No, also no support in hardware.
> > +
> > + intc: interrupt-controller {
>
> Needs a unit-address.
Ok, change it to:
intc: interrupt-controller@0x0050 {
Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../interrupt-controller/csky,apb-intc.txt | 45
> > ++
> > 1 file changed, 45 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > new file mode 100644
> > index 000..faa482c
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > @@ -0,0 +1,45 @@
> > +==
> > +C-SKY APB Interrupt Controller
> > +==
> > +
> > +C-SKY APB Interrupt Controller is a simple soc interrupt controller
> > +on the apb bus and we only use it as root irq controller.
> > +
> > + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64
> > irq nums.
> > + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
>
> Can't this be described in DT as 2 csky,apb-intc nodes?
In detail, dual-apb-intc is not the same as two apb-intc, so I still want to
name them
separately, so I will keep this and it is clearer.
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,apb-intc"
> > + "csky,dual-apb-intc"
> > + "csky,gx6605s-intc"
> > +- interrupt-cells
>
> #interrupt-cells
Yes, I forgot #.
- #interrupt-cells
> > +Usage: required
> > +Value type:
> > +Definition: must be <1>
>
> No edge or level configuration?
No, also no support in hardware.
> > +
> > + intc: interrupt-controller {
>
> Needs a unit-address.
Ok, change it to:
intc: interrupt-controller@0x0050 {
Guo Ren
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/timer/csky,gx6605s-timer.txt | 46
> > ++
> > 1 file changed, 46 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> >
> > diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > new file mode 100644
> > index 000..1136d9e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > @@ -0,0 +1,46 @@
> > +=
> > +gx6605s SOC Timer
> > +=
> > +
> > +The timer is used in gx6605s soc as system timer and the driver
> > +contain clk event and clk source.
> > +
> > +==
> > +timer node bindings definition
> > +==
> > +
> > +Description: Describes gx6605s SOC timer
> > +
> > +PROPERTIES
> > +
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,gx6605s"
>
> -timer?
Yes, thx. must be "csky,gx6605s-timer"
>
> > + - reg
> > + Usage: required
> > + Value type:
> > + Definition: in soc from cpu view
> > + - clocks
> > + Usage: required
> > + Value type:
>
> phandle + clock specifier cells
Sorry, I don't got it. Do you mean:
Value type:
?
>
> > + Definition: must be input clk node
> > +- interrupt
> > +Usage: required
> > +Value type:
> > +Definition: must be timer irq num defined by soc
> > +- interrupt-parent:
>
> This is implied. Don't need to document it here.
Ok, remove interrupt-parent
>
> > +Usage: required
> > + Value type:
> > +Definition: must be interrupt controller node
> > +
> > +Examples:
> > +-
> > +
> > + timer:timer {
>
> Needs a unit-address.
Ok, change to "timer0: timer@0x0020a000"
>
> > + compatible = "csky,gx6605s-timer";
> > + reg = <0x0020a000 0x400>;
> > + clocks = <_apb_clk>;
> > + interrupts = <10>;
> > + interrupt-parent = <>;
> > + };
> > --
> > 2.7.4
> >
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/timer/csky,gx6605s-timer.txt | 46
> > ++
> > 1 file changed, 46 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> >
> > diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > new file mode 100644
> > index 000..1136d9e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > @@ -0,0 +1,46 @@
> > +=
> > +gx6605s SOC Timer
> > +=
> > +
> > +The timer is used in gx6605s soc as system timer and the driver
> > +contain clk event and clk source.
> > +
> > +==
> > +timer node bindings definition
> > +==
> > +
> > +Description: Describes gx6605s SOC timer
> > +
> > +PROPERTIES
> > +
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,gx6605s"
>
> -timer?
Yes, thx. must be "csky,gx6605s-timer"
>
> > + - reg
> > + Usage: required
> > + Value type:
> > + Definition: in soc from cpu view
> > + - clocks
> > + Usage: required
> > + Value type:
>
> phandle + clock specifier cells
Sorry, I don't got it. Do you mean:
Value type:
?
>
> > + Definition: must be input clk node
> > +- interrupt
> > +Usage: required
> > +Value type:
> > +Definition: must be timer irq num defined by soc
> > +- interrupt-parent:
>
> This is implied. Don't need to document it here.
Ok, remove interrupt-parent
>
> > +Usage: required
> > + Value type:
> > +Definition: must be interrupt controller node
> > +
> > +Examples:
> > +-
> > +
> > + timer:timer {
>
> Needs a unit-address.
Ok, change to "timer0: timer@0x0020a000"
>
> > + compatible = "csky,gx6605s-timer";
> > + reg = <0x0020a000 0x400>;
> > + clocks = <_apb_clk>;
> > + interrupts = <10>;
> > + interrupt-parent = <>;
> > + };
> > --
> > 2.7.4
> >
Re: [PATCH V3 18/26] dt-bindings: csky CPU Bindings
On Wed, Sep 05, 2018 at 07:37:50PM -0500, Rob Herring wrote: > On Wed, Sep 5, 2018 at 7:08 AM Guo Ren wrote: > > > > Signed-off-by: Guo Ren > > --- > > Documentation/devicetree/bindings/csky/cpus.txt | 70 > > + > > 1 file changed, 70 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/csky/cpus.txt > > Please make sure DT bindings are sent to DT list. Oh, I forgot add devicet...@vger.kernel.org. Thx for mentioned. Guo Ren
