Re: [PATCH v1 1/1] arm64: dts: mt6779: add spi host dts nodes
On Tue, 2021-01-26 at 21:18 +0800, Mason Zhang wrote:
> From: mtk22786
>
> this patch add spi host dts nodes for mt6779 IC.
>
> Change-Id: If4a3cbb09843f472210b390352db4b9886f5c00c
> Signed-off-by: Mason Zhang
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..272f4346d35e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
add the compatible string into the SPI binding
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = ;
add 4th value into interrupts property to support PPI partition
(0 for SPI)
interrupts = ;
Regards,
Hanks Chen
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@1101 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> +
Re: [PATCH v1 1/3] irqchip/gic: enable irq target all
Hi Marc,
Sorry for the late reply.
On Fri, 2020-11-27 at 18:11 +, Marc Zyngier wrote:
> On 2020-11-27 14:15, Hanks Chen wrote:
> > Support for interrupt distribution design for SMP system solutions.
>
> As far as I know, we have been supporting interrupt distribution on
> ARM SMP systems pretty well for the past... what... 15 years?
> I'm sure Russell can dig out an ARM926 SMP system that even predates
> that.
>
> > With this feature enabled ,the SPI interrupts would be routed to
> > all the cores rather than boot core to achieve better
> > load balance of interrupt handling.
>
> Please quantify this compared to the current distribution method.
>
Got it, but I need some time to prepare for the demonstration.
I'll show it soon.
Btw, it is good on IO bandwidth-sensitive applications, we could also
use androbench to recognize it.
> > That is, interrupts might be serviced simultaneously on different CPUs.
>
> They already can. What is new here? Or do you mean the *same* interrupt
> being serviced by different CPUs *at the same time*? That'd be fun.
>
It is my fault, I used the imprecise word to describe it.
Not mean 'same interrupt being serviced by different CPUs'.
You are right, we can use affinity API to achieve 'different CPUs'
However, I focus on HW behavior.
If we don't change the setting of affinity(target to boot CPU),
SPI IRQs might still be serviced on different CPUs after applying target
all.
> > Signed-off-by: Hanks Chen
> > ---
> > drivers/irqchip/Kconfig| 12
> > drivers/irqchip/irq-gic-v3.c | 107 +
> > include/linux/irqchip/arm-gic-v3.h | 1 +
> > kernel/irq/cpuhotplug.c| 22 ++
> > kernel/irq/manage.c| 7 ++
> > 5 files changed, 122 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index c6098eee0c7c..c88ee7731e92 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -597,4 +597,16 @@ config MST_IRQ
> > help
> > Support MStar Interrupt Controller.
> >
> > +config ARM_IRQ_TARGET_ALL
> > + bool "Distribute interrupts across processors on SMP system"
> > + depends on SMP && ARM_GIC_V3
> > + help
> > + Support for interrupt distribution design for
> > + SMP system solutions. With this feature enabled ,the
> > + SPI interrupts would be routed to all the cores rather
> > + than boot cpu to achieve better load balance of interrupt
> > + handling
> > +
> > + If you don't know what to do here, say N.
>
> There is no way we start introducing conditional compilation for
> architectural features. Either this works at all times, or it doesn't
> exist.
>
I have no idea how to solve it.
Indeed, it is not good to enable the feature on every ARM-based
platform.
maybe I could use device tree to determine whether or not the feature
should be enabled.
e.g.
gic: interrupt-controller {
compatible = "arm,gic-v3";
...
irq-target-all-enable = <1>;
};
Would this be better?
> > +
> > endmenu
> > diff --git a/drivers/irqchip/irq-gic-v3.c
> > b/drivers/irqchip/irq-gic-v3.c
> > index 16fecc0febe8..62a878ce4681 100644
> > --- a/drivers/irqchip/irq-gic-v3.c
> > +++ b/drivers/irqchip/irq-gic-v3.c
> > @@ -381,6 +381,12 @@ static inline bool gic_supports_nmi(void)
> >static_branch_likely(_pseudo_nmis);
> > }
> >
> > +static inline bool gic_supports_1n(void)
> > +{
> > + return (IS_ENABLED(CONFIG_ARM_IRQ_TARGET_ALL) &&
> > + ~(readl_relaxed(gic_data.dist_base + GICD_TYPER) &
> > GICD_TYPER_No1N));
> > +}
> > +
> > static int gic_irq_set_irqchip_state(struct irq_data *d,
> > enum irqchip_irq_state which, bool val)
> > {
> > @@ -716,6 +722,7 @@ static void __init gic_dist_init(void)
> > {
> > unsigned int i;
> > u64 affinity;
> > +
>
> Spurious whitespace.
Got it, I'll fix it.
>
> > void __iomem *base = gic_data.dist_base;
> > u32 val;
> >
> > @@ -759,16 +766,27 @@ static void __init gic_dist_init(void)
> > /* Enable distributor with ARE, Group1 */
> > writel_relaxed(val, base + GICD_CTLR);
> >
> > - /*
> > -* Set all global interrupts to the boot CPU only. ARE must be
> > -* enabled.
> > -*/
> > - affinity =
> > gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
> > - for (i = 32;
[PATCH v1 1/3] irqchip/gic: enable irq target all
Support for interrupt distribution design for SMP system solutions.
With this feature enabled ,the SPI interrupts would be routed to
all the cores rather than boot core to achieve better
load balance of interrupt handling.
That is, interrupts might be serviced simultaneously on different CPUs.
Signed-off-by: Hanks Chen
---
drivers/irqchip/Kconfig| 12
drivers/irqchip/irq-gic-v3.c | 107 +
include/linux/irqchip/arm-gic-v3.h | 1 +
kernel/irq/cpuhotplug.c| 22 ++
kernel/irq/manage.c| 7 ++
5 files changed, 122 insertions(+), 27 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c6098eee0c7c..c88ee7731e92 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -597,4 +597,16 @@ config MST_IRQ
help
Support MStar Interrupt Controller.
+config ARM_IRQ_TARGET_ALL
+ bool "Distribute interrupts across processors on SMP system"
+ depends on SMP && ARM_GIC_V3
+ help
+ Support for interrupt distribution design for
+ SMP system solutions. With this feature enabled ,the
+ SPI interrupts would be routed to all the cores rather
+ than boot cpu to achieve better load balance of interrupt
+ handling
+
+ If you don't know what to do here, say N.
+
endmenu
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 16fecc0febe8..62a878ce4681 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -381,6 +381,12 @@ static inline bool gic_supports_nmi(void)
static_branch_likely(_pseudo_nmis);
}
+static inline bool gic_supports_1n(void)
+{
+ return (IS_ENABLED(CONFIG_ARM_IRQ_TARGET_ALL) &&
+ ~(readl_relaxed(gic_data.dist_base + GICD_TYPER) &
GICD_TYPER_No1N));
+}
+
static int gic_irq_set_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which, bool val)
{
@@ -716,6 +722,7 @@ static void __init gic_dist_init(void)
{
unsigned int i;
u64 affinity;
+
void __iomem *base = gic_data.dist_base;
u32 val;
@@ -759,16 +766,27 @@ static void __init gic_dist_init(void)
/* Enable distributor with ARE, Group1 */
writel_relaxed(val, base + GICD_CTLR);
- /*
-* Set all global interrupts to the boot CPU only. ARE must be
-* enabled.
-*/
- affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
- for (i = 32; i < GIC_LINE_NR; i++)
- gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
+ if (!gic_supports_1n()) {
+ /*
+* Set all global interrupts to the boot CPU only. ARE must be
+* enabled.
+*/
+ affinity =
gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
+ for (i = 32; i < GIC_LINE_NR; i++)
+ gic_write_irouter(affinity, base + GICD_IROUTER + i *
8);
- for (i = 0; i < GIC_ESPI_NR; i++)
- gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
+ for (i = 0; i < GIC_ESPI_NR; i++)
+ gic_write_irouter(affinity, base + GICD_IROUTERnE + i *
8);
+ } else {
+ /* default set target all for all SPI */
+ for (i = 32; i < GIC_LINE_NR; i++)
+ gic_write_irouter(GICD_IROUTER_SPI_MODE_ANY,
+ base + GICD_IROUTER + i * 8);
+
+ for (i = 0; i < GIC_ESPI_NR; i++)
+ gic_write_irouter(GICD_IROUTER_SPI_MODE_ANY,
+ base + GICD_IROUTERnE + i * 8);
+ }
}
static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem
*))
@@ -1191,29 +1209,64 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
if (gic_irq_in_rdist(d))
return -EINVAL;
- /* If interrupt was enabled, disable it first */
- enabled = gic_peek_irq(d, GICD_ISENABLER);
- if (enabled)
- gic_mask_irq(d);
+ if (!gic_supports_1n()) {
+ /* If interrupt was enabled, disable it first */
+ enabled = gic_peek_irq(d, GICD_ISENABLER);
+ if (enabled)
+ gic_mask_irq(d);
- offset = convert_offset_index(d, GICD_IROUTER, );
- reg = gic_dist_base(d) + offset + (index * 8);
- val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
+ offset = convert_offset_index(d, GICD_IROUTER, );
+ reg = gic_dist_base(d) + offset + (index * 8);
+ val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
- gic_write_irouter(val, reg);
+ gic_write_irouter(val, reg);
- /*
-* If the interrupt was enabled, e
Support 1 of N SPI interrupt for interrupt distribution
*** BLURB HERE *** The GICv3 supports 1 of N selection of SPI interrupts. When the GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects the appropriate core for a SPI. Actually, dispatch the interrupt by hardware Interrupt Control Unit is more efficient than irqbalance of software logic and no need to implement software contoller to decide the targeted CPU on various platform. In order to reduce interrupt latency, all interrupts are targeted to each online CPU defaultly by 1 of N selection of SPI interrupts. That is, SPI interrupts might be serviced simultaneously on different CPUs. [default policy] AS-IS (target to boot CPU) CPU0 CPU1 CPU2 CPU3 29: 92 0 0 0 GICv3 141 Level ttyS0 TO-BE (enable ARM_IRQ_TARGET_ALL) CPU0 CPU1 CPU2 CPU3 29: 23 23 24 22 GICv3 141 Level ttyS0 Hanks Chen (3): irqchip/gic: enable irq target all arm: disable irq on cpu shutdown flow arm64: disable irq on cpu shutdown flow arch/arm/kernel/smp.c | 10 ++- arch/arm64/kernel/smp.c| 9 ++- drivers/irqchip/Kconfig| 12 drivers/irqchip/irq-gic-v3.c | 107 + include/linux/irqchip/arm-gic-v3.h | 1 + kernel/irq/cpuhotplug.c| 22 ++ kernel/irq/manage.c| 7 ++ 7 files changed, 138 insertions(+), 30 deletions(-) -- 2.18.0
[PATCH v1 3/3] arm64: disable irq on cpu shutdown flow
Disable irq on cpu shutdown flow to ensure interrupts
did not bother this cpu after status as offline.
To avoid suspicious RCU usage
(0)[0:swapper/0]RCU used illegally from offline CPU! ...
(0)[0:swapper/0]lockdep: [name:lockdep&]cpu_id = 0, cpu_is_offline = 1
Signed-off-by: Hanks Chen
---
arch/arm64/kernel/smp.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 82e75fc2c903..27a6553fa86f 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -308,6 +308,12 @@ int __cpu_disable(void)
remove_cpu_topology(cpu);
numa_remove_cpu(cpu);
+ /*
+* we disable irq here to ensure interrupts
+* did not bother this cpu after status as offline.
+*/
+ local_irq_disable();
+
/*
* Take this CPU offline. Once we clear this, we can't return,
* and we must not schedule until we're ready to give up the cpu.
@@ -842,9 +848,10 @@ void arch_irq_work_raise(void)
static void local_cpu_stop(void)
{
+ local_daif_mask();
+
set_cpu_online(smp_processor_id(), false);
- local_daif_mask();
sdei_mask_local_cpu();
cpu_park_loop();
}
--
2.18.0
[PATCH v1 2/3] arm: disable irq on cpu shutdown flow
Disable irq on cpu shutdown flow to ensure interrupts
did not bother this cpu after status as offline.
To avoid suspicious RCU usage
[0:swapper/0]RCU used illegally from offline CPU! ...
[0:swapper/0]lockdep: [name:lockdep&]cpu_id = 0, cpu_is_offline = 1
Signed-off-by: Hanks Chen
---
arch/arm/kernel/smp.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 48099c6e1e4a..6b8f72490320 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -262,6 +262,12 @@ int __cpu_disable(void)
remove_cpu_topology(cpu);
#endif
+ /*
+* we disable irq here to ensure interrupts
+* did not bother this cpu after status as offline.
+*/
+ local_irq_disable();
+
/*
* Take this CPU offline. Once we clear this, we can't return,
* and we must not schedule until we're ready to give up the cpu.
@@ -600,11 +606,11 @@ static void ipi_cpu_stop(unsigned int cpu)
raw_spin_unlock(_lock);
}
- set_cpu_online(cpu, false);
-
local_fiq_disable();
local_irq_disable();
+ set_cpu_online(cpu, false);
+
while (1) {
cpu_relax();
wfe();
--
2.18.0
Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote: > Quoting Hanks Chen (2020-10-03 03:06:47) > > Hi Michael & Stephen, > > > > Please kindly let me know your comments about this patch. > > Thanks > > > > What's the base for this patch? I tried applying to v5.9-rc1 and it > didn't work. Sorry, what does that mean? Do you have encountered a merged conflict or run time failed? I based on kernel-5.8-rc1 to add it and it can boot to kernel shell. Thanks! Hanks Chen
Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Hi Michael & Stephen,
Please kindly let me know your comments about this patch.
Thanks
Regards,
Hanks
On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote:
> Hi all,
>
> Gentle ping on this patch.
>
> Thanks
>
>
> Hanks Chen
>
>
> On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> >
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> > Signed-off-by: Wendell Lin
> > Signed-off-by: Hanks Chen
> > Reviewed-by: Matthias Brugger
> > ---
> > drivers/clk/mediatek/clk-mt6779.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c
> > b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766cccf5844..6e0d3a166729 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> > "pwm_sel", 19),
> > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> > "pwm_sel", 21),
> > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > + "uart_sel", 22),
> > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> > "uart_sel", 23),
> > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH v2] pinctrl: mediatek: check mtk_is_virt_gpio input parameter
Hi Sean & Linux & Matthias,
Please kindly let me know your comments about this fixes patch.
Thanks
Regards,
Hanks
On Thu, 2020-08-20 at 19:22 +0800, Hanks Chen wrote:
> check mtk_is_virt_gpio input parameter,
> virtual gpio need to support eint mode.
>
> add error handler for the ko case
> to fix this boot fail:
> pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
> lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]
>
> Fixes: edd546465002 ("pinctrl: mediatek: avoid virtual gpio trying to set
> reg")
> Singed-off-by: Jie Yang
> Signed-off-by: Hanks Chen
>
> ---
> Changes since v1:
> - update Singed-off-by
> - align with pinctrl/mediatek/pinctrl-mtk-mt*.h
>
> ---
> drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> index c53e2c391e32..a485d79f51a1 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> @@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned
> int gpio_n)
>
> desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
>
> + /* if the GPIO is not supported for eint mode */
> + if (desc->eint.eint_m == NO_EINT_SUPPORT)
> + return virt_gpio;
> +
> if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
> virt_gpio = true;
>
Re: Re: [PATCH v2 0/2] Remove MT6779 UART3 clock support
Hi Michael & Stephen, Gentle ping on this clk patch. Thanks. Regards, Hanks On Tue, 2020-09-08 at 14:31 +0800, Hanks Chen wrote: > Hi all, > > Gentle ping on this patch set. > > Thanks! > > > Hanks Chen > > > On Thu, 2020-07-30 at 21:04 +0800, Hanks Chen wrote: > > Hi all, > > > > Gentle ping on this patch. > > > > Thanks! > > > > Hanks Chen > > > > > > On Wed, 2020-07-22 at 17:21 +0200, Matthias Brugger wrote: > > > > > > On 22/07/2020 13:16, Hanks Chen wrote: > > > > On Wed, 2020-07-22 at 10:43 +0200, Matthias Brugger wrote: > > > >> > > > >> On 22/07/2020 05:09, Hanks Chen wrote: > > > >>> remove the redundant clk interface of uart. > > > >>> CLK_INFRA_UART3 is a dummy clk interface, > > > >>> it has no effect on the operation of the read/write instruction. > > > >>> > > > >>> Change since v2: > > > >>> Commit "dt-bindings: clock: remove UART3 clock support" > > > >> > > > >> Sorry just another comment. I think we can make this one patch > > > >> deleting everything. > > > >> > > > > Sorry, I don't understand the comment. Do I need to merge them into one > > > > big patch? > > > > Btw, if I use one patch, I would get check patch fail. > > > > --- > > > > [2020-07-22 19:12:49,046 ERROR] Run check patch results: > > > > WARNING:DT_SPLIT_BINDING_PATCH: DT binding docs and includes should be a > > > > separate patch. See: > > > > Documentation/devicetree/bindings/submitting-patches.rst > > > > --- > > > > > > Hm, I think that's a debatable error message from checkpatch, but let's > > > leave it > > > as it is. > > > > > > Regards, > > > Matthias > > > > > > > > > > > > > > Hanks > > > > > > > >>> -- remove Fixes tag > > > >>> Commit "clk: mediatek: remove UART3 clock support" > > > >>> -- remove Fixes tag > > > >>> > > > >>> Hanks Chen (2): > > > >>> dt-bindings: clock: remove UART3 clock support > > > >>> clk: mediatek: remove UART3 clock support > > > >>> > > > >>>drivers/clk/mediatek/clk-mt6779.c | 2 -- > > > >>>include/dt-bindings/clock/mt6779-clk.h | 1 - > > > >>>2 files changed, 3 deletions(-) > > > >>> > > > > > > > > ___ > > Linux-mediatek mailing list > > linux-media...@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: Re: [PATCH v2 0/2] Remove MT6779 UART3 clock support
Hi all, Gentle ping on this patch set. Thanks! Hanks Chen On Thu, 2020-07-30 at 21:04 +0800, Hanks Chen wrote: > Hi all, > > Gentle ping on this patch. > > Thanks! > > Hanks Chen > > > On Wed, 2020-07-22 at 17:21 +0200, Matthias Brugger wrote: > > > > On 22/07/2020 13:16, Hanks Chen wrote: > > > On Wed, 2020-07-22 at 10:43 +0200, Matthias Brugger wrote: > > >> > > >> On 22/07/2020 05:09, Hanks Chen wrote: > > >>> remove the redundant clk interface of uart. > > >>> CLK_INFRA_UART3 is a dummy clk interface, > > >>> it has no effect on the operation of the read/write instruction. > > >>> > > >>> Change since v2: > > >>> Commit "dt-bindings: clock: remove UART3 clock support" > > >> > > >> Sorry just another comment. I think we can make this one patch deleting > > >> everything. > > >> > > > Sorry, I don't understand the comment. Do I need to merge them into one > > > big patch? > > > Btw, if I use one patch, I would get check patch fail. > > > --- > > > [2020-07-22 19:12:49,046 ERROR] Run check patch results: > > > WARNING:DT_SPLIT_BINDING_PATCH: DT binding docs and includes should be a > > > separate patch. See: > > > Documentation/devicetree/bindings/submitting-patches.rst > > > --- > > > > Hm, I think that's a debatable error message from checkpatch, but let's > > leave it > > as it is. > > > > Regards, > > Matthias > > > > > > > > > > Hanks > > > > > >>> -- remove Fixes tag > > >>> Commit "clk: mediatek: remove UART3 clock support" > > >>> -- remove Fixes tag > > >>> > > >>> Hanks Chen (2): > > >>> dt-bindings: clock: remove UART3 clock support > > >>> clk: mediatek: remove UART3 clock support > > >>> > > >>>drivers/clk/mediatek/clk-mt6779.c | 2 -- > > >>>include/dt-bindings/clock/mt6779-clk.h | 1 - > > >>>2 files changed, 3 deletions(-) > > >>> > > > > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Hi all,
Gentle ping on this patch.
Thanks
Hanks Chen
On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin
> Signed-off-by: Hanks Chen
> Reviewed-by: Matthias Brugger
> ---
> drivers/clk/mediatek/clk-mt6779.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/mediatek/clk-mt6779.c
> b/drivers/clk/mediatek/clk-mt6779.c
> index 9766cccf5844..6e0d3a166729 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> "pwm_sel", 19),
> GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> "pwm_sel", 21),
> + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> + "uart_sel", 22),
> GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> "uart_sel", 23),
> GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
Re: [PATCH] pinctrl: mediatek: check mtk_is_virt_gpio input parameter
On Wed, 2020-08-19 at 16:43 -0700, Sean Wang wrote:
> Hi Hanks,
>
> On Thu, Aug 13, 2020 at 4:14 AM Hanks Chen wrote:
> >
> > check mtk_is_virt_gpio input parameter,
> > virtual gpio need to support eint mode.
> >
> > add error handler for the ko case
> > to fix this boot fail:
> > pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
> > lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]
>
> it is better we post the complete call stack when the failure occurs
>
> >
> > Fixes: edd546465002 ("pinctrl: mediatek: avoid virtual gpio trying to set
> > reg")
> > Singed-off-by: sin_jieyang
>
> signed-off-by with the full name
Got it, I'll update it in next version.
>
> > Signed-off-by: Hanks Chen
> > ---
> > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> > b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> > index c53e2c391e32..27ab9c512ae1 100644
> > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> > @@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned
> > int gpio_n)
> >
> > desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
> >
> > + /* if the GPIO is not supported for eint mode */
> > + if (desc->eint.eint_m == EINT_NA)
>
> s/NO_EINT_SUPPORT/EINT_NA/ to align with pinctrl/mediatek/pinctrl-mtk-mt*.h
> uses
Got it, I'll fix it in next version.
Thanks for your reply
Hanks
>
> > + return virt_gpio;
> > +
> > if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
> > virt_gpio = true;
> >
> > --
> > 2.18.0
[PATCH v2] pinctrl: mediatek: check mtk_is_virt_gpio input parameter
check mtk_is_virt_gpio input parameter,
virtual gpio need to support eint mode.
add error handler for the ko case
to fix this boot fail:
pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]
Fixes: edd546465002 ("pinctrl: mediatek: avoid virtual gpio trying to set reg")
Singed-off-by: Jie Yang
Signed-off-by: Hanks Chen
---
Changes since v1:
- update Singed-off-by
- align with pinctrl/mediatek/pinctrl-mtk-mt*.h
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index c53e2c391e32..a485d79f51a1 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int
gpio_n)
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+ /* if the GPIO is not supported for eint mode */
+ if (desc->eint.eint_m == NO_EINT_SUPPORT)
+ return virt_gpio;
+
if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
virt_gpio = true;
--
2.18.0
[PATCH] pinctrl: mediatek: check mtk_is_virt_gpio input parameter
check mtk_is_virt_gpio input parameter,
virtual gpio need to support eint mode.
add error handler for the ko case
to fix this boot fail:
pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]
Fixes: edd546465002 ("pinctrl: mediatek: avoid virtual gpio trying to set reg")
Singed-off-by: sin_jieyang
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index c53e2c391e32..27ab9c512ae1 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int
gpio_n)
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+ /* if the GPIO is not supported for eint mode */
+ if (desc->eint.eint_m == EINT_NA)
+ return virt_gpio;
+
if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
virt_gpio = true;
--
2.18.0
Re: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779
Hi Matthias and all,
Gentle ping on this patch.
Thanks
Hanks Chen
On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> this adds initial MT6779 dts settings for board support,
> including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
>
> Signed-off-by: Hanks Chen
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> 3 files changed, 303 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> b/arch/arm64/boot/dts/mediatek/Makefile
> index a57af9da9f5c..4d1b0f9d8d1c 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> new file mode 100644
> index ..164f5cbb3821
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Mars.C
> + *
> + */
> +
> +/dts-v1/;
> +#include "mt6779.dtsi"
> +
> +/ {
> + model = "MediaTek MT6779 EVB";
> + compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
> +
> + aliases {
> + serial0 =
> + };
> +
> + memory@4000 {
> + device_type = "memory";
> + reg = <0 0x4000 0 0x1e80>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +};
> +
> + {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> new file mode 100644
> index ..370f309d32de
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -0,0 +1,271 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Mars.C
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + compatible = "mediatek,mt6779";
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x000>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x100>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x200>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x300>;
> + };
> +
> + cpu4: cpu@4 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x400>;
> + };
> +
> + cpu5: cpu@5 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> +
[PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC
Change since v10: Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC" -- remove the patches which were applied to linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b07b616214857c9db01e2807cde2f6bba8019fc3 -- follow the latest 'dt-schema' and fix the dts sample Change since v9: Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC" -- remove driving desciprtion and reuse the generic schemas. Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- fix build error to support ko. -- follow the APIs as below. Commit "arm64: dts: add dts nodes for MT6779" -- remove the clk interface of UART3 in another mail thread. https://lkml.org/lkml/2020/7/21/1444 Change since v8: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- update the format Commit "arm64: dts: add dts nodes for MT6779" -- fix the typo in uart node Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (2): arm64: dts: add dts nodes for MT6779 clk: mediatek: add UART0 clock support .../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 ++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++ drivers/clk/mediatek/clk-mt6779.c | 2 + 5 files changed, 507 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi -- 2.18.0
[PATCH v10 2/3] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9da9f5c..4d1b0f9d8d1c 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index ..164f5cbb3821
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index ..370f309d32de
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
[PATCH v10 3/3] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6779.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766cccf5844..6e0d3a166729 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
--
2.18.0
[PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 ++
1 file changed, 202 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index ..152c151c27ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+const: mediatek,mt6779-pinctrl
+
+ reg:
+minItems: 9
+maxItems: 9
+
+ reg-names:
+items:
+ - const: "gpio"
+ - const: "iocfg_rm"
+ - const: "iocfg_br"
+ - const: "iocfg_lm"
+ - const: "iocfg_lb"
+ - const: "iocfg_rt"
+ - const: "iocfg_lt"
+ - const: "iocfg_tl"
+ - const: "eint"
+
+ gpio-controller: true
+
+ "#gpio-cells":
+const: 2
+description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the
below
+ mentioned gpio binding representation for description of particular
cells.
+
+ gpio-ranges:
+minItems: 1
+maxItems: 5
+description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+maxItems: 1
+description: |
+ Specifies the summary IRQ.
+
+ "#interrupt-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]*$':
+type: object
+patternProperties:
+ '-pins*$':
+type: object
+description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
muxer
+ configuration, pullups, drive strength, input enable/disable and
input schmitt.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pinmux:
+description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
defined
+ as macros in boot/dts/-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ input-disable: true
+
+ output-low: true
+
+ output-high: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ mediatek,pull-up-adv:
+description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+required:
+ - pinmux
+
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
Re: [PATCH v2 0/2] Remove MT6779 UART3 clock support
Hi all, Gentle ping on this patch. Thanks! Hanks Chen On Wed, 2020-07-22 at 17:21 +0200, Matthias Brugger wrote: > > On 22/07/2020 13:16, Hanks Chen wrote: > > On Wed, 2020-07-22 at 10:43 +0200, Matthias Brugger wrote: > >> > >> On 22/07/2020 05:09, Hanks Chen wrote: > >>> remove the redundant clk interface of uart. > >>> CLK_INFRA_UART3 is a dummy clk interface, > >>> it has no effect on the operation of the read/write instruction. > >>> > >>> Change since v2: > >>> Commit "dt-bindings: clock: remove UART3 clock support" > >> > >> Sorry just another comment. I think we can make this one patch deleting > >> everything. > >> > > Sorry, I don't understand the comment. Do I need to merge them into one > > big patch? > > Btw, if I use one patch, I would get check patch fail. > > --- > > [2020-07-22 19:12:49,046 ERROR] Run check patch results: > > WARNING:DT_SPLIT_BINDING_PATCH: DT binding docs and includes should be a > > separate patch. See: > > Documentation/devicetree/bindings/submitting-patches.rst > > --- > > Hm, I think that's a debatable error message from checkpatch, but let's leave > it > as it is. > > Regards, > Matthias > > > > > > Hanks > > > >>> -- remove Fixes tag > >>> Commit "clk: mediatek: remove UART3 clock support" > >>> -- remove Fixes tag > >>> > >>> Hanks Chen (2): > >>> dt-bindings: clock: remove UART3 clock support > >>> clk: mediatek: remove UART3 clock support > >>> > >>>drivers/clk/mediatek/clk-mt6779.c | 2 -- > >>>include/dt-bindings/clock/mt6779-clk.h | 1 - > >>>2 files changed, 3 deletions(-) > >>> > >
Re: [PATCH v9 6/7] arm64: dts: add dts nodes for MT6779
Hi Matthias and all,
gentle ping for this patch.
If no new comments, I would like to send a newer version for the series.
Thanks.
Hanks Chen
On Thu, 2020-07-23 at 19:19 +0800, Hanks Chen wrote:
> this adds initial MT6779 dts settings for board support,
> including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
>
> Signed-off-by: Hanks Chen
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> 3 files changed, 303 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> b/arch/arm64/boot/dts/mediatek/Makefile
> index a57af9da9f5c..4d1b0f9d8d1c 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> new file mode 100644
> index ..164f5cbb3821
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Mars.C
> + *
> + */
> +
> +/dts-v1/;
> +#include "mt6779.dtsi"
> +
> +/ {
> + model = "MediaTek MT6779 EVB";
> + compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
> +
> + aliases {
> + serial0 =
> + };
> +
> + memory@4000 {
> + device_type = "memory";
> + reg = <0 0x4000 0 0x1e80>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +};
> +
> + {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> new file mode 100644
> index ..370f309d32de
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -0,0 +1,271 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Mars.C
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + compatible = "mediatek,mt6779";
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x000>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x100>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x200>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x300>;
> + };
> +
> + cpu4: cpu@4 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + reg = <0x400>;
> + };
> +
> + cpu5: cpu@5 {
> + device_type = "cpu";
> + compatible = "arm,corte
Re: [PATCH v9 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu, 2020-07-23 at 09:51 -0600, Rob Herring wrote: > On Thu, 23 Jul 2020 19:19:52 +0800, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Reviewed-by: Rob Herring > > Signed-off-by: Andy Teng > > Signed-off-by: Hanks Chen > > --- > > .../pinctrl/mediatek,mt6779-pinctrl.yaml | 197 ++ > > 1 file changed, 197 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:0: [0, 268455936, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:1: [0, 297926656, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:2: [0, 298909696, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:3: [0, 300023808, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:4: [0, 300351488, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:5: [0, 300548096, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:6: [0, 301072384, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:7: [0, 301137920, 0, 4096] is too long > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml: > example-0: pinctrl@10005000:reg:8: [0, 268480512, 0, 4096] is too long > > > See > https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/1334743__;!!CTRNKA9wMg0ARbw!xVq21s-Vaw3If1-Q8EWJEDBBIUp0j30PIaGQWDyhCftbcOgFrjRqZMNHoHgOXksD3g$ > > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master > --upgrade > > Please check and re-submit. > Hi Rob, It's my fault I could reproduce the error log after dt-schema updates to the latest version. I'll fix it in next version. Thanks! Hanks Chen
Re: [PATCH v3 4/4] irqchip/mtk-cirq: Convert to a platform driver
On Fri, 2020-07-17 at 17:06 -0700, Saravana Kannan wrote:
> This driver can work as a platform driver. So covert it to a platform
> driver.
>
> Signed-off-by: Saravana Kannan
> ---
> drivers/irqchip/irq-mtk-cirq.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
> index 69ba8ce3c178..62a61275aaa3 100644
> --- a/drivers/irqchip/irq-mtk-cirq.c
> +++ b/drivers/irqchip/irq-mtk-cirq.c
> @@ -295,4 +295,6 @@ static int __init mtk_cirq_of_init(struct device_node
> *node,
> return ret;
> }
>
> -IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);
> +IRQCHIP_PLATFORM_DRIVER_BEGIN(mtk_cirq)
> +IRQCHIP_MATCH("mediatek,mtk-cirq", mtk_cirq_of_init)
> +IRQCHIP_PLATFORM_DRIVER_END(mtk_cirq)
Hi Saravana,
Looks good for me to convert cirq to a platform.
Thank you for your patch.
Reviewed-by: Hanks Chen
Hanks Chen
Re: [PATCH v3 3/4] irqchip/mtk-sysirq: Convert to a platform driver
On Fri, 2020-07-17 at 17:06 -0700, Saravana Kannan wrote:
> This driver can work as a platform driver. So covert it to a platform
> driver.
>
> Signed-off-by: Saravana Kannan
> ---
> drivers/irqchip/irq-mtk-sysirq.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mtk-sysirq.c
> b/drivers/irqchip/irq-mtk-sysirq.c
> index 6ff98b87e5c0..7299c5ab4d10 100644
> --- a/drivers/irqchip/irq-mtk-sysirq.c
> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> @@ -231,4 +231,6 @@ static int __init mtk_sysirq_of_init(struct device_node
> *node,
> kfree(chip_data);
> return ret;
> }
> -IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
> +IRQCHIP_PLATFORM_DRIVER_BEGIN(mtk_sysirq)
> +IRQCHIP_MATCH("mediatek,mt6577-sysirq", mtk_sysirq_of_init)
> +IRQCHIP_PLATFORM_DRIVER_END(mtk_sysirq)
Hi Saravana,
Looks good for me to convert it to a platform.
Thank you for your patch.
Reviewed-by: Hanks Chen
Hanks Chen
Re: [PATCH 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu, 2020-07-16 at 15:26 +0200, Linus Walleij wrote: > On Tue, Jul 14, 2020 at 11:04 AM Hanks Chen wrote: > > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > (...) > > Please make an attempt to reuse the generic schemas in > Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml > Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml > > See how other bindings reuse them, e.g.: > qcom,ipq6018-pinctrl.yaml > > Yours, > Linus Walleij Got it, I'll fix it in next version https://lkml.org/lkml/2020/7/23/385 Thank you for your reply Hanks Chen
[PATCH v9 0/7] Add basic SoC Support for Mediatek MT6779 SoC
Change since v9: Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC" -- remove driving desciprtion and reuse the generic schemas. Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- fix build error to support ko. -- follow the APIs as below. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pinctrl/mediatek?h=v5.8-rc6=cafe19db7751269bf6b4dd2148cbfa9fbe91d651 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/pinctrl/mediatek?h=v5.8-rc6=5f755e1f1efe5ca3b475b14169e6e85bf1411bb5 Commit "arm64: dts: add dts nodes for MT6779" -- remove the clk interface of UART3 in another mail thread. https://lkml.org/lkml/2020/7/21/1444 Change since v8: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- update the format Commit "arm64: dts: add dts nodes for MT6779" -- fix the typo in uart node Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support arm64: dts: add dts nodes for MT6779 clk: mediatek: add UART0 clock support .../pinctrl/mediatek,mt6779-pinctrl.yaml | 197 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 785 +++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 + drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 13 files changed, 4660 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h -- 2.18.0
[PATCH v9 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 777 ++
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +
4 files changed, 2875 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index f32d3644c509..1cedc5f2aadb 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -93,6 +93,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 4b7132876e71..b0b07c541d11 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
new file mode 100644
index ..ede185b58d41
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -0,0 +1,777 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng
+ *
+ */
+
+#include
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1,
+ * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA,
+ * iocfg_lt:0x11F2, iocfg_tl:0x11F3
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0,
[PATCH v9 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Reviewed-by: Rob Herring
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 197 ++
1 file changed, 197 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index ..2b304fe26d8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,197 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+const: mediatek,mt6779-pinctrl
+
+ reg:
+minItems: 9
+maxItems: 9
+
+ reg-names:
+items:
+ - const: "gpio"
+ - const: "iocfg_rm"
+ - const: "iocfg_br"
+ - const: "iocfg_lm"
+ - const: "iocfg_lb"
+ - const: "iocfg_rt"
+ - const: "iocfg_lt"
+ - const: "iocfg_tl"
+ - const: "eint"
+
+ gpio-controller: true
+
+ "#gpio-cells":
+const: 2
+description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the
below
+ mentioned gpio binding representation for description of particular
cells.
+
+ gpio-ranges:
+minItems: 1
+maxItems: 5
+description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+maxItems: 1
+description: |
+ Specifies the summary IRQ.
+
+ "#interrupt-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]*$':
+type: object
+patternProperties:
+ '-pins*$':
+type: object
+description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
muxer
+ configuration, pullups, drive strength, input enable/disable and
input schmitt.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pinmux:
+description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
defined
+ as macros in boot/dts/-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ input-disable: true
+
+ output-low: true
+
+ output-high: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ mediatek,pull-up-adv:
+description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+required:
+ - pinmux
+
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+pio: pinctrl@10005000 {
+compatible = "me
[PATCH v9 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 +++
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
drivers/pinctrl/mediatek/pinctrl-paris.c | 7 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b77b18fe5adc..c53e2c391e32 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned
long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 27df08736396..bd079f4fb1d6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 90a432bf9fed..a23c18251965 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip,
unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+* "Virtual" GPIOs are always and only used for interrupts
+* Since they are only used for interrupts, they are always inputs
+*/
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, );
--
2.18.0
[PATCH v9 7/7] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6779.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766cccf5844..6e0d3a166729 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
--
2.18.0
[PATCH v9 1/7] pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Mars Cheng Signed-off-by: Andy Teng Signed-off-by: Hanks Chen --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index ..87fdc4310936 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9
[PATCH v9 6/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9da9f5c..4d1b0f9d8d1c 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index ..164f5cbb3821
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index ..370f309d32de
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
[PATCH v9 5/7] pinctrl: mediatek: add mt6779 eint support
add driver setting to support mt6779 eint
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index ede185b58d41..bb0851c73304 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -732,11 +732,19 @@ static const char * const
mt6779_pinctrl_register_base_names[] = {
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num= 195,
+ .db_cnt= 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = _eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
2.18.0
Re: [PATCH v2 0/2] Remove MT6779 UART3 clock support
On Wed, 2020-07-22 at 10:43 +0200, Matthias Brugger wrote: > > On 22/07/2020 05:09, Hanks Chen wrote: > > remove the redundant clk interface of uart. > > CLK_INFRA_UART3 is a dummy clk interface, > > it has no effect on the operation of the read/write instruction. > > > > Change since v2: > > Commit "dt-bindings: clock: remove UART3 clock support" > > Sorry just another comment. I think we can make this one patch deleting > everything. > Sorry, I don't understand the comment. Do I need to merge them into one big patch? Btw, if I use one patch, I would get check patch fail. --- [2020-07-22 19:12:49,046 ERROR] Run check patch results: WARNING:DT_SPLIT_BINDING_PATCH: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst --- Hanks > > -- remove Fixes tag > > Commit "clk: mediatek: remove UART3 clock support" > > -- remove Fixes tag > > > > Hanks Chen (2): > >dt-bindings: clock: remove UART3 clock support > >clk: mediatek: remove UART3 clock support > > > > drivers/clk/mediatek/clk-mt6779.c | 2 -- > > include/dt-bindings/clock/mt6779-clk.h | 1 - > > 2 files changed, 3 deletions(-) > >
[PATCH v2 0/2] Remove MT6779 UART3 clock support
remove the redundant clk interface of uart. CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the operation of the read/write instruction. Change since v2: Commit "dt-bindings: clock: remove UART3 clock support" -- remove Fixes tag Commit "clk: mediatek: remove UART3 clock support" -- remove Fixes tag Hanks Chen (2): dt-bindings: clock: remove UART3 clock support clk: mediatek: remove UART3 clock support drivers/clk/mediatek/clk-mt6779.c | 2 -- include/dt-bindings/clock/mt6779-clk.h | 1 - 2 files changed, 3 deletions(-) -- 2.18.0
Re: [PATCH 1/2] dt-bindings: clock: remove UART3 clock support
On Wed, 2020-07-22 at 00:10 +0200, Matthias Brugger wrote:
>
> On 21/07/2020 07:40, Hanks Chen wrote:
> > remove the redundant clk interface of uart.
> >
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
>
> These are cosmetic changes. They don't fix any bug, so we won't need a Fixes
> tag
> here. Neither on 2/2.
>
> Regards,
> Matthias
>
Got it, I'll remove it in next version.
Thanks!
Hanks
> > Signed-off-by: Hanks Chen
> > ---
> > include/dt-bindings/clock/mt6779-clk.h | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/include/dt-bindings/clock/mt6779-clk.h
> > b/include/dt-bindings/clock/mt6779-clk.h
> > index b083139afbd2..2b5f2354d7eb 100644
> > --- a/include/dt-bindings/clock/mt6779-clk.h
> > +++ b/include/dt-bindings/clock/mt6779-clk.h
> > @@ -229,7 +229,6 @@
> > #define CLK_INFRA_UART0 21
> > #define CLK_INFRA_UART1 22
> > #define CLK_INFRA_UART2 23
> > -#define CLK_INFRA_UART324
> > #define CLK_INFRA_GCE_26M 25
> > #define CLK_INFRA_CQ_DMA_FPC 26
> > #define CLK_INFRA_BTIF27
> >
[PATCH v2 2/2] clk: mediatek: remove UART3 clock support
CLK_INFRA_UART3 is a dummy clk interface,
it has no effect on the operation of the read/write instruction.
Signed-off-by: Hanks Chen
---
drivers/clk/mediatek/clk-mt6779.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766cccf5844..75f2235486be 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -923,8 +923,6 @@ static const struct mtk_gate infra_clks[] = {
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
"uart_sel", 24),
- GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
- "uart_sel", 25),
GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
"axi_sel", 27),
GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
--
2.18.0
[PATCH v2 1/2] dt-bindings: clock: remove UART3 clock support
remove the redundant clk interface of uart. Signed-off-by: Hanks Chen --- include/dt-bindings/clock/mt6779-clk.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/clock/mt6779-clk.h b/include/dt-bindings/clock/mt6779-clk.h index b083139afbd2..2b5f2354d7eb 100644 --- a/include/dt-bindings/clock/mt6779-clk.h +++ b/include/dt-bindings/clock/mt6779-clk.h @@ -229,7 +229,6 @@ #define CLK_INFRA_UART021 #define CLK_INFRA_UART122 #define CLK_INFRA_UART223 -#define CLK_INFRA_UART324 #define CLK_INFRA_GCE_26M 25 #define CLK_INFRA_CQ_DMA_FPC 26 #define CLK_INFRA_BTIF 27 -- 2.18.0
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On Mon, 2020-07-20 at 18:13 +0200, Matthias Brugger wrote:
>
> On 16/07/2020 06:04, Hanks Chen wrote:
> > On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
> >>
> >> On 14/07/2020 11:20, Hanks Chen wrote:
> >>> this adds initial MT6779 dts settings for board support,
> >>> including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >>>
> >>> Signed-off-by: Hanks Chen
> >>> ---
> >>>arch/arm64/boot/dts/mediatek/Makefile | 1 +
> >>>arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> >>>arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> >>>3 files changed, 303 insertions(+)
> >>>create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>>create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>>
> >> [...]
> >>> +
> >>> + uart0: serial@11002000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11002000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART0>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart1: serial@11003000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11003000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART1>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart2: serial@11004000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11004000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART2>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>
> >> Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
> >> MT6779. So we should list them all here.
> >>
> >
> > Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
> > header file of clk.
>
> Correct, I got confused by the four clocks.
> With that clarified I'm fine with the patch and will take it as soon as the
> clock driver patch is accepted.
>
> Regards,
> Matthias
>
Got it, I send a new serial to fix the redundant UART clk
https://lkml.org/lkml/2020/7/21/45
Thanks
Hanks Chen
> > CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
> > operation of the read/write instruction.
> >
> > If you think it is not good, I can remove it in the header file of clk.
> >
> > Thanks
> >
> >> Regards,
> >> Matthias
> >
[PATCH 0/2] Remove MT6779 UART3 clock support
remove the redundant clk interface of uart. CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the operation of the read/write instruction. Hanks Chen (2): dt-bindings: clock: remove UART3 clock support clk: mediatek: remove UART3 clock support drivers/clk/mediatek/clk-mt6779.c | 2 -- include/dt-bindings/clock/mt6779-clk.h | 1 - 2 files changed, 3 deletions(-) -- 2.18.0
[PATCH 1/2] dt-bindings: clock: remove UART3 clock support
remove the redundant clk interface of uart.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Hanks Chen
---
include/dt-bindings/clock/mt6779-clk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/dt-bindings/clock/mt6779-clk.h
b/include/dt-bindings/clock/mt6779-clk.h
index b083139afbd2..2b5f2354d7eb 100644
--- a/include/dt-bindings/clock/mt6779-clk.h
+++ b/include/dt-bindings/clock/mt6779-clk.h
@@ -229,7 +229,6 @@
#define CLK_INFRA_UART021
#define CLK_INFRA_UART122
#define CLK_INFRA_UART223
-#define CLK_INFRA_UART324
#define CLK_INFRA_GCE_26M 25
#define CLK_INFRA_CQ_DMA_FPC 26
#define CLK_INFRA_BTIF 27
--
2.18.0
[PATCH 2/2] clk: mediatek: remove UART3 clock support
CLK_INFRA_UART3 is a dummy clk interface,
it has no effect on the operation of the read/write instruction.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Hanks Chen
---
drivers/clk/mediatek/clk-mt6779.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766cccf5844..75f2235486be 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -923,8 +923,6 @@ static const struct mtk_gate infra_clks[] = {
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
"uart_sel", 24),
- GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
- "uart_sel", 25),
GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
"axi_sel", 27),
GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
--
2.18.0
Re: linux-next: build failure after merge of the pinctrl tree
On Fri, 2020-07-17 at 17:16 +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the pinctrl tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/pinctrl/mediatek/pinctrl-mt6779.c:783:1: warning: data definition has
> no type or storage class
> 783 | arch_initcall(mt6779_pinctrl_init);
> | ^
> drivers/pinctrl/mediatek/pinctrl-mt6779.c:783:1: error: type defaults to
> 'int' in declaration of 'arch_initcall' [-Werror=implicit-int]
> drivers/pinctrl/mediatek/pinctrl-mt6779.c:783:1: warning: parameter names
> (without types) in function declaration
> drivers/pinctrl/mediatek/pinctrl-mt6779.c:779:19: warning:
> 'mt6779_pinctrl_init' defined but not used [-Wunused-function]
> 779 | static int __init mt6779_pinctrl_init(void)
> | ^~~
>
> Caused by commit
>
> e6f744c6ad4f ("pinctrl: mediatek: add pinctrl support for MT6779 SoC")
>
> Forgot to include module.h (since it is tristate in Kconfig) or init.h?
>
> I used the pinctrl tree from next-20200716 for today.
>
My fault, I'll fix it in next version.
(Series: Add basic SoC Support for Mediatek MT6779 SoC)
Thank you for your message
Hanks Chen
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
>
> On 14/07/2020 11:20, Hanks Chen wrote:
> > this adds initial MT6779 dts settings for board support,
> > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >
> > Signed-off-by: Hanks Chen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> > 3 files changed, 303 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> [...]
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART0>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART1>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11004000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART2>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
>
> Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
> MT6779. So we should list them all here.
>
Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
header file of clk.
CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
operation of the read/write instruction.
If you think it is not good, I can remove it in the header file of clk.
Thanks
> Regards,
> Matthias
[PATCH v8 1/7] pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Mars Cheng Signed-off-by: Andy Teng Signed-off-by: Hanks Chen --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index ..87fdc4310936 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9
[PATCH v8 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 ++
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +
4 files changed, 2873 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index f32d3644c509..1cedc5f2aadb 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -93,6 +93,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 4b7132876e71..b0b07c541d11 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
new file mode 100644
index ..145bf2294ce1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng
+ *
+ */
+
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1,
+ * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA,
+ * iocfg_lt:0x11F2, iocfg_tl:0x11F3
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(6
[PATCH v8 7/7] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6779.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766cccf5844..6e0d3a166729 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
--
2.18.0
[PATCH v8 5/7] pinctrl: mediatek: add mt6779 eint support
add driver setting to support mt6779 eint
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf2294ce1..32822603a1df 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@ static const char * const
mt6779_pinctrl_register_base_names[] = {
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num= 195,
+ .db_cnt= 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = _eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
2.18.0
[PATCH v8 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 +++
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
drivers/pinctrl/mediatek/pinctrl-paris.c | 7 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b77b18fe5adc..c53e2c391e32 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned
long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 27df08736396..bd079f4fb1d6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 90a432bf9fed..a23c18251965 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip,
unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+* "Virtual" GPIOs are always and only used for interrupts
+* Since they are only used for interrupts, they are always inputs
+*/
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, );
--
2.18.0
[PATCH v8 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng Signed-off-by: Hanks Chen --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 203 ++ 1 file changed, 203 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index ..77b715ff61b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: +const: mediatek,mt6779-pinctrl + + reg: +minItems: 9 +maxItems: 9 + + reg-names: +items: + - const: "gpio" + - const: "iocfg_rm" + - const: "iocfg_br" + - const: "iocfg_lm" + - const: "iocfg_lb" + - const: "iocfg_rt" + - const: "iocfg_lt" + - const: "iocfg_tl" + - const: "eint" + + gpio-controller: true + + "#gpio-cells": +const: 2 +description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: +minItems: 1 +maxItems: 5 +description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: +maxItems: 1 +description: | + Specifies the summary IRQ. + + "#interrupt-cells": +const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': +type: object +patternProperties: + '-pins*$': +type: object +description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. +$ref: pinmux-node.yaml# + +properties: + pinmux: +description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,pull-up-adv: +description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +$ref: /schemas/types.yaml#/definitions/uint32 +enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: +description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +$ref: /schemas/types.yaml#/definitions/uint32 +enum: [0, 1, 2, 3] + + drive-strength: +description: | + Selects the drive strength for the specified pins in mA. +$ref: /schemas/types.yaml#/definitions/uint32 +enum: [2, 4, 6, 8, 10, 12, 14, 16] + +required: + - pinmux + +add
[PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9da9f5c..4d1b0f9d8d1c 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index ..164f5cbb3821
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index ..370f309d32de
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
[PATCH v8 0/7] Add basic SoC Support for Mediatek MT6779 SoC
Change since v8: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- update the format Commit "arm64: dts: add dts nodes for MT6779" -- fix the typo in uart node Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support arm64: dts: add dts nodes for MT6779 clk: mediatek: add UART0 clock support .../pinctrl/mediatek,mt6779-pinctrl.yaml | 203 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 +++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 + drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 13 files changed, 4664 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h -- 2.18.0
[PATCH 1/7] pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Mars Cheng Signed-off-by: Andy Teng Signed-off-by: Hanks Chen --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 000..87fdc43 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9
[PATCH 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +
4 files changed, 2873 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index f32d364..1cedc5f 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -93,6 +93,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 4b71328..b0b07c5 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
new file mode 100644
index 000..145bf22
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng
+ *
+ */
+
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1,
+ * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA,
+ * iocfg_lt:0x11F2, iocfg_tl:0x11F3
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10
[PATCH 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 +
drivers/pinctrl/mediatek/pinctrl-paris.c |7 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b77b18f..c53e2c3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned
long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 27df087..bd079f4f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 90a432b..a23c182 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip,
unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+* "Virtual" GPIOs are always and only used for interrupts
+* Since they are only used for interrupts, they are always inputs
+*/
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, );
--
1.7.9.5
[PATCH 6/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile |1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271 +++
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9d..4d1b0f9 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index 000..164f5cb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index 000..370f309
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
[PATCH 5/7] pinctrl: mediatek: add mt6779 eint support
add driver setting to support mt6779 eint
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf22..3282260 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num= 195,
+ .db_cnt= 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = _eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
1.7.9.5
[PATCH 7/7] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6779.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766ccc..6e0d3a1 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
--
1.7.9.5
[PATCH 0/7] Add basic SoC Support for Mediatek MT6779 SoC
Change since v8: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- update the format Commit "arm64: dts: add dts nodes for MT6779" -- fix the typo in uart node Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support arm64: dts: add dts nodes for MT6779 clk: mediatek: add UART0 clock support .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 203 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts| 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 13 files changed, 4664 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h -- 1.7.9.5
[PATCH 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Signed-off-by: Andy Teng
---
.../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 203
1 file changed, 203 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index 000..77b715f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+const: mediatek,mt6779-pinctrl
+
+ reg:
+minItems: 9
+maxItems: 9
+
+ reg-names:
+items:
+ - const: "gpio"
+ - const: "iocfg_rm"
+ - const: "iocfg_br"
+ - const: "iocfg_lm"
+ - const: "iocfg_lb"
+ - const: "iocfg_rt"
+ - const: "iocfg_lt"
+ - const: "iocfg_tl"
+ - const: "eint"
+
+ gpio-controller: true
+
+ "#gpio-cells":
+const: 2
+description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the
below
+ mentioned gpio binding representation for description of particular
cells.
+
+ gpio-ranges:
+minItems: 1
+maxItems: 5
+description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+maxItems: 1
+description: |
+ Specifies the summary IRQ.
+
+ "#interrupt-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]*$':
+type: object
+patternProperties:
+ '-pins*$':
+type: object
+description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
muxer
+ configuration, pullups, drive strength, input enable/disable and
input schmitt.
+$ref: pinmux-node.yaml#
+
+properties:
+ pinmux:
+description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
defined
+ as macros in boot/dts/-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ input-disable: true
+
+ output-low: true
+
+ output-high: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ mediatek,pull-up-adv:
+description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as
below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+
+ drive-strength:
+description: |
+ Selects the drive strength for the specified pins in mA.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+required:
+ - pinmux
+
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+pio: pinctrl@10005000 {
+compatible =
Re: [PATCH v7 7/7] arm64: dts: add dts nodes for MT6779
On Fri, 2020-07-10 at 15:47 +0200, Matthias Brugger wrote:
>
> On 02/07/2020 14:57, Hanks Chen wrote:
> > this adds initial MT6779 dts settings for board support,
> > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >
> > Signed-off-by: Hanks Chen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile |1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> > +++
> > 3 files changed, 303 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> [...]
> > +
> > + uart2: serial@11004000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART1>;
>
> I suppose that should be:
>
> clocks = <>, <_ao CLK_INFRA_UART2>;
>
My fault, I'll fix the typo in next version.
Thanks!
Hanks
>
> Regards,
> Matthias
>
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + audio: clock-controller@1121 {
> > + compatible = "mediatek,mt6779-audio", "syscon";
> > + reg = <0 0x1121 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + mfgcfg: clock-controller@13fbf000 {
> > + compatible = "mediatek,mt6779-mfgcfg", "syscon";
> > + reg = <0 0x13fbf000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + mmsys: syscon@1400 {
> > + compatible = "mediatek,mt6779-mmsys", "syscon";
> > + reg = <0 0x1400 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + imgsys: clock-controller@1502 {
> > + compatible = "mediatek,mt6779-imgsys", "syscon";
> > + reg = <0 0x1502 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + vdecsys: clock-controller@1600 {
> > + compatible = "mediatek,mt6779-vdecsys", "syscon";
> > + reg = <0 0x1600 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + vencsys: clock-controller@1700 {
> > + compatible = "mediatek,mt6779-vencsys", "syscon";
> > + reg = <0 0x1700 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + camsys: clock-controller@1a00 {
> > + compatible = "mediatek,mt6779-camsys", "syscon";
> > + reg = <0 0x1a00 0 0x1>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + ipesys: clock-controller@1b00 {
> > + compatible = "mediatek,mt6779-ipesys", "syscon";
> > + reg = <0 0x1b00 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + };
> > +};
> >
Re: [PATCH v7] Add basic SoC Support for Mediatek MT6779 SoC
On Tue, 2020-07-07 at 13:41 +0200, Linus Walleij wrote: > On Thu, Jul 2, 2020 at 2:57 PM Hanks Chen wrote: > > > Change since v7: > > Commit "dt-bindings: pinctrl: add bindings for MediaTek" > > -- fix typo and change order of patch > > Commit "clk: mediatek: add UART0 clock support" > > -- add fixes tag and real name > > Commit "arm64: dts: add dts nodes for MT6779" > > -- expose all three UARTs in the dtsi > > Oh I see there are still development on this patch set so I took out > the patches I applied again. > > Waiting for the final reviewed version. > Thank you for taking a look over these so quickly! Got it, I'll send a newer version. Thanks! > Yours, > Linus Walleij
Re: [PATCH v7 0/7] Add basic SoC Support for Mediatek MT6779 SoC
Hi Michael, Stephen, Matthias and all, gentle ping for this patch set If no new comments, I would like to send a newer version for the series. patch set: https://lkml.org/lkml/2020/7/2/497 Thanks Hanks Chen On Thu, 2020-07-02 at 20:57 +0800, Hanks Chen wrote: > *** BLURB HERE *** > > Andy Teng (1): > dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC > > Hanks Chen (6): > pinctrl: mediatek: update pinmux definitions for mt6779 > pinctrl: mediatek: avoid virtual gpio trying to set reg > pinctrl: mediatek: add pinctrl support for MT6779 SoC > pinctrl: mediatek: add mt6779 eint support > clk: mediatek: add UART0 clock support > arm64: dts: add dts nodes for MT6779 > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++ > arch/arm64/boot/dts/mediatek/Makefile |1 + > arch/arm64/boot/dts/mediatek/mt6779-evb.dts| 31 + > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ > drivers/clk/mediatek/clk-mt6779.c |2 + > drivers/pinctrl/mediatek/Kconfig | 12 + > drivers/pinctrl/mediatek/Makefile |1 + > drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + > drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 > > drivers/pinctrl/mediatek/pinctrl-paris.c |7 + > include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 > 13 files changed, 4671 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h > create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h >
Re: [PATCH v7 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu, 2020-07-02 at 14:58 -0600, Rob Herring wrote: > On Thu, Jul 02, 2020 at 08:57:05PM +0800, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > --- > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 > > > > 1 file changed, 210 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > new file mode 100644 > > index 000..3a9fc4d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > @@ -0,0 +1,210 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml*__;Iw!!CTRNKA9wMg0ARbw!0474C4nwnSzS27r76why4qthf5712hrWflC57fdhSU7LzHZYpD7W0t5ZhJBgmnpF-A$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0474C4nwnSzS27r76why4qthf5712hrWflC57fdhSU7LzHZYpD7W0t5ZhJAzv-fiRw$ > > > > + > > +title: Mediatek MT6779 Pin Controller Device Tree Bindings > > + > > +maintainers: > > + - Andy Teng > > + > > +description: |+ > > + The pin controller node should be the child of a syscon node with the > > + required property: > > + - compatible: "syscon" > > + > > +properties: > > + compatible: > > +const: mediatek,mt6779-pinctrl > > + > > + reg: > > +minItems: 9 > > +maxItems: 9 > > +description: | > > + physical address base for gpio-related control registers. > > Need to describe what each entry is. > > items: > - description: ... > - description: ... > - description: ... > Got it, I'll add description in next version. Thanks! > > + > > + reg-names: > > +description: | > > + GPIO base register names. The names are "gpio", "iocfg_rm", > > + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", > > + "iocfg_tl", "eint"; > > The names should be a schema. > Got it, I'll fix it. > > > + > > + gpio-controller: true > > + > > + "#gpio-cells": > > +const: 2 > > +description: | > > + Number of cells in GPIO specifier. Since the generic GPIO > > + binding is used, the amount of cells must be specified as 2. See the > > below > > + mentioned gpio binding representation for description of particular > > cells. > > + > > + gpio-ranges: > > +minItems: 1 > > +maxItems: 5 > > +description: | > > + GPIO valid number range. > > + > > + interrupt-controller: true > > + > > + interrupts: > > +maxItems: 1 > > +description: | > > + Specifies the summary IRQ. > > + > > + "#interrupt-cells": > > +const: 2 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - gpio-controller > > + - "#gpio-cells" > > + - gpio-ranges > > + - interrupt-controller > > + - interrupts > > + - "#interrupt-cells" > > + > > +patternProperties: > > + '-[0-9]*$': > > +type: object > > +patternProperties: > > + '-pins*$': > > +type: object > > +description: | > > + A pinctrl node should contain at least one subnodes representing > > the > > + pinctrl groups available on the machine. Each subnode will list > > the > > + pins it needs, and how they should be configured, with regard to > > muxer > > + configuration, pullups, drive strength, input enable/disable and > > input schmitt. > > Need to include the pinconf schema here. Got it, I'll add it in next version. > > > + > > +properties: > > + pinmux: > > +description: > > + integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and > > are defined > > + as macros in bo
[PATCH v7 1/7] pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Mars Cheng Signed-off-by: Andy Teng Signed-off-by: Hanks Chen --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 000..87fdc43 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9
[PATCH v7 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 +
drivers/pinctrl/mediatek/pinctrl-paris.c |7 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b77b18f..c53e2c3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned
long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 27df087..bd079f4f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 90a432b..a23c182 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip,
unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+* "Virtual" GPIOs are always and only used for interrupts
+* Since they are only used for interrupts, they are always inputs
+*/
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, );
--
1.7.9.5
[PATCH v7 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +
4 files changed, 2873 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index f32d364..1cedc5f 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -93,6 +93,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 4b71328..b0b07c5 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
new file mode 100644
index 000..145bf22
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng
+ *
+ */
+
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1,
+ * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA,
+ * iocfg_lt:0x11F2, iocfg_tl:0x11F3
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10
[PATCH v7 0/7] Add basic SoC Support for Mediatek MT6779 SoC
*** BLURB HERE *** Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support clk: mediatek: add UART0 clock support arm64: dts: add dts nodes for MT6779 .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts| 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 13 files changed, 4671 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h -- 1.7.9.5
[PATCH v7 6/7] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
---
drivers/clk/mediatek/clk-mt6779.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b/drivers/clk/mediatek/clk-mt6779.c
index 9766ccc..6e0d3a1 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
--
1.7.9.5
[PATCH v7] Add basic SoC Support for Mediatek MT6779 SoC
Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support clk: mediatek: add UART0 clock support arm64: dts: add dts nodes for MT6779 .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts| 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 13 files changed, 4671 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h
[PATCH v7 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng --- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 000..3a9fc4d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: +const: mediatek,mt6779-pinctrl + + reg: +minItems: 9 +maxItems: 9 +description: | + physical address base for gpio-related control registers. + + reg-names: +description: | + GPIO base register names. The names are "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + + gpio-controller: true + + "#gpio-cells": +const: 2 +description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: +minItems: 1 +maxItems: 5 +description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: +maxItems: 1 +description: | + Specifies the summary IRQ. + + "#interrupt-cells": +const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': +type: object +patternProperties: + '-pins*$': +type: object +description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + +properties: + pinmux: +description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/-pinfunc.h directly. + + bias-disable: +type: boolean + + bias-pull-up: +type: boolean + + bias-pull-down: +type: boolean + + input-enable: +type: boolean + + input-disable: +type: boolean + + output-low: +type: boolean + + output-high: +type: boolean + + input-schmitt-enable: +type: boolean + + input-schmitt-disable: +type: boolean + + mediatek,pull-up-adv: +description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: +description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + drive-strength: +description: | + Selects the drive strength for the specified pins in mA. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 +
[PATCH v7 5/7] pinctrl: mediatek: add mt6779 eint support
add driver setting to support mt6779 eint
Acked-by: Sean Wang
Signed-off-by: Mars Cheng
Signed-off-by: Hanks Chen
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf22..3282260 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num= 195,
+ .db_cnt= 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = _eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
1.7.9.5
[PATCH v7 7/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile |1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271 +++
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9d..4d1b0f9 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index 000..164f5cb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index 000..db21f23
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Mon, 2020-06-29 at 15:53 -0600, Rob Herring wrote: > On Thu, 18 Jun 2020 19:33:32 +0800, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > --- > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 > > > > 1 file changed, 210 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dts:21:18: > fatal error: dt-bindings/pinctrl/mt6779-pinfunc.h: No such file or directory > #include > ^~ > compilation terminated. > scripts/Makefile.lib:315: recipe for target > 'Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml' > failed > make[1]: *** > [Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml] > Error 1 > make[1]: *** Waiting for unfinished jobs > Makefile:1347: recipe for target 'dt_binding_check' failed > make: *** [dt_binding_check] Error 2 > > > See https://patchwork.ozlabs.org/patch/1312018 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master > --upgrade > > Please check and re-submit. > I already ran the dt_binding_check and it looks good. > > > Here, you need patch 2 to come first or merge it into this patch as it > is part of the binding. > I'll merge it into this patch in next version. Thank you for your comment. Hanks > Rob >
Re: [PATCH 1/1] irqchip: Add config MTK_SYSIRQ and MTK_CIRQ
On Thu, 2020-06-18 at 22:22 +0800, Hanks Chen wrote: > On Thu, 2020-06-18 at 13:41 +0100, Marc Zyngier wrote: > > On 2020-06-18 13:31, Hanks Chen wrote: > > > Mediatek sysirq and cirq drivers as-is were bound together to the > > > config > > > of ARCH_MEDIATEK. These two drivers should be able to be configured > > > separately. For example, on new Mediatek mobile chips such as > > > Dimensity > > > 820, the sysirq driver is not used since the hardware module is > > > removed. > > > > > > Add two new configs to sysirq and cirq drivers. > > > - config MTK_SYSIRQ for the interrupt polarity controller driver: > > > sysirq > > > - config MTK_CIRQ for the low-power interrupt driver: cirq > > > > > > Signed-off-by: cc.hwang > > > Signed-off-by: Hanks Chen > > > --- > > > drivers/irqchip/Kconfig | 12 > > > drivers/irqchip/Makefile |3 ++- > > > 2 files changed, 14 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > > index 29fead2..cc9aa18 100644 > > > --- a/drivers/irqchip/Kconfig > > > +++ b/drivers/irqchip/Kconfig > > > @@ -572,4 +572,16 @@ config LOONGSON_PCH_MSI > > > help > > > Support for the Loongson PCH MSI Controller. > > > > > > +config MTK_SYSIRQ > > > + tristate "Mediatek interrupt polarity controller" > > > > How do you expect this to work as a module? > > My fault, I missed some patches.I'll add them in next patches. > > These should be three patches: > 1. break existing configurations and create new config for them > 2. Change Kconfig to be loadable as a module and ensure all platforms > are executable. > 3. Make the irq-mtk-sysirq driver as a loadable kernel module for GKI > and flexibility. > . > Thank you for your comment > > > > > > + help > > > + Interrupt polarity controller driver to swap polarity for > > > + interrupts for Mediatek mobile chips. > > > + > > > +config MTK_CIRQ > > > + bool "Mediatek low-power interrupt controller" > > > + help > > > + Low-power interrupt controller driver to monitor IRQS > > > + in the sleep mode for Mediatek mobile chips. > > > + > > > endmenu > > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > > index 133f9c4..30421d2 100644 > > > --- a/drivers/irqchip/Makefile > > > +++ b/drivers/irqchip/Makefile > > > @@ -69,7 +69,8 @@ obj-$(CONFIG_BCM7120_L2_IRQ)+= > > > irq-bcm7120-l2.o > > > obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o > > > obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o > > > obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o > > > -obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o > > > irq-mtk-cirq.o > > > +obj-$(CONFIG_MTK_SYSIRQ) += irq-mtk-sysirq.o > > > +obj-$(CONFIG_MTK_CIRQ) += irq-mtk-cirq.o > > > obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o > > > obj-$(CONFIG_RENESAS_H8300H_INTC)+= irq-renesas-h8300h.o > > > obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o > > > > In general, this approach doesn't look right. As it stands, this is just > > breaking existing configurations > > > > Do you really expect users to know exactly which interrupt controllers > > their system is going to use? This seems like the wrong assumption. If > > you really want to save the handful of bytes these drivers take in your > > image, then add the relevant dependency information in Kconfig. > > > > 1. This patch will add a dependency on it in Kconfig, which ensures all > platforms are executable. > 2. We want to follow the Android GKI and according to the requirement of > GKI(General Kernel Image), all SoC and Board Peripheral drivers are > loadable kernel modules.so I need to breaking existing configurations > and create new config for them. > Thank you for your comment Hi Marc, I want to break the dependency between ARCH_MEDIATEK and CIRQ/SYSIRQ, because we need to follow the GKI. Could I add the MTK_CIRQ and MTK_SYSIRQ into defconfig? (arch/arm64/config/defconfig) It would ensures all platform are executable. e.g. --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig CONFIG_QCOM_PDC=y +CONFIG_MTK_SYSIRQ=m +CONFIG_MTK_CIRQ=y CONFIG_RESET_QCOM_AOSS=y --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/K
Re: [PATCH v5 6/6] arm64: dts: add dts nodes for MT6779
On Mon, 2020-06-22 at 13:25 +0200, Matthias Brugger wrote:
>
> On 16/06/2020 15:34, Hanks Chen wrote:
> > On Wed, 2020-03-25 at 17:39 +0100, Matthias Brugger wrote:
> >>
> >> On 25/03/2020 10:31, Hanks Chen wrote:
> >>> this adds initial MT6779 dts settings fo board support,
> >>
> >> "for board support"
> >>
> >>> including cpu, gic, timer, ccf, pinctrl, uart...etc.
> >>
> >> The etc is PMU and PSCI and sysirq, correct? Let's list at least sysirq as
> >> this
> >> is something MediaTek specific.
> >>
> >>>
> >>> Signed-off-by: Hanks Chen
> >>> ---
> >>> arch/arm64/boot/dts/mediatek/Makefile |1 +
> >>> arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31
> >>> arch/arm64/boot/dts/mediatek/mt6779.dtsi| 265
> >>> +++
> >>> 3 files changed, 297 insertions(+)
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> >>> b/arch/arm64/boot/dts/mediatek/Makefile
> >>> index 458bbc4..53f1c61 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/Makefile
> >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> >>> @@ -1,6 +1,7 @@
> >>> # SPDX-License-Identifier: GPL-2.0
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>> b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>> new file mode 100644
> >>> index 000..164f5cb
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>> @@ -0,0 +1,31 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/*
> >>> + * Copyright (c) 2019 MediaTek Inc.
> >>> + * Author: Mars.C
> >>> + *
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include "mt6779.dtsi"
> >>> +
> >>> +/ {
> >>> + model = "MediaTek MT6779 EVB";
> >>> + compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
> >>> +
> >>> + aliases {
> >>> + serial0 =
> >>> + };
> >>> +
> >>> + memory@4000 {
> >>> + device_type = "memory";
> >>> + reg = <0 0x4000 0 0x1e80>;
> >>> + };
> >>> +
> >>> + chosen {
> >>> + stdout-path = "serial0:921600n8";
> >>> + };
> >>> +};
> >>> +
> >>> + {
> >>> + status = "okay";
> >>> +};
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>> new file mode 100644
> >>> index 000..422ff5f
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>> @@ -0,0 +1,265 @@
> >> [...]
> >>> +
> >>> + uart_clk: dummy26m {
> >>> + compatible = "fixed-clock";
> >>> + clock-frequency = <2600>;
> >>> + #clock-cells = <0>;
> >>> + };
> >>
> >> No real clocks for uart? What about CLK_INFRA_UARTx?
> >
> > sorry, I miss the clocks for uart
> > I'll add "baud" and "bus" in next version.
> >
> > clocks = <>, <_ao CLK_INFRA_UART0>;
> > clock-names = "baud", "bus";
> >
> >
> >>
> >>> +
> >>> + timer {
> >>> + compatible = "arm,armv8-timer";
> >>> + interrupt-parent = <>;
> >>> + interrupts = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + };
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #si
Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Sun, 2020-06-21 at 23:13 +0200, Pavel Machek wrote: > On Thu 2020-06-18 19:33:32, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > > > + Pull up setings for 2 pull resistors, R0 and R1. User can > > + configure those special pins. Valid arguments are described > > as below: > > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > > Typo => disabled. Got it, I'll fix the typo in next version. Thanks! > Pavel >
Re: [PATCH v6 6/7] clk: mediatek: add UART0 clock support
On Thu, 2020-06-18 at 17:51 +0200, Matthias Brugger wrote:
>
> On 18/06/2020 13:33, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> >
>
> Please a dd fixes tag:
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Got it, I'll add it in next version.
>
> > Signed-off-by: Hanks Chen
> > Signed-off-by: mtk01761
>
> Must be a real name not "mtk01761"
Oops, I'll update his name.
Thank you for your comment.
>
> > ---
> > drivers/clk/mediatek/clk-mt6779.c |2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c
> > b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766ccc..6e0d3a1 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@
> > "pwm_sel", 19),
> > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> > "pwm_sel", 21),
> > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > + "uart_sel", 22),
> > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> > "uart_sel", 23),
> > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> >
Re: [PATCH 1/1] irqchip: Add config MTK_SYSIRQ and MTK_CIRQ
On Thu, 2020-06-18 at 13:41 +0100, Marc Zyngier wrote: > On 2020-06-18 13:31, Hanks Chen wrote: > > Mediatek sysirq and cirq drivers as-is were bound together to the > > config > > of ARCH_MEDIATEK. These two drivers should be able to be configured > > separately. For example, on new Mediatek mobile chips such as > > Dimensity > > 820, the sysirq driver is not used since the hardware module is > > removed. > > > > Add two new configs to sysirq and cirq drivers. > > - config MTK_SYSIRQ for the interrupt polarity controller driver: > > sysirq > > - config MTK_CIRQ for the low-power interrupt driver: cirq > > > > Signed-off-by: cc.hwang > > Signed-off-by: Hanks Chen > > --- > > drivers/irqchip/Kconfig | 12 > > drivers/irqchip/Makefile |3 ++- > > 2 files changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index 29fead2..cc9aa18 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -572,4 +572,16 @@ config LOONGSON_PCH_MSI > > help > > Support for the Loongson PCH MSI Controller. > > > > +config MTK_SYSIRQ > > + tristate "Mediatek interrupt polarity controller" > > How do you expect this to work as a module? My fault, I missed some patches.I'll add them in next patches. These should be three patches: 1. break existing configurations and create new config for them 2. Change Kconfig to be loadable as a module and ensure all platforms are executable. 3. Make the irq-mtk-sysirq driver as a loadable kernel module for GKI and flexibility. . Thank you for your comment > > > + help > > + Interrupt polarity controller driver to swap polarity for > > + interrupts for Mediatek mobile chips. > > + > > +config MTK_CIRQ > > + bool "Mediatek low-power interrupt controller" > > + help > > + Low-power interrupt controller driver to monitor IRQS > > + in the sleep mode for Mediatek mobile chips. > > + > > endmenu > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index 133f9c4..30421d2 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -69,7 +69,8 @@ obj-$(CONFIG_BCM7120_L2_IRQ) += > > irq-bcm7120-l2.o > > obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o > > obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o > > obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o > > -obj-$(CONFIG_ARCH_MEDIATEK)+= irq-mtk-sysirq.o > > irq-mtk-cirq.o > > +obj-$(CONFIG_MTK_SYSIRQ) += irq-mtk-sysirq.o > > +obj-$(CONFIG_MTK_CIRQ) += irq-mtk-cirq.o > > obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o > > obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o > > obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o > > In general, this approach doesn't look right. As it stands, this is just > breaking existing configurations > > Do you really expect users to know exactly which interrupt controllers > their system is going to use? This seems like the wrong assumption. If > you really want to save the handful of bytes these drivers take in your > image, then add the relevant dependency information in Kconfig. > 1. This patch will add a dependency on it in Kconfig, which ensures all platforms are executable. 2. We want to follow the Android GKI and according to the requirement of GKI(General Kernel Image), all SoC and Board Peripheral drivers are loadable kernel modules.so I need to breaking existing configurations and create new config for them. Thank you for your comment > M.
[PATCH 1/1] irqchip: Add config MTK_SYSIRQ and MTK_CIRQ
Mediatek sysirq and cirq drivers as-is were bound together to the config of ARCH_MEDIATEK. These two drivers should be able to be configured separately. For example, on new Mediatek mobile chips such as Dimensity 820, the sysirq driver is not used since the hardware module is removed. Add two new configs to sysirq and cirq drivers. - config MTK_SYSIRQ for the interrupt polarity controller driver: sysirq - config MTK_CIRQ for the low-power interrupt driver: cirq Signed-off-by: cc.hwang Signed-off-by: Hanks Chen --- drivers/irqchip/Kconfig | 12 drivers/irqchip/Makefile |3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 29fead2..cc9aa18 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -572,4 +572,16 @@ config LOONGSON_PCH_MSI help Support for the Loongson PCH MSI Controller. +config MTK_SYSIRQ + tristate "Mediatek interrupt polarity controller" + help + Interrupt polarity controller driver to swap polarity for + interrupts for Mediatek mobile chips. + +config MTK_CIRQ + bool "Mediatek low-power interrupt controller" + help + Low-power interrupt controller driver to monitor IRQS + in the sleep mode for Mediatek mobile chips. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 133f9c4..30421d2 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -69,7 +69,8 @@ obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o -obj-$(CONFIG_ARCH_MEDIATEK)+= irq-mtk-sysirq.o irq-mtk-cirq.o +obj-$(CONFIG_MTK_SYSIRQ) += irq-mtk-sysirq.o +obj-$(CONFIG_MTK_CIRQ) += irq-mtk-cirq.o obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o -- 1.7.9.5
[PATCH v6 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Acked-by: Sean Wang
Signed-off-by: Hanks Chen
Signed-off-by: Mars Cheng
Signed-off-by: Andy Teng
---
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +
4 files changed, 2873 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index f32d364..1cedc5f 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -93,6 +93,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 4b71328..b0b07c5 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
new file mode 100644
index 000..145bf22
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng
+ *
+ */
+
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1,
+ * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA,
+ * iocfg_lt:0x11F2, iocfg_tl:0x11F3
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10
[PATCH v6 6/7] clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support. Signed-off-by: Hanks Chen Signed-off-by: mtk01761 --- drivers/clk/mediatek/clk-mt6779.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", -- 1.7.9.5
[PATCH v6 5/7] pinctrl: mediatek: add mt6779 eint support
add driver setting to support mt6779 eint
Acked-by: Sean Wang
Signed-off-by: Hanks Chen
Signed-off-by: Mars Cheng
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf22..3282260 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num= 195,
+ .db_cnt= 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = _eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
1.7.9.5
[PATCH v6] Add basic SoC Support for Mediatek MT6779 SoC
This patch add basic SoC Support for Mediatek MT6779 SoC Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (6): pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: add mt6779 eint support clk: mediatek: add UART0 clock support arm64: dts: add dts nodes for MT6779 .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++ arch/arm64/boot/dts/mediatek/Makefile |1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts| 31 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 261 +++ drivers/clk/mediatek/clk-mt6779.c |2 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 + drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 drivers/pinctrl/mediatek/pinctrl-paris.c |7 + include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 13 files changed, 4661 insertions(+)
[PATCH v6 7/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile |1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 261 +++
3 files changed, 293 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9d..4d1b0f9 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index 000..164f5cb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index 000..64e5963
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ i
[PATCH v6 2/7] pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Hanks Chen Signed-off-by: Mars Cheng Signed-off-by: Andy Teng --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 000..87fdc43 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9
[PATCH v6 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Hanks Chen
Signed-off-by: Mars Cheng
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |1 +
drivers/pinctrl/mediatek/pinctrl-paris.c |7 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b77b18f..c53e2c3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned
long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 27df087..bd079f4f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 90a432b..a23c182 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip,
unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+* "Virtual" GPIOs are always and only used for interrupts
+* Since they are only used for interrupts, they are always inputs
+*/
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)>soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, );
--
1.7.9.5
[PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng --- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 000..85819a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: +const: mediatek,mt6779-pinctrl + + reg: +minItems: 9 +maxItems: 9 +description: | + physical address base for gpio-related control registers. + + reg-names: +description: | + GPIO base register names. The names are "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + + gpio-controller: true + + "#gpio-cells": +const: 2 +description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: +minItems: 1 +maxItems: 5 +description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: +maxItems: 1 +description: | + Specifies the summary IRQ. + + "#interrupt-cells": +const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': +type: object +patternProperties: + '-pins*$': +type: object +description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + +properties: + pinmux: +description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/-pinfunc.h directly. + + bias-disable: +type: boolean + + bias-pull-up: +type: boolean + + bias-pull-down: +type: boolean + + input-enable: +type: boolean + + input-disable: +type: boolean + + output-low: +type: boolean + + output-high: +type: boolean + + input-schmitt-enable: +type: boolean + + input-schmitt-disable: +type: boolean + + mediatek,pull-up-adv: +description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: +description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + drive-strength: +description: | + Selects the drive strength for the specified pins in mA. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 +
Re: [PATCH v5 6/6] arm64: dts: add dts nodes for MT6779
On Wed, 2020-03-25 at 17:39 +0100, Matthias Brugger wrote:
>
> On 25/03/2020 10:31, Hanks Chen wrote:
> > this adds initial MT6779 dts settings fo board support,
>
> "for board support"
>
> > including cpu, gic, timer, ccf, pinctrl, uart...etc.
>
> The etc is PMU and PSCI and sysirq, correct? Let's list at least sysirq as
> this
> is something MediaTek specific.
>
> >
> > Signed-off-by: Hanks Chen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile |1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi| 265
> > +++
> > 3 files changed, 297 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 458bbc4..53f1c61 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,6 +1,7 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > new file mode 100644
> > index 000..164f5cb
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> > + * Author: Mars.C
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt6779.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT6779 EVB";
> > + compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
> > +
> > + aliases {
> > + serial0 =
> > + };
> > +
> > + memory@4000 {
> > + device_type = "memory";
> > + reg = <0 0x4000 0 0x1e80>;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > new file mode 100644
> > index 000..422ff5f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > @@ -0,0 +1,265 @@
> [...]
> > +
> > + uart_clk: dummy26m {
> > + compatible = "fixed-clock";
> > + clock-frequency = <2600>;
> > + #clock-cells = <0>;
> > + };
>
> No real clocks for uart? What about CLK_INFRA_UARTx?
sorry, I miss the clocks for uart
I'll add "baud" and "bus" in next version.
clocks = <>, <_ao CLK_INFRA_UART0>;
clock-names = "baud", "bus";
>
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <>;
> > + interrupts = ,
> > +,
> > +,
> > +;
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> [...]
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x400>;
> > + interrupts = ;
> > + clocks = <_clk>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x400>;
> > + interrupts = ;
> > + clocks = <_clk>;
Re: [PATCH v5 4/6] pinctrl: mediatek: add pinctrl support for MT6779 SoC
On Thu, 2020-04-02 at 14:46 -0700, Sean Wang wrote: > Hi Hanks, > > On Wed, Mar 25, 2020 at 2:31 AM Hanks Chen wrote: > > > > This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core. > > > > We can add some useful help text about MT6779 pinctrl, especially > about specific parts like virtual gpio and its attributes > Then Acked-by: Sean Wang > Got it, I'll add it in next version. Thanks for the advices. > > Signed-off-by: Hanks Chen > > Signed-off-by: Mars Cheng > > Signed-off-by: Andy Teng > > --- > > drivers/pinctrl/mediatek/Kconfig |7 + > > drivers/pinctrl/mediatek/Makefile |1 + > > drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 + > > drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 > > + > > 4 files changed, 2868 insertions(+) > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h > > > > diff --git a/drivers/pinctrl/mediatek/Kconfig > > b/drivers/pinctrl/mediatek/Kconfig > > index 701f9af..f628d01 100644 > > --- a/drivers/pinctrl/mediatek/Kconfig > > +++ b/drivers/pinctrl/mediatek/Kconfig > > @@ -86,6 +86,13 @@ config PINCTRL_MT6765 > > default ARM64 && ARCH_MEDIATEK > > select PINCTRL_MTK_PARIS > > > > +config PINCTRL_MT6779 > > + bool "Mediatek MT6779 pin control" > > + depends on OF > > + depends on ARM64 || COMPILE_TEST > > + default ARM64 && ARCH_MEDIATEK > > + select PINCTRL_MTK_PARIS > > + > > config PINCTRL_MT6797 > > bool "Mediatek MT6797 pin control" > > depends on OF > > diff --git a/drivers/pinctrl/mediatek/Makefile > > b/drivers/pinctrl/mediatek/Makefile > > index a74325a..59c1c60 100644 > > --- a/drivers/pinctrl/mediatek/Makefile > > +++ b/drivers/pinctrl/mediatek/Makefile > > @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o > > obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o > > obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o > > obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o > > +obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o > > obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o > > obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o > > obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c > > b/drivers/pinctrl/mediatek/pinctrl-mt6779.c > > new file mode 100644 > > index 000..145bf22 > > --- /dev/null > > +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c > > @@ -0,0 +1,775 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Andy Teng > > + * > > + */ > > + > > +#include "pinctrl-mtk-mt6779.h" > > +#include "pinctrl-paris.h" > > + > > +/* MT6779 have multiple bases to program pin configuration listed as the > > below: > > + * gpio:0x10005000, iocfg_rm:0x11C2, iocfg_br:0x11D1, > > + * iocfg_lm:0x11E2, iocfg_lb:0x11E7, iocfg_rt:0x11EA, > > + * iocfg_lt:0x11F2, iocfg_tl:0x11F3 > > + * _i_based could be used to indicate what base the pin should be mapped > > into. > > + */ > > + > > +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, > > x_bits) \ > > + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, > > x_bits, \ > > + 32, 0) > > + > > > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH v5 2/6] pinctrl: mediatek: update pinmux definitions for mt6779
On Thu, 2020-04-02 at 14:54 -0700, Sean Wang wrote: > Hi, Hanks > > Just a few nitpicks and then Acked-by: Sean Wang > > On Wed, Mar 25, 2020 at 2:31 AM Hanks Chen wrote: > > > > Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. > > > > Signed-off-by: Hanks Chen > > Signed-off-by: Mars Cheng > > Signed-off-by: Andy Teng > > --- > > include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 > > ++ > > 1 file changed, 1242 insertions(+) > > create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h > > > > diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h > > b/include/dt-bindings/pinctrl/mt6779-pinfunc.h > > new file mode 100644 > > index 000..4698d2f > > --- /dev/null > > +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h > > @@ -0,0 +1,1242 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Andy Teng > > + * > > + */ > > + > > +#ifndef __MT6779_PINFUNC_H > > +#define __MT6779_PINFUNC_H > > + > > +#include "mt65xx.h" > > Use the standard include path instead: #include > > Got it, I'll revise it in next version Thanks for your comment. > > + > > > + > > +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) > > + > > +#endif /* __MT6779-PINFUNC_H */ >__MT6779_PINFUNC_H > > -- > > 1.7.9.5
Re: [PATCH v5 1/6] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu, 2020-03-26 at 11:43 -0600, Rob Herring wrote: > On Wed, Mar 25, 2020 at 3:31 AM Hanks Chen wrote: > > > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > --- > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 > > > > 1 file changed, 208 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > The header belongs in this patch so that 'make dt_binding_check' works. > > > > > diff --git > > a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > new file mode 100644 > > index 000..5f9bbf1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > @@ -0,0 +1,208 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek MT6779 Pin Controller Device Tree Bindings > > + > > +maintainers: > > + - Andy Teng > > + > > +description: |+ > > + The pin controller node should be the child of a syscon node with the > > + required property: > > + - compatible: "syscon" > > + > > +properties: > > + compatible: > > +const: mediatek,mt6779-pinctrl > > + > > + reg: > > +minItems: 9 > > +maxItems: 9 > > +description: | > > + physical address base for gpio-related control registers. > > + > > + reg-names: > > +description: | > > + GPIO base register names. > > Need to define what the names are and the order. Got it, I'll add it in next version. Thanks > > > + > > + gpio-controller: true > > + > > + "#gpio-cells": > > +const: 2 > > +description: | > > + Number of cells in GPIO specifier. Since the generic GPIO > > + binding is used, the amount of cells must be specified as 2. See the > > below > > + mentioned gpio binding representation for description of particular > > cells. > > + > > + gpio-ranges: > > +minItems: 1 > > +maxItems: 5 > > +description: | > > + GPIO valid number range. > > + > > + interrupt-controller: true > > + > > + interrupts: > > +minItems: 1 > > +maxItems: 4 > > Need to define what the interrupts are. > Got it, I'll add it in the next version. Thanks. > > +description: | > > + The interrupt outputs to sysirq. > > + > > + "#interrupt-cells": > > +const: 2 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - gpio-controller > > + - "#gpio-cells" > > + - gpio-ranges > > + - interrupt-controller > > + - interrupts > > + - "#interrupt-cells" > > + > > +patternProperties: > > + '^pins*$': > > '-pins$' would be preferred. > Got it, I'll fix it in next version. Thanks. > > +type: object > > +description: | > > + A pinctrl node should contain at least one subnodes representing the > > + pinctrl groups available on the machine. Each subnode will list the > > + pins it needs, and how they should be configured, with regard to > > muxer > > + configuration, pullups, drive strength, input enable/disable and > > input schmitt. > > + > > +properties: > > + pinmux: > > There's a common schema for all these properties. You need to > reference it (with $ref) and only define which properties you are > using and any additional constraints. > Got it, thx! > > +description: > > + integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and are > > defined > > + as macros in boot/dts/-pinfunc.h directly. > > +allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32-array > > + bias-disable: > > +type: boolean > > + > > + bias-pull-up: > > +oneOf: > > + - type: boolean > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + bias-pull-down: > > +oneOf
