Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85

[Jagan Teki]

On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine  wrote:
>
> Hi Jagan,
>
> On 2021-02-14 18:44, Jagan Teki wrote:
> > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> > controller IC's from Texas Instruments.
> >
> > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >
> > Right now the bridge driver is supporting Channel A with single
> > link, so dt-bindings documented according to it.
>
> Do you know when we can expect a v4 for this?
>
> I am currently working on top of your patch set to setup a dual-link
> LVDS bridge of SN65DSI84.

Yes, I'm planning to send v4 this week. will keep you in CC. thanks!

Jagan.

Re: [PATCH v4 1/4] drm: sun4i: dsi: Use drm_of_find_panel_or_bridge

[Jagan Teki]

Hi Laurent,

On Wed, Mar 24, 2021 at 3:09 PM Laurent Pinchart
 wrote:
>
> Hi Jagan,
>
> On Wed, Mar 24, 2021 at 02:44:57PM +0530, Jagan Teki wrote:
> > On Wed, Mar 24, 2021 at 8:18 AM Samuel Holland wrote:
> > > On 3/23/21 5:53 PM, Laurent Pinchart wrote:
> > > > On Mon, Mar 22, 2021 at 07:31:49PM +0530, Jagan Teki wrote:
> > > >> Replace of_drm_find_panel with drm_of_find_panel_or_bridge
> > > >> for finding panel, this indeed help to find the bridge if
> > > >> bridge support added.
> > > >>
> > > >> Added NULL in bridge argument, same will replace with bridge
> > > >> parameter once bridge supported.
> > > >>
> > > >> Signed-off-by: Jagan Teki 
> > > >
> > > > Looks good, there should be no functional change.
> > >
> > > Actually this breaks all existing users of this driver, see below.
> > >
> > > > Reviewed-by: Laurent Pinchart 
> > > >
> > > >> ---
> > > >> Changes for v4, v3:
> > > >> - none
> > > >>
> > > >>  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 11 ---
> > > >>  1 file changed, 8 insertions(+), 3 deletions(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
> > > >> b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > >> index 4f5efcace68e..2e9e7b2d4145 100644
> > > >> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > >> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > >> @@ -21,6 +21,7 @@
> > > >>
> > > >>  #include 
> > > >>  #include 
> > > >> +#include 
> > > >>  #include 
> > > >>  #include 
> > > >>  #include 
> > > >> @@ -963,10 +964,14 @@ static int sun6i_dsi_attach(struct mipi_dsi_host 
> > > >> *host,
> > > >>  struct mipi_dsi_device *device)
> > > >>  {
> > > >>  struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
> > > >> -struct drm_panel *panel = of_drm_find_panel(device->dev.of_node);
> > >
> > > This is using the OF node of the DSI device, which is a direct child of
> > > the DSI host's OF node. There is no OF graph involved.
> > >
> > > >> +struct drm_panel *panel;
> > > >> +int ret;
> > > >> +
> > > >> +ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
> > > >> +  &panel, NULL);
> > >
> > > However, this function expects to find the panel using OF graph. This
> > > does not work with existing device trees (PinePhone, PineTab) which do
> > > not use OF graph to connect the panel. And it cannot work, because the
> > > DSI host's binding specifies a single port: the input port from the
> > > display engine.
> >
> > Thanks for noticing this. I did understand your point and yes, I did
> > mention the updated pipeline in previous versions and forgot to add it
> > to this series.
> >
> > Here is the updated pipeline to make it work:
> >
> > https://patchwork.kernel.org/project/dri-devel/patch/20190524104252.20236-1-ja...@amarulasolutions.com/
> >
> > Let me know your comments on this, so I will add a patch for the
> > above-affected DTS files.
>
> DT is an ABI, we need to ensure backward compatibility. Changes in
> kernel drivers can't break devices that have an old DT.

Thanks for your point.

So, we need to choose APIs that would compatible with the old DT and
new DT changes. Am I correct?

Jagan.

Re: [PATCH v4 1/4] drm: sun4i: dsi: Use drm_of_find_panel_or_bridge

[Jagan Teki]

On Wed, Mar 24, 2021 at 8:18 AM Samuel Holland  wrote:
>
> On 3/23/21 5:53 PM, Laurent Pinchart wrote:
> > Hi Jagan,
> >
> > Thank you for the patch.
> >
> > On Mon, Mar 22, 2021 at 07:31:49PM +0530, Jagan Teki wrote:
> >> Replace of_drm_find_panel with drm_of_find_panel_or_bridge
> >> for finding panel, this indeed help to find the bridge if
> >> bridge support added.
> >>
> >> Added NULL in bridge argument, same will replace with bridge
> >> parameter once bridge supported.
> >>
> >> Signed-off-by: Jagan Teki 
> >
> > Looks good, there should be no functional change.
>
> Actually this breaks all existing users of this driver, see below.
>
> > Reviewed-by: Laurent Pinchart 
> >
> >> ---
> >> Changes for v4, v3:
> >> - none
> >>
> >>  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 11 ---
> >>  1 file changed, 8 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
> >> b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> >> index 4f5efcace68e..2e9e7b2d4145 100644
> >> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> >> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> >> @@ -21,6 +21,7 @@
> >>
> >>  #include 
> >>  #include 
> >> +#include 
> >>  #include 
> >>  #include 
> >>  #include 
> >> @@ -963,10 +964,14 @@ static int sun6i_dsi_attach(struct mipi_dsi_host 
> >> *host,
> >>  struct mipi_dsi_device *device)
> >>  {
> >>  struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
> >> -struct drm_panel *panel = of_drm_find_panel(device->dev.of_node);
>
> This is using the OF node of the DSI device, which is a direct child of
> the DSI host's OF node. There is no OF graph involved.
>
> >> +struct drm_panel *panel;
> >> +int ret;
> >> +
> >> +ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
> >> +  &panel, NULL);
>
> However, this function expects to find the panel using OF graph. This
> does not work with existing device trees (PinePhone, PineTab) which do
> not use OF graph to connect the panel. And it cannot work, because the
> DSI host's binding specifies a single port: the input port from the
> display engine.

Thanks for noticing this. I did understand your point and yes, I did
mention the updated pipeline in previous versions and forgot to add it
to this series.

Here is the updated pipeline to make it work:

https://patchwork.kernel.org/project/dri-devel/patch/20190524104252.20236-1-ja...@amarulasolutions.com/

Let me know your comments on this, so I will add a patch for the
above-affected DTS files.

Jagan.

[PATCH v4 3/4] drm: sun4i: dsi: Convert to bridge driver

[Jagan Teki]

DRM bridge drivers have build-in handling of treating all display
pipeline components as bridges.

So, convert the existing to a drm bridge driver with a built-in
encoder support for compatibility with existing component drivers.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- none
Changes for v3:
- new patch

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 75 --
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  6 +++
 2 files changed, 54 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 39321299dc27..6f3c5330a468 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -714,10 +714,10 @@ static int sun6i_dsi_start(struct sun6i_dsi *dsi,
return 0;
 }
 
-static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+static void sun6i_dsi_bridge_enable(struct drm_bridge *bridge)
 {
-   struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
-   struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+   struct drm_display_mode *mode = 
&bridge->encoder->crtc->state->adjusted_mode;
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
struct mipi_dsi_device *device = dsi->device;
union phy_configure_opts opts = { };
struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
@@ -801,9 +801,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
sun6i_dsi_start(dsi, DSI_START_HSD);
 }
 
-static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+static void sun6i_dsi_bridge_disable(struct drm_bridge *bridge)
 {
-   struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
 
DRM_DEBUG_DRIVER("Disabling DSI output\n");
 
@@ -852,9 +852,40 @@ static const struct drm_connector_funcs 
sun6i_dsi_connector_funcs = {
.atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 };
 
-static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
-   .disable= sun6i_dsi_encoder_disable,
-   .enable = sun6i_dsi_encoder_enable,
+static int sun6i_dsi_bridge_attach(struct drm_bridge *bridge,
+  enum drm_bridge_attach_flags flags)
+{
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
+   int ret;
+
+   if (dsi->panel_bridge)
+   return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, 
NULL, 0);
+
+   if (dsi->panel) {
+   drm_connector_helper_add(&dsi->connector,
+&sun6i_dsi_connector_helper_funcs);
+   ret = drm_connector_init(bridge->dev, &dsi->connector,
+&sun6i_dsi_connector_funcs,
+DRM_MODE_CONNECTOR_DSI);
+   if (ret) {
+   dev_err(dsi->dev, "Couldn't initialise the DSI 
connector\n");
+   goto err_cleanup_connector;
+   }
+
+   drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
+   }
+
+   return 0;
+
+err_cleanup_connector:
+   drm_encoder_cleanup(&dsi->encoder);
+   return ret;
+}
+
+static const struct drm_bridge_funcs sun6i_dsi_bridge_funcs = {
+   .enable = sun6i_dsi_bridge_enable,
+   .disable= sun6i_dsi_bridge_disable,
+   .attach = sun6i_dsi_bridge_attach,
 };
 
 static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
@@ -1063,8 +1094,6 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
int ret;
 
-   drm_encoder_helper_add(&dsi->encoder,
-  &sun6i_dsi_enc_helper_funcs);
ret = drm_simple_encoder_init(drm, &dsi->encoder,
  DRM_MODE_ENCODER_DSI);
if (ret) {
@@ -1073,27 +1102,12 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
}
dsi->encoder.possible_crtcs = BIT(0);
 
-   drm_connector_helper_add(&dsi->connector,
-&sun6i_dsi_connector_helper_funcs);
-   ret = drm_connector_init(drm, &dsi->connector,
-&sun6i_dsi_connector_funcs,
-DRM_MODE_CONNECTOR_DSI);
+   ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 0);
if (ret) {
-   dev_err(dsi->dev,
-   "Couldn't initialise the DSI connector\n");
+   dev_err(dsi->dev, "Couldn't attach drm bridge\n");
goto err_cleanup_connector;
}

[DO NOT MERGE] [PATCH v4 4/4] ARM: dts: sun8i: bananapi-m2m: Enable S070WV20-CT16 panel

[Jagan Teki]

This patch add support for Bananapi S070WV20-CT16 panel to
BPI-M2M board.

Bananapi S070WV20-CT16 is a pure RGB output panel with ICN6211 DSI/RGB
converter bridge, so enable bridge along with associated panel.

DSI panel connected via board DSI port with,
- DCDC1 as VCC-DSI supply
- PL5 gpio for bridge enable gpio pin
- PB7 gpio for lcd enable gpio pin
- PL4 gpio for backlight enable pin

Signed-off-by: Jagan Teki 
---
Changes for v4:
- replace reset with enable-gpios
Changes for v3:
- none 

 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 85 
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts 
b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index 293016d081cd..6f33e1ae8ffc 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -44,6 +44,7 @@
 #include "sun8i-a33.dtsi"
 
 #include 
+#include 
 
 / {
model = "BananaPi M2 Magic";
@@ -55,12 +56,21 @@ aliases {
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
+   mmc0 = &mmc0;
};
 
chosen {
stdout-path = "serial0:115200n8";
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <1 2 4 8 16 32 64 128 255>;
+   default-brightness-level = <8>;
+   enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PL4 
*/
+   };
+
leds {
compatible = "gpio-leds";
 
@@ -81,6 +91,18 @@ led-2 {
};
};
 
+   panel {
+   compatible = "bananapi,s070wv20-ct16";
+   enable-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN: PB7 
*/
+   backlight = <&backlight>;
+
+   port {
+   panel_out_bridge: endpoint {
+   remote-endpoint = <&bridge_out_panel>;
+   };
+   };
+   };
+
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
@@ -122,6 +144,59 @@ &dai {
status = "okay";
 };
 
+&de {
+   status = "okay";
+};
+
+&dphy {
+   status = "okay";
+};
+
+&dsi {
+   vcc-dsi-supply = <®_dcdc1>;  /* VCC-DSI */
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   dsi_out: port@0 {
+   reg = <0>;
+
+   dsi_out_bridge: endpoint {
+   remote-endpoint = <&bridge_out_dsi>;
+   };
+   };
+   };
+
+   bridge@0 {
+   compatible = "chipone,icn6211";
+   reg = <0>;
+   enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   bridge_in: port@0 {
+   reg = <0>;
+
+   bridge_out_dsi: endpoint {
+   remote-endpoint = <&dsi_out_bridge>;
+   };
+   };
+
+   bridge_out: port@1 {
+   reg = <1>;
+
+   bridge_out_panel: endpoint {
+   remote-endpoint = <&panel_out_bridge>;
+   };
+   };
+   };
+   };
+};
+
 &ehci0 {
status = "okay";
 };
@@ -157,6 +232,12 @@ &ohci0 {
status = "okay";
 };
 
+&pwm {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm0_pin>;
+   status = "okay";
+};
+
 &r_rsb {
status = "okay";
 
@@ -269,6 +350,10 @@ &sound {
status = "okay";
 };
 
+&tcon0 {
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
-- 
2.25.1

[PATCH v4 2/4] drm: sun4i: dsi: Add bridge support

[Jagan Teki]

Some display panels would come up with a non-DSI output which
can have an option to connect DSI interface by means of bridge
converter.

This DSI to non-DSI bridge converter would require a bridge
driver that would communicate the DSI controller for bridge
functionalities.

So, add support for bridge functionalities in Allwinner DSI
controller.

Cc: Samuel Holland 
Signed-off-by: Jagan Teki 
---
Note: 
Samuel Holland, The existing kms hotplug dropped in order to 
attach the bridge properly. 

However, I did try several ways to support hotplug with the 
bridge but it's resulting in a deadlock where bind never attach 
bridge until bridge pointer found and bridge pointer cannot 
found until bind finishes. Any inputs on this would be appreciated.

Changes for v4:
- none
Changes for v3:
- updated with new API's 

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 34 +-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  2 +-
 2 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 2e9e7b2d4145..39321299dc27 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -773,6 +773,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
if (dsi->panel)
drm_panel_prepare(dsi->panel);
 
+   if (dsi->panel_bridge)
+   dsi->panel_bridge->funcs->pre_enable(dsi->panel_bridge);
+
/*
 * FIXME: This should be moved after the switch to HS mode.
 *
@@ -788,6 +791,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
if (dsi->panel)
drm_panel_enable(dsi->panel);
 
+   if (dsi->panel_bridge)
+   dsi->panel_bridge->funcs->enable(dsi->panel_bridge);
+
sun6i_dsi_start(dsi, DSI_START_HSC);
 
udelay(1000);
@@ -804,6 +810,9 @@ static void sun6i_dsi_encoder_disable(struct drm_encoder 
*encoder)
if (dsi->panel) {
drm_panel_disable(dsi->panel);
drm_panel_unprepare(dsi->panel);
+   } else if (dsi->panel_bridge) {
+   dsi->panel_bridge->funcs->disable(dsi->panel_bridge);
+   dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
}
 
phy_power_off(dsi->dphy);
@@ -964,23 +973,17 @@ static int sun6i_dsi_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
 {
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
-   struct drm_panel *panel;
int ret;
 
ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
- &panel, NULL);
+ &dsi->panel, &dsi->panel_bridge);
if (ret)
return ret;
 
-   if (!dsi->drm || !dsi->drm->registered)
-   return -EPROBE_DEFER;
-
-   dsi->panel = panel;
dsi->device = device;
 
-   drm_kms_helper_hotplug_event(dsi->drm);
-
-   dev_info(host->dev, "Attached device %s\n", device->name);
+   dev_info(host->dev, "Attached %s %s\n",
+device->name, dsi->panel ? "panel" : "bridge");
 
return 0;
 }
@@ -991,9 +994,10 @@ static int sun6i_dsi_detach(struct mipi_dsi_host *host,
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
 
dsi->panel = NULL;
+   dsi->panel_bridge = NULL;
dsi->device = NULL;
 
-   drm_kms_helper_hotplug_event(dsi->drm);
+   drm_of_panel_bridge_remove(dsi->dev->of_node, 0, 0);
 
return 0;
 }
@@ -1082,7 +1086,13 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
 
drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
 
-   dsi->drm = drm;
+   if (dsi->panel_bridge) {
+   ret = drm_bridge_attach(&dsi->encoder, dsi->panel_bridge, NULL, 
0);
+   if (ret) {
+   dev_err(dsi->dev, "Couldn't attach drm bridge\n");
+   goto err_cleanup_connector;
+   }
+   }
 
return 0;
 
@@ -1096,7 +1106,7 @@ static void sun6i_dsi_unbind(struct device *dev, struct 
device *master,
 {
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
 
-   dsi->drm = NULL;
+   drm_encoder_cleanup(&dsi->encoder);
 }
 
 static const struct component_ops sun6i_dsi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index c863900ae3b4..370ecb356a63 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -29,8 +29,8 @@ struct sun6i_dsi {
 
struct device   *dev;
struct mipi_dsi_device  *device;
-   struct drm_device   *drm;
struct drm_panel*panel;
+   struct drm_bridge   *panel_bridge;
 };
 
 static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
-- 
2.25.1

[PATCH v4 1/4] drm: sun4i: dsi: Use drm_of_find_panel_or_bridge

[Jagan Teki]

Replace of_drm_find_panel with drm_of_find_panel_or_bridge
for finding panel, this indeed help to find the bridge if
bridge support added.

Added NULL in bridge argument, same will replace with bridge
parameter once bridge supported.

Signed-off-by: Jagan Teki 
---
Changes for v4, v3:
- none

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 4f5efcace68e..2e9e7b2d4145 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -21,6 +21,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -963,10 +964,14 @@ static int sun6i_dsi_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
 {
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
-   struct drm_panel *panel = of_drm_find_panel(device->dev.of_node);
+   struct drm_panel *panel;
+   int ret;
+
+   ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
+ &panel, NULL);
+   if (ret)
+   return ret;
 
-   if (IS_ERR(panel))
-   return PTR_ERR(panel);
if (!dsi->drm || !dsi->drm->registered)
return -EPROBE_DEFER;
 
-- 
2.25.1

[PATCH v4 0/4] drm: sun4i: dsi: Convert drm bridge

[Jagan Teki]

This series convert Allwinner DSI controller to full functional 
drm bridge driver for supporting slave panel, bridges.

Here, are the previous version changes[1].

Patch 1: use drm_of_find_panel_or_bridge API

Patch 2: Adding DRM Bridge support

Patch 3: Convert to bridge driver, that indeed drop
 encoder API's and support bridge API's

Patch 4: Overlay patch for bridge enablement in BPI-M2M

Note: Only nit on this series is kms hotplug, added Samuel Holland
for reviews and comments as he is authorized the code before.

[1] https://lkml.org/lkml/2021/2/14/173

Any inputs on this would be appreciated!
Jagan.

Jagan Teki (4):
  drm: sun4i: dsi: Use drm_of_find_panel_or_bridge
  drm: sun4i: dsi: Add bridge support
  drm: sun4i: dsi: Convert to bridge driver
  [DO NOT MERGE] ARM: dts: sun8i: bananapi-m2m: Enable S070WV20-CT16 panel

 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts |  85 
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c   | 100 +--
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h   |   8 +-
 3 files changed, 160 insertions(+), 33 deletions(-)

-- 
2.25.1

[PATCH v5 2/2] drm: bridge: Add Chipone ICN6211 MIPI-DSI to RGB bridge

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Converter bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produce RGB565, RGB666, RGB888 output format.

Add bridge driver for it.

Signed-off-by: Jagan Teki 
Reviewed-by: Robert Foss 
---
Changes for v5:
- rebase drm-misc-next
- collect Robert review tags
Changes for v4:
- added regulators
- replace reset with EN
- fixed warnings pointed by Robert
Changes for v3:
- updated the driver to inline with new drm bridge style

 MAINTAINERS  |   1 +
 drivers/gpu/drm/bridge/Kconfig   |  13 +
 drivers/gpu/drm/bridge/Makefile  |   1 +
 drivers/gpu/drm/bridge/chipone-icn6211.c | 293 +++
 4 files changed, 308 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/chipone-icn6211.c

diff --git a/MAINTAINERS b/MAINTAINERS
index b9d11101d060..b92a35c80eae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5572,6 +5572,7 @@ DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER 
BRIDGE
 M: Jagan Teki 
 S: Maintained
 F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
+F: drivers/gpu/drm/bridge/chipone-icn6211.c
 
 DRM DRIVER FOR FARADAY TVE200 TV ENCODER
 M: Linus Walleij 
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3..330ee70ed746 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,19 @@ config DRM_CDNS_DSI
  Support Cadence DPI to DSI bridge. This is an internal
  bridge and is meant to be directly embedded in a SoC.
 
+config DRM_CHIPONE_ICN6211
+   tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
+   depends on OF
+   select DRM_MIPI_DSI
+   select DRM_PANEL_BRIDGE
+   help
+ ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
+
+ It has a flexible configuration of MIPI DSI signal input
+ and produce RGB565, RGB666, RGB888 output format.
+
+ If in doubt, say "N".
+
 config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d..3eb84b638988 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
 obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
 obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
 obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c 
b/drivers/gpu/drm/bridge/chipone-icn6211.c
new file mode 100644
index ..a6151db95586
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define HACTIVE_LI 0x20
+#define VACTIVE_LI 0x21
+#define VACTIVE_HACTIVE_HI 0x22
+#define HFP_LI 0x23
+#define HSYNC_LI   0x24
+#define HBP_LI 0x25
+#define HFP_HSW_HBP_HI 0x26
+#define VFP0x27
+#define VSYNC  0x28
+#define VBP0x29
+
+struct chipone {
+   struct device *dev;
+   struct drm_bridge bridge;
+   struct drm_bridge *panel_bridge;
+   struct gpio_desc *enable_gpio;
+   struct regulator *vdd1;
+   struct regulator *vdd2;
+   struct regulator *vdd3;
+};
+
+static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct chipone, bridge);
+}
+
+static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
+{
+   return &bridge->encoder->crtc->state->adjusted_mode;
+}
+
+static inline int chipone_dsi_write(struct chipone *icn,  const void *seq,
+   size_t len)
+{
+   struct mipi_dsi_device *dsi = to_mipi_dsi_device(icn->dev);
+
+   return mipi_dsi_generic_write(dsi, seq, len);
+}
+
+#define ICN6211_DSI(icn, seq...)   \
+   {   \
+   const u8 d[] = { seq }; \
+   chipone_dsi_write(icn, d, ARRAY_SIZE(d));   \
+   }
+
+static void chipone_enable(struct drm_bridge *bridge)
+{
+   struct chipone *icn = bridge_to_chipone(bridge);
+   struct drm_display_mode *mode = bridge_to_mode(bridge);
+
+   ICN6211_DSI(icn, 0x7a, 0xc1);
+
+   ICN6211_DSI(icn, HACTIVE_LI, mode->hdisplay & 0xff);
+
+   ICN6211_DSI(icn, VACTIVE_LI, mode->vdisplay & 0xff);
+
+   /**
+* lsb nibble: 2nd n

[PATCH v5 1/2] dt-bindings: display: bridge: Add Chipone ICN6211 bindings

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Converter bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produces RGB565, RGB666, RGB888 output format.

Add dt-bingings for it.

Signed-off-by: Jagan Teki 
Reviewed-by: Robert Foss 
Reviewed-by: Rob Herring 
---
Changes for v5:
- rebase drm-misc-next
- collect Rob, Robert review tags
Changes for v4:
- fixed Laurent comments
- added regulators
- replace reset with EN
- fixed warnings pointed by Robert
Changes for v3:
- updated to new dt-bindings style

 .../display/bridge/chipone,icn6211.yaml   | 99 +++
 MAINTAINERS   |  5 +
 2 files changed, 104 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
new file mode 100644
index ..62c3bd4cb28d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
+
+  It has a flexible configuration of MIPI DSI signal input and
+  produce RGB565, RGB666, RGB888 output format.
+
+properties:
+  compatible:
+enum:
+  - chipone,icn6211
+
+  reg:
+maxItems: 1
+description: virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: Bridge EN pin, chip is reset when EN is low.
+
+  vdd1-supply:
+description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
+
+  vdd2-supply:
+description: A 1.8V/2.5V/3.3V supply that power the PLL.
+
+  vdd3-supply:
+description: A 1.8V/2.5V/3.3V supply that power the RGB output.
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DSI input
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DPI output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  bridge@0 {
+compatible = "chipone,icn6211";
+reg = <0>;
+enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+ports {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  port@0 {
+reg = <0>;
+
+bridge_in_dsi: endpoint {
+  remote-endpoint = <&dsi_out_bridge>;
+};
+  };
+
+  port@1 {
+reg = <1>;
+
+bridge_out_panel: endpoint {
+  remote-endpoint = <&panel_out_bridge>;
+};
+  };
+};
+  };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b705ba51c54..b9d11101d060 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5568,6 +5568,11 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml
 F: drivers/gpu/drm/panel/panel-boe-himax8279d.c
 
+DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
+
 DRM DRIVER FOR FARADAY TVE200 TV ENCODER
 M: Linus Walleij 
 S: Maintained
-- 
2.25.1

[PATCH v4 2/2] drm: bridge: Add Chipone ICN6211 MIPI-DSI to RGB bridge

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Converter bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produce RGB565, RGB666, RGB888 output format.

Add bridge driver for it.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- added regulators
- replace reset with EN
- fixed warnings pointed by Robert
Changes for v3:
- updated the driver to inline with new drm bridge style

 MAINTAINERS  |   1 +
 drivers/gpu/drm/bridge/Kconfig   |  13 +
 drivers/gpu/drm/bridge/Makefile  |   1 +
 drivers/gpu/drm/bridge/chipone-icn6211.c | 293 +++
 4 files changed, 308 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/chipone-icn6211.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 065cbdc889d3..9c59402e51bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5533,6 +5533,7 @@ DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER 
BRIDGE
 M: Jagan Teki 
 S: Maintained
 F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
+F: drivers/gpu/drm/bridge/chipone-icn6211.c
 
 DRM DRIVER FOR FARADAY TVE200 TV ENCODER
 M: Linus Walleij 
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3..330ee70ed746 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,19 @@ config DRM_CDNS_DSI
  Support Cadence DPI to DSI bridge. This is an internal
  bridge and is meant to be directly embedded in a SoC.
 
+config DRM_CHIPONE_ICN6211
+   tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
+   depends on OF
+   select DRM_MIPI_DSI
+   select DRM_PANEL_BRIDGE
+   help
+ ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
+
+ It has a flexible configuration of MIPI DSI signal input
+ and produce RGB565, RGB666, RGB888 output format.
+
+ If in doubt, say "N".
+
 config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d..3eb84b638988 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
 obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
 obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
 obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c 
b/drivers/gpu/drm/bridge/chipone-icn6211.c
new file mode 100644
index ..a6151db95586
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define HACTIVE_LI 0x20
+#define VACTIVE_LI 0x21
+#define VACTIVE_HACTIVE_HI 0x22
+#define HFP_LI 0x23
+#define HSYNC_LI   0x24
+#define HBP_LI 0x25
+#define HFP_HSW_HBP_HI 0x26
+#define VFP0x27
+#define VSYNC  0x28
+#define VBP0x29
+
+struct chipone {
+   struct device *dev;
+   struct drm_bridge bridge;
+   struct drm_bridge *panel_bridge;
+   struct gpio_desc *enable_gpio;
+   struct regulator *vdd1;
+   struct regulator *vdd2;
+   struct regulator *vdd3;
+};
+
+static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct chipone, bridge);
+}
+
+static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
+{
+   return &bridge->encoder->crtc->state->adjusted_mode;
+}
+
+static inline int chipone_dsi_write(struct chipone *icn,  const void *seq,
+   size_t len)
+{
+   struct mipi_dsi_device *dsi = to_mipi_dsi_device(icn->dev);
+
+   return mipi_dsi_generic_write(dsi, seq, len);
+}
+
+#define ICN6211_DSI(icn, seq...)   \
+   {   \
+   const u8 d[] = { seq }; \
+   chipone_dsi_write(icn, d, ARRAY_SIZE(d));   \
+   }
+
+static void chipone_enable(struct drm_bridge *bridge)
+{
+   struct chipone *icn = bridge_to_chipone(bridge);
+   struct drm_display_mode *mode = bridge_to_mode(bridge);
+
+   ICN6211_DSI(icn, 0x7a, 0xc1);
+
+   ICN6211_DSI(icn, HACTIVE_LI, mode->hdisplay & 0xff);
+
+   ICN6211_DSI(icn, VACTIVE_LI, mode->vdisplay & 0xff);
+
+   /**
+* lsb nibble: 2nd nibble of hdisplay
+* msb nibble: 2nd nibble of vdisplay
+*/
+   ICN6211_DS

[PATCH v4 1/2] dt-bindings: display: bridge: Add Chipone ICN6211 bindings

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Converter bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produces RGB565, RGB666, RGB888 output format.

Add dt-bingings for it.

Signed-off-by: Jagan Teki 
---
Changes for v4:
- fixed Laurent comments
- added regulators
- replace reset with EN
- fixed warnings pointed by Robert
Changes for v3:
- updated to new dt-bindings style

 .../display/bridge/chipone,icn6211.yaml   | 99 +++
 MAINTAINERS   |  5 +
 2 files changed, 104 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
new file mode 100644
index ..62c3bd4cb28d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
+
+  It has a flexible configuration of MIPI DSI signal input and
+  produce RGB565, RGB666, RGB888 output format.
+
+properties:
+  compatible:
+enum:
+  - chipone,icn6211
+
+  reg:
+maxItems: 1
+description: virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: Bridge EN pin, chip is reset when EN is low.
+
+  vdd1-supply:
+description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
+
+  vdd2-supply:
+description: A 1.8V/2.5V/3.3V supply that power the PLL.
+
+  vdd3-supply:
+description: A 1.8V/2.5V/3.3V supply that power the RGB output.
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DSI input
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DPI output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  bridge@0 {
+compatible = "chipone,icn6211";
+reg = <0>;
+enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+ports {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  port@0 {
+reg = <0>;
+
+bridge_in_dsi: endpoint {
+  remote-endpoint = <&dsi_out_bridge>;
+};
+  };
+
+  port@1 {
+reg = <1>;
+
+bridge_out_panel: endpoint {
+  remote-endpoint = <&panel_out_bridge>;
+};
+  };
+};
+  };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d241b832aae..065cbdc889d3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5529,6 +5529,11 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml
 F: drivers/gpu/drm/panel/panel-boe-himax8279d.c
 
+DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
+
 DRM DRIVER FOR FARADAY TVE200 TV ENCODER
 M: Linus Walleij 
 S: Maintained
-- 
2.25.1

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

Hi Laurent,

On Thu, Mar 4, 2021 at 4:29 AM Laurent Pinchart
 wrote:
>
> Hi Jagan,
>
> On Wed, Mar 03, 2021 at 08:08:35PM +0530, Jagan Teki wrote:
> > On Wed, Feb 24, 2021 at 6:44 PM Laurent Pinchart wrote:
> > > On Wed, Feb 24, 2021 at 06:07:43PM +0530, Jagan Teki wrote:
> > > > On Mon, Feb 15, 2021 at 5:48 PM Laurent Pinchart wrote:
> > > > > On Sun, Feb 14, 2021 at 11:22:10PM +0530, Jagan Teki wrote:
> > > > > > ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.
> > > > > >
> > > > > > It has a flexible configuration of MIPI DSI signal input and
> > > > > > produce RGB565, RGB666, RGB888 output format.
> > > > > >
> > > > > > Add dt-bingings for it.
> > > > > >
> > > > > > Signed-off-by: Jagan Teki 
> > > > > > ---
> > > > > > Changes for v3:
> > > > > > - updated to new dt-bindings style
> > > > > >
> > > > > >  .../display/bridge/chipone,icn6211.yaml   | 90 
> > > > > > +++
> > > > > >  1 file changed, 90 insertions(+)
> > > > > >  create mode 100644 
> > > > > > Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > > >
> > > > > > diff --git 
> > > > > > a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > > >  
> > > > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > > > new file mode 100644
> > > > > > index ..13764f13fe46
> > > > > > --- /dev/null
> > > > > > +++ 
> > > > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > > > @@ -0,0 +1,90 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML 1.2
> > > > > > +---
> > > > > > +$id: 
> > > > > > http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
> > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > > +
> > > > > > +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
> > > > > > +
> > > > > > +maintainers:
> > > > > > +  - Jagan Teki 
> > > > > > +
> > > > > > +description: |
> > > > > > +  ICN6211 is MIPI-DSI to RGB Convertor bridge from chipone.
> > > > > > +
> > > > > > +  It has a flexible configuration of MIPI DSI signal input and
> > > > > > +  produce RGB565, RGB666, RGB888 output format.
> > > > >
> > > > > How does one select between the output formats ? Should the output
> > > > > connection option be described in the device tree ?
> > > >
> > > > I think that is a good option to select output formats via dts. what
> > > > if it makes it a generic property like data-lanes? since it is common
> > > > across many other bridges.
> > >
> > > Describing the output connection in the device tree sounds like a good
> > > idea indeed. The bus-width property could be used for this, maybe along
> > > the lines of
> > > https://lore.kernel.org/dri-devel/20201013020619.gg3...@pendragon.ideasonboard.com/.
> >
> > I have seen an issue by passing bus-width where the same bus-with 24
> > can use by RGB888 and RGB666 according to
> > mipi_dsi_pixel_format_to_bpp. Having a default RGB888 format now and
> > update it when it supports properly, can be a good Idea I thought of.
> > Let me know if you have any comments?
>
> I'm fine with hardcoding a default for now. If a given bus wiring (which
> is described in DT by bus-width) can transport different formats, that's
> something that should be configured dynamically, either by querying what
> format a sink (such as a panel) requires, or if both the source and the
> sink can support different formats, possibly by involving userspace in
> the selection.

Not sure how we can get userspace involvement in DRM here, but if
source and sink can have different formats then having precedence to
the source would be a good option as it handles low-level
configuration for formats.

Look like it is worth trying-feature. Maybe we can come up with some
RFC and have a discussion.

Jagan.

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

On Wed, Feb 24, 2021 at 6:44 PM Laurent Pinchart
 wrote:
>
> Hi Jagan,
>
> On Wed, Feb 24, 2021 at 06:07:43PM +0530, Jagan Teki wrote:
> > On Mon, Feb 15, 2021 at 5:48 PM Laurent Pinchart wrote:
> > > On Sun, Feb 14, 2021 at 11:22:10PM +0530, Jagan Teki wrote:
> > > > ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.
> > > >
> > > > It has a flexible configuration of MIPI DSI signal input and
> > > > produce RGB565, RGB666, RGB888 output format.
> > > >
> > > > Add dt-bingings for it.
> > > >
> > > > Signed-off-by: Jagan Teki 
> > > > ---
> > > > Changes for v3:
> > > > - updated to new dt-bindings style
> > > >
> > > >  .../display/bridge/chipone,icn6211.yaml   | 90 +++
> > > >  1 file changed, 90 insertions(+)
> > > >  create mode 100644 
> > > > Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > >
> > > > diff --git 
> > > > a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
> > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > new file mode 100644
> > > > index ..13764f13fe46
> > > > --- /dev/null
> > > > +++ 
> > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > @@ -0,0 +1,90 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
> > > > +
> > > > +maintainers:
> > > > +  - Jagan Teki 
> > > > +
> > > > +description: |
> > > > +  ICN6211 is MIPI-DSI to RGB Convertor bridge from chipone.
> > > > +
> > > > +  It has a flexible configuration of MIPI DSI signal input and
> > > > +  produce RGB565, RGB666, RGB888 output format.
> > >
> > > How does one select between the output formats ? Should the output
> > > connection option be described in the device tree ?
> >
> > I think that is a good option to select output formats via dts. what
> > if it makes it a generic property like data-lanes? since it is common
> > across many other bridges.
>
> Describing the output connection in the device tree sounds like a good
> idea indeed. The bus-width property could be used for this, maybe along
> the lines of
> https://lore.kernel.org/dri-devel/20201013020619.gg3...@pendragon.ideasonboard.com/.

I have seen an issue by passing bus-width where the same bus-with 24
can use by RGB888 and RGB666 according to
mipi_dsi_pixel_format_to_bpp. Having a default RGB888 format now and
update it when it supports properly, can be a good Idea I thought of.
Let me know if you have any comments?

Jagan.

Re: [PATCH v3 6/7] drm: sun4i: dsi: Use drm_panel_bridge, connector API

[Jagan Teki]

On Tue, Mar 2, 2021 at 10:05 PM Maxime Ripard  wrote:
>
> On Fri, Feb 26, 2021 at 10:40:24PM +0530, Jagan Teki wrote:
> > On Fri, Feb 26, 2021 at 10:27 PM Maxime Ripard  wrote:
> > >
> > > Hi,
> > >
> > > On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> > > > Use drm_panel_bridge to replace manual panel handling code.
> > > >
> > > > This simplifies the driver to allows all components in the
> > > > display pipeline to be treated as bridges, paving the way
> > > > to generic connector handling.
> > > >
> > > > Use drm_bridge_connector_init to create a connector for display
> > > > pipelines that use drm_bridge.
> > > >
> > > > This allows splitting connector operations across multiple bridges
> > > > when necessary, instead of having the last bridge in the chain
> > > > creating the connector and handling all connector operations
> > > > internally.
> > > >
> > > > Signed-off-by: Jagan Teki 
> > >
> > > Most of the code removed in that patch was actually introduced earlier
> > > which feels a bit weird. Is there a reason we can't do that one first,
> > > and then introduce the bridge support?
> >
> > This patch adds new bridge API's which requires the driver has to
> > support the bridge first.
>
> I'm not sure what you're saying, you can definitely have a bridge
> without support for a downstream bridge.

I understand your point. what I'm saying here is, This patch
introduces two new bridge API's

devm_drm_panel_bridge_add
drm_bridge_connector_init

In order to add these API's the driver has to support the bridge
first. All the patches before this one support bridge and this patch
introduce new APIs, ie the reason we have code removed in this patch
which has been added before.

Okay. I think I will send the next version series till bridge
conversion. Improvement patches like this can take care of later
versions and even it depends on Patch v3 5/7 which indeed require a
separate discussion. This way it makes less confusion.

Hope it's fine for you?

Jagan.

[PATCH] drm/stm: ltdc: Use simple encoder

[Jagan Teki]

STM ltdc driver uses an empty implementation for its encoder.
Replace the code with the generic simple encoder.

Signed-off-by: Jagan Teki 
---
 drivers/gpu/drm/stm/ltdc.c | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 7812094f93d6..aeeb43524ca0 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -1020,14 +1021,6 @@ static int ltdc_crtc_init(struct drm_device *ddev, 
struct drm_crtc *crtc)
return ret;
 }
 
-/*
- * DRM_ENCODER
- */
-
-static const struct drm_encoder_funcs ltdc_encoder_funcs = {
-   .destroy = drm_encoder_cleanup,
-};
-
 static void ltdc_encoder_disable(struct drm_encoder *encoder)
 {
struct drm_device *ddev = encoder->dev;
@@ -1088,8 +1081,7 @@ static int ltdc_encoder_init(struct drm_device *ddev, 
struct drm_bridge *bridge)
encoder->possible_crtcs = CRTC_MASK;
encoder->possible_clones = 0;   /* No cloning support */
 
-   drm_encoder_init(ddev, encoder, <dc_encoder_funcs,
-DRM_MODE_ENCODER_DPI, NULL);
+   drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI);
 
drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs);
 
-- 
2.25.1

[PATCH v3 10/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Jagan Teki]

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none 

 arch/arm/boot/dts/Makefile|  1 +
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   | 47 +++
 2 files changed, 48 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6dc39bddaf7e..e86c46d7ca66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1074,6 +1074,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
+   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
new file mode 100644
index ..ec9f1d1cd50f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
+   compatible = "engicam,icore-stm32mp1-edimm2.2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v3 08/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Jagan Teki]

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none 

 arch/arm/boot/dts/Makefile|  1 +
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47 +++
 2 files changed, 48 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1332622a3f9f..6dc39bddaf7e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1073,6 +1073,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
+   stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
new file mode 100644
index ..d3058a036c74
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
+   compatible = "engicam,icore-stm32mp1-ctouch2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v3 09/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation
Board from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none 

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 3e45516403ce..01f595b8ae1b 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -67,7 +67,9 @@ properties:
 
   - description: Engicam i.Core STM32MP1 SoM based Boards
 items:
-  - const: engicam,icore-stm32mp1-ctouch2# STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - enum:
+  - engicam,icore-stm32mp1-ctouch2   # STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - engicam,icore-stm32mp1-edimm2.2  # STM32MP1 Engicam i.Core 
STM32MP1 EDIMM2.2 Starter Kit
   - const: engicam,icore-stm32mp1# STM32MP1 Engicam i.Core 
STM32MP1 SoM
   - const: st,stm32mp157
 
-- 
2.25.1

[PATCH v3 07/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features

i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- add device_type 

 .../boot/dts/stm32mp157a-icore-stm32mp1.dtsi  | 196 ++
 1 file changed, 196 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi

diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
new file mode 100644
index ..01166ccacf2b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,icore-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   device_type = "memory";
+   reg = <0xc000 0x2000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_usb: regulator-vdd-usb {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_usb";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdda: regulator-vdda {
+   compatible = "regulator-fixed";
+   regulator-name = "vdda";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_ddr: regulator-vdd-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   };
+
+   vtt_ddr: regulator-vtt-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vtt_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+   regulator-always-on;
+   vin-supply = <&vdd>;
+   };
+
+   vref_ddr: regulator-vref-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vref_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+ 

[PATCH v3 05/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated commit message
Changes for v2:
- don't create carrier board dtsi, add it in final dts.

 arch/arm/boot/dts/Makefile|   1 +
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 2 files changed, 155 insertions(+)
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b4a9cd071f99..1332622a3f9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1072,6 +1072,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git 
a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
new file mode 100644
index ..674b2d330dc4
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
+   default-on;
+   };
+
+   lcd_3v3: regulator-lcd-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "lcd_3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   power-supply = <&panel_pwr>;
+   };
+
+   panel_pwr: regulator-panel-pwr {
+   compatible = "regulator-fixed";
+   regulator-name = "panel_pwr";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
+   regulator-always-on;
+   };
+
+   panel {
+   compatible = "auo,b101aw03";
+   backlight = <&backlight>;
+   enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
+   power-supply = <&lcd_3v3>;
+
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+   };
+};
+
+&i2c2 {
+   i2c-scl-falling-time-ns = <20>;
+   i2c-scl-rising-time-ns = <185>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&i2c2_pins_a>;
+   pinctrl-1 = <&i2c2_sleep_pins_a>;
+   status = "okay";
+};
+
+<dc {
+   pinctrl-names = "default";
+   pinctrl-0 = <<dc_pins>;
+   status = "okay";
+
+   port {
+   ltdc_ep0_out: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&panel_in>;
+   };
+   };
+};
+
+&pinctrl {
+   ltdc_pins: ltdc {
+   pins {
+   pinmux = , /* LTDC_B2 */
+   

[PATCH v3 06/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none 

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 255d3ba50c63..3e45516403ce 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -65,6 +65,12 @@ properties:
   - const: st,stm32mp157c-ed1
   - const: st,stm32mp157
 
+  - description: Engicam i.Core STM32MP1 SoM based Boards
+items:
+  - const: engicam,icore-stm32mp1-ctouch2# STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - const: engicam,icore-stm32mp1# STM32MP1 Engicam i.Core 
STM32MP1 SoM
+  - const: st,stm32mp157
+
   - description: Engicam MicroGEA STM32MP1 SoM based Boards
 items:
   - enum:
-- 
2.25.1

[PATCH v3 04/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

7" OF is a capacitive touch 7" Open Frame panel solutions.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add bindings for it.

Acked-by: Rob Herring 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated commit message
Changes for v2:
- collect a-b

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 56b7e0b800b3..255d3ba50c63 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -67,7 +67,9 @@ properties:
 
   - description: Engicam MicroGEA STM32MP1 SoM based Boards
 items:
-  - const: engicam,microgea-stm32mp1-microdev2.0
+  - enum:
+  - engicam,microgea-stm32mp1-microdev2.0
+  - engicam,microgea-stm32mp1-microdev2.0-of7
   - const: engicam,microgea-stm32mp1
   - const: st,stm32mp157
 
-- 
2.25.1

[PATCH v3 00/10] ARM: dts: stm32: Add Engicam STM32MP1 SoM

[Jagan Teki]

This is the initial series to support Engicam MicroGEA STM32MP1 and
i.Core STM32MP1 SoM and it's associated carrier board dts(i) support.

Changes for v3:
- fixed v2 comments
- updated commit messages
Changes for v2:
- fixed v1 comments
- add i.Core STM32MP1 SoM 

Any inputs?
Jagan.

Jagan Teki (10):
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
  dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

 .../devicetree/bindings/arm/stm32/stm32.yaml  |  17 ++
 arch/arm/boot/dts/Makefile|   4 +
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts|  47 +
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 +
 .../boot/dts/stm32mp157a-icore-stm32mp1.dtsi  | 196 ++
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 +
 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 +
 8 files changed, 668 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

-- 
2.25.1

[PATCH v3 01/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0

[Jagan Teki]

MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated commit message
Changes for v2:
- none

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index e7525a3395e5..56b7e0b800b3 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -64,6 +64,13 @@ properties:
   - const: st,stm32mp157c-ev1
   - const: st,stm32mp157c-ed1
   - const: st,stm32mp157
+
+  - description: Engicam MicroGEA STM32MP1 SoM based Boards
+items:
+  - const: engicam,microgea-stm32mp1-microdev2.0
+  - const: engicam,microgea-stm32mp1
+  - const: st,stm32mp157
+
   - description: Octavo OSD32MP15x System-in-Package based boards
 items:
   - enum:
-- 
2.25.1

[PATCH v3 02/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- add device_type
- updated commit message
Changes for v2:
- none

 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 ++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
new file mode 100644
index ..0b85175f151e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   device_type = "memory";
+   reg = <0xc000 0x1000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vin: regulator-vin {
+   compatible = "regulator-fixed";
+   regulator-name = "vin";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vddq_ddr: regulator-vddq-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vddq_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+};
+
+&dts {
+   status = "okay";
+};
+
+&fmc {
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&fmc_pins_a>;
+   pinctrl-1 = <&fmc_sleep_pins_a>;
+   status = "okay";
+
+   nand-controller@4,0 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   nand-on-flash-bbt;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+   };
+};
+
+&ipcc {
+   status = "okay";
+};
+
+&iwdg2{
+   timeout-sec = <32>;
+   status = "okay";
+};
+
+&m4_rproc

[PATCH v3 03/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

[Jagan Teki]

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated commit message
Changes for v2:
- don't create carrier board dtsi, add it in final dts.

 arch/arm/boot/dts/Makefile|  1 +
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++
 2 files changed, 56 insertions(+)
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9f9f3e49132a..b4a9cd071f99 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
new file mode 100644
index ..7a75868164dc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&vdd>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
+
+/* J31: RS323 */
+&uart8 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart8_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

Re: [PATCH v3 6/7] drm: sun4i: dsi: Use drm_panel_bridge, connector API

[Jagan Teki]

On Fri, Feb 26, 2021 at 10:27 PM Maxime Ripard  wrote:
>
> Hi,
>
> On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> > Use drm_panel_bridge to replace manual panel handling code.
> >
> > This simplifies the driver to allows all components in the
> > display pipeline to be treated as bridges, paving the way
> > to generic connector handling.
> >
> > Use drm_bridge_connector_init to create a connector for display
> > pipelines that use drm_bridge.
> >
> > This allows splitting connector operations across multiple bridges
> > when necessary, instead of having the last bridge in the chain
> > creating the connector and handling all connector operations
> > internally.
> >
> > Signed-off-by: Jagan Teki 
>
> Most of the code removed in that patch was actually introduced earlier
> which feels a bit weird. Is there a reason we can't do that one first,
> and then introduce the bridge support?

This patch adds new bridge API's which requires the driver has to
support the bridge first.

Jagan.

Re: [PATCH v2 02/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

Hi Alexandre,

On Fri, Feb 26, 2021 at 9:42 PM Alexandre TORGUE
 wrote:
>
> Hi Jagan
>
> On 2/26/21 8:02 AM, Jagan Teki wrote:
> > MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> >
> > General features:
> > - STM32MP157AAC
> > - Up to 1GB DDR3L-800
> > - 512MB Nand flash
> > - I2S
> >
> > MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
> > boards for creating complete platform solutions.
> >
> > Add support for it.
> >
> > Signed-off-by: Matteo Lisi 
> > Signed-off-by: Francesco Utel 
> > Signed-off-by: Mirko Ardinghi 
> > Signed-off-by: Jagan Teki 
>
> Minor question: if the stm32mp157 is soldered on Microdev boards why do
> you mention it in this commit message ?

It was there in the commit message:

> > General features:
> > - STM32MP157AAC
> > - Up to 1GB DDR3L-800
> > - 512MB Nand flash
> > - I2S

>
> + a minor comment bellow.
>
> thanks
> Alex
>
> > ---
> > Changes for v2:
> > - none
> >
> >   .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
> >   1 file changed, 147 insertions(+)
> >   create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> >
> > diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
> > b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> > new file mode 100644
> > index ..97d569107bfe
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> > @@ -0,0 +1,147 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +/*
> > + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> > + * Copyright (c) 2020 Engicam srl
> > + * Copyright (c) 2020 Amarula Solutons(India)
> > + */
> > +
> > +/ {
> > + compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
> > +
> > + memory@c000 {
>
> you could add   device_type = "memory";

Okay.

Jagan.

Re: [PATCH 2/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

On Fri, Feb 26, 2021 at 8:39 PM Alexandre TORGUE
 wrote:
>
> Hi Jagan
>
> On 2/24/21 7:05 PM, Jagan Teki wrote:
> > On Mon, Jan 25, 2021 at 8:35 PM Alexandre TORGUE
> >  wrote:
> >>
> >> Hi,
> >>
> >> On 12/23/20 8:13 PM, Jagan Teki wrote:
> >>> MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> >>>
> >>> General features:
> >>> - STM32MP157AAC
> >>> - Up to 1GB DDR3L-800
> >>> - 512MB Nand flash
> >>> - I2S
> >>>
> >>> MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
> >>> boards for creating complete platform solutions.
> >>>
> >>> Add support for it.
> >>>
> >>> Signed-off-by: Matteo Lisi 
> >>> Signed-off-by: Francesco Utel 
> >>> Signed-off-by: Mirko Ardinghi 
> >>> Signed-off-by: Jagan Teki 
> >>> ---
> >>>.../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
> >>>1 file changed, 147 insertions(+)
> >>>create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> >>>
> >>> diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
> >>> b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> >>> new file mode 100644
> >>> index ..97d569107bfe
> >>> --- /dev/null
> >>> +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> >>> @@ -0,0 +1,147 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> >>> +/*
> >>> + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> >>> + * Copyright (c) 2020 Engicam srl
> >>> + * Copyright (c) 2020 Amarula Solutons(India)
> >>> + */
> >>> +
> >>
> >> If STM32MP157AAC is soldered onto this board, you should include SoC
> >> dtsi here and no into MicroDev 2.0 board. No ?
> >
> > No, it's an SoM dtsi. and it can be associated with the respective
> > carrier board and include files are attached in its dts.
> >
> > Please check the next patches on this series.
> Ok, I thought it was a mistake as you mentioned "- STM32MP157AAC" in
> your commit message.

Please check, v2 for this series. thanks!

Jagan.

Re: [PATCH] regulator: pf8x00: Use regulator_map_voltage_ascend for pf8x00_buck7_ops

[Jagan Teki]

On Tue, Feb 16, 2021 at 11:31 AM Axel Lin  wrote:
>
> The voltages in pf8x00_sw7_voltages are in ascendant order, so use
> regulator_map_voltage_ascend.
>
> Signed-off-by: Axel Lin 
> ---

Reviewed-by: Jagan Teki 

[PATCH v2 10/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Jagan Teki]

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 arch/arm/boot/dts/Makefile|  1 +
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   | 47 +++
 2 files changed, 48 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6dc39bddaf7e..e86c46d7ca66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1074,6 +1074,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
+   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
new file mode 100644
index ..ec9f1d1cd50f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
+   compatible = "engicam,icore-stm32mp1-edimm2.2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v2 06/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 255d3ba50c63..3e45516403ce 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -65,6 +65,12 @@ properties:
   - const: st,stm32mp157c-ed1
   - const: st,stm32mp157
 
+  - description: Engicam i.Core STM32MP1 SoM based Boards
+items:
+  - const: engicam,icore-stm32mp1-ctouch2# STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - const: engicam,icore-stm32mp1# STM32MP1 Engicam i.Core 
STM32MP1 SoM
+  - const: st,stm32mp157
+
   - description: Engicam MicroGEA STM32MP1 SoM based Boards
 items:
   - enum:
-- 
2.25.1

[PATCH v2 03/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

[Jagan Teki]

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- don't create carrier board dtsi, add it in final dts.

 arch/arm/boot/dts/Makefile|  1 +
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++
 2 files changed, 56 insertions(+)
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9f9f3e49132a..b4a9cd071f99 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
new file mode 100644
index ..7a75868164dc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&vdd>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
+
+/* J31: RS323 */
+&uart8 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart8_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v2 04/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

7" OF is a capacitive touch 7" Open Frame panel solutions.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add bindings for it.

Acked-by: Rob Herring 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect a-b 

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 56b7e0b800b3..255d3ba50c63 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -67,7 +67,9 @@ properties:
 
   - description: Engicam MicroGEA STM32MP1 SoM based Boards
 items:
-  - const: engicam,microgea-stm32mp1-microdev2.0
+  - enum:
+  - engicam,microgea-stm32mp1-microdev2.0
+  - engicam,microgea-stm32mp1-microdev2.0-of7
   - const: engicam,microgea-stm32mp1
   - const: st,stm32mp157
 
-- 
2.25.1

[PATCH v2 09/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation
Board from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 3e45516403ce..01f595b8ae1b 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -67,7 +67,9 @@ properties:
 
   - description: Engicam i.Core STM32MP1 SoM based Boards
 items:
-  - const: engicam,icore-stm32mp1-ctouch2# STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - enum:
+  - engicam,icore-stm32mp1-ctouch2   # STM32MP1 Engicam i.Core 
STM32MP1 C.TOUCH 2.0
+  - engicam,icore-stm32mp1-edimm2.2  # STM32MP1 Engicam i.Core 
STM32MP1 EDIMM2.2 Starter Kit
   - const: engicam,icore-stm32mp1# STM32MP1 Engicam i.Core 
STM32MP1 SoM
   - const: st,stm32mp157
 
-- 
2.25.1

[PATCH v2 05/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- don't create carrier board dtsi, add it in final dts.

 arch/arm/boot/dts/Makefile|   1 +
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 2 files changed, 155 insertions(+)
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b4a9cd071f99..1332622a3f9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1072,6 +1072,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git 
a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
new file mode 100644
index ..674b2d330dc4
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
+   default-on;
+   };
+
+   lcd_3v3: regulator-lcd-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "lcd_3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   power-supply = <&panel_pwr>;
+   };
+
+   panel_pwr: regulator-panel-pwr {
+   compatible = "regulator-fixed";
+   regulator-name = "panel_pwr";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
+   regulator-always-on;
+   };
+
+   panel {
+   compatible = "auo,b101aw03";
+   backlight = <&backlight>;
+   enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
+   power-supply = <&lcd_3v3>;
+
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+   };
+};
+
+&i2c2 {
+   i2c-scl-falling-time-ns = <20>;
+   i2c-scl-rising-time-ns = <185>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&i2c2_pins_a>;
+   pinctrl-1 = <&i2c2_sleep_pins_a>;
+   status = "okay";
+};
+
+<dc {
+   pinctrl-names = "default";
+   pinctrl-0 = <<dc_pins>;
+   status = "okay";
+
+   port {
+   ltdc_ep0_out: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&panel_in>;
+   };
+   };
+};
+
+&pinctrl {
+   ltdc_pins: ltdc {
+   pins {
+   pinmux = , /* LTDC_B2 */
+, /* LTDC_R6 */
+   

[PATCH v2 01/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index e7525a3395e5..56b7e0b800b3 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -64,6 +64,13 @@ properties:
   - const: st,stm32mp157c-ev1
   - const: st,stm32mp157c-ed1
   - const: st,stm32mp157
+
+  - description: Engicam MicroGEA STM32MP1 SoM based Boards
+items:
+  - const: engicam,microgea-stm32mp1-microdev2.0
+  - const: engicam,microgea-stm32mp1
+  - const: st,stm32mp157
+
   - description: Octavo OSD32MP15x System-in-Package based boards
 items:
   - enum:
-- 
2.25.1

[PATCH v2 08/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Jagan Teki]

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 arch/arm/boot/dts/Makefile|  1 +
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47 +++
 2 files changed, 48 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1332622a3f9f..6dc39bddaf7e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1073,6 +1073,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
+   stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
new file mode 100644
index ..d3058a036c74
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
+   compatible = "engicam,icore-stm32mp1-ctouch2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v2 00/10] ARM: dts: stm32: Add Engicam STM32MP1 SoM

[Jagan Teki]

This is the initial series to support Engicam MicroGEA STM32MP1 and
i.Core STM32MP1 SoM and it's associated carrier board dts(i) support.

Changes for v2:
- fixed v1 comments
- add i.Core STM32MP1 SoM 

Jagan Teki (10):
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
  dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

 .../devicetree/bindings/arm/stm32/stm32.yaml  |  17 ++
 arch/arm/boot/dts/Makefile|   4 +
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts|  47 +
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 +
 .../boot/dts/stm32mp157a-icore-stm32mp1.dtsi  | 195 ++
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 +
 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 +
 8 files changed, 666 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

-- 
2.25.1

[PATCH v2 07/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features

i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 .../boot/dts/stm32mp157a-icore-stm32mp1.dtsi  | 195 ++
 1 file changed, 195 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi

diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi 
b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
new file mode 100644
index ..c8e4b68c5661
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,icore-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   reg = <0xc000 0x2000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_usb: regulator-vdd-usb {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_usb";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdda: regulator-vdda {
+   compatible = "regulator-fixed";
+   regulator-name = "vdda";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_ddr: regulator-vdd-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   };
+
+   vtt_ddr: regulator-vtt-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vtt_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+   regulator-always-on;
+   vin-supply = <&vdd>;
+   };
+
+   vref_ddr: regulator-vref-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vref_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+   regulator-always-on;
+   vin-supply = <&

[PATCH v2 02/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
 1 file changed, 147 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
new file mode 100644
index ..97d569107bfe
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   reg = <0xc000 0x1000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vin: regulator-vin {
+   compatible = "regulator-fixed";
+   regulator-name = "vin";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vddq_ddr: regulator-vddq-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vddq_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+};
+
+&dts {
+   status = "okay";
+};
+
+&fmc {
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&fmc_pins_a>;
+   pinctrl-1 = <&fmc_sleep_pins_a>;
+   status = "okay";
+
+   nand-controller@4,0 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   nand-on-flash-bbt;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+   };
+};
+
+&ipcc {
+   status = "okay";
+};
+
+&iwdg2{
+   timeout-sec = <32>;
+   status = "okay";
+};
+
+&m4_rproc{
+   memory-region = <&retram>, <&mcuram>, <&mcuram2>, &

[PATCH v4 5/5] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once
Mainline Linux supported.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
Changes for v4:
- don't create carrier board dtsi, move changes in final dts.
Changes for v3:
- don't maintain common nodes and include it, if no feature diff
Changes for v2:
- enabled fec1 node
- updated commit message
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.
- add i2c nodes
- fixed v1 comments

 arch/arm64/boot/dts/freescale/Makefile|  1 +
 .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 97 +++
 2 files changed, 98 insertions(+)
 create mode 100644 
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 3b5957ff1606..d68ffa77b761 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
new file mode 100644
index ..a4a2ada14835
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+   model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
+   compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
+"fsl,imx8mm";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&fec1 {
+   status = "okay";
+};
+
+&i2c2 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2>;
+   status = "okay";
+};
+
+&i2c4 {
+   clock-frequency = <10>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4>;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl_i2c2: i2c2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL  0x41c3
+   MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_i2c4: i2c4grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL  0x41c3
+   MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_uart2: uart2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+   MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+   >;
+   };
+
+   pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+   fsl,pins = <
+   MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6   0x41
+   >;
+   };
+
+   pinctrl_usdhc1: usdhc1grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+   MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+   MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+   MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+   MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+   MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+   >;
+   };
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+   cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+   max-frequency = <5000>;
+   bus-width = <4>;
+   no-1-8-v;
+   pm-ignore-notify;
+   keep-power-in-suspend;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v4 4/5] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation
Board from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

Add bindings for it.

Signed-off-by: Jagan Teki 
Acked-by: Rob Herring 
---
Changes for v4:
- collect ack's
Changes for v3:
- fix dt-bindings
Changes for v2:
- update commit message

 Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
b/Documentation/devicetree/bindings/arm/fsl.yaml
index 949442d4f385..6d86a3a24983 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -690,7 +690,9 @@ properties:
 
   - description: Engicam i.Core MX8M Mini SoM based boards
 items:
-  - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - enum:
+  - engicam,icore-mx8mm-ctouch2# i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - engicam,icore-mx8mm-edimm2.2   # i.MX8MM Engicam i.Core 
MX8M Mini EDIMM2.2 Starter Kit
   - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core 
MX8M Mini SoM
   - const: fsl,imx8mm
 
-- 
2.25.1

[PATCH v4 3/5] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
Changes for v4:
- don't create carrier board dtsi, move changes in final dts.
Changes for v3:
- don't maintain common nodes and include it, if no feature diff
Changes for v2:
- enabled fec1 node
- updated commit message
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.
- add i2c nodes
- fixed v1 comments

 arch/arm64/boot/dts/freescale/Makefile|  1 +
 .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  | 97 +++
 2 files changed, 98 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..3b5957ff1606 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
new file mode 100644
index ..5389d6f2beba
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+   model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";
+   compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
+"fsl,imx8mm";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&fec1 {
+   status = "okay";
+};
+
+&i2c2 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2>;
+   status = "okay";
+};
+
+&i2c4 {
+   clock-frequency = <10>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4>;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl_i2c2: i2c2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL  0x41c3
+   MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_i2c4: i2c4grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL  0x41c3
+   MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_uart2: uart2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+   MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+   >;
+   };
+
+   pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+   fsl,pins = <
+   MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6   0x41
+   >;
+   };
+
+   pinctrl_usdhc1: usdhc1grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+   MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+   MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+   MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+   MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+   MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+   >;
+   };
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+   cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+   max-frequency = <5000>;
+   bus-width = <4>;
+   no-1-8-v;
+   pm-ignore-notify;
+   keep-power-in-suspend;
+   status = "okay";
+};
-- 
2.25.1

[PATCH v4 2/5] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.

General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features

i.Core MX8M Mini needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
Reviewed-by: Krzysztof Kozlowski 
---
Changes for v4:
- collect r-b
Changes for v3:
- keep regulator min/max hoping
Changes for v2:
- updated commit message
- add cpu nodes
- add fec1 node
- fixed pmic tree comments
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.

 .../dts/freescale/imx8mm-icore-mx8mm.dtsi | 232 ++
 1 file changed, 232 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
new file mode 100644
index ..b40148d728ea
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
+};
+
+&A53_0 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_1 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_2 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_3 {
+   cpu-supply = <®_buck4>;
+};
+
+&fec1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_fec1>;
+   phy-mode = "rgmii-id";
+   phy-handle = <ðphy>;
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy: ethernet-phy@3 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <3>;
+   reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+   reset-assert-us = <1>;
+   };
+   };
+};
+
+&i2c1 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1>;
+   status = "okay";
+
+   pmic@8 {
+   compatible = "nxp,pf8121a";
+   reg = <0x08>;
+
+   regulators {
+   reg_ldo1: ldo1 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo2: ldo2 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo3: ldo3 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo4: ldo4 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck1: buck1 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck2: buck2 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck3: buck3 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck4: buck4 {
+  

[PATCH v4 1/5] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Add bindings for it.

Signed-off-by: Jagan Teki 
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Rob Herring 
---
Changes for v4:
- collect ack's
Changes for v3:
- add proper bindings
Changes for v2:
- updated commit message

 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
b/Documentation/devicetree/bindings/arm/fsl.yaml
index 297c87f45db8..949442d4f385 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -688,6 +688,12 @@ properties:
   - variscite,var-som-mx8mm   # i.MX8MM Variscite VAR-SOM-MX8MM 
module
   - const: fsl,imx8mm
 
+  - description: Engicam i.Core MX8M Mini SoM based boards
+items:
+  - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core 
MX8M Mini SoM
+  - const: fsl,imx8mm
+
   - description: Kontron BL i.MX8MM (N801X S) Board
 items:
   - const: kontron,imx8mm-n801x-s
-- 
2.25.1

[PATCH v4 0/5] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini

[Jagan Teki]

Patch series for Engicam i.Core MX8M Mini SOM and it's associated 
carrier board dts(i) support.

Changes for v4:
- rebase on linux-next
- fixed Krzysztof comments
Changes for v3:
- don't maintain common nodes and include it, if no feature diff
- keep min/max regulator hoping
- collect Krzysztof r-b
- fix dt-bindings

Jagan Teki (5):
  dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
  dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

 .../devicetree/bindings/arm/fsl.yaml  |   8 +
 arch/arm64/boot/dts/freescale/Makefile|   2 +
 .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  |  97 
 .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts |  97 
 .../dts/freescale/imx8mm-icore-mx8mm.dtsi | 232 ++
 5 files changed, 436 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
 create mode 100644 
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi

-- 
2.25.1

Re: [PATCH 2/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

On Mon, Jan 25, 2021 at 8:35 PM Alexandre TORGUE
 wrote:
>
> Hi,
>
> On 12/23/20 8:13 PM, Jagan Teki wrote:
> > MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
> >
> > General features:
> > - STM32MP157AAC
> > - Up to 1GB DDR3L-800
> > - 512MB Nand flash
> > - I2S
> >
> > MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
> > boards for creating complete platform solutions.
> >
> > Add support for it.
> >
> > Signed-off-by: Matteo Lisi 
> > Signed-off-by: Francesco Utel 
> > Signed-off-by: Mirko Ardinghi 
> > Signed-off-by: Jagan Teki 
> > ---
> >   .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
> >   1 file changed, 147 insertions(+)
> >   create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> >
> > diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
> > b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> > new file mode 100644
> > index ..97d569107bfe
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
> > @@ -0,0 +1,147 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +/*
> > + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
> > + * Copyright (c) 2020 Engicam srl
> > + * Copyright (c) 2020 Amarula Solutons(India)
> > + */
> > +
>
> If STM32MP157AAC is soldered onto this board, you should include SoC
> dtsi here and no into MicroDev 2.0 board. No ?

No, it's an SoM dtsi. and it can be associated with the respective
carrier board and include files are attached in its dts.

Please check the next patches on this series.

Jagan.

Re: [PATCH] drm/bridge: dw-mipi-dsi: Move drm_bridge_add into probe

[Jagan Teki]

Hi Yannick,

Thanks for testing this change.

On Mon, Feb 15, 2021 at 1:39 PM yannick Fertre
 wrote:
>
> Hello Jagan, I tested your patch on the stm32mp1 board.
> Unfortunately, the dsi panel does not probe well with this patch. The
> problem is due to the panel which is placed in the node of the dsi
> bridge (no problem with i2c devices).
>
> Regarding component bindings for stm drivers, I am currently working on
> a new version.

1. All non-I2C bridges are attaching dsi via mipi_dsi_attach during
the bridge controller probe and that would be expecting
panel_or_bridge need to be in DSI host attach.

2. I2C bridges are attaching dsi via mipi_dsi_attach during the bridge
attach function and that would be expecting panel_or_bridge need to be
in DSI probe.

I believe these types of DSI controllers followed by DSI panels,
bridges are not available in Mainline. if I'm not mistaken.

Adding component bindings in this regards never helps, this seems to
be common for component or non-components DSI host drivers.

One way to handle this issue can be during drm helper initialization,
like attaching the dsi host instead of calling directly from bridge or
panel drivers.

Laurent, Heiko - let me know your suggestions if it make sense, thanks.

Jagan.

Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

Hi Riadh,

On Wed, Feb 17, 2021 at 8:44 PM Riadh Ghaddab  wrote:
>
> Hi Jagan,
>
> On 20/01/2021 12:21, Jagan Teki wrote:
>
> SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
> Texas Instruments.
>
> SN65DSI83, SN65DSI85 are variants of the same family of bridge
> controllers.
>
> Right now the bridge driver is supporting a single link, dual-link
> support requires to initiate I2C Channel B registers.
>
> Tested with STM32MP1 MIPI DSI host design configuration.
>
> Do you have the code to support the Dual channel LVDS feature ?
> If not I recently developed the code for a board using sn65dsi84 with Dual
> LVDS channel

I have the basic one, but not have the proper hardware to verify
dual-link. Please have a look at V2 of similar patches. We will sort
out the driver so-that it can work with possible configurations.

>
> Signed-off-by: Matteo Lisi 
> Signed-off-by: Jagan Teki 
> ---
>  MAINTAINERS   |   6 +
>  drivers/gpu/drm/bridge/Kconfig|  19 +
>  drivers/gpu/drm/bridge/Makefile   |   1 +
>  drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++
>  4 files changed, 514 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 12dd1fff2a39..44750ff7640c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5984,6 +5984,12 @@ S: Maintained
>  F: Documentation/devicetree/bindings/display/ti/
>  F: drivers/gpu/drm/omapdrm/
>
> +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
> +M: Jagan Teki 
> +S: Maintained
> +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
> +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c
> +
>  DRM DRIVERS FOR V3D
>  M: Eric Anholt 
>  S: Supported
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index e4110d6ca7b3..6494881bffb3 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -232,6 +232,25 @@ config DRM_TI_TFP410
>   help
>Texas Instruments TFP410 DVI/HDMI Transmitter driver
>
> +config DRM_TI_SN65DSI84
> + tristate "TI SN65DSI84 DSI to LVDS bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + select DRM_PANEL
> + select DRM_MIPI_DSI
> + help
> +  Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS
> +  bridge driver.
> +
> +  Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
> +  converts the formatted video data stream to a FlatLink compatible
> +  LVDS output operating at pixel clocks operating from 25 MHx to
> +  154 MHz.
> +
> +  SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with
> +  four data lanes per link.
> +
>  config DRM_TI_SN65DSI86
>   tristate "TI SN65DSI86 DSI to eDP bridge"
>   depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 86e7acc76f8d..3906052ef639 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
>  obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
>  obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
>  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o
>  obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
>  obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
>  obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c 
> b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> new file mode 100644
> index ..3ed1f9a7d898
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Engicam srl
> + * Copyright (C) 2021 Amarula Solutions(India)
> + * Author: Jagan Teki 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* sn65dsi84 registers */
> +#define SN65DSI_SOFT_RESET 0x09
> +#define SN65DSI_LVDS_CLK 0x0a
> +#define SN65DSI_CLK_DIV 0x0b
> +#define SN65DSI_CLK_PLL 0x0d
> +#define SN65DSI_DSI_CFG 0x10
> +#define SN65DSI_DSI_CLK_EQ 0x11
> +#define SN65DSI_DSI_CLK_RANGE 0x12
> +#define SN65DSI_LVDS_MODE 0x18
> +#define SN65DSI_CHA_LINE_LO 0x20
> +#define SN65DSI_CHA_LINE_HI 0x21
> +#define SN65DSI_CHA_VIRT_LO 0x24
> +#define SN65DSI_CHA_VIRT_HI 0x25
> +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28
> +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29
> +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c
> +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d
> +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30
>

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

Hi Laurent,

On Wed, Feb 24, 2021 at 6:44 PM Laurent Pinchart
 wrote:
>
> Hi Jagan,
>
> On Wed, Feb 24, 2021 at 06:07:43PM +0530, Jagan Teki wrote:
> > On Mon, Feb 15, 2021 at 5:48 PM Laurent Pinchart wrote:
> > > On Sun, Feb 14, 2021 at 11:22:10PM +0530, Jagan Teki wrote:
> > > > ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.
> > > >
> > > > It has a flexible configuration of MIPI DSI signal input and
> > > > produce RGB565, RGB666, RGB888 output format.
> > > >
> > > > Add dt-bingings for it.
> > > >
> > > > Signed-off-by: Jagan Teki 
> > > > ---
> > > > Changes for v3:
> > > > - updated to new dt-bindings style
> > > >
> > > >  .../display/bridge/chipone,icn6211.yaml   | 90 +++
> > > >  1 file changed, 90 insertions(+)
> > > >  create mode 100644 
> > > > Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > >
> > > > diff --git 
> > > > a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
> > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > new file mode 100644
> > > > index ..13764f13fe46
> > > > --- /dev/null
> > > > +++ 
> > > > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > > > @@ -0,0 +1,90 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
> > > > +
> > > > +maintainers:
> > > > +  - Jagan Teki 
> > > > +
> > > > +description: |
> > > > +  ICN6211 is MIPI-DSI to RGB Convertor bridge from chipone.
> > > > +
> > > > +  It has a flexible configuration of MIPI DSI signal input and
> > > > +  produce RGB565, RGB666, RGB888 output format.
> > >
> > > How does one select between the output formats ? Should the output
> > > connection option be described in the device tree ?
> >
> > I think that is a good option to select output formats via dts. what
> > if it makes it a generic property like data-lanes? since it is common
> > across many other bridges.
>
> Describing the output connection in the device tree sounds like a good
> idea indeed. The bus-width property could be used for this, maybe along
> the lines of
> https://lore.kernel.org/dri-devel/20201013020619.gg3...@pendragon.ideasonboard.com/.

I think this bridge is doing, what we discussed? am I correct?
Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml

>
> If, for a given wiring of the output, different formats could be used,
> then we would need to select them at runtime.

That means the opposite of what mipi_dsi_pixel_format_to_bpp is doing
right? like given bpp we need to select format.

Jagan.

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

Hi Laurent,

On Mon, Feb 15, 2021 at 5:48 PM Laurent Pinchart
 wrote:
>
> Hi Jagan,
>
> Thank you for the patch.
>
> On Sun, Feb 14, 2021 at 11:22:10PM +0530, Jagan Teki wrote:
> > ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.
> >
> > It has a flexible configuration of MIPI DSI signal input and
> > produce RGB565, RGB666, RGB888 output format.
> >
> > Add dt-bingings for it.
> >
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v3:
> > - updated to new dt-bindings style
> >
> >  .../display/bridge/chipone,icn6211.yaml   | 90 +++
> >  1 file changed, 90 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
> > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > new file mode 100644
> > index ..13764f13fe46
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
> > +
> > +maintainers:
> > +  - Jagan Teki 
> > +
> > +description: |
> > +  ICN6211 is MIPI-DSI to RGB Convertor bridge from chipone.
> > +
> > +  It has a flexible configuration of MIPI DSI signal input and
> > +  produce RGB565, RGB666, RGB888 output format.
>
> How does one select between the output formats ? Should the output
> connection option be described in the device tree ?

I think that is a good option to select output formats via dts. what
if it makes it a generic property like data-lanes? since it is common
across many other bridges.

>
> > +
> > +properties:
> > +  compatible:
> > +enum:
> > +  - chipone,icn6211
> > +
> > +  reg:
> > +maxItems: 1
> > +description: virtual channel number of a DSI peripheral
> > +
> > +  reset-gpios:
> > +description: GPIO connected for the reset pin
> > +
> > +  ports:
> > +$ref: /schemas/graph.yaml#/properties/ports
> > +
> > +properties:
> > +  port@0:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description:
> > +  Video port for MIPI DSI input
> > +
> > +  port@1:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description:
> > +  Video port for MIPI DPI output (panel or connector).
> > +
> > +required:
> > +  - port@0
> > +  - port@1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reset-gpios
> > +  - ports
>
> How about regulators ?

Will add it in the next version.

Jagan.

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

On Mon, Feb 15, 2021 at 5:28 PM Robert Foss  wrote:
>
> Hey Jagan,
>
> Thanks for submitting this.
>
> checkpatch.pl threw some typ-o warnings, and I listed them below. I
> think either spelling is correct, but 'spelling.txt' does list this as
> a typ-o explicitly, so I would suggest conforming to that just to
> silence the checkpatch warning.
>
> This patch also passes 'dt_binding_check' and 'dtbs_check', but I
> think I'd like to defer to Rob Herring for an actual r-b.
>
> On Sun, 14 Feb 2021 at 18:55, Jagan Teki  wrote:
> >
> > ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.
> >
> > It has a flexible configuration of MIPI DSI signal input and
> > produce RGB565, RGB666, RGB888 output format.
> >
> > Add dt-bingings for it.
> >
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v3:
> > - updated to new dt-bindings style
> >
> >  .../display/bridge/chipone,icn6211.yaml   | 90 +++
> >  1 file changed, 90 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
> > b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > new file mode 100644
> > index ..13764f13fe46
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
>
> $ scripts/checkpatch.pl --git HEAD~0
> WARNING: 'Convertor' may be misspelled - perhaps 'Converter'?

Thanks for pointing it.

I was aware of it before sending it and need to understand whether we
need to use vendor naming conversion or not. Chipone call these
devices are Convertor [1], So I have used the vendor notation for
better understanding.

Any comments are this would be welcome?

[1] http://en.chiponeic.com/content/details45_123.html

Jagan.

Re: [PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85

[Jagan Teki]

On Mon, Feb 15, 2021 at 2:32 PM Neil Armstrong  wrote:
>
> Hi,
>
> On 14/02/2021 18:44, Jagan Teki wrote:
> > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> > controller IC's from Texas Instruments.
> >
> > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >
> > Right now the bridge driver is supporting Channel A with single
> > link, so dt-bindings documented according to it.
>
> Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual 
> Channel DSI for SN65DSI85 even if not implemented in the driver ?

Patch documented only Single link LVDS as it only supported by driver.
Single link LVDS with Channel A configuration is common across all 3
variant chips. I have SN65DSI84 with Single link LVDS which is routed
in Channel A. Idea is to go with Single link and add double link later
and document the same.

Jagan.

[PATCH v3 5/7] drm: bridge: Queue the bridge chain instead of stacking

[Jagan Teki]

drm_bridge_attach has stacked the bridge chain, so the bridge
that gets pushed last can trigger its bridge function pre_enable
first from drm_atomic_bridge_chain_pre_enable.

This indeed gives a chance to trigger slave bridge pre_enable
first without triggering its host bridge pre_enable for the
usual host to slave device model like DSI host with panel slave.

For fully enabled bridge drivers, host bridge pre_enable has all
host related clock, reset, PHY configuration code that needs to
initialized before sending commands or configuration from a slave
to communicate its host.

Queue the bridge chain instead of stacking it so-that the bridges
that got enqueued first can have a chance to trigger first.

Cc: Maarten Lankhorst 
Cc: Thomas Zimmermann 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- new patch

 drivers/gpu/drm/drm_bridge.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
index 64f0effb52ac..e75d1a080c55 100644
--- a/drivers/gpu/drm/drm_bridge.c
+++ b/drivers/gpu/drm/drm_bridge.c
@@ -191,9 +191,9 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct 
drm_bridge *bridge,
bridge->encoder = encoder;
 
if (previous)
-   list_add(&bridge->chain_node, &previous->chain_node);
+   list_add_tail(&bridge->chain_node, &previous->chain_node);
else
-   list_add(&bridge->chain_node, &encoder->bridge_chain);
+   list_add_tail(&bridge->chain_node, &encoder->bridge_chain);
 
if (bridge->funcs->attach) {
ret = bridge->funcs->attach(bridge, flags);
-- 
2.25.1

[PATCH v3 4/7] drm: sun4i: dsi: Separate code for bridge pre_enable

[Jagan Teki]

The existing driver has an enablement code for initializing
clock, reset, PHY, DSI timings, and finally switching to HS
mode.

Move the clock, reset. PHY and DSI timings code into bridge
pre_enable and keep HS mode switch in enable.

As the driver supports fully enabled bridge functionalities,
this new enablement code separation will help to initialize
the host and slave bridge pre_enable, enable functions properly.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- new patch

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 6f3c5330a468..3cdc14daf25c 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -714,7 +714,7 @@ static int sun6i_dsi_start(struct sun6i_dsi *dsi,
return 0;
 }
 
-static void sun6i_dsi_bridge_enable(struct drm_bridge *bridge)
+static void sun6i_dsi_bridge_pre_enable(struct drm_bridge *bridge)
 {
struct drm_display_mode *mode = 
&bridge->encoder->crtc->state->adjusted_mode;
struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
@@ -775,6 +775,11 @@ static void sun6i_dsi_bridge_enable(struct drm_bridge 
*bridge)
 
if (dsi->panel_bridge)
dsi->panel_bridge->funcs->pre_enable(dsi->panel_bridge);
+}
+
+static void sun6i_dsi_bridge_enable(struct drm_bridge *bridge)
+{
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
 
/*
 * FIXME: This should be moved after the switch to HS mode.
@@ -883,6 +888,7 @@ static int sun6i_dsi_bridge_attach(struct drm_bridge 
*bridge,
 }
 
 static const struct drm_bridge_funcs sun6i_dsi_bridge_funcs = {
+   .pre_enable = sun6i_dsi_bridge_pre_enable,
.enable = sun6i_dsi_bridge_enable,
.disable= sun6i_dsi_bridge_disable,
.attach = sun6i_dsi_bridge_attach,
-- 
2.25.1

[DO NOT MERGE] [PATCH v3 7/7] ARM: dts: sun8i: bananapi-m2m: Enable S070WV20-CT16 panel

[Jagan Teki]

This patch add support for Bananapi S070WV20-CT16 panel to
BPI-M2M board.

Bananapi S070WV20-CT16 is a pure RGB output panel with ICN6211 DSI/RGB
convertor bridge, so enable bridge along with associated panel.

DSI panel connected via board DSI port with,
- DCDC1 as VCC-DSI supply
- PL5 gpio for bridge reset gpio pin
- PB7 gpio for lcd enable gpio pin
- PL4 gpio for backlight enable pin

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none 

 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 85 
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts 
b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index e1c75f7fa3ca..f3f63187badc 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -44,6 +44,7 @@
 #include "sun8i-a33.dtsi"
 
 #include 
+#include 
 
 / {
model = "BananaPi M2 Magic";
@@ -55,12 +56,21 @@ aliases {
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
+   mmc0 = &mmc0;
};
 
chosen {
stdout-path = "serial0:115200n8";
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <1 2 4 8 16 32 64 128 255>;
+   default-brightness-level = <8>;
+   enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PL4 
*/
+   };
+
leds {
compatible = "gpio-leds";
 
@@ -81,6 +91,18 @@ red {
};
};
 
+   panel {
+   compatible = "bananapi,s070wv20-ct16", "simple-panel";
+   enable-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN: PB7 
*/
+   backlight = <&backlight>;
+
+   port {
+   panel_out_bridge: endpoint {
+   remote-endpoint = <&bridge_out_panel>;
+   };
+   };
+   };
+
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
@@ -122,6 +144,59 @@ &dai {
status = "okay";
 };
 
+&de {
+   status = "okay";
+};
+
+&dphy {
+   status = "okay";
+};
+
+&dsi {
+   vcc-dsi-supply = <®_dcdc1>;  /* VCC-DSI */
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   dsi_out: port@0 {
+   reg = <0>;
+
+   dsi_out_bridge: endpoint {
+   remote-endpoint = <&bridge_out_dsi>;
+   };
+   };
+   };
+
+   bridge@0 {
+   compatible = "chipone,icn6211";
+   reg = <0>;
+   reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   bridge_in: port@0 {
+   reg = <0>;
+
+   bridge_out_dsi: endpoint {
+   remote-endpoint = <&dsi_out_bridge>;
+   };
+   };
+
+   bridge_out: port@1 {
+   reg = <1>;
+
+   bridge_out_panel: endpoint {
+   remote-endpoint = <&panel_out_bridge>;
+   };
+   };
+   };
+   };
+};
+
 &ehci0 {
status = "okay";
 };
@@ -157,6 +232,12 @@ &ohci0 {
status = "okay";
 };
 
+&pwm {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm0_pin>;
+   status = "okay";
+};
+
 &r_rsb {
status = "okay";
 
@@ -269,6 +350,10 @@ &sound {
status = "okay";
 };
 
+&tcon0 {
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
-- 
2.25.1

[PATCH v3 6/7] drm: sun4i: dsi: Use drm_panel_bridge, connector API

[Jagan Teki]

Use drm_panel_bridge to replace manual panel handling code.

This simplifies the driver to allows all components in the
display pipeline to be treated as bridges, paving the way
to generic connector handling.

Use drm_bridge_connector_init to create a connector for display
pipelines that use drm_bridge.

This allows splitting connector operations across multiple bridges
when necessary, instead of having the last bridge in the chain
creating the connector and handling all connector operations
internally.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- new patch

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 108 +++--
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |   7 --
 2 files changed, 27 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 3cdc14daf25c..5e5d3789b3df 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -20,6 +20,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -769,12 +770,6 @@ static void sun6i_dsi_bridge_pre_enable(struct drm_bridge 
*bridge)
phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
phy_configure(dsi->dphy, &opts);
phy_power_on(dsi->dphy);
-
-   if (dsi->panel)
-   drm_panel_prepare(dsi->panel);
-
-   if (dsi->panel_bridge)
-   dsi->panel_bridge->funcs->pre_enable(dsi->panel_bridge);
 }
 
 static void sun6i_dsi_bridge_enable(struct drm_bridge *bridge)
@@ -793,12 +788,6 @@ static void sun6i_dsi_bridge_enable(struct drm_bridge 
*bridge)
 * ordering on the panels I've tested it with, so I guess this
 * will do for now, until that IP is better understood.
 */
-   if (dsi->panel)
-   drm_panel_enable(dsi->panel);
-
-   if (dsi->panel_bridge)
-   dsi->panel_bridge->funcs->enable(dsi->panel_bridge);
-
sun6i_dsi_start(dsi, DSI_START_HSC);
 
udelay(1000);
@@ -812,14 +801,6 @@ static void sun6i_dsi_bridge_disable(struct drm_bridge 
*bridge)
 
DRM_DEBUG_DRIVER("Disabling DSI output\n");
 
-   if (dsi->panel) {
-   drm_panel_disable(dsi->panel);
-   drm_panel_unprepare(dsi->panel);
-   } else if (dsi->panel_bridge) {
-   dsi->panel_bridge->funcs->disable(dsi->panel_bridge);
-   dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
-   }
-
phy_power_off(dsi->dphy);
phy_exit(dsi->dphy);
 
@@ -828,63 +809,13 @@ static void sun6i_dsi_bridge_disable(struct drm_bridge 
*bridge)
regulator_disable(dsi->regulator);
 }
 
-static int sun6i_dsi_get_modes(struct drm_connector *connector)
-{
-   struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
-
-   return drm_panel_get_modes(dsi->panel, connector);
-}
-
-static const struct drm_connector_helper_funcs 
sun6i_dsi_connector_helper_funcs = {
-   .get_modes  = sun6i_dsi_get_modes,
-};
-
-static enum drm_connector_status
-sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
-{
-   struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
-
-   return dsi->panel ? connector_status_connected :
-   connector_status_disconnected;
-}
-
-static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
-   .detect = sun6i_dsi_connector_detect,
-   .fill_modes = drm_helper_probe_single_connector_modes,
-   .destroy= drm_connector_cleanup,
-   .reset  = drm_atomic_helper_connector_reset,
-   .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-   .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
-};
-
 static int sun6i_dsi_bridge_attach(struct drm_bridge *bridge,
   enum drm_bridge_attach_flags flags)
 {
struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
-   int ret;
-
-   if (dsi->panel_bridge)
-   return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, 
NULL, 0);
-
-   if (dsi->panel) {
-   drm_connector_helper_add(&dsi->connector,
-&sun6i_dsi_connector_helper_funcs);
-   ret = drm_connector_init(bridge->dev, &dsi->connector,
-&sun6i_dsi_connector_funcs,
-DRM_MODE_CONNECTOR_DSI);
-   if (ret) {
-   dev_err(dsi->dev, "Couldn't initialise the DSI 
connector\n");
-   goto err_cleanup_connector;
-   }
-
-   drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
-   }
-
-   return 0;
 
-err_cleanup

[PATCH v3 3/7] drm: sun4i: dsi: Convert to bridge driver

[Jagan Teki]

DRM bridge drivers have build-in handling of treating all display
pipeline components as bridges.

So, convert the existing to a drm bridge driver with a built-in
encoder support for compatibility with existing component drivers.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- new patch

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 75 --
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  6 +++
 2 files changed, 54 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 39321299dc27..6f3c5330a468 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -714,10 +714,10 @@ static int sun6i_dsi_start(struct sun6i_dsi *dsi,
return 0;
 }
 
-static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+static void sun6i_dsi_bridge_enable(struct drm_bridge *bridge)
 {
-   struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
-   struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+   struct drm_display_mode *mode = 
&bridge->encoder->crtc->state->adjusted_mode;
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
struct mipi_dsi_device *device = dsi->device;
union phy_configure_opts opts = { };
struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
@@ -801,9 +801,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
sun6i_dsi_start(dsi, DSI_START_HSD);
 }
 
-static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+static void sun6i_dsi_bridge_disable(struct drm_bridge *bridge)
 {
-   struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
 
DRM_DEBUG_DRIVER("Disabling DSI output\n");
 
@@ -852,9 +852,40 @@ static const struct drm_connector_funcs 
sun6i_dsi_connector_funcs = {
.atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 };
 
-static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
-   .disable= sun6i_dsi_encoder_disable,
-   .enable = sun6i_dsi_encoder_enable,
+static int sun6i_dsi_bridge_attach(struct drm_bridge *bridge,
+  enum drm_bridge_attach_flags flags)
+{
+   struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
+   int ret;
+
+   if (dsi->panel_bridge)
+   return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, 
NULL, 0);
+
+   if (dsi->panel) {
+   drm_connector_helper_add(&dsi->connector,
+&sun6i_dsi_connector_helper_funcs);
+   ret = drm_connector_init(bridge->dev, &dsi->connector,
+&sun6i_dsi_connector_funcs,
+DRM_MODE_CONNECTOR_DSI);
+   if (ret) {
+   dev_err(dsi->dev, "Couldn't initialise the DSI 
connector\n");
+   goto err_cleanup_connector;
+   }
+
+   drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
+   }
+
+   return 0;
+
+err_cleanup_connector:
+   drm_encoder_cleanup(&dsi->encoder);
+   return ret;
+}
+
+static const struct drm_bridge_funcs sun6i_dsi_bridge_funcs = {
+   .enable = sun6i_dsi_bridge_enable,
+   .disable= sun6i_dsi_bridge_disable,
+   .attach = sun6i_dsi_bridge_attach,
 };
 
 static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
@@ -1063,8 +1094,6 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
int ret;
 
-   drm_encoder_helper_add(&dsi->encoder,
-  &sun6i_dsi_enc_helper_funcs);
ret = drm_simple_encoder_init(drm, &dsi->encoder,
  DRM_MODE_ENCODER_DSI);
if (ret) {
@@ -1073,27 +1102,12 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
}
dsi->encoder.possible_crtcs = BIT(0);
 
-   drm_connector_helper_add(&dsi->connector,
-&sun6i_dsi_connector_helper_funcs);
-   ret = drm_connector_init(drm, &dsi->connector,
-&sun6i_dsi_connector_funcs,
-DRM_MODE_CONNECTOR_DSI);
+   ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 0);
if (ret) {
-   dev_err(dsi->dev,
-   "Couldn't initialise the DSI connector\n");
+   dev_err(dsi->dev, "Couldn't attach drm bridge\n");
goto err_cleanup_connector;
}
 
-   drm_connector_attach_encoder(&

[PATCH v3 0/7] drm: sun4i: dsi: Convert drm bridge

[Jagan Teki]

This series convert Allwinner DSI controller to full functional 
drm bridge driver for supporting slave panel, bridges.

Here, are the previous version changes[1].

The key concern about these changes is about kms hotplug which 
indeed not compatible with bridge conversion.  However, I did 
try several ways to support hotplug with the bridge but it's 
resulting in a deadlock where bind never attach bridge until 
bridge pointer found and bridge pointer cannot found until bind 
finishes. Any inputs on this would be appreciated.

[1] https://lwn.net/Articles/783127/

Any inputs?
Jagan.

Jagan Teki (7):
  drm: sun4i: dsi: Use drm_of_find_panel_or_bridge
  drm: sun4i: dsi: Add bridge support
  drm: sun4i: dsi: Convert to bridge driver
  drm: sun4i: dsi: Separate code for bridge pre_enable
  drm: bridge: Queue the bridge chain instead of stacking
  drm: sun4i: dsi: Use drm_panel_bridge, connector API
  [DO NOT MERGE] ARM: dts: sun8i: bananapi-m2m: Enable S070WV20-CT16 panel

 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts |  85 
 drivers/gpu/drm/drm_bridge.c |   4 +-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c   | 128 +--
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h   |  11 +-
 4 files changed, 150 insertions(+), 78 deletions(-)

-- 
2.25.1

[PATCH v3 2/7] drm: sun4i: dsi: Add bridge support

[Jagan Teki]

Some display panels would come up with a non-DSI output which
can have an option to connect DSI interface by means of bridge
converter.

This DSI to non-DSI bridge converter would require a bridge
driver that would communicate the DSI controller for bridge
functionalities.

So, add support for bridge functionalities in Allwinner DSI
controller.

Cc: Samuel Holland 
Signed-off-by: Jagan Teki 
---
Note: 
Samuel Holland, The existing kms hotplug dropped in order to 
attach the bridge properly. 

However, I did try several ways to support hotplug with the 
bridge but it's resulting in a deadlock where bind never attach 
bridge until bridge pointer found and bridge pointer cannot 
found until bind finishes. Any inputs on this would be appreciated.

Changes for v3:
- updated with new API's 

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 34 +-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  2 +-
 2 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 2e9e7b2d4145..39321299dc27 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -773,6 +773,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
if (dsi->panel)
drm_panel_prepare(dsi->panel);
 
+   if (dsi->panel_bridge)
+   dsi->panel_bridge->funcs->pre_enable(dsi->panel_bridge);
+
/*
 * FIXME: This should be moved after the switch to HS mode.
 *
@@ -788,6 +791,9 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder 
*encoder)
if (dsi->panel)
drm_panel_enable(dsi->panel);
 
+   if (dsi->panel_bridge)
+   dsi->panel_bridge->funcs->enable(dsi->panel_bridge);
+
sun6i_dsi_start(dsi, DSI_START_HSC);
 
udelay(1000);
@@ -804,6 +810,9 @@ static void sun6i_dsi_encoder_disable(struct drm_encoder 
*encoder)
if (dsi->panel) {
drm_panel_disable(dsi->panel);
drm_panel_unprepare(dsi->panel);
+   } else if (dsi->panel_bridge) {
+   dsi->panel_bridge->funcs->disable(dsi->panel_bridge);
+   dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
}
 
phy_power_off(dsi->dphy);
@@ -964,23 +973,17 @@ static int sun6i_dsi_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
 {
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
-   struct drm_panel *panel;
int ret;
 
ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
- &panel, NULL);
+ &dsi->panel, &dsi->panel_bridge);
if (ret)
return ret;
 
-   if (!dsi->drm || !dsi->drm->registered)
-   return -EPROBE_DEFER;
-
-   dsi->panel = panel;
dsi->device = device;
 
-   drm_kms_helper_hotplug_event(dsi->drm);
-
-   dev_info(host->dev, "Attached device %s\n", device->name);
+   dev_info(host->dev, "Attached %s %s\n",
+device->name, dsi->panel ? "panel" : "bridge");
 
return 0;
 }
@@ -991,9 +994,10 @@ static int sun6i_dsi_detach(struct mipi_dsi_host *host,
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
 
dsi->panel = NULL;
+   dsi->panel_bridge = NULL;
dsi->device = NULL;
 
-   drm_kms_helper_hotplug_event(dsi->drm);
+   drm_of_panel_bridge_remove(dsi->dev->of_node, 0, 0);
 
return 0;
 }
@@ -1082,7 +1086,13 @@ static int sun6i_dsi_bind(struct device *dev, struct 
device *master,
 
drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
 
-   dsi->drm = drm;
+   if (dsi->panel_bridge) {
+   ret = drm_bridge_attach(&dsi->encoder, dsi->panel_bridge, NULL, 
0);
+   if (ret) {
+   dev_err(dsi->dev, "Couldn't attach drm bridge\n");
+   goto err_cleanup_connector;
+   }
+   }
 
return 0;
 
@@ -1096,7 +1106,7 @@ static void sun6i_dsi_unbind(struct device *dev, struct 
device *master,
 {
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
 
-   dsi->drm = NULL;
+   drm_encoder_cleanup(&dsi->encoder);
 }
 
 static const struct component_ops sun6i_dsi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index c863900ae3b4..370ecb356a63 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -29,8 +29,8 @@ struct sun6i_dsi {
 
struct device   *dev;
struct mipi_dsi_device  *device;
-   struct drm_device   *drm;
struct drm_panel*panel;
+   struct drm_bridge   *panel_bridge;
 };
 
 static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
-- 
2.25.1

[PATCH v3 1/7] drm: sun4i: dsi: Use drm_of_find_panel_or_bridge

[Jagan Teki]

Replace of_drm_find_panel with drm_of_find_panel_or_bridge
for finding panel, this indeed help to find the bridge if
bridge support added.

Added NULL in bridge argument, same will replace with bridge
parameter once bridge supported.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- none

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 4f5efcace68e..2e9e7b2d4145 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -21,6 +21,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -963,10 +964,14 @@ static int sun6i_dsi_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
 {
struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
-   struct drm_panel *panel = of_drm_find_panel(device->dev.of_node);
+   struct drm_panel *panel;
+   int ret;
+
+   ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 0, 0,
+ &panel, NULL);
+   if (ret)
+   return ret;
 
-   if (IS_ERR(panel))
-   return PTR_ERR(panel);
if (!dsi->drm || !dsi->drm->registered)
return -EPROBE_DEFER;
 
-- 
2.25.1

[PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for Chipone ICN6211

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produce RGB565, RGB666, RGB888 output format.

Add dt-bingings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated to new dt-bindings style

 .../display/bridge/chipone,icn6211.yaml   | 90 +++
 1 file changed, 90 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml 
b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
new file mode 100644
index ..13764f13fe46
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  ICN6211 is MIPI-DSI to RGB Convertor bridge from chipone.
+
+  It has a flexible configuration of MIPI DSI signal input and
+  produce RGB565, RGB666, RGB888 output format.
+
+properties:
+  compatible:
+enum:
+  - chipone,icn6211
+
+  reg:
+maxItems: 1
+description: virtual channel number of a DSI peripheral
+
+  reset-gpios:
+description: GPIO connected for the reset pin
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DSI input
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+  Video port for MIPI DPI output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - reset-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  bridge@0 {
+compatible = "chipone,icn6211";
+reg = <0>;
+reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
+
+ports {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  bridge_in: port@0 {
+reg = <0>;
+
+bridge_out_dsi: endpoint {
+  remote-endpoint = <&dsi_out_bridge>;
+};
+  };
+
+  bridge_out: port@1 {
+reg = <1>;
+
+bridge_out_panel: endpoint {
+  remote-endpoint = <&panel_out_bridge>;
+};
+  };
+};
+  };
+};
-- 
2.25.1

[PATCH v3 2/2] drm: bridge: Add Chipone ICN6211 MIPI-DSI to RGB bridge

[Jagan Teki]

ICN6211 is MIPI-DSI to RGB Convertor bridge from Chipone.

It has a flexible configuration of MIPI DSI signal input and
produce RGB565, RGB666, RGB888 output format.

Add bridge driver for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated the driver to inline with new drm bridge style

 MAINTAINERS  |   6 +
 drivers/gpu/drm/bridge/Kconfig   |  11 ++
 drivers/gpu/drm/bridge/Makefile  |   1 +
 drivers/gpu/drm/bridge/chipone-icn6211.c | 222 +++
 4 files changed, 240 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/chipone-icn6211.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 9d241b832aae..4f1084aae50d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5529,6 +5529,12 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml
 F: drivers/gpu/drm/panel/panel-boe-himax8279d.c
 
+DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTOR BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: drivers/gpu/drm/bridge/chipone-icn6211.c
+F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
+
 DRM DRIVER FOR FARADAY TVE200 TV ENCODER
 M: Linus Walleij 
 S: Maintained
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3..49d1565b7f25 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
  Support Cadence DPI to DSI bridge. This is an internal
  bridge and is meant to be directly embedded in a SoC.
 
+config DRM_CHIPONE_ICN6211
+   tristate "Chipone ICN6211 MIPI-DSI/RGB Convertor bridge"
+   depends on OF
+   select DRM_MIPI_DSI
+   select DRM_PANEL_BRIDGE
+   help
+ ICN6211 is MIPI-DSI/RGB Convertor bridge from chipone.
+
+ It has a flexible configuration of MIPI DSI signal input
+ and produce RGB565, RGB666, RGB888 output format.
+
 config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d..3eb84b638988 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
 obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
 obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
 obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c 
b/drivers/gpu/drm/bridge/chipone-icn6211.c
new file mode 100644
index ..3f478f21a4a5
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct chipone {
+   struct device *dev;
+   struct drm_bridge bridge;
+   struct drm_bridge *panel_bridge;
+   struct gpio_desc *reset_gpio;
+};
+
+static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct chipone, bridge);
+}
+
+static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
+{
+   return &bridge->encoder->crtc->state->adjusted_mode;
+}
+
+static void chipone_post_disable(struct drm_bridge *bridge)
+{
+   struct chipone *icn = bridge_to_chipone(bridge);
+
+   gpiod_set_value(icn->reset_gpio, 0);
+
+   msleep(50);
+}
+
+static inline int chipone_dsi_write(struct chipone *icn,  const void *seq,
+   size_t len)
+{
+   struct mipi_dsi_device *dsi = to_mipi_dsi_device(icn->dev);
+
+   return mipi_dsi_generic_write(dsi, seq, len);
+}
+
+#define CHIPONE_DSI(icn, seq...)   \
+   {   \
+   const u8 d[] = { seq }; \
+   chipone_dsi_write(icn, d, ARRAY_SIZE(d));   \
+   }
+
+static void chipone_enable(struct drm_bridge *bridge)
+{
+   struct chipone *icn = bridge_to_chipone(bridge);
+   struct drm_display_mode *mode = bridge_to_mode(bridge);
+
+   CHIPONE_DSI(icn, 0x7A, 0xC1);
+
+   /* lower 8 bits of hdisplay */
+   CHIPONE_DSI(icn, 0x20, mode->hdisplay & 0xff);
+
+   /* lower 8 bits of vdisplay */
+   CHIPONE_DSI(icn, 0x21, mode->vdisplay & 0xff);
+
+   /**
+* lsb nibble: 2nd nibble of hdisplay
+* msb nibble: 2nd nibble of vdisplay
+*/
+   CHIPONE_DSI(icn, 0x22, (((mode->hdisplay >> 8) & 0xf) |
+   (((mode->vdisplay >> 8) & 0xf) << 4)));
+
+   /* HFP */
+   CHIPONE_DSI(icn, 

[PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

[Jagan Teki]

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Driver is adding bridge configuration for Channel A, which
is a common configuration across all the bridge variants.

Add bridge driver for it.

Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- updated macro names to reflect datasheet
- add compatible for 83, 84 variants
- updated comments, kconfig
- fixed few Michael comments
Changes for v2:
- dropped the mdelays between commands as delays in init script in
  datasheet is based Aardvark I2C host adaptor.
  https://e2e.ti.com/support/interface/f/138/t/974276

 MAINTAINERS   |   6 +
 drivers/gpu/drm/bridge/Kconfig|  20 ++
 drivers/gpu/drm/bridge/Makefile   |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi8x.c | 475 ++
 4 files changed, 502 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi8x.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 4f1084aae50d..2af01632f557 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6017,6 +6017,12 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/ti/
 F: drivers/gpu/drm/omapdrm/
 
+DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
+F: drivers/gpu/drm/bridge/ti-sn65dsi8x.c
+
 DRM DRIVERS FOR V3D
 M: Eric Anholt 
 S: Supported
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 49d1565b7f25..8273a66c0eed 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -253,6 +253,26 @@ config DRM_TI_SN65DSI86
help
  Texas Instruments SN65DSI86 DSI to eDP Bridge driver
 
+config DRM_TI_SN65DSI8X
+   tristate "TI SN65DSI83/84/85 DSI to LVDS bridge"
+   depends on OF
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DSI
+   select DRM_PANEL_BRIDGE
+   select REGMAP_I2C
+   help
+ SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+ IC's from Texas Instruments.
+
+ SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+ SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+ SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+ Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+ converts the formatted video data stream to a FlatLink compatible
+ LVDS output operating at pixel clocks operating from 25 MHx to
+ 154 MHz.
+
 config DRM_TI_TPD12S015
tristate "TI TPD12S015 HDMI level shifter and ESD protection"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 3eb84b638988..e3d0dad9be30 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
 obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
+obj-$(CONFIG_DRM_TI_SN65DSI8X) += ti-sn65dsi8x.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
 obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi8x.c 
b/drivers/gpu/drm/bridge/ti-sn65dsi8x.c
new file mode 100644
index ..9b05b9295cbd
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi8x.c
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Engicam srl
+ * Copyright (C) 2021 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* registers */
+#define SN65DSI_SOFT_RESET 0x09
+#define SN65DSI_LVDS_CLK   0x0a
+#define SN65DSI_CLK_DIV0x0b
+#define SN65DSI_CLK_PLL0x0d
+#define SN65DSI_DSI_CFG0x10
+#define SN65DSI_DSI_CLK_EQ 0x11
+#define SN65DSI_DSI_CLK_RANGE  0x12
+#define SN65DSI_LVDS_MODE  0x18
+#define SN65DSI_CHA_LINE_LO0x20
+#define SN65DSI_CHA_LINE_HI0x21
+#define SN65DSI_CHA_VIRT_LO0x24
+#define SN65DSI_CHA_VIRT_HI0x25
+#define SN65DSI_CHA_SYNC_DELAY_LO  0x28
+#define SN65DSI_CHA_SYNC_DELAY_HI  0x29
+#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c
+#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d
+#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30
+#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31
+#define SN65DSI_CHA_HBACK_PORCH0x34
+#define SN65DSI_CHA_VBACK_PORCH0x36
+#define SN65DSI_CHA_HFRONT_PORCH   0x38
+#define SN65DSI_CHA_VF

[PATCH v3 1/2] dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85

[Jagan Teki]

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single
link, so dt-bindings documented according to it.

Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants 
Changes for v2:
- none

 .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++
 1 file changed, 122 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml 
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
new file mode 100644
index ..7f9f8cd6e786
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+  IC's from Texas Instruments.
+
+  SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+  SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+  SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+  Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+  converts the formatted video data stream to a FlatLink compatible
+  LVDS output operating at pixel clocks operating from 25 MHx to
+  154 MHz.
+
+properties:
+  compatible:
+enum:
+  - ti,sn65dsi83
+  - ti,sn65dsi84
+
+  reg:
+const: 0x2c
+
+  enable-gpios:
+maxItems: 1
+description: GPIO specifier for bridge enable pin (active high).
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+  DSI Input. The remote endpoint phandle should be a
+  reference to a valid mipi_dsi_host device node.
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+  Video port for LVDS output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <&bridge_in>;
+   data-lanes = <0 1>;
+   };
+   };
+   };
+};
+
+i2c6 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   bridge@2c {
+   compatible = "ti,sn65dsi84";
+   reg = <0x2c>;
+   enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   bridge_in: endpoint {
+remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   bridge_out: endpoint {
+remote-endpoint = <&panel_in_lvds>;
+   };
+   };
+   };
+   };
+};
-- 
2.25.1

Re: [PATCH v2 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

On Fri, Feb 5, 2021 at 4:50 AM Marek Vasut  wrote:
>
> On 2/4/21 11:29 PM, Laurent Pinchart wrote:
> > Hi Jagan,
> >
> > Thank you for the patch.
> >
> > On Wed, Feb 03, 2021 at 12:42:56PM +0530, Jagan Teki wrote:
> >> SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
> >> Texas Instruments.
> >>
> >> SN65DSI83, SN65DSI85 are variants of the same family of bridge
> >> controllers.
> >>
> >> Right now the bridge driver is supporting a single link, dual-link
> >> support requires to initiate I2C Channel B registers.
> >
> > MArek Vasut (on CC) has very recently posted a driver for the SN65DSI86.
> > Should the two drivers be merged together ?
>
> Since Jagan's V1 was out first, I will let Jagan pick whatever might be
> useful from the driver I posted, probably the O(1) clock rate
> calculation and some of the regmap stuff, and once there is some merged
> result, I am happy to test it on my hardware. The DSI83 is I think the
> same as DSI84, except with half of the channels.

Thanks. please wait for the v3 series, we can discuss further on top.

Jagan.

Re: [PATCH v2 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

On Wed, Feb 3, 2021 at 2:51 PM Michael Nazzareno Trimarchi
 wrote:
>
> Hi
>
> On Wed, Feb 3, 2021 at 8:13 AM Jagan Teki  wrote:
> >
> > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
> > Texas Instruments.
> >
> > SN65DSI83, SN65DSI85 are variants of the same family of bridge
> > controllers.
> >
> > Right now the bridge driver is supporting a single link, dual-link
> > support requires to initiate I2C Channel B registers.
> >
> > Tested with STM32MP1 MIPI DSI host design configuration.
> >
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - dropped the mdelays between commands as delays in init script in
> >   datasheet is based Aardvark I2C host adaptor.
> >   https://e2e.ti.com/support/interface/f/138/t/974276
> >
> >  MAINTAINERS   |   6 +
> >  drivers/gpu/drm/bridge/Kconfig|  19 ++
> >  drivers/gpu/drm/bridge/Makefile   |   1 +
> >  drivers/gpu/drm/bridge/ti-sn65dsi84.c | 457 ++
> >  4 files changed, 483 insertions(+)
> >  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 12dd1fff2a39..44750ff7640c 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -5984,6 +5984,12 @@ S:   Maintained
> >  F: Documentation/devicetree/bindings/display/ti/
> >  F: drivers/gpu/drm/omapdrm/
> >
> > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
> > +M: Jagan Teki 
> > +S: Maintained
> > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
> > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > +
> >  DRM DRIVERS FOR V3D
> >  M: Eric Anholt 
> >  S: Supported
> > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> > index e4110d6ca7b3..6494881bffb3 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -232,6 +232,25 @@ config DRM_TI_TFP410
> > help
> >   Texas Instruments TFP410 DVI/HDMI Transmitter driver
> >
> > +config DRM_TI_SN65DSI84
> > +   tristate "TI SN65DSI84 DSI to LVDS bridge"
> > +   depends on OF
> > +   select DRM_KMS_HELPER
> > +   select REGMAP_I2C
> > +   select DRM_PANEL
> > +   select DRM_MIPI_DSI
> > +   help
> > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS
> > + bridge driver.
> > +
> > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
> > + converts the formatted video data stream to a FlatLink compatible
> > + LVDS output operating at pixel clocks operating from 25 MHx to
> > + 154 MHz.
> > +
> > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with
> > + four data lanes per link.
> > +
> >  config DRM_TI_SN65DSI86
> > tristate "TI SN65DSI86 DSI to eDP bridge"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile 
> > b/drivers/gpu/drm/bridge/Makefile
> > index 86e7acc76f8d..3906052ef639 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> >  obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
> >  obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
> >  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o
> >  obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
> >  obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> >  obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
> > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c 
> > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > new file mode 100644
> > index ..27a9074db17e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > @@ -0,0 +1,457 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 Engicam srl
> > + * Copyright (C) 2021 Amarula Solutions(India)
> > + * Author: Jagan Teki 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* sn65dsi84 registers */
> > +#define SN65DSI_SOFT_RESET 0x09
> > +#define SN65DSI_LVDS_CLK   0x0a
> > +#define SN65DSI_CLK_DI

[PATCH] drm/bridge: dw-mipi-dsi: Move drm_bridge_add into probe

[Jagan Teki]

Usual I2C configured DSI bridge drivers have drm_bridge_add
in probe and mipi_dsi_attach in bridge attach functions.

With, this approach the drm pipeline is unable to find the
dsi bridge in stm drm drivers since the dw-mipi-dsi bridge is
adding drm bridge during bridge attach operations instead of
the probe.

This specific issue may not encounter for rockchip drm dsi
drivers, since rockchip drm uses component binding operations,
unlike stm drm drivers.

So, possible solutions are
1. Move drm_bridge_add into the dw-mipi-dsi probe.
2. Add mipi_dsi_attach in the bridge drivers probe.
3. Add component binding operations for stm drm drivers.

Option 1 is a relatively possible solution as most of the
mainline drm dsi with bridge drivers have a similar approach
to their dsi host vs bridge registration.

Signed-off-by: Jagan Teki 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 35 +--
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6b268f9445b3..8a535041f071 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -314,8 +314,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
 {
struct dw_mipi_dsi *dsi = host_to_dsi(host);
const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
-   struct drm_bridge *bridge;
-   struct drm_panel *panel;
int ret;
 
if (device->lanes > dsi->plat_data->max_data_lanes) {
@@ -329,22 +327,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;
 
-   ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
- &panel, &bridge);
-   if (ret)
-   return ret;
-
-   if (panel) {
-   bridge = drm_panel_bridge_add_typed(panel,
-   DRM_MODE_CONNECTOR_DSI);
-   if (IS_ERR(bridge))
-   return PTR_ERR(bridge);
-   }
-
-   dsi->panel_bridge = bridge;
-
-   drm_bridge_add(&dsi->bridge);
-
if (pdata->host_ops && pdata->host_ops->attach) {
ret = pdata->host_ops->attach(pdata->priv_data, device);
if (ret < 0)
@@ -1105,6 +1087,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
struct device *dev = &pdev->dev;
struct reset_control *apb_rst;
struct dw_mipi_dsi *dsi;
+   struct drm_bridge *bridge;
+   struct drm_panel *panel;
int ret;
 
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
@@ -1167,6 +1151,20 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
 
+   ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0,
+ &panel, &bridge);
+   if (ret)
+   return ERR_PTR(ret);
+
+   if (panel) {
+   bridge = drm_panel_bridge_add_typed(panel,
+   DRM_MODE_CONNECTOR_DSI);
+   if (IS_ERR(bridge))
+   return ERR_PTR(-ENODEV);
+   }
+
+   dsi->panel_bridge = bridge;
+
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
dsi->dsi_host.dev = dev;
ret = mipi_dsi_host_register(&dsi->dsi_host);
@@ -1181,6 +1179,7 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 #ifdef CONFIG_OF
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
+   drm_bridge_add(&dsi->bridge);
 
return dsi;
 }
-- 
2.25.1

[PATCH v2 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
Texas Instruments.

SN65DSI83, SN65DSI85 are variants of the same family of bridge
controllers.

Right now the bridge driver is supporting a single link, dual-link
support requires to initiate I2C Channel B registers.

Tested with STM32MP1 MIPI DSI host design configuration.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- dropped the mdelays between commands as delays in init script in
  datasheet is based Aardvark I2C host adaptor.
  https://e2e.ti.com/support/interface/f/138/t/974276

 MAINTAINERS   |   6 +
 drivers/gpu/drm/bridge/Kconfig|  19 ++
 drivers/gpu/drm/bridge/Makefile   |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi84.c | 457 ++
 4 files changed, 483 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 12dd1fff2a39..44750ff7640c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5984,6 +5984,12 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/ti/
 F: drivers/gpu/drm/omapdrm/
 
+DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
+F: drivers/gpu/drm/bridge/ti-sn65dsi84.c
+
 DRM DRIVERS FOR V3D
 M: Eric Anholt 
 S: Supported
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3..6494881bffb3 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -232,6 +232,25 @@ config DRM_TI_TFP410
help
  Texas Instruments TFP410 DVI/HDMI Transmitter driver
 
+config DRM_TI_SN65DSI84
+   tristate "TI SN65DSI84 DSI to LVDS bridge"
+   depends on OF
+   select DRM_KMS_HELPER
+   select REGMAP_I2C
+   select DRM_PANEL
+   select DRM_MIPI_DSI
+   help
+ Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS
+ bridge driver.
+
+ Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+ converts the formatted video data stream to a FlatLink compatible
+ LVDS output operating at pixel clocks operating from 25 MHx to
+ 154 MHz.
+
+ SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with
+ four data lanes per link.
+
 config DRM_TI_SN65DSI86
tristate "TI SN65DSI86 DSI to eDP bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d..3906052ef639 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
+obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o
 obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c 
b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
new file mode 100644
index ..27a9074db17e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Engicam srl
+ * Copyright (C) 2021 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* sn65dsi84 registers */
+#define SN65DSI_SOFT_RESET 0x09
+#define SN65DSI_LVDS_CLK   0x0a
+#define SN65DSI_CLK_DIV0x0b
+#define SN65DSI_CLK_PLL0x0d
+#define SN65DSI_DSI_CFG0x10
+#define SN65DSI_DSI_CLK_EQ 0x11
+#define SN65DSI_DSI_CLK_RANGE  0x12
+#define SN65DSI_LVDS_MODE  0x18
+#define SN65DSI_CHA_LINE_LO0x20
+#define SN65DSI_CHA_LINE_HI0x21
+#define SN65DSI_CHA_VIRT_LO0x24
+#define SN65DSI_CHA_VIRT_HI0x25
+#define SN65DSI_CHA_SYNC_DELAY_LO  0x28
+#define SN65DSI_CHA_SYNC_DELAY_HI  0x29
+#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c
+#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d
+#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30
+#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31
+#define SN65DSI_CHA_HBACK_PORCH0x34
+#define SN65DSI_CHA_VBACK_PORCH0x36
+#define SN65DSI_CHA_HFRONT_PORCH   0x38
+#define SN65DSI_CHA_VFRONT_PORCH   0x3a
+#define SN65DSI_CHA_ERR0xe5
+
+/* sn65dsi register bits */
+#define SN65DSI_RESET_EN   BIT(0)
+#define SN65DSI_PLL_EN BIT(0)
+#define SN65DSI_LVDS_CLK_MASK  GENMASK(3, 1)
+#define SN65DSI_LVDS_CLK_SHIFT 1
+#define SN65DSI_LVDS_CLK_SRC_DSI   BIT(0)
+#define SN65DSI_CLK_DIV_MASK   GE

[PATCH v2 1/2] dt-bindings: display: bridge: Add documentation for SN65DSI84

[Jagan Teki]

SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
Texas Instruments.

SN65DSI83, SN65DSI85 are variants of the same family of bridge
controllers.

Right now the bridge driver is supporting a single link, dual-link
support requires to initiate I2C Channel B registers, so dt-bindings
documented with single link LVDS.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 .../bindings/display/bridge/ti,sn65dsi84.yaml | 127 ++
 1 file changed, 127 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml 
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
new file mode 100644
index ..891382a76c1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi84.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI84 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  The SN65DSI84 DSI to FlatLink bridge features a single channel MIPI D-PHY 
receiver
+  front-end configuration with 4 lanes per channel operating at 1 Gbps per 
lanes.
+  The bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and 
converts
+  the formatted video data stream to a FlatLink compatible LVDS output 
operating
+  at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-Link LVDS,
+  Single-Link LVDS interface with four data lanes per link.
+
+  https://www.ti.com/product/SN65DSI84
+
+properties:
+  compatible:
+const: ti,sn65dsi84
+
+  reg:
+maxItems: 1
+description: i2c address of the bridge, 0x2c
+
+  enable-gpios:
+maxItems: 1
+description: GPIO specifier for bridge enable pin (active high).
+
+  ports:
+type: object
+description:
+  A node containing input and output port nodes with endpoint definitions
+  as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+properties:
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  port@0:
+type: object
+description: |
+  DSI Input. The remote endpoint phandle should be a
+  reference to a valid mipi_dsi_host device node.
+
+  port@1:
+type: object
+description: |
+  Video port for LVDS output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <&bridge_in>;
+   data-lanes = <0 1>;
+   };
+   };
+   };
+};
+
+i2c6 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   bridge@2c {
+   compatible = "ti,sn65dsi84";
+   reg = <0x2c>;
+   enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   bridge_in: endpoint {
+remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   bridge_out: endpoint {
+remote-endpoint = <&panel_in_lvds>;
+   };
+   };
+   };
+   };
+};
-- 
2.25.1

Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

On Wed, Jan 20, 2021 at 4:55 PM Michael Nazzareno Trimarchi
 wrote:
>
> Hi Jagan
>
> On Wed, Jan 20, 2021 at 12:22 PM Jagan Teki  
> wrote:
> >
> > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
> > Texas Instruments.
> >
> > SN65DSI83, SN65DSI85 are variants of the same family of bridge
> > controllers.
> >
> > Right now the bridge driver is supporting a single link, dual-link
> > support requires to initiate I2C Channel B registers.
> >
> > Tested with STM32MP1 MIPI DSI host design configuration.
> >
> > Signed-off-by: Matteo Lisi 
> > Signed-off-by: Jagan Teki 
> > ---
> >  MAINTAINERS   |   6 +
> >  drivers/gpu/drm/bridge/Kconfig|  19 +
> >  drivers/gpu/drm/bridge/Makefile   |   1 +
> >  drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++
> >  4 files changed, 514 insertions(+)
> >  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 12dd1fff2a39..44750ff7640c 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -5984,6 +5984,12 @@ S:   Maintained
> >  F: Documentation/devicetree/bindings/display/ti/
> >  F: drivers/gpu/drm/omapdrm/
> >
> > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
> > +M: Jagan Teki 
> > +S: Maintained
> > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
> > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > +
> >  DRM DRIVERS FOR V3D
> >  M: Eric Anholt 
> >  S: Supported
> > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> > index e4110d6ca7b3..6494881bffb3 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -232,6 +232,25 @@ config DRM_TI_TFP410
> > help
> >   Texas Instruments TFP410 DVI/HDMI Transmitter driver
> >
> > +config DRM_TI_SN65DSI84
> > +   tristate "TI SN65DSI84 DSI to LVDS bridge"
> > +   depends on OF
> > +   select DRM_KMS_HELPER
> > +   select REGMAP_I2C
> > +   select DRM_PANEL
> > +   select DRM_MIPI_DSI
> > +   help
> > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS
> > + bridge driver.
> > +
> > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
> > + converts the formatted video data stream to a FlatLink compatible
> > + LVDS output operating at pixel clocks operating from 25 MHx to
> > + 154 MHz.
> > +
> > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with
> > + four data lanes per link.
> > +
> >  config DRM_TI_SN65DSI86
> > tristate "TI SN65DSI86 DSI to eDP bridge"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile 
> > b/drivers/gpu/drm/bridge/Makefile
> > index 86e7acc76f8d..3906052ef639 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> >  obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
> >  obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
> >  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o
> >  obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
> >  obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> >  obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
> > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c 
> > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > new file mode 100644
> > index ..3ed1f9a7d898
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
> > @@ -0,0 +1,488 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 Engicam srl
> > + * Copyright (C) 2021 Amarula Solutions(India)
> > + * Author: Jagan Teki 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* sn65dsi84 registers */
> > +#define SN65DSI_SOFT_RESET 0x09
> > +#define SN65DSI_LVDS_CLK   0x0a
> > +#define SN65DSI_CLK_DIV0x0b
> > +#define SN65DSI_CLK_PLL0x0d
> > +#define SN65DSI_DSI_CFG0x10
> > +#defin

[PATCH 1/2] dt-bindings: display: bridge: Add documentation for SN65DSI84

[Jagan Teki]

SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
Texas Instruments.

SN65DSI83, SN65DSI85 are variants of the same family of bridge
controllers.

Right now the bridge driver is supporting a single link, dual-link
support requires to initiate I2C Channel B registers, so dt-bindings
documented with single link LVDS.

Signed-off-by: Jagan Teki 
---
 .../bindings/display/bridge/ti,sn65dsi84.yaml | 127 ++
 1 file changed, 127 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml 
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
new file mode 100644
index ..891382a76c1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi84.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI84 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+  - Jagan Teki 
+
+description: |
+  The SN65DSI84 DSI to FlatLink bridge features a single channel MIPI D-PHY 
receiver
+  front-end configuration with 4 lanes per channel operating at 1 Gbps per 
lanes.
+  The bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and 
converts
+  the formatted video data stream to a FlatLink compatible LVDS output 
operating
+  at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-Link LVDS,
+  Single-Link LVDS interface with four data lanes per link.
+
+  https://www.ti.com/product/SN65DSI84
+
+properties:
+  compatible:
+const: ti,sn65dsi84
+
+  reg:
+maxItems: 1
+description: i2c address of the bridge, 0x2c
+
+  enable-gpios:
+maxItems: 1
+description: GPIO specifier for bridge enable pin (active high).
+
+  ports:
+type: object
+description:
+  A node containing input and output port nodes with endpoint definitions
+  as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+properties:
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  port@0:
+type: object
+description: |
+  DSI Input. The remote endpoint phandle should be a
+  reference to a valid mipi_dsi_host device node.
+
+  port@1:
+type: object
+description: |
+  Video port for LVDS output (panel or connector).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <&bridge_in>;
+   data-lanes = <0 1>;
+   };
+   };
+   };
+};
+
+i2c6 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   bridge@2c {
+   compatible = "ti,sn65dsi84";
+   reg = <0x2c>;
+   enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   bridge_in: endpoint {
+remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   bridge_out: endpoint {
+remote-endpoint = <&panel_in_lvds>;
+   };
+   };
+   };
+   };
+};
-- 
2.25.1

[PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge

[Jagan Teki]

SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
Texas Instruments.

SN65DSI83, SN65DSI85 are variants of the same family of bridge
controllers.

Right now the bridge driver is supporting a single link, dual-link
support requires to initiate I2C Channel B registers.

Tested with STM32MP1 MIPI DSI host design configuration.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
 MAINTAINERS   |   6 +
 drivers/gpu/drm/bridge/Kconfig|  19 +
 drivers/gpu/drm/bridge/Makefile   |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++
 4 files changed, 514 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 12dd1fff2a39..44750ff7640c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5984,6 +5984,12 @@ S:   Maintained
 F: Documentation/devicetree/bindings/display/ti/
 F: drivers/gpu/drm/omapdrm/
 
+DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
+M: Jagan Teki 
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml
+F: drivers/gpu/drm/bridge/ti-sn65dsi84.c
+
 DRM DRIVERS FOR V3D
 M: Eric Anholt 
 S: Supported
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3..6494881bffb3 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -232,6 +232,25 @@ config DRM_TI_TFP410
help
  Texas Instruments TFP410 DVI/HDMI Transmitter driver
 
+config DRM_TI_SN65DSI84
+   tristate "TI SN65DSI84 DSI to LVDS bridge"
+   depends on OF
+   select DRM_KMS_HELPER
+   select REGMAP_I2C
+   select DRM_PANEL
+   select DRM_MIPI_DSI
+   help
+ Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS
+ bridge driver.
+
+ Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+ converts the formatted video data stream to a FlatLink compatible
+ LVDS output operating at pixel clocks operating from 25 MHx to
+ 154 MHz.
+
+ SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with
+ four data lanes per link.
+
 config DRM_TI_SN65DSI86
tristate "TI SN65DSI86 DSI to eDP bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d..3906052ef639 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
+obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o
 obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c 
b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
new file mode 100644
index ..3ed1f9a7d898
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Engicam srl
+ * Copyright (C) 2021 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* sn65dsi84 registers */
+#define SN65DSI_SOFT_RESET 0x09
+#define SN65DSI_LVDS_CLK   0x0a
+#define SN65DSI_CLK_DIV0x0b
+#define SN65DSI_CLK_PLL0x0d
+#define SN65DSI_DSI_CFG0x10
+#define SN65DSI_DSI_CLK_EQ 0x11
+#define SN65DSI_DSI_CLK_RANGE  0x12
+#define SN65DSI_LVDS_MODE  0x18
+#define SN65DSI_CHA_LINE_LO0x20
+#define SN65DSI_CHA_LINE_HI0x21
+#define SN65DSI_CHA_VIRT_LO0x24
+#define SN65DSI_CHA_VIRT_HI0x25
+#define SN65DSI_CHA_SYNC_DELAY_LO  0x28
+#define SN65DSI_CHA_SYNC_DELAY_HI  0x29
+#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c
+#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d
+#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30
+#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31
+#define SN65DSI_CHA_HBACK_PORCH0x34
+#define SN65DSI_CHA_VBACK_PORCH0x36
+#define SN65DSI_CHA_HFRONT_PORCH   0x38
+#define SN65DSI_CHA_VFRONT_PORCH   0x3a
+#define SN65DSI_CHA_ERR0xe5
+
+/* sn65dsi register bits */
+#define SN65DSI_RESET_EN   BIT(0)
+#define SN65DSI_PLL_EN BIT(0)
+#define SN65DSI_LVDS_CLK_MASK  GENMASK(3, 1)
+#define SN65DSI_LVDS_CLK_SHIFT 1
+#define SN65DSI_LVDS_CLK_SRC_DSI   BIT(0)
+#define SN65DSI_CLK_DIV_MASK   GENMASK(7, 3)
+#define SN65DSI_CLK_DIV_SHIFT  3
+#define SN65DSI_DSI_LANE_MASK  GENMASK(4, 3)
+#define SN65DSI_DSI_LANE_SHIFT 3
+#define S

Re: [PATCH] drm/panel: feiyang-fy07024di26a30d: cleanup if panel attaching failed

[Jagan Teki]

On Thu, Jan 7, 2021 at 10:16 AM Icenowy Zheng  wrote:
>
>
>
> 于 2021年1月6日 GMT+08:00 下午5:47:20, Jagan Teki  写到:
> >On Sat, Nov 28, 2020 at 6:23 PM Icenowy Zheng  wrote:
> >>
> >> Attaching the panel can fail, so cleanup work is necessary, otherwise
> >> a pointer to freed struct drm_panel* will remain in drm_panel code.
> >>
> >> Do the cleanup if panel attaching failed.
> >>
> >> Fixes: 69dc678abc2b ("drm/panel: Add Feiyang FY07024DI26A30-D
> >MIPI-DSI LCD panel")
> >
> >The fact that this has failed to probe due to recent changes in
> >sun6i_mipi_dsi.c I don't know how to put that into the commit message.
>
> It's not related, we shouldn't assume this panel driver will always
> be used with sunxi SoCs.

Well, I'm aware of it. What I'm trying to say is this panel has
referenced with one of exiting panel in a tree and that indeed return
mipi_dsi_attach and it verified with DSI host at that time.

>
> It's a panel driver bug that cannot deal with -EPROBE_DEFER well.

Yes, ie reason I have added Reviewed-by tag above.

Jagan.

Re: [PATCH] drm/panel: feiyang-fy07024di26a30d: cleanup if panel attaching failed

[Jagan Teki]

On Sat, Nov 28, 2020 at 6:23 PM Icenowy Zheng  wrote:
>
> Attaching the panel can fail, so cleanup work is necessary, otherwise
> a pointer to freed struct drm_panel* will remain in drm_panel code.
>
> Do the cleanup if panel attaching failed.
>
> Fixes: 69dc678abc2b ("drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD 
> panel")

The fact that this has failed to probe due to recent changes in
sun6i_mipi_dsi.c I don't know how to put that into the commit message.
> Signed-off-by: Icenowy Zheng 
> ---

Reviewed-by: Jagan Teki 

Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Mon, Dec 28, 2020 at 2:04 PM Krzysztof Kozlowski  wrote:
>
> On Mon, 28 Dec 2020 at 09:21, Jagan Teki  wrote:
> > > > #include "imx8mm.dtsi"
> > > > #include "imx8mm-beacon-som.dtsi"
> > > > #include "imx8mm-beacon-baseboard.dtsi"
> > > >
> > > > (SoC dtsi, SoM dtsi, Carrier board dtsi)
> > > >
> > > > > design which makes any sense. We do not create empty DTS files which
> > > > > only include one more DTSI. The contents of
> > > > > imx8mm-engicam-ctouch2.dtsi should be directly in
> > > > > imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 -
> > > > > you overcomplicate simple stuff. It really looks like you ignored the
> > > > > comments from v1 in multiple places.
> > > >
> > > > As explained above, the design is pretty much the same as the existing 
> > > > SoM's.
> > > >
> > > > imx8mm-engicam-ctouch2.dtsi is not just a dtsi file where nodes are
> > > > enabled. It has nodes enabled for Carrier board, so keeping nodes
> > > > separately will
> > >
> > > The files represent real devices or their components. So you have a
> > > SOM - a DTSI file. You have a carrier board - a DTS file. That's
> > > simple design which is mostly followed, unless something over
> > > complicated passes the review.
> > >
> > > > 1. More verbose for which IP's are available in the carrier board
> > >
> > > No difference when carrier DTSI is the DTS. Exactly the same.
> > >
> > > > 2. Easy to extend if someone can create another SoM with a similar 
> > > > Carrier.
> > >
> > > Not really, if they include carrier DTSI they need to override a lot.
> > > So usually (including practice - I did it) they *copy* the carrier to
> > > create their own design.
> >
> > But what if the new board has slite change to use exiting carrier like
> > what ctouch2 10" OF. Can we add ctouch2 dtsi as a separate file for
> > this case?
>
> If you submit another DTS using the imx8mm-engicam-ctouch2.dtsi - with
> its own differences of course (not copying other DTS...) - then having
> a DTSI makes sense. In current form, still NAK for all the reasons I
> explained more than once.

Okay, thanks for the review.

Jagan.

Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Thu, Dec 24, 2020 at 3:51 PM Krzysztof Kozlowski  wrote:
>
> On Thu, 24 Dec 2020 at 11:08, Jagan Teki  wrote:
> >
> > On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski  wrote:
> > >
> > > On Wed, 23 Dec 2020 at 13:07, Jagan Teki  
> > > wrote:
> > > >
> > > > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski  
> > > > wrote:
> > > > >
> > > > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote:
> > > > > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> > > > > > board.
> > > > > >
> > > > > > Genaral features:
> > > > > > - Ethernet 10/100
> > > > > > - Wifi/BT
> > > > > > - USB Type A/OTG
> > > > > > - Audio Out
> > > > > > - CAN
> > > > > > - LVDS panel connector
> > > > > >
> > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from 
> > > > > > Engicam.
> > > > > >
> > > > > > i.Core MX8M Mini needs to mount on top of this Carrier board for
> > > > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> > > > > >
> > > > > > Add support for it.
> > > > > >
> > > > > > Signed-off-by: Matteo Lisi 
> > > > > > Signed-off-by: Jagan Teki 
> > > > > > ---
> > > > > > Changes for v3:
> > > > > > - don't maintain common nodes and include it, if no feature diff
> > > > > > Changes for v2:
> > > > > > - enabled fec1 node
> > > > > > - updated commit message
> > > > > > - dropped engicam from filename since it aligned with imx6 engicam
> > > > > >   dts files naming conventions.
> > > > > > - add i2c nodes
> > > > > > - fixed v1 comments
> > > > > >
> > > > > >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> > > > > >  .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 
> > > > > > +++
> > > > > >  .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  | 21 +
> > > > > >  3 files changed, 104 insertions(+)
> > > > > >  create mode 100644 
> > > > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
> > > > >
> > > > > You split some common part to ctouch2.dtsi so it can be reused in
> > > > > multiple places. I saw so far only one usage, where are the others?
> > > >
> > > > To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier
> > > > board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display),
> > > > since DSI is not yet mainlined, I didn't add this yet.
> > >
> > > If I understand correctly: it is a DTSI which is included only by one
> > > DTS... and DTS does not have any other nodes. This as well is not the
> >
> > This is not mandatory as per my understanding, including exiting DTS
> > topologies in Mainline.
> >
> > There are several places where more than one dtsi has been included,
> > Simple example of imx8mm tree is
>
> It's not the problem of including more than one DTSI. It's the problem
> of creating fake DTS or DTSI files whose purpose is only to include
> others. Keep it simple. Don't create unnecessary files. "Entities
> should not be multiplied without necessity."
>
> >
> > arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts
>
> Which was wrong as well. Don't create unnecessary files.
>
> >
> > /dts-v1/;
> >
> > #include "imx8mm.dtsi"
> > #include "imx8mm-beacon-som.dtsi"
> > #include "imx8mm-beacon-baseboard.dtsi"
> >
> > (SoC dtsi, SoM dtsi, Carrier board dtsi)
> >
> > > design which makes any sense. We do not create empty DTS files which
> > > only include one more DTSI. The contents of
> > > imx8mm-engicam-ctouch2.dtsi should be directly in
> > > imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 -
> > > you overcomplicate simple stuff. It really looks like you ignored the
> > > comments from v1 in multiple places.
> >
> > As explained above, the design is pretty much the same as the existing 
> > SoM's.
> >
> > imx8mm-engicam-ctouch2.dtsi is not just a dtsi fi

Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski  wrote:
>
> On Wed, 23 Dec 2020 at 13:07, Jagan Teki  wrote:
> >
> > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski  wrote:
> > >
> > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote:
> > > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> > > > board.
> > > >
> > > > Genaral features:
> > > > - Ethernet 10/100
> > > > - Wifi/BT
> > > > - USB Type A/OTG
> > > > - Audio Out
> > > > - CAN
> > > > - LVDS panel connector
> > > >
> > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> > > >
> > > > i.Core MX8M Mini needs to mount on top of this Carrier board for
> > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> > > >
> > > > Add support for it.
> > > >
> > > > Signed-off-by: Matteo Lisi 
> > > > Signed-off-by: Jagan Teki 
> > > > ---
> > > > Changes for v3:
> > > > - don't maintain common nodes and include it, if no feature diff
> > > > Changes for v2:
> > > > - enabled fec1 node
> > > > - updated commit message
> > > > - dropped engicam from filename since it aligned with imx6 engicam
> > > >   dts files naming conventions.
> > > > - add i2c nodes
> > > > - fixed v1 comments
> > > >
> > > >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> > > >  .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++
> > > >  .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  | 21 +
> > > >  3 files changed, 104 insertions(+)
> > > >  create mode 100644 
> > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
> > >
> > > You split some common part to ctouch2.dtsi so it can be reused in
> > > multiple places. I saw so far only one usage, where are the others?
> >
> > To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier
> > board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display),
> > since DSI is not yet mainlined, I didn't add this yet.
>
> If I understand correctly: it is a DTSI which is included only by one
> DTS... and DTS does not have any other nodes. This as well is not the

This is not mandatory as per my understanding, including exiting DTS
topologies in Mainline.

There are several places where more than one dtsi has been included,
Simple example of imx8mm tree is

arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts

/dts-v1/;

#include "imx8mm.dtsi"
#include "imx8mm-beacon-som.dtsi"
#include "imx8mm-beacon-baseboard.dtsi"

(SoC dtsi, SoM dtsi, Carrier board dtsi)

> design which makes any sense. We do not create empty DTS files which
> only include one more DTSI. The contents of
> imx8mm-engicam-ctouch2.dtsi should be directly in
> imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 -
> you overcomplicate simple stuff. It really looks like you ignored the
> comments from v1 in multiple places.

As explained above, the design is pretty much the same as the existing SoM's.

imx8mm-engicam-ctouch2.dtsi is not just a dtsi file where nodes are
enabled. It has nodes enabled for Carrier board, so keeping nodes
separately will

1. More verbose for which IP's are available in the carrier board
2. Easy to extend if someone can create another SoM with a similar Carrier.

Ie is the whole idea to keep carrier board dtsi and includes them in dts.

As I suggest, if you can look into px30 you can understand more easily.

Jagan.

[PATCH 1/5] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index e7525a3395e5..56b7e0b800b3 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -64,6 +64,13 @@ properties:
   - const: st,stm32mp157c-ev1
   - const: st,stm32mp157c-ed1
   - const: st,stm32mp157
+
+  - description: Engicam MicroGEA STM32MP1 SoM based Boards
+items:
+  - const: engicam,microgea-stm32mp1-microdev2.0
+  - const: engicam,microgea-stm32mp1
+  - const: st,stm32mp157
+
   - description: Octavo OSD32MP15x System-in-Package based boards
 items:
   - enum:
-- 
2.25.1

[PATCH 4/5] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

7" OF is a capacitive touch 7" Open Frame panel solutions.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml 
b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 56b7e0b800b3..255d3ba50c63 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -67,7 +67,9 @@ properties:
 
   - description: Engicam MicroGEA STM32MP1 SoM based Boards
 items:
-  - const: engicam,microgea-stm32mp1-microdev2.0
+  - enum:
+  - engicam,microgea-stm32mp1-microdev2.0
+  - engicam,microgea-stm32mp1-microdev2.0-of7
   - const: engicam,microgea-stm32mp1
   - const: st,stm32mp157
 
-- 
2.25.1

[PATCH 5/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
 arch/arm/boot/dts/Makefile|   1 +
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 120 ++
 2 files changed, 121 insertions(+)
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b4a9cd071f99..1332622a3f9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1072,6 +1072,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git 
a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
new file mode 100644
index ..b96e683072e2
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-engicam-microdev2.0.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
+   default-on;
+   };
+
+   lcd_3v3: regulator-lcd-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "lcd_3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   power-supply = <&panel_pwr>;
+   };
+
+   panel_pwr: regulator-panel-pwr {
+   compatible = "regulator-fixed";
+   regulator-name = "panel_pwr";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
+   regulator-always-on;
+   };
+
+   panel {
+   compatible = "auo,b101aw03";
+   backlight = <&backlight>;
+   enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
+   power-supply = <&lcd_3v3>;
+
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <<dc_ep0_out>;
+   };
+   };
+   };
+};
+
+&i2c2 {
+   i2c-scl-falling-time-ns = <20>;
+   i2c-scl-rising-time-ns = <185>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&i2c2_pins_a>;
+   pinctrl-1 = <&i2c2_sleep_pins_a>;
+   status = "okay";
+};
+
+<dc {
+   pinctrl-names = "default";
+   pinctrl-0 = <<dc_pins>;
+   status = "okay";
+
+   port {
+   ltdc_ep0_out: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&panel_in>;
+   };
+   };
+};
+
+&pinctrl {
+   ltdc_pins: ltdc {
+   pins {
+   pinmux = , /* LTDC_B2 */
+, /* LTDC_R6 */
+, /* LTDC_R5 */
+, /* LTDC_B3 */
+,  /* LTDC_B0 */
+,  /* LTDC_G0 */
+,  /* LTDC_G1 */
+  

[PATCH 2/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM

[Jagan Teki]

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
 1 file changed, 147 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
new file mode 100644
index ..97d569107bfe
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   reg = <0xc000 0x1000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vin: regulator-vin {
+   compatible = "regulator-fixed";
+   regulator-name = "vin";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vddq_ddr: regulator-vddq-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vddq_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+};
+
+&dts {
+   status = "okay";
+};
+
+&fmc {
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&fmc_pins_a>;
+   pinctrl-1 = <&fmc_sleep_pins_a>;
+   status = "okay";
+
+   nand-controller@4,0 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   nand-on-flash-bbt;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+   };
+};
+
+&ipcc {
+   status = "okay";
+};
+
+&iwdg2{
+   timeout-sec = <32>;
+   status = "okay";
+};
+
+&m4_rproc{
+   memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vr

[PATCH 3/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

[Jagan Teki]

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Francesco Utel 
Signed-off-by: Mirko Ardinghi 
Signed-off-by: Jagan Teki 
---
 arch/arm/boot/dts/Makefile|  1 +
 .../dts/stm32mp157a-engicam-microdev2.0.dtsi  | 44 +++
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 21 +
 3 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-engicam-microdev2.0.dtsi
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9f9f3e49132a..b4a9cd071f99 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
stm32mp157a-iot-box.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-engicam-microdev2.0.dtsi 
b/arch/arm/boot/dts/stm32mp157a-engicam-microdev2.0.dtsi
new file mode 100644
index ..a5c04eb80a99
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-engicam-microdev2.0.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+};
+
+&sdmmc1{
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&vdd>;
+   status = "okay";
+};
+
+&uart4{
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
+
+/* J31: RS323 */
+&uart8 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart8_pins_a>;
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts 
b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
new file mode 100644
index ..51707bfb649d
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-engicam-microdev2.0.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
-- 
2.25.1

[PATCH 0/5] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1

[Jagan Teki]

This is the initial series to support Engicam MicroGEA STM32MP1
SoM and it's associated carrier board dts(i) support.

MicroGEA STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

MicroGEA STM32MP1 needs to mount on top of Engicam carrier boards for
creating complete platform boards.

Possible carrier boards are,
- MicroDev 2.0
- MicroDev 7" Open Frame.

Any inputs?
Jagan.

Jagan Teki (5):
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board
  dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

 .../devicetree/bindings/arm/stm32/stm32.yaml  |   9 ++
 arch/arm/boot/dts/Makefile|   2 +
 .../dts/stm32mp157a-engicam-microdev2.0.dtsi  |  44 ++
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 120 ++
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  21 +++
 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 147 ++
 6 files changed, 343 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp157a-engicam-microdev2.0.dtsi
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
 create mode 100644 
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi

-- 
2.25.1

Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski  wrote:
>
> On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote:
> > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> > board.
> >
> > Genaral features:
> > - Ethernet 10/100
> > - Wifi/BT
> > - USB Type A/OTG
> > - Audio Out
> > - CAN
> > - LVDS panel connector
> >
> > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> >
> > i.Core MX8M Mini needs to mount on top of this Carrier board for
> > creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> >
> > Add support for it.
> >
> > Signed-off-by: Matteo Lisi 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v3:
> > - don't maintain common nodes and include it, if no feature diff
> > Changes for v2:
> > - enabled fec1 node
> > - updated commit message
> > - dropped engicam from filename since it aligned with imx6 engicam
> >   dts files naming conventions.
> > - add i2c nodes
> > - fixed v1 comments
> >
> >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> >  .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++
> >  .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  | 21 +
> >  3 files changed, 104 insertions(+)
> >  create mode 100644 
> > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
>
> You split some common part to ctouch2.dtsi so it can be reused in
> multiple places. I saw so far only one usage, where are the others?

To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier
board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display),
since DSI is not yet mainlined, I didn't add this yet.

Jagan.

[PATCH] ARM: dts: stm32: Add STM32MP1 I2C6 SDA/SCL pinmux

[Jagan Teki]

Add SDA/SCL pinmux lines for I2C6 on STM32MP1.

This support adds both in default and sleep states.

Signed-off-by: Jagan Teki 
---
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 20a59e8f7a33..2036c1d0d798 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -2018,6 +2018,23 @@ pins {
};
};
 
+   i2c6_pins_a: i2c6-0 {
+   pins {
+   pinmux = , /* I2C6_SCL */
+; /* I2C6_SDA */
+   bias-disable;
+   drive-open-drain;
+   slew-rate = <0>;
+   };
+   };
+
+   i2c6_sleep_pins_a: i2c6-sleep-0 {
+   pins {
+   pinmux = , /* I2C6_SCL */
+; /* I2C6_SDA */
+   };
+   };
+
spi1_pins_a: spi1-0 {
pins1 {
pinmux = , /* SPI1_SCK */
-- 
2.25.1

[PATCH v3 1/6] arm64: defconfig: Enable REGULATOR_PF8X00

[Jagan Teki]

Enable PF8X00 regulator driver by default as it used in
some of i.MX8MM hardware platforms.

Cc: Catalin Marinas 
Cc: Will Deacon 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- collect Krzysztof r-b
Changes for v2:
- updated commit message

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fae83673c3c3..e952c76ee970 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -594,6 +594,7 @@ CONFIG_REGULATOR_HI655X=y
 CONFIG_REGULATOR_MAX77620=y
 CONFIG_REGULATOR_MAX8973=y
 CONFIG_REGULATOR_PCA9450=y
+CONFIG_REGULATOR_PF8X00=y
 CONFIG_REGULATOR_PFUZE100=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_QCOM_RPMH=y
-- 
2.25.1

[PATCH v3 6/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once
Mainline Linux supported.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- don't maintain common nodes and include it, if no feature diff
Changes for v2:
- updated commit message
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.

 arch/arm64/boot/dts/freescale/Makefile|  1 +
 .../freescale/imx8mm-engicam-edimm2.2.dtsi| 82 +++
 .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 21 +
 3 files changed, 104 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
 create mode 100644 
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 8d49a2c74604..43783076f856 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
new file mode 100644
index ..f7870efd9dab
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+&fec1 {
+   status = "okay";
+};
+
+&i2c2 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2>;
+   status = "okay";
+};
+
+&i2c4 {
+   clock-frequency = <10>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4>;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl_i2c2: i2c2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL  0x41c3
+   MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_i2c4: i2c4grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL  0x41c3
+   MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_uart2: uart2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+   MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+   >;
+   };
+
+   pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+   fsl,pins = <
+   MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6   0x41
+   >;
+   };
+
+   pinctrl_usdhc1: usdhc1grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+   MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+   MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+   MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+   MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+   MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+   >;
+   };
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+   cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+   max-frequency = <5000>;
+   bus-width = <4>;
+   no-1-8-v;
+   pm-ignore-notify;
+   keep-power-in-suspend;
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
new file mode 100644
index ..672aee1800c4
--- /dev/null
+++ b/

[PATCH v3 5/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation
Board from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- fix dt-bindings
Changes for v2:
- update commit message

 Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
b/Documentation/devicetree/bindings/arm/fsl.yaml
index f1de68341873..2dab4b5bf99a 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -675,7 +675,9 @@ properties:
 
   - description: Engicam i.Core MX8M Mini SoM based boards
 items:
-  - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - enum:
+  - engicam,icore-mx8mm-ctouch2# i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - engicam,icore-mx8mm-edimm2.2   # i.MX8MM Engicam i.Core 
MX8M Mini EDIMM2.2 Starter Kit
   - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core 
MX8M Mini SoM
   - const: fsl,imx8mm
 
-- 
2.25.1

[PATCH v3 2/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Add bindings for it.

Signed-off-by: Jagan Teki 
---
Changes for v3:
- add proper bindings 
Changes for v2:
- updated commit message

 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
b/Documentation/devicetree/bindings/arm/fsl.yaml
index 67980dcef66d..f1de68341873 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -673,6 +673,12 @@ properties:
   - variscite,var-som-mx8mm   # i.MX8MM Variscite VAR-SOM-MX8MM 
module
   - const: fsl,imx8mm
 
+  - description: Engicam i.Core MX8M Mini SoM based boards
+items:
+  - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core 
MX8M Mini C.TOUCH 2.0
+  - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core 
MX8M Mini SoM
+  - const: fsl,imx8mm
+
   - description: Kontron BL i.MX8MM (N801X S) Board
 items:
   - const: kontron,imx8mm-n801x-s
-- 
2.25.1

[PATCH v3 0/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini

[Jagan Teki]

This is the initial series to support Engicam i.Core MX8M Mini SOM
and it's associated carrier board dts(i) support.

i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam.

i.Core MX8M Mini needs to mount on top of Engicam baseboards for
creating complete platform boards.

Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0

Changes for v3:
- don't maintain common nodes and include it, if no feature diff
- keep min/max regulator hoping
- collect Krzysztof r-b
- fix dt-bindings

Any inputs?
Jagan.

Jagan Teki (6):
  arm64: defconfig: Enable REGULATOR_PF8X00
  dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
  dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
  arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

 .../devicetree/bindings/arm/fsl.yaml  |   8 +
 arch/arm64/boot/dts/freescale/Makefile|   2 +
 .../dts/freescale/imx8mm-engicam-ctouch2.dtsi |  82 +++
 .../freescale/imx8mm-engicam-edimm2.2.dtsi|  82 +++
 .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  |  21 ++
 .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts |  21 ++
 .../dts/freescale/imx8mm-icore-mx8mm.dtsi | 232 ++
 arch/arm64/configs/defconfig  |   1 +
 8 files changed, 449 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
 create mode 100644 
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi

-- 
2.25.1

[PATCH v3 3/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM

[Jagan Teki]

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.

General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features

i.Core MX8M Mini needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- keep regulator min/max hoping
Changes for v2:
- updated commit message
- add cpu nodes
- add fec1 node
- fixed pmic tree comments
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.

 .../dts/freescale/imx8mm-icore-mx8mm.dtsi | 232 ++
 1 file changed, 232 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
new file mode 100644
index ..b40148d728ea
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
+};
+
+&A53_0 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_1 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_2 {
+   cpu-supply = <®_buck4>;
+};
+
+&A53_3 {
+   cpu-supply = <®_buck4>;
+};
+
+&fec1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_fec1>;
+   phy-mode = "rgmii-id";
+   phy-handle = <ðphy>;
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy: ethernet-phy@3 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <3>;
+   reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+   reset-assert-us = <1>;
+   };
+   };
+};
+
+&i2c1 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1>;
+   status = "okay";
+
+   pmic@8 {
+   compatible = "nxp,pf8121a";
+   reg = <0x08>;
+
+   regulators {
+   reg_ldo1: ldo1 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo2: ldo2 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo3: ldo3 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_ldo4: ldo4 {
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck1: buck1 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck2: buck2 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck3: buck3 {
+   regulator-min-microvolt =  <40>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_buck4: buck4 {
+   regulator-min-microvolt =  <40>;
+

[PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Matteo Lisi 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- don't maintain common nodes and include it, if no feature diff
Changes for v2:
- enabled fec1 node
- updated commit message
- dropped engicam from filename since it aligned with imx6 engicam
  dts files naming conventions.
- add i2c nodes
- fixed v1 comments

 arch/arm64/boot/dts/freescale/Makefile|  1 +
 .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++
 .../freescale/imx8mm-icore-mx8mm-ctouch2.dts  | 21 +
 3 files changed, 104 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 6f0777ee6cd6..8d49a2c74604 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
new file mode 100644
index ..f7870efd9dab
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+&fec1 {
+   status = "okay";
+};
+
+&i2c2 {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c2>;
+   status = "okay";
+};
+
+&i2c4 {
+   clock-frequency = <10>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c4>;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl_i2c2: i2c2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL  0x41c3
+   MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_i2c4: i2c4grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL  0x41c3
+   MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA  0x41c3
+   >;
+   };
+
+   pinctrl_uart2: uart2grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+   MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+   >;
+   };
+
+   pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+   fsl,pins = <
+   MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6   0x41
+   >;
+   };
+
+   pinctrl_usdhc1: usdhc1grp {
+   fsl,pins = <
+   MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+   MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+   MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+   MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+   MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+   MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+   >;
+   };
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+   cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+   max-frequency = <5000>;
+   bus-width = <4>;
+   no-1-8-v;
+   pm-ignore-notify;
+   keep-power-in-suspend;
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
new file mode 100644
index ..8eb01b1f882a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyrig

Re: [PATCH v2 2/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Mon, Dec 21, 2020 at 8:17 PM Jagan Teki  wrote:
>
> On Mon, Dec 21, 2020 at 8:12 PM Krzysztof Kozlowski  wrote:
> >
> > On Mon, Dec 21, 2020 at 08:09:47PM +0530, Jagan Teki wrote:
> > > On Mon, Dec 21, 2020 at 7:35 PM Krzysztof Kozlowski  
> > > wrote:
> > > >
> > > > On Mon, Dec 21, 2020 at 07:29:22PM +0530, Jagan Teki wrote:
> > > > > On Mon, Dec 21, 2020 at 7:16 PM Krzysztof Kozlowski  
> > > > > wrote:
> > > > > >
> > > > > > On Mon, Dec 21, 2020 at 05:01:47PM +0530, Jagan Teki wrote:
> > > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from 
> > > > > > > Engicam.
> > > > > > >
> > > > > > > C.TOUCH 2.0 is a general purpose carrier board with capacitive
> > > > > > > touch interface support.
> > > > > > >
> > > > > > > i.Core MX8M Mini needs to mount on top of this Carrier board for
> > > > > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> > > > > > >
> > > > > > > Add bindings for it.
> > > > > > >
> > > > > > > Signed-off-by: Jagan Teki 
> > > > > > > ---
> > > > > > > Changes for v2:
> > > > > > > - updated commit message
> > > > > > >
> > > > > > >  Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++
> > > > > > >  1 file changed, 2 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
> > > > > > > b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > > > index 67980dcef66d..e653e0a43016 100644
> > > > > > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > > > @@ -667,6 +667,8 @@ properties:
> > > > > > >  items:
> > > > > > >- enum:
> > > > > > >- beacon,imx8mm-beacon-kit  # i.MX8MM Beacon 
> > > > > > > Development Kit
> > > > > > > +  - engicam,icore-mx8mm   # i.MX8MM 
> > > > > > > Engicam i.Core MX8M Mini SOM
> > > > > > > +  - engicam,icore-mx8mm-ctouch2   # i.MX8MM 
> > > > > > > Engicam i.Core MX8M Mini C.TOUCH 2.0
> > > > > >
> > > > > > Please test your DTS against new schema with dtbs_check. This won't
> > > > > > match.
> > > > >
> > > > > Sorry, not sure I understand clearly here.
> > > > >
> > > > > This the dts file ie used matched compatible.
> > > > > compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
> > > > >  "fsl,imx8mm";
> > > > >
> > > > > I did build the dtbs_check without showing any issues like,
> > > > >
> > > > > $ make ARCH=arm64 dtbs_check
> > > > > ...
> > > > >
> > > > > From schema: 
> > > > > /w/dt-schema/dt-schema/dtschema/schemas/property-units.yaml
> > > > >   DTC arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb
> > > > >   DTC 
> > > > > arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2-of10.dtb
> > > > >   DTC 
> > > > > arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb
> > > > > ..
> > > > >
> > > > > Can you let me know what I missed here?
> > > >
> > > > You pasted here output of validating with property-units.yaml (or
> > > > something else), not the schema which you changed. If you want to limit
> > > > the tests, use DT_SCHEMA_FILES.
> > > >
> > > > I mentioned about exactly the same problem in yout previous v1
> > > > at patch #5. No changes here stil.
> > >
> > > Yes, I usually did that check before posting. Please check the build
> > > log below and fsl.yaml binding is fine to build.
> > >
> > > # make dt_binding_check DT_SCHEMA_FILES=arm/fsl.yaml
> >
> > 1. Wrong path to schema file,
> > 2. Bindings pass, they are not a problem. You were running dtbs_check,
&g

Re: [PATCH v2 6/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

On Tue, Dec 22, 2020 at 2:23 PM Krzysztof Kozlowski  wrote:
>
> On Tue, Dec 22, 2020 at 02:20:55PM +0530, Jagan Teki wrote:
> > On Tue, Dec 22, 2020 at 2:36 AM Krzysztof Kozlowski  wrote:
> > >
> > > On Tue, Dec 22, 2020 at 01:03:07AM +0530, Jagan Teki wrote:
> > > > On Mon, Dec 21, 2020 at 7:36 PM Krzysztof Kozlowski  
> > > > wrote:
> > > > >
> > > > > On Mon, Dec 21, 2020 at 05:01:51PM +0530, Jagan Teki wrote:
> > > > > > Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
> > > > > > Evaluation Board.
> > > > > >
> > > > > > Genaral features:
> > > > > > - LCD 7" C.Touch
> > > > > > - microSD slot
> > > > > > - Ethernet 1Gb
> > > > > > - Wifi/BT
> > > > > > - 2x LVDS Full HD interfaces
> > > > > > - 3x USB 2.0
> > > > > > - 1x USB 3.0
> > > > > > - HDMI Out
> > > > > > - Mini PCIe
> > > > > > - MIPI CSI
> > > > > > - 2x CAN
> > > > > > - Audio Out
> > > > > >
> > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from 
> > > > > > Engicam.
> > > > > >
> > > > > > i.Core MX8M Mini needs to mount on top of this Evaluation board for
> > > > > > creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
> > > > > >
> > > > > > PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi 
> > > > > > once
> > > > > > Mainline Linux supported.
> > > > > >
> > > > > > Add support for it.
> > > > > >
> > > > > > Signed-off-by: Matteo Lisi 
> > > > > > Signed-off-by: Jagan Teki 
> > > > > > ---
> > > > > > Changes for v2:
> > > > > > - updated commit message
> > > > > > - dropped engicam from filename since it aligned with imx6 engicam
> > > > > >   dts files naming conventions.
> > > > > >
> > > > > >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> > > > > >  .../freescale/imx8mm-engicam-edimm2.2.dtsi|  7 +++
> > > > > >  .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 21 
> > > > > > +++
> > > > > >  3 files changed, 29 insertions(+)
> > > > > >  create mode 100644 
> > > > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > > > >  create mode 100644 
> > > > > > arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile 
> > > > > > b/arch/arm64/boot/dts/freescale/Makefile
> > > > > > index 8d49a2c74604..43783076f856 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/Makefile
> > > > > > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > > > > > @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
> > > > > > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
> > > > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
> > > > > > diff --git 
> > > > > > a/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi 
> > > > > > b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > > > > new file mode 100644
> > > > > > index ..294df07289a2
> > > > > > --- /dev/null
> > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > > > > @@ -0,0 +1,7 @@
> > > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > > > +/*
> > > > > > + * Copyright (c) 2020 Engicam srl
> > > > > > + * Copyright (c) 2020 Amarula Solutions(India)
> > > > > > + */
> > > > > > +
> > > > > >

Re: [PATCH v2 6/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

On Tue, Dec 22, 2020 at 2:36 AM Krzysztof Kozlowski  wrote:
>
> On Tue, Dec 22, 2020 at 01:03:07AM +0530, Jagan Teki wrote:
> > On Mon, Dec 21, 2020 at 7:36 PM Krzysztof Kozlowski  wrote:
> > >
> > > On Mon, Dec 21, 2020 at 05:01:51PM +0530, Jagan Teki wrote:
> > > > Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
> > > > Evaluation Board.
> > > >
> > > > Genaral features:
> > > > - LCD 7" C.Touch
> > > > - microSD slot
> > > > - Ethernet 1Gb
> > > > - Wifi/BT
> > > > - 2x LVDS Full HD interfaces
> > > > - 3x USB 2.0
> > > > - 1x USB 3.0
> > > > - HDMI Out
> > > > - Mini PCIe
> > > > - MIPI CSI
> > > > - 2x CAN
> > > > - Audio Out
> > > >
> > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> > > >
> > > > i.Core MX8M Mini needs to mount on top of this Evaluation board for
> > > > creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
> > > >
> > > > PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once
> > > > Mainline Linux supported.
> > > >
> > > > Add support for it.
> > > >
> > > > Signed-off-by: Matteo Lisi 
> > > > Signed-off-by: Jagan Teki 
> > > > ---
> > > > Changes for v2:
> > > > - updated commit message
> > > > - dropped engicam from filename since it aligned with imx6 engicam
> > > >   dts files naming conventions.
> > > >
> > > >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> > > >  .../freescale/imx8mm-engicam-edimm2.2.dtsi|  7 +++
> > > >  .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 21 +++
> > > >  3 files changed, 29 insertions(+)
> > > >  create mode 100644 
> > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > >  create mode 100644 
> > > > arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile 
> > > > b/arch/arm64/boot/dts/freescale/Makefile
> > > > index 8d49a2c74604..43783076f856 100644
> > > > --- a/arch/arm64/boot/dts/freescale/Makefile
> > > > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > > > @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
> > > > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
> > > >  dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi 
> > > > b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > > new file mode 100644
> > > > index ..294df07289a2
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > > > @@ -0,0 +1,7 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + * Copyright (c) 2020 Engicam srl
> > > > + * Copyright (c) 2020 Amarula Solutions(India)
> > > > + */
> > > > +
> > > > +#include "imx8mm-engicam-common.dtsi"
> > >
> > > It seems you ignored my comments from previous email. That's not how we
> > > go with the process.
> > >
> > > Don't create confusing or overcomplicated hierarchy of includes. Don't
> > > create files which do nothing.
> >
> > Idea is to move common nodes in separate dtsi instead of adding
> > redundant nodes into respective areas. let me know if it still
> > confusing.
>
> A file which *only* includes another file does not fulfill this idea of
> moving common nodes to a separate DTSI file. Or if I still miss
> something, please point me, what common nodes are stored in
> imx8mm-engicam-edimm2.2.dtsi?

imx8mm-engicam-edimm2.2.dtsi for EDIMM2.2 Carrier
imx8mm-engicam-ctouch2.dtsi for C.TOUCH2 Carrier
imx8mm-engicam-common.dtsi for common nodes for above 2 carrier boards.

Yes, imx8mm-engicam-edimm2.2.dtsi is empty now but nodes like PCIe,
CSI, DSI will support once the respective drivers are part of Mainline
but those are not supported in C.TOUCH2 carrier board dtsi. There are
some GPIO pins differences between EDIMM2.2 and C.TOUCH2 carriers on
WiFi/BT so those will be part of the respective carrier dtsi.

Hope this would clear.

Jagan.

Re: [PATCH v2 6/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

[Jagan Teki]

On Mon, Dec 21, 2020 at 7:36 PM Krzysztof Kozlowski  wrote:
>
> On Mon, Dec 21, 2020 at 05:01:51PM +0530, Jagan Teki wrote:
> > Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
> > Evaluation Board.
> >
> > Genaral features:
> > - LCD 7" C.Touch
> > - microSD slot
> > - Ethernet 1Gb
> > - Wifi/BT
> > - 2x LVDS Full HD interfaces
> > - 3x USB 2.0
> > - 1x USB 3.0
> > - HDMI Out
> > - Mini PCIe
> > - MIPI CSI
> > - 2x CAN
> > - Audio Out
> >
> > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> >
> > i.Core MX8M Mini needs to mount on top of this Evaluation board for
> > creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
> >
> > PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once
> > Mainline Linux supported.
> >
> > Add support for it.
> >
> > Signed-off-by: Matteo Lisi 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - updated commit message
> > - dropped engicam from filename since it aligned with imx6 engicam
> >   dts files naming conventions.
> >
> >  arch/arm64/boot/dts/freescale/Makefile|  1 +
> >  .../freescale/imx8mm-engicam-edimm2.2.dtsi|  7 +++
> >  .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 21 +++
> >  3 files changed, 29 insertions(+)
> >  create mode 100644 
> > arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> >  create mode 100644 
> > arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile 
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 8d49a2c74604..43783076f856 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi 
> > b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > new file mode 100644
> > index ..294df07289a2
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi
> > @@ -0,0 +1,7 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2020 Engicam srl
> > + * Copyright (c) 2020 Amarula Solutions(India)
> > + */
> > +
> > +#include "imx8mm-engicam-common.dtsi"
>
> It seems you ignored my comments from previous email. That's not how we
> go with the process.
>
> Don't create confusing or overcomplicated hierarchy of includes. Don't
> create files which do nothing.

Idea is to move common nodes in separate dtsi instead of adding
redundant nodes into respective areas. let me know if it still
confusing.

Jagan.

Re: [PATCH v2 2/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

[Jagan Teki]

On Mon, Dec 21, 2020 at 7:16 PM Krzysztof Kozlowski  wrote:
>
> On Mon, Dec 21, 2020 at 05:01:47PM +0530, Jagan Teki wrote:
> > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> >
> > C.TOUCH 2.0 is a general purpose carrier board with capacitive
> > touch interface support.
> >
> > i.Core MX8M Mini needs to mount on top of this Carrier board for
> > creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> >
> > Add bindings for it.
> >
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - updated commit message
> >
> >  Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml 
> > b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index 67980dcef66d..e653e0a43016 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -667,6 +667,8 @@ properties:
> >  items:
> >- enum:
> >- beacon,imx8mm-beacon-kit  # i.MX8MM Beacon Development Kit
> > +  - engicam,icore-mx8mm   # i.MX8MM Engicam i.Core 
> > MX8M Mini SOM
> > +  - engicam,icore-mx8mm-ctouch2   # i.MX8MM Engicam i.Core 
> > MX8M Mini C.TOUCH 2.0
>
> Please test your DTS against new schema with dtbs_check. This won't
> match.

Sorry, not sure I understand clearly here.

This the dts file ie used matched compatible.
compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
 "fsl,imx8mm";

I did build the dtbs_check without showing any issues like,

$ make ARCH=arm64 dtbs_check
...

From schema: /w/dt-schema/dt-schema/dtschema/schemas/property-units.yaml
  DTC arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb
  DTC arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2-of10.dtb
  DTC arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb
..

Can you let me know what I missed here?

Jagan.