[PATCH 2/3] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 2/3] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 0/3] QorIQ TMU bindings and device tree update
As Rui Zhang suggested I combine TMU binding patch and two device tree patchset together. He will take all of them after the device tree patchset got ACK. @Scott please help to review the device tree patchset. Thanks. Jia Hongtao (3): dt-bindings: Update QorIQ TMU thermal bindings powerpc/mpc85xx: Update TMU device tree node for T1040/T1042 powerpc/mpc85xx: Update TMU device tree node for T1023/T1024 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++ arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++-- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++-- 3 files changed, 11 insertions(+), 4 deletions(-) -- 2.1.0.27.g96db324
[PATCH 0/3] QorIQ TMU bindings and device tree update
As Rui Zhang suggested I combine TMU binding patch and two device tree patchset together. He will take all of them after the device tree patchset got ACK. @Scott please help to review the device tree patchset. Thanks. Jia Hongtao (3): dt-bindings: Update QorIQ TMU thermal bindings powerpc/mpc85xx: Update TMU device tree node for T1040/T1042 powerpc/mpc85xx: Update TMU device tree node for T1023/T1024 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++ arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++-- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++-- 3 files changed, 11 insertions(+), 4 deletions(-) -- 2.1.0.27.g96db324
[PATCH 3/3] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index da2894c..4908af5 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -422,7 +422,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -430,7 +430,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 3/3] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index da2894c..4908af5 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -422,7 +422,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -430,7 +430,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 1/3] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH 1/3] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH V3] arm64: dts: ls1046a: Add TMU device tree support
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V3:
* Update the subject title according to Shawn Guo's comment.
* Fix some style issue.
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 80 ++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..4a164b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +281,84 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1 */
+ <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+ /* Calibration data group 2 */
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+ /* Calibration data group 3 */
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+ /* Calibration data group 4 */
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+
[PATCH V3] arm64: dts: ls1046a: Add TMU device tree support
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Changes for V3:
* Update the subject title according to Shawn Guo's comment.
* Fix some style issue.
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 80 ++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..4a164b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +281,84 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1 */
+ <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+ /* Calibration data group 2 */
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+ /* Calibration data group 3 */
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+ /* Calibration data group 4 */
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ coolin
[PATCH V2] arm64:dts:ls1046a: Add TMU device tree support
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 83 ++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..df53a4a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +281,87 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1*/
+ <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ /* Calibration data group 2*/
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ /* Calibration data group 3*/
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ /* Calibration data group 4*/
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+
[PATCH V2] arm64:dts:ls1046a: Add TMU device tree support
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 83 ++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..df53a4a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +281,87 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1*/
+ <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ /* Calibration data group 2*/
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ /* Calibration data group 3*/
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ /* Calibration data group 4*/
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ coolin
[PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..40604e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,8 @@
*/
#include
+#include
+
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +69,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +282,82 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ cooling-de
[PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..40604e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,8 @@
*/
#include
+#include
+
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +69,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +282,82 @@
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ cooling-device =
[PATCH 2/2] arm64:dt:ls1012a: Add TMU device tree support for LS1012A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Depend on patch "[v3] arm64: Add DTS support for FSL's LS1012A SoC".
https://patchwork.kernel.org/patch/9462399/
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..bc694b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -43,6 +43,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1012a";
@@ -127,6 +128,81 @@
#clock-cells = <2>;
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ cooling-device =
+ < THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+
[PATCH 2/2] arm64:dt:ls1012a: Add TMU device tree support for LS1012A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Depend on patch "[v3] arm64: Add DTS support for FSL's LS1012A SoC".
https://patchwork.kernel.org/patch/9462399/
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..bc694b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -43,6 +43,7 @@
*/
#include
+#include
/ {
compatible = "fsl,ls1012a";
@@ -127,6 +128,81 @@
#clock-cells = <2>;
clocks = <>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ cooling-device =
+ < THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
[PATCH V3 2/2] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V3 2/2] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 5/5] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index b0dd010..8bc1f8f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8..265e0a8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 337da90..723185e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,15 +64,16 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
@@ -78,15 +81,16 @@
next-level-cache = <_l2>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = < 1 1>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
@@ -94,15 +98,16 @@
next-level-cache = <_l2>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = < 1 2>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
@@ -110,15 +115,16 @@
next-level-cache = <_l2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = < 1 3>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@
[PATCH V2 5/5] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
From: Hongtao Jia
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index b0dd010..8bc1f8f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8..265e0a8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 337da90..723185e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,15 +64,16 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
@@ -78,15 +81,16 @@
next-level-cache = <_l2>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = < 1 1>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
@@ -94,15 +98,16 @@
next-level-cache = <_l2>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = < 1 2>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
@@ -110,15 +115,16 @@
next-level-cache = <_l2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = < 1 3>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@301 {
+ cp
[PATCH V2 3/5] arm:dt:ls1021a: Add TMU device tree support for LS1021A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..282d854 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
[PATCH V2 3/5] arm:dt:ls1021a: Add TMU device tree support for LS1021A
From: Hongtao Jia
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..282d854 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+
[PATCH V2 4/5] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index dd9e919..0989d63 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index d2313e0..c37110b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 220ac70..41e5dc1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -66,6 +68,7 @@
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -254,6 +257,81 @@
big-endian;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000&g
[PATCH V2 4/5] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
From: Hongtao Jia
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index dd9e919..0989d63 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index d2313e0..c37110b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 220ac70..41e5dc1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -66,6 +68,7 @@
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -254,6 +257,81 @@
big-endian;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
+
+
[PATCH V2 1/5] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia <hongtao@nxp.com>
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 1/5] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 2/5] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia <hongtao@nxp.com>
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 2/5] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes of V2:
* Add HAS_IOMEM dependency to fix build error on UM
drivers/thermal/Kconfig | 10 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 339 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..56ef30d 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,16 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ depends on HAS_IOMEM
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/
[PATCH V2 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao
---
Changes of V2:
* Add HAS_IOMEM dependency to fix build error on UM
drivers/thermal/Kconfig | 10 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 339 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..56ef30d 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,16 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ depends on HAS_IOMEM
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/*
+ * Thermal zone da
[PATCH V2 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Remove formatting chnages.
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH V2 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Remove formatting chnages.
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH 2/7] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 507649e..089eb56 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 2/7] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 507649e..089eb56 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 3/7] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
drivers/thermal/Kconfig | 9 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 338 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..bef26cd 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,15 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/*
+ * Thermal zone data
+ */
+struct qoriq_tmu_data {
+ struct thermal_zone_device *tz;
+
[PATCH 3/7] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao
---
drivers/thermal/Kconfig | 9 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 338 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..bef26cd 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,15 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/*
+ * Thermal zone data
+ */
+struct qoriq_tmu_data {
+ struct thermal_zone_device *tz;
+ struct qoriq_tmu_r
[PATCH 4/7] arm:dt:ls1021a: Add TMU device tree support for LS1021A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e92..1bac9d8 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+
[PATCH 4/7] arm:dt:ls1021a: Add TMU device tree support for LS1021A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e92..1bac9d8 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+
[PATCH 6/7] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index e8801fa..18e99f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index e127f0b..f1c8115 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..5cc27df 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,56 +64,60 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
clocks = < 1 0>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
clocks = < 1 1>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
clocks = < 1 1>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
clocks = < 1 2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
clocks = < 1 2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
clocks = < 1 3>;
+ #cooling-cells = <2>;
};
- cpu@301 {
+ cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
@@ -191,6 +197,100 @@
clocks = <>;
};
+ tmu: tmu@1f8 {
+ compatible = "fsl,qori
[PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8eeef80 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,22 +1,28 @@
* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible: Must include "fsl,qoriq-tmu". The version of the device is
determined by the TMU IP Block Revision Register (IPBRR0) at
offset 0x0BF8.
- Table of correspondences between IPBRR0 values and example chips:
+ Table of correspondences between IPBRR0 values and example chips:
Value Device
-- -
0x01900102 T1040
-- reg : Address range of TMU registers.
-- interrupts : Contains the interrupt for TMU.
-- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+- reg: Address range of TMU registers.
+- interrupts: Contains the interrupt for TMU.
+- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
the SoC reference manual. The first cell is TTR0CR, the second is
TTR1CR, etc.
-- fsl,tmu-calibration : A list of cell pairs containing temperature
+- fsl,tmu-calibration: A list of cell pairs containing temperature
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian: If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8eeef80 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,22 +1,28 @@
* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible: Must include "fsl,qoriq-tmu". The version of the device is
determined by the TMU IP Block Revision Register (IPBRR0) at
offset 0x0BF8.
- Table of correspondences between IPBRR0 values and example chips:
+ Table of correspondences between IPBRR0 values and example chips:
Value Device
-- -
0x01900102 T1040
-- reg : Address range of TMU registers.
-- interrupts : Contains the interrupt for TMU.
-- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+- reg: Address range of TMU registers.
+- interrupts: Contains the interrupt for TMU.
+- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
the SoC reference manual. The first cell is TTR0CR, the second is
TTR1CR, etc.
-- fsl,tmu-calibration : A list of cell pairs containing temperature
+- fsl,tmu-calibration: A list of cell pairs containing temperature
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian: If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
2.1.0.27.g96db324
[PATCH 6/7] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index e8801fa..18e99f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index e127f0b..f1c8115 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..5cc27df 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,56 +64,60 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
clocks = < 1 0>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
clocks = < 1 1>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
clocks = < 1 1>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
clocks = < 1 2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
clocks = < 1 2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
clocks = < 1 3>;
+ #cooling-cells = <2>;
};
- cpu@301 {
+ cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
@@ -191,6 +197,100 @@
clocks = <>;
};
+ tmu: tmu@1f8 {
+ compatible = "fsl,qoriq-tmu&
[PATCH 5/7] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 9d3e9fe..fa447b6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index f895fc0..6015d88 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..4004273 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -65,6 +67,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -196,6 +199,81 @@
bus-width = <4>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
[PATCH 5/7] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 9d3e9fe..fa447b6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index f895fc0..6015d88 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..4004273 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -65,6 +67,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -196,6 +199,81 @@
bus-width = <4>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
+
+ trips {
+
RE: [PATCH V3 5/6] Avoid duplicate probe for of platform devices
> -Original Message- > From: Rob Herring [mailto:robherri...@gmail.com] > Sent: Monday, July 09, 2012 9:58 PM > To: Li Yang-R58472 > Cc: Jia Hongtao-B38951; Greg KH; devicetree-disc...@lists.ozlabs.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform devices > > On 07/08/2012 10:46 PM, Li Yang-R58472 wrote: > >>> I don't understand, why is this just showing up now? What > >>> changed to cause this? Couldn't that be the real problem here? > >>> > >> > >> The issue is showing up because we now probe devices twice. > >> Previously, we just probe devices once. But now we changed the way > >> of pci init which makes pci controllers should be probed earlier > >> than other devices. So we have to probe pci nodes separately. Probe > >> more than once is the root cause of this issue. > >> > >> The pci patchset I mentioned please refer to: > >> http://patchwork.ozlabs.org/patch/163742/ > > > > Let me try to clarify a little bit. The of platform bus normally > > traverse the device tree to add all the devices. The change which > > caused problem is that we need to probe PCIe RC devices at a earlier > > stage of initialization. So we added these PCIe RC devices earlier > > than the normal device tree traversal process. These PCIe RC devices > > will be scanned again during the normal traversal and cause > > duplicated devices being added. Our proposal is to deal with > > duplicated devices automatically and make it possible to scan the > > device tree multiple times for devices to be added. > > What is making PCI need to be probed earlier? Perhaps deferred probe > would work? Pci initialization fsl_add_bridge() should be called earlier as they used to be called in board specific code xx_setup_arch(). Now we put this init part in the probe function of pci controller to make the code infrastructure better. That make pci bus should be probed earlier. > > Perhaps giving of_platform_populate an exclude list of compatible > strings to skip would work. > > Rob Yes, this would work and we actually already implemented this solution. But I think it looks hackish and will influence the other API users. Thanks. -Jia Hongtao. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH V3 5/6] Avoid duplicate probe for of platform devices
-Original Message- From: Rob Herring [mailto:robherri...@gmail.com] Sent: Monday, July 09, 2012 9:58 PM To: Li Yang-R58472 Cc: Jia Hongtao-B38951; Greg KH; devicetree-disc...@lists.ozlabs.org; linux-kernel@vger.kernel.org Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform devices On 07/08/2012 10:46 PM, Li Yang-R58472 wrote: I don't understand, why is this just showing up now? What changed to cause this? Couldn't that be the real problem here? The issue is showing up because we now probe devices twice. Previously, we just probe devices once. But now we changed the way of pci init which makes pci controllers should be probed earlier than other devices. So we have to probe pci nodes separately. Probe more than once is the root cause of this issue. The pci patchset I mentioned please refer to: http://patchwork.ozlabs.org/patch/163742/ Let me try to clarify a little bit. The of platform bus normally traverse the device tree to add all the devices. The change which caused problem is that we need to probe PCIe RC devices at a earlier stage of initialization. So we added these PCIe RC devices earlier than the normal device tree traversal process. These PCIe RC devices will be scanned again during the normal traversal and cause duplicated devices being added. Our proposal is to deal with duplicated devices automatically and make it possible to scan the device tree multiple times for devices to be added. What is making PCI need to be probed earlier? Perhaps deferred probe would work? Pci initialization fsl_add_bridge() should be called earlier as they used to be called in board specific code xx_setup_arch(). Now we put this init part in the probe function of pci controller to make the code infrastructure better. That make pci bus should be probed earlier. Perhaps giving of_platform_populate an exclude list of compatible strings to skip would work. Rob Yes, this would work and we actually already implemented this solution. But I think it looks hackish and will influence the other API users. Thanks. -Jia Hongtao. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH V3 5/6] Avoid duplicate probe for of platform devices
> -Original Message- > From: Greg KH [mailto:g...@kroah.com] > Sent: Saturday, July 07, 2012 12:17 AM > To: Jia Hongtao-B38951 > Cc: Rob Herring; devicetree-disc...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; Li Yang-R58472 > Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform devices > > On Fri, Jul 06, 2012 at 06:07:43AM +, Jia Hongtao-B38951 wrote: > > > > > -Original Message- > > > From: Greg KH [mailto:g...@kroah.com] > > > Sent: Friday, July 06, 2012 12:26 PM > > > To: Jia Hongtao-B38951 > > > Cc: Rob Herring; devicetree-disc...@lists.ozlabs.org; linux- > > > ker...@vger.kernel.org; Li Yang-R58472 > > > Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform > devices > > > > > > On Fri, Jul 06, 2012 at 02:05:05AM +, Jia Hongtao-B38951 wrote: > > > > Hi Rob and Greg KH, > > > > > > > > Do you have any better idea to avoid duplication probe warning? > > > > > > I have no idea what the problem is that you are trying to solve. > > > > > > > > On 06/08/2012 04:43 AM, Jia Hongtao wrote: > > > > > > We changed the pcie controller driver to platform driver so > that > > > the > > > > > PCI > > > > > > of platform devices need to be created earlier in the > arch_initcall > > > > > stage > > > > > > according to the original timing of calling fsl_add_bridge(). > So we > > > do > > > > > PCI > > > > > > probing separately from other devices. But probing more than > once > > > could > > > > > > cause duplication warning. We add check if the devices have > already > > > > > probed > > > > > > before probing any devices to avoid duplication warning. > > > > > > Ick, something else is going wrong here, how could you ever have the > > > same device probed more than once? > > > > > > > > > Signed-off-by: Jia Hongtao > > > > > > Signed-off-by: Li Yang > > > > > > --- > > > > > > > > > > Where's v1 and v2 history? > > > > > > > > > > > drivers/of/platform.c | 18 -- > > > > > > 1 files changed, 12 insertions(+), 6 deletions(-) > > > > > > > > > > > > diff --git a/drivers/of/platform.c b/drivers/of/platform.c > > > > > > index a37330e..3aab01f 100644 > > > > > > --- a/drivers/of/platform.c > > > > > > +++ b/drivers/of/platform.c > > > > > > @@ -139,6 +139,18 @@ struct platform_device > *of_device_alloc(struct > > > > > device_node *np, > > > > > > if (!dev) > > > > > > return NULL; > > > > > > > > > > > > + dev->dev.of_node = of_node_get(np); > > > > > > + if (bus_id) > > > > > > + dev_set_name(>dev, "%s", bus_id); > > > > > > + else > > > > > > + of_device_make_bus_id(>dev); > > > > > > + > > > > > > + if (kset_find_obj(dev->dev.kobj.kset, kobject_name( > > > >dev.kobj))) > > > > > > Whatever you are trying to do here, odds are, it's wrong :) > > > > > > What is happening that is causing the problem? What is causing the > > > platform core to be calling probe on a device more than once? > > > > > > greg k-h > > > > This is why in some cases we may probe twice: > > Firstly, we need to probe pci controller separately. But in KVM > different > > topology of device tree is used in which pci nodes are not under root > node > > but under "simple bus". Unfortunately, of_platform_bus_probe() will > probe > > all the first level nodes under "simple bus" so pci nodes will probe > again. > > Sounds like a bug :) > > > Two ways to solve this problem: > > 1. All the nodes that need to be probed should just under root. > > That seems reasonable. > > > 2. Avoid duplication probe at runtime like this patch did. > > No, don't paper over the real problem in the platform core code like > this. Fix the real issue here instead. > > > I do like the first one but it's hard to changing the traditional way > that > > exist for a long time. > > I don't understand, why is this just showing up now? What changed to > cause this? Couldn't that be the real problem here? > The issue is showing up because we now probe devices twice. Previously, we just probe devices once. But now we changed the way of pci init which makes pci controllers should be probed earlier than other devices. So we have to probe pci nodes separately. Probe more than once is the root cause of this issue. The pci patchset I mentioned please refer to: http://patchwork.ozlabs.org/patch/163742/ - Jia Hongtao. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH V3 5/6] Avoid duplicate probe for of platform devices
-Original Message- From: Greg KH [mailto:g...@kroah.com] Sent: Saturday, July 07, 2012 12:17 AM To: Jia Hongtao-B38951 Cc: Rob Herring; devicetree-disc...@lists.ozlabs.org; linux- ker...@vger.kernel.org; Li Yang-R58472 Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform devices On Fri, Jul 06, 2012 at 06:07:43AM +, Jia Hongtao-B38951 wrote: -Original Message- From: Greg KH [mailto:g...@kroah.com] Sent: Friday, July 06, 2012 12:26 PM To: Jia Hongtao-B38951 Cc: Rob Herring; devicetree-disc...@lists.ozlabs.org; linux- ker...@vger.kernel.org; Li Yang-R58472 Subject: Re: [PATCH V3 5/6] Avoid duplicate probe for of platform devices On Fri, Jul 06, 2012 at 02:05:05AM +, Jia Hongtao-B38951 wrote: Hi Rob and Greg KH, Do you have any better idea to avoid duplication probe warning? I have no idea what the problem is that you are trying to solve. On 06/08/2012 04:43 AM, Jia Hongtao wrote: We changed the pcie controller driver to platform driver so that the PCI of platform devices need to be created earlier in the arch_initcall stage according to the original timing of calling fsl_add_bridge(). So we do PCI probing separately from other devices. But probing more than once could cause duplication warning. We add check if the devices have already probed before probing any devices to avoid duplication warning. Ick, something else is going wrong here, how could you ever have the same device probed more than once? Signed-off-by: Jia Hongtao b38...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- Where's v1 and v2 history? drivers/of/platform.c | 18 -- 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/of/platform.c b/drivers/of/platform.c index a37330e..3aab01f 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -139,6 +139,18 @@ struct platform_device *of_device_alloc(struct device_node *np, if (!dev) return NULL; + dev-dev.of_node = of_node_get(np); + if (bus_id) + dev_set_name(dev-dev, %s, bus_id); + else + of_device_make_bus_id(dev-dev); + + if (kset_find_obj(dev-dev.kobj.kset, kobject_name(dev- dev.kobj))) Whatever you are trying to do here, odds are, it's wrong :) What is happening that is causing the problem? What is causing the platform core to be calling probe on a device more than once? greg k-h This is why in some cases we may probe twice: Firstly, we need to probe pci controller separately. But in KVM different topology of device tree is used in which pci nodes are not under root node but under simple bus. Unfortunately, of_platform_bus_probe() will probe all the first level nodes under simple bus so pci nodes will probe again. Sounds like a bug :) Two ways to solve this problem: 1. All the nodes that need to be probed should just under root. That seems reasonable. 2. Avoid duplication probe at runtime like this patch did. No, don't paper over the real problem in the platform core code like this. Fix the real issue here instead. I do like the first one but it's hard to changing the traditional way that exist for a long time. I don't understand, why is this just showing up now? What changed to cause this? Couldn't that be the real problem here? The issue is showing up because we now probe devices twice. Previously, we just probe devices once. But now we changed the way of pci init which makes pci controllers should be probed earlier than other devices. So we have to probe pci nodes separately. Probe more than once is the root cause of this issue. The pci patchset I mentioned please refer to: http://patchwork.ozlabs.org/patch/163742/ - Jia Hongtao. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
