[PATCH 1/4] drm/panel: seperate panel power control from panel prepare/unprepare
Some dsi panels require the dsi lanes keeping low before panel power
on. So seperate the panel power control and the communication with panel.
And put the power control in drm_panel_prepare_power and
drm_panel_unprepare_power. Put the communication with panel in
drm_panel_prepare and drm_panel_unprepare.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/bridge/panel.c | 17 +++
drivers/gpu/drm/drm_panel.c| 38 ++
include/drm/drm_bridge.h | 2 ++
include/drm/drm_panel.h| 17 +++
4 files changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 0ddc37551194..a19c96e710fc 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -125,6 +125,23 @@ static int panel_bridge_get_modes(struct drm_bridge
*bridge,
return drm_panel_get_modes(panel_bridge->panel, connector);
}
+int panel_bridge_prepare_power(struct drm_bridge *bridge)
+{
+ struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+ return drm_panel_prepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_prepare_power);
+
+int panel_bridge_unprepare_power(struct drm_bridge *bridge)
+{
+struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+return drm_panel_unprepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_unprepare_power);
+
+
static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index f634371c717a..7bb5185db17d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -115,6 +115,24 @@ int drm_panel_prepare(struct drm_panel *panel)
}
EXPORT_SYMBOL(drm_panel_prepare);
+/**
+ * drm_panel_prepare_power - power on a panel's power
+ * @panel: DRM panel
+ *
+ * Calling this function will enable power and deassert any reset signals to
+ * the panel.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_prepare_power(struct drm_panel *panel)
+{
+ if (panel && panel->funcs && panel->funcs->prepare_power)
+ return panel->funcs->prepare_power(panel);
+
+ return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_prepare_power);
+
/**
* drm_panel_unprepare - power off a panel
* @panel: DRM panel
@@ -138,6 +156,26 @@ int drm_panel_unprepare(struct drm_panel *panel)
}
EXPORT_SYMBOL(drm_panel_unprepare);
+/**
+ * drm_panel_unprepare_power - power off a panel
+ * @panel: DRM panel
+ *
+ * Calling this function will completely power off a panel (assert the panel's
+ * reset, turn off power supplies, ...). After this function has completed, it
+ * is usually no longer possible to communicate with the panel until another
+ * call to drm_panel_prepare_power and drm_panel_prepare().
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_unprepare_power(struct drm_panel *panel)
+{
+ if (panel && panel->funcs && panel->funcs->unprepare_power)
+ return panel->funcs->unprepare_power(panel);
+
+ return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_unprepare_power);
+
/**
* drm_panel_enable - enable a panel
* @panel: DRM panel
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index 2195daa289d2..cc94c9da47d8 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -892,6 +892,8 @@ struct drm_bridge *devm_drm_panel_bridge_add_typed(struct
device *dev,
struct drm_panel *panel,
u32 connector_type);
struct drm_connector *drm_panel_bridge_connector(struct drm_bridge *bridge);
+int panel_bridge_prepare_power(struct drm_bridge *bridge);
+int panel_bridge_unprepare_power(struct drm_bridge *bridge);
#endif
#endif
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 33605c3f0eba..48e83712ad44 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -68,6 +68,13 @@ enum drm_panel_orientation;
* functionality to enable/disable backlight.
*/
struct drm_panel_funcs {
+ /**
+* @prepare_power:
+*
+* Turn on panel power.
+*/
+ int (*prepare_power)(struct drm_panel *panel);
+
/**
* @prepare:
*
@@ -115,6 +122,13 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel,
struct drm_connector *connector);
+ /**
+* @unprepare_power:
+*
+* Turn off panel_power.
+*/
+ int (*unprepare_power)(struct drm_panel *panel);
+
/**
* @get_timings:
*
@@ -180,6 +194,9 @@ void drm_panel_init(struct drm_panel
[PATCH 2/4] drm/panel: boe-tv101wum-n16 seperate the panel power control
Seperate the panel power control from prepare/unprepare.
Signed-off-by: Jitao Shi
---
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 72 +--
1 file changed, 50 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index db9d0b86d542..dc49079a74d1 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -50,6 +50,7 @@ struct boe_panel {
struct regulator *avdd;
struct gpio_desc *enable_gpio;
+ bool prepared_power;
bool prepared;
};
@@ -488,22 +489,13 @@ static int boe_panel_enter_sleep_mode(struct boe_panel
*boe)
return 0;
}
-static int boe_panel_unprepare(struct drm_panel *panel)
+static int boe_panel_unprepare_power(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
- int ret;
- if (!boe->prepared)
+ if (!boe->prepared_power)
return 0;
- ret = boe_panel_enter_sleep_mode(boe);
- if (ret < 0) {
- dev_err(panel->dev, "failed to set panel off: %d\n", ret);
- return ret;
- }
-
- msleep(150);
-
if (boe->desc->discharge_on_disable) {
regulator_disable(boe->avee);
regulator_disable(boe->avdd);
@@ -512,6 +504,7 @@ static int boe_panel_unprepare(struct drm_panel *panel)
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
} else {
+ msleep(150);
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(500, 1000);
regulator_disable(boe->avee);
@@ -520,17 +513,39 @@ static int boe_panel_unprepare(struct drm_panel *panel)
regulator_disable(boe->pp1800);
}
+ boe->prepared_power = false;
+
+ return 0;
+}
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+ struct boe_panel *boe = to_boe_panel(panel);
+ int ret;
+
+ if (!boe->prepared)
+ return 0;
+
+ if (!boe->desc->discharge_on_disable) {
+ ret = boe_panel_enter_sleep_mode(boe);
+ if (ret < 0) {
+ dev_err(panel->dev, "failed to set panel off: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
boe->prepared = false;
return 0;
}
-static int boe_panel_prepare(struct drm_panel *panel)
+static int boe_panel_prepare_power(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
int ret;
- if (boe->prepared)
+ if (boe->prepared_power)
return 0;
gpiod_set_value(boe->enable_gpio, 0);
@@ -558,18 +573,10 @@ static int boe_panel_prepare(struct drm_panel *panel)
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(6000, 1);
- ret = boe_panel_init_dcs_cmd(boe);
- if (ret < 0) {
- dev_err(panel->dev, "failed to init panel: %d\n", ret);
- goto poweroff;
- }
-
- boe->prepared = true;
+ boe->prepared_power = true;
return 0;
-poweroff:
- regulator_disable(boe->avee);
poweroffavdd:
regulator_disable(boe->avdd);
poweroff1v8:
@@ -580,6 +587,25 @@ static int boe_panel_prepare(struct drm_panel *panel)
return ret;
}
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+ struct boe_panel *boe = to_boe_panel(panel);
+ int ret;
+
+ if (boe->prepared)
+ return 0;
+
+ ret = boe_panel_init_dcs_cmd(boe);
+ if (ret < 0) {
+ dev_err(panel->dev, "failed to init panel: %d\n", ret);
+ return ret;
+ }
+
+ boe->prepared = true;
+
+ return 0;
+}
+
static int boe_panel_enable(struct drm_panel *panel)
{
msleep(130);
@@ -749,7 +775,9 @@ static int boe_panel_get_modes(struct drm_panel *panel,
static const struct drm_panel_funcs boe_panel_funcs = {
.unprepare = boe_panel_unprepare,
+ .unprepare_power = boe_panel_unprepare_power,
.prepare = boe_panel_prepare,
+ .prepare_power = boe_panel_prepare_power,
.enable = boe_panel_enable,
.get_modes = boe_panel_get_modes,
};
--
2.25.1
[PATCH 4/4] drm/mediatek: add dsi module reset driver
Reset dsi HW to default when power on. Prevent the setting differet
between bootloader and kernel.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 36 +-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 455fe582c6b5..113438ddd4cc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -7,10 +7,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
#include
@@ -143,6 +145,8 @@
#define DATA_0 (0xff << 16)
#define DATA_1 (0xff << 24)
+#define MMSYS_SW_RST_DSI_B BIT(25)
+
#define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
#define MTK_DSI_HOST_IS_READ(type) \
@@ -186,7 +190,8 @@ struct mtk_dsi {
struct drm_bridge *next_bridge;
struct drm_connector *connector;
struct phy *phy;
-
+ struct regmap *mmsys_sw_rst_b;
+ u32 sw_rst_b;
void __iomem *regs;
struct clk *engine_clk;
@@ -272,6 +277,16 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
}
+static void mtk_dsi_reset_all(struct mtk_dsi *dsi)
+{
+ regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
+ MMSYS_SW_RST_DSI_B, 0);
+ usleep_range(1000, 1100);
+
+ regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
+ MMSYS_SW_RST_DSI_B, MMSYS_SW_RST_DSI_B);
+}
+
static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
{
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
@@ -985,6 +1000,8 @@ static int mtk_dsi_bind(struct device *dev, struct device
*master, void *data)
ret = mtk_dsi_encoder_init(drm, dsi);
+ mtk_dsi_reset_all(dsi);
+
return ret;
}
@@ -1007,6 +1024,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct drm_panel *panel;
struct resource *regs;
+ struct regmap *regmap;
int irq_num;
int ret;
@@ -1022,6 +1040,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
+ regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+"mediatek,syscon-dsi");
+ ret = of_property_read_u32_index(dev->of_node, "mediatek,syscon-dsi", 1,
+&dsi->sw_rst_b);
+
+ if (IS_ERR(regmap))
+ ret = PTR_ERR(regmap);
+
+ if (ret) {
+ ret = PTR_ERR(regmap);
+ dev_err(dev, "Failed to get mmsys registers: %d\n", ret);
+ return ret;
+ }
+
+ dsi->mmsys_sw_rst_b = regmap;
+
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
&panel, &dsi->next_bridge);
if (ret)
--
2.25.1
[PATCH 3/4] drm/mediatek: fine tune the dsi panel's power sequence
Add the drm_panel_prepare_power and drm_panel_unprepare_power control.
Turn on panel power(drm_panel_prepare_power) and control before dsi
enable. And then dsi enable, send dcs cmd in drm_panel_prepare, last
turn on backlight.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index a1ff152ef468..455fe582c6b5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -615,10 +615,13 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
dsi->lanes);
+ if (panel_bridge_prepare_power(dsi->next_bridge))
+ DRM_INFO("can't prepare power the panel\n");
+
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
if (ret < 0) {
dev_err(dev, "Failed to set data rate: %d\n", ret);
- goto err_refcount;
+ goto err_prepare_power;
}
phy_power_on(dsi->phy);
@@ -661,7 +664,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->engine_clk);
err_phy_power_off:
phy_power_off(dsi->phy);
-err_refcount:
+err_prepare_power:
+ if (panel_bridge_unprepare_power(dsi->next_bridge))
+ DRM_INFO("Can't unprepare power the panel\n");
dsi->refcount--;
return ret;
}
@@ -694,6 +699,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->digital_clk);
phy_power_off(dsi->phy);
+
+ if (panel_bridge_unprepare_power(dsi->next_bridge))
+ DRM_INFO("Can't unprepare power the panel\n");
}
static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
--
2.25.1
[PATCH] drm/mediatek: force hsa hsa hfp packets multiple of line num to avoid screen shift
The bridge chip ANX7625 require the line packets ending at the sametime
or ANX7625 will shift the screen.
Change-Id: Ia324ad28fbff54140feedb9a1d6bfb2b246d0447
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index a1ff152ef468..e825a80862de 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
u32 data_rate;
+ /* force dsi line end without dsi_null data */
+ bool force_dsi_end_without_null;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -495,6 +497,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
+ if (dsi->force_dsi_end_without_null) {
+ horizontal_sync_active_byte =
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+ horizontal_frontporch_byte =
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+ horizontal_backporch_byte = roundup(horizontal_backporch_byte,
dsi->lanes) - 2;
+ horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp +
2) % dsi->lanes;
+ }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1091,6 +1100,9 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
+ dsi->force_dsi_end_without_null = of_property_read_bool(dev->of_node,
+
"force_dsi_end_without_null");
+
drm_bridge_add(&dsi->bridge);
ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
--
2.25.1
[PATCH 1/3] drm/mediatek: dpi dual edge sample mode support
DPI can sample on falling, rising or both edge.
When DPI sample the data both rising and falling edge.
It can reduce half data io pins.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ccd681a2a4c2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -81,6 +81,7 @@ struct mtk_dpi {
struct pinctrl *pinctrl;
struct pinctrl_state *pins_gpio;
struct pinctrl_state *pins_dpi;
+ bool ddr_edge_sel;
int refcount;
};
@@ -119,6 +120,7 @@ struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
bool edge_sel_en;
+ bool dual_edge;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -378,6 +380,15 @@ static void mtk_dpi_config_color_format(struct mtk_dpi
*dpi,
}
}
+static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
+{
+ if (dpi->conf->dual_edge) {
+ mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->ddr_edge_sel ?
EDGE_SEL : 0, EDGE_SEL);
+ }
+}
+
static void mtk_dpi_power_off(struct mtk_dpi *dpi)
{
if (WARN_ON(dpi->refcount == 0))
@@ -516,6 +527,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
+ mtk_dpi_dual_edge(dpi);
mtk_dpi_config_disable_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
--
2.12.5
[PATCH 3/3] drm/mediatek: dpi: add bus format negociation
Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
the possible output and input formats for the current mode and monitor,
and use the negotiated formats in a basic atomic_check callback.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 96 --
1 file changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 87bb27649c4c..4e45d1b01b0c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -81,6 +81,8 @@ struct mtk_dpi {
struct pinctrl *pinctrl;
struct pinctrl_state *pins_gpio;
struct pinctrl_state *pins_dpi;
+ unsigned int in_bus_format;
+ unsigned int out_bus_format;
bool ddr_edge_sel;
int refcount;
};
@@ -534,6 +536,92 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
return 0;
}
+#define MAX_OUTPUT_SEL_FORMATS 2
+
+static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge
*bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ struct drm_display_mode *mode = &crtc_state->mode;
+ u32 *output_fmts;
+ struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+ *num_output_fmts = 0;
+
+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
+ GFP_KERNEL);
+ if (!output_fmts)
+ return NULL;
+
+ /* Default 8bit RGB fallback */
+ if (dpi->conf->dual_edge) {
+ output_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
+ output_fmts[1] = MEDIA_BUS_FMT_RGB888_2X12_BE;
+ *num_output_fmts = 2;
+ } else {
+ output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+ *num_output_fmts = 1;
+ }
+
+ return output_fmts;
+}
+
+#define MAX_INPUT_SEL_FORMATS 1
+
+static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ *num_input_fmts = 0;
+
+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
+GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ *num_input_fmts = 1;
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+
+ return input_fmts;
+}
+
+static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct mtk_dpi *dpi = bridge->driver_private;
+
+ dpi->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ dpi->in_bus_format = bridge_state->input_bus_cfg.format;
+
+ dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
+ bridge_state->input_bus_cfg.format,
+ bridge_state->output_bus_cfg.format);
+
+ if (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE ||
+ dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_BE) {
+ dpi->ddr_edge_sel =
+ (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ?
+true : false;
+ }
+
+ dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
+ dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
+ dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
+ dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
+
+ return 0;
+}
+
static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
@@ -572,6 +660,9 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs =
{
.mode_set = mtk_dpi_bridge_mode_set,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
+ .atomic_check = mtk_dpi_bridge_atomic_check,
+ .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
+ .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
};
static void mtk_dpi_start(struct mtk_ddp_comp *comp)
@@ -621,11 +712,6 @@ static int mtk_dpi_bind(struct device *dev, struct device
*master, void *data)
goto err_cleanup;
[PATCH 0/3] mt8183 dpi supports dual edge
DPI can sample on falling, rising or both edge. When DPI sample the data both rising and falling edge. It can reduce half data io pins. Jitao Shi (3): drm/mediatek: dpi dual edge sample mode support drm/mediatek: config mt8183 driver data to support dual edge sample drm/mediatek: dpi: add bus format negociation drivers/gpu/drm/mediatek/mtk_dpi.c | 109 +++-- 1 file changed, 104 insertions(+), 5 deletions(-) -- 2.12.5
[PATCH 2/3] drm/mediatek: config mt8183 driver data to support dual edge sample
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ccd681a2a4c2..87bb27649c4c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -696,6 +696,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .dual_edge = true,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.12.5
[PATCH v3 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi
Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi. Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6cdb734c91a9..2f566f19e6e0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi + - mediatek,mt8192-dpi reg: maxItems: 1 -- 2.25.1
[PATCH v3 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+ u32 max_clock_khz;
bool edge_sel_en;
};
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge
*bridge)
mtk_dpi_set_display_mode(dpi, &dpi->mode);
}
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+ struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+ if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+ .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
};
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 30,
};
static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+ .max_clock_khz = 15,
};
static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 10,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.25.1
[PATCH v3 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..f6f71eb67ff1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,12 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
};
+static const struct mtk_dpi_conf mt8192_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .max_clock_khz = 15,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -837,6 +843,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
.data = &mt8183_conf,
},
+ { .compatible = "mediatek,mt8192-dpi",
+ .data = &mt8192_conf,
+ },
{ },
};
--
2.25.1
[PATCH v3 0/3] Add check for max clock rate in mode_valid
Changes since v2: - add const struct drm_display_info *info in mtk_dpi_bridge_mode_valid Jitao Shi (3): drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid drm/mediatek: mtk_dpi: Add dpi config for mt8192 dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi .../display/mediatek/mediatek,dpi.yaml| 1 + drivers/gpu/drm/mediatek/mtk_dpi.c| 26 +++ 2 files changed, 27 insertions(+) -- 2.25.1
[PATCH v2 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..f6f71eb67ff1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,12 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
};
+static const struct mtk_dpi_conf mt8192_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .max_clock_khz = 15,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -837,6 +843,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
.data = &mt8183_conf,
},
+ { .compatible = "mediatek,mt8192-dpi",
+ .data = &mt8192_conf,
+ },
{ },
};
--
2.25.1
[PATCH v2 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+ u32 max_clock_khz;
bool edge_sel_en;
};
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge
*bridge)
mtk_dpi_set_display_mode(dpi, &dpi->mode);
}
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+ struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+ if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+ .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
};
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 30,
};
static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+ .max_clock_khz = 15,
};
static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 10,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.25.1
[PATCH v2 0/3] Add check for max clock rate in mode_valid
Changes since v1: - fix build err. Jitao Shi (3): drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid drm/mediatek: mtk_dpi: Add dpi config for mt8192 dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi .../display/mediatek/mediatek,dpi.yaml| 1 + drivers/gpu/drm/mediatek/mtk_dpi.c| 26 +++ 2 files changed, 27 insertions(+) -- 2.25.1
[PATCH v2 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi
Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi. Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6cdb734c91a9..2f566f19e6e0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi + - mediatek,mt8192-dpi reg: maxItems: 1 -- 2.25.1
[PATCH 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+ u32 max_clock_khz;
bool edge_sel_en;
};
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge
*bridge)
mtk_dpi_set_display_mode(dpi, &dpi->mode);
}
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+ struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+ if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+ .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
};
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 30,
};
static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+ .max_clock_khz = 15,
};
static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+ .max_clock_khz = 10,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.25.1
[PATCH 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..b7905f3f4d1b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,13 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
};
+static const struct mtk_dpi_conf mt8192_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .dual_edge = true,
+ .max_clock_khz = 15,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -837,6 +844,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
.data = &mt8183_conf,
},
+ { .compatible = "mediatek,mt8192-dpi",
+ .data = &mt8192_conf,
+ },
{ },
};
--
2.25.1
[PATCH 0/3] Add check for max clock rate in mode_valid
Jitao Shi (3): drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid drm/mediatek: mtk_dpi: Add dpi config for mt8192 dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi .../display/mediatek/mediatek,dpi.yaml| 1 + drivers/gpu/drm/mediatek/mtk_dpi.c| 27 +++ 2 files changed, 28 insertions(+) -- 2.25.1
[PATCH 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi
Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi. Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6cdb734c91a9..2f566f19e6e0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi + - mediatek,mt8192-dpi reg: maxItems: 1 -- 2.25.1
[PATCH] drm/mediatek: fine tune the data lane trail by project dts
Some panels or bridges require customized hs_da_trail time.
So add a property in devicetree for this panels and bridges.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 8c70ec39bfe1..6e7092fa2fee 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,7 @@ struct mtk_dsi {
struct clk *hs_clk;
u32 data_rate;
+ u32 da_trail_delta;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
timing->da_hs_prepare;
- timing->da_hs_trail = timing->da_hs_prepare + 1;
+ timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
timing->ta_go = 4 * timing->lpx - 2;
timing->ta_sure = timing->lpx + 2;
@@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
goto err_unregister_host;
}
+ ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
+&dsi->da_trail_delta);
+ if (ret) {
+ dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n",
ret);
+ dsi->da_trail_delta = 0;
+ }
+
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
--
2.12.5
[PATCH v2 0/2] Fix EoTp flag
Changes since v1: - Seperate the line time as single patch. Jitao Shi (2): drm/mediatek: dsi: Fix EoTp flag drm/mediatek: dsi: fine tune the line time cause by EOTp drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.12.5
[PATCH v2 1/2] drm/mediatek: dsi: Fix EoTp flag
SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 65fd99c528af..2bc46f2350f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -401,8 +401,11 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } - tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + tmp_reg |= HSTX_CKLP_EN; + + if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) + tmp_reg |= DIS_EOT; writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } -- 2.12.5
[PATCH v2 2/2] drm/mediatek: dsi: fine tune the line time cause by EOTp
Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 2bc46f2350f1..8c70ec39bfe1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -481,6 +481,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) timing->da_hs_zero + timing->da_hs_exit + 3; delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; + delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0; horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; -- 2.12.5
[PATCH v2 2/3] pwm: mtk_disp: convert the driver to atomic API
Switch the driver to atomic API apply().
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 114 +++--
1 file changed, 58 insertions(+), 56 deletions(-)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 21416a8b6b47..502228adf718 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -20,6 +20,7 @@
#define PWM_CLKDIV_SHIFT 16
#define PWM_CLKDIV_MAX 0x3ff
#define PWM_CLKDIV_MASK(PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
+#define PWM_POLARITY BIT(2)
#define PWM_PERIOD_BIT_WIDTH 12
#define PWM_PERIOD_MASK((1 << PWM_PERIOD_BIT_WIDTH) - 1)
@@ -47,6 +48,7 @@ struct mtk_disp_pwm {
struct clk *clk_main;
struct clk *clk_mm;
void __iomem *base;
+ bool enabled;
};
static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
@@ -66,11 +68,11 @@ static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm
*mdp, u32 offset,
writel(value, address);
}
-static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
- int duty_ns, int period_ns)
+static int mtk_disp_pwm_enable(struct pwm_chip *chip,
+ const struct pwm_state *state)
{
struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
- u32 clk_div, period, high_width, value;
+ u32 clk_div, period, high_width, value, polarity;
u64 div, rate;
int err;
@@ -84,33 +86,47 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip,
struct pwm_device *pwm,
* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
*/
+ if (!mdp->enabled) {
+ err = clk_prepare_enable(mdp->clk_main);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_main: %d\n",
+ err);
+ return err;
+ }
+ err = clk_prepare_enable(mdp->clk_mm);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_mm: %d\n",
+ err);
+ clk_disable_unprepare(mdp->clk_main);
+ return err;
+ }
+ }
rate = clk_get_rate(mdp->clk_main);
- clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
+ clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >>
PWM_PERIOD_BIT_WIDTH;
- if (clk_div > PWM_CLKDIV_MAX)
+ if (clk_div > PWM_CLKDIV_MAX) {
+ dev_err(chip->dev, "clock rate is too high: rate = %d Hz\n",
+ rate);
+ clk_disable_unprepare(mdp->clk_mm);
+ clk_disable_unprepare(mdp->clk_main);
return -EINVAL;
-
+ }
div = NSEC_PER_SEC * (clk_div + 1);
- period = div64_u64(rate * period_ns, div);
+ period = div64_u64(rate * state->period, div);
if (period > 0)
period--;
- high_width = div64_u64(rate * duty_ns, div);
+ high_width = div64_u64(rate * state->duty_cycle, div);
value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
-
- err = clk_enable(mdp->clk_main);
- if (err < 0)
- return err;
-
- err = clk_enable(mdp->clk_mm);
- if (err < 0) {
- clk_disable(mdp->clk_main);
- return err;
- }
+ polarity = 0;
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ polarity = PWM_POLARITY;
mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
PWM_CLKDIV_MASK,
clk_div << PWM_CLKDIV_SHIFT);
+ mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
+PWM_POLARITY, polarity);
mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
value);
@@ -122,50 +138,49 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip,
struct pwm_device *pwm,
mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
mdp->data->commit_mask,
0x0);
+ } else {
+ mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
+mdp->data->bls_debug_mask,
+mdp->data->bls_debug_mask);
+ mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
+mdp->data->con0_sel,
+
[PATCH v2 1/3] pwm: mtk_disp: clear the clock operations
Remove the clk_prepare from mtk_disp_pwm_probe.
Remove the clk_unprepare from mtk_disp_pwm_remove.
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 23 ++-
1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 87c6b4bc5d43..21416a8b6b47 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -192,14 +192,6 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev)
if (IS_ERR(mdp->clk_mm))
return PTR_ERR(mdp->clk_mm);
- ret = clk_prepare(mdp->clk_main);
- if (ret < 0)
- return ret;
-
- ret = clk_prepare(mdp->clk_mm);
- if (ret < 0)
- goto disable_clk_main;
-
mdp->chip.dev = &pdev->dev;
mdp->chip.ops = &mtk_disp_pwm_ops;
mdp->chip.base = -1;
@@ -208,7 +200,7 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&mdp->chip);
if (ret < 0) {
dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
- goto disable_clk_mm;
+ return ret;
}
platform_set_drvdata(pdev, mdp);
@@ -227,24 +219,13 @@ static int mtk_disp_pwm_probe(struct platform_device
*pdev)
}
return 0;
-
-disable_clk_mm:
- clk_unprepare(mdp->clk_mm);
-disable_clk_main:
- clk_unprepare(mdp->clk_main);
- return ret;
}
static int mtk_disp_pwm_remove(struct platform_device *pdev)
{
struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
- int ret;
-
- ret = pwmchip_remove(&mdp->chip);
- clk_unprepare(mdp->clk_mm);
- clk_unprepare(mdp->clk_main);
- return ret;
+ return pwmchip_remove(&mdp->chip);
}
static const struct mtk_pwm_data mt2701_pwm_data = {
--
2.12.5
[PATCH v2 3/3] pwm: mtk_disp: implement .get_state()
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 502228adf718..166e0a8ca703 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -179,8 +179,54 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip,
struct pwm_device *pwm,
return mtk_disp_pwm_enable(chip, state);
}
+static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
+ u32 clk_div, period, high_width, con0, con1;
+ u64 rate;
+ int err;
+
+ err = clk_prepare_enable(mdp->clk_main);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_main: %d\n", err);
+ return;
+ }
+ err = clk_prepare_enable(mdp->clk_mm);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_mm: %d\n", err);
+ clk_disable_unprepare(mdp->clk_main);
+ return;
+ }
+
+ rate = clk_get_rate(mdp->clk_main);
+
+ con0 = readl(mdp->base + mdp->data->con0);
+ con1 = readl(mdp->base + mdp->data->con1);
+
+ state->polarity = con0 & PWM_POLARITY ?
+ PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+ state->enabled = !!(con0 & BIT(0));
+
+ clk_div = (con0 & PWM_CLKDIV_MASK) >> PWM_CLKDIV_SHIFT;
+ period = con1 & PWM_PERIOD_MASK;
+ state->period = div_u64(period * (clk_div + 1) * NSEC_PER_SEC, rate);
+ high_width = (con1 & PWM_HIGH_WIDTH_MASK) >> PWM_HIGH_WIDTH_SHIFT;
+ state->duty_cycle = div_u64(high_width * (clk_div + 1) * NSEC_PER_SEC,
+ rate);
+
+ if (!state->enabled) {
+ clk_disable_unprepare(mdp->clk_mm);
+ clk_disable_unprepare(mdp->clk_main);
+ }
+
+ mdp->enabled = state->enabled;
+}
+
static const struct pwm_ops mtk_disp_pwm_ops = {
.apply = mtk_disp_pwm_apply,
+ .get_state = mtk_disp_pwm_get_state,
.owner = THIS_MODULE,
};
--
2.12.5
[PATCH v2 0/3] Convert the mtk_disp driver to aotmic API
Changes since v1: - Seperate clock operation as single patch. - Seperate apply() as single patch. - Seperate get_state() operation as single patch. Jitao Shi (3): pwm: mtk_disp: clear the clock operations pwm: mtk_disp: convert the driver to atomic API pwm: mtk_disp: implement .get_state() drivers/pwm/pwm-mtk-disp.c | 179 ++--- 1 file changed, 104 insertions(+), 75 deletions(-) -- 2.12.5
[PATCH] drm/mediatek: dsi: Fix EoTp flag
SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 65fd99c528af..8c70ec39bfe1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -401,8 +401,11 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) break; } - tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + tmp_reg |= HSTX_CKLP_EN; + + if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) + tmp_reg |= DIS_EOT; writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } @@ -478,6 +481,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) timing->da_hs_zero + timing->da_hs_exit + 3; delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; + delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0; horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; -- 2.25.1
[PATCH v5 1/1] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.
if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++---
1 file changed, 25 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80b7a082e874..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+ u32 delta;
struct mtk_phy_timing *timing = &dsi->phy_timing;
struct videomode *vm = &dsi->vm;
@@ -466,50 +467,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
+ horizontal_backporch_byte =
+ (vm->hback_porch * dsi_tmp_buf_bpp - 10);
else
- horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
- dsi_tmp_buf_bpp;
+ horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
+ dsi_tmp_buf_bpp - 10);
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit;
-
- if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 18) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
-
- horizontal_backporch_byte =
- horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ timing->da_hs_zero + timing->da_hs_exit + 3;
+
+ delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+ if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+ data_phy_cycles * dsi->lanes + delta) {
+ horizontal_frontporch_byte =
+ vm->hfront_porch * dsi_tmp_buf_bpp -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hfront_porch /
+ (vm->hfront_porch + vm->hback_porch);
+
+ horizontal_backporch_byte =
+ horizontal_backporch_byte -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hback_porch /
+ (vm->hfront_porch + vm->hback_porch);
} else {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 12) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
- horizontal_backporch_byte = horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+ horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
}
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
--
2.12.5
[PATCH v5 0/1] fix scrolling of panel with small hfp or hbp
Changes since v4: - Merge revert path and fixup patch to on patch Changes since v3: - Revert v2, for v2 will cause some bridge ic no output. the cause the video linetime doesn't match display mode from get mode. - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte are > 0. Jitao Shi (1): drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++--- 1 file changed, 25 insertions(+), 40 deletions(-) -- 2.12.5
Re: [v4 PATCH 0/2] fix scrolling of panel with small hfp or hbp
On Mon, 2020-10-12 at 23:22 +0800, Chun-Kuang Hu wrote: > Hi, Jitao: > > Jitao Shi 於 2020年10月10日 週六 下午3:09寫道： > > > > Changes since v3: > > - Revert v2, for v2 will cause some bridge ic no output. the cause > >the video linetime doesn't match display mode from get mode. > > - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte > >are > 0. > > Because v2 is merged into mainline, I think you should merge 1/2 and > 2/2 to one patch which fix the problem caused by v2. > > Regards, > Chun-Kuang. > Thanks for your reviewing. I'll update next version. Best Regards Jitao > > > > Jitao Shi (2): > > Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or > > hbp" > > drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp > > > > drivers/gpu/drm/mediatek/mtk_dsi.c | 65 > > +++--- > > 1 file changed, 25 insertions(+), 40 deletions(-) > > > > -- > > 2.12.5 > > ___ > > dri-devel mailing list > > dri-de...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 2/2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.
if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 54 ++
1 file changed, 19 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 16fd99dcdacf..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+ u32 delta;
struct mtk_phy_timing *timing = &dsi->phy_timing;
struct videomode *vm = &dsi->vm;
@@ -475,42 +476,25 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
timing->da_hs_zero + timing->da_hs_exit + 3;
- if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 18) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
-
- horizontal_backporch_byte =
- horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+ if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+ data_phy_cycles * dsi->lanes + delta) {
+ horizontal_frontporch_byte =
+ vm->hfront_porch * dsi_tmp_buf_bpp -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hfront_porch /
+ (vm->hfront_porch + vm->hback_porch);
+
+ horizontal_backporch_byte =
+ horizontal_backporch_byte -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hback_porch /
+ (vm->hfront_porch + vm->hback_porch);
} else {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 12) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
- horizontal_backporch_byte = horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+ horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
}
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
--
2.12.5
[PATCH v4 1/2] Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or hbp"
This reverts commit 35bf948f1edbf507f6e57e0879fa6ea36d2d2930.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80b7a082e874..16fd99dcdacf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -466,13 +466,14 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
+ horizontal_backporch_byte =
+ (vm->hback_porch * dsi_tmp_buf_bpp - 10);
else
- horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
- dsi_tmp_buf_bpp;
+ horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
+ dsi_tmp_buf_bpp - 10);
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit;
+ timing->da_hs_zero + timing->da_hs_exit + 3;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
--
2.12.5
[v4 PATCH 0/2] fix scrolling of panel with small hfp or hbp
Changes since v3: - Revert v2, for v2 will cause some bridge ic no output. the cause the video linetime doesn't match display mode from get mode. - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte are > 0. Jitao Shi (2): Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or hbp" drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++--- 1 file changed, 25 insertions(+), 40 deletions(-) -- 2.12.5
[v2 PATCH] dt-bindings: display: mediatek: convert the dpi bindings to yaml
Convert display/mediatek/mediatek,dpi.txt to display/mediatek/mediatek,dpi.yaml
and remove the old text bindings.
Signed-off-by: Jitao Shi
---
.../bindings/display/mediatek/mediatek,dpi.txt | 42 --
.../bindings/display/mediatek/mediatek,dpi.yaml| 97 ++
2 files changed, 97 insertions(+), 42 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
- compatible = "mediatek,mt8173-dpi";
- reg = <0 0x1401d000 0 0x1000>;
- interrupts = ;
- clocks = <&mmsys CLK_MM_DPI_PIXEL>,
-<&mmsys CLK_MM_DPI_ENGINE>,
-<&apmixedsys CLK_APMIXED_TVDPLL>;
- clock-names = "pixel", "engine", "pll";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dpi_pin_func>;
- pinctrl-1 = <&dpi_pin_idle>;
-
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&hdmi0_in>;
- };
- };
-};
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..4de08bc46fb3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The Mediatek DPI function block is a sink of the display subsystem and
+ provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+ output bus.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt2701-dpi
+ - mediatek,mt8173-dpi
+ - mediatek,mt8183-dpi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Pixel Clock
+ - description: Engine Clock
+ - description: DPI PLL
+
+ clock-names:
+items:
+ - const: pixel
+ - const: engine
+ - const: pll
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+items:
+ - const: default
+ - const: sleep
+
+ port:
+type: object
+description:
+ Output port node with endpoint definitions as described in
+ Documentation/devicetree/bindings/graph.txt. This port should be
connected
+ to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+ endpoint:
+type: object
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0x1401d000 0x1000>;
+interrupts = ;
+clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <&dpi_pin_func>;
+pinctrl-1 = <&dpi_pin_idle>;
+
+port {
+dpi0_out: endpoint {
+remote-endpoint = <&hdmi0_in>;
+};
+};
+};
+
+...
--
2.12.5
[v3 PATCH] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.
if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 54 ++
1 file changed, 19 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 16fd99dcdacf..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+ u32 delta;
struct mtk_phy_timing *timing = &dsi->phy_timing;
struct videomode *vm = &dsi->vm;
@@ -475,42 +476,25 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
timing->da_hs_zero + timing->da_hs_exit + 3;
- if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 18) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
-
- horizontal_backporch_byte =
- horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 18) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+ if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+ data_phy_cycles * dsi->lanes + delta) {
+ horizontal_frontporch_byte =
+ vm->hfront_porch * dsi_tmp_buf_bpp -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hfront_porch /
+ (vm->hfront_porch + vm->hback_porch);
+
+ horizontal_backporch_byte =
+ horizontal_backporch_byte -
+ (data_phy_cycles * dsi->lanes + delta) *
+ vm->hback_porch /
+ (vm->hfront_porch + vm->hback_porch);
} else {
- if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
- data_phy_cycles * dsi->lanes + 12) {
- horizontal_frontporch_byte =
- vm->hfront_porch * dsi_tmp_buf_bpp -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hfront_porch /
- (vm->hfront_porch + vm->hback_porch);
- horizontal_backporch_byte = horizontal_backporch_byte -
- (data_phy_cycles * dsi->lanes + 12) *
- vm->hback_porch /
- (vm->hfront_porch + vm->hback_porch);
- } else {
- DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
- horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
- }
+ DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+ horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
}
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
--
2.12.5
Re: [PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
On Tue, 2020-08-18 at 07:42 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
>
> Jitao Shi 於 2020年8月17日 週一 下午9:07寫道：
> >
> > horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
> > So remove the wrong subtraction 10.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
> > 1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 270bf22c98fe..5d031e634571 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> > *dsi)
> > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp -
> > 10);
>
> So this subtraction 10 is correct?
>
> Regards,
> Chun-Kuang.
>
Yes, It is right.
In the cea861 and dmt spec the mini hsync is 40 pixels.
So the vm->hsync_len * dsi_tmp_buf_bpp >= 120 > 10
Best Regards
jitao
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > - horizontal_backporch_byte =
> > - (vm->hback_porch * dsi_tmp_buf_bpp - 10);
> > + horizontal_backporch_byte = vm->hback_porch *
> > dsi_tmp_buf_bpp;
> > else
> > - horizontal_backporch_byte = ((vm->hback_porch +
> > vm->hsync_len) *
> > - dsi_tmp_buf_bpp - 10);
> > + horizontal_backporch_byte = (vm->hback_porch +
> > vm->hsync_len) *
> > + dsi_tmp_buf_bpp;
> >
> > data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > - timing->da_hs_zero + timing->da_hs_exit + 3;
> > + timing->da_hs_zero + timing->da_hs_exit;
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
> > --
> > 2.12.5
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
[PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
So remove the wrong subtraction 10.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 270bf22c98fe..5d031e634571 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- horizontal_backporch_byte =
- (vm->hback_porch * dsi_tmp_buf_bpp - 10);
+ horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
else
- horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
- dsi_tmp_buf_bpp - 10);
+ horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
+ dsi_tmp_buf_bpp;
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit + 3;
+ timing->da_hs_zero + timing->da_hs_exit;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
--
2.12.5
[PATCH] drm/panel: Fix auo,kd101n80-45na horizontal noise on edges of panel
Fine tune the HBP and HFP to avoid the dot noise on the left and right edges.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 48a164257d18..3edb33e61908 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -615,9 +615,9 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
.clock = 157000,
.hdisplay = 1200,
- .hsync_start = 1200 + 80,
- .hsync_end = 1200 + 80 + 24,
- .htotal = 1200 + 80 + 24 + 36,
+ .hsync_start = 1200 + 60,
+ .hsync_end = 1200 + 60 + 24,
+ .htotal = 1200 + 60 + 24 + 56,
.vdisplay = 1920,
.vsync_start = 1920 + 16,
.vsync_end = 1920 + 16 + 4,
--
2.25.1
[v2 PATCH] drm/panel: auo,b116xw03: fix flash backlight when power on
Delay the backlight on to make sure the video stable.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/panel/panel-simple.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 3ad828eaefe1..61781ffa7840 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -724,6 +724,7 @@ static const struct drm_display_mode auo_b116xw03_mode = {
.vsync_end = 768 + 10 + 12,
.vtotal = 768 + 10 + 12 + 6,
.vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};
static const struct panel_desc auo_b116xw03 = {
@@ -734,6 +735,12 @@ static const struct panel_desc auo_b116xw03 = {
.width = 256,
.height = 144,
},
+ .delay = {
+ .enable = 400,
+ },
+ .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ .connector_type = DRM_MODE_CONNECTOR_eDP,
};
static const struct drm_display_mode auo_b133xtn01_mode = {
--
2.25.1
Re: [PATCH] drm/panel: auo,b116xw03: fix flash backlight when power on
On Sun, 2020-07-05 at 10:06 +0200, Sam Ravnborg wrote:
> Hi Jitao.
>
> On Fri, Jul 03, 2020 at 05:51:13PM +0800, Jitao Shi wrote:
> > Delay the backlight on to make sure the video stable.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/panel/panel-simple.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
> > b/drivers/gpu/drm/panel/panel-simple.c
> > index 3ad828eaefe1..18f34f286d3d 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -734,6 +734,9 @@ static const struct panel_desc auo_b116xw03 = {
> > .width = 256,
> > .height = 144,
> > },
> > + .delay = {
> > + .enable = 400,
> > + },
> > };
> >
> > static const struct drm_display_mode auo_b133xtn01_mode = {
>
> Patch did not apply to drm-misc-next.
> Please update - and when you do so also add:
> .bus_flags
> .bus_format
> .connector_type
>
> So we have this panel properly defined.
>
> Sam
Thanks for your review.
I'll add those next version.
Jitao
[PATCH] drm/panel: auo,b116xw03: fix flash backlight when power on
Delay the backlight on to make sure the video stable.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/panel/panel-simple.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 3ad828eaefe1..18f34f286d3d 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -734,6 +734,9 @@ static const struct panel_desc auo_b116xw03 = {
.width = 256,
.height = 144,
},
+ .delay = {
+ .enable = 400,
+ },
};
static const struct drm_display_mode auo_b133xtn01_mode = {
--
2.25.1
[PATCH v16 0/1] mt8183 dpi support pin mode swap
Changes since v15: - Fix YAML License to (GPL-2.0-only OR BSD-2-Clause). - "dt-bindings: display: mediatek: control dpi pins mode to avoid leakage" "drm/mediatek: set dpi pin mode to gpio low to avoid leakage current" applied v15. The links are https://patchwork.kernel.org/patch/11489545/ https://patchwork.kernel.org/patch/11489577/ Changes since v14: - add "Acked-by" and "Reviewed-by" - change port@0 to port in yaml Changes since v13: - move dpi dual edge patches to another series because it will have long time to implement the dual edge change base boris patches. https://patchwork.kernel.org/cover/11354279/ Changes since v12: - fix mediatek,dpi.yaml make_dt_binding_check errors. Change since v11: - fine tune mediatek,dpi.yaml. - add Acked-by: Rob Herring . Change since v10: - convert the Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt to yaml format. - read the pclk-sample in endpoint. Changes since v9: - rename pinctrl-names = "gpiomode", "dpimode" to "active", "idle". - fix some typo. Changes since v8: - drop pclk-sample redefine in mediatek,dpi.txt - only get the gpiomode and dpimode when dpi->pinctrl is successful. Changes since v7: - separate dt-bindings to independent patches. - move dpi dual edge to one patch. Changes since v6: - change dual_edge to pclk-sample - remove dpi_pin_mode_swap and Changes since v5: - fine tune the dt-bindings commit message. Changes since v4: - move pin mode control and dual edge control to deveice tree. - update dt-bindings document for pin mode swap and dual edge control. Changes since v3: - add dpi pin mode control when dpi on or off. - update dpi dual edge comment. Changes since v2: - update dt-bindings document for mt8183 dpi. - separate dual edge modfication as independent patch. Jitao Shi (1): dt-bindings: display: mediatek: convert the dpi bindings to yaml .../display/mediatek/mediatek,dpi.txt | 42 .../display/mediatek/mediatek,dpi.yaml| 97 +++ 2 files changed, 97 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml -- 2.25.1
[PATCH v16 1/1] dt-bindings: display: mediatek: convert the dpi bindings to yaml
Convert display/mediatek/mediatek,dpi.txt to display/mediatek/mediatek,dpi.yaml
and remove the old text bindings.
Signed-off-by: Jitao Shi
---
.../display/mediatek/mediatek,dpi.txt | 42
.../display/mediatek/mediatek,dpi.yaml| 97 +++
2 files changed, 97 insertions(+), 42 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
- compatible = "mediatek,mt8173-dpi";
- reg = <0 0x1401d000 0 0x1000>;
- interrupts = ;
- clocks = <&mmsys CLK_MM_DPI_PIXEL>,
-<&mmsys CLK_MM_DPI_ENGINE>,
-<&apmixedsys CLK_APMIXED_TVDPLL>;
- clock-names = "pixel", "engine", "pll";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dpi_pin_func>;
- pinctrl-1 = <&dpi_pin_idle>;
-
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&hdmi0_in>;
- };
- };
-};
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..860b719b5dc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The Mediatek DPI function block is a sink of the display subsystem and
+ provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+ output bus.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt2701-dpi
+ - mediatek,mt8173-dpi
+ - mediatek,mt8183-dpi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Pixel Clock
+ - description: Engine Clock
+ - description: DPI PLL
+
+ clock-names:
+items:
+ - const: pixel
+ - const: engine
+ - const: pll
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+items:
+ - const: default
+ - const: sleep
+
+ port:
+type: object
+description:
+ Output port node with endpoint definitions as described in
+ Documentation/devicetree/bindings/graph.txt. This port should be
connected
+ to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+ endpoint:
+type: object
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0 0x1401d000 0 0x1000>;
+interrupts = ;
+clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <&dpi_pin_func>;
+pinctrl-1 = <&dpi_pin_idle>;
+
+port {
+dpi0_out: endpoint {
+remote-endpoint = <&hdmi0_in>;
+};
+};
+};
+
+...
--
2.25.1
[PATCH] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
If panel has too small hfp or hbp, horizontal_frontporch_byte or
horizontal_backporch_byte may become very small value or negative
value. This patch adjusts their values so that they are greater
than minimum value and keep total of them unchanged.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 0ede69830a9d..aebaafd90ceb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -148,6 +148,9 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
+#define MIN_HFP_BYTE 0x02
+#define MIN_HBP_BYTE 0x02
+
struct mtk_phy_timing {
u32 lpx;
u32 da_hs_prepare;
@@ -450,6 +453,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
+ s32 signed_hfp_byte, signed_hbp_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
struct mtk_phy_timing *timing = &dsi->phy_timing;
@@ -519,6 +523,20 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
}
}
+ signed_hfp_byte = (s32)horizontal_frontporch_byte;
+ signed_hbp_byte = (s32)horizontal_backporch_byte;
+
+ if (signed_hfp_byte + signed_hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
+ DRM_WARN("Calculated hfp_byte and hbp_byte are too small, "
+"panel may not work properly.\n");
+ } else if (signed_hfp_byte < MIN_HFP_BYTE) {
+ horizontal_frontporch_byte = MIN_HFP_BYTE;
+ horizontal_backporch_byte -= MIN_HFP_BYTE - signed_hfp_byte;
+ } else if (signed_hbp_byte < MIN_HBP_BYTE) {
+ horizontal_frontporch_byte -= MIN_HBP_BYTE - signed_hbp_byte;
+ horizontal_backporch_byte = MIN_HBP_BYTE;
+ }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
--
2.25.1
[PATCH v6 3/3] drm/mediatek: add mipi_tx driver for mt8183
This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 ++
4 files changed, 154 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
mtk_dsi.o \
mtk_mipi_tx.o \
mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 77b9a185e970..e4d34484ecc8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -175,6 +175,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
.data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
.data = &mt8173_mipitx_data },
+ { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
};
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 4f905313564f..413f35d86219 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -44,5 +44,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
extern const struct mtk_mipitx_data mt2701_mipitx_data;
extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..db13ebdbe262
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN BIT(0)
+#define RG_DSI_ANA_CK_SEL BIT(1)
+#define RG_DSI_PHY_CK_SEL BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN BIT(6)
+#define RG_DSI_BG_CORE_EN BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
+{
+ struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ unsigned int txdiv, txdiv0;
+ u64 pcw;
+
+ dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
+
+ if (mipi_tx->data_rate >= 20) {
+ txdiv = 1;
+ txdiv0 = 0;
+ } else if (mipi_tx->data_rate >= 10) {
+ txdiv = 2;
+ txdiv0 = 1;
+ } else if (mipi_tx->data_rate >= 5) {
+ txdiv = 4;
+ txdiv0 = 2;
+ } else if (mipi_tx->data_rate > 25000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ } else if (mipi_tx->data_rate >= 12500) {
+ txdiv = 16;
+ txdiv0 = 4;
+ } else {
+ return -EINVAL;
+ }
+
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+ mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+ udelay(1);
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+ pcw = div_u64(((u64)mipi_tx->data_rate * txdiv)
[v4 4/7] drm/mediatek: add frame size control
Our new DSI chip has frame size control.
So add the driver data to control for different chips.
Signed-off-by: Jitao Shi
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index eea47294079e..18a192656a89 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -162,6 +163,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -430,6 +432,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive, dsi->regs +
DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
--
2.21.0
[v4 6/7] drm/mediatek: change the dsi phytiming calculate method
Change the method of frame rate calc which can get more accurate
frame rate.
data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data
if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
bpp: bit per pixel
Signed-off-by: Jitao Shi
Tested-by: Ryan Case
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 122 -
1 file changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index abf6ddec5db6..558727c60ba3 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -144,12 +144,6 @@
#define DATA_0 (0xff << 16)
#define DATA_1 (0xff << 24)
-#define T_LPX 5
-#define T_HS_PREP 6
-#define T_HS_TRAIL 8
-#define T_HS_EXIT 7
-#define T_HS_ZERO 10
-
#define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
#define MTK_DSI_HOST_IS_READ(type) \
@@ -158,6 +152,25 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
+struct mtk_phy_timing {
+ u32 lpx;
+ u32 da_hs_prepare;
+ u32 da_hs_zero;
+ u32 da_hs_trail;
+
+ u32 ta_go;
+ u32 ta_sure;
+ u32 ta_get;
+ u32 da_hs_exit;
+
+ u32 clk_hs_zero;
+ u32 clk_hs_trail;
+
+ u32 clk_hs_prepare;
+ u32 clk_hs_post;
+ u32 clk_hs_exit;
+};
+
struct phy;
struct mtk_dsi_driver_data {
@@ -182,12 +195,13 @@ struct mtk_dsi {
struct clk *digital_clk;
struct clk *hs_clk;
- u32 data_rate;
+ u64 data_rate;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
unsigned int lanes;
struct videomode vm;
+ struct mtk_phy_timing phy_timing;
int refcount;
bool enabled;
u32 irq_data;
@@ -221,17 +235,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
+ struct mtk_phy_timing *timing = &dsi->phy_timing;
+
+ ui = 10 / dsi->data_rate;
+ cycle_time = 80 / dsi->data_rate;
+
+ timing->lpx = NS_TO_CYCLE(60, cycle_time);
+ timing->da_hs_prepare = NS_TO_CYCLE(40 + 5 * ui, cycle_time);
+ timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+ timing->da_hs_trail = NS_TO_CYCLE(80 + 4 * ui, cycle_time);
- ui = 1000 / dsi->data_rate + 0x01;
- cycle_time = 8000 / dsi->data_rate + 0x01;
+ timing->ta_go = 4 * timing->lpx;
+ timing->ta_sure = 3 * timing->lpx / 2;
+ timing->ta_get = 5 * timing->lpx;
+ timing->da_hs_exit = 2 * timing->lpx;
- timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
- timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
- timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+ timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+ timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+ timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+ timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+ timing->clk_hs_exit = 2 * timing->lpx;
+
+ timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+ timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+ timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+ timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -418,7 +451,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
- u32 dsi_tmp_buf_bpp;
+ u32 dsi_tmp_buf_bpp, data_phy_cycles;
+ struct mtk_phy_timing *timing = &dsi->phy_timing;
struct videomode *vm = &dsi->vm;
@@ -433,7 +467,8 @@ static void mtk_dsi_config_
[PATCH v1 1/2] drm/mediatek: separate mipi_tx to different file
Different IC has different mipi_tx setting of dsi. This patch separates the mipi_tx hardware relate part for mt8173. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 350 ++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 51 +++ drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 290 +++ 4 files changed, 377 insertions(+), 315 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 82ae49c64221..2c8de1f5a5ee 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_drm_plane.o \ mtk_dsi.o \ mtk_mipi_tx.o \ + mtk_mt8173_mipi_tx.o \ mtk_dpi.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 90e913108950..fa361c8be8d7 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -11,292 +11,45 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MIPITX_DSI_CON 0x00 -#define RG_DSI_LDOCORE_EN BIT(0) -#define RG_DSI_CKG_LDOOUT_EN BIT(1) -#define RG_DSI_BCLK_SEL(3 << 2) -#define RG_DSI_LD_IDX_SEL (7 << 4) -#define RG_DSI_PHYCLK_SEL (2 << 8) -#define RG_DSI_DSICLK_FREQ_SEL BIT(10) -#define RG_DSI_LPTX_CLMP_ENBIT(11) - -#define MIPITX_DSI_CLOCK_LANE 0x04 -#define MIPITX_DSI_DATA_LANE0 0x08 -#define MIPITX_DSI_DATA_LANE1 0x0c -#define MIPITX_DSI_DATA_LANE2 0x10 -#define MIPITX_DSI_DATA_LANE3 0x14 -#define RG_DSI_LNTx_LDOOUT_EN BIT(0) -#define RG_DSI_LNTx_CKLANE_EN BIT(1) -#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2) -#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3) -#define RG_DSI_LNTx_LPTX_IMINUSBIT(4) -#define RG_DSI_LNTx_LPCD_IPLUS BIT(5) -#define RG_DSI_LNTx_LPCD_IMINUSBIT(6) -#define RG_DSI_LNTx_RT_CODE(0xf << 8) - -#define MIPITX_DSI_TOP_CON 0x40 -#define RG_DSI_LNT_INTR_EN BIT(0) -#define RG_DSI_LNT_HS_BIAS_EN BIT(1) -#define RG_DSI_LNT_IMP_CAL_EN BIT(2) -#define RG_DSI_LNT_TESTMODE_EN BIT(3) -#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4) -#define RG_DSI_LNT_AIO_SEL (7 << 8) -#define RG_DSI_PAD_TIE_LOW_EN BIT(11) -#define RG_DSI_DEBUG_INPUT_EN BIT(12) -#define RG_DSI_PRESERVE(7 << 13) - -#define MIPITX_DSI_BG_CON 0x44 -#define RG_DSI_BG_CORE_EN BIT(0) -#define RG_DSI_BG_CKEN BIT(1) -#define RG_DSI_BG_DIV (0x3 << 2) -#define RG_DSI_BG_FAST_CHARGE BIT(4) -#define RG_DSI_VOUT_MSK(0x3 << 5) -#define RG_DSI_V12_SEL (7 << 5) -#define RG_DSI_V10_SEL (7 << 8) -#define RG_DSI_V072_SEL(7 << 11) -#define RG_DSI_V04_SEL (7 << 14) -#define RG_DSI_V032_SEL(7 << 17) -#define RG_DSI_V02_SEL (7 << 20) -#define RG_DSI_BG_R1_TRIM (0xf << 24) -#define RG_DSI_BG_R2_TRIM (0xf << 28) - -#define MIPITX_DSI_PLL_CON00x50 -#define RG_DSI_MPPLL_PLL_ENBIT(0) -#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1) -#define RG_DSI_MPPLL_PREDIV(3 << 1) -#define RG_DSI_MPPLL_TXDIV0(3 << 3) -#define RG_DSI_MPPLL_TXDIV1(3 << 5) -#define RG_DSI_MPPLL_POSDIV(7 << 7) -#define RG_DSI_MPPLL_MONVC_EN BIT(10) -#define RG_DSI_MPPLL_MONREF_EN BIT(11) -#define RG_DSI_MPPLL_VOD_ENBIT(12) - -#define MIPITX_DSI_PLL_CON10x54 -#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0) -#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) -#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2) -#define RG_DSI_MPPLL_SDM_SSC_PRD (0x << 16) - -#define MIPITX_DSI_PLL_CON20x58 - -#define MIPITX_DSI_PLL_TOP 0x64 -#define RG_DSI_MPPLL_PRESERVE (0xff << 8) - -#define MIPITX_DSI_PLL_PWR 0x68 -#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0) -#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1) -#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) - -#define MIPITX_DSI_SW_CTRL 0x80 -#define SW_CTRL_EN BIT(0) - -#define MIPITX_DSI_SW_CTRL_CON00x84 -#define SW_LNTC_LPTX_PRE_OE
[PATCH v1 2/2] drm/mediatek: add mipi_tx driver for mt8183
This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 168 ++
3 files changed, 171 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index fa361c8be8d7..83fb7717d383 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -198,6 +198,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
.data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
.data = &mt8173_mipitx_data },
+ { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
};
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 2d7f05b0d6a7..af83023e81cf 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -47,5 +47,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
extern const struct mtk_mipitx_data mt2701_mipitx_data;
extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..07f70a3cad13
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN BIT(0)
+#define RG_DSI_ANA_CK_SEL BIT(1)
+#define RG_DSI_PHY_CK_SEL BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN BIT(6)
+#define RG_DSI_BG_CORE_EN BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
+{
+ struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ unsigned int txdiv, txdiv0, txdiv1;
+ u64 pcw;
+ int ret;
+
+ dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
+
+ if (mipi_tx->data_rate >= 20) {
+ txdiv = 1;
+ txdiv0 = 0;
+ txdiv1 = 0;
+ } else if (mipi_tx->data_rate >= 10) {
+ txdiv = 2;
+ txdiv0 = 1;
+ txdiv1 = 0;
+ } else if (mipi_tx->data_rate >= 5) {
+ txdiv = 4;
+ txdiv0 = 2;
+ txdiv1 = 0;
+ } else if (mipi_tx->data_rate > 25000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ txdiv1 = 0;
+ } else if (mipi_tx->data_rate >= 12500) {
+ txdiv = 16;
+ txdiv0 = 4;
+ txdiv1 = 0;
+ } else {
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(mipi_tx->ref_clk);
+ if (ret < 0) {
+ dev_err(mipi_tx->dev, "can't mipi_tx ref_clk %d\n", ret);
+ return ret;
+ }
+
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+ mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ usleep_range(30, 100);
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_
[PATCH v1 0/2] drm/mediatek: add mipi_tx driver for mt8183
MT8183 has different setting to MT8173(exist chip). We add mt8183 mipi_tx driver. 1) Separate mipi_tx to common part and chip relate part. 2) Add mt8183 mipi_tx driver Changes since v0: - Separate two independent patches. Jitao Shi (2): drm/mediatek: separate mipi_tx to different file drm/mediatek: add mipi_tx driver for mt8183 drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 352 ++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 52 +++ drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 290 +++ drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 168 + 5 files changed, 548 insertions(+), 315 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c -- 2.20.1
[v2 1/1] drm/mediatek: add mt8183 dpi support
MT8183 samples on rising and falling edge. It can reduce half data
io.
MT8173 also has those registers. But the hw function is removed.
So MT8173 doesn't support DPI dual edge sample and can't use the
same setting to mt8183.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 62a9d47df948..610c23334047 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -117,6 +117,7 @@ struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
bool edge_sel_en;
+ bool dual_edge;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
*dpi)
mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
}
+static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
+}
+
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)
{
@@ -509,6 +517,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
mtk_dpi_config_disable_edge(dpi);
+ if (dpi->conf->dual_edge)
+ mtk_dpi_enable_dual_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -671,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
return 2;
}
+static unsigned int mt8183_calculate_factor(int clock)
+{
+ if (clock <= 27000)
+ return 8;
+ else if (clock <= 167000)
+ return 4;
+ else
+ return 2;
+}
+
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
@@ -682,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
.edge_sel_en = true,
};
+static const struct mtk_dpi_conf mt8183_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .dual_edge = true,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -777,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,
},
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = &mt8183_conf,
+ },
{ },
};
--
2.20.1
Re: [PATCH] drm/mediatek: add mt8183 dpi support
On Fri, 2019-02-15 at 00:13 +0800, CK Hu wrote:
> Hi, Jitao:
>
> On Mon, 2019-02-11 at 12:50 +0800, Jitao Shi wrote:
> > MT8183 sample on rising and falling edge. It can reduce half data io.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 62a9d47df948..610c23334047 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -117,6 +117,7 @@ struct mtk_dpi_conf {
> > unsigned int (*cal_factor)(int clock);
> > u32 reg_h_fre_con;
> > bool edge_sel_en;
> > + bool dual_edge;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32
> > mask)
> > @@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
> > *dpi)
> > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> > }
> >
> > +static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
> > +{
> > + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> > +DDR_EN | DDR_4PHASE);
> > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
> > +}
>
> All these register exist in MT8173, if you do the same setting in
> MT8173, could it also sample on rising edge and falling edge?
>
> Regards,
> CK
Hi CK,
MT8173 has those registers. But the hw function is removed.
So MT8173 doesn't support DPI dual edge sample.
Best Regards
Jitao
>
> > +
> > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> > enum mtk_dpi_out_color_format format)
> > {
> > @@ -509,6 +517,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > mtk_dpi_config_color_format(dpi, dpi->color_format);
> > mtk_dpi_config_2n_h_fre(dpi);
> > mtk_dpi_config_disable_edge(dpi);
> > + if (dpi->conf->dual_edge)
> > + mtk_dpi_enable_dual_edge(dpi);
> > mtk_dpi_sw_reset(dpi, false);
> >
> > return 0;
> > @@ -671,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
> > return 2;
> > }
> >
> > +static unsigned int mt8183_calculate_factor(int clock)
> > +{
> > + if (clock <= 27000)
> > + return 8;
> > + else if (clock <= 167000)
> > + return 4;
> > + else
> > + return 2;
> > +}
> > +
> > static const struct mtk_dpi_conf mt8173_conf = {
> > .cal_factor = mt8173_calculate_factor,
> > .reg_h_fre_con = 0xe0,
> > @@ -682,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
> > .edge_sel_en = true,
> > };
> >
> > +static const struct mtk_dpi_conf mt8183_conf = {
> > + .cal_factor = mt8183_calculate_factor,
> > + .reg_h_fre_con = 0xe0,
> > + .dual_edge = true,
> > +};
> > +
> > static int mtk_dpi_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -777,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
> > { .compatible = "mediatek,mt8173-dpi",
> > .data = &mt8173_conf,
> > },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = &mt8183_conf,
> > + },
> > { },
> > };
> >
>
>
Re: [PATCH] drm/mediatek: add mt8183 dpi support
On Fri, 2019-02-15 at 00:13 +0800, CK Hu wrote:
> Hi, Jitao:
>
> On Mon, 2019-02-11 at 12:50 +0800, Jitao Shi wrote:
> > MT8183 sample on rising and falling edge. It can reduce half data io.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 62a9d47df948..610c23334047 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -117,6 +117,7 @@ struct mtk_dpi_conf {
> > unsigned int (*cal_factor)(int clock);
> > u32 reg_h_fre_con;
> > bool edge_sel_en;
> > + bool dual_edge;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32
> > mask)
> > @@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
> > *dpi)
> > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> > }
> >
> > +static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
> > +{
> > + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> > +DDR_EN | DDR_4PHASE);
> > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
> > +}
>
> All these register exist in MT8173, if you do the same setting in
> MT8173, could it also sample on rising edge and falling edge?
>
> Regards,
> CK
>
I'll fix is next version.
Thanks for your review.
Best Regards.
Jitao
> > +
> > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> > enum mtk_dpi_out_color_format format)
> > {
> > @@ -509,6 +517,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > mtk_dpi_config_color_format(dpi, dpi->color_format);
> > mtk_dpi_config_2n_h_fre(dpi);
> > mtk_dpi_config_disable_edge(dpi);
> > + if (dpi->conf->dual_edge)
> > + mtk_dpi_enable_dual_edge(dpi);
> > mtk_dpi_sw_reset(dpi, false);
> >
> > return 0;
> > @@ -671,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
> > return 2;
> > }
> >
> > +static unsigned int mt8183_calculate_factor(int clock)
> > +{
> > + if (clock <= 27000)
> > + return 8;
> > + else if (clock <= 167000)
> > + return 4;
> > + else
> > + return 2;
> > +}
> > +
> > static const struct mtk_dpi_conf mt8173_conf = {
> > .cal_factor = mt8173_calculate_factor,
> > .reg_h_fre_con = 0xe0,
> > @@ -682,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
> > .edge_sel_en = true,
> > };
> >
> > +static const struct mtk_dpi_conf mt8183_conf = {
> > + .cal_factor = mt8183_calculate_factor,
> > + .reg_h_fre_con = 0xe0,
> > + .dual_edge = true,
> > +};
> > +
> > static int mtk_dpi_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -777,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
> > { .compatible = "mediatek,mt8173-dpi",
> > .data = &mt8173_conf,
> > },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = &mt8183_conf,
> > + },
> > { },
> > };
> >
>
>
Re: [PATCH] drm/mediatek: add mt8183 dpi support
On Thu, 2019-02-14 at 15:41 -0500, Sean Paul wrote:
> On Mon, Feb 11, 2019 at 12:50:59PM +0800, Jitao Shi wrote:
> > MT8183 sample on rising and falling edge. It can reduce half data io.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 62a9d47df948..610c23334047 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -117,6 +117,7 @@ struct mtk_dpi_conf {
> > unsigned int (*cal_factor)(int clock);
> > u32 reg_h_fre_con;
> > bool edge_sel_en;
> > + bool dual_edge;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32
> > mask)
> > @@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
> > *dpi)
> > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> > }
> >
> > +static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
> > +{
> > + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> > +DDR_EN | DDR_4PHASE);
> > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
> > +}
> > +
> > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> > enum mtk_dpi_out_color_format format)
> > {
> > @@ -509,6 +517,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > mtk_dpi_config_color_format(dpi, dpi->color_format);
> > mtk_dpi_config_2n_h_fre(dpi);
> > mtk_dpi_config_disable_edge(dpi);
> > + if (dpi->conf->dual_edge)
> > + mtk_dpi_enable_dual_edge(dpi);
> > mtk_dpi_sw_reset(dpi, false);
> >
> > return 0;
> > @@ -671,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
> > return 2;
> > }
> >
> > +static unsigned int mt8183_calculate_factor(int clock)
> > +{
> > + if (clock <= 27000)
> > + return 8;
> > + else if (clock <= 167000)
> > + return 4;
> > + else
> > + return 2;
> > +}
> > +
> > static const struct mtk_dpi_conf mt8173_conf = {
> > .cal_factor = mt8173_calculate_factor,
> > .reg_h_fre_con = 0xe0,
> > @@ -682,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
> > .edge_sel_en = true,
> > };
> >
> > +static const struct mtk_dpi_conf mt8183_conf = {
> > + .cal_factor = mt8183_calculate_factor,
> > + .reg_h_fre_con = 0xe0,
> > + .dual_edge = true,
> > +};
> > +
> > static int mtk_dpi_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -777,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
> > { .compatible = "mediatek,mt8173-dpi",
> > .data = &mt8173_conf,
> > },
> > + { .compatible = "mediatek,mt8183-dpi",
>
> Do you need to add this compatible value to the dt binding? If you can do as
> CK
> suggested, maybe you don't need this at all (and mt8183 can use the mt8173
> compatible string in the dt).
>
> Sean
>
Yes, CK is right.
I'll move it to mt8173.
> > + .data = &mt8183_conf,
> > + },
> > { },
> > };
> >
> > --
> > 2.12.5
> >
>
Re: [PATCH 2/3] drm/mediatek: CMDQ reg address of mt8173 is different with mt2701
On Thu, 2019-02-14 at 13:48 +0800, Nicolas Boichat wrote:
> On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
> >
> > Config the different CMDQ reg address in driver data.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 39 --
> > 1 file changed, 31 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 93fa255b4aad..80db02a25cb0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -156,6 +156,10 @@
> >
> > struct phy;
> >
> > +struct mtk_dsi_driver_data {
> > + const u32 reg_cmdq_off;
> > +};
> > +
> > struct mtk_dsi {
> > struct mtk_ddp_comp ddp_comp;
> > struct device *dev;
> > @@ -182,6 +186,7 @@ struct mtk_dsi {
> > bool enabled;
> > u32 irq_data;
> > wait_queue_head_t irq_wait_queue;
> > + struct mtk_dsi_driver_data *driver_data;
> > };
> >
> > static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
> > @@ -934,6 +939,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const
> > struct mipi_dsi_msg *msg)
> > const char *tx_buf = msg->tx_buf;
> > u8 config, cmdq_size, cmdq_off, type = msg->type;
> > u32 reg_val, cmdq_mask, i;
> > + u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
> >
> > if (MTK_DSI_HOST_IS_READ(type))
> > config = BTA;
> > @@ -953,9 +959,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const
> > struct mipi_dsi_msg *msg)
> > }
> >
> > for (i = 0; i < msg->tx_len; i++)
> > - writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
> > + mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
> > +(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
> > +tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
>
> I found the writeb call _much_ clearer ... Either switch back to that,
> or create a new mtk_disk_mask_byte function maybe?
I'll fix it next version.
>
> >
> > - mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
> > + mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
>
> You're removing DSI_CMDQ0 usage in this patch, so remove the #define
> in this patch too (instead of doing that in 3/3).
I'll fix it next version.
>
> > mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> > }
> >
> > @@ -1074,10 +1082,27 @@ static const struct component_ops
> > mtk_dsi_component_ops = {
> > .unbind = mtk_dsi_unbind,
> > };
> >
> > +static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
> > + .reg_cmdq_off = 0x200,
> > +};
> > +
> > +static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
> > + .reg_cmdq_off = 0x180,
> > +};
> > +
> > +static const struct of_device_id mtk_dsi_of_match[] = {
> > + { .compatible = "mediatek,mt2701-dsi",
> > + .data = &mt2701_dsi_driver_data },
> > + { .compatible = "mediatek,mt8173-dsi",
> > + .data = &mt8173_dsi_driver_data },
> > + { },
> > +};
> > +
> > static int mtk_dsi_probe(struct platform_device *pdev)
> > {
> > struct mtk_dsi *dsi;
> > struct device *dev = &pdev->dev;
> > + const struct of_device_id *of_id;
> > struct resource *regs;
> > int irq_num;
> > int comp_id;
> > @@ -1101,6 +1126,10 @@ static int mtk_dsi_probe(struct platform_device
> > *pdev)
> > if (ret)
> > goto err_unregister_host;
> >
> > + of_id = of_match_device(mtk_dsi_of_match, &pdev->dev);
> > + dsi->driver_data = (struct mtk_dsi_driver_data *)
> > + of_id->data;
>
> This fits in 80 chars. Also, of_id->data is a void*, so no cast needed.
I'll fix it next version.
>
> > +
> > dsi->engine_clk = devm_clk_get(dev, "engine");
> > if (IS_ERR(dsi->engine_clk)) {
> > ret = PTR_ERR(dsi->engine_clk);
> > @@ -1194,12 +1223,6 @@ static int mtk_dsi_remove(struct platform_device
> > *pdev)
> > return 0;
> > }
> >
> > -static const struct of_device_id mtk_dsi_of_match[] = {
> > - { .compatible = "mediatek,mt2701-dsi" },
> > - { .compatible = "mediatek,mt8173-dsi" },
> > - { },
> > -};
>
> Any reason you moved this up?
of_match_device is called by mtk_dsi_probe.
Best regards
Jitao
>
> > -
> > struct platform_driver mtk_dsi_driver = {
> > .probe = mtk_dsi_probe,
> > .remove = mtk_dsi_remove,
> > --
> > 2.20.1
> >
Re: [PATCH 1/3] drm/mediatek: move mipi_dsi_host_register to probe
On Thu, 2019-02-14 at 14:02 +0800, Nicolas Boichat wrote:
> Just some comments on the error path, I'm not sure about the change itself.
>
> On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
> >
> > DSI panel driver need attach function which is inculde in
> > mipi_dsi_host_ops.
> >
> > If mipi_dsi_host_register is not in probe, dsi panel will
> > probe fail or more delay.
> >
> > So move the mipi_dsi_host_register to probe from bind.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 49 ++
> > 1 file changed, 30 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 27b507eb4a99..93fa255b4aad 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > device *master, void *data)
> > return ret;
> > }
> >
> > - ret = mipi_dsi_host_register(&dsi->host);
> > - if (ret < 0) {
> > - dev_err(dev, "failed to register DSI host: %d\n", ret);
> > - goto err_ddp_comp_unregister;
> > - }
> > -
> > ret = mtk_dsi_create_conn_enc(drm, dsi);
> > if (ret) {
> > DRM_ERROR("Encoder create failed with %d\n", ret);
> > @@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > device *master, void *data)
> > return 0;
> >
> > err_unregister:
> > - mipi_dsi_host_unregister(&dsi->host);
> > -err_ddp_comp_unregister:
> > mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
> > return ret;
> > }
> > @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device
> > *pdev)
> >
> > dsi->host.ops = &mtk_dsi_ops;
> > dsi->host.dev = dev;
> > + dsi->dev = dev;
> > + ret = mipi_dsi_host_register(&dsi->host);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to register DSI host: %d\n", ret);
> > + return -EPROBE_DEFER;
>
> return ret
>
Ok, I'll fix it next version.
> > + }
> >
> > ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> > &dsi->panel, &dsi->bridge);
> > if (ret)
> > - return ret;
> > + goto err_unregister_host;
> >
> > dsi->engine_clk = devm_clk_get(dev, "engine");
> > if (IS_ERR(dsi->engine_clk)) {
> > ret = PTR_ERR(dsi->engine_clk);
> > dev_err(dev, "Failed to get engine clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->digital_clk = devm_clk_get(dev, "digital");
> > if (IS_ERR(dsi->digital_clk)) {
> > ret = PTR_ERR(dsi->digital_clk);
> > dev_err(dev, "Failed to get digital clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->hs_clk = devm_clk_get(dev, "hs");
> > if (IS_ERR(dsi->hs_clk)) {
> > ret = PTR_ERR(dsi->hs_clk);
> > dev_err(dev, "Failed to get hs clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > @@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device
> > *pdev)
> > if (IS_ERR(dsi->regs)) {
> > ret = PTR_ERR(dsi->regs);
> > dev_err(dev, "Failed to ioremap memory: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->phy = devm_phy_get(dev, "dphy");
> > if (IS_ERR(dsi->phy)) {
> > ret = PTR_ERR(dsi->phy);
> > dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > comp_id = mtk_ddp_comp_get_i
Re: [PATCH 3/3] drm/mediatek: add mt8183 dsi driver support
On Thu, 2019-02-14 at 13:54 +0800, Nicolas Boichat wrote:
> On Thu, Feb 14, 2019 at 12:43 PM Jitao Shi wrote:
> >
> > MT8183 dsi has two changes with mt8173.
> > 1. Add the register double buffer control, but we no need it, So make
> >it default off.
>
> Can you describe a little bit more what this is about? That's shadow
> registers, right?
>
Yes, it is shadow registers.
Jitao
> > 2. Add picture size control.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++-
> > 1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 80db02a25cb0..20cb53f05d42 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -78,6 +78,7 @@
> > #define DSI_VBP_NL 0x24
> > #define DSI_VFP_NL 0x28
> > #define DSI_VACT_NL0x2C
> > +#define DSI_SIZE_CON 0x38
> > #define DSI_HSA_WC 0x50
> > #define DSI_HBP_WC 0x54
> > #define DSI_HFP_WC 0x58
> > @@ -131,7 +132,10 @@
> > #define VM_CMD_EN BIT(0)
> > #define TS_VFP_EN BIT(5)
> >
> > -#define DSI_CMDQ0 0x180
>
> As I said earlier, move this to 2/3.
>
Thank for you review.
I'll move it to 2/3 next version.
Best Regards
Jitao
> > +#define DSI_SHADOW_DEBUG 0x190U
> > +#define FORCE_COMMIT BIT(0)
> > +#define BYPASS_SHADOW BIT(1)
> > +
> > #define CONFIG (0xff << 0)
> > #define SHORT_PACKET 0
> > #define LONG_PACKET2
> > @@ -158,6 +162,7 @@ struct phy;
> >
> > struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > + bool has_size_ctl;
> > };
> >
> > struct mtk_dsi {
> > @@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> > *dsi)
> > writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
> > writel(vm->vactive, dsi->regs + DSI_VACT_NL);
> >
> > + if (dsi->driver_data->has_size_ctl)
> > + writel(vm->vactive << 16 | vm->hactive, dsi->regs +
> > DSI_SIZE_CON);
> > +
> > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp -
> > 10);
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > @@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > }
> >
> > mtk_dsi_enable(dsi);
> > +
> > + /* DSI no need this double buffer, disable it when writing register
> > */
>
> "DSI does not need double buffering, disable it when writing register"
>
I'll fix it next version.
> > + writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG);
>
> So you do this on all MT* variants, is that ok?
>
> > mtk_dsi_reset_engine(dsi);
> > mtk_dsi_phy_timconfig(dsi);
> >
> > @@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data
> > mt2701_dsi_driver_data = {
> > .reg_cmdq_off = 0x180,
> > };
> >
> > +static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
> > + .reg_cmdq_off = 0x200,
> > + .has_size_ctl = true,
> > +};
> > +
> > static const struct of_device_id mtk_dsi_of_match[] = {
> > { .compatible = "mediatek,mt2701-dsi",
> > .data = &mt2701_dsi_driver_data },
> > { .compatible = "mediatek,mt8173-dsi",
> > .data = &mt8173_dsi_driver_data },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = &mt8183_dsi_driver_data },
> > { },
> > };
> >
> > --
> > 2.20.1
> >
Re: [PATCH 3/3] drm/mediatek: add mt8183 dsi driver support
On Thu, 2019-02-14 at 10:54 +0100, Matthias Brugger wrote:
>
> On 14/02/2019 05:42, Jitao Shi wrote:
> > MT8183 dsi has two changes with mt8173.
> > 1. Add the register double buffer control, but we no need it, So make
> >it default off.
> > 2. Add picture size control.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++-
> > 1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 80db02a25cb0..20cb53f05d42 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -78,6 +78,7 @@
> > #define DSI_VBP_NL 0x24
> > #define DSI_VFP_NL 0x28
> > #define DSI_VACT_NL0x2C
> > +#define DSI_SIZE_CON 0x38
> > #define DSI_HSA_WC 0x50
> > #define DSI_HBP_WC 0x54
> > #define DSI_HFP_WC 0x58
> > @@ -131,7 +132,10 @@
> > #define VM_CMD_EN BIT(0)
> > #define TS_VFP_EN BIT(5)
> >
> > -#define DSI_CMDQ0 0x180
> > +#define DSI_SHADOW_DEBUG 0x190U
> > +#define FORCE_COMMIT BIT(0)
> > +#define BYPASS_SHADOW BIT(1)
> > +
> > #define CONFIG (0xff << 0)
> > #define SHORT_PACKET 0
> > #define LONG_PACKET2
> > @@ -158,6 +162,7 @@ struct phy;
> >
> > struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > + bool has_size_ctl;
> > };
> >
> > struct mtk_dsi {
> > @@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> > *dsi)
> > writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
> > writel(vm->vactive, dsi->regs + DSI_VACT_NL);
> >
> > + if (dsi->driver_data->has_size_ctl)
> > + writel(vm->vactive << 16 | vm->hactive, dsi->regs +
> > DSI_SIZE_CON);
> > +
> > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > @@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > }
> >
> > mtk_dsi_enable(dsi);
> > +
> > + /* DSI no need this double buffer, disable it when writing register */
> > + writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG);
>
> Is this a mt8183 thing? Did you assure that this does not introduce
> regressions
> on other SoCs, or does it fix any?
>
> I think this should be a independent patch. If it fixes an actual issue, then
> please provide a fixes tag in that patch.
>
> Thanks,
> Matthias
>
Yes, this is for mt8183. But this reg is reverse on other mtk soc.
It is unsuitable. And i'll put it in mt8183 driver data next version.
Best Regards
Jitao
> > mtk_dsi_reset_engine(dsi);
> > mtk_dsi_phy_timconfig(dsi);
> >
> > @@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data
> > mt2701_dsi_driver_data = {
> > .reg_cmdq_off = 0x180,
> > };
> >
> > +static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
> > + .reg_cmdq_off = 0x200,
> > + .has_size_ctl = true,
> > +};
> > +
> > static const struct of_device_id mtk_dsi_of_match[] = {
> > { .compatible = "mediatek,mt2701-dsi",
> > .data = &mt2701_dsi_driver_data },
> > { .compatible = "mediatek,mt8173-dsi",
> > .data = &mt8173_dsi_driver_data },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = &mt8183_dsi_driver_data },
> > { },
> > };
> >
> >
Re: [PATCH 1/3] drm/mediatek: move mipi_dsi_host_register to probe
On Thu, 2019-02-14 at 15:48 -0500, Sean Paul wrote:
> On Thu, Feb 14, 2019 at 12:42:41PM +0800, Jitao Shi wrote:
> > DSI panel driver need attach function which is inculde in
> > mipi_dsi_host_ops.
>
> Which function is required from dsi_host?
>
> Sean
>
mipi_dsi_attach request the mipi_dsi_host_register ready.
for example.
mipi_dsi_attach is called by panel_simple_dsi_probe.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/panel/panel-simple.c?h=v5.0-rc6#n2987
jitao
> >
> > If mipi_dsi_host_register is not in probe, dsi panel will
> > probe fail or more delay.
> >
> > So move the mipi_dsi_host_register to probe from bind.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 49 ++
> > 1 file changed, 30 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 27b507eb4a99..93fa255b4aad 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > device *master, void *data)
> > return ret;
> > }
> >
> > - ret = mipi_dsi_host_register(&dsi->host);
> > - if (ret < 0) {
> > - dev_err(dev, "failed to register DSI host: %d\n", ret);
> > - goto err_ddp_comp_unregister;
> > - }
> > -
> > ret = mtk_dsi_create_conn_enc(drm, dsi);
> > if (ret) {
> > DRM_ERROR("Encoder create failed with %d\n", ret);
> > @@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > device *master, void *data)
> > return 0;
> >
> > err_unregister:
> > - mipi_dsi_host_unregister(&dsi->host);
> > -err_ddp_comp_unregister:
> > mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
> > return ret;
> > }
> > @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device
> > *pdev)
> >
> > dsi->host.ops = &mtk_dsi_ops;
> > dsi->host.dev = dev;
> > + dsi->dev = dev;
> > + ret = mipi_dsi_host_register(&dsi->host);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to register DSI host: %d\n", ret);
> > + return -EPROBE_DEFER;
> > + }
> >
> > ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> > &dsi->panel, &dsi->bridge);
> > if (ret)
> > - return ret;
> > + goto err_unregister_host;
> >
> > dsi->engine_clk = devm_clk_get(dev, "engine");
> > if (IS_ERR(dsi->engine_clk)) {
> > ret = PTR_ERR(dsi->engine_clk);
> > dev_err(dev, "Failed to get engine clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->digital_clk = devm_clk_get(dev, "digital");
> > if (IS_ERR(dsi->digital_clk)) {
> > ret = PTR_ERR(dsi->digital_clk);
> > dev_err(dev, "Failed to get digital clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->hs_clk = devm_clk_get(dev, "hs");
> > if (IS_ERR(dsi->hs_clk)) {
> > ret = PTR_ERR(dsi->hs_clk);
> > dev_err(dev, "Failed to get hs clock: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > @@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device
> > *pdev)
> > if (IS_ERR(dsi->regs)) {
> > ret = PTR_ERR(dsi->regs);
> > dev_err(dev, "Failed to ioremap memory: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > dsi->phy = devm_phy_get(dev, "dphy");
> > if (IS_ERR(dsi->phy)) {
> > ret = PTR_ERR(dsi->phy);
> > dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
> > - return ret;
> > + goto err_unregister_host;
> > }
> >
> > comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
> > if (co
Re: [PATCH] drm/mediatek: add mipi_tx driver for mt8183
On Tue, 2019-02-12 at 10:28 +0100, Matthias Brugger wrote: > > On 12/02/2019 07:19, Jitao Shi wrote: > > This patch adds mipi tx driver support for mt8183. > > > > Mipi_tx of mt8183 is very different to mt8173. > > 1.Separate mipi tx setting to mtk_mt8173_mipi_tx.c for mt8173 > > 2.Separate mipi tx setting to mtk_mt8183_mipi_tx.c for mt8183 > > 3.To reuse the common code, make the common functions in mtk_mipi_tx.c > > > > I hadn't a look on the code, but this commit message already indicates, that > you > should split this up in several patches. > Something like this: > 1. patch: carve out common functions to mtk_mipi_tx.c at this point only used > by > mt8173 > 2. patch: add support for mt8183 > > Regards, > Matthias > Thanks for your advice. I'll split it to several patches. Best Regards Jitao > > Signed-off-by: Jitao Shi > > --- > > drivers/gpu/drm/mediatek/Makefile | 2 + > > drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 352 ++ > > drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 52 +++ > > drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 290 +++ > > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 168 + > > 5 files changed, 549 insertions(+), 315 deletions(-) > > create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h > > create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c > > create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > > > diff --git a/drivers/gpu/drm/mediatek/Makefile > > b/drivers/gpu/drm/mediatek/Makefile > > index 82ae49c64221..8067a4be8311 100644 > > --- a/drivers/gpu/drm/mediatek/Makefile > > +++ b/drivers/gpu/drm/mediatek/Makefile > > @@ -12,6 +12,8 @@ mediatek-drm-y := mtk_disp_color.o \ > > mtk_drm_plane.o \ > > mtk_dsi.o \ > > mtk_mipi_tx.o \ > > + mtk_mt8173_mipi_tx.o \ > > + mtk_mt8183_mipi_tx.o \ > > mtk_dpi.o > > > > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o > > diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > > b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > > index 90e913108950..7591a38ca565 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > > +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c > > @@ -11,292 +11,45 @@ > > * GNU General Public License for more details. > > */ > > > > -#include > > -#include > > -#include > > -#include > > -#include > > -#include > > -#include > > -#include > > - > > -#define MIPITX_DSI_CON 0x00 > > -#define RG_DSI_LDOCORE_EN BIT(0) > > -#define RG_DSI_CKG_LDOOUT_EN BIT(1) > > -#define RG_DSI_BCLK_SEL(3 << 2) > > -#define RG_DSI_LD_IDX_SEL (7 << 4) > > -#define RG_DSI_PHYCLK_SEL (2 << 8) > > -#define RG_DSI_DSICLK_FREQ_SEL BIT(10) > > -#define RG_DSI_LPTX_CLMP_ENBIT(11) > > - > > -#define MIPITX_DSI_CLOCK_LANE 0x04 > > -#define MIPITX_DSI_DATA_LANE0 0x08 > > -#define MIPITX_DSI_DATA_LANE1 0x0c > > -#define MIPITX_DSI_DATA_LANE2 0x10 > > -#define MIPITX_DSI_DATA_LANE3 0x14 > > -#define RG_DSI_LNTx_LDOOUT_EN BIT(0) > > -#define RG_DSI_LNTx_CKLANE_EN BIT(1) > > -#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2) > > -#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3) > > -#define RG_DSI_LNTx_LPTX_IMINUSBIT(4) > > -#define RG_DSI_LNTx_LPCD_IPLUS BIT(5) > > -#define RG_DSI_LNTx_LPCD_IMINUSBIT(6) > > -#define RG_DSI_LNTx_RT_CODE(0xf << 8) > > - > > -#define MIPITX_DSI_TOP_CON 0x40 > > -#define RG_DSI_LNT_INTR_EN BIT(0) > > -#define RG_DSI_LNT_HS_BIAS_EN BIT(1) > > -#define RG_DSI_LNT_IMP_CAL_EN BIT(2) > > -#define RG_DSI_LNT_TESTMODE_EN BIT(3) > > -#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4) > > -#define RG_DSI_LNT_AIO_SEL (7 << 8) > > -#define RG_DSI_PAD_TIE_LOW_EN BIT(11) > > -#define RG_DSI_DEBUG_INPUT_EN BIT(12) > > -#define RG_DSI_PRESERVE(7 << 13) > > - > > -#define MIPITX_DSI_BG_CON 0x44 > > -#define RG_DSI_BG_CORE_EN BIT(0) > > -#define RG_DSI_BG_CKEN BIT(1) > > -#define RG_DSI_BG_DIV (0x3 << 2) > > -#define RG_DSI_BG_FAST_CHARGE
[PATCH 3/3] drm/mediatek: add mt8183 dsi driver support
MT8183 dsi has two changes with mt8173.
1. Add the register double buffer control, but we no need it, So make
it default off.
2. Add picture size control.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80db02a25cb0..20cb53f05d42 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -131,7 +132,10 @@
#define VM_CMD_EN BIT(0)
#define TS_VFP_EN BIT(5)
-#define DSI_CMDQ0 0x180
+#define DSI_SHADOW_DEBUG 0x190U
+#define FORCE_COMMIT BIT(0)
+#define BYPASS_SHADOW BIT(1)
+
#define CONFIG (0xff << 0)
#define SHORT_PACKET 0
#define LONG_PACKET2
@@ -158,6 +162,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive, dsi->regs +
DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
@@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
mtk_dsi_enable(dsi);
+
+ /* DSI no need this double buffer, disable it when writing register */
+ writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG);
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
@@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
};
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+ .has_size_ctl = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
.data = &mt8173_dsi_driver_data },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
};
--
2.20.1
[PATCH 1/3] drm/mediatek: move mipi_dsi_host_register to probe
DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.
If mipi_dsi_host_register is not in probe, dsi panel will
probe fail or more delay.
So move the mipi_dsi_host_register to probe from bind.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 49 ++
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 27b507eb4a99..93fa255b4aad 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
device *master, void *data)
return ret;
}
- ret = mipi_dsi_host_register(&dsi->host);
- if (ret < 0) {
- dev_err(dev, "failed to register DSI host: %d\n", ret);
- goto err_ddp_comp_unregister;
- }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct device
*master, void *data)
return 0;
err_unregister:
- mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
}
@@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+ dsi->dev = dev;
+ ret = mipi_dsi_host_register(&dsi->host);
+ if (ret < 0) {
+ dev_err(dev, "failed to register DSI host: %d\n", ret);
+ return -EPROBE_DEFER;
+ }
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
&dsi->panel, &dsi->bridge);
if (ret)
- return ret;
+ goto err_unregister_host;
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
- return comp_id;
+ ret = comp_id;
+ goto err_unregister_host;
}
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
irq_num = platform_get_irq(pdev, 0);
if (irq_num < 0) {
dev_err(&pdev->dev, "failed to request dsi irq resource\n");
- return -EPROBE_DEFER;
+ ret = -EPROBE_DEFER;
+ goto err_unregister_host;
}
irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
@@ -1163,14 +1163,25 @@ static int mtk_dsi_probe(struct platform_device *pdev)
IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
if (ret) {
dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
- return -EPROBE_DEFER;
+ ret = -
[PATCH 2/3] drm/mediatek: CMDQ reg address of mt8173 is different with mt2701
Config the different CMDQ reg address in driver data.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 39 --
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 93fa255b4aad..80db02a25cb0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -156,6 +156,10 @@
struct phy;
+struct mtk_dsi_driver_data {
+ const u32 reg_cmdq_off;
+};
+
struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -182,6 +186,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+ struct mtk_dsi_driver_data *driver_data;
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -934,6 +939,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+ u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -953,9 +959,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
}
for (i = 0; i < msg->tx_len; i++)
- writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+ mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
- mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+ mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
}
@@ -1074,10 +1082,27 @@ static const struct component_ops mtk_dsi_component_ops
= {
.unbind = mtk_dsi_unbind,
};
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+ .reg_cmdq_off = 0x180,
+};
+
+static const struct of_device_id mtk_dsi_of_match[] = {
+ { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+ { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
+ { },
+};
+
static int mtk_dsi_probe(struct platform_device *pdev)
{
struct mtk_dsi *dsi;
struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id;
struct resource *regs;
int irq_num;
int comp_id;
@@ -1101,6 +1126,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
+ of_id = of_match_device(mtk_dsi_of_match, &pdev->dev);
+ dsi->driver_data = (struct mtk_dsi_driver_data *)
+ of_id->data;
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1194,12 +1223,6 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id mtk_dsi_of_match[] = {
- { .compatible = "mediatek,mt2701-dsi" },
- { .compatible = "mediatek,mt8173-dsi" },
- { },
-};
-
struct platform_driver mtk_dsi_driver = {
.probe = mtk_dsi_probe,
.remove = mtk_dsi_remove,
--
2.20.1
[PATCH] drm/mediatek: add mipi_tx driver for mt8183
This patch adds mipi tx driver support for mt8183. Mipi_tx of mt8183 is very different to mt8173. 1.Separate mipi tx setting to mtk_mt8173_mipi_tx.c for mt8173 2.Separate mipi tx setting to mtk_mt8183_mipi_tx.c for mt8183 3.To reuse the common code, make the common functions in mtk_mipi_tx.c Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 352 ++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 52 +++ drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 290 +++ drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 168 + 5 files changed, 549 insertions(+), 315 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 82ae49c64221..8067a4be8311 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -12,6 +12,8 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_drm_plane.o \ mtk_dsi.o \ mtk_mipi_tx.o \ + mtk_mt8173_mipi_tx.o \ + mtk_mt8183_mipi_tx.o \ mtk_dpi.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 90e913108950..7591a38ca565 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -11,292 +11,45 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MIPITX_DSI_CON 0x00 -#define RG_DSI_LDOCORE_EN BIT(0) -#define RG_DSI_CKG_LDOOUT_EN BIT(1) -#define RG_DSI_BCLK_SEL(3 << 2) -#define RG_DSI_LD_IDX_SEL (7 << 4) -#define RG_DSI_PHYCLK_SEL (2 << 8) -#define RG_DSI_DSICLK_FREQ_SEL BIT(10) -#define RG_DSI_LPTX_CLMP_ENBIT(11) - -#define MIPITX_DSI_CLOCK_LANE 0x04 -#define MIPITX_DSI_DATA_LANE0 0x08 -#define MIPITX_DSI_DATA_LANE1 0x0c -#define MIPITX_DSI_DATA_LANE2 0x10 -#define MIPITX_DSI_DATA_LANE3 0x14 -#define RG_DSI_LNTx_LDOOUT_EN BIT(0) -#define RG_DSI_LNTx_CKLANE_EN BIT(1) -#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2) -#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3) -#define RG_DSI_LNTx_LPTX_IMINUSBIT(4) -#define RG_DSI_LNTx_LPCD_IPLUS BIT(5) -#define RG_DSI_LNTx_LPCD_IMINUSBIT(6) -#define RG_DSI_LNTx_RT_CODE(0xf << 8) - -#define MIPITX_DSI_TOP_CON 0x40 -#define RG_DSI_LNT_INTR_EN BIT(0) -#define RG_DSI_LNT_HS_BIAS_EN BIT(1) -#define RG_DSI_LNT_IMP_CAL_EN BIT(2) -#define RG_DSI_LNT_TESTMODE_EN BIT(3) -#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4) -#define RG_DSI_LNT_AIO_SEL (7 << 8) -#define RG_DSI_PAD_TIE_LOW_EN BIT(11) -#define RG_DSI_DEBUG_INPUT_EN BIT(12) -#define RG_DSI_PRESERVE(7 << 13) - -#define MIPITX_DSI_BG_CON 0x44 -#define RG_DSI_BG_CORE_EN BIT(0) -#define RG_DSI_BG_CKEN BIT(1) -#define RG_DSI_BG_DIV (0x3 << 2) -#define RG_DSI_BG_FAST_CHARGE BIT(4) -#define RG_DSI_VOUT_MSK(0x3 << 5) -#define RG_DSI_V12_SEL (7 << 5) -#define RG_DSI_V10_SEL (7 << 8) -#define RG_DSI_V072_SEL(7 << 11) -#define RG_DSI_V04_SEL (7 << 14) -#define RG_DSI_V032_SEL(7 << 17) -#define RG_DSI_V02_SEL (7 << 20) -#define RG_DSI_BG_R1_TRIM (0xf << 24) -#define RG_DSI_BG_R2_TRIM (0xf << 28) - -#define MIPITX_DSI_PLL_CON00x50 -#define RG_DSI_MPPLL_PLL_ENBIT(0) -#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1) -#define RG_DSI_MPPLL_PREDIV(3 << 1) -#define RG_DSI_MPPLL_TXDIV0(3 << 3) -#define RG_DSI_MPPLL_TXDIV1(3 << 5) -#define RG_DSI_MPPLL_POSDIV(7 << 7) -#define RG_DSI_MPPLL_MONVC_EN BIT(10) -#define RG_DSI_MPPLL_MONREF_EN BIT(11) -#define RG_DSI_MPPLL_VOD_ENBIT(12) - -#define MIPITX_DSI_PLL_CON10x54 -#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0) -#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) -#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2) -#define RG_DSI_MPPLL_SDM_SSC_PRD (0x << 16) - -#define MIPITX_DSI_PLL_CON20x58 - -#define MIPITX_DSI_PLL_TOP 0x64 -#define RG_DSI_MPPLL_PRESERVE (0xff << 8) - -#define MI
[PATCH] drm/mediatek: add mt8183 dpi support
MT8183 sample on rising and falling edge. It can reduce half data io.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 62a9d47df948..610c23334047 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -117,6 +117,7 @@ struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
bool edge_sel_en;
+ bool dual_edge;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
*dpi)
mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
}
+static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
+}
+
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)
{
@@ -509,6 +517,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
mtk_dpi_config_disable_edge(dpi);
+ if (dpi->conf->dual_edge)
+ mtk_dpi_enable_dual_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -671,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
return 2;
}
+static unsigned int mt8183_calculate_factor(int clock)
+{
+ if (clock <= 27000)
+ return 8;
+ else if (clock <= 167000)
+ return 4;
+ else
+ return 2;
+}
+
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
@@ -682,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
.edge_sel_en = true,
};
+static const struct mtk_dpi_conf mt8183_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .dual_edge = true,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -777,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,
},
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = &mt8183_conf,
+ },
{ },
};
--
2.12.5
Re: [PATCH V2] pwm: Add MediaTek MT8183 display PWM driver support
On Tue, 2019-01-22 at 10:16 +0100, Uwe Kleine-König wrote: > On Tue, Jan 22, 2019 at 05:02:43PM +0800, Jitao Shi wrote: > > Use the mtk_pwm_data struction to define different registers > > and add MT8183 specific register operations, such as MT8183 > > doesn't have commit register, needs to disable double buffer > > before writing register, and needs to select commit mode > > and use PWM_PERIOD/PWM_HIGH_WIDTH. > > > > Signed-off-by: Jitao Shi > > There is no difference compared to (implicit) v1 sent a few minutes > earlier, right? There was another patch sent with the same Subject last > week, so I assume the mail from today without "v2" in the Subject was a > mistake? > > > --- > Adding a paragraph below the tripple dash that points out what was > changed compared to the previous submission is a good idea to help > reviewers to more easily see what was changed. I guess you only adapted > the commit log as a reaction to Matthias Burgger's review? > > Best regards > Uwe > Yes, I miss the "V2" and fine tune the commit message. Best Regards Jitao
[PATCH V2] pwm: Add MediaTek MT8183 display PWM driver support
Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 893940d45f0d..15803c71fe80 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -277,10 +277,21 @@ static const struct mtk_pwm_data mt8173_pwm_data = {
.commit_mask = 0x1,
};
+static const struct mtk_pwm_data mt8183_pwm_data = {
+ .enable_mask = BIT(0),
+ .con0 = 0x18,
+ .con0_sel = 0x0,
+ .con1 = 0x1c,
+ .has_commit = false,
+ .bls_debug = 0x80,
+ .bls_debug_mask = 0x3,
+};
+
static const struct of_device_id mtk_disp_pwm_of_match[] = {
{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
+ { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
--
2.12.5
[PATCH] pwm: Add MediaTek MT8183 display PWM driver support
Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 893940d45f0d..15803c71fe80 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -277,10 +277,21 @@ static const struct mtk_pwm_data mt8173_pwm_data = {
.commit_mask = 0x1,
};
+static const struct mtk_pwm_data mt8183_pwm_data = {
+ .enable_mask = BIT(0),
+ .con0 = 0x18,
+ .con0_sel = 0x0,
+ .con1 = 0x1c,
+ .has_commit = false,
+ .bls_debug = 0x80,
+ .bls_debug_mask = 0x3,
+};
+
static const struct of_device_id mtk_disp_pwm_of_match[] = {
{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
+ { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
--
2.20.1
Re: [PATCH 9/9] drm/mediatek: add dpi dual edge support
On Wed, 2019-01-09 at 17:58 +0100, Matthias Brugger wrote:
>
> On 04/01/2019 08:03, chunhui dai wrote:
> > DPI sample on rising and falling edge. It can reduce half data io.
> >
> > Signed-off-by: Jitao Shi
> > Signed-off-by: chunhui dai
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 30 ++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 4a2f4a6..acb4f47 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -117,6 +117,7 @@ struct mtk_dpi_conf {
> > unsigned int (*cal_factor)(int clock);
> > u32 reg_h_fre_con;
> > bool edge_sel_en;
> > + bool dual_edge;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32
> > mask)
> > @@ -353,6 +354,15 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
> > *dpi)
> > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> > }
> >
> > +static void mtk_dpi_config_dual_edge(struct mtk_dpi *dpi)
>
> I think it is clearer if you rename the function to something like:
> mtk_dpi_enable_dual_edge and call it in mtk_dpi_set_display_mode if
> dpi->conf->dual_edge is true.
>
> Regards,
> Matthias
>
I'll fix it in next patch.
Best Regards
Jitao
> > +{
> > + if (dpi->conf->dual_edge) {
> > + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN |
> > + DDR_4PHASE, DDR_EN | DDR_4PHASE);
> > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
> > + }
> > +}
> > +
> > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> > enum mtk_dpi_out_color_format format)
> > {
> > @@ -509,6 +519,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > mtk_dpi_config_color_format(dpi, dpi->color_format);
> > mtk_dpi_config_2n_h_fre(dpi);
> > mtk_dpi_config_disable_edge(dpi);
> > + mtk_dpi_config_dual_edge(dpi);
> > mtk_dpi_sw_reset(dpi, false);
> >
> > return 0;
> > @@ -669,6 +680,16 @@ static unsigned int mt2701_calculate_factor(int clock)
> > return 1;
> > }
> >
> > +static unsigned int mt8183_calculate_factor(int clock)
> > +{
> > + if (clock <= 27000)
> > + return 8;
> > + else if (clock <= 167000)
> > + return 4;
> > + else
> > + return 2;
> > +}
> > +
> > static const struct mtk_dpi_conf mt8173_conf = {
> > .cal_factor = mt8173_calculate_factor,
> > .reg_h_fre_con = 0xe0,
> > @@ -680,6 +701,12 @@ static unsigned int mt2701_calculate_factor(int clock)
> > .edge_sel_en = true,
> > };
> >
> > +static const struct mtk_dpi_conf mt8183_conf = {
> > + .cal_factor = mt8183_calculate_factor,
> > + .reg_h_fre_con = 0xe0,
> > + .dual_edge = true,
> > +};
> > +
> > static int mtk_dpi_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -775,6 +802,9 @@ static int mtk_dpi_remove(struct platform_device *pdev)
> > { .compatible = "mediatek,mt8173-dpi",
> > .data = &mt8173_conf,
> > },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = &mt8183_conf,
> > + },
> > { },
> > };
> >
> >
Re: [PATCH 9/9] drm/mediatek: add dpi dual edge support
Hi CK,
Ok, I'll send it again in an independent patch.
Best Regards
Jitao
On Wed, 2019-01-16 at 14:52 +0800, CK Hu (胡俊光) wrote:
> Hi, Chunhui:
>
> > -Original Message-
> > From: chunhui dai [mailto:chunhui@mediatek.com]
> > Sent: Friday, January 04, 2019 3:04 PM
> > To: --to=Michael Turquette; Stephen Boyd; CK Hu (胡俊光)
> > Cc: Matthias Brugger; Philipp Zabel; David Airlie; Chunhui Dai (戴春晖); Sean
> > Wang; Ryder Lee (李庚諺); Colin Ian King; linux-...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> > linux-media...@lists.infradead.org; dri-de...@lists.freedesktop.org;
> > srv_heupstream; Bibby Hsieh (謝濟遠); JamesJJ Liao (廖建智); Jitao Shi (石记
> > 涛)
> > Subject: [PATCH 9/9] drm/mediatek: add dpi dual edge support
> >
> > DPI sample on rising and falling edge. It can reduce half data io.
>
> This patch looks like a patch for MT8183. For MT8173 and MT2701, dual_edge is
> false.
> For now, we have not support MT8183 yet.
> So you could just set dual_edge to false and remove MT8183 part in this patch.
> You could send the MT8183 part in an independent patch, not in a series of
> MT2701.
>
> Regards,
> CK
>
> >
> > Signed-off-by: Jitao Shi
> > Signed-off-by: chunhui dai
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 30
> > ++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 4a2f4a6..acb4f47 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -117,6 +117,7 @@ struct mtk_dpi_conf {
> > unsigned int (*cal_factor)(int clock);
> > u32 reg_h_fre_con;
> > bool edge_sel_en;
> > + bool dual_edge;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32
> > mask)
> > @@ -353,6 +354,15 @@ static void mtk_dpi_config_disable_edge(struct
> > mtk_dpi *dpi)
> > mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
> >
> > +static void mtk_dpi_config_dual_edge(struct mtk_dpi *dpi) {
> > + if (dpi->conf->dual_edge) {
> > + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN |
> > + DDR_4PHASE, DDR_EN | DDR_4PHASE);
> > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
> > + }
> > +}
> > +
> > static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> > enum mtk_dpi_out_color_format format)
> > { @@
> > -509,6 +519,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > mtk_dpi_config_color_format(dpi, dpi->color_format);
> > mtk_dpi_config_2n_h_fre(dpi);
> > mtk_dpi_config_disable_edge(dpi);
> > + mtk_dpi_config_dual_edge(dpi);
> > mtk_dpi_sw_reset(dpi, false);
> >
> > return 0;
> > @@ -669,6 +680,16 @@ static unsigned int mt2701_calculate_factor(int
> > clock)
> > return 1;
> > }
> >
> > +static unsigned int mt8183_calculate_factor(int clock) {
> > + if (clock <= 27000)
> > + return 8;
> > + else if (clock <= 167000)
> > + return 4;
> > + else
> > + return 2;
> > +}
> > +
> > static const struct mtk_dpi_conf mt8173_conf = {
> > .cal_factor = mt8173_calculate_factor,
> > .reg_h_fre_con = 0xe0,
> > @@ -680,6 +701,12 @@ static unsigned int mt2701_calculate_factor(int
> > clock)
> > .edge_sel_en = true,
> > };
> >
> > +static const struct mtk_dpi_conf mt8183_conf = {
> > + .cal_factor = mt8183_calculate_factor,
> > + .reg_h_fre_con = 0xe0,
> > + .dual_edge = true,
> > +};
> > +
> > static int mtk_dpi_probe(struct platform_device *pdev) {
> > struct device *dev = &pdev->dev;
> > @@ -775,6 +802,9 @@ static int mtk_dpi_remove(struct platform_device
> > *pdev)
> > { .compatible = "mediatek,mt8173-dpi",
> > .data = &mt8173_conf,
> > },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = &mt8183_conf,
> > + },
> > { },
> > };
> >
> > --
> > 1.9.1
>
[PATCH] pwm: Add MediaTek MT8183 display PWM driver support
Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
have commit register, needs to enable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi
---
drivers/pwm/pwm-mtk-disp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 893940d45f0d..15803c71fe80 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -277,10 +277,21 @@ static const struct mtk_pwm_data mt8173_pwm_data = {
.commit_mask = 0x1,
};
+static const struct mtk_pwm_data mt8183_pwm_data = {
+ .enable_mask = BIT(0),
+ .con0 = 0x18,
+ .con0_sel = 0x0,
+ .con1 = 0x1c,
+ .has_commit = false,
+ .bls_debug = 0x80,
+ .bls_debug_mask = 0x3,
+};
+
static const struct of_device_id mtk_disp_pwm_of_match[] = {
{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
+ { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
--
2.12.5
[PATCH v5] drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
mode, those signals will cause h-time larger than normal and reduce FPS.
So need to multiply a coefficient to offset the extra signal's effect.
coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+
Ths_trail+Ths_exit)/(htotal*bpp/lane_number)
Signed-off-by: Jitao Shi
---
Change since v4:
- tune the calc comment more clear.
- define the phy timings as constants.
Chnage since v3:
- wrapp the commit msg.
- fix alignment of some lines.
Change since v2:
- move phy timing back to dsi_phy_timconfig.
Change since v1:
- phy_timing2 and phy_timing3 refer clock cycle time.
- define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET
DA_HS_EXIT.
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 64 +++-
1 file changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 28b2044..eaa5a22 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -86,7 +86,7 @@
#define DSI_PHY_TIMECON0 0x110
#define LPX(0xff << 0)
-#define HS_PRPR(0xff << 8)
+#define HS_PREP(0xff << 8)
#define HS_ZERO(0xff << 16)
#define HS_TRAIL (0xff << 24)
@@ -102,10 +102,16 @@
#define CLK_TRAIL (0xff << 24)
#define DSI_PHY_TIMECON3 0x11c
-#define CLK_HS_PRPR(0xff << 0)
+#define CLK_HS_PREP(0xff << 0)
#define CLK_HS_POST(0xff << 8)
#define CLK_HS_EXIT(0xff << 16)
+#define T_LPX 5
+#define T_HS_PREP 6
+#define T_HS_TRAIL 8
+#define T_HS_EXIT 7
+#define T_HS_ZERO 10
+
#define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
struct phy;
@@ -161,20 +167,18 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset,
u32 mask, u32 data)
static void dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
- unsigned int ui, cycle_time;
- unsigned int lpx;
+ u32 ui, cycle_time;
ui = 1000 / dsi->data_rate + 0x01;
cycle_time = 8000 / dsi->data_rate + 0x01;
- lpx = 5;
- timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
- timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
- (4 * lpx);
+ timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
+ timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
+ T_HS_EXIT << 24;
timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
(NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
- NS_TO_CYCLE(0x40, cycle_time);
+ timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
+ NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -202,19 +206,47 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->dev;
int ret;
+ u64 pixel_clock, total_bits;
+ u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
if (++dsi->refcount != 1)
return 0;
+ switch (dsi->format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
+
/**
-* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
-* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
-* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
-* we set mipi_ratio is 1.05.
+* vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
+* htotal_time = htotal * byte_per_pixel / num_lanes
+* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
+* mipi_ratio = (htotal_time + overhead_time) / htotal_time
+* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
*/
- dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
+ pixel_clock = dsi->vm.pixelclock * 1000;
+ hto
Re: [v17 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
Dear Archit, Thanks a lot for your reviewing. I have sent a new patchset for those review items. On Fri, 2016-11-11 at 11:32 +0530, Archit Taneja wrote: > Hi Jitao, > > I couldn't locate the original mail, so posting on this thread instead. > Some comments below. > > On 11/10/2016 10:09 PM, Enric Balletbo Serra wrote: > > Hi Jitao, > > > > 2016-08-27 8:44 GMT+02:00 Jitao Shi : > >> This patch adds drm_bridge driver for parade DSI to eDP bridge chip. > >> > >> Signed-off-by: Jitao Shi > >> Reviewed-by: Daniel Kurtz > >> --- > >> Changes since v16: > >> - Disable ps8640 DSI MCS Function. > >> - Rename gpios name more clearly. > >> - Tune the ps8640 power on sequence. > >> > >> Changes since v15: > >> - Drop drm_connector_(un)register calls from parade ps8640. > >>The main DRM driver mtk_drm_drv now calls > >>drm_connector_register_all() after drm_dev_register() in the > >>mtk_drm_bind() function. That function should iterate over all > >>connectors and call drm_connector_register() for each of them. > >>So, remove drm_connector_(un)register calls from parade ps8640. > >> > >> Changes since v14: > >> - update copyright info. > >> - change bridge_to_ps8640 and connector_to_ps8640 to inline function. > >> - fix some coding style. > >> - use sizeof as array counter. > >> - use drm_get_edid when read edid. > >> - add mutex when firmware updating. > >> > >> Changes since v13: > >> - add const on data, ps8640_write_bytes(struct i2c_client *client, const > >> u8 *data, u16 data_len) > >> - fix PAGE2_SW_REST tyro. > >> - move the buf[3] init to entrance of the function. > >> > >> Changes since v12: > >> - fix hw_chip_id build warning > >> > >> Changes since v11: > >> - Remove depends on I2C, add DRM depends > >> - Reuse ps8640_write_bytes() in ps8640_write_byte() > >> - Use timer check for polling like the routines in > >> - Fix no drm_connector_unregister/drm_connector_cleanup when > >> ps8640_bridge_attach fail > >> - Check the ps8640 hardware id in ps8640_validate_firmware > >> - Remove fw_version check > >> - Move ps8640_validate_firmware before ps8640_enter_bl > >> - Add ddc_i2c unregister when probe fail and ps8640_remove > >> --- > >> drivers/gpu/drm/bridge/Kconfig | 12 + > >> drivers/gpu/drm/bridge/Makefile|1 + > >> drivers/gpu/drm/bridge/parade-ps8640.c | 1077 > >> > >> 3 files changed, 1090 insertions(+) > >> create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c > >> > >> diff --git a/drivers/gpu/drm/bridge/Kconfig > >> b/drivers/gpu/drm/bridge/Kconfig > >> index b590e67..c59d043 100644 > >> --- a/drivers/gpu/drm/bridge/Kconfig > >> +++ b/drivers/gpu/drm/bridge/Kconfig > >> @@ -50,6 +50,18 @@ config DRM_PARADE_PS8622 > >> ---help--- > >> Parade eDP-LVDS bridge chip driver. > >> > >> +config DRM_PARADE_PS8640 > >> + tristate "Parade PS8640 MIPI DSI to eDP Converter" > >> + depends on DRM > >> + depends on OF > >> + select DRM_KMS_HELPER > >> + select DRM_MIPI_DSI > >> + select DRM_PANEL > >> + ---help--- > >> + Choose this option if you have PS8640 for display > >> + The PS8640 is a high-performance and low-power > >> + MIPI DSI to eDP converter > >> + > >> config DRM_SII902X > >> tristate "Silicon Image sii902x RGB/HDMI bridge" > >> depends on OF > >> diff --git a/drivers/gpu/drm/bridge/Makefile > >> b/drivers/gpu/drm/bridge/Makefile > >> index efdb07e..3360537 100644 > >> --- a/drivers/gpu/drm/bridge/Makefile > >> +++ b/drivers/gpu/drm/bridge/Makefile > >> @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o > >> obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o > >> obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o > >> obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o > >> +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o > >> obj-$(CONFIG_DRM_SII902X) += sii902x.o > >> obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > >> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ > >> diff --git a/drivers/gpu/
[PATCH v18 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v17:
- No change.
Changes since v16:
- No change.
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v18 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip. Signed-off-by: Jitao Shi Reviewed-by: Daniel Kurtz Reviewed-by: Enric Balletbo i Serra --- Changes since v17: - remove some unused head files. - add macros for ps8640 pages. - remove ddc_i2c client - add mipi_dsi_device_register_full - remove the manufacturer from the name and i2c_device_id Changes since v16: - Disable ps8640 DSI MCS Function. - Rename gpios name more clearly. - Tune the ps8640 power on sequence. Changes since v15: - Drop drm_connector_(un)register calls from parade ps8640. The main DRM driver mtk_drm_drv now calls drm_connector_register_all() after drm_dev_register() in the mtk_drm_bind() function. That function should iterate over all connectors and call drm_connector_register() for each of them. So, remove drm_connector_(un)register calls from parade ps8640. Changes since v14: - update copyright info. - change bridge_to_ps8640 and connector_to_ps8640 to inline function. - fix some coding style. - use sizeof as array counter. - use drm_get_edid when read edid. - add mutex when firmware updating. Changes since v13: - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len) - fix PAGE2_SW_REST tyro. - move the buf[3] init to entrance of the function. Changes since v12: - fix hw_chip_id build warning Changes since v11: - Remove depends on I2C, add DRM depends - Reuse ps8640_write_bytes() in ps8640_write_byte() - Use timer check for polling like the routines in - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail - Check the ps8640 hardware id in ps8640_validate_firmware - Remove fw_version check - Move ps8640_validate_firmware before ps8640_enter_bl - Add ddc_i2c unregister when probe fail and ps8640_remove --- drivers/gpu/drm/bridge/Kconfig | 12 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/parade-ps8640.c | 1079 3 files changed, 1092 insertions(+) create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 10e12e7..7f41bbc 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -57,6 +57,18 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on DRM + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + config DRM_SII902X tristate "Silicon Image sii902x RGB/HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index cdf3a3c..7d93d40 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000..2d9c337 --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define PAGE1_VSTART 0x6b +#define PAGE2_SPI_CFG3 0x82 +#define I2C_TO_SPI_RESET 0x20 +#define PAGE2_ROMADD_BYTE1 0x8e +#define PAGE2_ROMADD_BYTE2 0x8f +#define PAGE2_SWSPI_WDATA 0x90 +#define PAGE2_SWSPI_RDATA 0x91 +#define PAGE2_SWSPI_LEN0x92 +#define PAGE2_SWSPI_CTL0x93 +#define TRIGGER_NO_READBACK0x05 +#define TRIGGER_READBACK 0x01 +#define PAGE2_SPI_STATUS 0x9e +#define SPI_READY 0x0c +#define PAGE2_GPIO_L 0xa6 +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9
[PATCH v4] drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
mode, those signals will cause h-time larger than normal and reduce FPS.
So need to multiply a coefficient to offset the extra signal's effect.
coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+
Ths_trail+Ths_exit)/(htotal*bpp/lane_number)
Signed-off-by: Jitao Shi
---
Chnage since v3:
- wrapp the commit msg.
- fix alignment of some lines.
Change since v2:
- move phy timing back to dsi_phy_timconfig.
Change since v1:
- phy_timing2 and phy_timing3 refer clock cycle time.
- define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET
DA_HS_EXIT.
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 71 +---
1 file changed, 49 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 28b2044..5defe58 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -85,16 +85,16 @@
#define LD0_WAKEUP_EN BIT(2)
#define DSI_PHY_TIMECON0 0x110
-#define LPX(0xff << 0)
-#define HS_PRPR(0xff << 8)
-#define HS_ZERO(0xff << 16)
-#define HS_TRAIL (0xff << 24)
+#define LPX(5 << 0)
+#define HS_PRPR(6 << 8)
+#define HS_ZERO(10 << 16)
+#define HS_TRAIL (8 << 24)
#define DSI_PHY_TIMECON1 0x114
-#define TA_GO (0xff << 0)
-#define TA_SURE(0xff << 8)
-#define TA_GET (0xff << 16)
-#define DA_HS_EXIT (0xff << 24)
+#define TA_GO (20 << 0)
+#define TA_SURE(7 << 8)
+#define TA_GET (25 << 16)
+#define DA_HS_EXIT (7 << 24)
#define DSI_PHY_TIMECON2 0x118
#define CONT_DET (0xff << 0)
@@ -161,20 +161,17 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset,
u32 mask, u32 data)
static void dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
- unsigned int ui, cycle_time;
- unsigned int lpx;
+ u32 ui, cycle_time;
ui = 1000 / dsi->data_rate + 0x01;
cycle_time = 8000 / dsi->data_rate + 0x01;
- lpx = 5;
- timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
- timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
- (4 * lpx);
+ timcon0 = LPX | HS_PRPR | HS_ZERO | HS_TRAIL;
+ timcon1 = 4 * LPX | (3 * LPX / 2) << 8 | 5 * LPX << 16 | DA_HS_EXIT;
timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
(NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
- NS_TO_CYCLE(0x40, cycle_time);
+ timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * LPX) << 16 |
+ NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -202,19 +199,49 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->dev;
int ret;
+ u64 bit_clock, total_bits;
+ u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
if (++dsi->refcount != 1)
return 0;
+ switch (dsi->format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
/**
-* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
-* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
-* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
-* we set mipi_ratio is 1.05.
+* data_rate = (pixel_clock) * bit_per_pixel * mipi_ratio / lane_num;
+* vm.pixelclock is Khz, data_rata unit is Hz, so need to multiply 1000
+* mipi_ratio is (htotal * byte_per_pixel / lane_num + Tlpx + Ths_prep
+*+ Thstrail + Ths_exit + Ths_zero) /
+* (htotal * byte_per_pixel /lane_number)
*/
- dsi->data_rate = dsi->vm.pixelclock * 3 * 21
Re: [PATCH v2] drm/mediatek: fixed the calc method of data rate per lane
On Wed, 2016-10-26 at 14:41 +0800, CK Hu wrote:
> Hi, Jitao:
>
> On Tue, 2016-10-25 at 13:40 +0800, Jitao Shi wrote:
> > Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
> > Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
> > signal will cause h-time larger than normal and reduce FPS.
> > Need to multiply a coefficient to offset the extra signal's effect.
> > coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+Ths_trail+
> > Ths_exit)/(htotal*bpp/lane_number))
> >
> > Signed-off-by: Jitao Shi
> > ---
> > Change since v1:
> > - phy_timing2 and phy_timing3 refer clock cycle time.
> > - define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET
> > DA_HS_EXIT
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 103
> > +++-
> > 1 file changed, 67 insertions(+), 36 deletions(-)
> >
>
> [snip...]
>
> >
> > -static void dsi_phy_timconfig(struct mtk_dsi *dsi)
> > +static void dsi_phy_timconfig(struct mtk_dsi *dsi, u32 phy_timing0,
> > + u32 phy_timing1, u32 phy_timing2,
> > + u32 phy_timing3)
> > {
> > - u32 timcon0, timcon1, timcon2, timcon3;
> > - unsigned int ui, cycle_time;
> > - unsigned int lpx;
> > -
> > - ui = 1000 / dsi->data_rate + 0x01;
> > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > - lpx = 5;
> > -
> > - timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
> > - timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
> > - (4 * lpx);
> > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > - timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
> > - NS_TO_CYCLE(0x40, cycle_time);
> > -
> > - writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > - writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > - writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
> > - writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
>
> Why do you move these calculation to mtk_dsi_poweron()? You can keep
> calculation here and just do some modification.
>
> Regards,
> CK
Thanks for your review. I'll fix it in next patchset.
Best Regards
jitao
>
> > + writel(phy_timing0, dsi->regs + DSI_PHY_TIMECON0);
> > + writel(phy_timing1, dsi->regs + DSI_PHY_TIMECON1);
> > + writel(phy_timing2, dsi->regs + DSI_PHY_TIMECON2);
> > + writel(phy_timing3, dsi->regs + DSI_PHY_TIMECON3);
> > }
> >
> > static void mtk_dsi_enable(struct mtk_dsi *dsi)
> > @@ -202,19 +188,51 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > {
> > struct device *dev = dsi->dev;
> > int ret;
> > + u64 bit_clock, total_bits;
> > + u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > + u32 phy_timing0, phy_timing1, phy_timing2, phy_timing3;
> > + u32 ui, cycle_time;
> >
> > if (++dsi->refcount != 1)
> > return 0;
> >
> > + switch (dsi->format) {
> > + case MIPI_DSI_FMT_RGB565:
> > + bit_per_pixel = 16;
> > + break;
> > + case MIPI_DSI_FMT_RGB666_PACKED:
> > + bit_per_pixel = 18;
> > + break;
> > + case MIPI_DSI_FMT_RGB666:
> > + case MIPI_DSI_FMT_RGB888:
> > + default:
> > + bit_per_pixel = 24;
> > + break;
> > + }
> > + /**
> > +* data_rate = (pixel_clock) * bit_per_pixel * mipi_ratio / lane_num;
> > +* vm.pixelclock is Khz, data_rata unit is Hz, so need to multiply 1000
> > +* mipi_ratio is (htotal * byte_per_pixel / lane_num + Tlpx + Ths_prep
> > +*+ Thstrail + Ths_exit + Ths_zero) /
> > +* (htotal * byte_per_pixel /lane_number)
> > +*/
> > + bit_clock = dsi->vm.pixelclock * 1000 * bit_per_pixel;
> > + htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > +dsi->vm.hsync_len;
> > + htotal_bits = htotal * bit_per_pixel;
> > +
> > /**
> > -* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
> > -* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
> > -* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
> > -* we set mipi_ratio
[PATCH v3] drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
signal will cause h-time larger than normal and reduce FPS.
Need to multiply a coefficient to offset the extra signal's effect.
coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+Ths_trail+
Ths_exit)/(htotal*bpp/lane_number))
Signed-off-by: Jitao Shi
---
Change since v2:
- move phy timing back to dsi_phy_timconfig.
Change since v1:
- phy_timing2 and phy_timing3 refer clock cycle time.
- define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET DA_HS_EXIT
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 74 +---
1 file changed, 51 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 28b2044..8b3b38a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -85,16 +85,16 @@
#define LD0_WAKEUP_EN BIT(2)
#define DSI_PHY_TIMECON0 0x110
-#define LPX(0xff << 0)
-#define HS_PRPR(0xff << 8)
-#define HS_ZERO(0xff << 16)
-#define HS_TRAIL (0xff << 24)
+#define LPX(5 << 0)
+#define HS_PRPR(6 << 8)
+#define HS_ZERO(10 << 16)
+#define HS_TRAIL (8 << 24)
#define DSI_PHY_TIMECON1 0x114
-#define TA_GO (0xff << 0)
-#define TA_SURE(0xff << 8)
-#define TA_GET (0xff << 16)
-#define DA_HS_EXIT (0xff << 24)
+#define TA_GO (20 << 0)
+#define TA_SURE(7 << 8)
+#define TA_GET (25 << 16)
+#define DA_HS_EXIT (7 << 24)
#define DSI_PHY_TIMECON2 0x118
#define CONT_DET (0xff << 0)
@@ -161,20 +161,18 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset,
u32 mask, u32 data)
static void dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
- unsigned int ui, cycle_time;
- unsigned int lpx;
+ u32 ui, cycle_time;
ui = 1000 / dsi->data_rate + 0x01;
cycle_time = 8000 / dsi->data_rate + 0x01;
- lpx = 5;
- timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
- timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
- (4 * lpx);
+ timcon0 = LPX | HS_PRPR | HS_ZERO | HS_TRAIL;
+ timcon1 = 4 * LPX | (3 * LPX / 2) << 8 | 5 * LPX << 16 | DA_HS_EXIT;
timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
- NS_TO_CYCLE(0x40, cycle_time);
+ (NS_TO_CYCLE(0x150, cycle_time) << 16);
+ timcon3 = (2 * LPX) << 16 |
+ NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
+ NS_TO_CYCLE(0x40, cycle_time);
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -202,19 +200,49 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->dev;
int ret;
+ u64 bit_clock, total_bits;
+ u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
if (++dsi->refcount != 1)
return 0;
+ switch (dsi->format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
/**
-* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
-* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
-* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
-* we set mipi_ratio is 1.05.
+* data_rate = (pixel_clock) * bit_per_pixel * mipi_ratio / lane_num;
+* vm.pixelclock is Khz, data_rata unit is Hz, so need to multiply 1000
+* mipi_ratio is (htotal * byte_per_pixel / lane_num + Tlpx + Ths_prep
+*+ Thstrail + Ths_exit + Ths_zero) /
+* (htotal * byte_per_pixel /lane_number)
*/
- dsi->data_rate = dsi->vm.pixelclock *
[PATCH v2] drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
signal will cause h-time larger than normal and reduce FPS.
Need to multiply a coefficient to offset the extra signal's effect.
coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+Ths_trail+
Ths_exit)/(htotal*bpp/lane_number))
Signed-off-by: Jitao Shi
---
Change since v1:
- phy_timing2 and phy_timing3 refer clock cycle time.
- define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET DA_HS_EXIT
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 103 +++-
1 file changed, 67 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 28b2044..ade6f46 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -85,16 +85,16 @@
#define LD0_WAKEUP_EN BIT(2)
#define DSI_PHY_TIMECON0 0x110
-#define LPX(0xff << 0)
-#define HS_PRPR(0xff << 8)
-#define HS_ZERO(0xff << 16)
-#define HS_TRAIL (0xff << 24)
+#define LPX(5 << 0)
+#define HS_PRPR(6 << 8)
+#define HS_ZERO(10 << 16)
+#define HS_TRAIL (8 << 24)
#define DSI_PHY_TIMECON1 0x114
-#define TA_GO (0xff << 0)
-#define TA_SURE(0xff << 8)
-#define TA_GET (0xff << 16)
-#define DA_HS_EXIT (0xff << 24)
+#define TA_GO (20 << 0)
+#define TA_SURE(7 << 8)
+#define TA_GET (25 << 16)
+#define DA_HS_EXIT (7 << 24)
#define DSI_PHY_TIMECON2 0x118
#define CONT_DET (0xff << 0)
@@ -158,28 +158,14 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset,
u32 mask, u32 data)
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
}
-static void dsi_phy_timconfig(struct mtk_dsi *dsi)
+static void dsi_phy_timconfig(struct mtk_dsi *dsi, u32 phy_timing0,
+ u32 phy_timing1, u32 phy_timing2,
+ u32 phy_timing3)
{
- u32 timcon0, timcon1, timcon2, timcon3;
- unsigned int ui, cycle_time;
- unsigned int lpx;
-
- ui = 1000 / dsi->data_rate + 0x01;
- cycle_time = 8000 / dsi->data_rate + 0x01;
- lpx = 5;
-
- timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
- timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
- (4 * lpx);
- timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
- NS_TO_CYCLE(0x40, cycle_time);
-
- writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
- writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
- writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
- writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
+ writel(phy_timing0, dsi->regs + DSI_PHY_TIMECON0);
+ writel(phy_timing1, dsi->regs + DSI_PHY_TIMECON1);
+ writel(phy_timing2, dsi->regs + DSI_PHY_TIMECON2);
+ writel(phy_timing3, dsi->regs + DSI_PHY_TIMECON3);
}
static void mtk_dsi_enable(struct mtk_dsi *dsi)
@@ -202,19 +188,51 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->dev;
int ret;
+ u64 bit_clock, total_bits;
+ u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
+ u32 phy_timing0, phy_timing1, phy_timing2, phy_timing3;
+ u32 ui, cycle_time;
if (++dsi->refcount != 1)
return 0;
+ switch (dsi->format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
+ /**
+* data_rate = (pixel_clock) * bit_per_pixel * mipi_ratio / lane_num;
+* vm.pixelclock is Khz, data_rata unit is Hz, so need to multiply 1000
+* mipi_ratio is (htotal * byte_per_pixel / lane_num + Tlpx + Ths_prep
+*+ Thstrail + Ths_exit + Ths_zero) /
+* (htotal * byte_per_pixel /lane_number)
+*/
+
[v17 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip. Signed-off-by: Jitao Shi Reviewed-by: Daniel Kurtz --- Changes since v16: - Disable ps8640 DSI MCS Function. - Rename gpios name more clearly. - Tune the ps8640 power on sequence. Changes since v15: - Drop drm_connector_(un)register calls from parade ps8640. The main DRM driver mtk_drm_drv now calls drm_connector_register_all() after drm_dev_register() in the mtk_drm_bind() function. That function should iterate over all connectors and call drm_connector_register() for each of them. So, remove drm_connector_(un)register calls from parade ps8640. Changes since v14: - update copyright info. - change bridge_to_ps8640 and connector_to_ps8640 to inline function. - fix some coding style. - use sizeof as array counter. - use drm_get_edid when read edid. - add mutex when firmware updating. Changes since v13: - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len) - fix PAGE2_SW_REST tyro. - move the buf[3] init to entrance of the function. Changes since v12: - fix hw_chip_id build warning Changes since v11: - Remove depends on I2C, add DRM depends - Reuse ps8640_write_bytes() in ps8640_write_byte() - Use timer check for polling like the routines in - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail - Check the ps8640 hardware id in ps8640_validate_firmware - Remove fw_version check - Move ps8640_validate_firmware before ps8640_enter_bl - Add ddc_i2c unregister when probe fail and ps8640_remove --- drivers/gpu/drm/bridge/Kconfig | 12 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/parade-ps8640.c | 1077 3 files changed, 1090 insertions(+) create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index b590e67..c59d043 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -50,6 +50,18 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on DRM + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + config DRM_SII902X tristate "Silicon Image sii902x RGB/HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index efdb07e..3360537 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000..7d67431 --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,1077 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define PAGE1_VSTART 0x6b +#define PAGE2_SPI_CFG3 0x82 +#define I2C_TO_SPI_RESET 0x20 +#define PAGE2_ROMADD_BYTE1 0x8e +#define PAGE2_ROMADD_BYTE2 0x8f +#define PAGE2_SWSPI_WDATA 0x90 +#define PAGE2_SWSPI_RDATA 0x91 +#define PAGE2_SWSPI_LEN0x92 +#define PAGE2_SWSPI_CTL0x93 +#define TRIGGER_NO_READBACK0x05 +#define TRIGGER_READBACK 0x01 +#define PAGE2_SPI_STATUS 0x9e +#define SPI_READY 0x0c +#define PAGE2_GPIO_L 0xa6 +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9 BIT(1) +#define PAGE2_IROM_CTRL0xb0 +#define IROM_ENABLE0xc0 +#define IROM_DISABLE 0x80 +#define PAGE2_SW_RESET 0xbc +#define SPI_SW_RESET BIT(7) +
[v17 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v16:
- No change.
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
signal will cause h-time larger than normal and reduce FPS.
Need to multiply a coefficient to offset the extra signal's effect.
coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+Ths_trail+
Ths_exit)/(htotal*bpp/lane_number))
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 111 ++--
1 file changed, 67 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 28b2044..506aa22 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -85,28 +85,26 @@
#define LD0_WAKEUP_EN BIT(2)
#define DSI_PHY_TIMECON0 0x110
-#define LPX(0xff << 0)
-#define HS_PRPR(0xff << 8)
-#define HS_ZERO(0xff << 16)
-#define HS_TRAIL (0xff << 24)
+#define LPX(x) ((x) << 0)
+#define HS_PRPR(x) ((x) << 8)
+#define HS_ZERO(x) ((x) << 16)
+#define HS_TRAIL(x)((x) << 24)
#define DSI_PHY_TIMECON1 0x114
-#define TA_GO (0xff << 0)
-#define TA_SURE(0xff << 8)
-#define TA_GET (0xff << 16)
-#define DA_HS_EXIT (0xff << 24)
+#define TA_GO(x) ((x) << 0)
+#define TA_SURE(x) ((x) << 8)
+#define TA_GET(x) ((x) << 16)
+#define DA_HS_EXIT(x) ((x) << 24)
#define DSI_PHY_TIMECON2 0x118
-#define CONT_DET (0xff << 0)
-#define CLK_ZERO (0xff << 16)
-#define CLK_TRAIL (0xff << 24)
+#define CONT_DET(x)((x) << 0)
+#define CLK_ZERO(x)((x) << 16)
+#define CLK_TRAIL(x) ((x) << 24)
#define DSI_PHY_TIMECON3 0x11c
-#define CLK_HS_PRPR(0xff << 0)
-#define CLK_HS_POST(0xff << 8)
-#define CLK_HS_EXIT(0xff << 16)
-
-#define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
+#define CLK_HS_PRPR(x) ((x) << 0)
+#define CLK_HS_POST(x) ((x) << 8)
+#define CLK_HS_EXIT(x) ((x) << 16)
struct phy;
@@ -158,28 +156,14 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset,
u32 mask, u32 data)
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
}
-static void dsi_phy_timconfig(struct mtk_dsi *dsi)
+static void dsi_phy_timconfig(struct mtk_dsi *dsi, u32 phy_timing0,
+ u32 phy_timing1, u32 phy_timing2,
+ u32 phy_timing3)
{
- u32 timcon0, timcon1, timcon2, timcon3;
- unsigned int ui, cycle_time;
- unsigned int lpx;
-
- ui = 1000 / dsi->data_rate + 0x01;
- cycle_time = 8000 / dsi->data_rate + 0x01;
- lpx = 5;
-
- timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
- timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
- (4 * lpx);
- timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
- NS_TO_CYCLE(0x40, cycle_time);
-
- writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
- writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
- writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
- writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
+ writel(phy_timing0, dsi->regs + DSI_PHY_TIMECON0);
+ writel(phy_timing1, dsi->regs + DSI_PHY_TIMECON1);
+ writel(phy_timing2, dsi->regs + DSI_PHY_TIMECON2);
+ writel(phy_timing3, dsi->regs + DSI_PHY_TIMECON3);
}
static void mtk_dsi_enable(struct mtk_dsi *dsi)
@@ -202,19 +186,57 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->dev;
int ret;
+ u64 bit_clock, total_bits;
+ u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
+ u32 phy_timing0, phy_timing1, phy_timing2, phy_timing3;
if (++dsi->refcount != 1)
return 0;
+ phy_timing0 = LPX(5) | HS_PRPR(6) | HS_ZERO(10) | HS_TRAIL(8);
+ phy_timing1 = TA_GO(20) | TA_SURE(7) | TA_GET(25) | DA_HS_EXIT(7);
+ phy_timing2 = CLK_ZERO(38) | CLK_TRAIL(22);
+ phy_timing
[PATCH 2/2 v16] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip. Signed-off-by: Jitao Shi Reviewed-by: Daniel Kurtz --- Changes since v15: - Drop drm_connector_(un)register calls from parade ps8640. The main DRM driver mtk_drm_drv now calls drm_connector_register_all() after drm_dev_register() in the mtk_drm_bind() function. That function should iterate over all connectors and call drm_connector_register() for each of them. So, remove drm_connector_(un)register calls from parade ps8640. Changes since v14: - update copyright info. - change bridge_to_ps8640 and connector_to_ps8640 to inline function. - fix some coding style. - use sizeof as array counter. - use drm_get_edid when read edid. - add mutex when firmware updating. Changes since v13: - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len) - fix PAGE2_SW_REST tyro. - move the buf[3] init to entrance of the function. Changes since v12: - fix hw_chip_id build warning Changes since v11: - Remove depends on I2C, add DRM depends - Reuse ps8640_write_bytes() in ps8640_write_byte() - Use timer check for polling like the routines in - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail - Check the ps8640 hardware id in ps8640_validate_firmware - Remove fw_version check - Move ps8640_validate_firmware before ps8640_enter_bl - Add ddc_i2c unregister when probe fail and ps8640_remove --- drivers/gpu/drm/bridge/Kconfig | 12 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/parade-ps8640.c | 1067 3 files changed, 1080 insertions(+) create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 8f7423f..02fea1a 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -50,6 +50,18 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on DRM + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + source "drivers/gpu/drm/bridge/analogix/Kconfig" endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 96b13b3..6c00b2f 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000..a73871e --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,1067 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define PAGE2_SPI_CFG3 0x82 +#define I2C_TO_SPI_RESET 0x20 +#define PAGE2_ROMADD_BYTE1 0x8e +#define PAGE2_ROMADD_BYTE2 0x8f +#define PAGE2_SWSPI_WDATA 0x90 +#define PAGE2_SWSPI_RDATA 0x91 +#define PAGE2_SWSPI_LEN0x92 +#define PAGE2_SWSPI_CTL0x93 +#define TRIGGER_NO_READBACK0x05 +#define TRIGGER_READBACK 0x01 +#define PAGE2_SPI_STATUS 0x9e +#define SPI_READY 0x0c +#define PAGE2_GPIO_L 0xa6 +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9 BIT(1) +#define PAGE2_IROM_CTRL0xb0 +#define IROM_ENABLE0xc0 +#define IROM_DISABLE 0x80 +#define PAGE2_SW_RESET 0xbc +#define SPI_SW_RESET BIT(7) +#define MPU_SW_RESET BIT(6) +#define PAGE2_ENCTLSPI_WR 0xda +#define PAGE2_I2C_BYPASS 0xea +#define I2C_BYPASS_EN 0xd0 +#define PAGE3_SET_ADD 0xfe +#define PAGE3_SET_VAL 0xff +#define VDO_CTL_ADD0x13 +#define VDO_DIS0x18 +#define VDO_EN
[PATCH 1/2 v16] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v15 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip. Signed-off-by: Jitao Shi Reviewed-by: Daniel Kurtz --- Changes since v14: - update copyright info. - change bridge_to_ps8640 and connector_to_ps8640 to inline function. - fix some coding style. - use sizeof as array counter. - use drm_get_edid when read edid. - add mutex when firmware updating. Changes since v13: - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len) - fix PAGE2_SW_REST tyro. - move the buf[3] init to entrance of the function. Changes since v12: - fix hw_chip_id build warning Changes since v11: - Remove depends on I2C, add DRM depends - Reuse ps8640_write_bytes() in ps8640_write_byte() - Use timer check for polling like the routines in - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail - Check the ps8640 hardware id in ps8640_validate_firmware - Remove fw_version check - Move ps8640_validate_firmware before ps8640_enter_bl - Add ddc_i2c unregister when probe fail and ps8640_remove --- drivers/gpu/drm/bridge/Kconfig | 12 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/parade-ps8640.c | 1076 3 files changed, 1089 insertions(+) create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 27e2022..be6084e 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -40,4 +40,16 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on DRM + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index f13c33d..fbe38dc 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000..a82ed6c --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,1076 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define PAGE2_SPI_CFG3 0x82 +#define I2C_TO_SPI_RESET 0x20 +#define PAGE2_ROMADD_BYTE1 0x8e +#define PAGE2_ROMADD_BYTE2 0x8f +#define PAGE2_SWSPI_WDATA 0x90 +#define PAGE2_SWSPI_RDATA 0x91 +#define PAGE2_SWSPI_LEN0x92 +#define PAGE2_SWSPI_CTL0x93 +#define TRIGGER_NO_READBACK0x05 +#define TRIGGER_READBACK 0x01 +#define PAGE2_SPI_STATUS 0x9e +#define SPI_READY 0x0c +#define PAGE2_GPIO_L 0xa6 +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9 BIT(1) +#define PAGE2_IROM_CTRL0xb0 +#define IROM_ENABLE0xc0 +#define IROM_DISABLE 0x80 +#define PAGE2_SW_RESET 0xbc +#define SPI_SW_RESET BIT(7) +#define MPU_SW_RESET BIT(6) +#define PAGE2_ENCTLSPI_WR 0xda +#define PAGE2_I2C_BYPASS 0xea +#define I2C_BYPASS_EN 0xd0 +#define PAGE3_SET_ADD 0xfe +#define PAGE3_SET_VAL 0xff +#define VDO_CTL_ADD0x13 +#define VDO_DIS0x18 +#define VDO_EN 0x1c +#define PAGE4_REV_L0xf0 +#define PAGE4_REV_H0xf1 +#define PAGE4_CHIP_L 0xf2 +#define PAGE4_CHIP_H 0xf3 + +/* Firmware */ +#define SPI_MAX_RETRY_CNT 8 +#define PS_FW_NAME "ps864x_fw.bin" + +#define FW_CHIP_ID_OFFSET 0 +#define FW_VERSION_OFFSET 2 +#define EDID_I2C_ADDR 0x50 + +#define WRITE_STATUS_REG_CMD 0x01 +#define READ_STATUS_REG_CMD
[PATCH v15 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
Re: [PATCH v14 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
On Thu, 2016-04-14 at 16:28 +0200, Thierry Reding wrote:
> On Sun, Apr 03, 2016 at 12:20:45PM +0800, Jitao Shi wrote:
> [...]
> > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
> > b/drivers/gpu/drm/bridge/parade-ps8640.c
> > new file mode 100644
> > index 000..87f8bc7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> > @@ -0,0 +1,1066 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
>
> Presumably the copyright here should be updated?
Thanks for your review. I'll update it next version.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define PAGE2_SPI_CFG3 0x82
> > +#define I2C_TO_SPI_RESET 0x20
> > +#define PAGE2_ROMADD_BYTE1 0x8e
> > +#define PAGE2_ROMADD_BYTE2 0x8f
> > +#define PAGE2_SWSPI_WDATA 0x90
> > +#define PAGE2_SWSPI_RDATA 0x91
> > +#define PAGE2_SWSPI_LEN0x92
> > +#define PAGE2_SWSPI_CTL0x93
> > +#define TRIGGER_NO_READBACK0x05
> > +#define TRIGGER_READBACK 0x01
> > +#define PAGE2_SPI_STATUS 0x9e
> > +#define PAGE2_GPIO_L 0xa6
> > +#define PAGE2_GPIO_H 0xa7
> > +#define PS_GPIO9 BIT(1)
> > +#define PAGE2_IROM_CTRL0xb0
> > +#define IROM_ENABLE0xc0
> > +#define IROM_DISABLE 0x80
> > +#define PAGE2_SW_RESET 0xbc
> > +#define SPI_SW_RESET BIT(7)
> > +#define MPU_SW_RESET BIT(6)
> > +#define PAGE2_ENCTLSPI_WR 0xda
> > +#define PAGE2_I2C_BYPASS 0xea
> > +#define I2C_BYPASS_EN 0xd0
> > +#define PAGE3_SET_ADD 0xfe
> > +#define PAGE3_SET_VAL 0xff
> > +#define VDO_CTL_ADD0x13
> > +#define VDO_DIS0x18
> > +#define VDO_EN 0x1c
> > +#define PAGE4_REV_L0xf0
> > +#define PAGE4_REV_H0xf1
> > +#define PAGE4_CHIP_L 0xf2
> > +#define PAGE4_CHIP_H 0xf3
> > +
> > +/* Firmware */
> > +#define SPI_MAX_RETRY_CNT 8
> > +#define PS_FW_NAME "ps864x_fw.bin"
> > +
> > +#define FW_CHIP_ID_OFFSET 0
> > +#define FW_VERSION_OFFSET 2
> > +#define EDID_I2C_ADDR 0x50
> > +
> > +#define WRITE_STATUS_REG_CMD 0x01
> > +#define READ_STATUS_REG_CMD0x05
> > +#define BUSY BIT(0)
> > +#define CLEAR_ALL_PROTECT 0x00
> > +#define BLK_PROTECT_BITS 0x0c
> > +#define STATUS_REG_PROTECT BIT(7)
> > +#define WRITE_ENABLE_CMD 0x06
> > +#define CHIP_ERASE_CMD 0xc7
> > +
> > +#define bridge_to_ps8640(e)container_of(e, struct ps8640, bridge)
> > +#define connector_to_ps8640(e) container_of(e, struct ps8640,
> > connector)
>
> I'd prefer these to be static inline functions.
I'll update it next version.
Thanks
>
> > +
> > +struct ps8640_info {
> > + u8 family_id;
> > + u8 variant_id;
> > + u16 version;
> > +};
> > +
> > +struct ps8640 {
> > + struct drm_connector connector;
> > + struct drm_bridge bridge;
> > + struct edid *edid;
> > + struct mipi_dsi_device dsi;
> > + struct i2c_client *page[8];
> > + struct i2c_client *ddc_i2c;
> > + struct regulator_bulk_data supplies[2];
> > + struct drm_panel *panel;
> > + struct gpio_desc *gpio_rst_n;
> > + struct gpio_desc *gpio_slp_n;
> > + struct gpio_desc *gpio_mode_sel_n;
> > + bool enabled;
> > +
> > + /* firmware file info */
> > + bool in_fw_update;
> > + struct ps8640_info info;
> > +};
> > +
> > +static const u8 enc_ctrl_code[6] = {0xaa, 0x55, 0x50, 0x41, 0x52, 0x44};
> > +static const u8 hw_chip_id[4] = {0x00, 0x0a, 0x00, 0x30};
>
> Spaces after { and before }, please.
I'll fix them next version, thanks.
> > +
> > +static int ps8640_read(struct i2c_client *client, u8 reg, u8 *data,
> > + u16 data_len)
> > +{
> > + int ret;
> > + struct i2c_msg msgs[] = {
> > + {
> > +.addr = client->addr,
> > +.flags = 0,
> > +
[PATCH v14 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v13:
- No change
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..022b33f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,43 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v14 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip. Signed-off-by: Jitao Shi Reviewed-by: Daniel Kurtz --- Changes since v13: - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len) - fix PAGE2_SW_REST tyro. - move the buf[3] init to entrance of the function. Changes since v12: - fix hw_chip_id build warning Changes since v11: - Remove depends on I2C, add DRM depends - Reuse ps8640_write_bytes() in ps8640_write_byte() - Use timer check for polling like the routines in - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail - Check the ps8640 hardware id in ps8640_validate_firmware - Remove fw_version check - Move ps8640_validate_firmware before ps8640_enter_bl - Add ddc_i2c unregister when probe fail and ps8640_remove --- drivers/gpu/drm/bridge/Kconfig | 12 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/parade-ps8640.c | 1066 3 files changed, 1079 insertions(+) create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 27e2022..be6084e 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -40,4 +40,16 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on DRM + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index f13c33d..fbe38dc 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000..87f8bc7 --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,1066 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define PAGE2_SPI_CFG3 0x82 +#define I2C_TO_SPI_RESET 0x20 +#define PAGE2_ROMADD_BYTE1 0x8e +#define PAGE2_ROMADD_BYTE2 0x8f +#define PAGE2_SWSPI_WDATA 0x90 +#define PAGE2_SWSPI_RDATA 0x91 +#define PAGE2_SWSPI_LEN0x92 +#define PAGE2_SWSPI_CTL0x93 +#define TRIGGER_NO_READBACK0x05 +#define TRIGGER_READBACK 0x01 +#define PAGE2_SPI_STATUS 0x9e +#define PAGE2_GPIO_L 0xa6 +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9 BIT(1) +#define PAGE2_IROM_CTRL0xb0 +#define IROM_ENABLE0xc0 +#define IROM_DISABLE 0x80 +#define PAGE2_SW_RESET 0xbc +#define SPI_SW_RESET BIT(7) +#define MPU_SW_RESET BIT(6) +#define PAGE2_ENCTLSPI_WR 0xda +#define PAGE2_I2C_BYPASS 0xea +#define I2C_BYPASS_EN 0xd0 +#define PAGE3_SET_ADD 0xfe +#define PAGE3_SET_VAL 0xff +#define VDO_CTL_ADD0x13 +#define VDO_DIS0x18 +#define VDO_EN 0x1c +#define PAGE4_REV_L0xf0 +#define PAGE4_REV_H0xf1 +#define PAGE4_CHIP_L 0xf2 +#define PAGE4_CHIP_H 0xf3 + +/* Firmware */ +#define SPI_MAX_RETRY_CNT 8 +#define PS_FW_NAME "ps864x_fw.bin" + +#define FW_CHIP_ID_OFFSET 0 +#define FW_VERSION_OFFSET 2 +#define EDID_I2C_ADDR 0x50 + +#define WRITE_STATUS_REG_CMD 0x01 +#define READ_STATUS_REG_CMD0x05 +#define BUSY BIT(0) +#define CLEAR_ALL_PROTECT 0x00 +#define BLK_PROTECT_BITS 0x0c +#define STATUS_REG_PROTECT BIT(7) +#define WRITE_ENABLE_CMD 0x06 +#define CHIP_ERASE_CMD 0xc7 + +#define bridge_to_ps8640(e)container_of(e, struct ps86
[PATCH v13 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
---
Changes since v12:
- fix hw_chip_id build warning
Changes since v11:
- Remove depends on I2C, add DRM depends
- Reuse ps8640_write_bytes() in ps8640_write_byte()
- Use timer check for polling like the routines in
- Fix no drm_connector_unregister/drm_connector_cleanup when
ps8640_bridge_attach fail
- Check the ps8640 hardware id in ps8640_validate_firmware
- Remove fw_version check
- Move ps8640_validate_firmware before ps8640_enter_bl
- Add ddc_i2c unregister when probe fail and ps8640_remove
The following patches are needed to support dsi host through none dsi bus:
https://patchwork.kernel.org/patch/8289181/ ("drm/dsi: check for CONFIG_OF when
defining")
https://patchwork.kernel.org/patch/8289051/ ("drm/dsi: Use
mipi_dsi_device_register_full for DSI device")
https://patchwork.kernel.org/patch/8289081/ ("drm/dsi: Try to match non-DT DSI
devices")
https://patchwork.kernel.org/patch/8289121/ ("drm/dsi: Add routine to
unregister a DSI device")
https://patchwork.kernel.org/patch/8289091/ ("drm/dsi: Get DSI host by DT
device node")
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile|1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1073
3 files changed, 1086 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 27e2022..be6084e 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -40,4 +40,16 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on DRM
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index f13c33d..fbe38dc 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 000..7bd5c12
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1073 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN0x92
+#define PAGE2_SWSPI_CTL0x93
+#define TRIGGER_NO_READBACK0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL0xb0
+#define IROM_ENABLE0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_REST 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD0x13
+#define VDO_DIS0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L0xf0
+#define PAGE4_REV_H0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+/* Firmware */
+#define SPI_MAX_RETRY_CNT 8
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_
[PATCH v12 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
---
Changes since v11:
- Remove depends on I2C, add DRM depends
- Reuse ps8640_write_bytes() in ps8640_write_byte()
- Use timer check for polling like the routines in
- Fix no drm_connector_unregister/drm_connector_cleanup when
ps8640_bridge_attach fail
- Check the ps8640 hardware id in ps8640_validate_firmware
- Remove fw_version check
- Move ps8640_validate_firmware before ps8640_enter_bl
- Add ddc_i2c unregister when probe fail and ps8640_remove
The following patches are needed to support dsi host through none dsi bus:
https://patchwork.kernel.org/patch/8289181/ ("drm/dsi: check for CONFIG_OF when
defining")
https://patchwork.kernel.org/patch/8289051/ ("drm/dsi: Use
mipi_dsi_device_register_full for DSI device")
https://patchwork.kernel.org/patch/8289081/ ("drm/dsi: Try to match non-DT DSI
devices")
https://patchwork.kernel.org/patch/8289121/ ("drm/dsi: Add routine to
unregister a DSI device")
https://patchwork.kernel.org/patch/8289091/ ("drm/dsi: Get DSI host by DT
device node")
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile|1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1073
3 files changed, 1086 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 27e2022..be6084e 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -40,4 +40,16 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on DRM
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index f13c33d..fbe38dc 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 000..d7700e2
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1073 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN0x92
+#define PAGE2_SWSPI_CTL0x93
+#define TRIGGER_NO_READBACK0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL0xb0
+#define IROM_ENABLE0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_REST 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD0x13
+#define VDO_DIS0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L0xf0
+#define PAGE4_REV_H0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+/* Firmware */
+#define SPI_MAX_RETRY_CNT 8
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_I2C_ADDR 0x50
+
+#define WRITE_STATUS_REG_CMD 0x01
+#de
[PATCH v13 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v12:
- No change
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..022b33f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,43 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v12 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Changes since v11:
- No change
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..022b33f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,43 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v11 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Chnages since v10:
- set sleep reset pin as GPIO_ACTIVE_LOW
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 000..022b33f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,43 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
[PATCH v11 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
---
Changes since v10:
- Tuning PS8640 reset sleep pins squence
The following patches are needed to support dsi host through none dsi bus:
https://patchwork.kernel.org/patch/8289181/ ("drm/dsi: check for CONFIG_OF when
defining")
https://patchwork.kernel.org/patch/8289051/ ("drm/dsi: Use
mipi_dsi_device_register_full for DSI device")
https://patchwork.kernel.org/patch/8289081/ ("drm/dsi: Try to match non-DT DSI
devices")
https://patchwork.kernel.org/patch/8289121/ ("drm/dsi: Add routine to
unregister a DSI device")
https://patchwork.kernel.org/patch/8289091/ ("drm/dsi: Get DSI host by DT
device node")
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile|1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1060
3 files changed, 1072 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 27e2022..b4edd8c 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -40,4 +40,15 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on OF && I2C
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index f13c33d..fbe38dc 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 000..d7410df
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1060 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN0x92
+#define PAGE2_SWSPI_CTL0x93
+#define TRIGGER_NO_READBACK0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL0xb0
+#define IROM_ENABLE0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_REST 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD0x13
+#define VDO_DIS0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L0xf0
+#define PAGE4_REV_H0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+/* Firmware */
+#define SPI_MAX_RETRY_CNT 8
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_I2C_ADDR 0x50
+
+#define WRITE_STATUS_REG_CMD 0x01
+#define READ_STATUS_REG_CMD0x05
+#define CLEAR_ALL_PROTECT 0x00
+#define BLK_PROTECT_BITS 0x0c
+#define STATUS_REG_PROTECT BIT(7)
+#define WRITE_ENABLE_CMD 0x06
+#define CHIP_ERASE_CMD 0xc7
+
+#define bridge_to_ps8640(e)container_of(e, struct ps8640, bridge)
+#define connector_to_ps8640(e) container_of(e, struct ps8640, connector)
+
+struct ps8640_info {
+
[PATCH v2 1/2] dt-bindings: Add LG lp120up1 panel bindings
Add documentation for lp120up1 panel Signed-off-by: Jitao Shi Acked-by: Rob Herring --- Changes since v1: - add Acked-by: Rob Herring --- .../bindings/display/panel/lg,lp120up1.txt |7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt b/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt new file mode 100644 index 000..8c5de69 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt @@ -0,0 +1,7 @@ +LG 12.0" (1920x1280 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lp120up1" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 1.7.9.5
[PATCH v2 2/2] drm/panel: Support for LG lp120up1 panel with eDP input
The LG lp120up1 TFT LCD panel with eDP interface is a 12.0" 1920x1280
panel, which can be supported by the simple panel driver
Signed-off-by: Jitao Shi
---
Changes since v1:
- Add eDP panel type in comment msg
- Fixed comment msg with 72 characters width
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index f88a631..2030c37 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -982,6 +982,29 @@ static const struct panel_desc lg_lb070wv8 = {
.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
};
+static const struct drm_display_mode lg_lp120up1_mode = {
+ .clock = 162300,
+ .hdisplay = 1920,
+ .hsync_start = 1920 + 40,
+ .hsync_end = 1920 + 40 + 40,
+ .htotal = 1920 + 40 + 40+ 80,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 4,
+ .vsync_end = 1280 + 4 + 4,
+ .vtotal = 1280 + 4 + 4 + 12,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc lg_lp120up1 = {
+ .modes = &lg_lp120up1_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 267,
+ .height = 183,
+ },
+};
+
static const struct drm_display_mode lg_lp129qe_mode = {
.clock = 285250,
.hdisplay = 2560,
@@ -1256,6 +1279,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "lg,lb070wv8",
.data = &lg_lb070wv8,
}, {
+ .compatible = "lg,lp120up1",
+ .data = &lg_lp120up1,
+ }, {
.compatible = "lg,lp129qe",
.data = &lg_lp129qe,
}, {
--
1.7.9.5
