[PATCH 3/3] ARM: BCM: Add SMP support for Broadcom NSP
Add SMP support for Broadcom's Northstar Plus SoC,
cpu enable method and pen_release procedures. This
changes also consolidates iProc family's - BCM NSP
and BCM Kona, SMP handling in a common file.
Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.
Signed-off-by: Kapil Hali <kap...@broadcom.com>
---
arch/arm/mach-bcm/Kconfig | 2 +
arch/arm/mach-bcm/Makefile | 8 +-
arch/arm/mach-bcm/bcm_nsp.h | 19
arch/arm/mach-bcm/headsmp.S | 37
arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 142 ++--
5 files changed, 197 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
create mode 100644 arch/arm/mach-bcm/headsmp.S
rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1679fa4..2e9dbb5 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
select ARCH_BCM_IPROC
select ARM_ERRATA_754322
select ARM_ERRATA_775420
+ select ARM_ERRATA_764369 if SMP
+ select HAVE_SMP
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..36a4ca30 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
# Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+endif
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
# BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
# BCM281XX and BCM21664 L2 cache control
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/bcm_nsp.h b/arch/arm/mach-bcm/bcm_nsp.h
new file mode 100644
index 000..58e1e80
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_nsp.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BCM_NSP_H
+#define __BCM_NSP_H
+
+extern void nsp_secondary_startup(void);
+
+#endif /* __BCM_NSP_H */
diff --git a/arch/arm/mach-bcm/headsmp.S b/arch/arm/mach-bcm/headsmp.S
new file mode 100644
index 000..0da13b2
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+
+/*
+ * iProc specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until
+ * we are ready for them to initialise.
+ */
+ENTRY(nsp_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ bsecondary_startup
+
+1: .long .
+ .long pen_release
+
+ENDPROC(nsp_secondary_startup)
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 63%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 66a0465..619030e 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
@@ -12,16 +12,23 @@
* GNU General Public License for more details.
*/
-#include
[PATCH 0/3] SMP support for Broadcom NSP
Hi,
This series adds SMP support for Broadcom's Northstar Plus SoC.
There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.
The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.
The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.
The second patch adds SMP support to the BCM NSP device tree file.
Finally, third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.
This patch series is constructed based on Linux v4.3-rc2.
The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1
Kapil Hali (3):
dt-bindings: add SMP enable-method for Broadcom NSP
ARM: dts: add SMP support for Broadcom NSP
ARM: BCM: Add SMP support for Broadcom NSP
.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 ++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++--
arch/arm/mach-bcm/Kconfig | 2 +
arch/arm/mach-bcm/Makefile | 8 +-
arch/arm/mach-bcm/bcm_nsp.h| 19 +++
arch/arm/mach-bcm/headsmp.S| 37 ++
arch/arm/mach-bcm/{kona_smp.c => platsmp.c}| 142 +++--
8 files changed, 255 insertions(+), 23 deletions(-)
create mode 100644
Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
create mode 100644 arch/arm/mach-bcm/headsmp.S
rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
--
2.1.0
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[PATCH 2/3] ARM: dts: add SMP support for Broadcom NSP
Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.
Signed-off-by: Kapil Hali <kap...@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d1875d9 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0x042c>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x1>;
+ };
+ };
+
mpcore {
compatible = "simple-bus";
ranges = <0x 0x1902 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <>;
- reg = <0x0>;
- };
- };
-
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
--
2.1.0
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[PATCH 1/3] dt-bindings: add SMP enable-method for Broadcom NSP
Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU pen-release mechanism.
Signed-off-by: Kapil Hali <kap...@broadcom.com>
---
.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 ++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 37 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 000..8506da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+-
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+ - enable-method = "brcm,bcm-nsp-smp";
+ - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0x042c>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..1172d9b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -190,6 +190,7 @@ nodes to be present and contain the properties described
below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,psci"
+ "brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
"marvell,armada-380-smp"
--
2.1.0
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