Re: [PATCH V2] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Hello Kgene,

Can you please pick this patch to your tree ?

Best Wishes,
Leela Krishna.

On Wed, Apr 30, 2014 at 1:32 PM, Chanwoo Choi  wrote:
> Hi,
>
> On 04/23/2014 02:52 PM, Leela Krishna Amudala wrote:
>> A common macro v7_exit_coherency_flush available which does the below tasks 
>> in
>> the seqeunce.
>> -clearing C bit
>> -clearing L1 cache
>> -exit SMP
>> -instruction and data synchronization
>>
>> So removing the local functions which does the same thing and use the macro 
>> instead.
>>
>> Signed-off-by: Leela Krishna Amudala 
>> Acked-by: Nicolas Pitre 
>> ---
>> Changes since V1:
>>   - removed unwanted primary_part variable in exynos_cpu_die()
>>   - given more description in commit message
>> suggested by Daniel Lezcano 
>>
>>  arch/arm/mach-exynos/hotplug.c |   63 
>> +---
>>  1 file changed, 1 insertion(+), 62 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..9ca692d 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -24,56 +24,6 @@
>>  #include "common.h"
>>  #include "regs-pmu.h"
>>
>> -static inline void cpu_enter_lowpower_a9(void)
>> -{
>> - unsigned int v;
>> -
>> - asm volatile(
>> - "   mcr p15, 0, %1, c7, c5, 0\n"
>> - "   mcr p15, 0, %1, c7, c10, 4\n"
>> - /*
>> -  * Turn off coherency
>> -  */
>> - "   mrc p15, 0, %0, c1, c0, 1\n"
>> - "   bic %0, %0, %3\n"
>> - "   mcr p15, 0, %0, c1, c0, 1\n"
>> - "   mrc p15, 0, %0, c1, c0, 0\n"
>> - "   bic %0, %0, %2\n"
>> - "   mcr p15, 0, %0, c1, c0, 0\n"
>> -   : "=" (v)
>> -   : "r" (0), "Ir" (CR_C), "Ir" (0x40)
>> -   : "cc");
>> -}
>> -
>> -static inline void cpu_enter_lowpower_a15(void)
>> -{
>> - unsigned int v;
>> -
>> - asm volatile(
>> - "   mrc p15, 0, %0, c1, c0, 0\n"
>> - "   bic %0, %0, %1\n"
>> - "   mcr p15, 0, %0, c1, c0, 0\n"
>> -   : "=" (v)
>> -   : "Ir" (CR_C)
>> -   : "cc");
>> -
>> - flush_cache_louis();
>> -
>> - asm volatile(
>> - /*
>> - * Turn off coherency
>> - */
>> - "   mrc p15, 0, %0, c1, c0, 1\n"
>> - "   bic %0, %0, %1\n"
>> - "   mcr p15, 0, %0, c1, c0, 1\n"
>> - : "=" (v)
>> - : "Ir" (0x40)
>> - : "cc");
>> -
>> - isb();
>> - dsb();
>> -}
>> -
>>  static inline void cpu_leave_lowpower(void)
>>  {
>>   unsigned int v;
>> @@ -132,19 +82,8 @@ static inline void platform_do_lowpower(unsigned int 
>> cpu, int *spurious)
>>  void __ref exynos_cpu_die(unsigned int cpu)
>>  {
>>   int spurious = 0;
>> - int primary_part = 0;
>>
>> - /*
>> -  * we're ready for shutdown now, so do it.
>> -  * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> -  * number by reading the Main ID register and then perform the
>> -  * appropriate sequence for entering low power.
>> -  */
>> - asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> - if ((primary_part & 0xfff0) == 0xc0f0)
>> - cpu_enter_lowpower_a15();
>> - else
>> - cpu_enter_lowpower_a9();
>> + v7_exit_coherency_flush(louis);
>>
>>   platform_do_lowpower(cpu, );
>>
>>
>
> I tested this patch on Exynos3250 based on Cortex-A7 dual core.
>
> Tested-by: Chanwoo Choi 
>
> Thanks,
> Chanwoo Choi
>
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Re: [PATCH V2] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Hello Kgene,

Can you please pick this patch to your tree ?

Best Wishes,
Leela Krishna.

On Wed, Apr 30, 2014 at 1:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
 Hi,

 On 04/23/2014 02:52 PM, Leela Krishna Amudala wrote:
 A common macro v7_exit_coherency_flush available which does the below tasks 
 in
 the seqeunce.
 -clearing C bit
 -clearing L1 cache
 -exit SMP
 -instruction and data synchronization

 So removing the local functions which does the same thing and use the macro 
 instead.

 Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
 Acked-by: Nicolas Pitre n...@linaro.org
 ---
 Changes since V1:
   - removed unwanted primary_part variable in exynos_cpu_die()
   - given more description in commit message
 suggested by Daniel Lezcano daniel.lezc...@linaro.org

  arch/arm/mach-exynos/hotplug.c |   63 
 +---
  1 file changed, 1 insertion(+), 62 deletions(-)

 diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..9ca692d 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -24,56 +24,6 @@
  #include common.h
  #include regs-pmu.h

 -static inline void cpu_enter_lowpower_a9(void)
 -{
 - unsigned int v;
 -
 - asm volatile(
 -mcr p15, 0, %1, c7, c5, 0\n
 -mcr p15, 0, %1, c7, c10, 4\n
 - /*
 -  * Turn off coherency
 -  */
 -mrc p15, 0, %0, c1, c0, 1\n
 -bic %0, %0, %3\n
 -mcr p15, 0, %0, c1, c0, 1\n
 -mrc p15, 0, %0, c1, c0, 0\n
 -bic %0, %0, %2\n
 -mcr p15, 0, %0, c1, c0, 0\n
 -   : =r (v)
 -   : r (0), Ir (CR_C), Ir (0x40)
 -   : cc);
 -}
 -
 -static inline void cpu_enter_lowpower_a15(void)
 -{
 - unsigned int v;
 -
 - asm volatile(
 -mrc p15, 0, %0, c1, c0, 0\n
 -bic %0, %0, %1\n
 -mcr p15, 0, %0, c1, c0, 0\n
 -   : =r (v)
 -   : Ir (CR_C)
 -   : cc);
 -
 - flush_cache_louis();
 -
 - asm volatile(
 - /*
 - * Turn off coherency
 - */
 -mrc p15, 0, %0, c1, c0, 1\n
 -bic %0, %0, %1\n
 -mcr p15, 0, %0, c1, c0, 1\n
 - : =r (v)
 - : Ir (0x40)
 - : cc);
 -
 - isb();
 - dsb();
 -}
 -
  static inline void cpu_leave_lowpower(void)
  {
   unsigned int v;
 @@ -132,19 +82,8 @@ static inline void platform_do_lowpower(unsigned int 
 cpu, int *spurious)
  void __ref exynos_cpu_die(unsigned int cpu)
  {
   int spurious = 0;
 - int primary_part = 0;

 - /*
 -  * we're ready for shutdown now, so do it.
 -  * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
 -  * number by reading the Main ID register and then perform the
 -  * appropriate sequence for entering low power.
 -  */
 - asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc);
 - if ((primary_part  0xfff0) == 0xc0f0)
 - cpu_enter_lowpower_a15();
 - else
 - cpu_enter_lowpower_a9();
 + v7_exit_coherency_flush(louis);

   platform_do_lowpower(cpu, spurious);



 I tested this patch on Exynos3250 based on Cortex-A7 dual core.

 Tested-by: Chanwoo Choi cw00.c...@samsung.com

 Thanks,
 Chanwoo Choi

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Re: [PATCH 0/2] Add generic cpu power control functions for exynos

[Leela Krishna Amudala]

Hi Abhilash,

If you are okay with this patchset you can rebase/merge it with your
mcpm patches.

Best Wishes,
Leela Krishna.

On Thu, Apr 24, 2014 at 3:24 PM, Daniel Lezcano
 wrote:
>
> Hi Abhilash and Leela,
>
> FYI I think you are working on similar patches.
>
>
> On 04/24/2014 11:31 AM, Leela Krishna Amudala wrote:
>> This patchset adds the generic cpu power control functions for
>>
>> exynos based SoCs to power up/down and to know the status of the cpu.
>>
>> Note: This series has been rebased on 3.15-rc1 and tested on
>> Exynos based Origen(Cortex-A9) and Arndale-octa(Cortex A7,A15) boards.
>>
>> Leela Krishna Amudala (2):
>>ARM: EXYNOS: Add generic cpu power control functions for all exynos
>>  based SoCs
>>ARM: EXYNOS: use generic exynos cpu power control functions
>>
>>   arch/arm/mach-exynos/common.h   |3 +++
>>   arch/arm/mach-exynos/platsmp.c  |9 +++--
>>   arch/arm/mach-exynos/pm.c   |   36
>> 
>>   arch/arm/mach-exynos/regs-pmu.h |6 ++
>>   4 files changed, 48 insertions(+), 6 deletions(-)
>>
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
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[PATCH 1/2] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Leela Krishna Amudala]

Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know the cpu status.

Signed-off-by: Leela Krishna Amudala 
---
 arch/arm/mach-exynos/common.h   |3 +++
 arch/arm/mach-exynos/pm.c   |   36 
 arch/arm/mach-exynos/regs-pmu.h |6 ++
 3 files changed, 45 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..566f222 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -62,5 +62,8 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_powerdown(int cpu);
+extern void exynos_cpu_powerup(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ce..6651028 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, 
unsigned int state)
return -ENOENT;
 }
 
+/**
+ * exynos_cpu_powerdown : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power downs the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_powerdown(int cpu)
+{
+   __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_powerup : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_powerup(int cpu)
+{
+   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+   return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+   S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..0bdfcbc 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -121,6 +121,12 @@
 
 #define S5P_CHECK_SLEEP0x0BAD
 
+#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
+   (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)\
+   (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWRS5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR  S5P_PMUREG(0x1174)
-- 
1.7.9.5

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[PATCH 0/2] Add generic cpu power control functions for exynos

[Leela Krishna Amudala]

This patchset adds the generic cpu power control functions for
exynos based SoCs to power up/down and to know the status of the cpu.

Note: This series has been rebased on 3.15-rc1 and tested on 
Exynos based Origen(Cortex-A9) and Arndale-octa(Cortex A7,A15) boards.

Leela Krishna Amudala (2):
  ARM: EXYNOS: Add generic cpu power control functions for all exynos
based SoCs
  ARM: EXYNOS: use generic exynos cpu power control functions

 arch/arm/mach-exynos/common.h   |3 +++
 arch/arm/mach-exynos/platsmp.c  |9 +++--
 arch/arm/mach-exynos/pm.c   |   36 
 arch/arm/mach-exynos/regs-pmu.h |6 ++
 4 files changed, 48 insertions(+), 6 deletions(-)

-- 
1.7.9.5

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[PATCH 2/2] ARM: EXYNOS: use generic exynos cpu power control functions

[Leela Krishna Amudala]

Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu.

Signed-off-by: Leela Krishna Amudala 
---
 arch/arm/mach-exynos/platsmp.c |9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..e3d005b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -107,15 +107,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
-
+   if (!exynos_cpu_power_state(cpu)) {
+   exynos_cpu_powerup(cpu);
timeout = 10;
 
/* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-   & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+   while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
 
-- 
1.7.9.5

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[PATCH 2/2] ARM: EXYNOS: use generic exynos cpu power control functions

[Leela Krishna Amudala]

Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu.

Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
---
 arch/arm/mach-exynos/platsmp.c |9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..e3d005b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -107,15 +107,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN)) {
-   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
-
+   if (!exynos_cpu_power_state(cpu)) {
+   exynos_cpu_powerup(cpu);
timeout = 10;
 
/* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+   while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
 
-- 
1.7.9.5

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[PATCH 0/2] Add generic cpu power control functions for exynos

[Leela Krishna Amudala]

This patchset adds the generic cpu power control functions for
exynos based SoCs to power up/down and to know the status of the cpu.

Note: This series has been rebased on 3.15-rc1 and tested on 
Exynos based Origen(Cortex-A9) and Arndale-octa(Cortex A7,A15) boards.

Leela Krishna Amudala (2):
  ARM: EXYNOS: Add generic cpu power control functions for all exynos
based SoCs
  ARM: EXYNOS: use generic exynos cpu power control functions

 arch/arm/mach-exynos/common.h   |3 +++
 arch/arm/mach-exynos/platsmp.c  |9 +++--
 arch/arm/mach-exynos/pm.c   |   36 
 arch/arm/mach-exynos/regs-pmu.h |6 ++
 4 files changed, 48 insertions(+), 6 deletions(-)

-- 
1.7.9.5

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[PATCH 1/2] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Leela Krishna Amudala]

Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know the cpu status.

Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
---
 arch/arm/mach-exynos/common.h   |3 +++
 arch/arm/mach-exynos/pm.c   |   36 
 arch/arm/mach-exynos/regs-pmu.h |6 ++
 3 files changed, 45 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..566f222 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -62,5 +62,8 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_powerdown(int cpu);
+extern void exynos_cpu_powerup(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ce..6651028 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, 
unsigned int state)
return -ENOENT;
 }
 
+/**
+ * exynos_cpu_powerdown : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power downs the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_powerdown(int cpu)
+{
+   __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_powerup : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_powerup(int cpu)
+{
+   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+   return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) 
+   S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..0bdfcbc 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -121,6 +121,12 @@
 
 #define S5P_CHECK_SLEEP0x0BAD
 
+#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
+   (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)\
+   (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWRS5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR  S5P_PMUREG(0x1174)
-- 
1.7.9.5

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Re: [PATCH 0/2] Add generic cpu power control functions for exynos

[Leela Krishna Amudala]

Hi Abhilash,

If you are okay with this patchset you can rebase/merge it with your
mcpm patches.

Best Wishes,
Leela Krishna.

On Thu, Apr 24, 2014 at 3:24 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:

 Hi Abhilash and Leela,

 FYI I think you are working on similar patches.


 On 04/24/2014 11:31 AM, Leela Krishna Amudala wrote:
 This patchset adds the generic cpu power control functions for

 exynos based SoCs to power up/down and to know the status of the cpu.

 Note: This series has been rebased on 3.15-rc1 and tested on
 Exynos based Origen(Cortex-A9) and Arndale-octa(Cortex A7,A15) boards.

 Leela Krishna Amudala (2):
ARM: EXYNOS: Add generic cpu power control functions for all exynos
  based SoCs
ARM: EXYNOS: use generic exynos cpu power control functions

   arch/arm/mach-exynos/common.h   |3 +++
   arch/arm/mach-exynos/platsmp.c  |9 +++--
   arch/arm/mach-exynos/pm.c   |   36
 
   arch/arm/mach-exynos/regs-pmu.h |6 ++
   4 files changed, 48 insertions(+), 6 deletions(-)



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[PATCH V2] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

A common macro v7_exit_coherency_flush available which does the below tasks in
the seqeunce.
-clearing C bit
-clearing L1 cache
-exit SMP
-instruction and data synchronization

So removing the local functions which does the same thing and use the macro 
instead.

Signed-off-by: Leela Krishna Amudala 
Acked-by: Nicolas Pitre 
---
Changes since V1:
- removed unwanted primary_part variable in exynos_cpu_die()
- given more description in commit message
  suggested by Daniel Lezcano 

 arch/arm/mach-exynos/hotplug.c |   63 +---
 1 file changed, 1 insertion(+), 62 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9ca692d 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -24,56 +24,6 @@
 #include "common.h"
 #include "regs-pmu.h"
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-   unsigned int v;
-
-   asm volatile(
-   "   mcr p15, 0, %1, c7, c5, 0\n"
-   "   mcr p15, 0, %1, c7, c10, 4\n"
-   /*
-* Turn off coherency
-*/
-   "   mrc p15, 0, %0, c1, c0, 1\n"
-   "   bic %0, %0, %3\n"
-   "   mcr p15, 0, %0, c1, c0, 1\n"
-   "   mrc p15, 0, %0, c1, c0, 0\n"
-   "   bic %0, %0, %2\n"
-   "   mcr p15, 0, %0, c1, c0, 0\n"
- : "=" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-   unsigned int v;
-
-   asm volatile(
-   "   mrc p15, 0, %0, c1, c0, 0\n"
-   "   bic %0, %0, %1\n"
-   "   mcr p15, 0, %0, c1, c0, 0\n"
- : "=" (v)
- : "Ir" (CR_C)
- : "cc");
-
-   flush_cache_louis();
-
-   asm volatile(
-   /*
-   * Turn off coherency
-   */
-   "   mrc p15, 0, %0, c1, c0, 1\n"
-   "   bic %0, %0, %1\n"
-   "   mcr p15, 0, %0, c1, c0, 1\n"
-   : "=" (v)
-   : "Ir" (0x40)
-   : "cc");
-
-   isb();
-   dsb();
-}
-
 static inline void cpu_leave_lowpower(void)
 {
unsigned int v;
@@ -132,19 +82,8 @@ static inline void platform_do_lowpower(unsigned int cpu, 
int *spurious)
 void __ref exynos_cpu_die(unsigned int cpu)
 {
int spurious = 0;
-   int primary_part = 0;
 
-   /*
-* we're ready for shutdown now, so do it.
-* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
-* number by reading the Main ID register and then perform the
-* appropriate sequence for entering low power.
-*/
-   asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-   if ((primary_part & 0xfff0) == 0xc0f0)
-   cpu_enter_lowpower_a15();
-   else
-   cpu_enter_lowpower_a9();
+   v7_exit_coherency_flush(louis);
 
platform_do_lowpower(cpu, );
 
-- 
1.7.9.5

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Re: [PATCH] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Hi Daniel,

Thanks for reviewing the patch.

On Tue, Apr 22, 2014 at 8:06 PM, Daniel Lezcano
 wrote:
> On 04/22/2014 04:18 PM, Leela Krishna Amudala wrote:
>>
>> Remove the duplicated code for cache disabling and use
>> "v7_exit_coherency_flush"
>> macro to do the same job.
>
>
> Hi Leela,
>
> thanks for this patch! It would be nice if you can describe why those macros
> can be replaced by the generic v7_exit_coherency_flush macro.
>

Okay, will give the description in commit message

>
>>
>> Signed-off-by: Leela Krishna Amudala 
>>
>> ---
>> cpu hotplug is tested with 3.15-rc1 on Origen(which has cortex A9) and
>> Arndale octa(which has cortex A7 and A15) boards.
>>
>>   arch/arm/mach-exynos/hotplug.c |   56
>> ++--
>>   1 file changed, 2 insertions(+), 54 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c
>> b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..9eb8d1b 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -24,56 +24,6 @@
>>   #include "common.h"
>>   #include "regs-pmu.h"
>>
>> -static inline void cpu_enter_lowpower_a9(void)
>> -{
>> -   unsigned int v;
>> -
>> -   asm volatile(
>> -   "   mcr p15, 0, %1, c7, c5, 0\n"
>> -   "   mcr p15, 0, %1, c7, c10, 4\n"
>> -   /*
>> -* Turn off coherency
>> -*/
>> -   "   mrc p15, 0, %0, c1, c0, 1\n"
>> -   "   bic %0, %0, %3\n"
>> -   "   mcr p15, 0, %0, c1, c0, 1\n"
>> -   "   mrc p15, 0, %0, c1, c0, 0\n"
>> -   "   bic %0, %0, %2\n"
>> -   "   mcr p15, 0, %0, c1, c0, 0\n"
>> - : "=" (v)
>> - : "r" (0), "Ir" (CR_C), "Ir" (0x40)
>> - : "cc");
>> -}
>> -
>> -static inline void cpu_enter_lowpower_a15(void)
>> -{
>> -   unsigned int v;
>> -
>> -   asm volatile(
>> -   "   mrc p15, 0, %0, c1, c0, 0\n"
>> -   "   bic %0, %0, %1\n"
>> -   "   mcr p15, 0, %0, c1, c0, 0\n"
>> - : "=" (v)
>> - : "Ir" (CR_C)
>> - : "cc");
>> -
>> -   flush_cache_louis();
>> -
>> -   asm volatile(
>> -   /*
>> -   * Turn off coherency
>> -   */
>> -   "   mrc p15, 0, %0, c1, c0, 1\n"
>> -   "   bic %0, %0, %1\n"
>> -   "   mcr p15, 0, %0, c1, c0, 1\n"
>> -   : "=" (v)
>> -   : "Ir" (0x40)
>> -   : "cc");
>> -
>> -   isb();
>> -   dsb();
>> -}
>> -
>>   static inline void cpu_leave_lowpower(void)
>>   {
>> unsigned int v;
>> @@ -141,10 +91,8 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>  * appropriate sequence for entering low power.
>>  */
>> asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>
>
> Can't you remove this asm line above as well as the primary_part variable ?

Didn't notice it, will remove this.

>
>
>> -   if ((primary_part & 0xfff0) == 0xc0f0)
>> -   cpu_enter_lowpower_a15();
>> -   else
>> -   cpu_enter_lowpower_a9();
>> +
>> +   v7_exit_coherency_flush(louis);
>>
>> platform_do_lowpower(cpu, );
>>
>>
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
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[PATCH] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Remove the duplicated code for cache disabling and use "v7_exit_coherency_flush"
macro to do the same job.

Signed-off-by: Leela Krishna Amudala 

---
cpu hotplug is tested with 3.15-rc1 on Origen(which has cortex A9) and
Arndale octa(which has cortex A7 and A15) boards.

 arch/arm/mach-exynos/hotplug.c |   56 ++--
 1 file changed, 2 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9eb8d1b 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -24,56 +24,6 @@
 #include "common.h"
 #include "regs-pmu.h"
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-   unsigned int v;
-
-   asm volatile(
-   "   mcr p15, 0, %1, c7, c5, 0\n"
-   "   mcr p15, 0, %1, c7, c10, 4\n"
-   /*
-* Turn off coherency
-*/
-   "   mrc p15, 0, %0, c1, c0, 1\n"
-   "   bic %0, %0, %3\n"
-   "   mcr p15, 0, %0, c1, c0, 1\n"
-   "   mrc p15, 0, %0, c1, c0, 0\n"
-   "   bic %0, %0, %2\n"
-   "   mcr p15, 0, %0, c1, c0, 0\n"
- : "=" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-   unsigned int v;
-
-   asm volatile(
-   "   mrc p15, 0, %0, c1, c0, 0\n"
-   "   bic %0, %0, %1\n"
-   "   mcr p15, 0, %0, c1, c0, 0\n"
- : "=" (v)
- : "Ir" (CR_C)
- : "cc");
-
-   flush_cache_louis();
-
-   asm volatile(
-   /*
-   * Turn off coherency
-   */
-   "   mrc p15, 0, %0, c1, c0, 1\n"
-   "   bic %0, %0, %1\n"
-   "   mcr p15, 0, %0, c1, c0, 1\n"
-   : "=" (v)
-   : "Ir" (0x40)
-   : "cc");
-
-   isb();
-   dsb();
-}
-
 static inline void cpu_leave_lowpower(void)
 {
unsigned int v;
@@ -141,10 +91,8 @@ void __ref exynos_cpu_die(unsigned int cpu)
 * appropriate sequence for entering low power.
 */
asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-   if ((primary_part & 0xfff0) == 0xc0f0)
-   cpu_enter_lowpower_a15();
-   else
-   cpu_enter_lowpower_a9();
+
+   v7_exit_coherency_flush(louis);
 
platform_do_lowpower(cpu, );
 
-- 
1.7.9.5

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[PATCH] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Remove the duplicated code for cache disabling and use v7_exit_coherency_flush
macro to do the same job.

Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org

---
cpu hotplug is tested with 3.15-rc1 on Origen(which has cortex A9) and
Arndale octa(which has cortex A7 and A15) boards.

 arch/arm/mach-exynos/hotplug.c |   56 ++--
 1 file changed, 2 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9eb8d1b 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -24,56 +24,6 @@
 #include common.h
 #include regs-pmu.h
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-   unsigned int v;
-
-   asm volatile(
-  mcr p15, 0, %1, c7, c5, 0\n
-  mcr p15, 0, %1, c7, c10, 4\n
-   /*
-* Turn off coherency
-*/
-  mrc p15, 0, %0, c1, c0, 1\n
-  bic %0, %0, %3\n
-  mcr p15, 0, %0, c1, c0, 1\n
-  mrc p15, 0, %0, c1, c0, 0\n
-  bic %0, %0, %2\n
-  mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : r (0), Ir (CR_C), Ir (0x40)
- : cc);
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-   unsigned int v;
-
-   asm volatile(
-  mrc p15, 0, %0, c1, c0, 0\n
-  bic %0, %0, %1\n
-  mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : Ir (CR_C)
- : cc);
-
-   flush_cache_louis();
-
-   asm volatile(
-   /*
-   * Turn off coherency
-   */
-  mrc p15, 0, %0, c1, c0, 1\n
-  bic %0, %0, %1\n
-  mcr p15, 0, %0, c1, c0, 1\n
-   : =r (v)
-   : Ir (0x40)
-   : cc);
-
-   isb();
-   dsb();
-}
-
 static inline void cpu_leave_lowpower(void)
 {
unsigned int v;
@@ -141,10 +91,8 @@ void __ref exynos_cpu_die(unsigned int cpu)
 * appropriate sequence for entering low power.
 */
asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc);
-   if ((primary_part  0xfff0) == 0xc0f0)
-   cpu_enter_lowpower_a15();
-   else
-   cpu_enter_lowpower_a9();
+
+   v7_exit_coherency_flush(louis);
 
platform_do_lowpower(cpu, spurious);
 
-- 
1.7.9.5

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Re: [PATCH] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

Hi Daniel,

Thanks for reviewing the patch.

On Tue, Apr 22, 2014 at 8:06 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
 On 04/22/2014 04:18 PM, Leela Krishna Amudala wrote:

 Remove the duplicated code for cache disabling and use
 v7_exit_coherency_flush
 macro to do the same job.


 Hi Leela,

 thanks for this patch! It would be nice if you can describe why those macros
 can be replaced by the generic v7_exit_coherency_flush macro.


Okay, will give the description in commit message



 Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org

 ---
 cpu hotplug is tested with 3.15-rc1 on Origen(which has cortex A9) and
 Arndale octa(which has cortex A7 and A15) boards.

   arch/arm/mach-exynos/hotplug.c |   56
 ++--
   1 file changed, 2 insertions(+), 54 deletions(-)

 diff --git a/arch/arm/mach-exynos/hotplug.c
 b/arch/arm/mach-exynos/hotplug.c
 index 5eead53..9eb8d1b 100644
 --- a/arch/arm/mach-exynos/hotplug.c
 +++ b/arch/arm/mach-exynos/hotplug.c
 @@ -24,56 +24,6 @@
   #include common.h
   #include regs-pmu.h

 -static inline void cpu_enter_lowpower_a9(void)
 -{
 -   unsigned int v;
 -
 -   asm volatile(
 -  mcr p15, 0, %1, c7, c5, 0\n
 -  mcr p15, 0, %1, c7, c10, 4\n
 -   /*
 -* Turn off coherency
 -*/
 -  mrc p15, 0, %0, c1, c0, 1\n
 -  bic %0, %0, %3\n
 -  mcr p15, 0, %0, c1, c0, 1\n
 -  mrc p15, 0, %0, c1, c0, 0\n
 -  bic %0, %0, %2\n
 -  mcr p15, 0, %0, c1, c0, 0\n
 - : =r (v)
 - : r (0), Ir (CR_C), Ir (0x40)
 - : cc);
 -}
 -
 -static inline void cpu_enter_lowpower_a15(void)
 -{
 -   unsigned int v;
 -
 -   asm volatile(
 -  mrc p15, 0, %0, c1, c0, 0\n
 -  bic %0, %0, %1\n
 -  mcr p15, 0, %0, c1, c0, 0\n
 - : =r (v)
 - : Ir (CR_C)
 - : cc);
 -
 -   flush_cache_louis();
 -
 -   asm volatile(
 -   /*
 -   * Turn off coherency
 -   */
 -  mrc p15, 0, %0, c1, c0, 1\n
 -  bic %0, %0, %1\n
 -  mcr p15, 0, %0, c1, c0, 1\n
 -   : =r (v)
 -   : Ir (0x40)
 -   : cc);
 -
 -   isb();
 -   dsb();
 -}
 -
   static inline void cpu_leave_lowpower(void)
   {
 unsigned int v;
 @@ -141,10 +91,8 @@ void __ref exynos_cpu_die(unsigned int cpu)
  * appropriate sequence for entering low power.
  */
 asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc);


 Can't you remove this asm line above as well as the primary_part variable ?

Didn't notice it, will remove this.



 -   if ((primary_part  0xfff0) == 0xc0f0)
 -   cpu_enter_lowpower_a15();
 -   else
 -   cpu_enter_lowpower_a9();
 +
 +   v7_exit_coherency_flush(louis);

 platform_do_lowpower(cpu, spurious);




 --
  http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs

 Follow Linaro:  http://www.facebook.com/pages/Linaro Facebook |
 http://twitter.com/#!/linaroorg Twitter |
 http://www.linaro.org/linaro-blog/ Blog

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH V2] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Leela Krishna Amudala]

A common macro v7_exit_coherency_flush available which does the below tasks in
the seqeunce.
-clearing C bit
-clearing L1 cache
-exit SMP
-instruction and data synchronization

So removing the local functions which does the same thing and use the macro 
instead.

Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
Acked-by: Nicolas Pitre n...@linaro.org
---
Changes since V1:
- removed unwanted primary_part variable in exynos_cpu_die()
- given more description in commit message
  suggested by Daniel Lezcano daniel.lezc...@linaro.org

 arch/arm/mach-exynos/hotplug.c |   63 +---
 1 file changed, 1 insertion(+), 62 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9ca692d 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -24,56 +24,6 @@
 #include common.h
 #include regs-pmu.h
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-   unsigned int v;
-
-   asm volatile(
-  mcr p15, 0, %1, c7, c5, 0\n
-  mcr p15, 0, %1, c7, c10, 4\n
-   /*
-* Turn off coherency
-*/
-  mrc p15, 0, %0, c1, c0, 1\n
-  bic %0, %0, %3\n
-  mcr p15, 0, %0, c1, c0, 1\n
-  mrc p15, 0, %0, c1, c0, 0\n
-  bic %0, %0, %2\n
-  mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : r (0), Ir (CR_C), Ir (0x40)
- : cc);
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-   unsigned int v;
-
-   asm volatile(
-  mrc p15, 0, %0, c1, c0, 0\n
-  bic %0, %0, %1\n
-  mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : Ir (CR_C)
- : cc);
-
-   flush_cache_louis();
-
-   asm volatile(
-   /*
-   * Turn off coherency
-   */
-  mrc p15, 0, %0, c1, c0, 1\n
-  bic %0, %0, %1\n
-  mcr p15, 0, %0, c1, c0, 1\n
-   : =r (v)
-   : Ir (0x40)
-   : cc);
-
-   isb();
-   dsb();
-}
-
 static inline void cpu_leave_lowpower(void)
 {
unsigned int v;
@@ -132,19 +82,8 @@ static inline void platform_do_lowpower(unsigned int cpu, 
int *spurious)
 void __ref exynos_cpu_die(unsigned int cpu)
 {
int spurious = 0;
-   int primary_part = 0;
 
-   /*
-* we're ready for shutdown now, so do it.
-* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
-* number by reading the Main ID register and then perform the
-* appropriate sequence for entering low power.
-*/
-   asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc);
-   if ((primary_part  0xfff0) == 0xc0f0)
-   cpu_enter_lowpower_a15();
-   else
-   cpu_enter_lowpower_a9();
+   v7_exit_coherency_flush(louis);
 
platform_do_lowpower(cpu, spurious);
 
-- 
1.7.9.5

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Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Leela Krishna Amudala]

Hi All,

I didn't see this series in mainline, Any comments for this ?

Thanks,
Leela Krishna Amudala.


On Tue, Dec 10, 2013 at 12:10 PM, Naveen Krishna Chatradhi
 wrote:
> This patchset does a little clean up of the existing code (linux-soc-thermal)
> 1.  [v11] thermal: samsung: replace inten_ bit fields with intclr_
> 2.  [v11] thermal: samsung: change base_common to more meaningful base_second
>
> adds support for Exynos5420 in the driver and (linux-soc-thermal)
> 3.  [v11] thermal: samsung: Add TMU support for Exynos5420 SoCs
> also adds the device tree nodes for the same to exynos5420.dtsi 
> (linux-samsung.git)
> 4.  [v11] ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
> (linux-soc-thermal)
> Naveen Krishna Chatradhi (3):
>   thermal: samsung: replace inten_ bit fields with intclr_
>   thermal: samsung: change base_common to more meaningful base_second
>   thermal: samsung: Add TMU support for Exynos5420 SoCs
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   42 ++-
>  drivers/thermal/samsung/exynos_tmu.c   |   72 +---
>  drivers/thermal/samsung/exynos_tmu.h   |   21 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c  |  119 
> ++--
>  drivers/thermal/samsung/exynos_tmu_data.h  |   12 +-
>  5 files changed, 228 insertions(+), 38 deletions(-)
>
> (linux-samsung.git)
> Naveen Krishna Chatradhi (1):
>   ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
>  arch/arm/boot/dts/exynos5420.dtsi |   40 
> +
>  1 file changed, 40 insertions(+)
> --
> 1.7.10.4
>
> --
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Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Leela Krishna Amudala]

Hi All,

I didn't see this series in mainline, Any comments for this ?

Thanks,
Leela Krishna Amudala.


On Tue, Dec 10, 2013 at 12:10 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
 This patchset does a little clean up of the existing code (linux-soc-thermal)
 1.  [v11] thermal: samsung: replace inten_ bit fields with intclr_
 2.  [v11] thermal: samsung: change base_common to more meaningful base_second

 adds support for Exynos5420 in the driver and (linux-soc-thermal)
 3.  [v11] thermal: samsung: Add TMU support for Exynos5420 SoCs
 also adds the device tree nodes for the same to exynos5420.dtsi 
 (linux-samsung.git)
 4.  [v11] ARM: dts: Exynos5420: Add device nodes for TMU blocks

 (linux-soc-thermal)
 Naveen Krishna Chatradhi (3):
   thermal: samsung: replace inten_ bit fields with intclr_
   thermal: samsung: change base_common to more meaningful base_second
   thermal: samsung: Add TMU support for Exynos5420 SoCs

  .../devicetree/bindings/thermal/exynos-thermal.txt |   42 ++-
  drivers/thermal/samsung/exynos_tmu.c   |   72 +---
  drivers/thermal/samsung/exynos_tmu.h   |   21 ++--
  drivers/thermal/samsung/exynos_tmu_data.c  |  119 
 ++--
  drivers/thermal/samsung/exynos_tmu_data.h  |   12 +-
  5 files changed, 228 insertions(+), 38 deletions(-)

 (linux-samsung.git)
 Naveen Krishna Chatradhi (1):
   ARM: dts: Exynos5420: Add device nodes for TMU blocks

  arch/arm/boot/dts/exynos5420.dtsi |   40 
 +
  1 file changed, 40 insertions(+)
 --
 1.7.10.4

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Re: [PATCH] watchdog: s3c2410_wdt: Report when the watchdog reset the system

[Leela Krishna Amudala]

Hi Guenter Roeck,

On Tue, Dec 3, 2013 at 3:06 AM, Guenter Roeck  wrote:
>
> On Mon, Dec 02, 2013 at 12:47:53PM -0800, Olof Johansson wrote:
> > On Mon, Dec 2, 2013 at 12:21 PM, Guenter Roeck  wrote:
> > > On Mon, Dec 02, 2013 at 10:14:41AM -0800, Doug Anderson wrote:
> > >> A good watchdog driver is supposed to report when it was responsible
> > >> for resetting the system.  Implement this for the s3c2410, at least on
> > >> exynos5250 and exynos5420 where we already have a pointer to the PMU
> > >> registers to read the information.
> > >>
> > >> Signed-off-by: Doug Anderson 
> > >> ---
> > >> This patch is based atop Leela Krishna's recent series that ends with
> > >> (ARM: dts: update watchdog device nodes for Exynos5250 and Exynos5420)
> > >> AKA .
> > >>
> > >>  drivers/watchdog/s3c2410_wdt.c | 42 
> > >> +++---
> > >>  1 file changed, 39 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a/drivers/watchdog/s3c2410_wdt.c 
> > >> b/drivers/watchdog/s3c2410_wdt.c
> > >> index 47f4dcf..2c87d37 100644
> > >> --- a/drivers/watchdog/s3c2410_wdt.c
> > >> +++ b/drivers/watchdog/s3c2410_wdt.c
> > >> @@ -62,9 +62,13 @@
> > >>  #define CONFIG_S3C2410_WATCHDOG_ATBOOT   (0)
> > >>  #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
> > >>
> > >> +#define RST_STAT_REG_OFFSET  0x0404
> > >>  #define WDT_DISABLE_REG_OFFSET   0x0408
> > >>  #define WDT_MASK_RESET_REG_OFFSET0x040c
> > >>  #define QUIRK_NEEDS_PMU_CONFIG   (1 << 0)
> > >> +#define QUIRK_HAS_RST_STAT   (1 << 1)
> > >> +#define QUIRKS_NEED_PMUREG   (QUIRK_NEEDS_PMU_CONFIG | \
> > >> +  QUIRK_HAS_RST_STAT)
> > >>
> > > I am not really happy about the NEED (both of them, really) here.
> > > How about HAS instead ?
> >
> > Ah, I just commented on these things on our internal review site too
> > on this patch. I don't even think a quirk is needed -- just use the
> > presence of a non-0 rst_stat_reg to tell if you need to use regmap.
> >
> Agreed; same is true for the QUIRK_NEEDS_PMU_CONFIG related registers
> as well.
>

As Tomasz Figa suggested I introduced quirks,

Tomasz,
Any comments from you here...??


Best wishes,
Leela Krishna


> Guenter
> --
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Re: [PATCH] watchdog: s3c2410_wdt: Report when the watchdog reset the system

[Leela Krishna Amudala]

Hi Guenter Roeck,

On Tue, Dec 3, 2013 at 3:06 AM, Guenter Roeck li...@roeck-us.net wrote:

 On Mon, Dec 02, 2013 at 12:47:53PM -0800, Olof Johansson wrote:
  On Mon, Dec 2, 2013 at 12:21 PM, Guenter Roeck li...@roeck-us.net wrote:
   On Mon, Dec 02, 2013 at 10:14:41AM -0800, Doug Anderson wrote:
   A good watchdog driver is supposed to report when it was responsible
   for resetting the system.  Implement this for the s3c2410, at least on
   exynos5250 and exynos5420 where we already have a pointer to the PMU
   registers to read the information.
  
   Signed-off-by: Doug Anderson diand...@chromium.org
   ---
   This patch is based atop Leela Krishna's recent series that ends with
   (ARM: dts: update watchdog device nodes for Exynos5250 and Exynos5420)
   AKA https://patchwork.kernel.org/patch/3251861/.
  
drivers/watchdog/s3c2410_wdt.c | 42 
   +++---
1 file changed, 39 insertions(+), 3 deletions(-)
  
   diff --git a/drivers/watchdog/s3c2410_wdt.c 
   b/drivers/watchdog/s3c2410_wdt.c
   index 47f4dcf..2c87d37 100644
   --- a/drivers/watchdog/s3c2410_wdt.c
   +++ b/drivers/watchdog/s3c2410_wdt.c
   @@ -62,9 +62,13 @@
#define CONFIG_S3C2410_WATCHDOG_ATBOOT   (0)
#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  
   +#define RST_STAT_REG_OFFSET  0x0404
#define WDT_DISABLE_REG_OFFSET   0x0408
#define WDT_MASK_RESET_REG_OFFSET0x040c
#define QUIRK_NEEDS_PMU_CONFIG   (1  0)
   +#define QUIRK_HAS_RST_STAT   (1  1)
   +#define QUIRKS_NEED_PMUREG   (QUIRK_NEEDS_PMU_CONFIG | \
   +  QUIRK_HAS_RST_STAT)
  
   I am not really happy about the NEED (both of them, really) here.
   How about HAS instead ?
 
  Ah, I just commented on these things on our internal review site too
  on this patch. I don't even think a quirk is needed -- just use the
  presence of a non-0 rst_stat_reg to tell if you need to use regmap.
 
 Agreed; same is true for the QUIRK_NEEDS_PMU_CONFIG related registers
 as well.


As Tomasz Figa suggested I introduced quirks,

Tomasz,
Any comments from you here...??


Best wishes,
Leela Krishna


 Guenter
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Re: [PATCH 2/3] tegra: pwm-backlight: add tegra pwm-bl driver

[Leela Krishna Amudala]

t it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct ventana_bl_data {
> +   struct regulator *vdd_power;
> +   struct regulator *vdd_panel;
> +   int bl_gpio;
> +   int panel_gpio;
> +   bool is_on;
> +};
> +
> +static int init_ventana(struct device *dev)
> +{
> +   struct ventana_bl_data *data;
> +   int ret;
> +
> +   data = devm_kzalloc(dev, sizeof(struct ventana_bl_data),
> GFP_KERNEL);
> +   if (!data)
> +   return -ENOMEM;
> +
> +   data->vdd_power = devm_regulator_get(dev, "power");
> +   if (IS_ERR(data->vdd_power)) {
> +   dev_err(dev, "cannot get power regulator!\n");
> +   return PTR_ERR(data->vdd_power);
> +   }
> +
> +   data->vdd_panel = devm_regulator_get(dev, "panel");
> +   if (IS_ERR(data->vdd_panel)) {
> +   dev_err(dev, "cannot get panel regulator!\n");
> +   return PTR_ERR(data->vdd_panel);
> +   }
> +
> +   ret = of_get_named_gpio(dev->of_node, "bl-gpio", 0);
> +   if (ret < 0) {
> +   dev_err(dev, "cannot find backlight GPIO!\n");
> +   return ret;
> +   }
> +   data->bl_gpio = ret;
> +
> +   ret = of_get_named_gpio(dev->of_node, "bl-panel", 0);
> +   if (ret < 0) {
> +   dev_err(dev, "cannot find panel GPIO!\n");
> +   return ret;
> +   }
> +   data->panel_gpio = ret;
> +
> +   ret = devm_gpio_request_one(dev, data->bl_gpio,
> +   GPIOF_DIR_OUT | GPIOF_OUT_INIT_LOW,
> +   "backlight");
> +   if (ret < 0) {
> +   dev_err(dev, "cannot request backlight GPIO!\n");
> +   return ret;
> +   }
> +
> +   ret = devm_gpio_request_one(dev, data->panel_gpio,
> +   GPIOF_DIR_OUT | GPIOF_OUT_INIT_LOW,
> +   "panel");
> +   if (ret < 0) {
> +   dev_err(dev, "cannot request panel GPIO!\n");
> +   return ret;
> +   }
> +
> +   pwm_backlight_set_subdriver_data(dev, data);

Here you are passing ventana_bl_data pointer as input and in the
pwm_backlight_get_subdriver_data() function you are assigning the
received driver data to backlight_device pointer. As both are two
different structures with different structure fields in it. There can
be a chance for a crash.

Please correct me if I'm wrong.

Best Wishes,
Leela Krishna Amudala.

> +
> +   return 0;
> +}
> +
> +static void exit_ventana(struct device *dev)
> +{
> +   struct ventana_bl_data *data =
> pwm_backlight_get_subdriver_data(dev);
> +
> +   devm_gpio_free(dev, data->panel_gpio);
> +   devm_gpio_free(dev, data->bl_gpio);
> +   devm_regulator_put(data->vdd_panel);
> +   devm_regulator_put(data->vdd_power);
> +   devm_kfree(dev, data);
> +}
> +
> +static int notify_ventana(struct device *dev, int brightness)
> +{
> +   struct ventana_bl_data *data =
> pwm_backlight_get_subdriver_data(dev);
> +   if (brightness && !data->is_on) {
> +   regulator_enable(data->vdd_panel);
> +   gpio_set_value(data->panel_gpio, 1);
> +   usleep_range(20, 20);
> +   regulator_enable(data->vdd_power);
> +   usleep_range(1, 1);
> +   } else if (!brightness && data->is_on) {
> +   gpio_set_value(data->bl_gpio, 0);
> +   }
> +
> +   return brightness;
> +}
> +
> +static void notify_after_ventana(struct device *dev, int brightness)
> +{
> +   struct ventana_bl_data *data =
> pwm_backlight_get_subdriver_data(dev);
> +   if (brightness && !data->is_on) {
> +   gpio_set_value(data->bl_gpio, 1);
> +   data->is_on = true;
> +   } else if (!brightness && data->is_on) {
> +   usleep_range(1, 1);
> +   regulator_disable(data->vdd_power);
> +   usleep_range(20, 20);
> +   gpio_set_value(data->panel_gpio, 0);
> +   regulator_disable(data->vdd_pane

Re: [PATCH 2/3] tegra: pwm-backlight: add tegra pwm-bl driver

[Leela Krishna Amudala]

(struct device *dev)
 +{
 +   struct ventana_bl_data *data;
 +   int ret;
 +
 +   data = devm_kzalloc(dev, sizeof(struct ventana_bl_data),
 GFP_KERNEL);
 +   if (!data)
 +   return -ENOMEM;
 +
 +   data-vdd_power = devm_regulator_get(dev, power);
 +   if (IS_ERR(data-vdd_power)) {
 +   dev_err(dev, cannot get power regulator!\n);
 +   return PTR_ERR(data-vdd_power);
 +   }
 +
 +   data-vdd_panel = devm_regulator_get(dev, panel);
 +   if (IS_ERR(data-vdd_panel)) {
 +   dev_err(dev, cannot get panel regulator!\n);
 +   return PTR_ERR(data-vdd_panel);
 +   }
 +
 +   ret = of_get_named_gpio(dev-of_node, bl-gpio, 0);
 +   if (ret  0) {
 +   dev_err(dev, cannot find backlight GPIO!\n);
 +   return ret;
 +   }
 +   data-bl_gpio = ret;
 +
 +   ret = of_get_named_gpio(dev-of_node, bl-panel, 0);
 +   if (ret  0) {
 +   dev_err(dev, cannot find panel GPIO!\n);
 +   return ret;
 +   }
 +   data-panel_gpio = ret;
 +
 +   ret = devm_gpio_request_one(dev, data-bl_gpio,
 +   GPIOF_DIR_OUT | GPIOF_OUT_INIT_LOW,
 +   backlight);
 +   if (ret  0) {
 +   dev_err(dev, cannot request backlight GPIO!\n);
 +   return ret;
 +   }
 +
 +   ret = devm_gpio_request_one(dev, data-panel_gpio,
 +   GPIOF_DIR_OUT | GPIOF_OUT_INIT_LOW,
 +   panel);
 +   if (ret  0) {
 +   dev_err(dev, cannot request panel GPIO!\n);
 +   return ret;
 +   }
 +
 +   pwm_backlight_set_subdriver_data(dev, data);

Here you are passing ventana_bl_data pointer as input and in the
pwm_backlight_get_subdriver_data() function you are assigning the
received driver data to backlight_device pointer. As both are two
different structures with different structure fields in it. There can
be a chance for a crash.

Please correct me if I'm wrong.

Best Wishes,
Leela Krishna Amudala.

 +
 +   return 0;
 +}
 +
 +static void exit_ventana(struct device *dev)
 +{
 +   struct ventana_bl_data *data =
 pwm_backlight_get_subdriver_data(dev);
 +
 +   devm_gpio_free(dev, data-panel_gpio);
 +   devm_gpio_free(dev, data-bl_gpio);
 +   devm_regulator_put(data-vdd_panel);
 +   devm_regulator_put(data-vdd_power);
 +   devm_kfree(dev, data);
 +}
 +
 +static int notify_ventana(struct device *dev, int brightness)
 +{
 +   struct ventana_bl_data *data =
 pwm_backlight_get_subdriver_data(dev);
 +   if (brightness  !data-is_on) {
 +   regulator_enable(data-vdd_panel);
 +   gpio_set_value(data-panel_gpio, 1);
 +   usleep_range(20, 20);
 +   regulator_enable(data-vdd_power);
 +   usleep_range(1, 1);
 +   } else if (!brightness  data-is_on) {
 +   gpio_set_value(data-bl_gpio, 0);
 +   }
 +
 +   return brightness;
 +}
 +
 +static void notify_after_ventana(struct device *dev, int brightness)
 +{
 +   struct ventana_bl_data *data =
 pwm_backlight_get_subdriver_data(dev);
 +   if (brightness  !data-is_on) {
 +   gpio_set_value(data-bl_gpio, 1);
 +   data-is_on = true;
 +   } else if (!brightness  data-is_on) {
 +   usleep_range(1, 1);
 +   regulator_disable(data-vdd_power);
 +   usleep_range(20, 20);
 +   gpio_set_value(data-panel_gpio, 0);
 +   regulator_disable(data-vdd_panel);
 +   data-is_on = false;
 +   }
 +}
 +
 +static struct pwm_backlight_subdriver pwm_backlight_ventana_subdriver = {
 +   .name = pwm-backlight-ventana,
 +   .init = init_ventana,
 +   .exit = exit_ventana,
 +   .notify = notify_ventana,
 +   .notify_after = notify_after_ventana,
 +};
 +
 +static int __init pwm_backlight_tegra_init(void)
 +{
 +   pwm_backlight_add_subdriver(pwm_backlight_ventana_subdriver);
 +   return 0;
 +}
 +
 +static void __exit pwm_backlight_tegra_exit(void)
 +{
 +   pwm_backlight_remove_subdriver(pwm_backlight_ventana_subdriver);
 +}
 +
 +module_init(pwm_backlight_tegra_init);
 +module_exit(pwm_backlight_tegra_exit);
 +
 +MODULE_DESCRIPTION(Backlight Driver for Tegra boards);
 +MODULE_LICENSE(GPL);
 +MODULE_ALIAS(platform:pwm-tegra-backlight);
 +
 +
 --
 1.8.1.1

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