Re: [PATCHv2] arm64: dts: agilex: add QSPI support for Intel Agilex
On Wed, 2019-10-16 at 02:40 -0700, Ooi, Joyce wrote:
> This patch adds QSPI flash interface in device tree for Intel Agilex
>
> Signed-off-by: Ooi, Joyce
> ---
> v2: update the qspi_rootfs partition size
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 35
> ++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> index 7814a9e..8de8118 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> @@ -73,3 +73,38 @@
> &watchdog0 {
> status = "okay";
> };
> +
> +&qspi {
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "mt25qu02g";
> + reg = <0>;
> + spi-max-frequency = <5000>;
QSPI can support up to 100MHz.
> +
> + m25p,fast-read;
> + cdns,page-size = <256>;
> + cdns,block-size = <16>;
> + cdns,read-delay = <1>;
> + cdns,tshsl-ns = <50>;
> + cdns,tsd2d-ns = <50>;
> + cdns,tchsh-ns = <4>;
> + cdns,tslch-ns = <4>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qspi_boot: partition@0 {
> + label = "Boot and fpga data";
> + reg = <0x0 0x034B>;
> + };
> +
> + qspi_rootfs: partition@34B {
> + label = "Root Filesystem - JFFS2";
> + reg = <0x034B 0x0CB5>;
> + };
> + };
> + };
> +};
Re: [PATCH] nios2: force the string buffer NULL-terminated
On Mon, 2019-08-05 at 18:17 +0800, Wang Xiayang wrote: > strncpy() does not ensure NULL-termination when the input string > size equals to the destination buffer size COMMAND_LINE_SIZE. > Besides, grep under arch/ with 'boot_command_line' shows > no other arch-specific code uses strncpy() when copying > boot_command_line. > > Use strlcpy() instead. > > This issue is identified by a Coccinelle script. > > Signed-off-by: Wang Xiayang Merged to v5.4-rc1. Thanks. Acked-by: Ley Foon Tan > --- > arch/nios2/kernel/setup.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c > index 6bbd4ae2beb0..4cf35b09c0ec 100644 > --- a/arch/nios2/kernel/setup.c > +++ b/arch/nios2/kernel/setup.c > @@ -123,7 +123,7 @@ asmlinkage void __init nios2_boot_init(unsigned > r4, unsigned r5, unsigned r6, > dtb_passed = r6; > > if (r7) > - strncpy(cmdline_passed, (char *)r7, > COMMAND_LINE_SIZE); > + strlcpy(cmdline_passed, (char *)r7, > COMMAND_LINE_SIZE); > } > #endif > > @@ -131,10 +131,10 @@ asmlinkage void __init nios2_boot_init(unsigned > r4, unsigned r5, unsigned r6, > > #ifndef CONFIG_CMDLINE_FORCE > if (cmdline_passed[0]) > - strncpy(boot_command_line, cmdline_passed, > COMMAND_LINE_SIZE); > + strlcpy(boot_command_line, cmdline_passed, > COMMAND_LINE_SIZE); > #ifdef CONFIG_NIOS2_CMDLINE_IGNORE_DTB > else > - strncpy(boot_command_line, CONFIG_CMDLINE, > COMMAND_LINE_SIZE); > + strlcpy(boot_command_line, CONFIG_CMDLINE, > COMMAND_LINE_SIZE); > #endif > #endif > > -- > 2.11.0 > > > > > Confidentiality Notice. > This message may contain information that is confidential or > otherwise protected from disclosure. If you are not the intended > recipient, you are hereby notified that any use, disclosure, > dissemination, distribution, or copying of this message, or any > attachments, is strictly prohibited. If you have received this > message in error, please advise the sender by reply e-mail, and > delete the message and any attachments. Thank you.
[GIT PULL] arch/nios2 update for v5.4
Hi Linus Please pull the arch/nios2 update below. Thanks. Regards Ley Foon The following changes since commit 4d856f72c10ecb060868ed10ff1b1453943fc6c8: Linux 5.3 (2019-09-15 14:19:32 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v5.4-rc1 for you to fetch changes up to 91d99a724e9c60e14332c26ab2284bf696b94c8e: nios2: force the string buffer NULL-terminated (2019-09-20 14:55:57 +0800) nios2 update for v5.4-rc1 nios2: force the string buffer NULL-terminated Wang Xiayang (1): nios2: force the string buffer NULL-terminated arch/nios2/kernel/setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Re: [PATCH] nios2: remove pointless second entry for CONFIG_TRACE_IRQFLAGS_SUPPORT
On Sun, 2019-06-23 at 23:13 +0900, Masahiro Yamada wrote: > On Sun, May 12, 2019 at 10:16 PM Masahiro Yamada > wrote: > > > > > > Strangely enough, NIOS2 defines TRACE_IRQFLAGS_SUPPORT twice > > with different values, which is pointless and confusing. > > > > [1] arch/nios2/Kconfig > > > > config TRACE_IRQFLAGS_SUPPORT > > def_bool n > > > > [2] arch/nios2/Kconfig.debug > > > > config TRACE_IRQFLAGS_SUPPORT > > def_bool y > > > > [1] is included before [2]. In the Kconfig syntax, the first one > > is effective. So, TRACE_IRQFLAGS_SUPPORT is always 'n'. > > > > The second define in arch/nios2/Kconfig.debug is dead code. > > > > Signed-off-by: Masahiro Yamada > > --- > Ping. > > Acked-by: Ley Foon Tan Will integrate to next kernel version. Thanks. > > > > arch/nios2/Kconfig.debug | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/arch/nios2/Kconfig.debug b/arch/nios2/Kconfig.debug > > index f1da8a7..a8bc06e 100644 > > --- a/arch/nios2/Kconfig.debug > > +++ b/arch/nios2/Kconfig.debug > > @@ -1,8 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > > > -config TRACE_IRQFLAGS_SUPPORT > > - def_bool y > > - > > config EARLY_PRINTK > > bool "Activate early kernel debugging" > > default y > > -- > > 2.7.4 > > > > -- > Best Regards > Masahiro Yamada > > Regards Ley Foon
[PATCH v2] PCI: altera: Fix configuration type based on secondary number
This fix issue when access config from PCIe switch.
Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
as previous version (V1) does.
The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan
---
v2:
- Add get_tlp_header() function.
---
drivers/pci/controller/pcie-altera.c | 41 ++--
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 27222071ace7..d2497ca43828 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -44,6 +44,8 @@
#define S10_RP_RXCPL_STATUS0x200C
#define S10_RP_CFG_ADDR(pcie, reg) \
(((pcie)->hip_base) + (reg) + (1 << 20))
+#define S10_RP_SECONDARY(pcie) \
+ readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
@@ -55,14 +57,9 @@
#define TLP_WRITE_TAG 0x10
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
-#define TLP_CFGRD_DW0(pcie, bus) \
- bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
- : pcie->pcie_data->cfgrd1) << 24) | \
- TLP_PAYLOAD_SIZE)
-#define TLP_CFGWR_DW0(pcie, bus) \
- bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
- : pcie->pcie_data->cfgwr1) << 24) | \
- TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW0(pcie, cfg) \
+ (((cfg) << 24) |\
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
@@ -322,14 +319,31 @@ static void s10_tlp_write_packet(struct altera_pcie
*pcie, u32 *headers,
s10_tlp_write_tx(pcie, data, RP_TX_EOP);
}
+static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
+ int where, u8 byte_en, bool read, u32 *headers)
+{
+ u8 cfg;
+ u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
+ u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
+ u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
+
+ if (pcie->pcie_data->version == ALTERA_PCIE_V1)
+ cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
+ else
+ cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
+
+ headers[0] = TLP_CFG_DW0(pcie, cfg);
+ headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
+ headers[2] = TLP_CFG_DW2(bus, devfn, where);
+}
+
static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
int where, u8 byte_en, u32 *value)
{
u32 headers[TLP_HDR_SIZE];
- headers[0] = TLP_CFGRD_DW0(pcie, bus);
- headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
- headers[2] = TLP_CFG_DW2(bus, devfn, where);
+ get_tlp_header(pcie, bus, devfn, where, byte_en, true,
+ headers);
pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
@@ -342,9 +356,8 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8
bus, u32 devfn,
u32 headers[TLP_HDR_SIZE];
int ret;
- headers[0] = TLP_CFGWR_DW0(pcie, bus);
- headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
- headers[2] = TLP_CFG_DW2(bus, devfn, where);
+ get_tlp_header(pcie, bus, devfn, where, byte_en, false,
+ headers);
/* check alignment to Qword */
if ((where & 0x7) == 0)
--
2.19.0
Re: [PATCH 1/2] PCI: altera: Fix configuration type based on secondary number
On Thu, May 30, 2019 at 11:25 PM Lorenzo Pieralisi
wrote:
>
> On Fri, May 24, 2019 at 02:07:25PM +0800, Ley Foon Tan wrote:
> > This fix issue when access config from PCIe switch.
> >
> > Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
> > as previous version (V1) does.
> >
> > The PCIe controller need to send Type 0 config TLP if the targeting bus
> > matches with the secondary bus number, which is when the TLP is targeting
> > the immediate device on the link.
> >
> > The PCIe controller send Type 1 config TLP if the targeting bus is
> > larger than the secondary bus, which is when the TLP is targeting the
> > device not immediate on the link.
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > drivers/pci/controller/pcie-altera.c | 22 --
> > 1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-altera.c
> > b/drivers/pci/controller/pcie-altera.c
> > index 27222071ace7..047bcc214f9b 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -44,6 +44,8 @@
> > #define S10_RP_RXCPL_STATUS 0x200C
> > #define S10_RP_CFG_ADDR(pcie, reg) \
> > (((pcie)->hip_base) + (reg) + (1 << 20))
> > +#define S10_RP_SECONDARY(pcie) \
> > + readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
> >
> > /* TLP configuration type 0 and 1 */
> > #define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0
> > */
> > @@ -63,6 +65,14 @@
> > bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
> > : pcie->pcie_data->cfgwr1) << 24) | \
> > TLP_PAYLOAD_SIZE)
> > +#define S10_TLP_CFGRD_DW0(pcie, bus) \
> > + (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgrd0 \
> > + : pcie->pcie_data->cfgrd1) << 24) | \
> > + TLP_PAYLOAD_SIZE)
> > +#define S10_TLP_CFGWR_DW0(pcie, bus) \
> > + (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgwr0 \
> > + : pcie->pcie_data->cfgwr1) << 24) | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFG_DW1(pcie, tag, be) \
> > (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) |
> > (be))
> > #define TLP_CFG_DW2(bus, devfn, offset) \
> > @@ -327,7 +337,11 @@ static int tlp_cfg_dword_read(struct altera_pcie
> > *pcie, u8 bus, u32 devfn,
> > {
> > u32 headers[TLP_HDR_SIZE];
> >
> > - headers[0] = TLP_CFGRD_DW0(pcie, bus);
> > + if (pcie->pcie_data->version == ALTERA_PCIE_V1)
> > + headers[0] = TLP_CFGRD_DW0(pcie, bus);
> > + else
> > + headers[0] = S10_TLP_CFGRD_DW0(pcie, bus);
> > +
> > headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
> > headers[2] = TLP_CFG_DW2(bus, devfn, where);
> >
> > @@ -342,7 +356,11 @@ static int tlp_cfg_dword_write(struct altera_pcie
> > *pcie, u8 bus, u32 devfn,
> > u32 headers[TLP_HDR_SIZE];
> > int ret;
> >
> > - headers[0] = TLP_CFGWR_DW0(pcie, bus);
> > + if (pcie->pcie_data->version == ALTERA_PCIE_V1)
> > + headers[0] = TLP_CFGWR_DW0(pcie, bus);
> > + else
> > + headers[0] = S10_TLP_CFGWR_DW0(pcie, bus);
> > +
>
> Why don't you rewrite all these macros as an eg:
>
> static inline u32 get_tlp_header()
> {}
>
> where you can also handle the version and everything needed to
> detect what header should be set-up ?
>
Okay, will change this.
Thanks.
Regards
Ley Foon
Re: [PATCH] PCI: altera: Allow building as module
On Tue, Jun 4, 2019 at 9:18 PM Bjorn Helgaas wrote: > > On Wed, Apr 24, 2019 at 12:57:14PM +0800, Ley Foon Tan wrote: > > Altera PCIe Rootport IP is a soft IP and is only available after > > FPGA image is programmed. > > > > Make driver modulable to support use case FPGA image is programmed > > after kernel is booted. User proram FPGA image in kernel then only load > > PCIe driver module. > > I'm not objecting to these patches, but help me understand how this > works. The "usual" scenario is that if a driver is loaded before a > matching device is available, i.e., either the driver is built > statically or it is loaded before a device is hot-added, the event of > the device being available causes the driver's probe method to be > called. > > This seems to be a more manual process of programming the FPGA which > results in a new "altera-pcie" platform device. And then apparently > you need to load the appropriate module by hand? Is there no > "hot-add" type of event for this platform device that automatically > looks for the driver? Yes, we need load module manually now. Regards Ley Foon
[PATCH 2/2] PCI: altera: Remove cfgrdX and cfgwrX
No longer need cfgrdX and cfgwrX since we have separate defines for
TLP_CFG*_DW0 and S10_TLP_CFG*_DW0, so remove them.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 33 +++-
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 047bcc214f9b..d96980a4e327 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -58,20 +58,20 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
- bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
- : pcie->pcie_data->cfgrd1) << 24) | \
+ bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
+ : TLP_FMTTYPE_CFGRD1) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
- bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
- : pcie->pcie_data->cfgwr1) << 24) | \
+ bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
+ : TLP_FMTTYPE_CFGWR1) << 24) | \
TLP_PAYLOAD_SIZE)
#define S10_TLP_CFGRD_DW0(pcie, bus) \
- (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgrd0 \
- : pcie->pcie_data->cfgrd1) << 24) | \
+ (bus) > S10_RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1\
+ : TLP_FMTTYPE_CFGRD0) << 24) | \
TLP_PAYLOAD_SIZE)
#define S10_TLP_CFGWR_DW0(pcie, bus) \
- (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgwr0 \
- : pcie->pcie_data->cfgwr1) << 24) | \
+ (bus) > S10_RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1\
+ : TLP_FMTTYPE_CFGWR0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
@@ -87,11 +87,6 @@
#define DWORD_MASK 3
-#define S10_TLP_FMTTYPE_CFGRD0 0x05
-#define S10_TLP_FMTTYPE_CFGRD1 0x04
-#define S10_TLP_FMTTYPE_CFGWR0 0x45
-#define S10_TLP_FMTTYPE_CFGWR1 0x44
-
enum altera_pcie_version {
ALTERA_PCIE_V1 = 0,
ALTERA_PCIE_V2,
@@ -124,10 +119,6 @@ struct altera_pcie_data {
const struct altera_pcie_ops *ops;
enum altera_pcie_version version;
u32 cap_offset; /* PCIe capability structure register offset */
- u32 cfgrd0;
- u32 cfgrd1;
- u32 cfgwr0;
- u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -784,20 +775,12 @@ static const struct altera_pcie_data altera_pcie_1_0_data
= {
.ops = &altera_pcie_ops_1_0,
.cap_offset = 0x80,
.version = ALTERA_PCIE_V1,
- .cfgrd0 = TLP_FMTTYPE_CFGRD0,
- .cfgrd1 = TLP_FMTTYPE_CFGRD1,
- .cfgwr0 = TLP_FMTTYPE_CFGWR0,
- .cfgwr1 = TLP_FMTTYPE_CFGWR1,
};
static const struct altera_pcie_data altera_pcie_2_0_data = {
.ops = &altera_pcie_ops_2_0,
.version = ALTERA_PCIE_V2,
.cap_offset = 0x70,
- .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
- .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
- .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
- .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
};
static const struct of_device_id altera_pcie_of_match[] = {
--
2.19.0
[PATCH 0/2] Fix Altera PCIe configuration type handling
This fix issue when access config from PCIe switch. Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion as previous version (V1) does. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Ley Foon Tan (2): PCI: altera: Fix configuration type based on secondary number PCI: altera: Remove cfgrdX and cfgwrX drivers/pci/controller/pcie-altera.c | 47 ++-- 1 file changed, 24 insertions(+), 23 deletions(-) -- 2.19.0
[PATCH 1/2] PCI: altera: Fix configuration type based on secondary number
This fix issue when access config from PCIe switch.
Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
as previous version (V1) does.
The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 27222071ace7..047bcc214f9b 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -44,6 +44,8 @@
#define S10_RP_RXCPL_STATUS0x200C
#define S10_RP_CFG_ADDR(pcie, reg) \
(((pcie)->hip_base) + (reg) + (1 << 20))
+#define S10_RP_SECONDARY(pcie) \
+ readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
@@ -63,6 +65,14 @@
bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
: pcie->pcie_data->cfgwr1) << 24) | \
TLP_PAYLOAD_SIZE)
+#define S10_TLP_CFGRD_DW0(pcie, bus) \
+ (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
+#define S10_TLP_CFGWR_DW0(pcie, bus) \
+ (bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
@@ -327,7 +337,11 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8
bus, u32 devfn,
{
u32 headers[TLP_HDR_SIZE];
- headers[0] = TLP_CFGRD_DW0(pcie, bus);
+ if (pcie->pcie_data->version == ALTERA_PCIE_V1)
+ headers[0] = TLP_CFGRD_DW0(pcie, bus);
+ else
+ headers[0] = S10_TLP_CFGRD_DW0(pcie, bus);
+
headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
@@ -342,7 +356,11 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie,
u8 bus, u32 devfn,
u32 headers[TLP_HDR_SIZE];
int ret;
- headers[0] = TLP_CFGWR_DW0(pcie, bus);
+ if (pcie->pcie_data->version == ALTERA_PCIE_V1)
+ headers[0] = TLP_CFGWR_DW0(pcie, bus);
+ else
+ headers[0] = S10_TLP_CFGWR_DW0(pcie, bus);
+
headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
--
2.19.0
Re: [PATCH] PCI: altera: Fix no return warning for altera_pcie_irq_teardown()
On Fri, May 24, 2019 at 10:15 AM Ley Foon Tan wrote:
>
> Fix compilation warning caused by patch "PCI: altera: Allow building as
> module".
>
> drivers/pci/controller/pcie-altera.c: In function ‘altera_pcie_irq_teardown’:
> drivers/pci/controller/pcie-altera.c:723:1: warning: no return statement in
> function returning non-void [-Wreturn-type]
> }
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/pci/controller/pcie-altera.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-altera.c
> b/drivers/pci/controller/pcie-altera.c
> index 6c86bc69ace8..27222071ace7 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -706,7 +706,7 @@ static int altera_pcie_init_irq_domain(struct altera_pcie
> *pcie)
> return 0;
> }
>
> -static int altera_pcie_irq_teardown(struct altera_pcie *pcie)
> +static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
> {
> irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
> irq_domain_remove(pcie->irq_domain);
> --
> 2.19.0
>
Hi
You can squash this patch to this https://lkml.org/lkml/2019/4/24/18
"PCI: altera: Allow building as module" if want.
Thanks.
Regards
Ley Foon
[PATCH] PCI: altera: Fix no return warning for altera_pcie_irq_teardown()
Fix compilation warning caused by patch "PCI: altera: Allow building as module".
drivers/pci/controller/pcie-altera.c: In function ‘altera_pcie_irq_teardown’:
drivers/pci/controller/pcie-altera.c:723:1: warning: no return statement in
function returning non-void [-Wreturn-type]
}
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 6c86bc69ace8..27222071ace7 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -706,7 +706,7 @@ static int altera_pcie_init_irq_domain(struct altera_pcie
*pcie)
return 0;
}
-static int altera_pcie_irq_teardown(struct altera_pcie *pcie)
+static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
{
irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
irq_domain_remove(pcie->irq_domain);
--
2.19.0
Re: [PATCH] PCI: altera-msi: Allow building as module
On Wed, May 15, 2019 at 9:59 PM Lorenzo Pieralisi
wrote:
>
> On Tue, May 14, 2019 at 01:35:20PM +0800, Ley Foon Tan wrote:
> > On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan
> > wrote:
> > >
> > > Altera MSI IP is a soft IP and is only available after
> > > FPGA image is programmed.
> > >
> > > Make driver modulable to support use case FPGA image is programmed
> > > after kernel is booted. User proram FPGA image in kernel then only load
> > > MSI driver module.
> > >
> > > Signed-off-by: Ley Foon Tan
> > > ---
> > > drivers/pci/controller/Kconfig | 2 +-
> > > drivers/pci/controller/pcie-altera-msi.c | 10 ++
> > > 2 files changed, 11 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/Kconfig
> > > b/drivers/pci/controller/Kconfig
> > > index 4b550f9cdd56..920546cb84e2 100644
> > > --- a/drivers/pci/controller/Kconfig
> > > +++ b/drivers/pci/controller/Kconfig
> > > @@ -181,7 +181,7 @@ config PCIE_ALTERA
> > > FPGA.
> > >
> > > config PCIE_ALTERA_MSI
> > > - bool "Altera PCIe MSI feature"
> > > + tristate "Altera PCIe MSI feature"
> > > depends on PCIE_ALTERA
> > > depends on PCI_MSI_IRQ_DOMAIN
> > > help
> > > diff --git a/drivers/pci/controller/pcie-altera-msi.c
> > > b/drivers/pci/controller/pcie-altera-msi.c
> > > index 025ef7d9a046..16d938920ca5 100644
> > > --- a/drivers/pci/controller/pcie-altera-msi.c
> > > +++ b/drivers/pci/controller/pcie-altera-msi.c
> > > @@ -10,6 +10,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -288,4 +289,13 @@ static int __init altera_msi_init(void)
> > > {
> > > return platform_driver_register(&altera_msi_driver);
> > > }
> > > +
> > > +static void __exit altera_msi_exit(void)
> > > +{
> > > + platform_driver_unregister(&altera_msi_driver);
> > > +}
> > > +
> > > subsys_initcall(altera_msi_init);
> > > +MODULE_DEVICE_TABLE(of, altera_msi_of_match);
> > > +module_exit(altera_msi_exit);
> > > +MODULE_LICENSE("GPL v2");
> > > --
> > > 2.19.0
> > >
> > Hi
> >
> > Any comment for this patch?
>
> I will get to these patches for the next merge window, thanks.
Thanks.
Regards
Ley Foon
Re: [PATCH] PCI: altera-msi: Allow building as module
On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan wrote:
>
> Altera MSI IP is a soft IP and is only available after
> FPGA image is programmed.
>
> Make driver modulable to support use case FPGA image is programmed
> after kernel is booted. User proram FPGA image in kernel then only load
> MSI driver module.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-altera-msi.c | 10 ++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 4b550f9cdd56..920546cb84e2 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -181,7 +181,7 @@ config PCIE_ALTERA
> FPGA.
>
> config PCIE_ALTERA_MSI
> - bool "Altera PCIe MSI feature"
> + tristate "Altera PCIe MSI feature"
> depends on PCIE_ALTERA
> depends on PCI_MSI_IRQ_DOMAIN
> help
> diff --git a/drivers/pci/controller/pcie-altera-msi.c
> b/drivers/pci/controller/pcie-altera-msi.c
> index 025ef7d9a046..16d938920ca5 100644
> --- a/drivers/pci/controller/pcie-altera-msi.c
> +++ b/drivers/pci/controller/pcie-altera-msi.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -288,4 +289,13 @@ static int __init altera_msi_init(void)
> {
> return platform_driver_register(&altera_msi_driver);
> }
> +
> +static void __exit altera_msi_exit(void)
> +{
> + platform_driver_unregister(&altera_msi_driver);
> +}
> +
> subsys_initcall(altera_msi_init);
> +MODULE_DEVICE_TABLE(of, altera_msi_of_match);
> +module_exit(altera_msi_exit);
> +MODULE_LICENSE("GPL v2");
> --
> 2.19.0
>
Hi
Any comment for this patch?
Regards
Ley Foon
Re: [PATCH] PCI: altera: Allow building as module
On Wed, Apr 24, 2019 at 12:57 PM Ley Foon Tan wrote:
>
> Altera PCIe Rootport IP is a soft IP and is only available after
> FPGA image is programmed.
>
> Make driver modulable to support use case FPGA image is programmed
> after kernel is booted. User proram FPGA image in kernel then only load
> PCIe driver module.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-altera.c | 28 ++--
> 2 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 6012f3059acd..4b550f9cdd56 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -174,7 +174,7 @@ config PCIE_IPROC_MSI
> PCIe controller
>
> config PCIE_ALTERA
> - bool "Altera PCIe controller"
> + tristate "Altera PCIe controller"
> depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
> help
> Say Y here if you want to enable PCIe controller support on Altera
> diff --git a/drivers/pci/controller/pcie-altera.c
> b/drivers/pci/controller/pcie-altera.c
> index 27edcebd1726..6c86bc69ace8 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -705,6 +706,13 @@ static int altera_pcie_init_irq_domain(struct
> altera_pcie *pcie)
> return 0;
> }
>
> +static int altera_pcie_irq_teardown(struct altera_pcie *pcie)
> +{
> + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
> + irq_domain_remove(pcie->irq_domain);
> + irq_dispose_mapping(pcie->irq);
> +}
> +
> static int altera_pcie_parse_dt(struct altera_pcie *pcie)
> {
> struct device *dev = &pcie->pdev->dev;
> @@ -798,6 +806,7 @@ static int altera_pcie_probe(struct platform_device *pdev)
>
> pcie = pci_host_bridge_priv(bridge);
> pcie->pdev = pdev;
> + platform_set_drvdata(pdev, pcie);
>
> match = of_match_device(altera_pcie_of_match, &pdev->dev);
> if (!match)
> @@ -855,13 +864,28 @@ static int altera_pcie_probe(struct platform_device
> *pdev)
> return ret;
> }
>
> +static int altera_pcie_remove(struct platform_device *pdev)
> +{
> + struct altera_pcie *pcie = platform_get_drvdata(pdev);
> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> +
> + pci_stop_root_bus(bridge->bus);
> + pci_remove_root_bus(bridge->bus);
> + pci_free_resource_list(&pcie->resources);
> + altera_pcie_irq_teardown(pcie);
> +
> + return 0;
> +}
> +
> static struct platform_driver altera_pcie_driver = {
> .probe = altera_pcie_probe,
> + .remove = altera_pcie_remove,
> .driver = {
> .name = "altera-pcie",
> .of_match_table = altera_pcie_of_match,
> - .suppress_bind_attrs = true,
> },
> };
>
> -builtin_platform_driver(altera_pcie_driver);
> +MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
> +module_platform_driver(altera_pcie_driver);
> +MODULE_LICENSE("GPL v2");
> --
> 2.19.0
>
Hi
Any comment for this patch?
Regards
Ley Foon
[PATCH] PCI: altera-msi: Allow building as module
Altera MSI IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
MSI driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-altera-msi.c | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 4b550f9cdd56..920546cb84e2 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -181,7 +181,7 @@ config PCIE_ALTERA
FPGA.
config PCIE_ALTERA_MSI
- bool "Altera PCIe MSI feature"
+ tristate "Altera PCIe MSI feature"
depends on PCIE_ALTERA
depends on PCI_MSI_IRQ_DOMAIN
help
diff --git a/drivers/pci/controller/pcie-altera-msi.c
b/drivers/pci/controller/pcie-altera-msi.c
index 025ef7d9a046..16d938920ca5 100644
--- a/drivers/pci/controller/pcie-altera-msi.c
+++ b/drivers/pci/controller/pcie-altera-msi.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -288,4 +289,13 @@ static int __init altera_msi_init(void)
{
return platform_driver_register(&altera_msi_driver);
}
+
+static void __exit altera_msi_exit(void)
+{
+ platform_driver_unregister(&altera_msi_driver);
+}
+
subsys_initcall(altera_msi_init);
+MODULE_DEVICE_TABLE(of, altera_msi_of_match);
+module_exit(altera_msi_exit);
+MODULE_LICENSE("GPL v2");
--
2.19.0
[PATCH] PCI: altera: Allow building as module
Altera PCIe Rootport IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
PCIe driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-altera.c | 28 ++--
2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6012f3059acd..4b550f9cdd56 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -174,7 +174,7 @@ config PCIE_IPROC_MSI
PCIe controller
config PCIE_ALTERA
- bool "Altera PCIe controller"
+ tristate "Altera PCIe controller"
depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
help
Say Y here if you want to enable PCIe controller support on Altera
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 27edcebd1726..6c86bc69ace8 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -705,6 +706,13 @@ static int altera_pcie_init_irq_domain(struct altera_pcie
*pcie)
return 0;
}
+static int altera_pcie_irq_teardown(struct altera_pcie *pcie)
+{
+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
+ irq_domain_remove(pcie->irq_domain);
+ irq_dispose_mapping(pcie->irq);
+}
+
static int altera_pcie_parse_dt(struct altera_pcie *pcie)
{
struct device *dev = &pcie->pdev->dev;
@@ -798,6 +806,7 @@ static int altera_pcie_probe(struct platform_device *pdev)
pcie = pci_host_bridge_priv(bridge);
pcie->pdev = pdev;
+ platform_set_drvdata(pdev, pcie);
match = of_match_device(altera_pcie_of_match, &pdev->dev);
if (!match)
@@ -855,13 +864,28 @@ static int altera_pcie_probe(struct platform_device *pdev)
return ret;
}
+static int altera_pcie_remove(struct platform_device *pdev)
+{
+ struct altera_pcie *pcie = platform_get_drvdata(pdev);
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
+
+ pci_stop_root_bus(bridge->bus);
+ pci_remove_root_bus(bridge->bus);
+ pci_free_resource_list(&pcie->resources);
+ altera_pcie_irq_teardown(pcie);
+
+ return 0;
+}
+
static struct platform_driver altera_pcie_driver = {
.probe = altera_pcie_probe,
+ .remove = altera_pcie_remove,
.driver = {
.name = "altera-pcie",
.of_match_table = altera_pcie_of_match,
- .suppress_bind_attrs = true,
},
};
-builtin_platform_driver(altera_pcie_driver);
+MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
+module_platform_driver(altera_pcie_driver);
+MODULE_LICENSE("GPL v2");
--
2.19.0
[GIT PULL] arch/nios2 updates for v5.1
Hi Linus Please pull the arch/nios2 updates below. Most of updates are MMU related. Thanks. Regards Ley Foon The following changes since commit 1c163f4c7b3f621efff9b28a47abb36f7378d783: Linux 5.0 (2019-03-03 15:21:29 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v5.1-rc1 for you to fetch changes up to 21e6bff5e0ef0033d776e64c40e6873d7c75e74b: nios2: Fix update_mmu_cache preload the TLB with the new PTE (2019-03-07 06:00:48 +0800) nios2 update for v5.1-rc1 nios2: Fix update_mmu_cache preload the TLB with the new PTE nios2: update_mmu_cache preload the TLB with the new PTE nios2: User address TLB flush break after finding the matching entry nios2: flush_tlb_all use TLBMISC way auto-increment feature nios2: improve readability of tlb functions nios2: flush_tlb_mm flush only the pid nios2: flush_tlb_pid can just restore TLBMISC once nios2: TLBMISC writes do not require PID bits to be set nios2: Use an invalid TLB entry address helper function nios2: pte_clear does not need to flush TLB nios2: flush_tlb_page use PID based flush nios2: update_mmu_cache clear the old entry from the TLB nios2: remove redundant 'default n' from Kconfig-s nios2: ksyms: Add missing symbol exports Bartlomiej Zolnierkiewicz (1): nios2: remove redundant 'default n' from Kconfig-s Guenter Roeck (1): nios2: ksyms: Add missing symbol exports Nicholas Piggin (12): nios2: update_mmu_cache clear the old entry from the TLB nios2: flush_tlb_page use PID based flush nios2: pte_clear does not need to flush TLB nios2: Use an invalid TLB entry address helper function nios2: TLBMISC writes do not require PID bits to be set nios2: flush_tlb_pid can just restore TLBMISC once nios2: flush_tlb_mm flush only the pid nios2: improve readability of tlb functions nios2: flush_tlb_all use TLBMISC way auto-increment feature nios2: User address TLB flush break after finding the matching entry nios2: update_mmu_cache preload the TLB with the new PTE nios2: Fix update_mmu_cache preload the TLB with the new PTE arch/nios2/Kconfig | 1 - arch/nios2/include/asm/pgtable.h | 1 - arch/nios2/include/asm/tlbflush.h| 19 +++- arch/nios2/kernel/nios2_ksyms.c | 12 +++ arch/nios2/mm/cacheflush.c | 7 +- arch/nios2/mm/fault.c| 2 +- arch/nios2/mm/tlb.c | 192 --- arch/nios2/platform/Kconfig.platform | 9 -- 8 files changed, 142 insertions(+), 101 deletions(-)
Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support
On Fri, 2019-03-01 at 14:15 +, Lorenzo Pieralisi wrote:
> On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote:
> >
> > On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote:
> > >
> > > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
> > >
> > > [...]
> > >
> > > >
> > > >
> > > > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32
> > > > *value)
> > > > +{
> > > > + int i;
> > > > + u32 ctrl;
> > > > + u32 comp_status;
> > > > + u32 dw[4];
> > > > + u32 count;
> > > > +
> > > > + for (i = 0; i < TLP_LOOP; i++) {
> > > > + ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
> > > > + if (!(ctrl & RP_RXCPL_SOP)) {
> > > > + udelay(5);
> > > > + continue;
> > > > + }
> > > > +
> > > > + /* Read first DW */
> > > > + dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
> > > > + count = 1;
> > > > +
> > > > + /* Poll for EOP */
> > > > + for (i = 0; i < TLP_LOOP && count <
> > > > ARRAY_SIZE(dw); i++) {
> > > > + ctrl = cra_readl(pcie,
> > > > S10_RP_RXCPL_STATUS);
> > > > + dw[count++] = cra_reeadl(pcie,
> > > > S10_RP_RXCPL_REG);
> > > > + if (ctrl & RP_RXCPL_EOP) {
> > > > + comp_status =
> > > > TLP_COMP_STATUS(dw[1]);
> > > > + if (comp_status)
> > > > + return
> > > > PCIBIOS_DEVICE_NOT_FOUND;
> > > > +
> > > > + if (value &&
> > > > + TLP_BYTE_COUNT(dw[1])
> > > > ==
> > > > sizeof(u32) &&
> > > > + count == 4)
> > > > + *value = dw[3];
> > > > +
> > > > + return PCIBIOS_SUCCESSFUL;
> > > > + }
> > > Two more things.
> > >
> > > - Why don't you need a udelay() in the inner loop ?
> > It has received start of packet (SOP) when in the inner loop, next
> > DW
> > will come on next. So, I don't add udelay here.
> > >
> > > - I think that count >= ARRAY_SIZE(dw) in the inner loop is an
> > > error
> > > ?? condition and it should be flagged up with a warning before
> > > exiting.
> > Yes, please add this.
> > >
> > >
> > > I can make these changes if you let me know your thoughts on
> > > this.
> > Please go ahead and change this.
> I rewrote the loop.
>
> Please have a look at my branch not-to-merge/pci-altera, if that's
> OK and it passes the kbot tests I will try to get it upstream.
>
> Lorenzo
We need return error if (i >= TLP_LOOP). Other than that is okay.
+ if (i >= TLP_LOOP)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
I also attached a patch in attachment to fix the Sparse warnings.
You can squash it to this patch.
Thanks.
Regards
Ley Foon
>
> >
> > Thanks.
> >
> > Regards
> > Ley Foon
> > >
> > >
> > > Lorenzo
> > >
> > > >
> > > >
> > > > + }
> > > > + }
> > > > +
> > > > + return PCIBIOS_DEVICE_NOT_FOUND;
> > > > +}
> > > > +
> > > > ??static void tlp_write_packet(struct altera_pcie *pcie, u32
> > > > *headers,
> > > > ?? ??u32 data, bool align)
> > > > ??{
> > > > @@ -210,6 +306,15 @@ static void tlp_write_packet(struct
> > > > altera_pcie *pcie, u32 *headers,
> > > > ?? tlp_write_tx(pcie, &tlp_rp_regdata);
> > > > ??}
> > > > ??
> > > > +static void s10_tlp_write_packet(struct altera_pcie *pcie, u32
> > > > *headers,
> > > > + ??u32 data, bool dummy)
> > > > +{
> > > > + s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
> > > >
Re: [PATCH 10/14] nios2: define syscall_get_arch()
On Wed, 2019-02-27 at 18:31 +0300, Dmitry V. Levin wrote:
> syscall_get_arch() is required to be implemented on all architectures
> in addition to already implemented syscall_get_nr(),
> syscall_get_arguments(), syscall_get_error(), and
> syscall_get_return_value() functions in order to extend the generic
> ptrace API with PTRACE_GET_SYSCALL_INFO request.
>
> Acked-by: Paul Moore
> Cc: Elvira Khabirova
> Cc: Eugene Syromyatnikov
> Cc: Ley Foon Tan
> Cc: Oleg Nesterov
> Cc: Andy Lutomirski
> Cc: nios2-...@lists.rocketboards.org
> Cc: linux-au...@redhat.com
> Signed-off-by: Dmitry V. Levin
Acked-by: Ley Foon Tan
Regards
Ley Foon
> ---
> This is just a gentle ping, the patch is unchanged.
>
> arch/nios2/include/asm/syscall.h | 6 ++
> include/uapi/linux/audit.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/arch/nios2/include/asm/syscall.h
> b/arch/nios2/include/asm/syscall.h
> index 9de220854c4a..cf35e210fc4d 100644
> --- a/arch/nios2/include/asm/syscall.h
> +++ b/arch/nios2/include/asm/syscall.h
> @@ -17,6 +17,7 @@
> #ifndef __ASM_NIOS2_SYSCALL_H__
> #define __ASM_NIOS2_SYSCALL_H__
>
> +#include
> #include
> #include
>
> @@ -135,4 +136,9 @@ static inline void syscall_set_arguments(struct
> task_struct *task,
> }
> }
>
> +static inline int syscall_get_arch(void)
> +{
> + return AUDIT_ARCH_NIOS2;
> +}
> +
> #endif
> diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h
> index 1568ddc1c945..efeb0bbd6c4d 100644
> --- a/include/uapi/linux/audit.h
> +++ b/include/uapi/linux/audit.h
> @@ -403,6 +403,7 @@ enum {
> __AUDIT_ARCH_CONVENTION_MIPS64_N32)
> #define AUDIT_ARCH_NDS32 (EM_NDS32|__AUDIT_ARCH_LE)
> #define AUDIT_ARCH_NDS32BE (EM_NDS32)
> +#define AUDIT_ARCH_NIOS2 (EM_ALTERA_NIOS2|__AUDIT_ARCH_LE)
> #define AUDIT_ARCH_OPENRISC(EM_OPENRISC)
> #define AUDIT_ARCH_PARISC (EM_PARISC)
> #define AUDIT_ARCH_PARISC64(EM_PARISC|__AUDIT_ARCH_64BIT)
> --
> ldv
>
>
>
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.
Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support
On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote:
> On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
>
> [...]
>
> >
> > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32
> > *value)
> > +{
> > + int i;
> > + u32 ctrl;
> > + u32 comp_status;
> > + u32 dw[4];
> > + u32 count;
> > +
> > + for (i = 0; i < TLP_LOOP; i++) {
> > + ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
> > + if (!(ctrl & RP_RXCPL_SOP)) {
> > + udelay(5);
> > + continue;
> > + }
> > +
> > + /* Read first DW */
> > + dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
> > + count = 1;
> > +
> > + /* Poll for EOP */
> > + for (i = 0; i < TLP_LOOP && count <
> > ARRAY_SIZE(dw); i++) {
> > + ctrl = cra_readl(pcie,
> > S10_RP_RXCPL_STATUS);
> > + dw[count++] = cra_reeadl(pcie,
> > S10_RP_RXCPL_REG);
> > + if (ctrl & RP_RXCPL_EOP) {
> > + comp_status =
> > TLP_COMP_STATUS(dw[1]);
> > + if (comp_status)
> > + return
> > PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + if (value &&
> > + TLP_BYTE_COUNT(dw[1]) ==
> > sizeof(u32) &&
> > + count == 4)
> > + *value = dw[3];
> > +
> > + return PCIBIOS_SUCCESSFUL;
> > + }
> Two more things.
>
> - Why don't you need a udelay() in the inner loop ?
It has received start of packet (SOP) when in the inner loop, next DW
will come on next. So, I don't add udelay here.
> - I think that count >= ARRAY_SIZE(dw) in the inner loop is an error
> condition and it should be flagged up with a warning before
> exiting.
Yes, please add this.
>
> I can make these changes if you let me know your thoughts on this.
Please go ahead and change this.
Thanks.
Regards
Ley Foon
>
> Lorenzo
>
> >
> > + }
> > + }
> > +
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +}
> > +
> > static void tlp_write_packet(struct altera_pcie *pcie, u32
> > *headers,
> > u32 data, bool align)
> > {
> > @@ -210,6 +306,15 @@ static void tlp_write_packet(struct
> > altera_pcie *pcie, u32 *headers,
> > tlp_write_tx(pcie, &tlp_rp_regdata);
> > }
> >
> > +static void s10_tlp_write_packet(struct altera_pcie *pcie, u32
> > *headers,
> > + u32 data, bool dummy)
> > +{
> > + s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
> > + s10_tlp_write_tx(pcie, headers[1], 0);
> > + s10_tlp_write_tx(pcie, headers[2], 0);
> > + s10_tlp_write_tx(pcie, data, RP_TX_EOP);
> > +}
> > +
> > static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus,
> > u32 devfn,
> > int where, u8 byte_en, u32 *value)
> > {
> > @@ -219,9 +324,9 @@ static int tlp_cfg_dword_read(struct
> > altera_pcie *pcie, u8 bus, u32 devfn,
> > headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
> > headers[2] = TLP_CFG_DW2(bus, devfn, where);
> >
> > - tlp_write_packet(pcie, headers, 0, false);
> > + pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0,
> > false);
> >
> > - return tlp_read_packet(pcie, value);
> > + return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
> > }
> >
> > static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus,
> > u32 devfn,
> > @@ -236,11 +341,13 @@ static int tlp_cfg_dword_write(struct
> > altera_pcie *pcie, u8 bus, u32 devfn,
> >
> > /* check alignment to Qword */
> > if ((where & 0x7) == 0)
> > - tlp_write_packet(pcie, headers, value, true);
> > + pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
> > + value, true);
> > else
> > - tlp_write_packet(pcie, headers, value, false);
> > + pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
> > + value, false);
> >
> > - ret = tlp_read_packet(pcie, NULL);
> > + ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
> > if (r
[PATCH v6 3/3] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f17c91a..816b244a221e 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 2.19.0
[PATCH v6 2/3] PCI: altera: Enable driver on ARM64
Enable PCIE_ALTERA on ARM64 platform. Signed-off-by: Ley Foon Tan --- drivers/pci/controller/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 6671946dbf66..6012f3059acd 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI config PCIE_ALTERA bool "Altera PCIe controller" - depends on ARM || NIOS2 || COMPILE_TEST + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST help Say Y here if you want to enable PCIe controller support on Altera FPGA. -- 2.19.0
[PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences compare with PCIe Root Port IP on Cyclone V
and Arria 10 devices:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 264 ---
1 file changed, 240 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51205b3..c57fd7f4e848 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,47 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
+enum altera_pcie_version {
+ ALTERA_PCIE_V1 = 0,
+ ALTERA_PCIE_V2,
+};
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_ops {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
+ int where, int size, u32 value);
+};
+
+struct altera_pcie_data {
+ const struct altera_pcie_ops *ops;
+ enum altera_pcie_version version;
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -101,6 +141,15 @@ static bool altera_pcie_link_up(struct altera_pcie *pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+ void __iomem *addr = S10_RP_CFG_ADDR(pcie,
+
[PATCH v6 0/3] Add Stratix 10 PCIe Root Port support
Add PCIe Root Port support for Stratix 10 device and also update device tree binding documentation. v5 -> v6: - - Move udelay to SOP polling - Move count checking to for loop condition - Change dw[count++] to dw[0] for first DW v4 -> v5: - - Add struct altera_pcie_ops - Add count checking in s10_tlp_read_packet() v3 -> v4: - - Separate Kconfig change to a patch - Change cast to mask v2 -> v3: - - Rename Stratix10 to Stratix 10. - Change bool s10_flag to enum version. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 [v2]: https://lkml.org/lkml/2018/12/31/46 [v3]: https://lkml.org/lkml/2019/1/2/16 [v4]: https://lkml.org/lkml/2019/2/14/58 [v5]: https://lkml.org/lkml/2019/2/26/200 Ley Foon Tan (3): PCI: altera: Add Stratix 10 PCIe support PCI: altera: Enable driver on ARM64 dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt | 4 +- drivers/pci/controller/Kconfig| 2 +- drivers/pci/controller/pcie-altera.c | 264 -- 3 files changed, 244 insertions(+), 26 deletions(-) -- 2.19.0
Re: [PATCH v5 1/3] PCI: altera: Add Stratix 10 PCIe support
On Wed, 2019-02-27 at 17:38 +, Lorenzo Pieralisi wrote:
> On Tue, Feb 26, 2019 at 05:15:46PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences compare with PCIe Root Port IP on Cyclone V
> > and Arria 10 devices:
> >
> > - HIP interface to access Root Port configuration register.
> > - TLP programming flow:
> > - One REG0 register
> > - Don't need to check alignment
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > drivers/pci/controller/pcie-altera.c | 266
> > ---
> > 1 file changed, 242 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-altera.c
> > b/drivers/pci/controller/pcie-altera.c
> > index 7d05e51205b3..b3c05f2f309b 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -11,6 +11,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -37,7 +38,12 @@
> > #define RP_LTSSM_MASK 0x1f
> > #define LTSSM_L0 0xf
> >
> > -#define PCIE_CAP_OFFSET0x80
> > +#define S10_RP_TX_CNTRL0x2004
> > +#define S10_RP_RXCPL_REG 0x2008
> > +#define S10_RP_RXCPL_STATUS0x200C
> > +#define S10_RP_CFG_ADDR(pcie, reg) \
> > + (((pcie)->hip_base) + (reg) + (1 << 20))
> > +
> > /* TLP configuration type 0 and 1 */
> > #define TLP_FMTTYPE_CFGRD0 0x04/*
> > Configuration Read Type 0 */
> > #define TLP_FMTTYPE_CFGWR0 0x44/*
> > Configuration Write Type 0 */
> > @@ -49,18 +55,19 @@
> > #define RP_DEVFN 0
> > #define TLP_REQ_ID(bus, devfn) (((bus) << 8) |
> > (devfn))
> > #define TLP_CFGRD_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0
> > \
> > - : TLP_FMTTYPE_CFGRD1) << 24) |
> > \
> > - TLP_PAYLOAD_SIZE)
> > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0
> > \
> > + : pcie->pcie_data->cfgrd1) << 24)
> > | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFGWR_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0
> > \
> > - : TLP_FMTTYPE_CFGWR1) << 24) |
> > \
> > - TLP_PAYLOAD_SIZE)
> > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0
> > \
> > + : pcie->pcie_data->cfgwr1) << 24)
> > | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFG_DW1(pcie, tag, be) \
> > -(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag <<
> > 8) | (be))
> > + (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag
> > << 8) | (be))
> > #define TLP_CFG_DW2(bus, devfn, offset)\
> > (((bus) << 24) | ((devfn) << 16) |
> > (offset))
> > #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
> > +#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
> > #define TLP_HDR_SIZE 3
> > #define TLP_LOOP 500
> >
> > @@ -69,14 +76,47 @@
> >
> > #define DWORD_MASK 3
> >
> > +#define S10_TLP_FMTTYPE_CFGRD0 0x05
> > +#define S10_TLP_FMTTYPE_CFGRD1 0x04
> > +#define S10_TLP_FMTTYPE_CFGWR0 0x45
> > +#define S10_TLP_FMTTYPE_CFGWR1 0x44
> > +
> > +enum altera_pcie_version {
> > + ALTERA_PCIE_V1 = 0,
> > + ALTERA_PCIE_V2,
> > +};
> > +
> > struct altera_pcie {
> > struct platform_device *pdev;
> > - void __iomem*cra_base; /* DT Cra */
> > + void __iomem*cra_base;
> > + void __iomem*hip_base;
> > int irq;
> > u8 root_bus_nr;
> > struct irq_domain *irq_domain;
> > struct resource bus_range;
> > struct list_headresources;
> > + const struct altera_pcie_data *pcie_data;
> > +
[PATCH v5 2/3] PCI: altera: Enable driver on ARM64
Enable PCIE_ALTERA on ARM64 platform. Signed-off-by: Ley Foon Tan --- drivers/pci/controller/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 6671946dbf66..6012f3059acd 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI config PCIE_ALTERA bool "Altera PCIe controller" - depends on ARM || NIOS2 || COMPILE_TEST + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST help Say Y here if you want to enable PCIe controller support on Altera FPGA. -- 2.19.0
[PATCH v5 0/3] Add Stratix 10 PCIe Root Port support
Add PCIe Root Port support for Stratix 10 device and also update device tree binding documentation. v4 -> v5: - - Add struct altera_pcie_ops - Add count checking in s10_tlp_read_packet() v3 -> v4: - - Separate Kconfig change to a patch - Change cast to mask v2 -> v3: - - Rename Stratix10 to Stratix 10. - Change bool s10_flag to enum version. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 [v2]: https://lkml.org/lkml/2018/12/31/46 [v3]: https://lkml.org/lkml/2019/1/2/16 [v4]: https://lkml.org/lkml/2019/2/14/58 Ley Foon Tan (3): PCI: altera: Add Stratix 10 PCIe support PCI: altera: Enable driver on ARM64 dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt | 4 +- drivers/pci/controller/Kconfig| 2 +- drivers/pci/controller/pcie-altera.c | 266 -- 3 files changed, 246 insertions(+), 26 deletions(-) -- 2.19.0
[PATCH v5 1/3] PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences compare with PCIe Root Port IP on Cyclone V
and Arria 10 devices:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 266 ---
1 file changed, 242 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51205b3..b3c05f2f309b 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,47 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
+enum altera_pcie_version {
+ ALTERA_PCIE_V1 = 0,
+ ALTERA_PCIE_V2,
+};
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_ops {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
+ int where, int size, u32 value);
+};
+
+struct altera_pcie_data {
+ const struct altera_pcie_ops *ops;
+ enum altera_pcie_version version;
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -101,6 +141,15 @@ static bool altera_pcie_link_up(struct altera_pcie *pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+ void __iomem *addr = S10_RP_CFG_ADDR(pcie,
+
[PATCH v5 3/3] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f17c91a..816b244a221e 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 2.19.0
Re: [PATCH v4 1/3] PCI: altera: Add Stratix 10 PCIe support
On Mon, Feb 25, 2019 at 5:35 PM Ley Foon Tan wrote:
>
> On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> > On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> > >
> > > Add PCIe Root Port support for Stratix 10 device.
> > >
> > > Main differences:
> > Main differences with what ? We need to rewrite this commit log.
> Differences compare with Cyclone V and Arria 10 devices.
> I will rewrite this.
> >
> > >
> > > - HIP interface to access Root Port configuration register.
> > > - TLP programming flow:
> > > - One REG0 register
> > > - Don't need to check alignment
> > >
> > > Signed-off-by: Ley Foon Tan
> > > ---
> > > drivers/pci/controller/pcie-altera.c | 246
> > > ++
> > > 1 files changed, 222 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-altera.c
> > > b/drivers/pci/controller/pcie-altera.c
> > > index 7d05e51..76bb6a6 100644
> > > --- a/drivers/pci/controller/pcie-altera.c
> > > +++ b/drivers/pci/controller/pcie-altera.c
> > > @@ -11,6 +11,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -37,7 +38,12 @@
> > > #define RP_LTSSM_MASK 0x1f
> > > #define LTSSM_L0 0xf
> > >
> > > -#define PCIE_CAP_OFFSET0x80
> > > +#define S10_RP_TX_CNTRL0x2004
> > > +#define S10_RP_RXCPL_REG 0x2008
> > > +#define S10_RP_RXCPL_STATUS0x200C
> > > +#define S10_RP_CFG_ADDR(pcie, reg) \
> > > + (((pcie)->hip_base) + (reg) + (1 << 20))
> > > +
> > > /* TLP configuration type 0 and 1 */
> > > #define TLP_FMTTYPE_CFGRD0 0x04/*
> > > Configuration Read Type 0 */
> > > #define TLP_FMTTYPE_CFGWR0 0x44/*
> > > Configuration Write Type 0 */
> > > @@ -49,18 +55,19 @@
> > > #define RP_DEVFN 0
> > > #define TLP_REQ_ID(bus, devfn) (((bus) << 8) |
> > > (devfn))
> > > #define TLP_CFGRD_DW0(pcie, bus)
> > > \
> > > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0
> > > \
> > > - : TLP_FMTTYPE_CFGRD1) << 24) |
> > > \
> > > - TLP_PAYLOAD_SIZE)
> > > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0
> > > \
> > > + : pcie->pcie_data->cfgrd1) << 24)
> > > | \
> > > + TLP_PAYLOAD_SIZE)
> > > #define TLP_CFGWR_DW0(pcie, bus)
> > > \
> > > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0
> > > \
> > > - : TLP_FMTTYPE_CFGWR1) << 24) |
> > > \
> > > - TLP_PAYLOAD_SIZE)
> > > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0
> > > \
> > > + : pcie->pcie_data->cfgwr1) << 24)
> > > | \
> > > + TLP_PAYLOAD_SIZE)
> > > #define TLP_CFG_DW1(pcie, tag, be) \
> > > -(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag <<
> > > 8) | (be))
> > > + (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag
> > > << 8) | (be))
> > > #define TLP_CFG_DW2(bus, devfn, offset)\
> > > (((bus) << 24) | ((devfn) << 16) |
> > > (offset))
> > > #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
> > > +#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
> > > #define TLP_HDR_SIZE 3
> > > #define TLP_LOOP 500
> > >
> > > @@ -69,14 +76,43 @@
> > >
> > > #define DWORD_MASK 3
> > >
> > > +#define S10_TLP_FMTTYPE_CFGRD0 0x05
> > > +#define S10_TLP_FMTTYPE_CFGRD1 0x04
> > > +#define S10_TLP_FMTTYPE_CFGWR0 0x45
> > > +#define S10_TLP_FMTTYPE_CFGWR1 0x44
> > > +
> > > +enum altera_pcie_version {
> > > + ALTERA_PCIE_V1 = 0,
> > > + ALTERA_PCIE_V2,
> > > +};
> > > +
> &
Re: [PATCH v4 1/3] PCI: altera: Add Stratix 10 PCIe support
On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences:
> Main differences with what ? We need to rewrite this commit log.
Differences compare with Cyclone V and Arria 10 devices.
I will rewrite this.
>
> >
> > - HIP interface to access Root Port configuration register.
> > - TLP programming flow:
> > - One REG0 register
> > - Don't need to check alignment
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > drivers/pci/controller/pcie-altera.c | 246
> > ++
> > 1 files changed, 222 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-altera.c
> > b/drivers/pci/controller/pcie-altera.c
> > index 7d05e51..76bb6a6 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -11,6 +11,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -37,7 +38,12 @@
> > #define RP_LTSSM_MASK 0x1f
> > #define LTSSM_L0 0xf
> >
> > -#define PCIE_CAP_OFFSET0x80
> > +#define S10_RP_TX_CNTRL0x2004
> > +#define S10_RP_RXCPL_REG 0x2008
> > +#define S10_RP_RXCPL_STATUS0x200C
> > +#define S10_RP_CFG_ADDR(pcie, reg) \
> > + (((pcie)->hip_base) + (reg) + (1 << 20))
> > +
> > /* TLP configuration type 0 and 1 */
> > #define TLP_FMTTYPE_CFGRD0 0x04/*
> > Configuration Read Type 0 */
> > #define TLP_FMTTYPE_CFGWR0 0x44/*
> > Configuration Write Type 0 */
> > @@ -49,18 +55,19 @@
> > #define RP_DEVFN 0
> > #define TLP_REQ_ID(bus, devfn) (((bus) << 8) |
> > (devfn))
> > #define TLP_CFGRD_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0
> > \
> > - : TLP_FMTTYPE_CFGRD1) << 24) |
> > \
> > - TLP_PAYLOAD_SIZE)
> > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0
> > \
> > + : pcie->pcie_data->cfgrd1) << 24)
> > | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFGWR_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0
> > \
> > - : TLP_FMTTYPE_CFGWR1) << 24) |
> > \
> > - TLP_PAYLOAD_SIZE)
> > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0
> > \
> > + : pcie->pcie_data->cfgwr1) << 24)
> > | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFG_DW1(pcie, tag, be) \
> > -(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag <<
> > 8) | (be))
> > + (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag
> > << 8) | (be))
> > #define TLP_CFG_DW2(bus, devfn, offset)\
> > (((bus) << 24) | ((devfn) << 16) |
> > (offset))
> > #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
> > +#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
> > #define TLP_HDR_SIZE 3
> > #define TLP_LOOP 500
> >
> > @@ -69,14 +76,43 @@
> >
> > #define DWORD_MASK 3
> >
> > +#define S10_TLP_FMTTYPE_CFGRD0 0x05
> > +#define S10_TLP_FMTTYPE_CFGRD1 0x04
> > +#define S10_TLP_FMTTYPE_CFGWR0 0x45
> > +#define S10_TLP_FMTTYPE_CFGWR1 0x44
> > +
> > +enum altera_pcie_version {
> > + ALTERA_PCIE_V1 = 0,
> > + ALTERA_PCIE_V2,
> > +};
> > +
> > struct altera_pcie {
> > struct platform_device *pdev;
> > - void __iomem*cra_base; /* DT Cra */
> > + void __iomem*cra_base;
> > + void __iomem*hip_base;
> > int irq;
> > u8 root_bus_nr;
> > struct irq_domain *irq_domain;
> > struct resource bus_range;
> > struct list_headresources;
> > +
Re: [PATCH 05/11] tracing: consolidate the TRACE_IRQFLAGS_SUPPORT symbol
On Fri, 2019-02-15 at 16:55 +0900, Masahiro Yamada wrote: > +CC: Ley Foon Tan > +CC: nios2-...@lists.rocketboards.org > > > On Thu, Feb 14, 2019 at 2:40 AM Christoph Hellwig wrote: > > > > > diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig > > index 715e6c09b4a5..3b50689007f5 100644 > > --- a/arch/nios2/Kconfig > > +++ b/arch/nios2/Kconfig > > @@ -20,6 +20,7 @@ config NIOS2 > > select OF_EARLY_FLATTREE > > select SOC_BUS > > select SPARSE_IRQ > > + select TRACE_IRQFLAGS_SUPPORT > > This is a behavior change of nios2. > > TRACE_IRQFLAGS_SUPPORT was previously 'n', > and this commit is changing it to 'y'. > > > > > Strangely, nios2 defines TRACE_IRQFLAGS_SUPPORT twice > with different default values. > > In Kconfig, the first one becomes effective. > > In this case, 'def_bool n' in arch/nios2/Kconfig is used. > 'def_bool y' in arch/nios2/Kconfig.debug is dead code. > > > I think this select should be dropped > to keep the current behavior, > but I hope the NIOS2 maintainer will give us > some comments just in case. > Yes, please drop this patch to keep original behavior. Thanks. Regards Ley Foon > > > > > > > select USB_ARCH_HAS_HCD if USB_SUPPORT > > select CPU_NO_EFFICIENT_FFS > > select ARCH_DISCARD_MEMBLOCK > > @@ -39,9 +40,6 @@ config NO_IOPORT_MAP > > config FPU > > def_bool n > > > > -config TRACE_IRQFLAGS_SUPPORT > > - def_bool n > > - > > menu "Kernel features" > > > > source "kernel/Kconfig.hz" > > diff --git a/arch/nios2/Kconfig.debug b/arch/nios2/Kconfig.debug > > index f1da8a7b17ff..a8bc06e96ef5 100644 > > --- a/arch/nios2/Kconfig.debug > > +++ b/arch/nios2/Kconfig.debug > > @@ -1,8 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > > > -config TRACE_IRQFLAGS_SUPPORT > > - def_bool y > > - > > config EARLY_PRINTK > > bool "Activate early kernel debugging" > > default y > -- > Best Regards > Masahiro Yamada > > > > Confidentiality Notice. > This message may contain information that is confidential or > otherwise protected from disclosure. If you are not the intended > recipient, you are hereby notified that any use, disclosure, > dissemination, distribution, or copying of this message, or any > attachments, is strictly prohibited. If you have received this > message in error, please advise the sender by reply e-mail, and > delete the message and any attachments. Thank you.
[PATCH v4 2/3] PCI: altera: Enable driver on ARM64
Enable PCIE_ALTERA on ARM64 platform. Signed-off-by: Ley Foon Tan --- drivers/pci/controller/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 6671946..6012f30 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI config PCIE_ALTERA bool "Altera PCIe controller" - depends on ARM || NIOS2 || COMPILE_TEST + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST help Say Y here if you want to enable PCIe controller support on Altera FPGA. -- 1.7.1
[PATCH v4 0/3] Add Stratix 10 PCIe Root Port support
Add PCIe Root Port support for Stratix 10 device and also update device tree binding documentation. v3 -> v4: - - Separate Kconfig change to a patch - Change cast to mask v2 -> v3: - - Rename Stratix10 to Stratix 10. - Change bool s10_flag to enum version. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 [v2]: https://lkml.org/lkml/2018/12/31/46 [v3]: https://lkml.org/lkml/2019/1/2/16 Ley Foon Tan (3): PCI: altera: Add Stratix 10 PCIe support PCI: altera: Enable driver on ARM64 dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt|4 +- drivers/pci/controller/Kconfig |2 +- drivers/pci/controller/pcie-altera.c | 246 ++-- 3 files changed, 226 insertions(+), 26 deletions(-)
[PATCH v4 3/3] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/altera-pcie.txt|4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f1..816b244 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 1.7.1
[PATCH v4 1/3] PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 246 ++
1 files changed, 222 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..76bb6a6 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,43 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
+enum altera_pcie_version {
+ ALTERA_PCIE_V1 = 0,
+ ALTERA_PCIE_V2,
+};
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_data {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+ int size, u32 value);
+ enum altera_pcie_version version;
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -101,6 +137,15 @@ static bool altera_pcie_link_up(struct altera_pcie *pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+ void __iomem *addr = S10_RP_CFG_ADDR(pcie,
+ pcie->pcie_data->cap_offset +
+ PCI_EXP_LNKSTA);
+
+ return !!(readw(addr) & PCI_EXP_LNKSTA_DLLL
Re: [PATCH v3 1/2] PCI: altera: Add Stratix 10 PCIe support
On Sat, Feb 9, 2019 at 12:29 AM Lorenzo Pieralisi wrote: > > Apologies, I have dropped the ball on this one. > > On Wed, Jan 02, 2019 at 02:16:48PM +0800, Ley Foon Tan wrote: > > Add PCIe Root Port support for Stratix 10 device. > > > > Main differences: > > - HIP interface to access Root Port configuration register. > > - TLP programming flow: > > - One REG0 register > > - Don't need to check alignment > > > > Signed-off-by: Ley Foon Tan > > --- > > drivers/pci/controller/Kconfig |2 +- > > drivers/pci/controller/pcie-altera.c | 246 > > ++ > > 2 files changed, 223 insertions(+), 25 deletions(-) > > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > > index 6671946..6012f30 100644 > > --- a/drivers/pci/controller/Kconfig > > +++ b/drivers/pci/controller/Kconfig > > @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI > > > > config PCIE_ALTERA > > bool "Altera PCIe controller" > > - depends on ARM || NIOS2 || COMPILE_TEST > > + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST > > This is an unrelated change and should be a separate patch. Noted. > > > help > > Say Y here if you want to enable PCIe controller support on Altera > > FPGA. > > diff --git a/drivers/pci/controller/pcie-altera.c > > b/drivers/pci/controller/pcie-altera.c > > index 7d05e51..4c3b61b 100644 > > --- a/drivers/pci/controller/pcie-altera.c > > +++ b/drivers/pci/controller/pcie-altera.c > > @@ -11,6 +11,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -37,7 +38,12 @@ > > #define RP_LTSSM_MASK0x1f > > #define LTSSM_L0 0xf > > > > -#define PCIE_CAP_OFFSET 0x80 > > +#define S10_RP_TX_CNTRL 0x2004 > > +#define S10_RP_RXCPL_REG 0x2008 > > +#define S10_RP_RXCPL_STATUS 0x200C > > +#define S10_RP_CFG_ADDR(pcie, reg) \ > > + (((pcie)->hip_base) + (reg) + (1 << 20)) > > + > > /* TLP configuration type 0 and 1 */ > > #define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 > > */ > > #define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 > > */ > > @@ -49,18 +55,19 @@ > > #define RP_DEVFN 0 > > #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) > > #define TLP_CFGRD_DW0(pcie, bus) \ > > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 > > \ > > - : TLP_FMTTYPE_CFGRD1) << 24) | \ > > - TLP_PAYLOAD_SIZE) > > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \ > > + : pcie->pcie_data->cfgrd1) << 24) | \ > > + TLP_PAYLOAD_SIZE) > > #define TLP_CFGWR_DW0(pcie, bus) \ > > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 > > \ > > - : TLP_FMTTYPE_CFGWR1) << 24) | \ > > - TLP_PAYLOAD_SIZE) > > + bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \ > > + : pcie->pcie_data->cfgwr1) << 24) | \ > > + TLP_PAYLOAD_SIZE) > > #define TLP_CFG_DW1(pcie, tag, be) \ > > -(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | > > (be)) > > + (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | > > (be)) > > #define TLP_CFG_DW2(bus, devfn, offset) \ > > (((bus) << 24) | ((devfn) << 16) | (offset)) > > #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) > > +#define TLP_BYTE_COUNT(s)(((s) >> 0) & 0xfff) > > #define TLP_HDR_SIZE 3 > > #define TLP_LOOP 500 > > > > @@ -69,14 +76,43 @@ > > > > #define DWORD_MASK 3 > > > > +#define S10_TLP_FMTTYPE_CFGRD0 0x05 > > +#define S10_TLP_FMTTYPE_CFGRD1 0x04 > > +#define S10_TLP_FMTTYPE_CFGWR0 0x45 > > +#define S10_TLP_FMTTYPE_CFGWR1 0x44 > > + > >
Re: [PATCH v3 0/2] Add Stratix 10 PCIe Root Port support
On Wed, 2019-01-02 at 14:16 +0800, Ley Foon Tan wrote: > Add PCIe Root Port support for Stratix 10 device and also update > device tree binding documentation. > > v2 -> v3: > - > - Rename Stratix10 to Stratix 10. > - Change bool s10_flag to enum version. > > v1 -> v2: > - > - Add define S10_TLP_FMTTYPE_* macros. > - Remove initialize structure members to NULL/zero. > - Rename *_funcs to *_data. > - Update comment and fix coding style warning from checkpatch.pl. > - Rename StratixXX to stratix10. > > History: > > [v1]: https://lkml.org/lkml/2018/12/26/68 > [v2]: https://lkml.org/lkml/2018/12/31/46 > > Ley Foon Tan (2): > PCI: altera: Add Stratix 10 PCIe support > dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 > > .../devicetree/bindings/pci/altera-pcie.txt|4 +- > drivers/pci/controller/Kconfig |2 +- > drivers/pci/controller/pcie-altera.c | 246 > ++-- > 3 files changed, 226 insertions(+), 26 deletions(-) > Hi, Any further comment on these patches? Regards Ley Foon
[PATCH v3 0/2] Add Stratix 10 PCIe Root Port support
Add PCIe Root Port support for Stratix 10 device and also update device tree binding documentation. v2 -> v3: - - Rename Stratix10 to Stratix 10. - Change bool s10_flag to enum version. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 [v2]: https://lkml.org/lkml/2018/12/31/46 Ley Foon Tan (2): PCI: altera: Add Stratix 10 PCIe support dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt|4 +- drivers/pci/controller/Kconfig |2 +- drivers/pci/controller/pcie-altera.c | 246 ++-- 3 files changed, 226 insertions(+), 26 deletions(-)
[PATCH v3 1/2] PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
drivers/pci/controller/pcie-altera.c | 246 ++
2 files changed, 223 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946..6012f30 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -175,7 +175,7 @@ config PCIE_IPROC_MSI
config PCIE_ALTERA
bool "Altera PCIe controller"
- depends on ARM || NIOS2 || COMPILE_TEST
+ depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
help
Say Y here if you want to enable PCIe controller support on Altera
FPGA.
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..4c3b61b 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,43 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
+enum altera_pcie_version {
+ ALTERA_PCIE_V1 = 0,
+ ALTERA_PCIE_V2,
+};
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_data {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+ int size, u32 value);
+ enum altera_pcie_version version;
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
[PATCH v3 2/2] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan --- .../devicetree/bindings/pci/altera-pcie.txt|4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f1..816b244 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 1.7.1
Re: [PATCH v2 1/2] pci: altera: Add Stratix10 PCIe support
On Mon, 2018-12-31 at 09:17 -0600, Bjorn Helgaas wrote:
> Run "git log --oneline --follow drivers/pci/controller/pcie-altera.c"
> and
> make your subject line match in style, phrasing, and capitalization.
>
> Hint:
>
> pci: altera: Add Stratix10 PCIe support
> ef75369a5b9a PCI: altera: Fix platform_get_irq() error handling
> bfdbbf0e3c2a PCI: altera: Use size=4 IRQ domain for legacy INTx
> 6ab380957838 PCI: altera: Drop pci_fixup_irqs()
> 9815791319a0 PCI: altera: Convert PCI scan API to
> pci_scan_root_bus_bridge()
> 2a7275a3d867 PCI: altera: Fix TLP_CFG_DW0 for TLP write
>
> One of these is not like the others.
Okay, will change it.
>
> On Mon, Dec 31, 2018 at 04:24:52PM +0800, Ley Foon Tan wrote:
> ...
> >
> > +struct altera_pcie_data {
> > + int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
> > + void (*tlp_write_pkt)(struct altera_pcie *pcie, u32
> > *headers,
> > + u32 data, bool align);
> > + bool (*get_link_status)(struct altera_pcie *pcie);
> > + int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
> > + int size, u32 *value);
> > + int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int
> > where,
> > + int size, u32 value);
> > + bool s10_flag; /* Stratix 10 */
> This is OK if you only ever have two programming models (the original
> and Stratix 10). But if there's a possibility of more, an int model
> type that can be tested with a switch is more extensible.
>
> Personally I prefer bitfields over bool in structures, but ultimately
> Lorenzo will take this and I don't know whether he has a preference.
>
> https://lkml.kernel.org/r/CA+55aFxnePDimkVKVtv3gNmRGcwc8KQ5mHYvUxY8sA
> qg6yv...@mail.gmail.com
> https://lkml.kernel.org/r/CA+55aFzKQ6Pj18TB8p4Yr0M4t+S+BsiHH=BJNmn=76
> -ncjt...@mail.gmail.com
Yes, you are right. Will change it to something like "version type".
Regards
Ley Foon
Re: [PATCH v2 0/2] Add Stratix10 PCIe Root Port support
On Mon, 2018-12-31 at 10:15 -0600, Bjorn Helgaas wrote: > On Mon, Dec 31, 2018 at 04:24:51PM +0800, Ley Foon Tan wrote: > > > > Add PCIe Root Port support for Stratix10 device and also update > "Stratix10" is a big step better than "StratixXX" because a web > search > for the latter finds nothing, while the former does find useful > things. > > Intel materials on the web seem to use "Stratix 10". You might as > well include the space in English text. Okay, will change to Stratix 10. Regards Ley Foon
[PATCH v2 1/2] pci: altera: Add Stratix10 PCIe support
Add PCIe Root Port support for Stratix10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
drivers/pci/controller/pcie-altera.c | 240 ++
2 files changed, 217 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946..6012f30 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -175,7 +175,7 @@ config PCIE_IPROC_MSI
config PCIE_ALTERA
bool "Altera PCIe controller"
- depends on ARM || NIOS2 || COMPILE_TEST
+ depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
help
Say Y here if you want to enable PCIe controller support on Altera
FPGA.
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..385b822 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,38 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_data {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+ int size, u32 value);
+ bool s10_flag; /* Stratix 10 */
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp
[PATCH v2 0/2] Add Stratix10 PCIe Root Port support
Add PCIe Root Port support for Stratix10 device and also update device tree binding documentation. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 Ley Foon Tan (2): pci: altera: Add Stratix10 PCIe support Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt|4 +- drivers/pci/controller/Kconfig |2 +- drivers/pci/controller/pcie-altera.c | 240 ++-- 3 files changed, 220 insertions(+), 26 deletions(-)
[PATCH v2 2/2] Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan --- .../devicetree/bindings/pci/altera-pcie.txt|4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f1..816b244 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 1.7.1
Re: [PATCH 1/2] pci: altera: Add StratixXX PCIe support
On Fri, 2018-12-28 at 21:12 -0600, Bjorn Helgaas wrote:
> Run "git log --oneline drivers/pci/controller" and make your subject
> line
> match in style, phrasing, and capitalization.
>
> On Thu, Dec 27, 2018 at 01:09:45AM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe rootport support for StratixXX device.
> s/rootport/Root Port/
Noted.
>
> I don't know what the correct styling of "StratixXX" is. You also
> have
> "Stratix xx" below. Both (and the subject line) should probably
> match?
Will change it to Stratix10.
>
> >
> > Main differences:
> > - HIP interface
> > - TLP programming flow
> It'd be nice to elaborate on these differences a little bit.
Okay.
>
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > drivers/pci/controller/Kconfig |2 +-
> > drivers/pci/controller/pcie-altera.c | 228
> > +++---
> > 2 files changed, 209 insertions(+), 21 deletions(-)
> > mode change 100644 => 100755 drivers/pci/controller/Kconfig
> >
> > diff --git a/drivers/pci/controller/Kconfig
> > b/drivers/pci/controller/Kconfig
> > old mode 100644
> > new mode 100755
> > index 6671946..6012f30
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI
> >
> > config PCIE_ALTERA
> > bool "Altera PCIe controller"
> > - depends on ARM || NIOS2 || COMPILE_TEST
> > + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
> > help
> > Say Y here if you want to enable PCIe controller support
> > on Altera
> > FPGA.
> > diff --git a/drivers/pci/controller/pcie-altera.c
> > b/drivers/pci/controller/pcie-altera.c
> > index 7d05e51..b9d6eb2 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -11,6 +11,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -37,7 +38,12 @@
> > #define RP_LTSSM_MASK 0x1f
> > #define LTSSM_L0 0xf
> >
> > -#define PCIE_CAP_OFFSET0x80
> > +#define SXX_RP_TX_CNTRL0x2004
> > +#define SXX_RP_RXCPL_REG 0x2008
> > +#define SXX_RP_RXCPL_STATUS0x200C
> > +#define SXX_RP_CFG_ADDR(pcie, reg) \
> > + ((pcie->hip_base) + (reg) + (1 << 20))
> > +
> > /* TLP configuration type 0 and 1 */
> > #define TLP_FMTTYPE_CFGRD0 0x04/*
> > Configuration Read Type 0 */
> > #define TLP_FMTTYPE_CFGWR0 0x44/*
> > Configuration Write Type 0 */
> > @@ -49,18 +55,19 @@
> > #define RP_DEVFN 0
> > #define TLP_REQ_ID(bus, devfn) (((bus) << 8) |
> > (devfn))
> > #define TLP_CFGRD_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0
> > \
> > - : TLP_FMTTYPE_CFGRD1) << 24) |
> > \
> > +bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0
> > \
> > + : pcie->pcie_data->cfgrd1) <<
> > 24) | \
> > TLP_PAYLOAD_SIZE)
> > #define TLP_CFGWR_DW0(pcie, bus)
> > \
> > -bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0
> > \
> > - : TLP_FMTTYPE_CFGWR1) << 24) |
> > \
> > +bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0
> > \
> > + : pcie->pcie_data->cfgwr1) <<
> > 24) | \
> > TLP_PAYLOAD_SIZE)
> > #define TLP_CFG_DW1(pcie, tag, be) \
> > (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag <<
> > 8) | (be))
> > #define TLP_CFG_DW2(bus, devfn, offset)\
> > (((bus) << 24) | ((devfn) << 16) |
> > (offset))
> > #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
> > +#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
> > #define TLP_HDR_SIZE 3
> > #define TLP_LOOP 500
> >
> > @@ -72,11 +79,30 @@
> > struct altera_pcie {
> > struct platform_device *pdev;
> > void __iomem*cra_base; /* DT C
[PATCH 1/2] pci: altera: Add StratixXX PCIe support
Add PCIe rootport support for StratixXX device.
Main differences:
- HIP interface
- TLP programming flow
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/Kconfig |2 +-
drivers/pci/controller/pcie-altera.c | 228 +++---
2 files changed, 209 insertions(+), 21 deletions(-)
mode change 100644 => 100755 drivers/pci/controller/Kconfig
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
old mode 100644
new mode 100755
index 6671946..6012f30
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -175,7 +175,7 @@ config PCIE_IPROC_MSI
config PCIE_ALTERA
bool "Altera PCIe controller"
- depends on ARM || NIOS2 || COMPILE_TEST
+ depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
help
Say Y here if you want to enable PCIe controller support on Altera
FPGA.
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..b9d6eb2 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define SXX_RP_TX_CNTRL0x2004
+#define SXX_RP_RXCPL_REG 0x2008
+#define SXX_RP_RXCPL_STATUS0x200C
+#define SXX_RP_CFG_ADDR(pcie, reg) \
+ ((pcie->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
+bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0\
+ : pcie->pcie_data->cfgrd1) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
+bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0\
+ : pcie->pcie_data->cfgwr1) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -72,11 +79,30 @@
struct altera_pcie {
struct platform_device *pdev;
void __iomem*cra_base; /* DT Cra */
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_data {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+ int size, u32 value);
+ bool sxx_flag; /* Stratix xx */
+ u32 cap_offset; /* Capabilities register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -101,6 +127,13 @@ static bool altera_pcie_link_up(struct altera_pcie *pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+/* Instead of LTSSM state we use the link capabilities information */
+static bool sxx_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+ return !!(readw(SXX_RP_CFG_ADDR(pcie, pcie->pcie_data->cap_offset +
PCI_EXP_LNKSTA))
+ & PCI_EXP_LNKSTA_DLLLA);
+}
+
/*
* Altera PCIe
[PATCH 2/2] Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan --- .../devicetree/bindings/pci/altera-pcie.txt|4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) mode change 100644 => 100755 Documentation/devicetree/bindings/pci/altera-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt old mode 100644 new mode 100755 index 6c396f1..816b244 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 1.7.1
[PATCH 0/2] Add StratixXX PCIe Rootport support
Add PCIe rootport support for StratixXX device family and also update device tree binding documentation. Ley Foon Tan (2): pci: altera: Add StratixXX PCIe support Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt|4 +- drivers/pci/controller/Kconfig |2 +- drivers/pci/controller/pcie-altera.c | 228 ++-- 3 files changed, 212 insertions(+), 22 deletions(-) mode change 100644 => 100755 Documentation/devicetree/bindings/pci/altera-pcie.txt mode change 100644 => 100755 drivers/pci/controller/Kconfig
Re: [PATCH] nios2: remove redundant 'default n' from Kconfig-s
On Wed, 2018-10-10 at 17:00 +0200, Bartlomiej Zolnierkiewicz wrote:
> 'default n' is the default value for any bool or tristate Kconfig
> setting so there is no need to write it explicitly.
>
> Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
> is not set' for visible symbols") the Kconfig behavior is the same
> regardless of 'default n' being present or not:
>
> ...
> One side effect of (and the main motivation for) this change is
> making
> the following two definitions behave exactly the same:
>
> config FOO
> bool
>
> config FOO
> bool
> default n
>
> With this change, neither of these will generate a
> '# CONFIG_FOO is not set' line (assuming FOO isn't
> selected/implied).
> That might make it clearer to people that a bare 'default n' is
> redundant.
> ...
>
> Signed-off-by: Bartlomiej Zolnierkiewicz
Acked-by: Ley Foon Tan
> ---
> arch/nios2/Kconfig |1 -
> arch/nios2/platform/Kconfig.platform |9 -
> 2 files changed, 10 deletions(-)
>
> Index: b/arch/nios2/Kconfig
> ===
> --- a/arch/nios2/Kconfig2018-10-09 15:58:36.543122877 +0200
> +++ b/arch/nios2/Kconfig2018-10-10 16:57:50.411927641 +0200
> @@ -126,7 +126,6 @@ config NIOS2_CMDLINE_IGNORE_DTB
>
> config NIOS2_PASS_CMDLINE
> bool "Passed kernel command line from u-boot"
> - default n
> help
> Use bootargs env variable from u-boot for kernel command
> line.
> will override "Default kernel command string".
> Index: b/arch/nios2/platform/Kconfig.platform
> ===
> --- a/arch/nios2/platform/Kconfig.platform 2018-09-03
> 18:11:12.057792442 +0200
> +++ b/arch/nios2/platform/Kconfig.platform 2018-10-10
> 16:58:37.951928838 +0200
> @@ -17,7 +17,6 @@ comment "Device tree"
>
> config NIOS2_DTB_AT_PHYS_ADDR
> bool "DTB at physical address"
> - default n
> help
> When enabled you can select a physical address to load the
> dtb from.
> Normally this address is passed by a bootloader such as u-
> boot but
> @@ -37,7 +36,6 @@ config NIOS2_DTB_PHYS_ADDR
>
> config NIOS2_DTB_SOURCE_BOOL
> bool "Compile and link device tree into kernel image"
> - default n
> help
> This allows you to specify a dts (device tree source) file
> which will be compiled and linked into the kernel image.
> @@ -62,21 +60,18 @@ config NIOS2_ARCH_REVISION
>
> config NIOS2_HW_MUL_SUPPORT
> bool "Enable MUL instruction"
> - default n
> help
> Set to true if you configured the Nios II to include the
> MUL
> instruction. This will enable the -mhw-mul compiler flag.
>
> config NIOS2_HW_MULX_SUPPORT
> bool "Enable MULX instruction"
> - default n
> help
> Set to true if you configured the Nios II to include the
> MULX
> instruction. Enables the -mhw-mulx compiler flag.
>
> config NIOS2_HW_DIV_SUPPORT
> bool "Enable DIV instruction"
> - default n
> help
> Set to true if you configured the Nios II to include the
> DIV
> instruction. Enables the -mhw-div compiler flag.
> @@ -84,7 +79,6 @@ config NIOS2_HW_DIV_SUPPORT
> config NIOS2_BMX_SUPPORT
> bool "Enable BMX instructions"
> depends on NIOS2_ARCH_REVISION = 2
> - default n
> help
> Set to true if you configured the Nios II R2 to include
> the BMX Bit Manipulation Extension instructions. Enables
> @@ -93,7 +87,6 @@ config NIOS2_BMX_SUPPORT
> config NIOS2_CDX_SUPPORT
> bool "Enable CDX instructions"
> depends on NIOS2_ARCH_REVISION = 2
> - default n
> help
> Set to true if you configured the Nios II R2 to include
> the CDX Bit Manipulation Extension instructions. Enables
> @@ -101,13 +94,11 @@ config NIOS2_CDX_SUPPORT
>
> config NIOS2_FPU_SUPPORT
> bool "Custom floating point instr support"
> - default n
> help
> Enables the -mcustom-fpu-cfg=60-1 compiler flag.
>
> config NIOS2_CI_SWAB_SUPPORT
> bool "Byteswap custom instruction"
> - default n
> help
> Use the byteswap (en
Re: [PATCH] nios2: ksyms: Add missing symbol exports
On Sun, 2018-10-07 at 07:53 -0700, Guenter Roeck wrote:
> Building nios2:allmodconfig fails as follows (each symbol is only
> listed
> once).
>
> ERROR: "__ashldi3" [drivers/md/dm-writecache.ko] undefined!
> ERROR: "__ashrdi3" [fs/xfs/xfs.ko] undefined!
> ERROR: "__ucmpdi2" [drivers/media/i2c/adv7842.ko] undefined!
> ERROR: "__lshrdi3" [drivers/md/dm-zoned.ko] undefined!
> ERROR: "flush_icache_range" [drivers/misc/lkdtm/lkdtm.ko] undefined!
> ERROR: "empty_zero_page" [drivers/md/dm-mod.ko] undefined!
>
> The problem is seen with gcc 7.3.0.
>
> Export the missing symbols.
>
> Fixes: 2fc8483fdcde ("nios2: Build infrastructure")
> Signed-off-by: Guenter Roeck
Acked-by: Ley Foon Tan
> ---
> arch/nios2/kernel/nios2_ksyms.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/nios2/kernel/nios2_ksyms.c
> b/arch/nios2/kernel/nios2_ksyms.c
> index bf2f55d10a4d..4e704046a150 100644
> --- a/arch/nios2/kernel/nios2_ksyms.c
> +++ b/arch/nios2/kernel/nios2_ksyms.c
> @@ -9,12 +9,20 @@
> #include
> #include
>
> +#include
> +#include
> +
> /* string functions */
>
> EXPORT_SYMBOL(memcpy);
> EXPORT_SYMBOL(memset);
> EXPORT_SYMBOL(memmove);
>
> +/* memory management */
> +
> +EXPORT_SYMBOL(empty_zero_page);
> +EXPORT_SYMBOL(flush_icache_range);
> +
> /*
> * libgcc functions - functions that are used internally by the
> * compiler... (prototypes are not correct though, but that
> @@ -31,3 +39,7 @@ DECLARE_EXPORT(__udivsi3);
> DECLARE_EXPORT(__umoddi3);
> DECLARE_EXPORT(__umodsi3);
> DECLARE_EXPORT(__muldi3);
> +DECLARE_EXPORT(__ucmpdi2);
> +DECLARE_EXPORT(__lshrdi3);
> +DECLARE_EXPORT(__ashldi3);
> +DECLARE_EXPORT(__ashrdi3);
> --
> 2.7.4
>
>
>
>
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.
Re: [PATCH v2 2/9] nios2: build .dtb files in dts directory
On Fri, 2018-09-07 at 13:09 -0500, Rob Herring wrote: > On Thu, Sep 6, 2018 at 9:21 PM Ley Foon Tan > wrote: > > > > > > On Wed, 2018-09-05 at 18:53 -0500, Rob Herring wrote: > > > > > > Align nios2 with other architectures which build the dtb files in > > > the > > > same directory as the dts files. This is also in line with most > > > other > > > build targets which are located in the same directory as the > > > source. > > > This move will help enable the 'dtbs' target which builds all the > > > dtbs > > > regardless of kernel config. > > > > > > This transition could break some scripts if they expect dtb files > > > in > > > the old location. > > > > > > Cc: Ley Foon Tan > > > Cc: nios2-...@lists.rocketboards.org > > > Signed-off-by: Rob Herring > > > --- > > > Please ack so I can take the whole series via the DT tree. > > > > > > arch/nios2/Makefile | 4 ++-- > > > arch/nios2/boot/Makefile | 4 > > > arch/nios2/boot/dts/Makefile | 1 + > > > 3 files changed, 3 insertions(+), 6 deletions(-) > > > create mode 100644 arch/nios2/boot/dts/Makefile > > > > > > diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile > > > index 8673a79dca9c..50eece1c6adb 100644 > > > --- a/arch/nios2/Makefile > > > +++ b/arch/nios2/Makefile > > > @@ -59,10 +59,10 @@ archclean: > > > $(Q)$(MAKE) $(clean)=$(nios2-boot) > > > > > > %.dtb: | scripts > > > - $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > > > + $(Q)$(MAKE) $(build)=$(nios2-boot)/dts $(nios2- > > > boot)/dts/$@ > > > > > > dtbs: > > > - $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > > > + $(Q)$(MAKE) $(build)=$(nios2-boot)/dts > > > > > > $(BOOT_TARGETS): vmlinux > > > $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > > > diff --git a/arch/nios2/boot/Makefile b/arch/nios2/boot/Makefile > > > index 2ba23a679732..007586094dde 100644 > > > --- a/arch/nios2/boot/Makefile > > > +++ b/arch/nios2/boot/Makefile > > > @@ -47,10 +47,6 @@ obj-$(CONFIG_NIOS2_DTB_SOURCE_BOOL) += > > > linked_dtb.o > > > > > > targets += $(dtb-y) > > > > > > -# Rule to build device tree blobs with make command > > > -$(obj)/%.dtb: $(src)/dts/%.dts FORCE > > > - $(call if_changed_dep,dtc) > > > - > > > $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y)) > > > > > > install: > > > diff --git a/arch/nios2/boot/dts/Makefile > > > b/arch/nios2/boot/dts/Makefile > > > new file mode 100644 > > > index ..f66554cd5c45 > > > --- /dev/null > > > +++ b/arch/nios2/boot/dts/Makefile > > > @@ -0,0 +1 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > -- > > > 2.17.1 > > > > > Hi Rob > > > > I have synced your all-dtbs branch from here: https://git.kernel.or > > g/pu > > b/scm/linux/kernel/git/robh/linux.git/log/?h=all-dtbs > > > > It shows error when compile kernel image and also when "make > > dtbs_install". > Can you fetch the branch again and try it. I fixed a few dependency > issues. > > > > > make dtbs_install > > make[1]: *** No rule to make target > > 'arch/nios2/boot/dts/arch/nios2/boot/dts/10m50_devboard.dtb', > > needed by > > 'arch/nios2/boot/dts/arch/nios2/boot/dts/10m50_devboard.dtb.S'. St > > op. > What is the value of CONFIG_NIOS2_DTB_SOURCE? As patch 3 notes, it > now > should not have any path. > > If that's a problem, I could take the basename to strip the path, but > then sub directories wouldn't work either. > > BTW, next up, I want to consolidate the config variables for built-in > dtbs. > Hi Rob CONFIG_NIOS2_DTB_SOURCE has the relative path to dts file, arch/nios2/boot/dts/arch/nios2/boot/dts/10m50_devboard.dts Change CONFIG_NIOS2_DTB_SOURCE=10m50_devboard.dtb.S fix the dtb build issue. Regards Ley Foon
Re: [PATCH v2 2/9] nios2: build .dtb files in dts directory
On Wed, 2018-09-05 at 18:53 -0500, Rob Herring wrote: > Align nios2 with other architectures which build the dtb files in the > same directory as the dts files. This is also in line with most other > build targets which are located in the same directory as the source. > This move will help enable the 'dtbs' target which builds all the > dtbs > regardless of kernel config. > > This transition could break some scripts if they expect dtb files in > the old location. > > Cc: Ley Foon Tan > Cc: nios2-...@lists.rocketboards.org > Signed-off-by: Rob Herring > --- > Please ack so I can take the whole series via the DT tree. > > arch/nios2/Makefile | 4 ++-- > arch/nios2/boot/Makefile | 4 > arch/nios2/boot/dts/Makefile | 1 + > 3 files changed, 3 insertions(+), 6 deletions(-) > create mode 100644 arch/nios2/boot/dts/Makefile > > diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile > index 8673a79dca9c..50eece1c6adb 100644 > --- a/arch/nios2/Makefile > +++ b/arch/nios2/Makefile > @@ -59,10 +59,10 @@ archclean: > $(Q)$(MAKE) $(clean)=$(nios2-boot) > > %.dtb: | scripts > - $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > + $(Q)$(MAKE) $(build)=$(nios2-boot)/dts $(nios2-boot)/dts/$@ > > dtbs: > - $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > + $(Q)$(MAKE) $(build)=$(nios2-boot)/dts > > $(BOOT_TARGETS): vmlinux > $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@ > diff --git a/arch/nios2/boot/Makefile b/arch/nios2/boot/Makefile > index 2ba23a679732..007586094dde 100644 > --- a/arch/nios2/boot/Makefile > +++ b/arch/nios2/boot/Makefile > @@ -47,10 +47,6 @@ obj-$(CONFIG_NIOS2_DTB_SOURCE_BOOL) += > linked_dtb.o > > targets += $(dtb-y) > > -# Rule to build device tree blobs with make command > -$(obj)/%.dtb: $(src)/dts/%.dts FORCE > - $(call if_changed_dep,dtc) > - > $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y)) > > install: > diff --git a/arch/nios2/boot/dts/Makefile > b/arch/nios2/boot/dts/Makefile > new file mode 100644 > index ..f66554cd5c45 > --- /dev/null > +++ b/arch/nios2/boot/dts/Makefile > @@ -0,0 +1 @@ > +# SPDX-License-Identifier: GPL-2.0 > -- > 2.17.1 > Hi Rob I have synced your all-dtbs branch from here: https://git.kernel.org/pu b/scm/linux/kernel/git/robh/linux.git/log/?h=all-dtbs It shows error when compile kernel image and also when "make dtbs_install". make dtbs_install make[1]: *** No rule to make target 'arch/nios2/boot/dts/arch/nios2/boot/dts/10m50_devboard.dtb', needed by 'arch/nios2/boot/dts/arch/nios2/boot/dts/10m50_devboard.dtb.S'. Stop. Makefile:1229: recipe for target 'dtbs' failed make: *** [dtbs] Error 2 Regards Ley Foon
[GIT PULL] arch/nios2 update for v4.19-rc2
Hi Linus There is one arch/nios2 update for v4.19-rc2. Please consider pulling. Regards Ley Foon The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3: Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.19-rc2 for you to fetch changes up to c7c09dc187f0323ad40b5b6c57a6db673a386a7f: nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions (2018-08-27 09:47:20 +0800) nios2 fix for v4.19-rc2 nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions Tobias Klauser (1): nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions arch/nios2/Kconfig.debug | 9 - 1 file changed, 9 deletions(-)
Re: [PATCH] nios2: Convert to using %pOFn instead of device_node.name
On Mon, 2018-08-27 at 20:52 -0500, Rob Herring wrote:
> In preparation to remove the node name pointer from struct
> device_node,
> convert printf users to use the %pOFn format specifier.
>
> Cc: Ley Foon Tan
> Cc: nios2-...@lists.rocketboards.org
> Signed-off-by: Rob Herring
Acked-by: Ley Foon Tan
> ---
> arch/nios2/kernel/time.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/nios2/kernel/time.c b/arch/nios2/kernel/time.c
> index ab88b6dd4679..54467d0085a1 100644
> --- a/arch/nios2/kernel/time.c
> +++ b/arch/nios2/kernel/time.c
> @@ -214,12 +214,12 @@ static int __init
> nios2_timer_get_base_and_freq(struct device_node *np,
> {
> *base = of_iomap(np, 0);
> if (!*base) {
> - pr_crit("Unable to map reg for %s\n", np->name);
> + pr_crit("Unable to map reg for %pOFn\n", np);
> return -ENXIO;
> }
>
> if (of_property_read_u32(np, "clock-frequency", freq)) {
> - pr_crit("Unable to get %s clock frequency\n", np-
> >name);
> + pr_crit("Unable to get %pOFn clock frequency\n", np);
> return -EINVAL;
> }
>
> --
> 2.17.1
>
>
>
>
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.
Re: [PATCH] nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions
On Tue, 2018-08-21 at 01:15 +0900, Masahiro Yamada wrote: > 2018-08-16 16:05 GMT+09:00 Tobias Klauser : > > > > DEBUG_STACK_USAGE is already defined in lib/Kconfig.debug > > > > Signed-off-by: Tobias Klauser > > Reviewed-by: Masahiro Yamada > Acked-by: Ley Foon Tan > > > > > --- > > arch/nios2/Kconfig.debug | 9 - > > 1 file changed, 9 deletions(-) > > > > diff --git a/arch/nios2/Kconfig.debug b/arch/nios2/Kconfig.debug > > index 7a49f0d28d14..f1da8a7b17ff 100644 > > --- a/arch/nios2/Kconfig.debug > > +++ b/arch/nios2/Kconfig.debug > > @@ -3,15 +3,6 @@ > > config TRACE_IRQFLAGS_SUPPORT > > def_bool y > > > > -config DEBUG_STACK_USAGE > > - bool "Enable stack utilization instrumentation" > > - depends on DEBUG_KERNEL > > - help > > - Enables the display of the minimum amount of free stack > > which each > > - task has ever had available in the sysrq-T and sysrq-P > > debug output. > > - > > - This option will slow down process creation somewhat. > > - > > config EARLY_PRINTK > > bool "Activate early kernel debugging" > > default y > > -- > > 2.18.0.130.g98da2f6b3e4a > > > > > > > -- > Best Regards > Masahiro Yamada > > > > Confidentiality Notice. > This message may contain information that is confidential or > otherwise protected from disclosure. If you are not the intended > recipient, you are hereby notified that any use, disclosure, > dissemination, distribution, or copying of this message, or any > attachments, is strictly prohibited. If you have received this > message in error, please advise the sender by reply e-mail, and > delete the message and any attachments. Thank you.
Re: [PATCH 2/3] nios2: use generic early_init_dt_add_memory_arch
On Wed, 2018-07-04 at 16:18 +0300, Mike Rapoport wrote:
> All we have to do is to enable memblock, the generic FDT code will
> take
> care of the rest.
>
> Signed-off-by: Mike Rapoport
> ---
> arch/nios2/Kconfig| 1 +
> arch/nios2/kernel/prom.c | 10 --
> arch/nios2/kernel/setup.c | 2 ++
> 3 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
> index 3d4ec88..5db8fa1 100644
> --- a/arch/nios2/Kconfig
> +++ b/arch/nios2/Kconfig
> @@ -19,6 +19,7 @@ config NIOS2
> select SPARSE_IRQ
> select USB_ARCH_HAS_HCD if USB_SUPPORT
> select CPU_NO_EFFICIENT_FFS
> + select HAVE_MEMBLOCK
>
> config GENERIC_CSUM
> def_bool y
> diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
> index 8d7446a..ba96a49 100644
> --- a/arch/nios2/kernel/prom.c
> +++ b/arch/nios2/kernel/prom.c
> @@ -32,16 +32,6 @@
>
> #include
>
> -void __init early_init_dt_add_memory_arch(u64 base, u64 size)
> -{
> - u64 kernel_start = (u64)virt_to_phys(_text);
> -
> - if (!memory_size &&
> - (kernel_start >= base) && (kernel_start < (base + size)))
> - memory_size = size;
> -
> -}
> -
> int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
> phys_addr_t size,
> bool nomap)
> {
> diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
> index 926a02b..0946840 100644
> --- a/arch/nios2/kernel/setup.c
> +++ b/arch/nios2/kernel/setup.c
> @@ -17,6 +17,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -147,6 +148,7 @@ void __init setup_arch(char **cmdline_p)
>
> console_verbose();
>
> + memory_size = memblock_phys_mem_size();
> memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
> memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE +
> memory_size;
>
> --
Acked-by: Ley Foon Tan
Re: [PATCH 3/3] nios2: switch to NO_BOOTMEM
On Wed, 2018-07-04 at 16:18 +0300, Mike Rapoport wrote:
> Remove bootmem bitmap initialization and replace reserve_bootmem()
> with
> memblock_reserve().
>
> Signed-off-by: Mike Rapoport
> ---
> arch/nios2/Kconfig| 2 ++
> arch/nios2/kernel/prom.c | 7 ---
> arch/nios2/kernel/setup.c | 37 +
> 3 files changed, 7 insertions(+), 39 deletions(-)
>
> diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
> index 5db8fa1..661f7f9 100644
> --- a/arch/nios2/Kconfig
> +++ b/arch/nios2/Kconfig
> @@ -20,6 +20,8 @@ config NIOS2
> select USB_ARCH_HAS_HCD if USB_SUPPORT
> select CPU_NO_EFFICIENT_FFS
> select HAVE_MEMBLOCK
> + select ARCH_DISCARD_MEMBLOCK
> + select NO_BOOTMEM
>
> config GENERIC_CSUM
> def_bool y
> diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
> index ba96a49..a6d4f75 100644
> --- a/arch/nios2/kernel/prom.c
> +++ b/arch/nios2/kernel/prom.c
> @@ -32,13 +32,6 @@
>
> #include
>
> -int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
> phys_addr_t size,
> -bool nomap)
> -{
> - reserve_bootmem(base, size, BOOTMEM_DEFAULT);
> - return 0;
> -}
> -
> void __init early_init_devtree(void *params)
> {
> __be32 *dtb = (u32 *)__dtb_start;
> diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
> index 0946840..2d0011d 100644
> --- a/arch/nios2/kernel/setup.c
> +++ b/arch/nios2/kernel/setup.c
> @@ -144,10 +144,11 @@ asmlinkage void __init nios2_boot_init(unsigned
> r4, unsigned r5, unsigned r6,
>
> void __init setup_arch(char **cmdline_p)
> {
> - int bootmap_size;
> + int dram_start;
>
> console_verbose();
>
> + dram_start = memblock_start_of_DRAM();
> memory_size = memblock_phys_mem_size();
> memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
> memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE +
> memory_size;
> @@ -165,39 +166,11 @@ void __init setup_arch(char **cmdline_p)
> max_low_pfn = PFN_DOWN(memory_end);
> max_mapnr = max_low_pfn;
>
> - /*
> -* give all the memory to the bootmap allocator, tell it to
> put the
> -* boot mem_map at the start of memory
> -*/
> - pr_debug("init_bootmem_node(?,%#lx, %#x, %#lx)\n",
> - min_low_pfn, PFN_DOWN(PHYS_OFFSET), max_low_pfn);
> - bootmap_size = init_bootmem_node(NODE_DATA(0),
> - min_low_pfn,
> PFN_DOWN(PHYS_OFFSET),
> - max_low_pfn);
> -
> - /*
> -* free the usable memory, we have to make sure we do not
> free
> -* the bootmem bitmap so we then reserve it after freeing it
> :-)
> -*/
> - pr_debug("free_bootmem(%#lx, %#lx)\n",
> - memory_start, memory_end - memory_start);
> - free_bootmem(memory_start, memory_end - memory_start);
> -
> - /*
> -* Reserve the bootmem bitmap itself as well. We do this in
> two
> -* steps (first step was init_bootmem()) because this catches
> -* the (very unlikely) case of us accidentally initializing
> the
> -* bootmem allocator with an invalid RAM area.
> -*
> -* Arguments are start, size
> -*/
> - pr_debug("reserve_bootmem(%#lx, %#x)\n", memory_start,
> bootmap_size);
> - reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
> -
> + memblock_reserve(dram_start, memory_start - dram_start);
> #ifdef CONFIG_BLK_DEV_INITRD
> if (initrd_start) {
> - reserve_bootmem(virt_to_phys((void *)initrd_start),
> - initrd_end - initrd_start,
> BOOTMEM_DEFAULT);
> + memblock_reserve(virt_to_phys((void *)initrd_start),
> + initrd_end - initrd_start);
> }
> #endif /* CONFIG_BLK_DEV_INITRD */
>
> --
> 2.7.4
Acked-by: Ley Foon Tan
Re: [PATCH v4] MAINTAINERS: Add file patterns for nios2 device tree bindings
On Fri, 2018-06-22 at 12:08 +0200, Geert Uytterhoeven wrote: > Submitters of device tree binding documentation may forget to CC > the subsystem maintainer if this is missing. > > Signed-off-by: Geert Uytterhoeven > --- > v3: > - Update for next-20180622, > > v2: > - No changes. > > Impact on "scripts/get_maintainer.pl -f > Documentation/devicetree/bindings/nios2/": > > -Rob Herring (maintainer:OPEN FIRMWARE AND > FLATTENED DEVICE TREE > BINDINGS,commit_signer:2/2=100%,authored:1/2=50%) > +Ley Foon Tan (maintainer:NIOS2 ARCHITECTURE) > +Rob Herring (maintainer:OPEN FIRMWARE AND > FLATTENED DEVICE TREE BINDINGS) > Mark Rutland (maintainer:OPEN FIRMWARE AND > FLATTENED DEVICE TREE BINDINGS) > -Mathieu Malaterre > (commit_signer:1/2=50%,authored:1/2=50%) > -Thierry Reding (commit_signer:1/2=50%) > +nios2-...@lists.rocketboards.org (moderated list:NIOS2 ARCHITECTURE) > devicet...@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED > DEVICE TREE BINDINGS) > linux-kernel@vger.kernel.org (open list) > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index baa4dc046daf9cdc..dd72b804b9b8bab3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10074,6 +10074,7 @@ M: Ley Foon Tan > L: nios2-...@lists.rocketboards.org (moderated for non- > subscribers) > T: git > git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git > S: Maintained > +F: Documentation/devicetree/bindings/nios2/ > F: arch/nios2/ > > NOHZ, DYNTICKS SUPPORT > -- > 2.17.1 > > Reviewed-by: Ley Foon Tan
Re: [PATCH v2] PCI: controller: Move PCI_DOMAINS selection to arch Kconfig
On Thu, 2018-06-21 at 22:08 -0700, Scott Branden wrote:
>
>
> On 18-06-21 09:54 AM, Lorenzo Pieralisi wrote:
> >
> >
> > On Wed, Jun 20, 2018 at 10:07:33AM +0200, Jan Kiszka wrote:
> > >
> > >
> > > On 2018-06-19 13:21, Lorenzo Pieralisi wrote:
> > > >
> > > >
> > > > Commit 51bc085d6454 ("PCI: Improve host drivers compile test
> > > > coverage")
> > > > added configuration options to allow PCI host controller
> > > > drivers to be
> > > > compile tested on all architectures.
> > > >
> > > > Some host controller drivers (eg PCIE_ALTERA) config entries
> > > > select
> > > > the PCI_DOMAINS config option to enable PCI domains management
> > > > in
> > > > the kernel. Now that host controller drivers can be compiled on
> > > > all architectures, this triggers build regressions on arches
> > > > that
> > > > do not implement the PCI_DOMAINS required API (ie
> > > > pci_domain_nr()):
> > > >
> > > > drivers/ata/pata_ali.c: In function 'ali_init_chipset':
> > > > drivers/ata/pata_ali.c:469:38: error:
> > > > implicit declaration of function 'pci_domain_nr';
> > > > did you mean
> > > > 'pci_iomap_wc'?
> > > >
> > > > Furthemore, some software configurations (ie Jailhouse) require
> > > > a
> > > > PCI_DOMAINS enabled kernel to configure multiple host
> > > > controllers
> > > > without having an explicit dependency on the ARM platform on
> > > > which
> > > > they run.
> > > >
> > > > Make PCI_DOMAINS a visible configuration option on ARM so that
> > > > software
> > > > configurations that need it can manually select it and move the
> > > > PCI_DOMAINS selection from PCI controllers configuration file
> > > > to ARM
> > > > sub-arch config entries that currently require it, fixing the
> > > > issue.
> > > >
> > > > Fixes: 51bc085d6454 ("PCI: Improve host drivers compile test
> > > > coverage")
> > > > Link: https://lkml.kernel.org/r/20180612170229.GA10141@roeck-us
> > > > .net
> > > > Reported-by: Guenter Roeck
> > > > Signed-off-by: Lorenzo Pieralisi
> > > > Cc: Scott Branden
> > > > Cc: Will Deacon
> > > > Cc: Bjorn Helgaas
> > > > Cc: Rob Herring
> > > > Cc: Russell King
> > > > Cc: Jan Kiszka
> > > > Cc: Guenter Roeck
> > > > Cc: Ley Foon Tan
> > > > ---
> > > > v1 -> v2
> > > > - Removed ARCH_VIRT PCI_DOMAINS selection
> > > > - Added PCI_DOMAINS visible config option
> > > >
> > > > v1: https://marc.info/?l=linux-pci&m=152932092612352&w=2
> > > >
> > > > arch/arm/Kconfig | 8 +++-
> > > > arch/arm/mach-bcm/Kconfig | 1 +
> > > > arch/arm/mach-socfpga/Kconfig | 1 +
> > > > drivers/pci/controller/Kconfig | 3 ---
> > > > 4 files changed, 9 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 54eeb8d00bc6..843edfd000be 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -1245,8 +1245,14 @@ config PCI
> > > > VESA. If you have PCI, say Y, otherwise N.
> > > >
> > > > config PCI_DOMAINS
> > > > - bool
> > > > + bool "Support for multiple PCI domains"
> > > > depends on PCI
> > > > + help
> > > > + Enable PCI domains kernel management. Say Y if your
> > > > machine
> > > > + has a PCI bus hierarchy that requires more than one PCI
> > > > + domain (aka segment) to be correctly managed. Say N
> > > > otherwise.
> > > > +
> > > > + If you don't know what to do here, say N.
> > > >
> > > > config PCI_DOMAINS_GENERIC
> > > > def_bool PCI_DOMAINS
> > > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-
> > > > bcm/Kconfig
> > > > index c46a728df44e..25aac6ee2ab1 100644
> > > > --- a/arch/arm/mach-bcm/Kconfig
> > > > +++ b/arch/arm/mach
[GIT PULL] arch/nios2 update for v4.17-rc1
Hi Linus Here is nios2 update for v4.17-rc1. Please consider pulling. Regards Ley Foon The following changes since commit 0adb32858b0bddf4ada5f364a84ed60b196dbcda: Linux 4.16 (2018-04-01 14:20:27 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.17-rc1 for you to fetch changes up to 3d9644ef9a0f6c3ca0c1bd2aea1d82e7ea0a7f24: nios2: Use read_persistent_clock64() instead of read_persistent_clock() (2018-04-03 00:36:55 +0800) nios2 update for v4.17-rc1 nios2: Use read_persistent_clock64() instead of read_persistent_clock() Baolin Wang (1): nios2: Use read_persistent_clock64() instead of read_persistent_clock() arch/nios2/kernel/time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Re: [PATCH v6 11/16] nios2: Switch to generic free_initrd_mem.
On Sun, 2018-04-01 at 10:59 -0400, Shea Levy wrote:
> The first patch in this series added a weakly-defined generic
> implementation, which is functionally identical to the
> architecture-specific one removed here.
>
> Series boot-tested on RISC-V (which now uses the generic
> implementation) and x86_64 (which doesn't).
>
> Signed-off-by: Shea Levy
Acked-by: Ley Foon Tan
> ---
> arch/nios2/mm/init.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/arch/nios2/mm/init.c b/arch/nios2/mm/init.c
> index c92fe4234009..3df75ff8c768 100644
> --- a/arch/nios2/mm/init.c
> +++ b/arch/nios2/mm/init.c
> @@ -82,13 +82,6 @@ void __init mmu_init(void)
> flush_tlb_all();
> }
>
> -#ifdef CONFIG_BLK_DEV_INITRD
> -void __init free_initrd_mem(unsigned long start, unsigned long end)
> -{
> - free_reserved_area((void *)start, (void *)end, -1, "initrd");
> -}
> -#endif
> -
> void __ref free_initmem(void)
> {
> free_initmem_default(-1);
> --
> 2.16.2
Re: linux-next: Signed-off-by missing for commits in the nios2 tree
On Mon, 2018-02-12 at 13:14 +1100, Stephen Rothwell wrote:
> Hi Ley,
>
> On Mon, 12 Feb 2018 09:23:49 +0800 Ley Foon Tan om> wrote:
> >
> >
> > On Mon, 2018-02-12 at 09:20 +1100, Stephen Rothwell wrote:
> > >
> > >
> > > Commits
> > >
> > > 5d13c7317998 ("nios2: dts: Remove leading 0x and 0s from
> > > bindings
> > > notation")
> > > e0691ebb33c1 ("nios2: defconfig: Cleanup from old Kconfig
> > > options")
> > >
> > > are missing a Signed-off-by from their committer.
> > There are Signed-off-by in the commits.
> >
> > Signed-off-by: Mathieu Malaterre
> > Signed-off-by: Krzysztof Kozlowski
> They are the authors of the patches, but you are the committer i.e.
> you
> are on the path form the authors to Linus, so you need to add a
> Signed-off-by tag as well. I see Linus has merged theses commits
> now,
> so there is nothing to be done for them, but in the future please add
> a
> Signed-off-by tag for anything that you commit.
>
> See section 11 of Documentation/process/submitting-patches.rst
> --
Noted. Thanks.
Regards
Ley Foon
Re: linux-next: Signed-off-by missing for commits in the nios2 tree
On Mon, 2018-02-12 at 09:20 +1100, Stephen Rothwell wrote:
> Hi Ley,
>
> Commits
>
> 5d13c7317998 ("nios2: dts: Remove leading 0x and 0s from bindings
> notation")
> e0691ebb33c1 ("nios2: defconfig: Cleanup from old Kconfig options")
>
> are missing a Signed-off-by from their committer.
>
> --
There are Signed-off-by in the commits.
Signed-off-by: Mathieu Malaterre
Signed-off-by: Krzysztof Kozlowski
Regards
Ley Foon
[GIT PULL] arch/nios2 update for v4.16-rc1
Hi Linus Here is nios2 update for v4.16-rc1. Please consider pulling. Regards Ley Foon The following changes since commit d8a5b80568a9cb66810e75b182018e9edb68e8ff: Linux 4.15 (2018-01-28 13:20:33 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.16-rc1 for you to fetch changes up to e0691ebb33c12084ef11b6b59228c004e19f59c8: nios2: defconfig: Cleanup from old Kconfig options (2018-02-11 23:04:53 +0800) nios2 update for v4.16-rc1 nios2: defconfig: Cleanup from old Kconfig options nios2: dts: Remove leading 0x and 0s from bindings notation Krzysztof Kozlowski (1): nios2: defconfig: Cleanup from old Kconfig options Mathieu Malaterre (1): nios2: dts: Remove leading 0x and 0s from bindings notation arch/nios2/boot/dts/3c120_devboard.dts | 16 arch/nios2/configs/10m50_defconfig | 1 - arch/nios2/configs/3c120_defconfig | 1 - 3 files changed, 8 insertions(+), 10 deletions(-)
Re: [PATCH 10/11] nios2: kconfig: Remove blank help text
On Wed, 2018-01-31 at 10:34 +0100, Ulf Magnusson wrote: > Blank help texts are probably either a typo, a Kconfig > misunderstanding, > or some kind of half-committing to adding a help text (in which case > a > TODO comment would be clearer, if the help text really can't be added > right away). > > Best to remove them, IMO. > > Signed-off-by: Ulf Magnusson > --- > arch/nios2/Kconfig | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig > index 60fae03dac79..3d4ec88f1db1 100644 > --- a/arch/nios2/Kconfig > +++ b/arch/nios2/Kconfig > @@ -152,7 +152,6 @@ menu "Advanced setup" > > config ADVANCED_OPTIONS > bool "Prompt for advanced kernel configuration options" > - help > > comment "Default settings for advanced configuration options are > used" > depends on !ADVANCED_OPTIONS > -- > 2.14.1 > Acked-by: Ley Foon Tan
Re: [PATCH] PCI: altera: Fix bool initialization in tlp_read_packet
On Fri, 2018-01-19 at 21:26 -0600, Gustavo A. R. Silva wrote:
> Bool initializations should use true and false.
>
> This issue was detected with the help of Coccinelle.
>
> Fixes: eaa6111b70a7 ("PCI: altera: Add Altera PCIe host controller
> driver")
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/pci/host/pcie-altera.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-
> altera.c
> index 5cc4f59..f9ee090 100644
> --- a/drivers/pci/host/pcie-altera.c
> +++ b/drivers/pci/host/pcie-altera.c
> @@ -156,7 +156,7 @@ static bool altera_pcie_valid_device(struct
> altera_pcie *pcie,
> static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
> {
> int i;
> - bool sop = 0;
> + bool sop = false;
> u32 ctrl;
> u32 reg0, reg1;
> u32 comp_status = 1;
> --
> 2.7.4
Acked-by: Ley Foon Tan
[GIT PULL] arch/nios2 update for v4.14-rc1
Hi Linus Here is nios2 update for v4.14-rc1. Please consider pulling. Regards Ley Foon The following changes since commit 569dbb88e80deb68974ef6fdd6a13edb9d686261: Linux 4.13 (2017-09-03 13:56:17 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.14-rc1 for you to fetch changes up to 65d1e3ddeae117f6a224535e10a09145f0f96508: nios2: time: Read timer in get_cycles only if initialized (2017-09-15 20:30:58 +0800) nios2 update for v4.14-rc1 nios2: time: Read timer in get_cycles only if initialized nios2: add earlycon support to 3c120 devboard DTS Guenter Roeck (1): nios2: time: Read timer in get_cycles only if initialized Tobias Klauser (1): nios2: add earlycon support to 3c120 devboard DTS arch/nios2/boot/dts/3c120_devboard.dts | 3 ++- arch/nios2/kernel/time.c | 5 - 2 files changed, 6 insertions(+), 2 deletions(-)
[GIT PULL] arch/nios2 update for v4.12
Hi Linus Here is nios2 update for v4.12. This including nios2 fixes/enhancements and adding nios2 R2 support. Regards Ley Foon The following changes since commit 13e0988140374123bead1dd27c287354cb95108e: docs: complete bumping minimal GNU Make version to 3.81 (2017-05-06 18:49:09 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.12-rc1 for you to fetch changes up to e118c3fec9c0d8d2a96462c4c035305dc952e402: nios2: remove custom early console implementation (2017-05-11 17:44:21 +0800) nios2 update for v4.12-rc1 nios2: remove custom early console implementation nios2: use generic strncpy_from_user() and strnlen_user() nios2: Add CDX support nios2: Add BMX support nios2: Add NIOS2_ARCH_REVISION to select between R1 and R2 nios2: implement flush_dcache_mmap_lock/unlock nios2: enable earlycon support nios2: constify irq_domain_ops nios2: remove wrapper header for cmpxchg.h nios2: add .gitignore entries for auto-generated files Julien Beraud (1): nios2: implement flush_dcache_mmap_lock/unlock Ley Foon Tan (1): nios2: use generic strncpy_from_user() and strnlen_user() Marek Vasut (3): nios2: Add NIOS2_ARCH_REVISION to select between R1 and R2 nios2: Add BMX support nios2: Add CDX support Tobias Klauser (5): nios2: add .gitignore entries for auto-generated files nios2: remove wrapper header for cmpxchg.h nios2: constify irq_domain_ops nios2: enable earlycon support nios2: remove custom early console implementation arch/nios2/Kconfig | 2 + arch/nios2/Kconfig.debug | 1 - arch/nios2/Makefile| 5 ++ arch/nios2/boot/.gitignore | 2 + arch/nios2/boot/dts/10m50_devboard.dts | 3 +- arch/nios2/include/asm/Kbuild | 1 + arch/nios2/include/asm/cacheflush.h| 6 +- arch/nios2/include/asm/cmpxchg.h | 14 arch/nios2/include/asm/cpuinfo.h | 2 + arch/nios2/include/asm/prom.h | 22 -- arch/nios2/include/asm/setup.h | 2 - arch/nios2/include/asm/uaccess.h | 7 +- arch/nios2/kernel/.gitignore | 1 + arch/nios2/kernel/Makefile | 1 - arch/nios2/kernel/cpuinfo.c| 18 - arch/nios2/kernel/early_printk.c | 118 - arch/nios2/kernel/irq.c| 2 +- arch/nios2/kernel/prom.c | 49 -- arch/nios2/kernel/setup.c | 6 +- arch/nios2/mm/uaccess.c| 33 - arch/nios2/platform/Kconfig.platform | 26 21 files changed, 69 insertions(+), 252 deletions(-) create mode 100644 arch/nios2/boot/.gitignore delete mode 100644 arch/nios2/include/asm/cmpxchg.h delete mode 100644 arch/nios2/include/asm/prom.h create mode 100644 arch/nios2/kernel/.gitignore delete mode 100644 arch/nios2/kernel/early_printk.c
Re: [PATCH 1/1] nios2: implement flush_dcache_mmap_lock/unlock
On Mon, 2017-04-03 at 13:11 +0200, Julien Beraud wrote:
> Use spin_lock/unlock_irq instead of doing nothing. This fixes
> corruptions
> of the vma_interval_tree causing the kernel to be stuck in an
> infinite loop in vma_interval_tree_foreach.
>
> Signed-off-by: Julien Beraud
> ---
> arch/nios2/include/asm/cacheflush.h | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/nios2/include/asm/cacheflush.h
> b/arch/nios2/include/asm/cacheflush.h
> index 52abba973dc2..55e383c173f7 100644
> --- a/arch/nios2/include/asm/cacheflush.h
> +++ b/arch/nios2/include/asm/cacheflush.h
> @@ -46,7 +46,9 @@ extern void copy_from_user_page(struct
> vm_area_struct *vma, struct page *page,
> extern void flush_dcache_range(unsigned long start, unsigned long
> end);
> extern void invalidate_dcache_range(unsigned long start, unsigned
> long end);
>
> -#define flush_dcache_mmap_lock(mapping)do { } while
> (0)
> -#define flush_dcache_mmap_unlock(mapping) do { } while (0)
> +#define flush_dcache_mmap_lock(mapping) \
> + spin_lock_irq(&(mapping)->tree_lock)
> +#define flush_dcache_mmap_unlock(mapping) \
> + spin_unlock_irq(&(mapping)->tree_lock)
>
> #endif /* _ASM_NIOS2_CACHEFLUSH_H */
> --
> 2.11.0
>
Acked-by: Ley Foon Tan
Regards
Ley Foon
[GIT PULL] arch/nios2 fix for v4.11
Hi Linus There is one arch/nios2 fix for v4.11. Please consider pulling. Regards Ley Foon The following changes since commit a71c9a1c779f2499fb2afc0553e543f18aff6edf: Linux 4.11-rc5 (2017-04-02 17:23:54 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.11-fix for you to fetch changes up to 921d701e6f31e1ffaca3560416af1aa04edb4c4f: nios2: reserve boot memory for device tree (2017-04-02 20:13:57 -0700) nios2 fix for v4.11 - nios2: reserve boot memory for device tree Tobias Klauser (1): nios2: reserve boot memory for device tree arch/nios2/kernel/prom.c | 7 +++ arch/nios2/kernel/setup.c | 3 +++ 2 files changed, 10 insertions(+)
Re: [PATCH] nios2: reserve boot memory for device tree
On Fri, 2017-03-31 at 11:40 +0200, Tobias Klauser wrote:
> Make sure to reserve the boot memory for the flattened device tree.
> Otherwise it might get overwritten, e.g. when initial_boot_params is
> copied, leading to a corrupted FDT and a boot hang/crash:
>
> bootconsole [early0] enabled
> Early console on uart16650 initialized at 0xf8001600
> OF: fdt: Error -11 processing FDT
> Kernel panic - not syncing: setup_cpuinfo: No CPU found in
> devicetree!
>
> ---[ end Kernel panic - not syncing: setup_cpuinfo: No CPU found in
> devicetree!
>
> Guenter Roeck says:
>
> >
> > I think I found the problem. In unflatten_and_copy_device_tree(),
> > with added
> > debug information:
> >
> > OF: fdt: initial_boot_params=c861e400, dt=c861f000 size=28874
> > (0x70ca)
> >
> > ... and then initial_boot_params is copied to dt, which results in
> > corrupted
> > fdt since the memory overlaps. Looks like the initial_boot_params
> > memory
> > is not reserved and (re-)allocated by
> > early_init_dt_alloc_memory_arch().
> Cc: sta...@vger.kernel.org
> Reported-by: Guenter Roeck
> Reference: http://lkml.kernel.org/r/20170226210338.GA19476@roeck-us.n
> et
> Tested-by: Guenter Roeck
> Signed-off-by: Tobias Klauser
Acked-by: Ley Foon Tan
Thanks for the fix. Will add this for 4.11.
Regards
Ley Foon
> ---
> arch/nios2/kernel/prom.c | 7 +++
> arch/nios2/kernel/setup.c | 3 +++
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
> index 367c5426157b..3901b80d4420 100644
> --- a/arch/nios2/kernel/prom.c
> +++ b/arch/nios2/kernel/prom.c
> @@ -48,6 +48,13 @@ void * __init early_init_dt_alloc_memory_arch(u64
> size, u64 align)
> return alloc_bootmem_align(size, align);
> }
>
> +int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
> phys_addr_t size,
> +bool nomap)
> +{
> + reserve_bootmem(base, size, BOOTMEM_DEFAULT);
> + return 0;
> +}
> +
> void __init early_init_devtree(void *params)
> {
> __be32 *dtb = (u32 *)__dtb_start;
> diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
> index 6e57ffa5db27..6044d9be28b4 100644
> --- a/arch/nios2/kernel/setup.c
> +++ b/arch/nios2/kernel/setup.c
> @@ -201,6 +201,9 @@ void __init setup_arch(char **cmdline_p)
> }
> #endif /* CONFIG_BLK_DEV_INITRD */
>
> + early_init_fdt_reserve_self();
> + early_init_fdt_scan_reserved_mem();
> +
> unflatten_and_copy_device_tree();
>
> setup_cpuinfo();
> --
> 2.12.2.399.g034667a45805
>
>
>
>
>
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.
Re: [PATCH] PCI: altera: Fix TLP_CFG_DW0 for TLP write
On Tue, Feb 28, 2017 at 6:31 PM, Ley Foon Tan wrote:
> Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
> and this cause writing to configuration space will fail. This patch
> fix it by using correct FMTTYPE for write operation.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/pci/host/pcie-altera.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
> index 0c15402..68c839f 100644
> --- a/drivers/pci/host/pcie-altera.c
> +++ b/drivers/pci/host/pcie-altera.c
> @@ -57,10 +57,14 @@
> #define TLP_WRITE_TAG 0x10
> #define RP_DEVFN 0
> #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
> -#define TLP_CFG_DW0(pcie, bus) \
> +#define TLP_CFGRD_DW0(pcie, bus) \
> bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
> : TLP_FMTTYPE_CFGRD1) << 24) | \
> TLP_PAYLOAD_SIZE)
> +#define TLP_CFGWR_DW0(pcie, bus) \
> +bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
> + : TLP_FMTTYPE_CFGWR1) << 24) | \
> + TLP_PAYLOAD_SIZE)
> #define TLP_CFG_DW1(pcie, tag, be) \
> (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
> #define TLP_CFG_DW2(bus, devfn, offset)\
> @@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie,
> u8 bus, u32 devfn,
> {
> u32 headers[TLP_HDR_SIZE];
>
> - headers[0] = TLP_CFG_DW0(pcie, bus);
> + headers[0] = TLP_CFGRD_DW0(pcie, bus);
> headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
> headers[2] = TLP_CFG_DW2(bus, devfn, where);
>
> @@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie,
> u8 bus, u32 devfn,
> u32 headers[TLP_HDR_SIZE];
> int ret;
>
> - headers[0] = TLP_CFG_DW0(pcie, bus);
> + headers[0] = TLP_CFGWR_DW0(pcie, bus);
> headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
> headers[2] = TLP_CFG_DW2(bus, devfn, where);
Resend the patch by adding sta...@vger.kernel.org to cc list.
Please ignore the previous one.
Thanks.
Regards
Ley Foon
[PATCH] PCI: altera: Fix TLP_CFG_DW0 for TLP write
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
Cc: sta...@vger.kernel.org
---
drivers/pci/host/pcie-altera.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 0c15402..68c839f 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -57,10 +57,14 @@
#define TLP_WRITE_TAG 0x10
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
-#define TLP_CFG_DW0(pcie, bus) \
+#define TLP_CFGRD_DW0(pcie, bus) \
bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
: TLP_FMTTYPE_CFGRD1) << 24) | \
TLP_PAYLOAD_SIZE)
+#define TLP_CFGWR_DW0(pcie, bus) \
+bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
+ : TLP_FMTTYPE_CFGWR1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
@@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8
bus, u32 devfn,
{
u32 headers[TLP_HDR_SIZE];
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGRD_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
@@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8
bus, u32 devfn,
u32 headers[TLP_HDR_SIZE];
int ret;
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGWR_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
--
1.8.2.3
Re: [PATCH] PCI: altera: Fix TLP_CFG_DW0 for TLP write
On Tue, Feb 28, 2017 at 6:37 PM, Ley Foon Tan wrote:
> Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
> and this cause writing to configuration space will fail. This patch
> fix it by using correct FMTTYPE for write operation.
>
> Signed-off-by: Ley Foon Tan
> Cc: sta...@vger.kernel.org
> ---
> drivers/pci/host/pcie-altera.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
> index 0c15402..68c839f 100644
> --- a/drivers/pci/host/pcie-altera.c
> +++ b/drivers/pci/host/pcie-altera.c
> @@ -57,10 +57,14 @@
> #define TLP_WRITE_TAG 0x10
> #define RP_DEVFN 0
> #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
> -#define TLP_CFG_DW0(pcie, bus) \
> +#define TLP_CFGRD_DW0(pcie, bus) \
> bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
> : TLP_FMTTYPE_CFGRD1) << 24) | \
> TLP_PAYLOAD_SIZE)
> +#define TLP_CFGWR_DW0(pcie, bus) \
> +bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
> + : TLP_FMTTYPE_CFGWR1) << 24) | \
> + TLP_PAYLOAD_SIZE)
> #define TLP_CFG_DW1(pcie, tag, be) \
> (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
> #define TLP_CFG_DW2(bus, devfn, offset)\
> @@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie,
> u8 bus, u32 devfn,
> {
> u32 headers[TLP_HDR_SIZE];
>
> - headers[0] = TLP_CFG_DW0(pcie, bus);
> + headers[0] = TLP_CFGRD_DW0(pcie, bus);
> headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
> headers[2] = TLP_CFG_DW2(bus, devfn, where);
>
> @@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie,
> u8 bus, u32 devfn,
> u32 headers[TLP_HDR_SIZE];
> int ret;
>
> - headers[0] = TLP_CFG_DW0(pcie, bus);
> + headers[0] = TLP_CFGWR_DW0(pcie, bus);
> headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
> headers[2] = TLP_CFG_DW2(bus, devfn, where);
>
> --
> 1.8.2.3
>
Please use this patch instead. Add cc:sta...@vger.kernel.org to the
patch itself instead of cc in email list.
Regards
Ley Foon
[PATCH] PCI: altera: Fix TLP_CFG_DW0 for TLP write
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 0c15402..68c839f 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -57,10 +57,14 @@
#define TLP_WRITE_TAG 0x10
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
-#define TLP_CFG_DW0(pcie, bus) \
+#define TLP_CFGRD_DW0(pcie, bus) \
bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
: TLP_FMTTYPE_CFGRD1) << 24) | \
TLP_PAYLOAD_SIZE)
+#define TLP_CFGWR_DW0(pcie, bus) \
+bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
+ : TLP_FMTTYPE_CFGWR1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
@@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8
bus, u32 devfn,
{
u32 headers[TLP_HDR_SIZE];
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGRD_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
@@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8
bus, u32 devfn,
u32 headers[TLP_HDR_SIZE];
int ret;
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGWR_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
--
1.8.2.3
[PATCH] PCI: altera: Fix TLP_CFG_DW0 for TLP write
Commit eb5767122feba1 used the TLP_FMTTYPE_CFGRD* for TLP write operation
and this cause writing to configuration space will fail. This patch
fix it by using correct FMTTYPE for write operation.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 0c15402..68c839f 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -57,10 +57,14 @@
#define TLP_WRITE_TAG 0x10
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
-#define TLP_CFG_DW0(pcie, bus) \
+#define TLP_CFGRD_DW0(pcie, bus) \
bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
: TLP_FMTTYPE_CFGRD1) << 24) | \
TLP_PAYLOAD_SIZE)
+#define TLP_CFGWR_DW0(pcie, bus) \
+bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
+ : TLP_FMTTYPE_CFGWR1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
@@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8
bus, u32 devfn,
{
u32 headers[TLP_HDR_SIZE];
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGRD_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
@@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8
bus, u32 devfn,
u32 headers[TLP_HDR_SIZE];
int ret;
- headers[0] = TLP_CFG_DW0(pcie, bus);
+ headers[0] = TLP_CFGWR_DW0(pcie, bus);
headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
headers[2] = TLP_CFG_DW2(bus, devfn, where);
--
1.8.2.3
[GIT PULL] arch/nios2 update for 4.10
Hi Linus Here is the nios2 update for v4.10. Please consider pulling. Regards Ley Foon The following changes since commit 69973b830859bc6529a7a0468ba0d80ee5117826: Linux 4.9 (2016-12-11 11:17:54 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git tags/nios2-v4.10-rc1 for you to fetch changes up to 744606c76c4a3a73eb34d21f265013426426c4b5: nios2: add screen_info (2016-12-13 17:13:17 +0800) nios2 update for v4.10-rc1 - add screen_info - Convert pfn_valid to static inline - Extend !__ASSEMBLY__ section in asm/page.h Ley Foon Tan (1): nios2: add screen_info Tobias Klauser (2): nios2: Extend !__ASSEMBLY__ section in asm/page.h nios2: Convert pfn_valid to static inline arch/nios2/include/asm/page.h | 15 +++ arch/nios2/kernel/setup.c | 5 + 2 files changed, 16 insertions(+), 4 deletions(-)
Re: [PATCH] PCI: altera: use builtin_platform_driver
On Rab, 2016-11-23 at 14:52 +, Geliang Tang wrote:
> Use builtin_platform_driver() helper to simplify the code.
>
> Signed-off-by: Geliang Tang
Acked-by: Ley Foon Tan
> ---
> drivers/pci/host/pcie-altera.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-
> altera.c
> index b0ac4df..eefcb38 100644
> --- a/drivers/pci/host/pcie-altera.c
> +++ b/drivers/pci/host/pcie-altera.c
> @@ -641,8 +641,4 @@ static struct platform_driver altera_pcie_driver
> = {
> },
> };
>
> -static int altera_pcie_init(void)
> -{
> - return platform_driver_register(&altera_pcie_driver);
> -}
> -device_initcall(altera_pcie_init);
> +builtin_platform_driver(altera_pcie_driver);
> --
> 2.9.3
>
Re: [PATCH] asm-generic: Drop getrlimit and setrlimit syscalls from default list
On Mon, Oct 24, 2016 at 5:09 PM, James Hogan wrote: > On Sat, Oct 22, 2016 at 03:14:04PM +0300, Yury Norov wrote: >> The newer prlimit64 syscall provides all the functionality provided by >> the getrlimit and setrlimit syscalls and adds the pid of target process, >> so future architectures won't need to include getrlimit and setrlimit. >> >> Therefore drop getrlimit and setrlimit syscalls from the generic syscall >> list unless __ARCH_WANT_SET_GET_RLIMIT is defined by the architecture's >> unistd.h prior to including asm-generic/unistd.h, and adjust all >> architectures using the generic syscall list to define it so that no >> in-tree architectures are affected. >> >> Cc: Vineet Gupta >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Mark Salter >> Cc: Aurelien Jacquiot >> Cc: Yoshinori Sato >> Cc: Richard Kuo >> Cc: James Hogan >> Cc: Ley Foon Tan >> Cc: Jonas Bonn >> Cc: Chen Liqin >> Cc: Lennox Wu >> Cc: Chris Metcalf >> Cc: Guan Xuetao >> Cc: Arnd Bergmann >> Cc: Andrew Pinski >> Cc: linux-snps-...@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Cc: linux-arm-ker...@lists.infradead.org >> Cc: linux-c6x-...@linux-c6x.org >> Cc: uclinux-h8-de...@lists.sourceforge.jp >> Cc: linux-hexa...@vger.kernel.org >> Cc: linux-me...@vger.kernel.org >> Cc: nios2-...@lists.rocketboards.org >> Cc: linux-a...@vger.kernel.or >> Signed-off-by: Yury Norov >> >> --- >> arch/arc/include/uapi/asm/unistd.h | 1 + >> arch/arm64/include/uapi/asm/unistd.h | 1 + >> arch/c6x/include/uapi/asm/unistd.h | 1 + >> arch/h8300/include/uapi/asm/unistd.h | 1 + >> arch/hexagon/include/uapi/asm/unistd.h | 1 + >> arch/metag/include/uapi/asm/unistd.h | 1 + > > Acked-by: James Hogan [metag] > > Cheers > James > >> arch/nios2/include/uapi/asm/unistd.h | 1 + Acked-by: Ley Foon Tan [nios2] >> arch/openrisc/include/uapi/asm/unistd.h | 1 + >> arch/score/include/uapi/asm/unistd.h | 1 + >> arch/tile/include/uapi/asm/unistd.h | 1 + >> arch/unicore32/include/uapi/asm/unistd.h | 1 + >> include/uapi/asm-generic/unistd.h| 5 + >> 12 files changed, 16 insertions(+) >> >> diff --git a/arch/arc/include/uapi/asm/unistd.h >> b/arch/arc/include/uapi/asm/unistd.h >> index 41fa2ec..928546d 100644 >> --- a/arch/arc/include/uapi/asm/unistd.h >> +++ b/arch/arc/include/uapi/asm/unistd.h >> @@ -16,6 +16,7 @@ >> #define _UAPI_ASM_ARC_UNISTD_H >> >> #define __ARCH_WANT_RENAMEAT >> +#define __ARCH_WANT_SET_GET_RLIMIT >> #define __ARCH_WANT_SYS_EXECVE >> #define __ARCH_WANT_SYS_CLONE >> #define __ARCH_WANT_SYS_VFORK >> diff --git a/arch/arm64/include/uapi/asm/unistd.h >> b/arch/arm64/include/uapi/asm/unistd.h >> index 043d17a..48355a6 100644 >> --- a/arch/arm64/include/uapi/asm/unistd.h >> +++ b/arch/arm64/include/uapi/asm/unistd.h >> @@ -15,5 +15,6 @@ >> */ >> >> #define __ARCH_WANT_RENAMEAT >> +#define __ARCH_WANT_SET_GET_RLIMIT >> >> #include >> diff --git a/arch/c6x/include/uapi/asm/unistd.h >> b/arch/c6x/include/uapi/asm/unistd.h >> index 12d73d9..f676231 100644 >> --- a/arch/c6x/include/uapi/asm/unistd.h >> +++ b/arch/c6x/include/uapi/asm/unistd.h >> @@ -15,6 +15,7 @@ >> */ >> >> #define __ARCH_WANT_RENAMEAT >> +#define __ARCH_WANT_SET_GET_RLIMIT >> #define __ARCH_WANT_SYS_CLONE >> >> /* Use the standard ABI for syscalls. */ >> diff --git a/arch/h8300/include/uapi/asm/unistd.h >> b/arch/h8300/include/uapi/asm/unistd.h >> index 7dd20ef..2f98394 100644 >> --- a/arch/h8300/include/uapi/asm/unistd.h >> +++ b/arch/h8300/include/uapi/asm/unistd.h >> @@ -1,5 +1,6 @@ >> #define __ARCH_NOMMU >> >> #define __ARCH_WANT_RENAMEAT >> +#define __ARCH_WANT_SET_GET_RLIMIT >> >> #include >> diff --git a/arch/hexagon/include/uapi/asm/unistd.h >> b/arch/hexagon/include/uapi/asm/unistd.h >> index 2151760..52d585c 100644 >> --- a/arch/hexagon/include/uapi/asm/unistd.h >> +++ b/arch/hexagon/include/uapi/asm/unistd.h >> @@ -28,6 +28,7 @@ >> >> #define sys_mmap2 sys_mmap_pgoff >> #define __ARCH_WANT_RENAMEAT >> +#define __ARCH_WANT_SET_GET_RLIMIT >> #define __ARCH_WANT_SYS_EXECVE >> #define __ARCH_WANT_SYS_CLONE >> #define __ARCH_WANT_SYS_VFORK >> diff --git a/arch/metag/include/uapi/asm/unistd.h >> b/arch/metag/include/uapi/asm/unistd.h >>
Re: [PATCH 26/28] nios2: fix timer initcall return value
On Tue, Oct 18, 2016 at 6:16 AM, Arnd Bergmann wrote: > When called more than twice, the nios2_time_init() function > return an uninitialized value, as detected by gcc -Wmaybe-uninitialized > > arch/nios2/kernel/time.c: warning: 'ret' may be used uninitialized in this > function > > This makes it return '0' here, matching the comment above the > function. > > Signed-off-by: Arnd Bergmann > --- > arch/nios2/kernel/time.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/nios2/kernel/time.c b/arch/nios2/kernel/time.c > index d9563dd..746bf5c 100644 > --- a/arch/nios2/kernel/time.c > +++ b/arch/nios2/kernel/time.c > @@ -324,6 +324,7 @@ static int __init nios2_time_init(struct device_node > *timer) > ret = nios2_clocksource_init(timer); > break; > default: > + ret = 0; > break; > } Acked-by: Ley Foon Tan
Re: [PATCHv2 4/4] nios2: dts: 10m50: Add tx-threshold parameter
On Fri, Sep 23, 2016 at 3:56 AM, wrote:
> From: Thor Thayer
>
> The tx-threshold parameter sets the TX FIFO low water threshold
> trigger for the Altera 16550-FIFO32 soft IP.
>
> Signed-off-by: Thor Thayer
> ---
> v2 Change from tx-loadsz to tx-threshold
> ---
> arch/nios2/boot/dts/10m50_devboard.dts |1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/nios2/boot/dts/10m50_devboard.dts
> b/arch/nios2/boot/dts/10m50_devboard.dts
> index 3e411c6..f362b22 100755
> --- a/arch/nios2/boot/dts/10m50_devboard.dts
> +++ b/arch/nios2/boot/dts/10m50_devboard.dts
> @@ -83,6 +83,7 @@
> fifo-size = <32>;
> reg-io-width = <4>;
> reg-shift = <2>;
> + tx-threshold = <16>;
> };
>
> sysid: sysid@18001528 {
Acked-by: Ley Foon Tan
Re: [PATCH v4 0/2] PCI: altera: Retrain link in rootport mode only
On Fri, Aug 26, 2016 at 9:47 AM, Ley Foon Tan wrote: > Altera PCIe IP can be configured as rootport or device and they might have > same vendor ID. It will cause the system hang issue if Altera PCIe is in > endpoint mode and work with other PCIe rootport that from other vendors. > > This series of patch rework configs accessors and move retrain function > from _FIXUP to altera_pcie_host_init(). > > History: > v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT > v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP > v4: Split patch to 2 patches > > Ley Foon Tan (2): > PCI: altera: Rework configs accessors > PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init() > > drivers/pci/host/pcie-altera.c | 215 > + > 1 file changed, 132 insertions(+), 83 deletions(-) > Hi Bjorn Do you have further comment on this patch series? Thanks. Regards Ley Foon
[PATCH v4 1/2] PCI: altera: Rework configs accessors
Rework configs accessors so a future patch can use them in _probe()
with struct altera_pcie instead of struct pci_bus.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 64 +++---
1 file changed, 41 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..34e6258 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -330,22 +330,14 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie,
u8 bus, u32 devfn,
return PCIBIOS_SUCCESSFUL;
}
-static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *value)
+static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int where, int size,
+u32 *value)
{
- struct altera_pcie *pcie = bus->sysdata;
int ret;
u32 data;
u8 byte_en;
- if (altera_pcie_hide_rc_bar(bus, devfn, where))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
- *value = 0x;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
switch (size) {
case 1:
byte_en = 1 << (where & 3);
@@ -358,7 +350,7 @@ static int altera_pcie_cfg_read(struct pci_bus *bus,
unsigned int devfn,
break;
}
- ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
+ ret = tlp_cfg_dword_read(pcie, busno, devfn,
(where & ~DWORD_MASK), byte_en, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
@@ -378,20 +370,14 @@ static int altera_pcie_cfg_read(struct pci_bus *bus,
unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
-static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
-int where, int size, u32 value)
+static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
+ unsigned int devfn, int where, int size,
+ u32 value)
{
- struct altera_pcie *pcie = bus->sysdata;
u32 data32;
u32 shift = 8 * (where & 3);
u8 byte_en;
- if (altera_pcie_hide_rc_bar(bus, devfn, where))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
switch (size) {
case 1:
data32 = (value & 0xff) << shift;
@@ -407,8 +393,40 @@ static int altera_pcie_cfg_write(struct pci_bus *bus,
unsigned int devfn,
break;
}
- return tlp_cfg_dword_write(pcie, bus->number, devfn,
- (where & ~DWORD_MASK), byte_en, data32);
+ return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
+ byte_en, data32);
+}
+
+static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *value)
+{
+ struct altera_pcie *pcie = bus->sysdata;
+
+ if (altera_pcie_hide_rc_bar(bus, devfn, where))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+ if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
+ *value = 0x;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
+value);
+}
+
+static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
+int where, int size, u32 value)
+{
+ struct altera_pcie *pcie = bus->sysdata;
+
+ if (altera_pcie_hide_rc_bar(bus, devfn, where))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+ if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
+value);
}
static struct pci_ops altera_pcie_ops = {
--
1.8.2.1
Re: [Nios2-dev] [PATCH] nios2: use of_property_read_bool
On Wed, Aug 10, 2016 at 8:27 PM, Tobias Klauser wrote: > Use of_property_read_bool instead of open-coding it as fpcu_has. Convert > the members of struct cpuinfo from u32 to bool accordingly as they are > only used as boolean anyhow. > > Signed-off-by: Tobias Klauser Acked-by: Ley Foon Tan Thanks. > --- > arch/nios2/include/asm/cpuinfo.h | 8 > arch/nios2/kernel/cpuinfo.c | 15 +-- > 2 files changed, 9 insertions(+), 14 deletions(-) >
[PATCH v4 0/2] PCI: altera: Retrain link in rootport mode only
Altera PCIe IP can be configured as rootport or device and they might have same vendor ID. It will cause the system hang issue if Altera PCIe is in endpoint mode and work with other PCIe rootport that from other vendors. This series of patch rework configs accessors and move retrain function from _FIXUP to altera_pcie_host_init(). History: v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP v4: Split patch to 2 patches Ley Foon Tan (2): PCI: altera: Rework configs accessors PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init() drivers/pci/host/pcie-altera.c | 215 + 1 file changed, 132 insertions(+), 83 deletions(-) -- 1.8.2.1
[PATCH v4 2/2] PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init()
Altera PCIe IP can be configured as rootport or device and they might have
same vendor ID. It will cause the system hang issue if Altera PCIe is in
endpoint mode and work with other PCIe rootport that from other vendors.
Move link retrain function from _FIXUP to altera_pcie_host_init().
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 151 +
1 file changed, 91 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 34e6258..4ca50a2 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -43,6 +43,7 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
+#define PCIE_CAP_OFFSET0x80
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -100,66 +101,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie
*pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
-static void altera_wait_link_retrain(struct pci_dev *dev)
-{
- u16 reg16;
- unsigned long start_jiffies;
- struct altera_pcie *pcie = dev->bus->sysdata;
-
- /* Wait for link training end. */
- start_jiffies = jiffies;
- for (;;) {
- pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_LT))
- break;
-
- if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
- dev_err(&pcie->pdev->dev, "link retrain timeout\n");
- break;
- }
- udelay(100);
- }
-
- /* Wait for link is up */
- start_jiffies = jiffies;
- for (;;) {
- if (altera_pcie_link_is_up(pcie))
- break;
-
- if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
- dev_err(&pcie->pdev->dev, "link up timeout\n");
- break;
- }
- udelay(100);
- }
-}
-
-static void altera_pcie_retrain(struct pci_dev *dev)
-{
- u16 linkcap, linkstat;
- struct altera_pcie *pcie = dev->bus->sysdata;
-
- if (!altera_pcie_link_is_up(pcie))
- return;
-
- /*
-* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
-* current speed is 2.5 GB/s.
-*/
- pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
-
- if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
- return;
-
- pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
- if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
- pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
-PCI_EXP_LNKCTL_RL);
- altera_wait_link_retrain(dev);
- }
-}
-DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-
/*
* Altera PCIe port uses BAR0 of RC's configuration space as the translation
* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
@@ -434,6 +375,90 @@ static struct pci_ops altera_pcie_ops = {
.write = altera_pcie_cfg_write,
};
+static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
+ unsigned int devfn, int offset, u16 *value)
+{
+ u32 data;
+ int ret;
+
+ ret = _altera_pcie_cfg_read(pcie, busno, devfn,
+ PCIE_CAP_OFFSET + offset, sizeof(*value),
+ &data);
+ *value = data;
+ return ret;
+}
+
+static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int offset, u16 value)
+{
+ return _altera_pcie_cfg_write(pcie, busno, devfn,
+ PCIE_CAP_OFFSET + offset, sizeof(value),
+ value);
+}
+
+static void altera_wait_link_retrain(struct altera_pcie *pcie)
+{
+ u16 reg16;
+ unsigned long start_jiffies;
+
+ /* Wait for link training end. */
+ start_jiffies = jiffies;
+ for (;;) {
+ altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
+PCI_EXP_LNKSTA, ®16);
+ if (!(reg16 & PCI_EXP_LNKSTA_LT))
+ break;
+
+ if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
+ dev_err(&pcie->pdev->dev, "link retrain timeout\n");
+ break;
+ }
+ udelay(100);
+ }
+
+ /* Wait
Re: [PATCH v3] PCI: altera: Retrain link in rootport mode only
On Thu, Aug 25, 2016 at 9:56 PM, Bjorn Helgaas wrote: > On Thu, Aug 25, 2016 at 01:59:56PM +0800, Ley Foon Tan wrote: >> Altera PCIe IP can be configured as rootport or device and they might have >> same vendor ID. It will cause the system hang issue if Altera PCIe is in >> endpoint mode and work with other PCIe rootport that from other vendors. >> Moved retrain function to before pci_scan_root_bus and removed _FIXUP. >> Add _altera_pcie_cfg_read() and _altera_pcie_cfg_write() to use struct >> altera_pcie as argument instead of struct pci_bus. > > I think this makes sense. Can you split this into two patches: > > - Rework the config accessors > - Move retrain from the quirk to altera_pcie_host_init() Okay, will resend this. Thanks. > I also want to look through the other host bridge drivers and see if > there's any consistency in naming and structure of the config accessors. > The pattern of a wrapper that takes "struct pci_bus *, unsigned int devfn, > ..." that calls an internal function that takes the driver structure > instead of the "struct pci_bus *" might be useful in other drivers as well.
[PATCH v3] PCI: altera: Retrain link in rootport mode only
Altera PCIe IP can be configured as rootport or device and they might have
same vendor ID. It will cause the system hang issue if Altera PCIe is in
endpoint mode and work with other PCIe rootport that from other vendors.
Moved retrain function to before pci_scan_root_bus and removed _FIXUP.
Add _altera_pcie_cfg_read() and _altera_pcie_cfg_write() to use struct
altera_pcie as argument instead of struct pci_bus.
Signed-off-by: Ley Foon Tan
---
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
---
drivers/pci/host/pcie-altera.c | 217 +
1 file changed, 134 insertions(+), 83 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..4ce6d86 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -43,6 +43,8 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
+#define PCIE_CAP_OFFSET0x80
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -100,66 +102,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie
*pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
-static void altera_wait_link_retrain(struct pci_dev *dev)
-{
- u16 reg16;
- unsigned long start_jiffies;
- struct altera_pcie *pcie = dev->bus->sysdata;
-
- /* Wait for link training end. */
- start_jiffies = jiffies;
- for (;;) {
- pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_LT))
- break;
-
- if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
- dev_err(&pcie->pdev->dev, "link retrain timeout\n");
- break;
- }
- udelay(100);
- }
-
- /* Wait for link is up */
- start_jiffies = jiffies;
- for (;;) {
- if (altera_pcie_link_is_up(pcie))
- break;
-
- if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
- dev_err(&pcie->pdev->dev, "link up timeout\n");
- break;
- }
- udelay(100);
- }
-}
-
-static void altera_pcie_retrain(struct pci_dev *dev)
-{
- u16 linkcap, linkstat;
- struct altera_pcie *pcie = dev->bus->sysdata;
-
- if (!altera_pcie_link_is_up(pcie))
- return;
-
- /*
-* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
-* current speed is 2.5 GB/s.
-*/
- pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
-
- if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
- return;
-
- pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
- if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
- pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
-PCI_EXP_LNKCTL_RL);
- altera_wait_link_retrain(dev);
- }
-}
-DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-
/*
* Altera PCIe port uses BAR0 of RC's configuration space as the translation
* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
@@ -330,22 +272,14 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie,
u8 bus, u32 devfn,
return PCIBIOS_SUCCESSFUL;
}
-static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *value)
+static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int where, int size,
+u32 *value)
{
- struct altera_pcie *pcie = bus->sysdata;
int ret;
u32 data;
u8 byte_en;
- if (altera_pcie_hide_rc_bar(bus, devfn, where))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
- *value = 0x;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
switch (size) {
case 1:
byte_en = 1 << (where & 3);
@@ -358,7 +292,7 @@ static int altera_pcie_cfg_read(struct pci_bus *bus,
unsigned int devfn,
break;
}
- ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
+ ret = tlp_cfg_dword_read(pcie, busno, devfn,
(where & ~DWORD_MASK), byte_en, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
Re: [PATCH v2] PCI: altera: Retrain link in rootport mode only
On Thu, Aug 25, 2016 at 1:54 AM, Bjorn Helgaas wrote: > [+cc Ray, Scott, Jon, bcm-kernel-feedback-list] > > On Wed, Aug 24, 2016 at 03:07:52PM +0800, Ley Foon Tan wrote: >> On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas wrote: >> > On Fri, Aug 19, 2016 at 04:24:38PM +0800, Ley Foon Tan wrote: >> >> Altera PCIe IP can be configured as rootport or device and they might have >> >> same vendor ID. It will cause the system hang issue if Altera PCIe is in >> >> endpoint mode and work with other PCIe rootport that from other vendors. >> >> So, add the rootport mode checking in link retrain fixup function. >> >> >> >> Signed-off-by: Ley Foon Tan >> >> --- >> >> v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT >> >> --- >> >> drivers/pci/host/pcie-altera.c | 3 +++ >> >> 1 file changed, 3 insertions(+) >> >> >> >> diff --git a/drivers/pci/host/pcie-altera.c >> >> b/drivers/pci/host/pcie-altera.c >> >> index 58eef99..33b6968 100644 >> >> --- a/drivers/pci/host/pcie-altera.c >> >> +++ b/drivers/pci/host/pcie-altera.c >> >> @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev) >> >> u16 linkcap, linkstat; >> >> struct altera_pcie *pcie = dev->bus->sysdata; >> >> >> >> + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) >> >> + return; >> >> + >> >> if (!altera_pcie_link_is_up(pcie)) >> >> return; >> > >> > Instead of making this a PCI fixup, can you make an >> > altera_pcie_host_init() function, call it from altera_pcie_probe(), >> > and do the link retrain there? Then you wouldn't need to worry about >> > whether this is a Root Port or an Endpoint, plus it would make the >> > altera driver structure more like the other drivers. >> > >> > You would call altera_pcie_host_init() before pci_scan_root_bus(), so >> > you wouldn't have a pci_dev yet, so you wouldn't be able to use >> > pcie_capability_set_word() to set the PCI_EXP_LNKCTL_RL bit. But I >> > assume there's some device-dependent way to access it using >> > cra_writel()? >> We can't use cra_write() to set PCI_EXP_LNKCTL_RL bit. > > Why not? I don't mean it has to be cra_write(), but isn't there some > way you can write that bit before we scan the root bus? It doesn't > make sense that we have to scan the bus before we can train the link. > > We want to be able to tell the PCI core "all the device-specific root > complex initialization has been done, here are the config accessors > you need, please scan for devices." I want to keep device-specific > things like this quirk directly in the driver and out of the > enumeration process. We don't have internal register bit to trigger link retrain, but need to set PCI_EXP_LNKCTL_RL bit in Link Control register of PCIe Capabilities Structure. So, this requires the altera_pcie_cfg_read() and altera_pcie_cfg_write(). I can restructure the altera_pcie_cfg_read() and altera_pcie_cfg_write() and have new _altera_pcie_cfg_read() and _altera_pcie_cfg_write() that avoid the dependency of struct pci_bus. By doing this, we can retrain the link before pci_scan_root_bus and remove _FIXUP() Will send new v3 patch, please take a look. > >> We can use >> pci_bus_find_capability() and pci_bus_read_config_word() with struct >> pci_bus instead. >> But this only can be called after pci_scan_root_bus(). > >> Found >> iproc_pcie_check_link() have similar implementation. > > You're right, and I don't like iproc_pcie_check_link() either, for the > same reasons. > > The iproc_pcie_check_link() is a little better because it's called > before enumeration: > > pci_create_root_bus() > iproc_pcie_check_link() > pci_scan_child_bus() > > But it would be a lot better if iproc_pcie_check_link() were done > first, before pci_create_root_bus(). Then it would be more like the > structure of other drivers, and we could use pci_scan_root_bus() > instead. > > Comments, iproc folks? > > Bjorn > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] PCI: altera: Retrain link in rootport mode only
On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas wrote: > On Fri, Aug 19, 2016 at 04:24:38PM +0800, Ley Foon Tan wrote: >> Altera PCIe IP can be configured as rootport or device and they might have >> same vendor ID. It will cause the system hang issue if Altera PCIe is in >> endpoint mode and work with other PCIe rootport that from other vendors. >> So, add the rootport mode checking in link retrain fixup function. >> >> Signed-off-by: Ley Foon Tan >> --- >> v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT >> --- >> drivers/pci/host/pcie-altera.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c >> index 58eef99..33b6968 100644 >> --- a/drivers/pci/host/pcie-altera.c >> +++ b/drivers/pci/host/pcie-altera.c >> @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev) >> u16 linkcap, linkstat; >> struct altera_pcie *pcie = dev->bus->sysdata; >> >> + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) >> + return; >> + >> if (!altera_pcie_link_is_up(pcie)) >> return; > > Instead of making this a PCI fixup, can you make an > altera_pcie_host_init() function, call it from altera_pcie_probe(), > and do the link retrain there? Then you wouldn't need to worry about > whether this is a Root Port or an Endpoint, plus it would make the > altera driver structure more like the other drivers. > > You would call altera_pcie_host_init() before pci_scan_root_bus(), so > you wouldn't have a pci_dev yet, so you wouldn't be able to use > pcie_capability_set_word() to set the PCI_EXP_LNKCTL_RL bit. But I > assume there's some device-dependent way to access it using > cra_writel()? We can't use cra_write() to set PCI_EXP_LNKCTL_RL bit. We can use pci_bus_find_capability() and pci_bus_read_config_word() with struct pci_bus instead. But this only can be called after pci_scan_root_bus(). Found iproc_pcie_check_link() have similar implementation. Tested this method is working. Do you think it is okay? If yes, then I will send in next revision. Thanks. Regards Ley Foon
[PATCH v2] PCI: altera: Retrain link in rootport mode only
Altera PCIe IP can be configured as rootport or device and they might have same vendor ID. It will cause the system hang issue if Altera PCIe is in endpoint mode and work with other PCIe rootport that from other vendors. So, add the rootport mode checking in link retrain fixup function. Signed-off-by: Ley Foon Tan --- v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT --- drivers/pci/host/pcie-altera.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c index 58eef99..33b6968 100644 --- a/drivers/pci/host/pcie-altera.c +++ b/drivers/pci/host/pcie-altera.c @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev) u16 linkcap, linkstat; struct altera_pcie *pcie = dev->bus->sysdata; + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) + return; + if (!altera_pcie_link_is_up(pcie)) return; -- 1.8.2.1
Re: [PATCH] PCI: altera: Retrain link in rootport mode only
On Fri, Aug 19, 2016 at 4:18 AM, Bjorn Helgaas wrote: > > On Mon, Aug 15, 2016 at 04:36:19PM +0800, Ley Foon Tan wrote: > > Altera PCIe IP can be configured as rootport or device and they might have > > same vendor ID. It will cause the system hang issue if Altera PCIe is in > > endpoint mode and work with other PCIe rootport that from other vendors. > > So, add the rootport mode checking in link retrain fixup function. > > > > Signed-off-by: Ley Foon Tan > > --- > > drivers/pci/host/pcie-altera.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c > > index 58eef99..6477738 100644 > > --- a/drivers/pci/host/pcie-altera.c > > +++ b/drivers/pci/host/pcie-altera.c > > @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev) > > u16 linkcap, linkstat; > > struct altera_pcie *pcie = dev->bus->sysdata; > > > > + if (!pci_is_root_bus(dev->bus)) > > + return; > > It seems like it would be more direct to check for > "pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT"? Okay, will change in next version. > > > if (!altera_pcie_link_is_up(pcie)) > > return; > > > > -- > > 1.8.2.1 > >
Re: [PATCH] PCI: altera: Poll for link training status after retraining the link
On Fri, Aug 19, 2016 at 4:19 AM, Bjorn Helgaas wrote:
> On Mon, Aug 15, 2016 at 02:06:02PM +0800, Ley Foon Tan wrote:
>> Poll for link training status is cleared before poll for link up status.
>> This can help to get the reliable link up status, especially when PCIe
>> is in Gen 3 speed.
>>
>> Signed-off-by: Ley Foon Tan
>
> Applied to pci/host-altera for v4.9, thanks!
Thanks, Bjorn.
>
>> ---
>> drivers/pci/host/pcie-altera.c | 45
>> ++
>> 1 file changed, 37 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
>> index 2b78376..58eef99 100644
>> --- a/drivers/pci/host/pcie-altera.c
>> +++ b/drivers/pci/host/pcie-altera.c
>> @@ -61,7 +61,8 @@
>> #define TLP_LOOP 500
>> #define RP_DEVFN 0
>>
>> -#define LINK_UP_TIMEOUT 5000
>> +#define LINK_UP_TIMEOUT HZ
>> +#define LINK_RETRAIN_TIMEOUT HZ
>>
>> #define INTX_NUM 4
>>
>> @@ -99,11 +100,44 @@ static bool altera_pcie_link_is_up(struct altera_pcie
>> *pcie)
>> return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
>> }
>>
>> +static void altera_wait_link_retrain(struct pci_dev *dev)
>> +{
>> + u16 reg16;
>> + unsigned long start_jiffies;
>> + struct altera_pcie *pcie = dev->bus->sysdata;
>> +
>> + /* Wait for link training end. */
>> + start_jiffies = jiffies;
>> + for (;;) {
>> + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
>> + if (!(reg16 & PCI_EXP_LNKSTA_LT))
>> + break;
>> +
>> + if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
>> {
>> + dev_err(&pcie->pdev->dev, "link retrain timeout\n");
>> + break;
>> + }
>> + udelay(100);
>> + }
>> +
>> + /* Wait for link is up */
>> + start_jiffies = jiffies;
>> + for (;;) {
>> + if (altera_pcie_link_is_up(pcie))
>> + break;
>> +
>> + if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
>> + dev_err(&pcie->pdev->dev, "link up timeout\n");
>> + break;
>> + }
>> + udelay(100);
>> + }
>> +}
>> +
>> static void altera_pcie_retrain(struct pci_dev *dev)
>> {
>> u16 linkcap, linkstat;
>> struct altera_pcie *pcie = dev->bus->sysdata;
>> - int timeout = 0;
>>
>> if (!altera_pcie_link_is_up(pcie))
>> return;
>> @@ -121,12 +155,7 @@ static void altera_pcie_retrain(struct pci_dev *dev)
>> if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
>> pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
>>PCI_EXP_LNKCTL_RL);
>> - while (!altera_pcie_link_is_up(pcie)) {
>> - timeout++;
>> - if (timeout > LINK_UP_TIMEOUT)
>> - break;
>> - udelay(5);
>> - }
>> + altera_wait_link_retrain(dev);
>> }
>> }
>> DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
>> --
>> 1.8.2.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] PCI: altera: Poll for link training status after retraining the link
Poll for link training status is cleared before poll for link up status.
This can help to get the reliable link up status, especially when PCIe
is in Gen 3 speed.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/pcie-altera.c | 45 ++
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 2b78376..58eef99 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -61,7 +61,8 @@
#define TLP_LOOP 500
#define RP_DEVFN 0
-#define LINK_UP_TIMEOUT5000
+#define LINK_UP_TIMEOUTHZ
+#define LINK_RETRAIN_TIMEOUT HZ
#define INTX_NUM 4
@@ -99,11 +100,44 @@ static bool altera_pcie_link_is_up(struct altera_pcie
*pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+static void altera_wait_link_retrain(struct pci_dev *dev)
+{
+ u16 reg16;
+ unsigned long start_jiffies;
+ struct altera_pcie *pcie = dev->bus->sysdata;
+
+ /* Wait for link training end. */
+ start_jiffies = jiffies;
+ for (;;) {
+ pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
+ if (!(reg16 & PCI_EXP_LNKSTA_LT))
+ break;
+
+ if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
+ dev_err(&pcie->pdev->dev, "link retrain timeout\n");
+ break;
+ }
+ udelay(100);
+ }
+
+ /* Wait for link is up */
+ start_jiffies = jiffies;
+ for (;;) {
+ if (altera_pcie_link_is_up(pcie))
+ break;
+
+ if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
+ dev_err(&pcie->pdev->dev, "link up timeout\n");
+ break;
+ }
+ udelay(100);
+ }
+}
+
static void altera_pcie_retrain(struct pci_dev *dev)
{
u16 linkcap, linkstat;
struct altera_pcie *pcie = dev->bus->sysdata;
- int timeout = 0;
if (!altera_pcie_link_is_up(pcie))
return;
@@ -121,12 +155,7 @@ static void altera_pcie_retrain(struct pci_dev *dev)
if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_RL);
- while (!altera_pcie_link_is_up(pcie)) {
- timeout++;
- if (timeout > LINK_UP_TIMEOUT)
- break;
- udelay(5);
- }
+ altera_wait_link_retrain(dev);
}
}
DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
--
1.8.2.1
[PATCH] PCI: altera: Retrain link in rootport mode only
Altera PCIe IP can be configured as rootport or device and they might have same vendor ID. It will cause the system hang issue if Altera PCIe is in endpoint mode and work with other PCIe rootport that from other vendors. So, add the rootport mode checking in link retrain fixup function. Signed-off-by: Ley Foon Tan --- drivers/pci/host/pcie-altera.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c index 58eef99..6477738 100644 --- a/drivers/pci/host/pcie-altera.c +++ b/drivers/pci/host/pcie-altera.c @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev) u16 linkcap, linkstat; struct altera_pcie *pcie = dev->bus->sysdata; + if (!pci_is_root_bus(dev->bus)) + return; + if (!altera_pcie_link_is_up(pcie)) return; -- 1.8.2.1
Re: [PATCH 0/2] PCI: altera: fix link retrain
On Sat, Jul 23, 2016 at 5:07 AM, Bjorn Helgaas wrote:
>
> On Tue, Jun 21, 2016 at 04:53:11PM +0800, Ley Foon Tan wrote:
> > This 2 patches fix the issue before and after retrain link.
> >
> > Ley Foon Tan (2):
> > PCI: altera: check link status before retrain link
> > PCI: altera: Polling for link up status after retrain the link
> >
> > drivers/pci/host/pcie-altera.c | 48
> > +++---
> > 1 file changed, 31 insertions(+), 17 deletions(-)
>
> I applied these to pci/host-altera for v4.8, thanks!
>
> I split the code move into its own patch so the bug fix is clearly
> visible. I also fixed these whitespace errors:
>
> if(!altera_pcie_link_is_up(pcie))
> while(!altera_pcie_link_is_up(pcie)) {
>
> A space is required after "if" and "while".
Hi Bjorn
Thanks a lot!
Regards
Ley Foon
Re: [PATCH 0/2] PCI: altera: fix link retrain
On Tue, Jul 12, 2016 at 6:19 PM, Ley Foon Tan wrote: > > On Tue, Jun 21, 2016 at 4:53 PM, Ley Foon Tan wrote: > > > > This 2 patches fix the issue before and after retrain link. > > > > Ley Foon Tan (2): > > PCI: altera: check link status before retrain link > > PCI: altera: Polling for link up status after retrain the link > > > > drivers/pci/host/pcie-altera.c | 48 > > +++--- > > 1 file changed, 31 insertions(+), 17 deletions(-) > > > > Hi Bjorn > > Do you any comment on these 2 patches? > > Regards > Ley Foon Hi Bjorn Do you have any chance take a look these 2 patches? Hope they can go into 4.8-rc1. Thanks. Regards Ley Foon
