Re: [PATCH] MIPS: fix build failure

[Markos Chandras]

On 10/28/2015 10:18 AM, Markos Chandras wrote:
> On 10/28/2015 10:08 AM, Sudip Mukherjee wrote:
>> While building for mips defconfig the build failed with the error:
>> In function 'create_elf_tables':
>> arch/mips/include/asm/elf.h:425:14: error: 
>> 'AT_SYSINFO_EHDR' undeclared (first use in this function)
>>
>> AT_SYSINFO_EHDR is defined in uapi/asm/auxvec.h which was not included
>> here.
>>
>> Fixes: c1fb442ade67 ("MIPS: Initial implementation of a VDSO")
>> Signed-off-by: Sudip Mukherjee 
>> ---
>>
>> This patch is based on mips-for-linux-next branch.
>>
> 
> Something is not right here. The  header is already
> included in that file which in turns includes uapi/asm/auxvec.h
> 
> I haven't seen this failure in Ralf's tree. Could you share your .config
> and perhaps the hash of the mips-for-linux-next tree you tried it on?
> 
> 
I believe your problem might be similar to this

https://www.linux-mips.org/archives/linux-mips/2015-10/msg00280.html

in other words either remove the generated headers or do a 'make
mrproper' (make sure to backup your .config) and try again

-- 
markos
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Re: [PATCH] MIPS: fix build failure

[Markos Chandras]

On 10/28/2015 10:08 AM, Sudip Mukherjee wrote:
> While building for mips defconfig the build failed with the error:
> In function 'create_elf_tables':
> arch/mips/include/asm/elf.h:425:14: error: 
> 'AT_SYSINFO_EHDR' undeclared (first use in this function)
> 
> AT_SYSINFO_EHDR is defined in uapi/asm/auxvec.h which was not included
> here.
> 
> Fixes: c1fb442ade67 ("MIPS: Initial implementation of a VDSO")
> Signed-off-by: Sudip Mukherjee 
> ---
> 
> This patch is based on mips-for-linux-next branch.
> 

Something is not right here. The  header is already
included in that file which in turns includes uapi/asm/auxvec.h

I haven't seen this failure in Ralf's tree. Could you share your .config
and perhaps the hash of the mips-for-linux-next tree you tried it on?


-- 
markos
--
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Re: [PATCH] MIPS: fix build failure

[Markos Chandras]

On 10/28/2015 10:08 AM, Sudip Mukherjee wrote:
> While building for mips defconfig the build failed with the error:
> In function 'create_elf_tables':
> arch/mips/include/asm/elf.h:425:14: error: 
> 'AT_SYSINFO_EHDR' undeclared (first use in this function)
> 
> AT_SYSINFO_EHDR is defined in uapi/asm/auxvec.h which was not included
> here.
> 
> Fixes: c1fb442ade67 ("MIPS: Initial implementation of a VDSO")
> Signed-off-by: Sudip Mukherjee 
> ---
> 
> This patch is based on mips-for-linux-next branch.
> 

Something is not right here. The  header is already
included in that file which in turns includes uapi/asm/auxvec.h

I haven't seen this failure in Ralf's tree. Could you share your .config
and perhaps the hash of the mips-for-linux-next tree you tried it on?


-- 
markos
--
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Re: [PATCH] MIPS: fix build failure

[Markos Chandras]

On 10/28/2015 10:18 AM, Markos Chandras wrote:
> On 10/28/2015 10:08 AM, Sudip Mukherjee wrote:
>> While building for mips defconfig the build failed with the error:
>> In function 'create_elf_tables':
>> arch/mips/include/asm/elf.h:425:14: error: 
>> 'AT_SYSINFO_EHDR' undeclared (first use in this function)
>>
>> AT_SYSINFO_EHDR is defined in uapi/asm/auxvec.h which was not included
>> here.
>>
>> Fixes: c1fb442ade67 ("MIPS: Initial implementation of a VDSO")
>> Signed-off-by: Sudip Mukherjee <su...@vectorindia.org>
>> ---
>>
>> This patch is based on mips-for-linux-next branch.
>>
> 
> Something is not right here. The  header is already
> included in that file which in turns includes uapi/asm/auxvec.h
> 
> I haven't seen this failure in Ralf's tree. Could you share your .config
> and perhaps the hash of the mips-for-linux-next tree you tried it on?
> 
> 
I believe your problem might be similar to this

https://www.linux-mips.org/archives/linux-mips/2015-10/msg00280.html

in other words either remove the generated headers or do a 'make
mrproper' (make sure to backup your .config) and try again

-- 
markos
--
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[PATCH v3 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith 

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
Changes since v2:
- Do not export VDSO symbols if the toolchain does not have proper support
for the VDSO.

Changes since v1:
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  71 ++-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   5 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 9 files changed, 460 insertions(+), 10 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 
+#include 
+
 /**
  * struct mips_vdso_image - Details of a VDSO image.
  * @data: Pointer to VDSO image data (page-aligne

Re: [PATCH v3] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/20/2015 07:12 PM, Leonid Yegoshin wrote:
> On 10/20/2015 01:35 AM, Markos Chandras wrote:
>> What tree did you use for this patch? It does not seem to apply to
>> mainline or Ralf's upstream-sfr. 
> 
> May I ask you to elaborate more and send me a concern details?
> I definitely rebased it to mips-for-linux-next of upstream-sfr from LMO.
> 
> - Leonid
> 
Ok thanks for clarifying. It does apply to today's upstream-sfr.

-- 
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Re: [PATCH v3] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/20/2015 07:12 PM, Leonid Yegoshin wrote:
> On 10/20/2015 01:35 AM, Markos Chandras wrote:
>> What tree did you use for this patch? It does not seem to apply to
>> mainline or Ralf's upstream-sfr. 
> 
> May I ask you to elaborate more and send me a concern details?
> I definitely rebased it to mips-for-linux-next of upstream-sfr from LMO.
> 
> - Leonid
> 
Ok thanks for clarifying. It does apply to today's upstream-sfr.

-- 
markos
--
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[PATCH v3 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
Changes since v2:
- Do not export VDSO symbols if the toolchain does not have proper support
for the VDSO.

Changes since v1:
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  71 ++-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   5 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 9 files changed, 460 insertions(+), 10 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.sm...@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 

Re: [PATCH v3] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/19/2015 07:39 PM, Leonid Yegoshin wrote:
> MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
> set to processing aka rt_sigaction() variant only.
> 
> Fixed.
> --
> V3: Signature added.
> v2: Taken in account CONFIG vars interdependencies and conditional expression
> simplified. As a result, the reverse problem fixed (introduced by v1).
> Tested on all 3 ABIs.
> --
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  arch/mips/include/asm/signal.h |   12 +---
>  arch/mips/kernel/signal.c  |2 +-
>  2 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
> index 003e273eff4c..2292373ff11a 100644
> --- a/arch/mips/include/asm/signal.h
> +++ b/arch/mips/include/asm/signal.h
> @@ -11,11 +11,17 @@
>  
>  #include 
>  
> +#ifdef CONFIG_MIPS32_COMPAT
> +extern struct mips_abi mips_abi_32;
>  
> -#ifdef CONFIG_TRAD_SIGNALS
> -#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
> +#define sig_uses_siginfo(ka, abi)   \
> + ((abi != _abi_32) ? 1 :\
> + ((ka)->sa.sa_flags & SA_SIGINFO))
>  #else
> -#define sig_uses_siginfo(ka) (1)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? 1 : \
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #endif
>  
>  #include 
> diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
> index bf792e2839a6..5f18d0b879e0 100644
> --- a/arch/mips/kernel/signal.c
> +++ b/arch/mips/kernel/signal.c
> @@ -798,7 +798,7 @@ static void handle_signal(struct ksignal *ksig, struct 
> pt_regs *regs)
>   regs->regs[0] = 0;  /* Don't deal with this again.  
> */
>   }
>  
> - if (sig_uses_siginfo(>ka))
> + if (sig_uses_siginfo(>ka, abi))
>   ret = abi->setup_rt_frame(vdso + abi->vdso->off_rt_sigreturn,
> ksig, regs, oldset);
>   else
> 
> 

What tree did you use for this patch? It does not seem to apply to
mainline or Ralf's upstream-sfr.

-- 
markos
--
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Re: [PATCH v3] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/19/2015 07:39 PM, Leonid Yegoshin wrote:
> MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
> set to processing aka rt_sigaction() variant only.
> 
> Fixed.
> --
> V3: Signature added.
> v2: Taken in account CONFIG vars interdependencies and conditional expression
> simplified. As a result, the reverse problem fixed (introduced by v1).
> Tested on all 3 ABIs.
> --
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  arch/mips/include/asm/signal.h |   12 +---
>  arch/mips/kernel/signal.c  |2 +-
>  2 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
> index 003e273eff4c..2292373ff11a 100644
> --- a/arch/mips/include/asm/signal.h
> +++ b/arch/mips/include/asm/signal.h
> @@ -11,11 +11,17 @@
>  
>  #include 
>  
> +#ifdef CONFIG_MIPS32_COMPAT
> +extern struct mips_abi mips_abi_32;
>  
> -#ifdef CONFIG_TRAD_SIGNALS
> -#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
> +#define sig_uses_siginfo(ka, abi)   \
> + ((abi != _abi_32) ? 1 :\
> + ((ka)->sa.sa_flags & SA_SIGINFO))
>  #else
> -#define sig_uses_siginfo(ka) (1)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? 1 : \
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #endif
>  
>  #include 
> diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
> index bf792e2839a6..5f18d0b879e0 100644
> --- a/arch/mips/kernel/signal.c
> +++ b/arch/mips/kernel/signal.c
> @@ -798,7 +798,7 @@ static void handle_signal(struct ksignal *ksig, struct 
> pt_regs *regs)
>   regs->regs[0] = 0;  /* Don't deal with this again.  
> */
>   }
>  
> - if (sig_uses_siginfo(>ka))
> + if (sig_uses_siginfo(>ka, abi))
>   ret = abi->setup_rt_frame(vdso + abi->vdso->off_rt_sigreturn,
> ksig, regs, oldset);
>   else
> 
> 

What tree did you use for this patch? It does not seem to apply to
mainline or Ralf's upstream-sfr.

-- 
markos
--
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Re: [PATCH] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/15/2015 07:50 PM, Leonid Yegoshin wrote:
> MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
> set to processing aka rt_sigaction() variant only.
> 
> Fixed.
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  arch/mips/include/asm/signal.h |   15 ---
>  arch/mips/kernel/signal.c  |2 +-
>  2 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
> index 003e273eff4c..06fe599782df 100644
> --- a/arch/mips/include/asm/signal.h
> +++ b/arch/mips/include/asm/signal.h
> @@ -11,11 +11,20 @@
>  
>  #include 
>  
> +#ifdef CONFIG_MIPS32_COMPAT
> +extern struct mips_abi mips_abi_32;
>  
> -#ifdef CONFIG_TRAD_SIGNALS
> -#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? \
> + (config_enabled(CONFIG_MIPS32_COMPAT) ? \
> + (abi != _abi_32) : 1) :\
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #else
> -#define sig_uses_siginfo(ka) (1)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? 1 : \
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #endif
>  
>  #include 
> diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
> index bf792e2839a6..5f18d0b879e0 100644
> --- a/arch/mips/kernel/signal.c
> +++ b/arch/mips/kernel/signal.c
> @@ -798,7 +798,7 @@ static void handle_signal(struct ksignal *ksig, struct 
> pt_regs *regs)
>   regs->regs[0] = 0;  /* Don't deal with this again.  
> */
>   }
>  
> - if (sig_uses_siginfo(>ka))
> + if (sig_uses_siginfo(>ka, abi))
>   ret = abi->setup_rt_frame(vdso + abi->vdso->off_rt_sigreturn,
> ksig, regs, oldset);
>   else
> 

Is this similar to

https://www.linux-mips.org/archives/linux-mips/2015-08/msg00449.html ?

-- 
markos
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Re: [PATCH] MIPS64: signal: n64 kernel bugfix of MIPS32 o32 ABI sigaction syscall

[Markos Chandras]

On 10/15/2015 07:50 PM, Leonid Yegoshin wrote:
> MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
> set to processing aka rt_sigaction() variant only.
> 
> Fixed.
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  arch/mips/include/asm/signal.h |   15 ---
>  arch/mips/kernel/signal.c  |2 +-
>  2 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
> index 003e273eff4c..06fe599782df 100644
> --- a/arch/mips/include/asm/signal.h
> +++ b/arch/mips/include/asm/signal.h
> @@ -11,11 +11,20 @@
>  
>  #include 
>  
> +#ifdef CONFIG_MIPS32_COMPAT
> +extern struct mips_abi mips_abi_32;
>  
> -#ifdef CONFIG_TRAD_SIGNALS
> -#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? \
> + (config_enabled(CONFIG_MIPS32_COMPAT) ? \
> + (abi != _abi_32) : 1) :\
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #else
> -#define sig_uses_siginfo(ka) (1)
> +#define sig_uses_siginfo(ka, abi)   \
> + (config_enabled(CONFIG_64BIT) ? 1 : \
> + (config_enabled(CONFIG_TRAD_SIGNALS) ?  \
> + ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
>  #endif
>  
>  #include 
> diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
> index bf792e2839a6..5f18d0b879e0 100644
> --- a/arch/mips/kernel/signal.c
> +++ b/arch/mips/kernel/signal.c
> @@ -798,7 +798,7 @@ static void handle_signal(struct ksignal *ksig, struct 
> pt_regs *regs)
>   regs->regs[0] = 0;  /* Don't deal with this again.  
> */
>   }
>  
> - if (sig_uses_siginfo(>ka))
> + if (sig_uses_siginfo(>ka, abi))
>   ret = abi->setup_rt_frame(vdso + abi->vdso->off_rt_sigreturn,
> ksig, regs, oldset);
>   else
> 

Is this similar to

https://www.linux-mips.org/archives/linux-mips/2015-08/msg00449.html ?

-- 
markos
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[PATCH v2 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith 

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
Changes since v1:
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  71 ++-
 arch/mips/vdso/Makefile  |   2 +-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   3 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 10 files changed, 459 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 
+#include 
+
 /**
  * struct mips_vdso_image - Details of a VDSO image.
  * @data: Pointer to VDSO image data (page-aligned).
@@ -53,18 +55,82 @@ extern struct mips_vdso_

[PATCH v2 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

From: Alex Smith 

The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.

When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.

[markos.chand...@imgtec.com:
- Move mapping code to arch/mips/kernel/vdso.c and use a resource
type to get the GIC usermode information
- Avoid renaming function arguments and use __gic_base_addr to hold
the base GIC address prior to ioremap.]

Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Marc Zyngier 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
Changes since v1:
- Move mapping code to arch/mips/kernel/vdso.c and use a resource
type to get the GIC usermode information
- Avoid renaming function arguments and use __gic_base_addr to hold
the base GIC address prior to ioremap.

http://www.linux-mips.org/archives/linux-mips/2015-09/msg00316.html
---
 drivers/irqchip/irq-mips-gic.c   | 14 ++
 include/linux/irqchip/mips-gic.h | 17 +
 2 files changed, 31 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16bb8a94..392beebb81ee 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -29,6 +29,7 @@ struct gic_pcpu_mask {
DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
 };
 
+static unsigned long __gic_base_addr;
 static void __iomem *gic_base;
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static DEFINE_SPINLOCK(gic_lock);
@@ -301,6 +302,17 @@ int gic_get_c0_fdc_int(void)
  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 }
 
+int gic_get_usm_range(struct resource *gic_usm_res)
+{
+   if (!gic_present)
+   return -1;
+
+   gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;
+   gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);
+
+   return 0;
+}
+
 static void gic_handle_shared_int(bool chained)
 {
unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
@@ -790,6 +802,8 @@ static void __init __gic_init(unsigned long gic_base_addr,
 {
unsigned int gicconfig;
 
+   __gic_base_addr = gic_base_addr;
+
gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 4e6861605050..71ab7c548550 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -9,6 +9,7 @@
 #define __LINUX_IRQCHIP_MIPS_GIC_H
 
 #include 
+#include 
 
 #define GIC_MAX_INTRS  256
 
@@ -245,6 +246,8 @@
 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
 
+#ifdef CONFIG_MIPS_GIC
+
 extern unsigned int gic_present;
 
 extern void gic_init(unsigned long gic_base_addr,
@@ -264,4 +267,18 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned 
int);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
+extern int gic_get_usm_range(struct resource *gic_usm_res);
+
+#else /* CONFIG_MIPS_GIC */
+
+#define gic_present0
+
+static int gic_get_usm_range(struct resource *gic_usm_res)
+{
+   /* Shouldn't be called. */
+   return -1
+}
+
+#endif /* CONFIG_MIPS_GIC */
+
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
-- 
2.6.1

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[PATCH v2 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
Changes since v1:
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  71 ++-
 arch/mips/vdso/Makefile  |   2 +-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   3 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 10 files changed, 459 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.sm...@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 
+#include 
+
 /**
  * struct mips_vdso_image - Details of a VDSO 

[PATCH v2 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.

When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.

[markos.chand...@imgtec.com:
- Move mapping code to arch/mips/kernel/vdso.c and use a resource
type to get the GIC usermode information
- Avoid renaming function arguments and use __gic_base_addr to hold
the base GIC address prior to ioremap.]

Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
Changes since v1:
- Move mapping code to arch/mips/kernel/vdso.c and use a resource
type to get the GIC usermode information
- Avoid renaming function arguments and use __gic_base_addr to hold
the base GIC address prior to ioremap.

http://www.linux-mips.org/archives/linux-mips/2015-09/msg00316.html
---
 drivers/irqchip/irq-mips-gic.c   | 14 ++
 include/linux/irqchip/mips-gic.h | 17 +
 2 files changed, 31 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16bb8a94..392beebb81ee 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -29,6 +29,7 @@ struct gic_pcpu_mask {
DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
 };
 
+static unsigned long __gic_base_addr;
 static void __iomem *gic_base;
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static DEFINE_SPINLOCK(gic_lock);
@@ -301,6 +302,17 @@ int gic_get_c0_fdc_int(void)
  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 }
 
+int gic_get_usm_range(struct resource *gic_usm_res)
+{
+   if (!gic_present)
+   return -1;
+
+   gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;
+   gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);
+
+   return 0;
+}
+
 static void gic_handle_shared_int(bool chained)
 {
unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
@@ -790,6 +802,8 @@ static void __init __gic_init(unsigned long gic_base_addr,
 {
unsigned int gicconfig;
 
+   __gic_base_addr = gic_base_addr;
+
gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 4e6861605050..71ab7c548550 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -9,6 +9,7 @@
 #define __LINUX_IRQCHIP_MIPS_GIC_H
 
 #include 
+#include 
 
 #define GIC_MAX_INTRS  256
 
@@ -245,6 +246,8 @@
 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
 
+#ifdef CONFIG_MIPS_GIC
+
 extern unsigned int gic_present;
 
 extern void gic_init(unsigned long gic_base_addr,
@@ -264,4 +267,18 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned 
int);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
+extern int gic_get_usm_range(struct resource *gic_usm_res);
+
+#else /* CONFIG_MIPS_GIC */
+
+#define gic_present0
+
+static int gic_get_usm_range(struct resource *gic_usm_res)
+{
+   /* Shouldn't be called. */
+   return -1
+}
+
+#endif /* CONFIG_MIPS_GIC */
+
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
-- 
2.6.1

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Re: [PATCH 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

Hi,

On 09/28/2015 11:55 AM, Marc Zyngier wrote:
> On 28/09/15 11:11, Markos Chandras wrote:
>> From: Alex Smith 
>>
>> The GIC provides a "user-mode visible" section containing a mirror of
>> the counter registers which can be mapped into user memory. This will
>> be used by the VDSO time function implementations, so provide a
>> function to map it in.
>>
>> When the GIC is not enabled in Kconfig a dummy inline version of this
>> function is provided, along with "#define gic_present 0", so that we
>> don't have to litter the VDSO code with ifdefs.
>>
>> Cc: Thomas Gleixner 
>> Cc: Jason Cooper 
>> Cc: Marc Zyngier 
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Alex Smith 
>> Signed-off-by: Markos Chandras 
>> ---
>>  drivers/irqchip/irq-mips-gic.c   | 27 +--
>>  include/linux/irqchip/mips-gic.h | 24 ++--
>>  2 files changed, 43 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
>> index af2f16bb8a94..c995b199ca32 100644
>> --- a/drivers/irqchip/irq-mips-gic.c
>> +++ b/drivers/irqchip/irq-mips-gic.c
>> @@ -13,6 +13,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -29,6 +30,7 @@ struct gic_pcpu_mask {
>>  DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
>>  };
>>  
>> +static unsigned long gic_base_addr;
>>  static void __iomem *gic_base;
>>  static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
>>  static DEFINE_SPINLOCK(gic_lock);
>> @@ -301,6 +303,19 @@ int gic_get_c0_fdc_int(void)
>>GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
>>  }
>>  
>> +int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
>> + unsigned long size)
>> +{
>> +unsigned long pfn;
>> +
>> +BUG_ON(!gic_present);
> 
> Why do you have a BUG() here, while you're just returning -1 in the case
> where CONFIG_MIPS_GIC is not refined? This feels overly harsh to me.

I suppose i could change that to return -1 if git_present is not true.

> 
>> +BUG_ON(size > USM_VISIBLE_SECTION_SIZE);
> 
> Same here.

But I think this is different. The size of mapping has to be less than
USM_VISIBLE_SECTION_SIZE because that's the maximum data size exposed by
the GIC chip for userspace use. So if that's not true, then BUG_ON seems
like a sensible thing to do.

> 
> - Does this code have to be in the irqchip driver? It really feels out
> of place, and I'd rather see a function that returns the mappable range
> to the VDSO code, where the mapping would occur.
> 
> Thanks,
> 

That does seem like a good idea. I will have a look


-- 
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Re: [PATCH 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

Hi,

On 09/28/2015 11:55 AM, Marc Zyngier wrote:
> On 28/09/15 11:11, Markos Chandras wrote:
>> From: Alex Smith <alex.sm...@imgtec.com>
>>
>> The GIC provides a "user-mode visible" section containing a mirror of
>> the counter registers which can be mapped into user memory. This will
>> be used by the VDSO time function implementations, so provide a
>> function to map it in.
>>
>> When the GIC is not enabled in Kconfig a dummy inline version of this
>> function is provided, along with "#define gic_present 0", so that we
>> don't have to litter the VDSO code with ifdefs.
>>
>> Cc: Thomas Gleixner <t...@linutronix.de>
>> Cc: Jason Cooper <ja...@lakedaemon.net>
>> Cc: Marc Zyngier <marc.zyng...@arm.com>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
>> Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
>> ---
>>  drivers/irqchip/irq-mips-gic.c   | 27 +--
>>  include/linux/irqchip/mips-gic.h | 24 ++--
>>  2 files changed, 43 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
>> index af2f16bb8a94..c995b199ca32 100644
>> --- a/drivers/irqchip/irq-mips-gic.c
>> +++ b/drivers/irqchip/irq-mips-gic.c
>> @@ -13,6 +13,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -29,6 +30,7 @@ struct gic_pcpu_mask {
>>  DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
>>  };
>>  
>> +static unsigned long gic_base_addr;
>>  static void __iomem *gic_base;
>>  static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
>>  static DEFINE_SPINLOCK(gic_lock);
>> @@ -301,6 +303,19 @@ int gic_get_c0_fdc_int(void)
>>GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
>>  }
>>  
>> +int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
>> + unsigned long size)
>> +{
>> +unsigned long pfn;
>> +
>> +BUG_ON(!gic_present);
> 
> Why do you have a BUG() here, while you're just returning -1 in the case
> where CONFIG_MIPS_GIC is not refined? This feels overly harsh to me.

I suppose i could change that to return -1 if git_present is not true.

> 
>> +BUG_ON(size > USM_VISIBLE_SECTION_SIZE);
> 
> Same here.

But I think this is different. The size of mapping has to be less than
USM_VISIBLE_SECTION_SIZE because that's the maximum data size exposed by
the GIC chip for userspace use. So if that's not true, then BUG_ON seems
like a sensible thing to do.

> 
> - Does this code have to be in the irqchip driver? It really feels out
> of place, and I'd rather see a function that returns the mappable range
> to the VDSO code, where the mapping would occur.
> 
> Thanks,
> 

That does seem like a good idea. I will have a look


-- 
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[PATCH 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith 

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  62 +-
 arch/mips/vdso/Makefile  |   2 +-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   3 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 10 files changed, 450 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 
+#include 
+
 /**
  * struct mips_vdso_image - Details of a VDSO image.
  * @data: Pointer to VDSO image data (page-aligned).
@@ -53,18 +55,82 @@ extern struct mips_vdso_image vdso_image_n32;
 
 /**
  * union mips_vdso_data - Data provided by the kernel for the VDSO.
+ * @xtime_sec: Current real time (seconds part).
+ * @xtime_nsec:Current real time (nanoseconds part, shifted).
+ * @wall_to_mono_sec:  Wall

[PATCH 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

From: Alex Smith 

The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.

When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.

Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Marc Zyngier 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
 drivers/irqchip/irq-mips-gic.c   | 27 +--
 include/linux/irqchip/mips-gic.h | 24 ++--
 2 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16bb8a94..c995b199ca32 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,6 +30,7 @@ struct gic_pcpu_mask {
DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
 };
 
+static unsigned long gic_base_addr;
 static void __iomem *gic_base;
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static DEFINE_SPINLOCK(gic_lock);
@@ -301,6 +303,19 @@ int gic_get_c0_fdc_int(void)
  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 }
 
+int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
+unsigned long size)
+{
+   unsigned long pfn;
+
+   BUG_ON(!gic_present);
+   BUG_ON(size > USM_VISIBLE_SECTION_SIZE);
+
+   pfn = (gic_base_addr + USM_VISIBLE_SECTION_OFS) >> PAGE_SHIFT;
+   return io_remap_pfn_range(vma, base, pfn, size,
+ pgprot_noncached(PAGE_READONLY));
+}
+
 static void gic_handle_shared_int(bool chained)
 {
unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
@@ -783,14 +798,15 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-static void __init __gic_init(unsigned long gic_base_addr,
- unsigned long gic_addrspace_size,
+static void __init __gic_init(unsigned long base_addr,
+ unsigned long addrspace_size,
  unsigned int cpu_vec, unsigned int irqbase,
  struct device_node *node)
 {
unsigned int gicconfig;
 
-   gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
+   gic_base_addr = base_addr;
+   gic_base = ioremap_nocache(base_addr, addrspace_size);
 
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -847,11 +863,10 @@ static void __init __gic_init(unsigned long gic_base_addr,
gic_ipi_init();
 }
 
-void __init gic_init(unsigned long gic_base_addr,
-unsigned long gic_addrspace_size,
+void __init gic_init(unsigned long base_addr, unsigned long addrspace_size,
 unsigned int cpu_vec, unsigned int irqbase)
 {
-   __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
+   __gic_init(base_addr, addrspace_size, cpu_vec, irqbase, NULL);
 }
 
 static int __init gic_of_init(struct device_node *node,
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 4e6861605050..68f2e9539204 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -245,10 +245,14 @@
 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
 
+struct vm_area_struct;
+
+#ifdef CONFIG_MIPS_GIC
+
 extern unsigned int gic_present;
 
-extern void gic_init(unsigned long gic_base_addr,
-   unsigned long gic_addrspace_size, unsigned int cpu_vec,
+extern void gic_init(unsigned long base_addr,
+   unsigned long addrspace_size, unsigned int cpu_vec,
unsigned int irqbase);
 extern void gic_clocksource_init(unsigned int);
 extern cycle_t gic_read_count(void);
@@ -264,4 +268,20 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned 
int);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
+extern int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
+   unsigned long size);
+
+#else /* CONFIG_MIPS_GIC */
+
+#define gic_present0
+
+static inline int gic_map_user_section(struct vm_area_struct *vma,
+  unsigned long base, unsigned long size)
+{
+   /* Shouldn't be called. */
+   return -1;
+}
+
+#endif /* CONFIG_MIPS_GIC */
+
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
-- 
2.5.3

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[PATCH 1/3] MIPS: Initial implementation of a VDSO

[Markos Chandras]

From: Alex Smith 

Add an initial implementation of a proper (i.e. an ELF shared library)
VDSO. With this commit it does not export any symbols, it only replaces
the current signal return trampoline page. A later commit will add user
implementations of gettimeofday()/clock_gettime().

To support both new toolchains and old ones which don't generate ABI
flags section, we define its content manually and then use a tool
(genvdso) to patch up the section to have the correct name and type.
genvdso also extracts symbol offsets ({,rt_}sigreturn) needed by the
kernel, and generates a C file containing a "struct mips_vdso_image"
containing both the VDSO data and these offsets. This C file is
compiled into the kernel.

On 64-bit kernels we require a different VDSO for each supported ABI,
so we may build up to 3 different VDSOs. The VDSO to use is selected by
the mips_abi structure.

A kernel/user shared data page is created and mapped below the VDSO
image. This is currently empty, but will be used by the user time
function implementations which are added later.

[markos.chand...@imgtec.com:
- Add more comments
- Move abi detection in genvdso.h since it's the get_symbol function
that needs it.
- Add an R6 specific way to calculate the base address of VDSO in order
to avoid the branch instruction which affects performance.
- Do not patch .gnu.attributes since it's not needed for dynamic linking.
- Simplify Makefile a little bit.
- checkpatch fixes]

Cc: linux-kernel@vger.kernel.org
Cc: Matthew Fortune 
Signed-off-by: Alex Smith 
Signed-off-by: Markos Chandras 
---
 arch/mips/Kbuild|   1 +
 arch/mips/include/asm/abi.h |   5 +-
 arch/mips/include/asm/elf.h |   7 +
 arch/mips/include/asm/processor.h   |   8 +-
 arch/mips/include/asm/vdso.h|  73 +++--
 arch/mips/include/uapi/asm/Kbuild   |   2 +-
 arch/mips/include/uapi/asm/auxvec.h |  17 +++
 arch/mips/kernel/signal.c   |  12 +-
 arch/mips/kernel/signal32.c |   7 +-
 arch/mips/kernel/signal_n32.c   |   5 +-
 arch/mips/kernel/vdso.c | 160 ++--
 arch/mips/vdso/.gitignore   |   4 +
 arch/mips/vdso/Makefile | 142 +
 arch/mips/vdso/elf.S|  68 +
 arch/mips/vdso/genvdso.c| 293 
 arch/mips/vdso/genvdso.h| 187 +++
 arch/mips/vdso/sigreturn.S  |  49 ++
 arch/mips/vdso/vdso.h   |  79 ++
 arch/mips/vdso/vdso.lds.S   | 100 
 19 files changed, 1095 insertions(+), 124 deletions(-)
 create mode 100644 arch/mips/include/uapi/asm/auxvec.h
 create mode 100644 arch/mips/vdso/.gitignore
 create mode 100644 arch/mips/vdso/Makefile
 create mode 100644 arch/mips/vdso/elf.S
 create mode 100644 arch/mips/vdso/genvdso.c
 create mode 100644 arch/mips/vdso/genvdso.h
 create mode 100644 arch/mips/vdso/sigreturn.S
 create mode 100644 arch/mips/vdso/vdso.h
 create mode 100644 arch/mips/vdso/vdso.lds.S

diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
index dd295335891a..5c3f688a5232 100644
--- a/arch/mips/Kbuild
+++ b/arch/mips/Kbuild
@@ -17,6 +17,7 @@ obj- := $(platform-)
 obj-y += kernel/
 obj-y += mm/
 obj-y += net/
+obj-y += vdso/
 
 ifdef CONFIG_KVM
 obj-y += kvm/
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 37f84078e78a..940760844e2f 100644
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -11,19 +11,20 @@
 
 #include 
 #include 
+#include 
 
 struct mips_abi {
int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
  struct pt_regs *regs, sigset_t *set);
-   const unsigned long signal_return_offset;
int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
 struct pt_regs *regs, sigset_t *set);
-   const unsigned long rt_signal_return_offset;
const unsigned long restart;
 
unsignedoff_sc_fpregs;
unsignedoff_sc_fpc_csr;
unsignedoff_sc_used_math;
+
+   struct mips_vdso_image *vdso;
 };
 
 #endif /* _ASM_ABI_H */
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 53b26933b12c..b01a6ff468e0 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -8,6 +8,7 @@
 #ifndef _ASM_ELF_H
 #define _ASM_ELF_H
 
+#include 
 #include 
 #include 
 
@@ -419,6 +420,12 @@ extern const char *__elf_platform;
 #define ELF_ET_DYN_BASE(TASK_SIZE / 3 * 2)
 #endif
 
+#define ARCH_DLINFO\
+do {   \
+   NEW_AUX_ENT(AT_SYSINFO_EHDR,\
+   (unsigned long)current->mm->context.vdso);  \
+} while (0)
+
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
 struct linux

[PATCH 0/3] MIPS VDSO support

[Markos Chandras]

Hi,

This series adds a proper VDSO to the kernel on MIPS. The first commit
adds the basic VDSO, replacing the current signal return trampoline
page. The following commits add user implementations of gettimeofday() and
clock_gettime() which can make use of either the CP0 count or the GIC
user-mode visible section.

A tree with these changes can be found at [1]. It's based on v4.3-rc3

Use of the time functions relies on glibc modifications. A patch for
this can be found in my repository at [2] and I will soon post it to the glibc
mailing list.

[1]: http://git.linux-mips.org/cgit/mchandras/linux.git/log/?h=4.3-vdso
[2]: https://github.com/hwoarang/glibc/tree/2.22-vdso

Alex Smith (3):
  MIPS: Initial implementation of a VDSO
  irqchip: irq-mips-gic: Provide function to map GIC user section
  MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

 arch/mips/Kbuild |   1 +
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/abi.h  |   5 +-
 arch/mips/include/asm/clocksource.h  |  29 
 arch/mips/include/asm/elf.h  |   7 +
 arch/mips/include/asm/processor.h|   8 +-
 arch/mips/include/asm/vdso.h | 139 +++--
 arch/mips/include/uapi/asm/Kbuild|   2 +-
 arch/mips/include/uapi/asm/auxvec.h  |  17 ++
 arch/mips/kernel/csrc-r4k.c  |  44 ++
 arch/mips/kernel/signal.c|  12 +-
 arch/mips/kernel/signal32.c  |   7 +-
 arch/mips/kernel/signal_n32.c|   5 +-
 arch/mips/kernel/vdso.c  | 198 ++-
 arch/mips/vdso/.gitignore|   4 +
 arch/mips/vdso/Makefile  | 142 +
 arch/mips/vdso/elf.S |  68 
 arch/mips/vdso/genvdso.c | 294 +++
 arch/mips/vdso/genvdso.h | 188 ++
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/sigreturn.S   |  49 ++
 arch/mips/vdso/vdso.h|  84 ++
 arch/mips/vdso/vdso.lds.S| 103 
 drivers/clocksource/mips-gic-timer.c |   7 +-
 drivers/irqchip/irq-mips-gic.c   |  27 +++-
 include/linux/irqchip/mips-gic.h |  24 ++-
 26 files changed, 1572 insertions(+), 129 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/include/uapi/asm/auxvec.h
 create mode 100644 arch/mips/vdso/.gitignore
 create mode 100644 arch/mips/vdso/Makefile
 create mode 100644 arch/mips/vdso/elf.S
 create mode 100644 arch/mips/vdso/genvdso.c
 create mode 100644 arch/mips/vdso/genvdso.h
 create mode 100644 arch/mips/vdso/gettimeofday.c
 create mode 100644 arch/mips/vdso/sigreturn.S
 create mode 100644 arch/mips/vdso/vdso.h
 create mode 100644 arch/mips/vdso/vdso.lds.S

-- 
2.5.3

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[PATCH 0/3] MIPS VDSO support

[Markos Chandras]

Hi,

This series adds a proper VDSO to the kernel on MIPS. The first commit
adds the basic VDSO, replacing the current signal return trampoline
page. The following commits add user implementations of gettimeofday() and
clock_gettime() which can make use of either the CP0 count or the GIC
user-mode visible section.

A tree with these changes can be found at [1]. It's based on v4.3-rc3

Use of the time functions relies on glibc modifications. A patch for
this can be found in my repository at [2] and I will soon post it to the glibc
mailing list.

[1]: http://git.linux-mips.org/cgit/mchandras/linux.git/log/?h=4.3-vdso
[2]: https://github.com/hwoarang/glibc/tree/2.22-vdso

Alex Smith (3):
  MIPS: Initial implementation of a VDSO
  irqchip: irq-mips-gic: Provide function to map GIC user section
  MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

 arch/mips/Kbuild |   1 +
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/abi.h  |   5 +-
 arch/mips/include/asm/clocksource.h  |  29 
 arch/mips/include/asm/elf.h  |   7 +
 arch/mips/include/asm/processor.h|   8 +-
 arch/mips/include/asm/vdso.h | 139 +++--
 arch/mips/include/uapi/asm/Kbuild|   2 +-
 arch/mips/include/uapi/asm/auxvec.h  |  17 ++
 arch/mips/kernel/csrc-r4k.c  |  44 ++
 arch/mips/kernel/signal.c|  12 +-
 arch/mips/kernel/signal32.c  |   7 +-
 arch/mips/kernel/signal_n32.c|   5 +-
 arch/mips/kernel/vdso.c  | 198 ++-
 arch/mips/vdso/.gitignore|   4 +
 arch/mips/vdso/Makefile  | 142 +
 arch/mips/vdso/elf.S |  68 
 arch/mips/vdso/genvdso.c | 294 +++
 arch/mips/vdso/genvdso.h | 188 ++
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/sigreturn.S   |  49 ++
 arch/mips/vdso/vdso.h|  84 ++
 arch/mips/vdso/vdso.lds.S| 103 
 drivers/clocksource/mips-gic-timer.c |   7 +-
 drivers/irqchip/irq-mips-gic.c   |  27 +++-
 include/linux/irqchip/mips-gic.h |  24 ++-
 26 files changed, 1572 insertions(+), 129 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/include/uapi/asm/auxvec.h
 create mode 100644 arch/mips/vdso/.gitignore
 create mode 100644 arch/mips/vdso/Makefile
 create mode 100644 arch/mips/vdso/elf.S
 create mode 100644 arch/mips/vdso/genvdso.c
 create mode 100644 arch/mips/vdso/genvdso.h
 create mode 100644 arch/mips/vdso/gettimeofday.c
 create mode 100644 arch/mips/vdso/sigreturn.S
 create mode 100644 arch/mips/vdso/vdso.h
 create mode 100644 arch/mips/vdso/vdso.lds.S

-- 
2.5.3

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[PATCH 3/3] MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.

When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.

When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.

This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.

A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):

 - Syscall:~31000 ns
 - VDSO (GIC): ~15000 ns
 - VDSO (CP0): ~9500 ns

[markos.chand...@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef]

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
 arch/mips/Kconfig|   5 +
 arch/mips/include/asm/clocksource.h  |  29 +
 arch/mips/include/asm/vdso.h |  68 +-
 arch/mips/kernel/csrc-r4k.c  |  44 +++
 arch/mips/kernel/vdso.c  |  62 +-
 arch/mips/vdso/Makefile  |   2 +-
 arch/mips/vdso/gettimeofday.c| 232 +++
 arch/mips/vdso/vdso.h|   9 ++
 arch/mips/vdso/vdso.lds.S|   3 +
 drivers/clocksource/mips-gic-timer.c |   7 +-
 10 files changed, 450 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/include/asm/clocksource.h
 create mode 100644 arch/mips/vdso/gettimeofday.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3aa5b0b4ef1..68f4f246887c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
+   select GENERIC_TIME_VSYSCALL
+   select ARCH_CLOCKSOURCE_DATA
 
 menu "Machine selection"
 
@@ -1036,6 +1038,9 @@ config CSRC_R4K
 config CSRC_SB1250
bool
 
+config MIPS_CLOCK_VSYSCALL
+   def_bool CSRC_R4K || CLKSRC_MIPS_GIC
+
 config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
diff --git a/arch/mips/include/asm/clocksource.h 
b/arch/mips/include/asm/clocksource.h
new file mode 100644
index ..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.sm...@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include 
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE0   /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K 1   /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC 2   /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource 
information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+   u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index db2d45be8f2e..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -13,6 +13,8 @@
 
 #include 
 
+#include 
+
 /**
  * struct mips_vdso_image - Details of a VDSO image.
  * @data: Pointer to VDSO image data (page-aligned).
@@ -53,18 +55,82 @@ extern struct mips_vdso_image vdso_image_n32;
 
 /**
  * union mips_vdso_data - Data provided by the kernel for the VDSO.
+ * @xtime_sec: Curre

[PATCH 2/3] irqchip: irq-mips-gic: Provide function to map GIC user section

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.

When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.

Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
 drivers/irqchip/irq-mips-gic.c   | 27 +--
 include/linux/irqchip/mips-gic.h | 24 ++--
 2 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16bb8a94..c995b199ca32 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,6 +30,7 @@ struct gic_pcpu_mask {
DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
 };
 
+static unsigned long gic_base_addr;
 static void __iomem *gic_base;
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static DEFINE_SPINLOCK(gic_lock);
@@ -301,6 +303,19 @@ int gic_get_c0_fdc_int(void)
  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 }
 
+int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
+unsigned long size)
+{
+   unsigned long pfn;
+
+   BUG_ON(!gic_present);
+   BUG_ON(size > USM_VISIBLE_SECTION_SIZE);
+
+   pfn = (gic_base_addr + USM_VISIBLE_SECTION_OFS) >> PAGE_SHIFT;
+   return io_remap_pfn_range(vma, base, pfn, size,
+ pgprot_noncached(PAGE_READONLY));
+}
+
 static void gic_handle_shared_int(bool chained)
 {
unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
@@ -783,14 +798,15 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-static void __init __gic_init(unsigned long gic_base_addr,
- unsigned long gic_addrspace_size,
+static void __init __gic_init(unsigned long base_addr,
+ unsigned long addrspace_size,
  unsigned int cpu_vec, unsigned int irqbase,
  struct device_node *node)
 {
unsigned int gicconfig;
 
-   gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
+   gic_base_addr = base_addr;
+   gic_base = ioremap_nocache(base_addr, addrspace_size);
 
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -847,11 +863,10 @@ static void __init __gic_init(unsigned long gic_base_addr,
gic_ipi_init();
 }
 
-void __init gic_init(unsigned long gic_base_addr,
-unsigned long gic_addrspace_size,
+void __init gic_init(unsigned long base_addr, unsigned long addrspace_size,
 unsigned int cpu_vec, unsigned int irqbase)
 {
-   __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
+   __gic_init(base_addr, addrspace_size, cpu_vec, irqbase, NULL);
 }
 
 static int __init gic_of_init(struct device_node *node,
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 4e6861605050..68f2e9539204 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -245,10 +245,14 @@
 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
 
+struct vm_area_struct;
+
+#ifdef CONFIG_MIPS_GIC
+
 extern unsigned int gic_present;
 
-extern void gic_init(unsigned long gic_base_addr,
-   unsigned long gic_addrspace_size, unsigned int cpu_vec,
+extern void gic_init(unsigned long base_addr,
+   unsigned long addrspace_size, unsigned int cpu_vec,
unsigned int irqbase);
 extern void gic_clocksource_init(unsigned int);
 extern cycle_t gic_read_count(void);
@@ -264,4 +268,20 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned 
int);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
+extern int gic_map_user_section(struct vm_area_struct *vma, unsigned long base,
+   unsigned long size);
+
+#else /* CONFIG_MIPS_GIC */
+
+#define gic_present0
+
+static inline int gic_map_user_section(struct vm_area_struct *vma,
+  unsigned long base, unsigned long size)
+{
+   /* Shouldn't be called. */
+   return -1;

[PATCH 1/3] MIPS: Initial implementation of a VDSO

[Markos Chandras]

From: Alex Smith <alex.sm...@imgtec.com>

Add an initial implementation of a proper (i.e. an ELF shared library)
VDSO. With this commit it does not export any symbols, it only replaces
the current signal return trampoline page. A later commit will add user
implementations of gettimeofday()/clock_gettime().

To support both new toolchains and old ones which don't generate ABI
flags section, we define its content manually and then use a tool
(genvdso) to patch up the section to have the correct name and type.
genvdso also extracts symbol offsets ({,rt_}sigreturn) needed by the
kernel, and generates a C file containing a "struct mips_vdso_image"
containing both the VDSO data and these offsets. This C file is
compiled into the kernel.

On 64-bit kernels we require a different VDSO for each supported ABI,
so we may build up to 3 different VDSOs. The VDSO to use is selected by
the mips_abi structure.

A kernel/user shared data page is created and mapped below the VDSO
image. This is currently empty, but will be used by the user time
function implementations which are added later.

[markos.chand...@imgtec.com:
- Add more comments
- Move abi detection in genvdso.h since it's the get_symbol function
that needs it.
- Add an R6 specific way to calculate the base address of VDSO in order
to avoid the branch instruction which affects performance.
- Do not patch .gnu.attributes since it's not needed for dynamic linking.
- Simplify Makefile a little bit.
- checkpatch fixes]

Cc: linux-kernel@vger.kernel.org
Cc: Matthew Fortune <matthew.fort...@imgtec.com>
Signed-off-by: Alex Smith <alex.sm...@imgtec.com>
Signed-off-by: Markos Chandras <markos.chand...@imgtec.com>
---
 arch/mips/Kbuild|   1 +
 arch/mips/include/asm/abi.h |   5 +-
 arch/mips/include/asm/elf.h |   7 +
 arch/mips/include/asm/processor.h   |   8 +-
 arch/mips/include/asm/vdso.h|  73 +++--
 arch/mips/include/uapi/asm/Kbuild   |   2 +-
 arch/mips/include/uapi/asm/auxvec.h |  17 +++
 arch/mips/kernel/signal.c   |  12 +-
 arch/mips/kernel/signal32.c |   7 +-
 arch/mips/kernel/signal_n32.c   |   5 +-
 arch/mips/kernel/vdso.c | 160 ++--
 arch/mips/vdso/.gitignore   |   4 +
 arch/mips/vdso/Makefile | 142 +
 arch/mips/vdso/elf.S|  68 +
 arch/mips/vdso/genvdso.c| 293 
 arch/mips/vdso/genvdso.h| 187 +++
 arch/mips/vdso/sigreturn.S  |  49 ++
 arch/mips/vdso/vdso.h   |  79 ++
 arch/mips/vdso/vdso.lds.S   | 100 
 19 files changed, 1095 insertions(+), 124 deletions(-)
 create mode 100644 arch/mips/include/uapi/asm/auxvec.h
 create mode 100644 arch/mips/vdso/.gitignore
 create mode 100644 arch/mips/vdso/Makefile
 create mode 100644 arch/mips/vdso/elf.S
 create mode 100644 arch/mips/vdso/genvdso.c
 create mode 100644 arch/mips/vdso/genvdso.h
 create mode 100644 arch/mips/vdso/sigreturn.S
 create mode 100644 arch/mips/vdso/vdso.h
 create mode 100644 arch/mips/vdso/vdso.lds.S

diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
index dd295335891a..5c3f688a5232 100644
--- a/arch/mips/Kbuild
+++ b/arch/mips/Kbuild
@@ -17,6 +17,7 @@ obj- := $(platform-)
 obj-y += kernel/
 obj-y += mm/
 obj-y += net/
+obj-y += vdso/
 
 ifdef CONFIG_KVM
 obj-y += kvm/
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 37f84078e78a..940760844e2f 100644
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -11,19 +11,20 @@
 
 #include 
 #include 
+#include 
 
 struct mips_abi {
int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
  struct pt_regs *regs, sigset_t *set);
-   const unsigned long signal_return_offset;
int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
 struct pt_regs *regs, sigset_t *set);
-   const unsigned long rt_signal_return_offset;
const unsigned long restart;
 
unsignedoff_sc_fpregs;
unsignedoff_sc_fpc_csr;
unsignedoff_sc_used_math;
+
+   struct mips_vdso_image *vdso;
 };
 
 #endif /* _ASM_ABI_H */
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 53b26933b12c..b01a6ff468e0 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -8,6 +8,7 @@
 #ifndef _ASM_ELF_H
 #define _ASM_ELF_H
 
+#include 
 #include 
 #include 
 
@@ -419,6 +420,12 @@ extern const char *__elf_platform;
 #define ELF_ET_DYN_BASE(TASK_SIZE / 3 * 2)
 #endif
 
+#define ARCH_DLINFO\
+do {   \
+   NEW_AUX_ENT(AT_SYSINFO_EHDR,\
+   (unsig

Re: [PATCH 2/2] MIPS: initialise MAARs on secondary CPUs

[Markos Chandras]

On 09/22/2015 08:08 PM, Paul Burton wrote:
> MAARs should be initialised on each CPU (or rather, core) in the system
> in order to achieve consistent behaviour & performance. Previously they
> have only been initialised on the boot CPU which leads to performance
> problems if tasks are later scheduled on a secondary CPU, particularly
> if those tasks make use of unaligned vector accesses where some CPUs
> don't handle any cases in hardware for non-speculative memory regions.
> Fix this by recording the MAAR configuration from the boot CPU and
> applying it to secondary CPUs as part of their bringup.
> 
> Reported-by: Doug Gilmore 
> Signed-off-by: Paul Burton 
> ---
> 
>  arch/mips/include/asm/maar.h |  9 +
>  arch/mips/kernel/smp.c   |  2 ++
>  arch/mips/mm/init.c  | 28 +---
>  3 files changed, 36 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/include/asm/maar.h b/arch/mips/include/asm/maar.h
> index b02891f..21d9607 100644
> --- a/arch/mips/include/asm/maar.h
> +++ b/arch/mips/include/asm/maar.h
> @@ -66,6 +66,15 @@ static inline void write_maar_pair(unsigned idx, 
> phys_addr_t lower,
>  }
>  
>  /**
> + * maar_init() - initialise MAARs
> + *
> + * Performs initialisation of MAARs for the current CPU, making use of the
> + * platforms implementation of platform_maar_init where necessary and
> + * duplicating the setup it provides on secondary CPUs.
> + */
> +extern void maar_init(void);
> +
> +/**
>   * struct maar_config - MAAR configuration data
>   * @lower:   The lowest address that the MAAR pair will affect. Must be
>   *   aligned to a 2^16 byte boundary.
> diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
> index a31896c..bd4385a 100644
> --- a/arch/mips/kernel/smp.c
> +++ b/arch/mips/kernel/smp.c
> @@ -42,6 +42,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  cpumask_t cpu_callin_map;/* Bitmask of started secondaries */
>  
> @@ -157,6 +158,7 @@ asmlinkage void start_secondary(void)
>   mips_clockevent_init();
>   mp_ops->init_secondary();
>   cpu_report();
> + maar_init();
>  

Hi,

This breaks the ip27_defconfig in both upstream-sfr and linux-next

arch/mips/built-in.o: In function `start_secondary':
(.text+0x123e4): undefined reference to `maar_init'
Makefile:944: recipe for target 'vmlinux' failed


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Re: [PATCH 2/2] MIPS: initialise MAARs on secondary CPUs

[Markos Chandras]

On 09/22/2015 08:08 PM, Paul Burton wrote:
> MAARs should be initialised on each CPU (or rather, core) in the system
> in order to achieve consistent behaviour & performance. Previously they
> have only been initialised on the boot CPU which leads to performance
> problems if tasks are later scheduled on a secondary CPU, particularly
> if those tasks make use of unaligned vector accesses where some CPUs
> don't handle any cases in hardware for non-speculative memory regions.
> Fix this by recording the MAAR configuration from the boot CPU and
> applying it to secondary CPUs as part of their bringup.
> 
> Reported-by: Doug Gilmore 
> Signed-off-by: Paul Burton 
> ---
> 
>  arch/mips/include/asm/maar.h |  9 +
>  arch/mips/kernel/smp.c   |  2 ++
>  arch/mips/mm/init.c  | 28 +---
>  3 files changed, 36 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/include/asm/maar.h b/arch/mips/include/asm/maar.h
> index b02891f..21d9607 100644
> --- a/arch/mips/include/asm/maar.h
> +++ b/arch/mips/include/asm/maar.h
> @@ -66,6 +66,15 @@ static inline void write_maar_pair(unsigned idx, 
> phys_addr_t lower,
>  }
>  
>  /**
> + * maar_init() - initialise MAARs
> + *
> + * Performs initialisation of MAARs for the current CPU, making use of the
> + * platforms implementation of platform_maar_init where necessary and
> + * duplicating the setup it provides on secondary CPUs.
> + */
> +extern void maar_init(void);
> +
> +/**
>   * struct maar_config - MAAR configuration data
>   * @lower:   The lowest address that the MAAR pair will affect. Must be
>   *   aligned to a 2^16 byte boundary.
> diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
> index a31896c..bd4385a 100644
> --- a/arch/mips/kernel/smp.c
> +++ b/arch/mips/kernel/smp.c
> @@ -42,6 +42,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  cpumask_t cpu_callin_map;/* Bitmask of started secondaries */
>  
> @@ -157,6 +158,7 @@ asmlinkage void start_secondary(void)
>   mips_clockevent_init();
>   mp_ops->init_secondary();
>   cpu_report();
> + maar_init();
>  

Hi,

This breaks the ip27_defconfig in both upstream-sfr and linux-next

arch/mips/built-in.o: In function `start_secondary':
(.text+0x123e4): undefined reference to `maar_init'
Makefile:944: recipe for target 'vmlinux' failed


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Re: [PATCH v2] MIPS: Fix console output for Fulong2e system

[Markos Chandras]

On 08/31/2015 05:19 AM, Guenter Roeck wrote:
> Commit 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
> made the number of UARTs dynamic if LEFI_FIRMWARE_INTERFACE is configured.
> Unfortunately, it did not initialize the number of UARTs if
> LEFI_FIRMWARE_INTERFACE is not configured. As a result, the Fulong2e
> system has no console.
> 
> Fixes: 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
> Acked-by: Huacai Chen 
> Signed-off-by: Guenter Roeck 
> ---

Tested-by: Markos Chandras 

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Re: [PATCH v2] MIPS: Fix console output for Fulong2e system

[Markos Chandras]

On 08/31/2015 05:19 AM, Guenter Roeck wrote:
> Commit 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
> made the number of UARTs dynamic if LEFI_FIRMWARE_INTERFACE is configured.
> Unfortunately, it did not initialize the number of UARTs if
> LEFI_FIRMWARE_INTERFACE is not configured. As a result, the Fulong2e
> system has no console.
> 
> Fixes: 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
> Acked-by: Huacai Chen <che...@lemote.com>
> Signed-off-by: Guenter Roeck <li...@roeck-us.net>
> ---

Tested-by: Markos Chandras <markos.chand...@imgtec.com>

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Re: [PATCH 6/6] MIPS: net: BPF: Introduce BPF ASM helpers

[Markos Chandras]

On Thu, Aug 13, 2015 at 10:42:46PM +0200, Aurelien Jarno wrote:
> 
> This patch relies on R2 instructions, and thus the Linux kernel fails to
> build when targetting non-R2 CPUs. See for example:
> 
> https://buildd.debian.org/status/fetch.php?pkg=linux=mipsel=4.2%7Erc6-1%7Eexp1=143948
> 
> -- 
> Aurelien Jarno  GPG: 4096R/1DDD8C9B
> aurel...@aurel32.net http://www.aurel32.net
Hi,

I think Ralf may have a fix for R1 cores but I am not sure about the status of
that patch. Ralf?

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Re: [PATCH 6/6] MIPS: net: BPF: Introduce BPF ASM helpers

[Markos Chandras]

On Thu, Aug 13, 2015 at 10:42:46PM +0200, Aurelien Jarno wrote:
 
 This patch relies on R2 instructions, and thus the Linux kernel fails to
 build when targetting non-R2 CPUs. See for example:
 
 https://buildd.debian.org/status/fetch.php?pkg=linuxarch=mipselver=4.2%7Erc6-1%7Eexp1stamp=143948
 
 -- 
 Aurelien Jarno  GPG: 4096R/1DDD8C9B
 aurel...@aurel32.net http://www.aurel32.net
Hi,

I think Ralf may have a fix for R1 cores but I am not sure about the status of
that patch. Ralf?

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Re: [PATCH] MIPS: R6: emulation of PC-relative instructions

[Markos Chandras]

Hi,

On Wed, Aug 05, 2015 at 04:53:43PM -0700, Leonid Yegoshin wrote:
> MIPS R6 has 6 new PC-relative instructions: LWUPC, LWPC, LDPC, ADDIUPC, ALUIPC
> and AUIPC. These instructions can be placed in BD-slot of BC1* branch
> instruction and FPU may be not available, which requires emulation of these
> instructions.
> 
> However, the traditional way to emulate that is via filling some emulation 
> block
> in stack or special area and jump to it. This is not suitable for PC-relative
> instructions.
> 
> So, this patch introduces a universal emulation of that instructions directly 
> by
> kernel emulator.
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  arch/mips/include/uapi/asm/inst.h |   42 ++-
>  arch/mips/kernel/mips-r2-to-r6-emul.c |3 +
>  arch/mips/math-emu/dsemul.c   |   94 
> +
>  3 files changed, 138 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/include/uapi/asm/inst.h 
> b/arch/mips/include/uapi/asm/inst.h
> index 3dce80e67948..6253197d4908 100644
> --- a/arch/mips/include/uapi/asm/inst.h
> +++ b/arch/mips/include/uapi/asm/inst.h
> @@ -33,7 +33,7 @@ enum major_op {
>   sdl_op, sdr_op, swr_op, cache_op,
>   ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
>   lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
> - sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
> + sc_op, swc1_op, swc2_op, balc6_op = swc2_op, pcrel_op,
>   scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
>  };
>  
>   if (nir) {
>   err = mipsr6_emul(regs, nir);
>   if (err > 0) {
> + regs->cp0_epc = nepc;

Does this change belog to this patch? If so why? Maybe a comment would help?
It does feel like it fixes a different problem but I haven't read your patch in 
depth.

>   err = mips_dsemul(regs, nir, cpc, epc, 
> r31);
>   if (err == SIGILL)
>   err = SIGEMT;
> @@ -1082,6 +1083,7 @@ repeat:
>   if (nir) {
>   err = mipsr6_emul(regs, nir);
>   if (err > 0) {
> + regs->cp0_epc = nepc;
likewise

>   err = mips_dsemul(regs, nir, cpc, epc, 
> r31);
>   if (err == SIGILL)
>   err = SIGEMT;
> @@ -1149,6 +1151,7 @@ repeat:
>   if (nir) {
>   err = mipsr6_emul(regs, nir);
>   if (err > 0) {
> + regs->cp0_epc = nepc;
likewise

>   err = mips_dsemul(regs, nir, cpc, epc, r31);
>   if (err == SIGILL)
>   err = SIGEMT;
> diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
> index eac76a09d822..9b388aaf594f 100644
> --- a/arch/mips/math-emu/dsemul.c
> +++ b/arch/mips/math-emu/dsemul.c
> @@ -8,6 +8,95 @@
>  
>  #include "ieee754.h"
>  
> +#ifdef CONFIG_CPU_MIPSR6

Can we simply avoid the if/def for R6 please? Just leave this function as is and
use if(cpu_has_mips_r6) when calling it. If you can't do that, please explain
why.

> +
> +static int mipsr6_pc(struct pt_regs *regs, mips_instruction inst, unsigned 
> long cpc,
> + unsigned long bpc, unsigned long r31)
> +{
> + union mips_instruction ir = (union mips_instruction)inst;
> + register unsigned long vaddr;
> + unsigned int val;
> + int err = SIGILL;
> +
> + if (ir.rel_format.opcode != pcrel_op)
> + return SIGILL;
> +
> + switch (ir.rel_format.op) {
> + case addiupc_op:
> + vaddr = regs->cp0_epc + (ir.rel_format.simmediate << 2);
> + if (config_enabled(CONFIG_64BIT) && !(regs->cp0_status & 
> ST0_UX))
> + __asm__ __volatile__("sll %0, %0, 0":"+"(vaddr)::);
> + regs->regs[ir.rel_format.rs] = vaddr;
> + return 0;
> +#ifdef CONFIG_CPU_MIPS64

Could you use cpu_has_mips64 and avoid the if/def and return SIGILL if it is not
true?

Same thing for the rest of this patch.

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Re: [PATCH] MIPS: R6: emulation of PC-relative instructions

[Markos Chandras]

Hi,

On Wed, Aug 05, 2015 at 04:53:43PM -0700, Leonid Yegoshin wrote:
 MIPS R6 has 6 new PC-relative instructions: LWUPC, LWPC, LDPC, ADDIUPC, ALUIPC
 and AUIPC. These instructions can be placed in BD-slot of BC1* branch
 instruction and FPU may be not available, which requires emulation of these
 instructions.
 
 However, the traditional way to emulate that is via filling some emulation 
 block
 in stack or special area and jump to it. This is not suitable for PC-relative
 instructions.
 
 So, this patch introduces a universal emulation of that instructions directly 
 by
 kernel emulator.
 
 Signed-off-by: Leonid Yegoshin leonid.yegos...@imgtec.com
 ---
  arch/mips/include/uapi/asm/inst.h |   42 ++-
  arch/mips/kernel/mips-r2-to-r6-emul.c |3 +
  arch/mips/math-emu/dsemul.c   |   94 
 +
  3 files changed, 138 insertions(+), 1 deletion(-)
 
 diff --git a/arch/mips/include/uapi/asm/inst.h 
 b/arch/mips/include/uapi/asm/inst.h
 index 3dce80e67948..6253197d4908 100644
 --- a/arch/mips/include/uapi/asm/inst.h
 +++ b/arch/mips/include/uapi/asm/inst.h
 @@ -33,7 +33,7 @@ enum major_op {
   sdl_op, sdr_op, swr_op, cache_op,
   ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
   lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
 - sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
 + sc_op, swc1_op, swc2_op, balc6_op = swc2_op, pcrel_op,
   scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
  };
  
   if (nir) {
   err = mipsr6_emul(regs, nir);
   if (err  0) {
 + regs-cp0_epc = nepc;

Does this change belog to this patch? If so why? Maybe a comment would help?
It does feel like it fixes a different problem but I haven't read your patch in 
depth.

   err = mips_dsemul(regs, nir, cpc, epc, 
 r31);
   if (err == SIGILL)
   err = SIGEMT;
 @@ -1082,6 +1083,7 @@ repeat:
   if (nir) {
   err = mipsr6_emul(regs, nir);
   if (err  0) {
 + regs-cp0_epc = nepc;
likewise

   err = mips_dsemul(regs, nir, cpc, epc, 
 r31);
   if (err == SIGILL)
   err = SIGEMT;
 @@ -1149,6 +1151,7 @@ repeat:
   if (nir) {
   err = mipsr6_emul(regs, nir);
   if (err  0) {
 + regs-cp0_epc = nepc;
likewise

   err = mips_dsemul(regs, nir, cpc, epc, r31);
   if (err == SIGILL)
   err = SIGEMT;
 diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
 index eac76a09d822..9b388aaf594f 100644
 --- a/arch/mips/math-emu/dsemul.c
 +++ b/arch/mips/math-emu/dsemul.c
 @@ -8,6 +8,95 @@
  
  #include ieee754.h
  
 +#ifdef CONFIG_CPU_MIPSR6

Can we simply avoid the if/def for R6 please? Just leave this function as is and
use if(cpu_has_mips_r6) when calling it. If you can't do that, please explain
why.

 +
 +static int mipsr6_pc(struct pt_regs *regs, mips_instruction inst, unsigned 
 long cpc,
 + unsigned long bpc, unsigned long r31)
 +{
 + union mips_instruction ir = (union mips_instruction)inst;
 + register unsigned long vaddr;
 + unsigned int val;
 + int err = SIGILL;
 +
 + if (ir.rel_format.opcode != pcrel_op)
 + return SIGILL;
 +
 + switch (ir.rel_format.op) {
 + case addiupc_op:
 + vaddr = regs-cp0_epc + (ir.rel_format.simmediate  2);
 + if (config_enabled(CONFIG_64BIT)  !(regs-cp0_status  
 ST0_UX))
 + __asm__ __volatile__(sll %0, %0, 0:+r(vaddr)::);
 + regs-regs[ir.rel_format.rs] = vaddr;
 + return 0;
 +#ifdef CONFIG_CPU_MIPS64

Could you use cpu_has_mips64 and avoid the if/def and return SIGILL if it is not
true?

Same thing for the rest of this patch.

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Re: [4.1,013/123] MIPS: c-r4k: Fix cache flushing for MT cores

[Markos Chandras]

On Mon, Aug 10, 2015 at 12:12:05PM -0700, Leonid Yegoshin wrote:
> On 08/10/2015 11:49 AM, gre...@linuxfoundation.org wrote:
> > On Mon, Aug 10, 2015 at 11:36:34AM -0700, Leonid Yegoshin wrote:
> >>
> > So, this is broken in Linus's tree too?
> 
> Yes.
> 
> >Or is it fixed there, and if
> > so, what is the git commit id?
> 
> There is no an accepted fix. My old patch is in
> 
> https://git.linux-mips.org/cgit/yegoshin/mips.git/commit/?id=98f6c462eb5319a4dcb3830f902c48141f38cd12
> 
> It was a precursor for my EVA set of patches since2.6.35.9 but was never 
> accepted and was lost during redesign of EVA by Markos.
> 
> - Leonid.
> 

I hope you realize that blocking this patch from the stable trees does not
actually fix the problem. The patch may not be perfect but it's better than what
we had before.

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Re: [4.1,013/123] MIPS: c-r4k: Fix cache flushing for MT cores

[Markos Chandras]

On Mon, Aug 10, 2015 at 12:12:05PM -0700, Leonid Yegoshin wrote:
 On 08/10/2015 11:49 AM, gre...@linuxfoundation.org wrote:
  On Mon, Aug 10, 2015 at 11:36:34AM -0700, Leonid Yegoshin wrote:
 
  So, this is broken in Linus's tree too?
 
 Yes.
 
 Or is it fixed there, and if
  so, what is the git commit id?
 
 There is no an accepted fix. My old patch is in
 
 https://git.linux-mips.org/cgit/yegoshin/mips.git/commit/?id=98f6c462eb5319a4dcb3830f902c48141f38cd12
 
 It was a precursor for my EVA set of patches since2.6.35.9 but was never 
 accepted and was lost during redesign of EVA by Markos.
 
 - Leonid.
 

I hope you realize that blocking this patch from the stable trees does not
actually fix the problem. The patch may not be perfect but it's better than what
we had before.

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Re: [PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

On 06/04/2015 05:49 PM, Alexei Starovoitov wrote:
> On 6/4/15 3:56 AM, Markos Chandras wrote:
>> Here are some fixes for MIPS/BPF. The first 5 patches do some cleanup
>> and lay the groundwork for the final one which introduces assembly
>> helpers
>> for MIPS and MIPS64. The goal is to speed up certain operations that do
>> not need to go through the common C functions. This also makes the
>> test_bpf
>> testsuite happy with all 60 tests passing. This is based in 4.1-rc6.
> 
> looks like these patches actually fix two real bugs, right?
> If so, I think you probably want them in 'net' tree ?

I was thinking to have them in the MIPS tree to be honest. The original
MIPS/BPF went via the MIPS tree as well. It also makes it easier for me
to work with Ralf on minor fixes, merge conflicts etc.

> 
> Different arch maintainers take different stance towards bpf jit
> changes. x86, arm and s390 are ok with them going through Dave's trees,
> since often there are dependencies on bpf core parts.
> So please state clearly what tree you want these patches to go in.
> 
> btw, in the net-next tree bpf testsuite has 246 tests and the last
> ten are very stressful for JITs.

Interesting. Thanks. I will rebase my tree shortly after 4.2-rc1 then
and run the testsuite again. I will post a v2 if I spot more problems
with it.

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Re: [PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

On 06/04/2015 07:40 PM, David Miller wrote:
> 
> I think your Subject meant to say "fixes for 4.2" right?
> 
> Because we're currently finishing up 4.1.x and the next merge
> window will be for 4.2.x
> 
Hi David,

Ralf only accepts patches for MIPS 4.2 that have been posted before
4.1-rc5. This is posted nearly before 4.1-rc7 so it's likely to go to
4.3 based on Ralf's policy. Unless of course he wants to merge that to
4.2 which would be nice of course.

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Re: [PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

On 06/04/2015 05:49 PM, Alexei Starovoitov wrote:
 On 6/4/15 3:56 AM, Markos Chandras wrote:
 Here are some fixes for MIPS/BPF. The first 5 patches do some cleanup
 and lay the groundwork for the final one which introduces assembly
 helpers
 for MIPS and MIPS64. The goal is to speed up certain operations that do
 not need to go through the common C functions. This also makes the
 test_bpf
 testsuite happy with all 60 tests passing. This is based in 4.1-rc6.
 
 looks like these patches actually fix two real bugs, right?
 If so, I think you probably want them in 'net' tree ?

I was thinking to have them in the MIPS tree to be honest. The original
MIPS/BPF went via the MIPS tree as well. It also makes it easier for me
to work with Ralf on minor fixes, merge conflicts etc.

 
 Different arch maintainers take different stance towards bpf jit
 changes. x86, arm and s390 are ok with them going through Dave's trees,
 since often there are dependencies on bpf core parts.
 So please state clearly what tree you want these patches to go in.
 
 btw, in the net-next tree bpf testsuite has 246 tests and the last
 ten are very stressful for JITs.

Interesting. Thanks. I will rebase my tree shortly after 4.2-rc1 then
and run the testsuite again. I will post a v2 if I spot more problems
with it.

-- 
markos
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Re: [PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

On 06/04/2015 07:40 PM, David Miller wrote:
 
 I think your Subject meant to say fixes for 4.2 right?
 
 Because we're currently finishing up 4.1.x and the next merge
 window will be for 4.2.x
 
Hi David,

Ralf only accepts patches for MIPS 4.2 that have been posted before
4.1-rc5. This is posted nearly before 4.1-rc7 so it's likely to go to
4.3 based on Ralf's policy. Unless of course he wants to merge that to
4.2 which would be nice of course.

-- 
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[PATCH 1/6] MIPS: net: BPF: Free up some callee-saved registers

[Markos Chandras]

Move the two scratch registers from s0 and s1 to t4 and t5 in order
to free up some callee-saved registers. We will use these callee-saved
registers to store some permanent data on them in a subsequent patch.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
 arch/mips/net/bpf_jit.c | 35 +++
 arch/mips/net/bpf_jit.h |  2 ++
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 5d6139390bf8..850b08ee3fab 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -29,9 +29,6 @@
 
 /* ABI
  *
- * s0  1st scratch register
- * s1  2nd scratch register
- * s2  offset register
  * s3  BPF register A
  * s4  BPF register X
  * s5  *skb
@@ -88,13 +85,13 @@
  * any of the $s0-$s6 registers will only be preserved if
  * they are going to actually be used.
  */
-#define r_s0   MIPS_R_S0 /* scratch reg 1 */
-#define r_s1   MIPS_R_S1 /* scratch reg 2 */
 #define r_off  MIPS_R_S2
 #define r_AMIPS_R_S3
 #define r_XMIPS_R_S4
 #define r_skb  MIPS_R_S5
 #define r_MMIPS_R_S6
+#define r_s0   MIPS_R_T4 /* scratch reg 1 */
+#define r_s1   MIPS_R_T5 /* scratch reg 2 */
 #define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
 #define r_tmp  MIPS_R_T7 /* No need to preserve this */
 #define r_zero MIPS_R_ZERO
@@ -108,8 +105,6 @@
 #define SEEN_SREG_SFT  (BPF_MEMWORDS + 1)
 #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT)
 #define SEEN_SREG(x)   (SEEN_SREG_BASE << (x))
-#define SEEN_S0SEEN_SREG(0)
-#define SEEN_S1SEEN_SREG(1)
 #define SEEN_OFF   SEEN_SREG(2)
 #define SEEN_A SEEN_SREG(3)
 #define SEEN_X SEEN_SREG(4)
@@ -817,7 +812,7 @@ load_common:
   b_imm(prog->len, ctx), ctx);
emit_reg_move(r_ret, r_zero, ctx);
 
-   ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
+   ctx->flags |= SEEN_CALL | SEEN_OFF |
SEEN_SKB | SEEN_A;
 
emit_load_func(r_s0, (ptr)load_func[load_order],
@@ -883,7 +878,7 @@ load_ind:
return -ENOTSUPP;
 
/* X <- 4 * (P[k:1] & 0xf) */
-   ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
+   ctx->flags |= SEEN_X | SEEN_CALL | SEEN_SKB;
/* Load offset to a1 */
emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
/*
@@ -947,7 +942,7 @@ load_ind:
case BPF_ALU | BPF_MUL | BPF_K:
/* A *= K */
/* Load K to scratch register before MUL */
-   ctx->flags |= SEEN_A | SEEN_S0;
+   ctx->flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_mul(r_A, r_A, r_s0, ctx);
break;
@@ -965,7 +960,7 @@ load_ind:
emit_srl(r_A, r_A, k, ctx);
break;
}
-   ctx->flags |= SEEN_A | SEEN_S0;
+   ctx->flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_div(r_A, r_s0, ctx);
break;
@@ -975,7 +970,7 @@ load_ind:
ctx->flags |= SEEN_A;
emit_jit_reg_move(r_A, r_zero, ctx);
} else {
-   ctx->flags |= SEEN_A | SEEN_S0;
+   ctx->flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_mod(r_A, r_s0, ctx);
}
@@ -1089,10 +1084,10 @@ jmp_cmp:
if ((condt & MIPS_COND_GE) ||
(condt & MIPS_COND_GT)) {
if (condt & MIPS_COND_K) { /* K */
-   ctx->flags |= SEEN_S0 | SEEN_A;
+   ctx->flags |= SEEN_A;
emit_sltiu(r_s0, r_A, k, ctx);
} else { /* X */
-   ctx->flags |= SEEN_S0 | SEEN_A |
+   ctx->flags |= SEEN_A |
SEEN_X;
emit_sltu(r_s0, r_A, r_X, ctx);
}
@@ -1104,7 +1099,7 @@ jmp_cmp:
  

[PATCH 3/6] MIPS: net: BPF: Fix stack pointer allocation

[Markos Chandras]

Fix stack pointer offset which could potentially corrupt
argument registers in the previous frame. The calculated offset
reflects the size of all the registers we need to preserve so there
is no need for this erroneous subtraction.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
 arch/mips/net/bpf_jit.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 56e0e8e9674d..84cd09ba230a 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -676,11 +676,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
sp_off += config_enabled(CONFIG_64BIT) ?
(ARGS_USED_BY_JIT + 1) * SZREG : SZREG;
 
-   /*
-* Subtract the bytes for the last registers since we only care about
-* the location on the stack pointer.
-*/
-   return sp_off - SZREG;
+   return sp_off;
 }
 
 static void build_prologue(struct jit_ctx *ctx)
-- 
2.4.2

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[PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

Hi,

Here are some fixes for MIPS/BPF. The first 5 patches do some cleanup
and lay the groundwork for the final one which introduces assembly helpers
for MIPS and MIPS64. The goal is to speed up certain operations that do
not need to go through the common C functions. This also makes the test_bpf
testsuite happy with all 60 tests passing. This is based in 4.1-rc6.

The patchset is also available in my git tree.

https://github.com/hwoarang/linux/tree/4.3-bpf

The last patch also contains performance results along with the relevant
scripts and data used for the analysis.

Markos Chandras (6):
  MIPS: net: BPF: Free up some callee-saved registers
  MIPS: net: BPF: Replace RSIZE with SZREG
  MIPS: net: BPF: Fix stack pointer allocation
  MIPS: net: BPF: Move register definition to the BPF header
  MIPS: net: BPF: Use BPF register names to describe the ABI
  MIPS: net: BPF: Introduce BPF ASM helpers

 arch/mips/net/Makefile  |   2 +-
 arch/mips/net/bpf_jit.c | 268 
 arch/mips/net/bpf_jit.h |  42 ++-
 arch/mips/net/bpf_jit_asm.S | 238 +++
 4 files changed, 350 insertions(+), 200 deletions(-)
 create mode 100644 arch/mips/net/bpf_jit_asm.S

-- 
2.4.2

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[PATCH 2/6] MIPS: net: BPF: Replace RSIZE with SZREG

[Markos Chandras]

The RSZIE was used to determine the register width but MIPS
already defines SZREG so use that instead.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
 arch/mips/net/bpf_jit.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 850b08ee3fab..56e0e8e9674d 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -60,7 +61,6 @@
  * 
  */
 
-#define RSIZE  (sizeof(unsigned long))
 #define ptr typeof(unsigned long)
 
 /* ABI specific return values */
@@ -576,12 +576,12 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* Argument save area */
if (config_enabled(CONFIG_64BIT))
/* Bottom of current frame */
-   real_off = align_sp(offset) - RSIZE;
+   real_off = align_sp(offset) - SZREG;
else
/* Top of previous frame */
-   real_off = align_sp(offset) + RSIZE;
+   real_off = align_sp(offset) + SZREG;
emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
+   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
 
real_off = 0;
}
@@ -592,7 +592,7 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned 
offset)
if ((sflags >> i) & 0x1) {
emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
 ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
i++;
tmp_flags >>= 1;
@@ -601,13 +601,13 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* save return address */
if (ctx->flags & SEEN_CALL) {
emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
 
/* Setup r_M leaving the alignment gap if necessary */
if (ctx->flags & SEEN_MEM) {
-   if (real_off % (RSIZE * 2))
-   real_off += RSIZE;
+   if (real_off % (SZREG * 2))
+   real_off += SZREG;
emit_long_instr(ctx, ADDIU, r_M, r_sp, real_off);
}
 }
@@ -621,12 +621,12 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
if (ctx->flags & SEEN_CALL) {
if (config_enabled(CONFIG_64BIT))
/* Bottom of current frame */
-   real_off = align_sp(offset) - RSIZE;
+   real_off = align_sp(offset) - SZREG;
else
/* Top of previous frame */
-   real_off = align_sp(offset) + RSIZE;
+   real_off = align_sp(offset) + SZREG;
emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
+   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
 
real_off = 0;
}
@@ -638,7 +638,7 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
if ((sflags >> i) & 0x1) {
emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
i++;
tmp_flags >>= 1;
@@ -658,7 +658,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
 
 
/* How may s* regs do we need to preserved? */
-   sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE;
+   sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * SZREG;
 
if (ctx->flags & SEEN_MEM)
sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
@@ -674,13 +674,13 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
 * this space ourselves. We need to preserve $ra as well.
 */
sp_off += config_enabled(CONFIG_64BIT) ?
-   (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
+   (ARGS_USED_BY_JIT + 1) * SZREG : SZREG;
 
/*
 * Subtract the bytes for the last registers since we only care about
 * the location on the stack pointer.
 */
-   return sp_off - RSIZE;
+   return sp_off - SZREG;

[PATCH 5/6] MIPS: net: BPF: Use BPF register names to describe the ABI

[Markos Chandras]

Use the BPF register names instead of the arch register names to
document how the ABI is structured.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
 arch/mips/net/bpf_jit.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 954df295f945..f0db4f8310b2 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -30,10 +30,10 @@
 
 /* ABI
  *
- * s3  BPF register A
- * s4  BPF register X
- * s5  *skb
- * s6  *scratch memory
+ * r_A BPF register A
+ * r_X BPF register X
+ * r_skb   *skb
+ * r_M *scratch memory
  *
  * On entry (*bpf_func)(*skb, *filter)
  * a0 = MIPS_R_A0 = skb;
-- 
2.4.2

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[PATCH 4/6] MIPS: net: BPF: Move register definition to the BPF header

[Markos Chandras]

The registers will be used by a subsequent patch introducing
ASM helpers so move them to a common header.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
 arch/mips/net/bpf_jit.c | 35 ---
 arch/mips/net/bpf_jit.h | 35 +++
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 84cd09ba230a..954df295f945 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -63,41 +63,6 @@
 
 #define ptr typeof(unsigned long)
 
-/* ABI specific return values */
-#ifdef CONFIG_32BIT /* O32 */
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define r_err  MIPS_R_V1
-#define r_val  MIPS_R_V0
-#else /* CONFIG_CPU_LITTLE_ENDIAN */
-#define r_err  MIPS_R_V0
-#define r_val  MIPS_R_V1
-#endif
-#else /* N64 */
-#define r_err  MIPS_R_V0
-#define r_val  MIPS_R_V0
-#endif
-
-#define r_ret  MIPS_R_V0
-
-/*
- * Use 2 scratch registers to avoid pipeline interlocks.
- * There is no overhead during epilogue and prologue since
- * any of the $s0-$s6 registers will only be preserved if
- * they are going to actually be used.
- */
-#define r_off  MIPS_R_S2
-#define r_AMIPS_R_S3
-#define r_XMIPS_R_S4
-#define r_skb  MIPS_R_S5
-#define r_MMIPS_R_S6
-#define r_s0   MIPS_R_T4 /* scratch reg 1 */
-#define r_s1   MIPS_R_T5 /* scratch reg 2 */
-#define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
-#define r_tmp  MIPS_R_T7 /* No need to preserve this */
-#define r_zero MIPS_R_ZERO
-#define r_sp   MIPS_R_SP
-#define r_ra   MIPS_R_RA
-
 #define SCRATCH_OFF(k) (4 * (k))
 
 /* JIT flags */
diff --git a/arch/mips/net/bpf_jit.h b/arch/mips/net/bpf_jit.h
index f9b5a4d3dbf4..3afa7a6d81b3 100644
--- a/arch/mips/net/bpf_jit.h
+++ b/arch/mips/net/bpf_jit.h
@@ -43,4 +43,39 @@
 #define MIPS_COND_X(0x1 << 5)
 #define MIPS_COND_K(0x1 << 6)
 
+/* ABI specific return values */
+#ifdef CONFIG_32BIT /* O32 */
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define r_err  MIPS_R_V1
+#define r_val  MIPS_R_V0
+#else /* CONFIG_CPU_LITTLE_ENDIAN */
+#define r_err  MIPS_R_V0
+#define r_val  MIPS_R_V1
+#endif
+#else /* N64 */
+#define r_err  MIPS_R_V0
+#define r_val  MIPS_R_V0
+#endif
+
+#define r_ret  MIPS_R_V0
+
+/*
+ * Use 2 scratch registers to avoid pipeline interlocks.
+ * There is no overhead during epilogue and prologue since
+ * any of the $s0-$s6 registers will only be preserved if
+ * they are going to actually be used.
+ */
+#define r_off  MIPS_R_S2
+#define r_AMIPS_R_S3
+#define r_XMIPS_R_S4
+#define r_skb  MIPS_R_S5
+#define r_MMIPS_R_S6
+#define r_s0   MIPS_R_T4 /* scratch reg 1 */
+#define r_s1   MIPS_R_T5 /* scratch reg 2 */
+#define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
+#define r_tmp  MIPS_R_T7 /* No need to preserve this */
+#define r_zero MIPS_R_ZERO
+#define r_sp   MIPS_R_SP
+#define r_ra   MIPS_R_RA
+
 #endif /* BPF_JIT_MIPS_OP_H */
-- 
2.4.2

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[PATCH 6/6] MIPS: net: BPF: Introduce BPF ASM helpers

[Markos Chandras]

This commit introduces BPF ASM helpers for MIPS and MIPS64 kernels.
The purpose of this patch is to twofold:

1) We are now able to handle negative offsets instead of either
falling back to the interpreter or to simply not do anything and
bail out.

2) Optimize reads from the packet header instead of calling the C
helpers

Because of this patch, we are now able to get rid of quite a bit of
code in the JIT generation process by using MIPS optimized assembly
code. The new assembly code makes the test_bpf testsuite happy with
all 60 test passing successfully compared to the previous
implementation where 2 tests were failing.
Doing some basic analysis in the results between the old
implementation and the new one we can obtain the following
summary running current mainline on an ER8 board (+/- 30us delta is
ignored to prevent noise from kernel scheduling or IRQ latencies):

Summary: 22 tests are faster, 7 are slower and 47 saw no improvement

with the most notable improvement being the tcpdump tests. The 7 tests
that seem to be a bit slower is because they all follow the slow path
(bpf_internal_load_pointer_neg_helper) which is meant to be slow so
that's not a problem.

Cc: net...@vger.kernel.org
Cc: "David S. Miller" 
Cc: Alexei Starovoitov 
Cc: Daniel Borkmann 
Cc: Hannes Frederic Sowa 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras 
---
I have uploaded the script and the bpf result files in my LMO webspace
in case you want to have a look. I didn't paste them in here because they
are nearly 200 lines. Simply download all 3 files and run './bpf_analysis.py'

http://www.linux-mips.org/~mchandras/bpf/
---
 arch/mips/net/Makefile  |   2 +-
 arch/mips/net/bpf_jit.c | 174 +---
 arch/mips/net/bpf_jit.h |  33 +++---
 arch/mips/net/bpf_jit_asm.S | 238 
 4 files changed, 302 insertions(+), 145 deletions(-)
 create mode 100644 arch/mips/net/bpf_jit_asm.S

diff --git a/arch/mips/net/Makefile b/arch/mips/net/Makefile
index ae74b3a91f5c..8c2771401f54 100644
--- a/arch/mips/net/Makefile
+++ b/arch/mips/net/Makefile
@@ -1,3 +1,3 @@
 # MIPS networking code
 
-obj-$(CONFIG_BPF_JIT) += bpf_jit.o
+obj-$(CONFIG_BPF_JIT) += bpf_jit.o bpf_jit_asm.o
diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index f0db4f8310b2..0c4a133f6216 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -29,11 +29,14 @@
 #include "bpf_jit.h"
 
 /* ABI
- *
+ * r_skb_hlSKB header length
+ * r_data  SKB data pointer
+ * r_off   Offset
  * r_A BPF register A
  * r_X BPF register X
  * r_skb   *skb
  * r_M *scratch memory
+ * r_skb_len   SKB length
  *
  * On entry (*bpf_func)(*skb, *filter)
  * a0 = MIPS_R_A0 = skb;
@@ -75,6 +78,8 @@
 #define SEEN_X SEEN_SREG(4)
 #define SEEN_SKB   SEEN_SREG(5)
 #define SEEN_MEM   SEEN_SREG(6)
+/* SEEN_SK_DATA also implies skb_hl an skb_len */
+#define SEEN_SKB_DATA  (SEEN_SREG(7) | SEEN_SREG(1) | SEEN_SREG(0))
 
 /* Arguments used by JIT */
 #define ARGS_USED_BY_JIT   2 /* only applicable to 64-bit */
@@ -537,20 +542,6 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* Adjust the stack pointer */
emit_stack_offset(-align_sp(offset), ctx);
 
-   if (ctx->flags & SEEN_CALL) {
-   /* Argument save area */
-   if (config_enabled(CONFIG_64BIT))
-   /* Bottom of current frame */
-   real_off = align_sp(offset) - SZREG;
-   else
-   /* Top of previous frame */
-   real_off = align_sp(offset) + SZREG;
-   emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
-
-   real_off = 0;
-   }
-
tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
/* sflags is essentially a bitmap */
while (tmp_flags) {
@@ -583,19 +574,6 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
int i, real_off = 0;
u32 sflags, tmp_flags;
 
-   if (ctx->flags & SEEN_CALL) {
-   if (config_enabled(CONFIG_64BIT))
-   /* Bottom of current frame */
-   real_off = align_sp(offset) - SZREG;
-   else
-   /* Top of previous frame */
-   real_off = align_sp(offset) + SZREG;
-   emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
-
-   real_off = 0;
-   }
-
tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
/* sflags is a bitmap */
i = 0;
@@ -629,17 +607,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
sp_off += 4 * BPF_MEMWORDS; /*

[PATCH 6/6] MIPS: net: BPF: Introduce BPF ASM helpers

[Markos Chandras]

This commit introduces BPF ASM helpers for MIPS and MIPS64 kernels.
The purpose of this patch is to twofold:

1) We are now able to handle negative offsets instead of either
falling back to the interpreter or to simply not do anything and
bail out.

2) Optimize reads from the packet header instead of calling the C
helpers

Because of this patch, we are now able to get rid of quite a bit of
code in the JIT generation process by using MIPS optimized assembly
code. The new assembly code makes the test_bpf testsuite happy with
all 60 test passing successfully compared to the previous
implementation where 2 tests were failing.
Doing some basic analysis in the results between the old
implementation and the new one we can obtain the following
summary running current mainline on an ER8 board (+/- 30us delta is
ignored to prevent noise from kernel scheduling or IRQ latencies):

Summary: 22 tests are faster, 7 are slower and 47 saw no improvement

with the most notable improvement being the tcpdump tests. The 7 tests
that seem to be a bit slower is because they all follow the slow path
(bpf_internal_load_pointer_neg_helper) which is meant to be slow so
that's not a problem.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
I have uploaded the script and the bpf result files in my LMO webspace
in case you want to have a look. I didn't paste them in here because they
are nearly 200 lines. Simply download all 3 files and run './bpf_analysis.py'

http://www.linux-mips.org/~mchandras/bpf/
---
 arch/mips/net/Makefile  |   2 +-
 arch/mips/net/bpf_jit.c | 174 +---
 arch/mips/net/bpf_jit.h |  33 +++---
 arch/mips/net/bpf_jit_asm.S | 238 
 4 files changed, 302 insertions(+), 145 deletions(-)
 create mode 100644 arch/mips/net/bpf_jit_asm.S

diff --git a/arch/mips/net/Makefile b/arch/mips/net/Makefile
index ae74b3a91f5c..8c2771401f54 100644
--- a/arch/mips/net/Makefile
+++ b/arch/mips/net/Makefile
@@ -1,3 +1,3 @@
 # MIPS networking code
 
-obj-$(CONFIG_BPF_JIT) += bpf_jit.o
+obj-$(CONFIG_BPF_JIT) += bpf_jit.o bpf_jit_asm.o
diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index f0db4f8310b2..0c4a133f6216 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -29,11 +29,14 @@
 #include bpf_jit.h
 
 /* ABI
- *
+ * r_skb_hlSKB header length
+ * r_data  SKB data pointer
+ * r_off   Offset
  * r_A BPF register A
  * r_X BPF register X
  * r_skb   *skb
  * r_M *scratch memory
+ * r_skb_len   SKB length
  *
  * On entry (*bpf_func)(*skb, *filter)
  * a0 = MIPS_R_A0 = skb;
@@ -75,6 +78,8 @@
 #define SEEN_X SEEN_SREG(4)
 #define SEEN_SKB   SEEN_SREG(5)
 #define SEEN_MEM   SEEN_SREG(6)
+/* SEEN_SK_DATA also implies skb_hl an skb_len */
+#define SEEN_SKB_DATA  (SEEN_SREG(7) | SEEN_SREG(1) | SEEN_SREG(0))
 
 /* Arguments used by JIT */
 #define ARGS_USED_BY_JIT   2 /* only applicable to 64-bit */
@@ -537,20 +542,6 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* Adjust the stack pointer */
emit_stack_offset(-align_sp(offset), ctx);
 
-   if (ctx-flags  SEEN_CALL) {
-   /* Argument save area */
-   if (config_enabled(CONFIG_64BIT))
-   /* Bottom of current frame */
-   real_off = align_sp(offset) - SZREG;
-   else
-   /* Top of previous frame */
-   real_off = align_sp(offset) + SZREG;
-   emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
-
-   real_off = 0;
-   }
-
tmp_flags = sflags = ctx-flags  SEEN_SREG_SFT;
/* sflags is essentially a bitmap */
while (tmp_flags) {
@@ -583,19 +574,6 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
int i, real_off = 0;
u32 sflags, tmp_flags;
 
-   if (ctx-flags  SEEN_CALL) {
-   if (config_enabled(CONFIG_64BIT))
-   /* Bottom of current frame */
-   real_off = align_sp(offset) - SZREG;
-   else
-   /* Top of previous frame */
-   real_off = align_sp(offset) + SZREG;
-   emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
-
-   real_off = 0;
-   }
-
tmp_flags = sflags = ctx-flags  SEEN_SREG_SFT;
/* sflags is a bitmap */
i = 0;
@@ -629,17 +607,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx

[PATCH 0/6] MIPS/BPF fixes for 4.3

[Markos Chandras]

Hi,

Here are some fixes for MIPS/BPF. The first 5 patches do some cleanup
and lay the groundwork for the final one which introduces assembly helpers
for MIPS and MIPS64. The goal is to speed up certain operations that do
not need to go through the common C functions. This also makes the test_bpf
testsuite happy with all 60 tests passing. This is based in 4.1-rc6.

The patchset is also available in my git tree.

https://github.com/hwoarang/linux/tree/4.3-bpf

The last patch also contains performance results along with the relevant
scripts and data used for the analysis.

Markos Chandras (6):
  MIPS: net: BPF: Free up some callee-saved registers
  MIPS: net: BPF: Replace RSIZE with SZREG
  MIPS: net: BPF: Fix stack pointer allocation
  MIPS: net: BPF: Move register definition to the BPF header
  MIPS: net: BPF: Use BPF register names to describe the ABI
  MIPS: net: BPF: Introduce BPF ASM helpers

 arch/mips/net/Makefile  |   2 +-
 arch/mips/net/bpf_jit.c | 268 
 arch/mips/net/bpf_jit.h |  42 ++-
 arch/mips/net/bpf_jit_asm.S | 238 +++
 4 files changed, 350 insertions(+), 200 deletions(-)
 create mode 100644 arch/mips/net/bpf_jit_asm.S

-- 
2.4.2

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[PATCH 2/6] MIPS: net: BPF: Replace RSIZE with SZREG

[Markos Chandras]

The RSZIE was used to determine the register width but MIPS
already defines SZREG so use that instead.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/net/bpf_jit.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 850b08ee3fab..56e0e8e9674d 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -20,6 +20,7 @@
 #include linux/string.h
 #include linux/slab.h
 #include linux/types.h
+#include asm/asm.h
 #include asm/bitops.h
 #include asm/cacheflush.h
 #include asm/cpu-features.h
@@ -60,7 +61,6 @@
  * 
  */
 
-#define RSIZE  (sizeof(unsigned long))
 #define ptr typeof(unsigned long)
 
 /* ABI specific return values */
@@ -576,12 +576,12 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* Argument save area */
if (config_enabled(CONFIG_64BIT))
/* Bottom of current frame */
-   real_off = align_sp(offset) - RSIZE;
+   real_off = align_sp(offset) - SZREG;
else
/* Top of previous frame */
-   real_off = align_sp(offset) + RSIZE;
+   real_off = align_sp(offset) + SZREG;
emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
+   emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
 
real_off = 0;
}
@@ -592,7 +592,7 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned 
offset)
if ((sflags  i)  0x1) {
emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
 ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
i++;
tmp_flags = 1;
@@ -601,13 +601,13 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, 
unsigned offset)
/* save return address */
if (ctx-flags  SEEN_CALL) {
emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
 
/* Setup r_M leaving the alignment gap if necessary */
if (ctx-flags  SEEN_MEM) {
-   if (real_off % (RSIZE * 2))
-   real_off += RSIZE;
+   if (real_off % (SZREG * 2))
+   real_off += SZREG;
emit_long_instr(ctx, ADDIU, r_M, r_sp, real_off);
}
 }
@@ -621,12 +621,12 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
if (ctx-flags  SEEN_CALL) {
if (config_enabled(CONFIG_64BIT))
/* Bottom of current frame */
-   real_off = align_sp(offset) - RSIZE;
+   real_off = align_sp(offset) - SZREG;
else
/* Top of previous frame */
-   real_off = align_sp(offset) + RSIZE;
+   real_off = align_sp(offset) + SZREG;
emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
-   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
+   emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + SZREG, ctx);
 
real_off = 0;
}
@@ -638,7 +638,7 @@ static void restore_bpf_jit_regs(struct jit_ctx *ctx,
if ((sflags  i)  0x1) {
emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
ctx);
-   real_off += RSIZE;
+   real_off += SZREG;
}
i++;
tmp_flags = 1;
@@ -658,7 +658,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
 
 
/* How may s* regs do we need to preserved? */
-   sp_off += hweight32(ctx-flags  SEEN_SREG_SFT) * RSIZE;
+   sp_off += hweight32(ctx-flags  SEEN_SREG_SFT) * SZREG;
 
if (ctx-flags  SEEN_MEM)
sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
@@ -674,13 +674,13 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
 * this space ourselves. We need to preserve $ra as well.
 */
sp_off += config_enabled(CONFIG_64BIT) ?
-   (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
+   (ARGS_USED_BY_JIT + 1) * SZREG : SZREG;
 
/*
 * Subtract the bytes for the last registers since we only care about
 * the location on the stack

[PATCH 5/6] MIPS: net: BPF: Use BPF register names to describe the ABI

[Markos Chandras]

Use the BPF register names instead of the arch register names to
document how the ABI is structured.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/net/bpf_jit.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 954df295f945..f0db4f8310b2 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -30,10 +30,10 @@
 
 /* ABI
  *
- * s3  BPF register A
- * s4  BPF register X
- * s5  *skb
- * s6  *scratch memory
+ * r_A BPF register A
+ * r_X BPF register X
+ * r_skb   *skb
+ * r_M *scratch memory
  *
  * On entry (*bpf_func)(*skb, *filter)
  * a0 = MIPS_R_A0 = skb;
-- 
2.4.2

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To unsubscribe from this list: send the line unsubscribe linux-kernel in
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 4/6] MIPS: net: BPF: Move register definition to the BPF header

[Markos Chandras]

The registers will be used by a subsequent patch introducing
ASM helpers so move them to a common header.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/net/bpf_jit.c | 35 ---
 arch/mips/net/bpf_jit.h | 35 +++
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 84cd09ba230a..954df295f945 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -63,41 +63,6 @@
 
 #define ptr typeof(unsigned long)
 
-/* ABI specific return values */
-#ifdef CONFIG_32BIT /* O32 */
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define r_err  MIPS_R_V1
-#define r_val  MIPS_R_V0
-#else /* CONFIG_CPU_LITTLE_ENDIAN */
-#define r_err  MIPS_R_V0
-#define r_val  MIPS_R_V1
-#endif
-#else /* N64 */
-#define r_err  MIPS_R_V0
-#define r_val  MIPS_R_V0
-#endif
-
-#define r_ret  MIPS_R_V0
-
-/*
- * Use 2 scratch registers to avoid pipeline interlocks.
- * There is no overhead during epilogue and prologue since
- * any of the $s0-$s6 registers will only be preserved if
- * they are going to actually be used.
- */
-#define r_off  MIPS_R_S2
-#define r_AMIPS_R_S3
-#define r_XMIPS_R_S4
-#define r_skb  MIPS_R_S5
-#define r_MMIPS_R_S6
-#define r_s0   MIPS_R_T4 /* scratch reg 1 */
-#define r_s1   MIPS_R_T5 /* scratch reg 2 */
-#define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
-#define r_tmp  MIPS_R_T7 /* No need to preserve this */
-#define r_zero MIPS_R_ZERO
-#define r_sp   MIPS_R_SP
-#define r_ra   MIPS_R_RA
-
 #define SCRATCH_OFF(k) (4 * (k))
 
 /* JIT flags */
diff --git a/arch/mips/net/bpf_jit.h b/arch/mips/net/bpf_jit.h
index f9b5a4d3dbf4..3afa7a6d81b3 100644
--- a/arch/mips/net/bpf_jit.h
+++ b/arch/mips/net/bpf_jit.h
@@ -43,4 +43,39 @@
 #define MIPS_COND_X(0x1  5)
 #define MIPS_COND_K(0x1  6)
 
+/* ABI specific return values */
+#ifdef CONFIG_32BIT /* O32 */
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define r_err  MIPS_R_V1
+#define r_val  MIPS_R_V0
+#else /* CONFIG_CPU_LITTLE_ENDIAN */
+#define r_err  MIPS_R_V0
+#define r_val  MIPS_R_V1
+#endif
+#else /* N64 */
+#define r_err  MIPS_R_V0
+#define r_val  MIPS_R_V0
+#endif
+
+#define r_ret  MIPS_R_V0
+
+/*
+ * Use 2 scratch registers to avoid pipeline interlocks.
+ * There is no overhead during epilogue and prologue since
+ * any of the $s0-$s6 registers will only be preserved if
+ * they are going to actually be used.
+ */
+#define r_off  MIPS_R_S2
+#define r_AMIPS_R_S3
+#define r_XMIPS_R_S4
+#define r_skb  MIPS_R_S5
+#define r_MMIPS_R_S6
+#define r_s0   MIPS_R_T4 /* scratch reg 1 */
+#define r_s1   MIPS_R_T5 /* scratch reg 2 */
+#define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
+#define r_tmp  MIPS_R_T7 /* No need to preserve this */
+#define r_zero MIPS_R_ZERO
+#define r_sp   MIPS_R_SP
+#define r_ra   MIPS_R_RA
+
 #endif /* BPF_JIT_MIPS_OP_H */
-- 
2.4.2

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 3/6] MIPS: net: BPF: Fix stack pointer allocation

[Markos Chandras]

Fix stack pointer offset which could potentially corrupt
argument registers in the previous frame. The calculated offset
reflects the size of all the registers we need to preserve so there
is no need for this erroneous subtraction.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/net/bpf_jit.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 56e0e8e9674d..84cd09ba230a 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -676,11 +676,7 @@ static unsigned int get_stack_depth(struct jit_ctx *ctx)
sp_off += config_enabled(CONFIG_64BIT) ?
(ARGS_USED_BY_JIT + 1) * SZREG : SZREG;
 
-   /*
-* Subtract the bytes for the last registers since we only care about
-* the location on the stack pointer.
-*/
-   return sp_off - SZREG;
+   return sp_off;
 }
 
 static void build_prologue(struct jit_ctx *ctx)
-- 
2.4.2

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 1/6] MIPS: net: BPF: Free up some callee-saved registers

[Markos Chandras]

Move the two scratch registers from s0 and s1 to t4 and t5 in order
to free up some callee-saved registers. We will use these callee-saved
registers to store some permanent data on them in a subsequent patch.

Cc: net...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: Alexei Starovoitov a...@plumgrid.com
Cc: Daniel Borkmann dbork...@redhat.com
Cc: Hannes Frederic Sowa han...@stressinduktion.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/net/bpf_jit.c | 35 +++
 arch/mips/net/bpf_jit.h |  2 ++
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 5d6139390bf8..850b08ee3fab 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -29,9 +29,6 @@
 
 /* ABI
  *
- * s0  1st scratch register
- * s1  2nd scratch register
- * s2  offset register
  * s3  BPF register A
  * s4  BPF register X
  * s5  *skb
@@ -88,13 +85,13 @@
  * any of the $s0-$s6 registers will only be preserved if
  * they are going to actually be used.
  */
-#define r_s0   MIPS_R_S0 /* scratch reg 1 */
-#define r_s1   MIPS_R_S1 /* scratch reg 2 */
 #define r_off  MIPS_R_S2
 #define r_AMIPS_R_S3
 #define r_XMIPS_R_S4
 #define r_skb  MIPS_R_S5
 #define r_MMIPS_R_S6
+#define r_s0   MIPS_R_T4 /* scratch reg 1 */
+#define r_s1   MIPS_R_T5 /* scratch reg 2 */
 #define r_tmp_imm  MIPS_R_T6 /* No need to preserve this */
 #define r_tmp  MIPS_R_T7 /* No need to preserve this */
 #define r_zero MIPS_R_ZERO
@@ -108,8 +105,6 @@
 #define SEEN_SREG_SFT  (BPF_MEMWORDS + 1)
 #define SEEN_SREG_BASE (1  SEEN_SREG_SFT)
 #define SEEN_SREG(x)   (SEEN_SREG_BASE  (x))
-#define SEEN_S0SEEN_SREG(0)
-#define SEEN_S1SEEN_SREG(1)
 #define SEEN_OFF   SEEN_SREG(2)
 #define SEEN_A SEEN_SREG(3)
 #define SEEN_X SEEN_SREG(4)
@@ -817,7 +812,7 @@ load_common:
   b_imm(prog-len, ctx), ctx);
emit_reg_move(r_ret, r_zero, ctx);
 
-   ctx-flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
+   ctx-flags |= SEEN_CALL | SEEN_OFF |
SEEN_SKB | SEEN_A;
 
emit_load_func(r_s0, (ptr)load_func[load_order],
@@ -883,7 +878,7 @@ load_ind:
return -ENOTSUPP;
 
/* X - 4 * (P[k:1]  0xf) */
-   ctx-flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
+   ctx-flags |= SEEN_X | SEEN_CALL | SEEN_SKB;
/* Load offset to a1 */
emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
/*
@@ -947,7 +942,7 @@ load_ind:
case BPF_ALU | BPF_MUL | BPF_K:
/* A *= K */
/* Load K to scratch register before MUL */
-   ctx-flags |= SEEN_A | SEEN_S0;
+   ctx-flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_mul(r_A, r_A, r_s0, ctx);
break;
@@ -965,7 +960,7 @@ load_ind:
emit_srl(r_A, r_A, k, ctx);
break;
}
-   ctx-flags |= SEEN_A | SEEN_S0;
+   ctx-flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_div(r_A, r_s0, ctx);
break;
@@ -975,7 +970,7 @@ load_ind:
ctx-flags |= SEEN_A;
emit_jit_reg_move(r_A, r_zero, ctx);
} else {
-   ctx-flags |= SEEN_A | SEEN_S0;
+   ctx-flags |= SEEN_A;
emit_load_imm(r_s0, k, ctx);
emit_mod(r_A, r_s0, ctx);
}
@@ -1089,10 +1084,10 @@ jmp_cmp:
if ((condt  MIPS_COND_GE) ||
(condt  MIPS_COND_GT)) {
if (condt  MIPS_COND_K) { /* K */
-   ctx-flags |= SEEN_S0 | SEEN_A;
+   ctx-flags |= SEEN_A;
emit_sltiu(r_s0, r_A, k, ctx);
} else { /* X */
-   ctx-flags |= SEEN_S0 | SEEN_A |
+   ctx-flags |= SEEN_A |
SEEN_X;
emit_sltu(r_s0, r_A, r_X, ctx);
}
@@ -1104,7 +1099,7 @@ jmp_cmp

Re: [PATCH 3.19 000/177] 3.19.7-stable review

[Markos Chandras]

On 05/04/2015 01:07 AM, Guenter Roeck wrote:
> On 05/02/2015 12:00 PM, Greg Kroah-Hartman wrote:
>> This is the start of the stable review cycle for the 3.19.7 release.
>> There are 177 patches in this series, all will be posted as a response
>> to this one.  If anyone has any issues with these being applied, please
>> let me know.
>>
>> Responses should be made by Mon May  4 18:59:31 UTC 2015.
>> Anything received after that time might be too late.
>>
> 
> Take two:
> 
> Build results:
> total: 125 pass: 112 fail: 13
> Failed builds:
> mips:defconfig
> mips:allmodconfig
> mips:bcm47xx_defconfig
> mips:bcm63xx_defconfig
> mips:nlm_xlp_defconfig
> mips:ath79_defconfig
> mips:ar7_defconfig
> mips:fuloong2e_defconfig
> mips:e55_defconfig
> mips:cavium_octeon_defconfig
> mips:malta_defconfig
> powerpc:defconfig
> powerpc:allmodconfig
> 
> Qemu test results:
> total: 30 pass: 22 fail: 8
> Failed tests:
> mips:mips_malta_defconfig
> mips:mips_malta_smp_defconfig
> mips:mipsel_malta_defconfig
> mips:mipsel_malta_smp_defconfig
> mips64:mips_malta64_defconfig
> mips64:mips_malta64_smp_defconfig
> powerpc:ppc64_book3s_defconfig
> powerpc:ppc64_book3s_smp_defconfig
> 
> ---
> Error logs:
> 
> mips:
> 
> arch/mips/kernel/unaligned.c: In function 'emulate_load_store_insn':
> arch/mips/kernel/unaligned.c:570:4: error: expected '}' before 'else'
> 
> Bisect points to 'MIPS: unaligned: Fix regular load/store instruction
> emulation for EVA'.
> 

I guess this is a fallout caused by the missing dependencies.

Patches

- [PATCH] MIPS: unaligned: Prevent EVA instructions on kernel unaligned"
(eeb538950367e3966cbf0237ab1a1dc30e059818)

- [PATCH] MIPS: unaligned: Surround load/store macros in do {} while
(3563c32d6532ece53c9dd8905a8e41983ef9952f)

couldn't be applied to 3.19 stable according to the emails I got from
Greg, so the third one in that series (aka the offending one) is now broken.

Please remove 'MIPS: unaligned: Fix regular load/store instruction
emulation for EVA' (6eae35485b26f9e51ab896eb8a936bed9908fdf6)

I will create a suitable 3.19 backport for that patchset.

Thanks and apologies for the breakage.

-- 
markos
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Re: [PATCH 3.19 000/177] 3.19.7-stable review

[Markos Chandras]

On 05/04/2015 01:07 AM, Guenter Roeck wrote:
 On 05/02/2015 12:00 PM, Greg Kroah-Hartman wrote:
 This is the start of the stable review cycle for the 3.19.7 release.
 There are 177 patches in this series, all will be posted as a response
 to this one.  If anyone has any issues with these being applied, please
 let me know.

 Responses should be made by Mon May  4 18:59:31 UTC 2015.
 Anything received after that time might be too late.

 
 Take two:
 
 Build results:
 total: 125 pass: 112 fail: 13
 Failed builds:
 mips:defconfig
 mips:allmodconfig
 mips:bcm47xx_defconfig
 mips:bcm63xx_defconfig
 mips:nlm_xlp_defconfig
 mips:ath79_defconfig
 mips:ar7_defconfig
 mips:fuloong2e_defconfig
 mips:e55_defconfig
 mips:cavium_octeon_defconfig
 mips:malta_defconfig
 powerpc:defconfig
 powerpc:allmodconfig
 
 Qemu test results:
 total: 30 pass: 22 fail: 8
 Failed tests:
 mips:mips_malta_defconfig
 mips:mips_malta_smp_defconfig
 mips:mipsel_malta_defconfig
 mips:mipsel_malta_smp_defconfig
 mips64:mips_malta64_defconfig
 mips64:mips_malta64_smp_defconfig
 powerpc:ppc64_book3s_defconfig
 powerpc:ppc64_book3s_smp_defconfig
 
 ---
 Error logs:
 
 mips:
 
 arch/mips/kernel/unaligned.c: In function 'emulate_load_store_insn':
 arch/mips/kernel/unaligned.c:570:4: error: expected '}' before 'else'
 
 Bisect points to 'MIPS: unaligned: Fix regular load/store instruction
 emulation for EVA'.
 

I guess this is a fallout caused by the missing dependencies.

Patches

- [PATCH] MIPS: unaligned: Prevent EVA instructions on kernel unaligned
(eeb538950367e3966cbf0237ab1a1dc30e059818)

- [PATCH] MIPS: unaligned: Surround load/store macros in do {} while
(3563c32d6532ece53c9dd8905a8e41983ef9952f)

couldn't be applied to 3.19 stable according to the emails I got from
Greg, so the third one in that series (aka the offending one) is now broken.

Please remove 'MIPS: unaligned: Fix regular load/store instruction
emulation for EVA' (6eae35485b26f9e51ab896eb8a936bed9908fdf6)

I will create a suitable 3.19 backport for that patchset.

Thanks and apologies for the breakage.

-- 
markos
--
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Re: [PATCH] MIPS64: R6: R2 emulation bugfix

[Markos Chandras]

On 04/29/2015 10:49 AM, Maciej W. Rozycki wrote:
> On Wed, 29 Apr 2015, James Hogan wrote:
> 
>>> Error recovery pointers for fixups was improperly set as ".word"
>>> which is unsuitable for MIPS64.
>>>
>>> Replaced by __stringify(PTR)
>>
>> Every other case of this sort of thing uses STR(PTR) (or __UA_ADDR in
>> uaccess.h). Can we stick to STR(PTR) for consistency please?
> 
>  Or __PA_ADDR in paccess.h.
> 
>  I have mixed feelings, the reason for __stringify being absent is the 
> macro being generic and more recently added than pieces of code that use 
> STR, e.g. unaligned.c that has been there since forever.  And we do use 
> __stringify in many other cases.
> 
>  On the other hand STR is short and sweet, unlike __stringify.

The patch overall looks good to me so here is my

Reviewed-by: Markos Chandras 

I do agree with James that it would be nice to have it in stable 4.0+ as
well.

I don't particularly care if STR() is going to be used at the end or we
stick to __stringify. Both are used in arch/mips/* anyway

-- 
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Re: [PATCH] MIPS64: R6: R2 emulation bugfix

[Markos Chandras]

On 04/29/2015 10:49 AM, Maciej W. Rozycki wrote:
 On Wed, 29 Apr 2015, James Hogan wrote:
 
 Error recovery pointers for fixups was improperly set as .word
 which is unsuitable for MIPS64.

 Replaced by __stringify(PTR)

 Every other case of this sort of thing uses STR(PTR) (or __UA_ADDR in
 uaccess.h). Can we stick to STR(PTR) for consistency please?
 
  Or __PA_ADDR in paccess.h.
 
  I have mixed feelings, the reason for __stringify being absent is the 
 macro being generic and more recently added than pieces of code that use 
 STR, e.g. unaligned.c that has been there since forever.  And we do use 
 __stringify in many other cases.
 
  On the other hand STR is short and sweet, unlike __stringify.

The patch overall looks good to me so here is my

Reviewed-by: Markos Chandras markos.chand...@imgtec.com

I do agree with James that it would be nice to have it in stable 4.0+ as
well.

I don't particularly care if STR() is going to be used at the end or we
stick to __stringify. Both are used in arch/mips/* anyway

-- 
markos
--
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[tip:irq/core] irqchip: mips-gic: Add new functions to start/ stop the GIC counter

[tip-bot for Markos Chandras]

Commit-ID:  fa6ed4cb6fd44ef4c6fad4d9572119d22381f32c
Gitweb: http://git.kernel.org/tip/fa6ed4cb6fd44ef4c6fad4d9572119d22381f32c
Author: Markos Chandras 
AuthorDate: Mon, 23 Mar 2015 12:32:01 +
Committer:  Jason Cooper 
CommitDate: Sun, 29 Mar 2015 20:08:23 +

irqchip: mips-gic: Add new functions to start/stop the GIC counter

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Andrew Bresticker 
Cc: Qais Yousef 
Cc: 
Signed-off-by: Markos Chandras 
Link: 
https://lkml.kernel.org/r/1427113923-9840-2-git-send-email-markos.chand...@imgtec.com
Signed-off-by: Jason Cooper 
---
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc08..f2d269b 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
return (((cycle_t) hi) << 32) + lo;
 }
+
+void gic_start_count(void)
+{
+   u32 gicconfig;
+
+   /* Start the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+   u32 gicconfig;
+
+   /* Stop the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac..3ea2e47 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
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[tip:irq/core] irqchip: mips-gic: Add new functions to start/ stop the GIC counter

[tip-bot for Markos Chandras]

Commit-ID:  fa6ed4cb6fd44ef4c6fad4d9572119d22381f32c
Gitweb: http://git.kernel.org/tip/fa6ed4cb6fd44ef4c6fad4d9572119d22381f32c
Author: Markos Chandras markos.chand...@imgtec.com
AuthorDate: Mon, 23 Mar 2015 12:32:01 +
Committer:  Jason Cooper ja...@lakedaemon.net
CommitDate: Sun, 29 Mar 2015 20:08:23 +

irqchip: mips-gic: Add new functions to start/stop the GIC counter

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner t...@linutronix.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Bresticker abres...@chromium.org
Cc: Qais Yousef qais.you...@imgtec.com
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
Link: 
https://lkml.kernel.org/r/1427113923-9840-2-git-send-email-markos.chand...@imgtec.com
Signed-off-by: Jason Cooper ja...@lakedaemon.net
---
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc08..f2d269b 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
return (((cycle_t) hi)  32) + lo;
 }
+
+void gic_start_count(void)
+{
+   u32 gicconfig;
+
+   /* Start the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig = ~(1  GIC_SH_CONFIG_COUNTSTOP_SHF);
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+   u32 gicconfig;
+
+   /* Stop the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig |= 1  GIC_SH_CONFIG_COUNTSTOP_SHF;
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac..3ea2e47 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
--
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[PATCH 2/3] clocksource: mips-gic-timer: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Cc: Daniel Lezcano 
Cc: Thomas Gleixner 
Cc: 
Signed-off-by: Markos Chandras 
---
 drivers/clocksource/mips-gic-timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clocksource/mips-gic-timer.c 
b/drivers/clocksource/mips-gic-timer.c
index 3bd31b1321f6..16adbc1fa4c1 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -133,6 +133,9 @@ static void __init __gic_clocksource_init(void)
clocksource_register_hz(_clocksource, gic_frequency);
 
gic_clockevent_init();
+
+   /* And finally start the counter */
+   gic_start_count();
 }
 
 void __init gic_clocksource_init(unsigned int frequency)
-- 
2.3.3

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[PATCH 3/3] MIPS: Malta: malta-time: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter before we try to determine its frequency.

Cc: 
Signed-off-by: Markos Chandras 
---
 arch/mips/mti-malta/malta-time.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index ce02dbdedc62..128a74bd7cea 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -87,8 +87,10 @@ static void __init estimate_frequencies(void)
 
/* Initialize counters. */
start = read_c0_count();
-   if (gic_present)
+   if (gic_present) {
+   gic_start_count();
gicstart = gic_read_count();
+   }
 
/* Read counter exactly on falling edge of update flag. */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
-- 
2.3.3

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[PATCH 0/3] GIC counter fixes

[Markos Chandras]

Hi,

Here are a few patches to ensure the GIC counter is running before we attempt
to use it since the default value on a MIPS core can be '1' which means
the GIC counter will be stopped after a CPU reset. These patches are based
on 4.0-rc1.

Markos Chandras (3):
  irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter
  clocksource: mips-gic-timer: Ensure GIC counter is running
  MIPS: Malta: malta-time: Ensure GIC counter is running

 arch/mips/mti-malta/malta-time.c |  4 +++-
 drivers/clocksource/mips-gic-timer.c |  3 +++
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 4 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.3.3

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[PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter

[Markos Chandras]

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Andrew Bresticker 
Cc: Qais Yousef 
Cc: 
Signed-off-by: Markos Chandras 
---
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc080e7ec..f2d269bca789 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
return (((cycle_t) hi) << 32) + lo;
 }
+
+void gic_start_count(void)
+{
+   u32 gicconfig;
+
+   /* Start the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+   u32 gicconfig;
+
+   /* Stop the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac451db..3ea2e4754c40 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-- 
2.3.3

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[PATCH 3/3] MIPS: Malta: malta-time: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter before we try to determine its frequency.

Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 arch/mips/mti-malta/malta-time.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index ce02dbdedc62..128a74bd7cea 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -87,8 +87,10 @@ static void __init estimate_frequencies(void)
 
/* Initialize counters. */
start = read_c0_count();
-   if (gic_present)
+   if (gic_present) {
+   gic_start_count();
gicstart = gic_read_count();
+   }
 
/* Read counter exactly on falling edge of update flag. */
while (CMOS_READ(RTC_REG_A)  RTC_UIP);
-- 
2.3.3

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[PATCH 2/3] clocksource: mips-gic-timer: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 drivers/clocksource/mips-gic-timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clocksource/mips-gic-timer.c 
b/drivers/clocksource/mips-gic-timer.c
index 3bd31b1321f6..16adbc1fa4c1 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -133,6 +133,9 @@ static void __init __gic_clocksource_init(void)
clocksource_register_hz(gic_clocksource, gic_frequency);
 
gic_clockevent_init();
+
+   /* And finally start the counter */
+   gic_start_count();
 }
 
 void __init gic_clocksource_init(unsigned int frequency)
-- 
2.3.3

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[PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter

[Markos Chandras]

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner t...@linutronix.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Bresticker abres...@chromium.org
Cc: Qais Yousef qais.you...@imgtec.com
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc080e7ec..f2d269bca789 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
return (((cycle_t) hi)  32) + lo;
 }
+
+void gic_start_count(void)
+{
+   u32 gicconfig;
+
+   /* Start the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig = ~(1  GIC_SH_CONFIG_COUNTSTOP_SHF);
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+   u32 gicconfig;
+
+   /* Stop the counter */
+   gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+   gicconfig |= 1  GIC_SH_CONFIG_COUNTSTOP_SHF;
+   gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac451db..3ea2e4754c40 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-- 
2.3.3

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[PATCH 0/3] GIC counter fixes

[Markos Chandras]

Hi,

Here are a few patches to ensure the GIC counter is running before we attempt
to use it since the default value on a MIPS core can be '1' which means
the GIC counter will be stopped after a CPU reset. These patches are based
on 4.0-rc1.

Markos Chandras (3):
  irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter
  clocksource: mips-gic-timer: Ensure GIC counter is running
  MIPS: Malta: malta-time: Ensure GIC counter is running

 arch/mips/mti-malta/malta-time.c |  4 +++-
 drivers/clocksource/mips-gic-timer.c |  3 +++
 drivers/irqchip/irq-mips-gic.c   | 21 +
 include/linux/irqchip/mips-gic.h |  2 ++
 4 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.3.3

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[PATCH v2] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

On a MIPS Malta board, tons of fifo underflow errors have been observed
when using u-boot as bootloader instead of YAMON. The reason for that
is that YAMON used to set the pcnet device to SRAM mode but u-boot does
not. As a result, the default Tx threshold (64 bytes) is now too small to
keep the fifo relatively used and it can result to Tx fifo underflow errors.
As a result of which, it's best to setup the SRAM on supported controllers
so we can always use the NOUFLO bit.

Cc: 
Cc: 
Cc: 
Cc: Don Fry 
Signed-off-by: Markos Chandras 
---
Changes since v1:
- Fix comment
---
 drivers/net/ethernet/amd/pcnet32.c | 31 +--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/pcnet32.c 
b/drivers/net/ethernet/amd/pcnet32.c
index 11d6e6561df1..15a8190a6f75 100644
--- a/drivers/net/ethernet/amd/pcnet32.c
+++ b/drivers/net/ethernet/amd/pcnet32.c
@@ -1543,7 +1543,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
 {
struct pcnet32_private *lp;
int i, media;
-   int fdx, mii, fset, dxsuflo;
+   int fdx, mii, fset, dxsuflo, sram;
int chip_version;
char *chipname;
struct net_device *dev;
@@ -1580,7 +1580,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
}
 
/* initialize variables */
-   fdx = mii = fset = dxsuflo = 0;
+   fdx = mii = fset = dxsuflo = sram = 0;
chip_version = (chip_version >> 12) & 0x;
 
switch (chip_version) {
@@ -1613,6 +1613,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = "PCnet/FAST III 79C973"; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2626:
chipname = "PCnet/Home 79C978"; /* PCI */
@@ -1636,6 +1637,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = "PCnet/FAST III 79C975"; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2628:
chipname = "PCnet/PRO 79C976";
@@ -1664,6 +1666,31 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
dxsuflo = 1;
}
 
+   /*
+* The Am79C973/Am79C975 controllers come with 12K of SRAM
+* which we can use for the Tx/Rx buffers but most importantly,
+* the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
+* Tx fifo underflows.
+*/
+   if (sram) {
+   /*
+* The SRAM is being configured in two steps. First we
+* set the SRAM size in the BCR25:SRAM_SIZE bits. According
+* to the datasheet, each bit corresponds to a 512-byte
+* page so we can have at most 24 pages. The SRAM_SIZE
+* holds the value of the upper 8 bits of the 16-bit SRAM size.
+* The low 8-bits start at 0x00 and end at 0xff. So the
+* address range is from 0x up to 0x17ff. Therefore,
+* the SRAM_SIZE is set to 0x17. The next step is to set
+* the BCR26:SRAM_BND midway through so the Tx and Rx
+* buffers can share the SRAM equally.
+*/
+   a->write_bcr(ioaddr, 25, 0x17);
+   a->write_bcr(ioaddr, 26, 0xc);
+   /* And finally enable the NOUFLO bit */
+   a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
+   }
+
dev = alloc_etherdev(sizeof(*lp));
if (!dev) {
ret = -ENOMEM;
-- 
2.3.3

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Re: [PATCH] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

Hi Don,

On Wed, Mar 18, 2015 at 07:07:34PM -0700, Don Fry wrote:
> One little change to the comment is needed.  See below
> 
> Don
> 
> On Wed, 2015-03-18 at 20:10 +, Markos Chandras wrote:
> > +   if (sram) {
> > +   /*
> > +* The SRAM is being configured in two steps. First we
> > +* set the SRAM size in the BCR25:SRAM_SIZE bits. According
> > +* to the datasheet, each bit corresponds to a 512-byte
> > +* page so we can have at most 24 pages. The SRAM_SIZE
> > +* corresponds holds the value of the upper 8 bits of
> > +* the 16-bit SRAM size. The low 8-bits start at 0x00
> > +* and end at 0xff. So the address range is from 0x
> > +* up to 0x17ff. Therefore, the SRAM_SIZE is set to 0x17.
> > +* The next step is to set the BCR24:SRAM_BND midway through
> > +* so the Tx and Rx buffers can share the SRAM equally.
> > +*/
> 
> The comment specifies BCR24 but the code is changing BCR26 which matches
> the documentation.  Please correct the comment to avoid confusion.
> 

Ah good catch. I will fix it and send a v2.

-- 
markos
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[PATCH v2] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

On a MIPS Malta board, tons of fifo underflow errors have been observed
when using u-boot as bootloader instead of YAMON. The reason for that
is that YAMON used to set the pcnet device to SRAM mode but u-boot does
not. As a result, the default Tx threshold (64 bytes) is now too small to
keep the fifo relatively used and it can result to Tx fifo underflow errors.
As a result of which, it's best to setup the SRAM on supported controllers
so we can always use the NOUFLO bit.

Cc: net...@vger.kernel.org
Cc: sta...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Don Fry pcne...@frontier.com
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
Changes since v1:
- Fix comment
---
 drivers/net/ethernet/amd/pcnet32.c | 31 +--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/pcnet32.c 
b/drivers/net/ethernet/amd/pcnet32.c
index 11d6e6561df1..15a8190a6f75 100644
--- a/drivers/net/ethernet/amd/pcnet32.c
+++ b/drivers/net/ethernet/amd/pcnet32.c
@@ -1543,7 +1543,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
 {
struct pcnet32_private *lp;
int i, media;
-   int fdx, mii, fset, dxsuflo;
+   int fdx, mii, fset, dxsuflo, sram;
int chip_version;
char *chipname;
struct net_device *dev;
@@ -1580,7 +1580,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
}
 
/* initialize variables */
-   fdx = mii = fset = dxsuflo = 0;
+   fdx = mii = fset = dxsuflo = sram = 0;
chip_version = (chip_version  12)  0x;
 
switch (chip_version) {
@@ -1613,6 +1613,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = PCnet/FAST III 79C973; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2626:
chipname = PCnet/Home 79C978; /* PCI */
@@ -1636,6 +1637,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = PCnet/FAST III 79C975; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2628:
chipname = PCnet/PRO 79C976;
@@ -1664,6 +1666,31 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
dxsuflo = 1;
}
 
+   /*
+* The Am79C973/Am79C975 controllers come with 12K of SRAM
+* which we can use for the Tx/Rx buffers but most importantly,
+* the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
+* Tx fifo underflows.
+*/
+   if (sram) {
+   /*
+* The SRAM is being configured in two steps. First we
+* set the SRAM size in the BCR25:SRAM_SIZE bits. According
+* to the datasheet, each bit corresponds to a 512-byte
+* page so we can have at most 24 pages. The SRAM_SIZE
+* holds the value of the upper 8 bits of the 16-bit SRAM size.
+* The low 8-bits start at 0x00 and end at 0xff. So the
+* address range is from 0x up to 0x17ff. Therefore,
+* the SRAM_SIZE is set to 0x17. The next step is to set
+* the BCR26:SRAM_BND midway through so the Tx and Rx
+* buffers can share the SRAM equally.
+*/
+   a-write_bcr(ioaddr, 25, 0x17);
+   a-write_bcr(ioaddr, 26, 0xc);
+   /* And finally enable the NOUFLO bit */
+   a-write_bcr(ioaddr, 18, a-read_bcr(ioaddr, 18) | (1  11));
+   }
+
dev = alloc_etherdev(sizeof(*lp));
if (!dev) {
ret = -ENOMEM;
-- 
2.3.3

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Re: [PATCH] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

Hi Don,

On Wed, Mar 18, 2015 at 07:07:34PM -0700, Don Fry wrote:
 One little change to the comment is needed.  See below
 
 Don
 
 On Wed, 2015-03-18 at 20:10 +, Markos Chandras wrote:
  +   if (sram) {
  +   /*
  +* The SRAM is being configured in two steps. First we
  +* set the SRAM size in the BCR25:SRAM_SIZE bits. According
  +* to the datasheet, each bit corresponds to a 512-byte
  +* page so we can have at most 24 pages. The SRAM_SIZE
  +* corresponds holds the value of the upper 8 bits of
  +* the 16-bit SRAM size. The low 8-bits start at 0x00
  +* and end at 0xff. So the address range is from 0x
  +* up to 0x17ff. Therefore, the SRAM_SIZE is set to 0x17.
  +* The next step is to set the BCR24:SRAM_BND midway through
  +* so the Tx and Rx buffers can share the SRAM equally.
  +*/
 
 The comment specifies BCR24 but the code is changing BCR26 which matches
 the documentation.  Please correct the comment to avoid confusion.
 

Ah good catch. I will fix it and send a v2.

-- 
markos
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[PATCH] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

On a MIPS Malta board, tons of fifo underflow errors have been observed
when using u-boot as bootloader instead of YAMON. The reason for that
is that YAMON used to set the pcnet device to SRAM mode but u-boot does
not. As a result, the default Tx threshold (64 bytes) is now too small to
keep the fifo relatively used and it can result to Tx fifo underflow errors.
As a result of which, it's best to setup the SRAM on supported controllers
so we can always use the NOUFLO bit.

Cc: 
Cc: 
Cc: 
Cc: Don Fry 
Signed-off-by: Markos Chandras 
---
 drivers/net/ethernet/amd/pcnet32.c | 31 +--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/pcnet32.c 
b/drivers/net/ethernet/amd/pcnet32.c
index 11d6e6561df1..7fb099f0c631 100644
--- a/drivers/net/ethernet/amd/pcnet32.c
+++ b/drivers/net/ethernet/amd/pcnet32.c
@@ -1543,7 +1543,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
 {
struct pcnet32_private *lp;
int i, media;
-   int fdx, mii, fset, dxsuflo;
+   int fdx, mii, fset, dxsuflo, sram;
int chip_version;
char *chipname;
struct net_device *dev;
@@ -1580,7 +1580,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
}
 
/* initialize variables */
-   fdx = mii = fset = dxsuflo = 0;
+   fdx = mii = fset = dxsuflo = sram = 0;
chip_version = (chip_version >> 12) & 0x;
 
switch (chip_version) {
@@ -1613,6 +1613,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = "PCnet/FAST III 79C973"; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2626:
chipname = "PCnet/Home 79C978"; /* PCI */
@@ -1636,6 +1637,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = "PCnet/FAST III 79C975"; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2628:
chipname = "PCnet/PRO 79C976";
@@ -1664,6 +1666,31 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
dxsuflo = 1;
}
 
+   /*
+* The Am79C973/Am79C975 controllers come with 12K of SRAM
+* which we can use for the Tx/Rx buffers but most importantly,
+* the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
+* Tx fifo underflows.
+*/
+   if (sram) {
+   /*
+* The SRAM is being configured in two steps. First we
+* set the SRAM size in the BCR25:SRAM_SIZE bits. According
+* to the datasheet, each bit corresponds to a 512-byte
+* page so we can have at most 24 pages. The SRAM_SIZE
+* corresponds holds the value of the upper 8 bits of
+* the 16-bit SRAM size. The low 8-bits start at 0x00
+* and end at 0xff. So the address range is from 0x
+* up to 0x17ff. Therefore, the SRAM_SIZE is set to 0x17.
+* The next step is to set the BCR24:SRAM_BND midway through
+* so the Tx and Rx buffers can share the SRAM equally.
+*/
+   a->write_bcr(ioaddr, 25, 0x17);
+   a->write_bcr(ioaddr, 26, 0xc);
+   /* And finally enable the NOUFLO bit */
+   a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
+   }
+
dev = alloc_etherdev(sizeof(*lp));
if (!dev) {
ret = -ENOMEM;
-- 
2.3.3

--
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH] net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3,5}

[Markos Chandras]

On a MIPS Malta board, tons of fifo underflow errors have been observed
when using u-boot as bootloader instead of YAMON. The reason for that
is that YAMON used to set the pcnet device to SRAM mode but u-boot does
not. As a result, the default Tx threshold (64 bytes) is now too small to
keep the fifo relatively used and it can result to Tx fifo underflow errors.
As a result of which, it's best to setup the SRAM on supported controllers
so we can always use the NOUFLO bit.

Cc: net...@vger.kernel.org
Cc: sta...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Don Fry pcne...@frontier.com
Signed-off-by: Markos Chandras markos.chand...@imgtec.com
---
 drivers/net/ethernet/amd/pcnet32.c | 31 +--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/pcnet32.c 
b/drivers/net/ethernet/amd/pcnet32.c
index 11d6e6561df1..7fb099f0c631 100644
--- a/drivers/net/ethernet/amd/pcnet32.c
+++ b/drivers/net/ethernet/amd/pcnet32.c
@@ -1543,7 +1543,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
 {
struct pcnet32_private *lp;
int i, media;
-   int fdx, mii, fset, dxsuflo;
+   int fdx, mii, fset, dxsuflo, sram;
int chip_version;
char *chipname;
struct net_device *dev;
@@ -1580,7 +1580,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
}
 
/* initialize variables */
-   fdx = mii = fset = dxsuflo = 0;
+   fdx = mii = fset = dxsuflo = sram = 0;
chip_version = (chip_version  12)  0x;
 
switch (chip_version) {
@@ -1613,6 +1613,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = PCnet/FAST III 79C973; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2626:
chipname = PCnet/Home 79C978; /* PCI */
@@ -1636,6 +1637,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
chipname = PCnet/FAST III 79C975; /* PCI */
fdx = 1;
mii = 1;
+   sram = 1;
break;
case 0x2628:
chipname = PCnet/PRO 79C976;
@@ -1664,6 +1666,31 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct 
pci_dev *pdev)
dxsuflo = 1;
}
 
+   /*
+* The Am79C973/Am79C975 controllers come with 12K of SRAM
+* which we can use for the Tx/Rx buffers but most importantly,
+* the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
+* Tx fifo underflows.
+*/
+   if (sram) {
+   /*
+* The SRAM is being configured in two steps. First we
+* set the SRAM size in the BCR25:SRAM_SIZE bits. According
+* to the datasheet, each bit corresponds to a 512-byte
+* page so we can have at most 24 pages. The SRAM_SIZE
+* corresponds holds the value of the upper 8 bits of
+* the 16-bit SRAM size. The low 8-bits start at 0x00
+* and end at 0xff. So the address range is from 0x
+* up to 0x17ff. Therefore, the SRAM_SIZE is set to 0x17.
+* The next step is to set the BCR24:SRAM_BND midway through
+* so the Tx and Rx buffers can share the SRAM equally.
+*/
+   a-write_bcr(ioaddr, 25, 0x17);
+   a-write_bcr(ioaddr, 26, 0xc);
+   /* And finally enable the NOUFLO bit */
+   a-write_bcr(ioaddr, 18, a-read_bcr(ioaddr, 18) | (1  11));
+   }
+
dev = alloc_etherdev(sizeof(*lp));
if (!dev) {
ret = -ENOMEM;
-- 
2.3.3

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Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction"

[Markos Chandras]

On 02/23/2015 10:52 PM, David Daney wrote:
> From: David Daney 
> 
> This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
> 
> There are two problems:
> 
> 1) It breaks OCTEON, which will now crash in early boot with:
> 
>   Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
> 
> 2) The logic is broken.
> 
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
> is required.  The offending patch attempts (and fails) to change the
> meaning to be that EHB is part of the ISA.
> 
> Signed-off-by: David Daney 
> ---
Hi,

First of all sorry about the octeon breakage.

However, whilst this patch will fix Octeon it will break R6

Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?

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Re: [PATCH] Revert MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction

[Markos Chandras]

On 02/23/2015 10:52 PM, David Daney wrote:
 From: David Daney david.da...@cavium.com
 
 This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
 
 There are two problems:
 
 1) It breaks OCTEON, which will now crash in early boot with:
 
   Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
 
 2) The logic is broken.
 
 The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
 is required.  The offending patch attempts (and fails) to change the
 meaning to be that EHB is part of the ISA.
 
 Signed-off-by: David Daney david.da...@cavium.com
 ---
Hi,

First of all sorry about the octeon breakage.

However, whilst this patch will fix Octeon it will break R6

Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?

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Re: linux-next: Tree for Feb 17 (mips build failures)

[Markos Chandras]

On Wed, Feb 18, 2015 at 05:54:57AM -0800, Guenter Roeck wrote:
> On 02/18/2015 01:14 AM, Markos Chandras wrote:
> > On Wed, Feb 18, 2015 at 07:37:40AM +1100, Stephen Rothwell wrote:
> >> Hi Guenter,
> >>
> >> [Add Ralf to cc]
> >>
> >> On Tue, 17 Feb 2015 09:20:36 -0800 Guenter Roeck  
> >> wrote:
> >>>
> >>> Build results:
> >>>   total: 121 pass: 109 fail: 12
> >>> Failed builds:
> >>>   mips:defconfig
> >>>   mips:allmodconfig
> >>>   mips:bcm47xx_defconfig
> >>>   mips:bcm63xx_defconfig
> >>>   mips:nlm_xlp_defconfig
> >>>   mips:ath79_defconfig
> >>>   mips:ar7_defconfig
> >>>   mips:fuloong2e_defconfig
> >>>   mips:e55_defconfig
> >>>   mips:cavium_octeon_defconfig
> >>>   mips:malta_defconfig
> >>>   sparc64:allmodconfig
> >>>
> >>> mips builds are all failing with
> >>>
> >>> Building mips:defconfig ... failed
> >>> --
> >>> Error log:
> >>> arch/mips/kernel/genex.S: Assembler messages:
> >>> arch/mips/kernel/genex.S:128: Error: Bad value (mips64r6) for internal use
> >>> arch/mips/kernel/genex.S:128: Error: unknown ISA level 64r6
> >>>
> >>> This was introduced by commit 0bf705e94771800 ("MIPS: kernel: genex: Set
> >>> correct ISA level") which apparently assumes that only mips64r6 is a valid
> >>> ISA level, though it is obviously not supported on older compilers. This
> >>> is on top of the other mips r6 related build errors seen yesterday.
> >>>
> >>> I really hope that this is not 3.20 material, given the lack of testing
> >>> with architectures other than mips r6 or with older compilers.
> >>
> >> --
> >> Cheers,
> >> Stephen Rothwells...@canb.auug.org.au
> >
> > This is just a typo I introduced yesterday by mistake. This has been fixed 
> > in
> > the meantime but it did not make it in today's linux-next.
> >
> Yes, but it is not the only r6 related bug. Did you fix all the others as 
> well ?
> 
> Guenter
> 

Hi,

Yes, all the recent build failures because of the r6 patches are now fixed.

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Re: linux-next: Tree for Feb 17 (mips build failures)

[Markos Chandras]

On Wed, Feb 18, 2015 at 07:37:40AM +1100, Stephen Rothwell wrote:
> Hi Guenter,
> 
> [Add Ralf to cc]
> 
> On Tue, 17 Feb 2015 09:20:36 -0800 Guenter Roeck  wrote:
> > 
> > Build results:
> > total: 121 pass: 109 fail: 12
> > Failed builds:
> > mips:defconfig
> > mips:allmodconfig
> > mips:bcm47xx_defconfig
> > mips:bcm63xx_defconfig
> > mips:nlm_xlp_defconfig
> > mips:ath79_defconfig
> > mips:ar7_defconfig
> > mips:fuloong2e_defconfig
> > mips:e55_defconfig
> > mips:cavium_octeon_defconfig
> > mips:malta_defconfig
> > sparc64:allmodconfig
> > 
> > mips builds are all failing with
> > 
> > Building mips:defconfig ... failed
> > --
> > Error log:
> > arch/mips/kernel/genex.S: Assembler messages:
> > arch/mips/kernel/genex.S:128: Error: Bad value (mips64r6) for internal use
> > arch/mips/kernel/genex.S:128: Error: unknown ISA level 64r6
> > 
> > This was introduced by commit 0bf705e94771800 ("MIPS: kernel: genex: Set
> > correct ISA level") which apparently assumes that only mips64r6 is a valid
> > ISA level, though it is obviously not supported on older compilers. This
> > is on top of the other mips r6 related build errors seen yesterday.
> > 
> > I really hope that this is not 3.20 material, given the lack of testing
> > with architectures other than mips r6 or with older compilers.
> 
> -- 
> Cheers,
> Stephen Rothwells...@canb.auug.org.au

This is just a typo I introduced yesterday by mistake. This has been fixed in
the meantime but it did not make it in today's linux-next.

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Re: linux-next: Tree for Feb 17 (mips build failures)

[Markos Chandras]

On Wed, Feb 18, 2015 at 07:37:40AM +1100, Stephen Rothwell wrote:
 Hi Guenter,
 
 [Add Ralf to cc]
 
 On Tue, 17 Feb 2015 09:20:36 -0800 Guenter Roeck li...@roeck-us.net wrote:
  
  Build results:
  total: 121 pass: 109 fail: 12
  Failed builds:
  mips:defconfig
  mips:allmodconfig
  mips:bcm47xx_defconfig
  mips:bcm63xx_defconfig
  mips:nlm_xlp_defconfig
  mips:ath79_defconfig
  mips:ar7_defconfig
  mips:fuloong2e_defconfig
  mips:e55_defconfig
  mips:cavium_octeon_defconfig
  mips:malta_defconfig
  sparc64:allmodconfig
  
  mips builds are all failing with
  
  Building mips:defconfig ... failed
  --
  Error log:
  arch/mips/kernel/genex.S: Assembler messages:
  arch/mips/kernel/genex.S:128: Error: Bad value (mips64r6) for internal use
  arch/mips/kernel/genex.S:128: Error: unknown ISA level 64r6
  
  This was introduced by commit 0bf705e94771800 (MIPS: kernel: genex: Set
  correct ISA level) which apparently assumes that only mips64r6 is a valid
  ISA level, though it is obviously not supported on older compilers. This
  is on top of the other mips r6 related build errors seen yesterday.
  
  I really hope that this is not 3.20 material, given the lack of testing
  with architectures other than mips r6 or with older compilers.
 
 -- 
 Cheers,
 Stephen Rothwells...@canb.auug.org.au

This is just a typo I introduced yesterday by mistake. This has been fixed in
the meantime but it did not make it in today's linux-next.

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Re: linux-next: Tree for Feb 17 (mips build failures)

[Markos Chandras]

On Wed, Feb 18, 2015 at 05:54:57AM -0800, Guenter Roeck wrote:
 On 02/18/2015 01:14 AM, Markos Chandras wrote:
  On Wed, Feb 18, 2015 at 07:37:40AM +1100, Stephen Rothwell wrote:
  Hi Guenter,
 
  [Add Ralf to cc]
 
  On Tue, 17 Feb 2015 09:20:36 -0800 Guenter Roeck li...@roeck-us.net 
  wrote:
 
  Build results:
total: 121 pass: 109 fail: 12
  Failed builds:
mips:defconfig
mips:allmodconfig
mips:bcm47xx_defconfig
mips:bcm63xx_defconfig
mips:nlm_xlp_defconfig
mips:ath79_defconfig
mips:ar7_defconfig
mips:fuloong2e_defconfig
mips:e55_defconfig
mips:cavium_octeon_defconfig
mips:malta_defconfig
sparc64:allmodconfig
 
  mips builds are all failing with
 
  Building mips:defconfig ... failed
  --
  Error log:
  arch/mips/kernel/genex.S: Assembler messages:
  arch/mips/kernel/genex.S:128: Error: Bad value (mips64r6) for internal use
  arch/mips/kernel/genex.S:128: Error: unknown ISA level 64r6
 
  This was introduced by commit 0bf705e94771800 (MIPS: kernel: genex: Set
  correct ISA level) which apparently assumes that only mips64r6 is a valid
  ISA level, though it is obviously not supported on older compilers. This
  is on top of the other mips r6 related build errors seen yesterday.
 
  I really hope that this is not 3.20 material, given the lack of testing
  with architectures other than mips r6 or with older compilers.
 
  --
  Cheers,
  Stephen Rothwells...@canb.auug.org.au
 
  This is just a typo I introduced yesterday by mistake. This has been fixed 
  in
  the meantime but it did not make it in today's linux-next.
 
 Yes, but it is not the only r6 related bug. Did you fix all the others as 
 well ?
 
 Guenter
 

Hi,

Yes, all the recent build failures because of the r6 patches are now fixed.

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Re: MIPS: FP32XX_HYBRID_FPRS

[Markos Chandras]

On Sat, Feb 14, 2015 at 06:33:59PM +0100, Paul Bolle wrote:
> On Sat, 2015-02-14 at 17:57 +0100, Paul Bolle wrote:
> > Your d8fb6537f1d4 ("MIPS: kernel: elf: Improve the overall ABI and FPU
> > mode checks") is included in yesterday's linux-next (ie, next-20150213).
> > I noticed because a script I use to check linux-next spotted a minor
> > problem with it.
> > 
> > That commit removed the only user of Kconfig symbol FP32XX_HYBRID_FPRS.
> > Setting FP32XX_HYBRID_FPRS is now pointless in linux-next. Is the
> > trivial commit to its entry form arch/mips/Kconfig.debug queued
>[] to remove its entry from [...] 
> 
> > somewhere?
> 
> 
> Paul Bolle
> 

Hi Paul,

Thanks I will fix the original patch to drop this symbol

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Re: MIPS: FP32XX_HYBRID_FPRS

[Markos Chandras]

On Sat, Feb 14, 2015 at 06:33:59PM +0100, Paul Bolle wrote:
 On Sat, 2015-02-14 at 17:57 +0100, Paul Bolle wrote:
  Your d8fb6537f1d4 (MIPS: kernel: elf: Improve the overall ABI and FPU
  mode checks) is included in yesterday's linux-next (ie, next-20150213).
  I noticed because a script I use to check linux-next spotted a minor
  problem with it.
  
  That commit removed the only user of Kconfig symbol FP32XX_HYBRID_FPRS.
  Setting FP32XX_HYBRID_FPRS is now pointless in linux-next. Is the
  trivial commit to its entry form arch/mips/Kconfig.debug queued
[] to remove its entry from [...] 
 
  somewhere?
 
 
 Paul Bolle
 

Hi Paul,

Thanks I will fix the original patch to drop this symbol

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Re: MIPS: CONFIG_CPU_MIPS_R6?

[Markos Chandras]

On Sat, Feb 14, 2015 at 06:26:45PM +0100, Paul Bolle wrote:
> Your commit 33d73a3d4159 ("MIPS: lib: memset: Add MIPS R6 support") is
> included in yesterday's linux next (ie, next-20150213). I noticed
> because a script I use to check linux-next spotted a trivial problem
> with it.
> 
> It added a reference to CONFIG_CPU_MIPS_R6 in comment. Should I submit
> the trivial patch to change that into a reference to CONFIG_CPU_MIPSR6
> or do you prefer to do that yourself?
> 
> 
> Paul Bolle
> 
Hi Paul,

Ok thanks I will fix both.

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Re: MIPS: CONFIG_CPU_MIPS_R6?

[Markos Chandras]

On Sat, Feb 14, 2015 at 06:26:45PM +0100, Paul Bolle wrote:
 Your commit 33d73a3d4159 (MIPS: lib: memset: Add MIPS R6 support) is
 included in yesterday's linux next (ie, next-20150213). I noticed
 because a script I use to check linux-next spotted a trivial problem
 with it.
 
 It added a reference to CONFIG_CPU_MIPS_R6 in comment. Should I submit
 the trivial patch to change that into a reference to CONFIG_CPU_MIPSR6
 or do you prefer to do that yourself?
 
 
 Paul Bolle
 
Hi Paul,

Ok thanks I will fix both.

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Re: [PATCH] MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS

[Markos Chandras]

On 01/13/2015 01:12 PM, Markos Chandras wrote:
> On 01/08/2015 12:17 PM, Paul Burton wrote:
>> Userland code may be built using an ABI which permits linking to objects
>> that have more restrictive floating point requirements. For example,
>> userland code may be built to target the O32 FPXX ABI. Such code may be
>> linked with other FPXX code, or code built for either one of the more
>> restrictive FP32 or FP64. When linking with more restrictive code, the
>> overall requirement of the process becomes that of the more restrictive
>> code. The kernel has no way to know in advance which mode the process
>> will need to be executed in, and indeed it may need to change during
>> execution. The dynamic loader is the only code which will know the
>> overall required mode, and so it needs to have a means to instruct the
>> kernel to switch the FP mode of the process.
>>
>> This patch introduces 2 new options to the prctl syscall which provide
>> such a capability. The FP mode of the process is represented as a
>> simple bitmask combining a number of mode bits mirroring those present
>> in the hardware. Userland can either retrieve the current FP mode of
>> the process:
>>
>>   mode = prctl(PR_GET_FP_MODE);
>> [...]
>> +int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
>> +{
>> +const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
>> +unsigned long switch_count;
>> +struct task_struct *t;
>> +
>> +/* Check the value is valid */
>> +if (value & ~known_bits)
>> +return -EOPNOTSUPP;
>> +
>> +/* Avoid inadvertently triggering emulation */
>> +if ((value & PR_FP_MODE_FR) && cpu_has_fpu &&
>> +!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
>> +return -EOPNOTSUPP;
>> +if ((value & PR_FP_MODE_FRE) && !cpu_has_fre)
>> +return -EOPNOTSUPP;
>> +

Hi Paul,

Do you think you can address this[1] suggestion by Matthew in this patch
since this hasn't been merged yet? Thanks

[1] http://www.linux-mips.org/archives/linux-mips/2015-01/msg00265.html

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Re: [PATCH] MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS

[Markos Chandras]

On 01/13/2015 01:12 PM, Markos Chandras wrote:
 On 01/08/2015 12:17 PM, Paul Burton wrote:
 Userland code may be built using an ABI which permits linking to objects
 that have more restrictive floating point requirements. For example,
 userland code may be built to target the O32 FPXX ABI. Such code may be
 linked with other FPXX code, or code built for either one of the more
 restrictive FP32 or FP64. When linking with more restrictive code, the
 overall requirement of the process becomes that of the more restrictive
 code. The kernel has no way to know in advance which mode the process
 will need to be executed in, and indeed it may need to change during
 execution. The dynamic loader is the only code which will know the
 overall required mode, and so it needs to have a means to instruct the
 kernel to switch the FP mode of the process.

 This patch introduces 2 new options to the prctl syscall which provide
 such a capability. The FP mode of the process is represented as a
 simple bitmask combining a number of mode bits mirroring those present
 in the hardware. Userland can either retrieve the current FP mode of
 the process:

   mode = prctl(PR_GET_FP_MODE);
 [...]
 +int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
 +{
 +const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
 +unsigned long switch_count;
 +struct task_struct *t;
 +
 +/* Check the value is valid */
 +if (value  ~known_bits)
 +return -EOPNOTSUPP;
 +
 +/* Avoid inadvertently triggering emulation */
 +if ((value  PR_FP_MODE_FR)  cpu_has_fpu 
 +!(current_cpu_data.fpu_id  MIPS_FPIR_F64))
 +return -EOPNOTSUPP;
 +if ((value  PR_FP_MODE_FRE)  !cpu_has_fre)
 +return -EOPNOTSUPP;
 +

Hi Paul,

Do you think you can address this[1] suggestion by Matthew in this patch
since this hasn't been merged yet? Thanks

[1] http://www.linux-mips.org/archives/linux-mips/2015-01/msg00265.html

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Re: [PATCH] MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS

[Markos Chandras]

On 01/08/2015 12:17 PM, Paul Burton wrote:
> Userland code may be built using an ABI which permits linking to objects
> that have more restrictive floating point requirements. For example,
> userland code may be built to target the O32 FPXX ABI. Such code may be
> linked with other FPXX code, or code built for either one of the more
> restrictive FP32 or FP64. When linking with more restrictive code, the
> overall requirement of the process becomes that of the more restrictive
> code. The kernel has no way to know in advance which mode the process
> will need to be executed in, and indeed it may need to change during
> execution. The dynamic loader is the only code which will know the
> overall required mode, and so it needs to have a means to instruct the
> kernel to switch the FP mode of the process.
> 
> This patch introduces 2 new options to the prctl syscall which provide
> such a capability. The FP mode of the process is represented as a
> simple bitmask combining a number of mode bits mirroring those present
> in the hardware. Userland can either retrieve the current FP mode of
> the process:
> 
>   mode = prctl(PR_GET_FP_MODE);
> 
> or modify the current FP mode of the process:
> 
>   err = prctl(PR_SET_FP_MODE, new_mode);
> 
> Signed-off-by: Paul Burton 
> Cc: Matthew Fortune 
> Cc: Markos Chandras 
Hi,

I think the "MIPS,prctl" in the title should be "MIPS: prctl"

I have also CC'd the LKML and the linux-api mailing lists since this
touches the kernel ABI with the new PR_[GS]ET_FP_MODE definitions.

(I intentionally leave the contents of the patch below so people can
comment on it)

> ---
>  arch/mips/include/asm/mmu.h |  3 ++
>  arch/mips/include/asm/mmu_context.h |  2 +
>  arch/mips/include/asm/processor.h   | 11 +
>  arch/mips/kernel/process.c  | 92 
> +
>  arch/mips/kernel/traps.c| 19 
>  include/uapi/linux/prctl.h  |  5 ++
>  kernel/sys.c| 12 +
>  7 files changed, 144 insertions(+)
> 
> diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
> index c436138..1afa1f9 100644
> --- a/arch/mips/include/asm/mmu.h
> +++ b/arch/mips/include/asm/mmu.h
> @@ -1,9 +1,12 @@
>  #ifndef __ASM_MMU_H
>  #define __ASM_MMU_H
>  
> +#include 
> +
>  typedef struct {
>   unsigned long asid[NR_CPUS];
>   void *vdso;
> + atomic_t fp_mode_switching;
>  } mm_context_t;
>  
>  #endif /* __ASM_MMU_H */
> diff --git a/arch/mips/include/asm/mmu_context.h 
> b/arch/mips/include/asm/mmu_context.h
> index 2f82568..87f1107 100644
> --- a/arch/mips/include/asm/mmu_context.h
> +++ b/arch/mips/include/asm/mmu_context.h
> @@ -132,6 +132,8 @@ init_new_context(struct task_struct *tsk, struct 
> mm_struct *mm)
>   for_each_possible_cpu(i)
>   cpu_context(i, mm) = 0;
>  
> + atomic_set(>context.fp_mode_switching, 0);
> +
>   return 0;
>  }
>  
> diff --git a/arch/mips/include/asm/processor.h 
> b/arch/mips/include/asm/processor.h
> index f1df4cb..9daa386 100644
> --- a/arch/mips/include/asm/processor.h
> +++ b/arch/mips/include/asm/processor.h
> @@ -399,4 +399,15 @@ unsigned long get_wchan(struct task_struct *p);
>  
>  #endif
>  
> +/*
> + * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE 
> options
> + * to the prctl syscall.
> + */
> +extern int mips_get_process_fp_mode(struct task_struct *task);
> +extern int mips_set_process_fp_mode(struct task_struct *task,
> + unsigned int value);
> +
> +#define GET_FP_MODE(task)mips_get_process_fp_mode(task)
> +#define SET_FP_MODE(task,value)  mips_set_process_fp_mode(task, 
> value)
> +
>  #endif /* _ASM_PROCESSOR_H */
> diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
> index eb76434..b732c0c 100644
> --- a/arch/mips/kernel/process.c
> +++ b/arch/mips/kernel/process.c
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  #include 
> @@ -550,3 +551,94 @@ void arch_trigger_all_cpu_backtrace(bool include_self)
>  {
>   smp_call_function(arch_dump_stack, NULL, 1);
>  }
> +
> +int mips_get_process_fp_mode(struct task_struct *task)
> +{
> + int value = 0;
> +
> + if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
> + value |= PR_FP_MODE_FR;
> + if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
> + value |= PR_FP_MODE_FRE;
> +
> + return value;
> +}
> +
> +int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
> +{
> + con

Re: [PATCH] MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS

[Markos Chandras]

On 01/08/2015 12:17 PM, Paul Burton wrote:
 Userland code may be built using an ABI which permits linking to objects
 that have more restrictive floating point requirements. For example,
 userland code may be built to target the O32 FPXX ABI. Such code may be
 linked with other FPXX code, or code built for either one of the more
 restrictive FP32 or FP64. When linking with more restrictive code, the
 overall requirement of the process becomes that of the more restrictive
 code. The kernel has no way to know in advance which mode the process
 will need to be executed in, and indeed it may need to change during
 execution. The dynamic loader is the only code which will know the
 overall required mode, and so it needs to have a means to instruct the
 kernel to switch the FP mode of the process.
 
 This patch introduces 2 new options to the prctl syscall which provide
 such a capability. The FP mode of the process is represented as a
 simple bitmask combining a number of mode bits mirroring those present
 in the hardware. Userland can either retrieve the current FP mode of
 the process:
 
   mode = prctl(PR_GET_FP_MODE);
 
 or modify the current FP mode of the process:
 
   err = prctl(PR_SET_FP_MODE, new_mode);
 
 Signed-off-by: Paul Burton paul.bur...@imgtec.com
 Cc: Matthew Fortune matthew.fort...@imgtec.com
 Cc: Markos Chandras markos.chand...@imgtec.com
Hi,

I think the MIPS,prctl in the title should be MIPS: prctl

I have also CC'd the LKML and the linux-api mailing lists since this
touches the kernel ABI with the new PR_[GS]ET_FP_MODE definitions.

(I intentionally leave the contents of the patch below so people can
comment on it)

 ---
  arch/mips/include/asm/mmu.h |  3 ++
  arch/mips/include/asm/mmu_context.h |  2 +
  arch/mips/include/asm/processor.h   | 11 +
  arch/mips/kernel/process.c  | 92 
 +
  arch/mips/kernel/traps.c| 19 
  include/uapi/linux/prctl.h  |  5 ++
  kernel/sys.c| 12 +
  7 files changed, 144 insertions(+)
 
 diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
 index c436138..1afa1f9 100644
 --- a/arch/mips/include/asm/mmu.h
 +++ b/arch/mips/include/asm/mmu.h
 @@ -1,9 +1,12 @@
  #ifndef __ASM_MMU_H
  #define __ASM_MMU_H
  
 +#include linux/atomic.h
 +
  typedef struct {
   unsigned long asid[NR_CPUS];
   void *vdso;
 + atomic_t fp_mode_switching;
  } mm_context_t;
  
  #endif /* __ASM_MMU_H */
 diff --git a/arch/mips/include/asm/mmu_context.h 
 b/arch/mips/include/asm/mmu_context.h
 index 2f82568..87f1107 100644
 --- a/arch/mips/include/asm/mmu_context.h
 +++ b/arch/mips/include/asm/mmu_context.h
 @@ -132,6 +132,8 @@ init_new_context(struct task_struct *tsk, struct 
 mm_struct *mm)
   for_each_possible_cpu(i)
   cpu_context(i, mm) = 0;
  
 + atomic_set(mm-context.fp_mode_switching, 0);
 +
   return 0;
  }
  
 diff --git a/arch/mips/include/asm/processor.h 
 b/arch/mips/include/asm/processor.h
 index f1df4cb..9daa386 100644
 --- a/arch/mips/include/asm/processor.h
 +++ b/arch/mips/include/asm/processor.h
 @@ -399,4 +399,15 @@ unsigned long get_wchan(struct task_struct *p);
  
  #endif
  
 +/*
 + * Functions  macros implementing the PR_GET_FP_MODE  PR_SET_FP_MODE 
 options
 + * to the prctl syscall.
 + */
 +extern int mips_get_process_fp_mode(struct task_struct *task);
 +extern int mips_set_process_fp_mode(struct task_struct *task,
 + unsigned int value);
 +
 +#define GET_FP_MODE(task)mips_get_process_fp_mode(task)
 +#define SET_FP_MODE(task,value)  mips_set_process_fp_mode(task, 
 value)
 +
  #endif /* _ASM_PROCESSOR_H */
 diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
 index eb76434..b732c0c 100644
 --- a/arch/mips/kernel/process.c
 +++ b/arch/mips/kernel/process.c
 @@ -25,6 +25,7 @@
  #include linux/completion.h
  #include linux/kallsyms.h
  #include linux/random.h
 +#include linux/prctl.h
  
  #include asm/asm.h
  #include asm/bootinfo.h
 @@ -550,3 +551,94 @@ void arch_trigger_all_cpu_backtrace(bool include_self)
  {
   smp_call_function(arch_dump_stack, NULL, 1);
  }
 +
 +int mips_get_process_fp_mode(struct task_struct *task)
 +{
 + int value = 0;
 +
 + if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
 + value |= PR_FP_MODE_FR;
 + if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
 + value |= PR_FP_MODE_FRE;
 +
 + return value;
 +}
 +
 +int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
 +{
 + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
 + unsigned long switch_count;
 + struct task_struct *t;
 +
 + /* Check the value is valid */
 + if (value  ~known_bits)
 + return -EOPNOTSUPP;
 +
 + /* Avoid inadvertently triggering emulation */
 + if ((value  PR_FP_MODE_FR)  cpu_has_fpu 
 + !(current_cpu_data.fpu_id

Re: [PATCH] MIPS: DMA: fix coherent alloc in non-coherent systems

[Markos Chandras]

On 10/30/2014 09:51 AM, James Hogan wrote:
> Hi Markos,
> 
> On 30/10/14 09:48, Markos Chandras wrote:
>>> diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h 
>>> b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
>>> index f9f4486..fe0b465 100644
>>> --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
>>> +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
>>> @@ -52,7 +52,7 @@ static inline int plat_dma_supported(struct device *dev, 
>>> u64 mask)
>>> return 0;
>>>  }
>>>  
>>> -static inline int plat_device_is_coherent(struct device *dev)
>>> +static inline int plat_device_is_coherent(const struct device *dev)
>>
>> Why adding const here?
>>
> 
> 
> 
>> Is it just a matter of consistence with the rest of the interfaces? Do
>> you need to move these into a separate patch since they don't quite fit
>> here.
> 
> See the new new call to plat_device_is_coherent(), which passes dev,
> which is const.
> 
> Cheers
> James
> 
Ah yes you are right. Thanks!

-- 
markos
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Re: [PATCH] MIPS: DMA: fix coherent alloc in non-coherent systems

[Markos Chandras]

Hi,

On 10/30/2014 01:48 AM, Leonid Yegoshin wrote:
> A default dma_alloc_coherent() fails to alloc a coherent memory on 
> non-coherent
> systems in case of device->coherent_dma_mask covering the whole memory space.
> 
> In case of non-coherent systems the coherent memory on MIPS is restricted by
> size of un-cachable segment and should be located in ZONE_DMA.
> 
> Added __GFP_DMA flag in case of non-coherent systems to enforce an allocation
> of coherent memory in ZONE_DMA.
> 
> Signed-off-by: Leonid Yegoshin 
> ---
>  .../include/asm/mach-cavium-octeon/dma-coherence.h |2 +-
>  arch/mips/include/asm/mach-generic/dma-coherence.h |2 +-
>  arch/mips/include/asm/mach-ip27/dma-coherence.h|2 +-
>  arch/mips/include/asm/mach-ip32/dma-coherence.h|2 +-
>  arch/mips/include/asm/mach-jazz/dma-coherence.h|2 +-
>  .../mips/include/asm/mach-loongson/dma-coherence.h |2 +-
>  arch/mips/mm/dma-default.c |   11 ---
>  7 files changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h 
> b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
> index f9f4486..fe0b465 100644
> --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
> +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
> @@ -52,7 +52,7 @@ static inline int plat_dma_supported(struct device *dev, 
> u64 mask)
>   return 0;
>  }
>  
> -static inline int plat_device_is_coherent(struct device *dev)
> +static inline int plat_device_is_coherent(const struct device *dev)

Why adding const here?

>  {
>   return 1;
>  }
> diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h 
> b/arch/mips/include/asm/mach-generic/dma-coherence.h
> index b4563df..2283996 100644
> --- a/arch/mips/include/asm/mach-generic/dma-coherence.h
> +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
> @@ -47,7 +47,7 @@ static inline int plat_dma_supported(struct device *dev, 
> u64 mask)
>   return 1;
>  }
>  
> -static inline int plat_device_is_coherent(struct device *dev)
> +static inline int plat_device_is_coherent(const struct device *dev)

likewise

>  {
>  #ifdef CONFIG_DMA_COHERENT
>   return 1;
> diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h 
> b/arch/mips/include/asm/mach-ip27/dma-coherence.h
> index 4ffddfd..c7767e3 100644
> --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
> +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
> @@ -58,7 +58,7 @@ static inline int plat_dma_supported(struct device *dev, 
> u64 mask)
>   return 1;
>  }
>  
> -static inline int plat_device_is_coherent(struct device *dev)
> +static inline int plat_device_is_coherent(const struct device *dev)

likewise

>  {
>   return 1;   /* IP27 non-cohernet mode is unsupported */
>  }
> diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h 
> b/arch/mips/include/asm/mach-ip32/dma-coherence.h
> index 104cfbc..a6b6a55 100644
> --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
> +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
> @@ -80,7 +80,7 @@ static inline int plat_dma_supported(struct device *dev, 
> u64 mask)
>   return 1;
>  }
>  
> -static inline int plat_device_is_coherent(struct device *dev)
> +static inline int plat_device_is_coherent(const struct device *dev)

likewise etc

Is it just a matter of consistence with the rest of the interfaces? Do
you need to move these into a separate patch since they don't quite fit
here.

-- 
markos
--
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Re: [PATCH] MIPS: DMA: fix coherent alloc in non-coherent systems

[Markos Chandras]

Hi,

On 10/30/2014 01:48 AM, Leonid Yegoshin wrote:
 A default dma_alloc_coherent() fails to alloc a coherent memory on 
 non-coherent
 systems in case of device-coherent_dma_mask covering the whole memory space.
 
 In case of non-coherent systems the coherent memory on MIPS is restricted by
 size of un-cachable segment and should be located in ZONE_DMA.
 
 Added __GFP_DMA flag in case of non-coherent systems to enforce an allocation
 of coherent memory in ZONE_DMA.
 
 Signed-off-by: Leonid Yegoshin leonid.yegos...@imgtec.com
 ---
  .../include/asm/mach-cavium-octeon/dma-coherence.h |2 +-
  arch/mips/include/asm/mach-generic/dma-coherence.h |2 +-
  arch/mips/include/asm/mach-ip27/dma-coherence.h|2 +-
  arch/mips/include/asm/mach-ip32/dma-coherence.h|2 +-
  arch/mips/include/asm/mach-jazz/dma-coherence.h|2 +-
  .../mips/include/asm/mach-loongson/dma-coherence.h |2 +-
  arch/mips/mm/dma-default.c |   11 ---
  7 files changed, 14 insertions(+), 9 deletions(-)
 
 diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h 
 b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 index f9f4486..fe0b465 100644
 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 @@ -52,7 +52,7 @@ static inline int plat_dma_supported(struct device *dev, 
 u64 mask)
   return 0;
  }
  
 -static inline int plat_device_is_coherent(struct device *dev)
 +static inline int plat_device_is_coherent(const struct device *dev)

Why adding const here?

  {
   return 1;
  }
 diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h 
 b/arch/mips/include/asm/mach-generic/dma-coherence.h
 index b4563df..2283996 100644
 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h
 +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
 @@ -47,7 +47,7 @@ static inline int plat_dma_supported(struct device *dev, 
 u64 mask)
   return 1;
  }
  
 -static inline int plat_device_is_coherent(struct device *dev)
 +static inline int plat_device_is_coherent(const struct device *dev)

likewise

  {
  #ifdef CONFIG_DMA_COHERENT
   return 1;
 diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h 
 b/arch/mips/include/asm/mach-ip27/dma-coherence.h
 index 4ffddfd..c7767e3 100644
 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
 +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
 @@ -58,7 +58,7 @@ static inline int plat_dma_supported(struct device *dev, 
 u64 mask)
   return 1;
  }
  
 -static inline int plat_device_is_coherent(struct device *dev)
 +static inline int plat_device_is_coherent(const struct device *dev)

likewise

  {
   return 1;   /* IP27 non-cohernet mode is unsupported */
  }
 diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h 
 b/arch/mips/include/asm/mach-ip32/dma-coherence.h
 index 104cfbc..a6b6a55 100644
 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
 +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
 @@ -80,7 +80,7 @@ static inline int plat_dma_supported(struct device *dev, 
 u64 mask)
   return 1;
  }
  
 -static inline int plat_device_is_coherent(struct device *dev)
 +static inline int plat_device_is_coherent(const struct device *dev)

likewise etc

Is it just a matter of consistence with the rest of the interfaces? Do
you need to move these into a separate patch since they don't quite fit
here.

-- 
markos
--
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Re: [PATCH] MIPS: DMA: fix coherent alloc in non-coherent systems

[Markos Chandras]

On 10/30/2014 09:51 AM, James Hogan wrote:
 Hi Markos,
 
 On 30/10/14 09:48, Markos Chandras wrote:
 diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h 
 b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 index f9f4486..fe0b465 100644
 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 @@ -52,7 +52,7 @@ static inline int plat_dma_supported(struct device *dev, 
 u64 mask)
 return 0;
  }
  
 -static inline int plat_device_is_coherent(struct device *dev)
 +static inline int plat_device_is_coherent(const struct device *dev)

 Why adding const here?

 
 snip
 
 Is it just a matter of consistence with the rest of the interfaces? Do
 you need to move these into a separate patch since they don't quite fit
 here.
 
 See the new new call to plat_device_is_coherent(), which passes dev,
 which is const.
 
 Cheers
 James
 
Ah yes you are right. Thanks!

-- 
markos
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Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 "mm/slab: support slab merge")

[Markos Chandras]

On 10/28/2014 03:00 PM, Joonsoo Kim wrote:
> 2014-10-28 23:32 GMT+09:00 Markos Chandras :
>> On 10/28/2014 02:21 PM, Joonsoo Kim wrote:
>>> 2014-10-28 22:48 GMT+09:00 Joonsoo Kim :
>>>> 2014-10-28 22:24 GMT+09:00 Markos Chandras :
>>>>> On 10/28/2014 01:19 PM, Markos Chandras wrote:
>>>>>> On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
>>>>>>> 2014-10-28 19:45 GMT+09:00 Markos Chandras :
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> It seems I am unable to boot my Malta with EVA. The problem appeared in
>>>>>>>> the 3.18 merge window. I bisected the problem (between v3.17 and
>>>>>>>> v3.18-rc1) and I found the following commit responsible for the broken 
>>>>>>>> boot.
>>>>>>>
>>>>>>> Hello,
>>>>>>>
>>>>>>> Did you start to bisect from v3.18-rc1?
>>>>>>> I'd like to be sure that this is another bug which is fixed by 
>>>>>>> following commit.
>>>>>>>
>>>>>>> commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
>>>>>>> Author: Joonsoo Kim 
>>>>>>> Date:   Mon Oct 13 15:51:01 2014 -0700
>>>>>>>
>>>>>>> mm/slab: fix unaligned access on sparc64
>>>>>>>
>>>>>>> This fix is merged into v3.18-rc1 sometime later that
>>>>>>> 'support slab merge' is merged.
>>>>>>>
>>>>>>> Thanks.
>>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
>>>>>> mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
>>>>>> problem
>>>>>>
>>>>>> btw i did more tests and this is not EVA specific. A maltaup_defconfig
>>>>>> fails in the same way. I suspect all malta*_defconfigs will fail in a
>>>>>> similar way which makes it probably easier for you to reproduce it on a
>>>>>> QEMU.
>>>>>>
>>>>>
>>>>> sorry maltaup_defconfig does not fail. maltasmvp_defconfig does. So it
>>>>> might be a similar problem like the one fixed in
>>>>> 85c9f4b04a08f6bc770b77530c22d04103468b8f
>>>>
>>>> Oops. Sorry. Above commit ('mm/slab: fix unaligned access on sparc64')
>>>> is irrelevant to this problem.
>>>>
>>>> Anyway, your problem would be related to merging with incompatible slab 
>>>> cache.
>>>> Best way to debug is printing source/target slab cache's object size and
>>>> alignment and find the problem. I will try to reproduce it using QEMU.
>>>
>>> I found that cross compile for MIPS isn't easy job. :)
>>
>> You could grab the following toolchain
>>
>> https://sourcery.mentor.com/GNUToolchain/release2791
>>
>> (get the IA32 linux tar)
>>
>> unpack it somewhere (eg /tmp) and then
>>
>> make ARCH=mips maltasmvp_defconfig
>> make ARCH=mips CROSS_COMPILE=/tmp/mips-2014.05/bin/mips-linux-gnu- -j8
>> or something :)
> 
> Wow!! Really Thanks!
> I will try it.
> 
>>> Could you help me to debug the problem with below patch?
>>
>> (there are a few build warnings with your patch
>> mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
>> unsigned int', but argument 5 has type 'size_t' [-Wformat=]
>> mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
>> unsigned int', but argument 7 has type 'unsigned int' [-Wformat=]
>> mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
>> unsigned int', but argument 8 has type 'int' [-Wformat=]
>> mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
>> unsigned int', but argument 9 has type 'int' [-Wformat=]
>> )
>>
>> but here is the output from a QEMU boot right before the crash
>>
>> CPU frequency 200.00 MHz
>> Calibrating delay loop... 1087.89 BogoMIPS (lpj=5439488)
>> pid_max: default: 32768 minimum: 301
>> __kmem_cache_alias: (cred_jar 92 0) to (kmalloc-128 128 128 128)
>> __kmem_cache_alias: (files_cache 256 0) to (kmalloc-256 256 128 256)
>> __kmem_cache_alias: (fs_cache 36 0) to (pid 64 64 44)
>> __kmem_cache_alias: (names_cache 4096 0) to (kmalloc-4096 4096 128 4096)
>> __kmem_cache_alias: (mnt_cache 160 0) to (filp 192 

Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 "mm/slab: support slab merge")

[Markos Chandras]

On 10/28/2014 02:21 PM, Joonsoo Kim wrote:
> 2014-10-28 22:48 GMT+09:00 Joonsoo Kim :
>> 2014-10-28 22:24 GMT+09:00 Markos Chandras :
>>> On 10/28/2014 01:19 PM, Markos Chandras wrote:
>>>> On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
>>>>> 2014-10-28 19:45 GMT+09:00 Markos Chandras :
>>>>>> Hi,
>>>>>>
>>>>>> It seems I am unable to boot my Malta with EVA. The problem appeared in
>>>>>> the 3.18 merge window. I bisected the problem (between v3.17 and
>>>>>> v3.18-rc1) and I found the following commit responsible for the broken 
>>>>>> boot.
>>>>>
>>>>> Hello,
>>>>>
>>>>> Did you start to bisect from v3.18-rc1?
>>>>> I'd like to be sure that this is another bug which is fixed by following 
>>>>> commit.
>>>>>
>>>>> commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
>>>>> Author: Joonsoo Kim 
>>>>> Date:   Mon Oct 13 15:51:01 2014 -0700
>>>>>
>>>>> mm/slab: fix unaligned access on sparc64
>>>>>
>>>>> This fix is merged into v3.18-rc1 sometime later that
>>>>> 'support slab merge' is merged.
>>>>>
>>>>> Thanks.
>>>>>
>>>> Hi,
>>>>
>>>> I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
>>>> mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
>>>> problem
>>>>
>>>> btw i did more tests and this is not EVA specific. A maltaup_defconfig
>>>> fails in the same way. I suspect all malta*_defconfigs will fail in a
>>>> similar way which makes it probably easier for you to reproduce it on a
>>>> QEMU.
>>>>
>>>
>>> sorry maltaup_defconfig does not fail. maltasmvp_defconfig does. So it
>>> might be a similar problem like the one fixed in
>>> 85c9f4b04a08f6bc770b77530c22d04103468b8f
>>
>> Oops. Sorry. Above commit ('mm/slab: fix unaligned access on sparc64')
>> is irrelevant to this problem.
>>
>> Anyway, your problem would be related to merging with incompatible slab 
>> cache.
>> Best way to debug is printing source/target slab cache's object size and
>> alignment and find the problem. I will try to reproduce it using QEMU.
> 
> I found that cross compile for MIPS isn't easy job. :)

You could grab the following toolchain

https://sourcery.mentor.com/GNUToolchain/release2791

(get the IA32 linux tar)

unpack it somewhere (eg /tmp) and then

make ARCH=mips maltasmvp_defconfig
make ARCH=mips CROSS_COMPILE=/tmp/mips-2014.05/bin/mips-linux-gnu- -j8
or something :)

> Could you help me to debug the problem with below patch?

(there are a few build warnings with your patch
mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
unsigned int', but argument 5 has type 'size_t' [-Wformat=]
mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
unsigned int', but argument 7 has type 'unsigned int' [-Wformat=]
mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
unsigned int', but argument 8 has type 'int' [-Wformat=]
mm/slab.c:2065:4: warning: format '%lu' expects argument of type 'long
unsigned int', but argument 9 has type 'int' [-Wformat=]
)

but here is the output from a QEMU boot right before the crash

CPU frequency 200.00 MHz
Calibrating delay loop... 1087.89 BogoMIPS (lpj=5439488)
pid_max: default: 32768 minimum: 301
__kmem_cache_alias: (cred_jar 92 0) to (kmalloc-128 128 128 128)
__kmem_cache_alias: (files_cache 256 0) to (kmalloc-256 256 128 256)
__kmem_cache_alias: (fs_cache 36 0) to (pid 64 64 44)
__kmem_cache_alias: (names_cache 4096 0) to (kmalloc-4096 4096 128 4096)
__kmem_cache_alias: (mnt_cache 160 0) to (filp 192 64 160)
Mount-cache hash table entries: 4096 (order: 0, 16384 bytes)
Mountpoint-cache hash table entries: 4096 (order: 0, 16384 bytes)
__kmem_cache_alias: (pool_workqueue 256 256) to (kmalloc-256 256 128 256)
Kernel bug detected[#1]:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted
3.18.0-rc2-00043-gf7e87a44ef60-dirty #1647
task: 8704b5d8 ti: 8704c000 task.ti: 8704c000


-- 
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Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 "mm/slab: support slab merge")

[Markos Chandras]

On 10/28/2014 01:19 PM, Markos Chandras wrote:
> On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
>> 2014-10-28 19:45 GMT+09:00 Markos Chandras :
>>> Hi,
>>>
>>> It seems I am unable to boot my Malta with EVA. The problem appeared in
>>> the 3.18 merge window. I bisected the problem (between v3.17 and
>>> v3.18-rc1) and I found the following commit responsible for the broken boot.
>>
>> Hello,
>>
>> Did you start to bisect from v3.18-rc1?
>> I'd like to be sure that this is another bug which is fixed by following 
>> commit.
>>
>> commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
>> Author: Joonsoo Kim 
>> Date:   Mon Oct 13 15:51:01 2014 -0700
>>
>> mm/slab: fix unaligned access on sparc64
>>
>> This fix is merged into v3.18-rc1 sometime later that
>> 'support slab merge' is merged.
>>
>> Thanks.
>>
> Hi,
> 
> I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
> mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
> problem
> 
> btw i did more tests and this is not EVA specific. A maltaup_defconfig
> fails in the same way. I suspect all malta*_defconfigs will fail in a
> similar way which makes it probably easier for you to reproduce it on a
> QEMU.
> 

sorry maltaup_defconfig does not fail. maltasmvp_defconfig does. So it
might be a similar problem like the one fixed in
85c9f4b04a08f6bc770b77530c22d04103468b8f

-- 
markos
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Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 "mm/slab: support slab merge")

[Markos Chandras]

On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
> 2014-10-28 19:45 GMT+09:00 Markos Chandras :
>> Hi,
>>
>> It seems I am unable to boot my Malta with EVA. The problem appeared in
>> the 3.18 merge window. I bisected the problem (between v3.17 and
>> v3.18-rc1) and I found the following commit responsible for the broken boot.
> 
> Hello,
> 
> Did you start to bisect from v3.18-rc1?
> I'd like to be sure that this is another bug which is fixed by following 
> commit.
> 
> commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
> Author: Joonsoo Kim 
> Date:   Mon Oct 13 15:51:01 2014 -0700
> 
> mm/slab: fix unaligned access on sparc64
> 
> This fix is merged into v3.18-rc1 sometime later that
> 'support slab merge' is merged.
> 
> Thanks.
> 
Hi,

I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
problem

btw i did more tests and this is not EVA specific. A maltaup_defconfig
fails in the same way. I suspect all malta*_defconfigs will fail in a
similar way which makes it probably easier for you to reproduce it on a
QEMU.

-- 
markos
--
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Boot problems on Malta with EVA (bisected to 12220dea07f1 "mm/slab: support slab merge")

[Markos Chandras]

Hi,

It seems I am unable to boot my Malta with EVA. The problem appeared in
the 3.18 merge window. I bisected the problem (between v3.17 and
v3.18-rc1) and I found the following commit responsible for the broken boot.

commit 12220dea07f1ac6ac717707104773d771c3f3077
Author: Joonsoo Kim 
Date:   Thu Oct 9 15:26:24 2014 -0700

mm/slab: support slab merge


Reverting my tree back to the parent of that commit
423c929cbbecc60e9c407f9048e58f5422f7995d ("
mm/slab_common: commonize slab merge logic")

restores the boot for me.

I don't quite understand the commit yet so let me know if you need more
information to debug this problem

Here is the kernel log of the failed boot.

Calibrating delay loop... 19.86 BogoMIPS (lpj=99328)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 4096 (order: 0, 16384 bytes)
Mountpoint-cache hash table entries: 4096 (order: 0, 16384 bytes)
Kernel bug detected[#1]:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.17.0-05639-g12220dea07f1 #1631
task: 1f04f5d8 ti: 1f05 task.ti: 1f05
$ 0   :  806c 0080 
$ 4   : 1f048080 0001 0001 
$ 8   : 1f04f5d8 0001 fffc 
$12   :   fffef7b7 
$16   : 1f048080 1f00ec00 1f048180 806ba998
$20   : 1f00ec00 8066 1f03b780 806ad380
$24   :  80154d70
$28   : 1f05 1f053d48 806ba8ec 80141184
Hi: 
Lo: 0b532b80
epc   : 80141190 alloc_unbound_pwq+0x234/0x304
Not tainted
ra: 80141184 alloc_unbound_pwq+0x228/0x304
Status: 1000dc03KERNEL EXL IE
Cause : 00800034
PrId  : 0001a82d (MIPS P5600)
Modules linked in:
Process swapper/0 (pid: 1, threadinfo=1f05, task=1f04f5d8, tls=)
Stack : 1f03b880 0002 1f03b800 80140d90 1f048180 1f03b880 0002
1f03b800
  1f03bb80 801417a4 1f0481e0 000e 1f048180 0200 1f048180
1f048190
  0002 1f048188 8066 8066 8065af94 80141dc0 0110d710
0100
  8065af94 806ad380 8065b200 8013ea70 1f048280 1f053e0c 8065af98
1f0481e0
   0004 8066 8066 8066 8066 8066
8066
  ...
Call Trace:
[<80141190>] alloc_unbound_pwq+0x234/0x304
[<801417a4>] apply_workqueue_attrs+0x11c/0x294
[<80141dc0>] __alloc_workqueue_key+0x23c/0x470
[<80683de4>] init_workqueues+0x320/0x400
[<8010058c>] do_one_initcall+0xe8/0x23c
[<8067cbec>] kernel_init_freeable+0x9c/0x224
[<80565fd8>] kernel_init+0x10/0x100
[<80104e38>] ret_from_kernel_thread+0x14/0x1c


Code: 10400032  00408021  320200ff <00020336> 2821  02002021
0c0defb0  24060100  26020074
---[ end trace cb88537fdc8fa200 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b

---[ end Kernel panic - not syncing: Attempted to kill init!
exitcode=0x000b

-- 
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Boot problems on Malta with EVA (bisected to 12220dea07f1 mm/slab: support slab merge)

[Markos Chandras]

Hi,

It seems I am unable to boot my Malta with EVA. The problem appeared in
the 3.18 merge window. I bisected the problem (between v3.17 and
v3.18-rc1) and I found the following commit responsible for the broken boot.

commit 12220dea07f1ac6ac717707104773d771c3f3077
Author: Joonsoo Kim iamjoonsoo@lge.com
Date:   Thu Oct 9 15:26:24 2014 -0700

mm/slab: support slab merge


Reverting my tree back to the parent of that commit
423c929cbbecc60e9c407f9048e58f5422f7995d (
mm/slab_common: commonize slab merge logic)

restores the boot for me.

I don't quite understand the commit yet so let me know if you need more
information to debug this problem

Here is the kernel log of the failed boot.

Calibrating delay loop... 19.86 BogoMIPS (lpj=99328)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 4096 (order: 0, 16384 bytes)
Mountpoint-cache hash table entries: 4096 (order: 0, 16384 bytes)
Kernel bug detected[#1]:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.17.0-05639-g12220dea07f1 #1631
task: 1f04f5d8 ti: 1f05 task.ti: 1f05
$ 0   :  806c 0080 
$ 4   : 1f048080 0001 0001 
$ 8   : 1f04f5d8 0001 fffc 
$12   :   fffef7b7 
$16   : 1f048080 1f00ec00 1f048180 806ba998
$20   : 1f00ec00 8066 1f03b780 806ad380
$24   :  80154d70
$28   : 1f05 1f053d48 806ba8ec 80141184
Hi: 
Lo: 0b532b80
epc   : 80141190 alloc_unbound_pwq+0x234/0x304
Not tainted
ra: 80141184 alloc_unbound_pwq+0x228/0x304
Status: 1000dc03KERNEL EXL IE
Cause : 00800034
PrId  : 0001a82d (MIPS P5600)
Modules linked in:
Process swapper/0 (pid: 1, threadinfo=1f05, task=1f04f5d8, tls=)
Stack : 1f03b880 0002 1f03b800 80140d90 1f048180 1f03b880 0002
1f03b800
  1f03bb80 801417a4 1f0481e0 000e 1f048180 0200 1f048180
1f048190
  0002 1f048188 8066 8066 8065af94 80141dc0 0110d710
0100
  8065af94 806ad380 8065b200 8013ea70 1f048280 1f053e0c 8065af98
1f0481e0
   0004 8066 8066 8066 8066 8066
8066
  ...
Call Trace:
[80141190] alloc_unbound_pwq+0x234/0x304
[801417a4] apply_workqueue_attrs+0x11c/0x294
[80141dc0] __alloc_workqueue_key+0x23c/0x470
[80683de4] init_workqueues+0x320/0x400
[8010058c] do_one_initcall+0xe8/0x23c
[8067cbec] kernel_init_freeable+0x9c/0x224
[80565fd8] kernel_init+0x10/0x100
[80104e38] ret_from_kernel_thread+0x14/0x1c


Code: 10400032  00408021  320200ff 00020336 2821  02002021
0c0defb0  24060100  26020074
---[ end trace cb88537fdc8fa200 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b

---[ end Kernel panic - not syncing: Attempted to kill init!
exitcode=0x000b

-- 
markos
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Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 mm/slab: support slab merge)

[Markos Chandras]

On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
 2014-10-28 19:45 GMT+09:00 Markos Chandras markos.chand...@imgtec.com:
 Hi,

 It seems I am unable to boot my Malta with EVA. The problem appeared in
 the 3.18 merge window. I bisected the problem (between v3.17 and
 v3.18-rc1) and I found the following commit responsible for the broken boot.
 
 Hello,
 
 Did you start to bisect from v3.18-rc1?
 I'd like to be sure that this is another bug which is fixed by following 
 commit.
 
 commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
 Author: Joonsoo Kim iamjoonsoo@lge.com
 Date:   Mon Oct 13 15:51:01 2014 -0700
 
 mm/slab: fix unaligned access on sparc64
 
 This fix is merged into v3.18-rc1 sometime later that
 'support slab merge' is merged.
 
 Thanks.
 
Hi,

I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
problem

btw i did more tests and this is not EVA specific. A maltaup_defconfig
fails in the same way. I suspect all malta*_defconfigs will fail in a
similar way which makes it probably easier for you to reproduce it on a
QEMU.

-- 
markos
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Re: Boot problems on Malta with EVA (bisected to 12220dea07f1 mm/slab: support slab merge)

[Markos Chandras]

On 10/28/2014 01:19 PM, Markos Chandras wrote:
 On 10/28/2014 01:01 PM, Joonsoo Kim wrote:
 2014-10-28 19:45 GMT+09:00 Markos Chandras markos.chand...@imgtec.com:
 Hi,

 It seems I am unable to boot my Malta with EVA. The problem appeared in
 the 3.18 merge window. I bisected the problem (between v3.17 and
 v3.18-rc1) and I found the following commit responsible for the broken boot.

 Hello,

 Did you start to bisect from v3.18-rc1?
 I'd like to be sure that this is another bug which is fixed by following 
 commit.

 commit 85c9f4b04a08f6bc770b77530c22d04103468b8f
 Author: Joonsoo Kim iamjoonsoo@lge.com
 Date:   Mon Oct 13 15:51:01 2014 -0700

 mm/slab: fix unaligned access on sparc64

 This fix is merged into v3.18-rc1 sometime later that
 'support slab merge' is merged.

 Thanks.

 Hi,
 
 I bisected from v3.17 until 3.18-rc1. But 3.18-rc2 and the latest
 mainline (f7e87a44ef60ad379e39b45437604141453bf0ec) still have the same
 problem
 
 btw i did more tests and this is not EVA specific. A maltaup_defconfig
 fails in the same way. I suspect all malta*_defconfigs will fail in a
 similar way which makes it probably easier for you to reproduce it on a
 QEMU.
 

sorry maltaup_defconfig does not fail. maltasmvp_defconfig does. So it
might be a similar problem like the one fixed in
85c9f4b04a08f6bc770b77530c22d04103468b8f

-- 
markos
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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