Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Mohamed Mediouni]

> On 21 Jan 2021, at 19:15, Marc Zyngier  wrote:
> 
> On 2021-01-21 17:55, Will Deacon wrote:
>> On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
>>> On 2021-01-21 15:12, Mohamed Mediouni wrote:
>>>> Please ignore that patch.
>>>> 
>>>> It turns out that the PCIe controller on Apple M1 expects posted
>>>> writes and so the memory range for it ought to be set nGnRE.
>>>> So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.
>>>> 
>>>> The MAIR approach isn’t adequate for such a thing, so we’ll have to
>>>> look elsewhere.
>>> Well, there isn't many alternative to having a memory type defined
>>> in MAIR if you want to access your PCIe devices with specific
>>> semantics.
>>> It probably means defining a memory type for PCI only, but:
>>> - we only have a single free MT entry, and I'm not sure we can
>>> afford to waste this on a specific platform (can we re-purpose
>>> GRE instead?),
>> We already have an nGnRnE MAIR for config space accesses.
> 
> I'm confused. If M1 needs nGnRE for PCI, and overrides nGnRE to nE
> for its in-SoC accesses, where does nGnRE goes?
> 
> Or do you propose that it is the page tables that get a different
> MT index?
> 

That MAIR patch that I added overrides nGnRE accesses to nGnRnE.

Linux tries to access to those SoC devices using nGnRE as the device
memory type without that workaround.

Maybe have a device tree property to override the used device memory type
for a given device on the SoC? Or that’s too big for what’s at the end just one 
particular set of SoCs?

But what the hardware wants is accesses to in-SoC devices being nGnRnE
and access to the PCIe BARs being nGnRE.

So both have to be supported…

>   M.
> -- 
> Jazz is not dead. It just smells funny...

Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

> On 21 Jan 2021, at 18:37, Rob Herring  wrote:
> 
> On Thu, Jan 21, 2021 at 10:43 AM Mohamed Mediouni
>  wrote:
>>> On 21 Jan 2021, at 17:40, Rob Herring  wrote:
>>> On Thu, Jan 21, 2021 at 6:52 AM Mohamed Mediouni
>>>  wrote:
>>>>> On 21 Jan 2021, at 13:44, Arnd Bergmann  wrote:
>>>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>>>>>  wrote:
> 
> [...]
> 
>>>>>> @@ -186,8 +325,11 @@ static int __init apple_aic_init(struct device_node 
>>>>>> *node,
>>>>>> if (WARN(!aic.base, "unable to map aic registers\n"))
>>>>>> return -EINVAL;
>>>>>> 
>>>>>> +   aic.fast_ipi = of_property_read_bool(node, "fast-ipi");
>>>>> 
>>>>> Where is this property documented, and what decides which one to use?
>>>> It’s getting documented in the next patch set.
>>>> 
>>>> This property is there to enable support for older iPhone processors
>>>> later on, some of which do not have fast IPI support.
>>>> 
>>>> On Apple M1, fast-ipi is always on.
>>> 
>>> This should be implied by the compatible string which needs to be more
>>> specific and include the SoC name.
>>> 
>>> Rob
>> 
>> Then we’ll eventually have two aic compatible strings, aic which is 
>> compatible
>> with Apple A7 onwards and aicv2 which is a superset with fast IPI (introduced
>> on the Apple A11, 3 years ago, with no further programmer-visible changes 
>> since
>> then).
>> 
>> Does that look right?
> 
> If we did this from the start, it would evolve like this:
> 
> A7: "AAPL,a7-aic"
> A8: "AAPL,a8-aic", "AAPL,a7-aic"  # Read this as A8 AIC is backwards
> compatible with A7 AIC
> A9: "AAPL,a9-aic", "AAPL,a7-aic"
> 
> A11: "AAPL,a11-aic", "AAPL,a7-aic"
> 
> If the A11 version could work on an OS that only supported the
> original model (sounds like this is the case) Or if it's not backwards
> compatible:
> 

The A11 AIC indeed can be used by older drivers that aren’t aware
of the fast IPI path introduced on A11 just fine.

> A11: "AAPL,a11-aic"
> 
> If the A11 is different and not backwards compatible.
> 
> Then M1 could be:
> 
> M1: "AAPL,m1-aic", "AAPL,a11-aic"
> 
> Or to even support an OS with only v1 support:
> 
> M1: "AAPL,m1-aic", "AAPL,a11-aic", "AAPL,a7-aic"
> 
> You don't really need the fallback here because there isn't any
> existing OS support and the baseline is the M1.
> 
> If you want to have generic fallback compatible strings with versions,
> that's fine too. I'm not really a fan of version numbers that are just
> made up by the binding author though. Most SoC vendors don't have
> rigorous versioning of their IP and those that do seem to have a new
> version on every SoC.
> 
> The important part is *always* having an SoC specific compatible so
> you can deal with any quirk or feature without having to change the
> DTB. Everyone says blocks are 'the same' until they aren’t.
> 
Is it fine if such a SoC-specific compatible is present but with having
the driver only know about AAPL,a11-aic for example?
(To just have it when it’d be needed if ever in the future, but not uselessly
add entries to the driver that will not be currently used)

On a tangent:

The internal naming scheme used by Apple is off-by-one:

Apple A14 for example is Apple H13P (H-series 13th gen processor, Phone)
Apple M1 is Apple H13G (H-series 13th gen, G series)
(And Apple A12X is Apple H11G for example, with A12 being H11P)

Should we bother with those or use the marketing names? Especially because
the beefier SoCs might not be of the H series anyway… as the internal scheme
reveals that M1 could as well have been an A14X.

And there’s also the other internal naming scheme:
Apple A12 being t8020, Apple A12X being t8027
Apple A14 being t8101
Apple M1 being t8103

T there means the foundry at which the chip was manufactured, in the cases 
above TSMC.

Of course Apple itself uses both… with the marketing name being nowhere in 
their device
trees.

Thank you,

> Rob

Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

> On 21 Jan 2021, at 17:40, Rob Herring  wrote:
> 
> On Thu, Jan 21, 2021 at 6:52 AM Mohamed Mediouni
>  wrote:
>> 
>> 
>> 
>>> On 21 Jan 2021, at 13:44, Arnd Bergmann  wrote:
>>> 
>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>>>  wrote:
>>> 
>>>> +#ifdef CONFIG_SMP
>>>> +static void apple_aic_ipi_send_mask(struct irq_data *d,
>>>> +   const struct cpumask *mask)
>>> 
>>> Not sure we care about the #ifdef here, given that arch/arm64 does not
>>> allow building a kernel without CONFIG_SMP.
>>> 
>>>> +   /*
>>>> + * Ensure that stores to Normal memory are visible to the
>>>> + * other CPUs before issuing the IPI.
>>>> + */
>>>> +   wmb();
>>>> +
>>>> +   for_each_cpu (cpu, mask) {
>>>> +   smp_mb__before_atomic();
>>>> +   atomic_or(1u << irqnr, per_cpu_ptr(&aic_ipi_mask, cpu));
>>>> +   smp_mb__after_atomic();
>>>> +   lcpu = get_cpu();
>>>> +   if (aic.fast_ipi) {
>>>> +   if ((lcpu >> 2) == (cpu >> 2))
>>>> +   write_sysreg(cpu & 3, SR_APPLE_IPI_LOCAL);
>>>> +   else
>>>> +   write_sysreg((cpu & 3) | ((cpu >> 2) << 
>>>> 16),
>>>> +SR_APPLE_IPI_REMOTE);
>>>> +   } else
>>>> +   writel(lcpu == cpu ? REG_IPI_FLAG_SELF :
>>>> +  (REG_IPI_FLAG_OTHER << 
>>>> cpu),
>>>> +  aic.base + REG_IPI_SET);
>>>> +   put_cpu();
>>>> +   }
>>>> +
>>>> +   /* Force the above writes to be executed */
>>>> +   if (aic.fast_ipi)
>>>> +   isb();
>>>> +}
>>> 
>>> Since this just loops over all CPUs, I'd probably just turn it into
>>> an ipi_send_single() callback and have the caller do the
>>> loop for simplicity.
>>> 
>>> I also have the feeling that splitting one hardware IPI into multiple
>>> logical interrupts, which are then all registered by the same irq
>>> handler adds a little more complexity than necessary.
>>> 
>>> Changing this would of course require modifications to
>>> arch/arm64/kernel/smp.c, which is hardwired to use
>>> CONFIG_GENERIC_IRQ_IPI in smp_cross_call(), and allowing
>>> a different code path there may be worse than emulating an
>>> irqchip.
>>> 
>>>> @@ -186,8 +325,11 @@ static int __init apple_aic_init(struct device_node 
>>>> *node,
>>>>  if (WARN(!aic.base, "unable to map aic registers\n"))
>>>>  return -EINVAL;
>>>> 
>>>> +   aic.fast_ipi = of_property_read_bool(node, "fast-ipi");
>>> 
>>> Where is this property documented, and what decides which one to use?
>> It’s getting documented in the next patch set.
>> 
>> This property is there to enable support for older iPhone processors
>> later on, some of which do not have fast IPI support.
>> 
>> On Apple M1, fast-ipi is always on.
> 
> This should be implied by the compatible string which needs to be more
> specific and include the SoC name.
> 
> Rob

Then we’ll eventually have two aic compatible strings, aic which is compatible
with Apple A7 onwards and aicv2 which is a superset with fast IPI (introduced 
on the Apple A11, 3 years ago, with no further programmer-visible changes since 
then).

Does that look right?

Thank you, 

Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

> On 21 Jan 2021, at 16:09, Arnd Bergmann  wrote:
> 
> On Thu, Jan 21, 2021 at 3:10 PM Marc Zyngier  wrote:
>> On 2021-01-21 13:34, Mohamed Mediouni wrote:
>>>> On 21 Jan 2021, at 14:22, Marc Zyngier  wrote:
>>> Because UART access adapters for the new M1 Macs aren’t plentiful
>>> at all, I actually use this for development, with iPhones which have
>>> much more easy to buy Lightning-to-UART adapters.
>>> 
>>> (That’s why the old implementation is there too)
>>> 
>>> Might be worth splitting the new one to a new commit though...
>> 
>> This series is supposed to cover M1 only, and adding extra support
>> as part of it is only likely to make the code harder to review.
>> 
>> I'd rather you focus on a single IPI interface (fast or slow,
>> I don't really care). Extra features can come in later.
> 
> Agreed. The slow interface is probably easier to start with,
> because it avoids hooking into the FIQ, so the FIQ can be
> completely decoupled from AIC and just used for the timer.
> 
> Maybe there is even a way to use more than one hardware IPI in
> the AIC?
> 
>   Arnd
Hello,

Decided to only have only the slow interface in the second patch series.

Thank you,

Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Mohamed Mediouni]

> On 21 Jan 2021, at 13:47, Will Deacon  wrote:
> 
> On Thu, Jan 21, 2021 at 11:44:23AM +, Marc Zyngier wrote:
>> On 2021-01-21 11:27, Will Deacon wrote:
>>> On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
>>>> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious
>>>> hardware quirk.
>>>> 
>>>> On Apple processors, writes using the nGnRE device memory type get
>>>> dropped in flight,
>>>> getting to nowhere.
>>>> 
>>>> Signed-off-by: Stan Skowronek 
>>>> Signed-off-by: Mohamed Mediouni 
>>>> ---
>>>> arch/arm64/mm/proc.S | 26 ++
>>>> 1 file changed, 26 insertions(+)
>>>> 
>>>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>>>> index 1f7ee8c8b7b8..06436916f137 100644
>>>> --- a/arch/arm64/mm/proc.S
>>>> +++ b/arch/arm64/mm/proc.S
>>>> @@ -51,6 +51,25 @@
>>>> #define TCR_KASAN_HW_FLAGS 0
>>>> #endif
>>>> 
>>>> +#ifdef CONFIG_ARCH_APPLE
>>>> +
>>>> +/*
>>>> + * Apple cores appear to black-hole writes done with nGnRE.
>>>> + * We settled on a work-around that uses MAIR vs changing every
>>>> single user of
>>>> + * nGnRE across the arm64 code.
>>>> + */
>>>> +
>>>> +#define MAIR_EL1_SET_APPLE
>>>> \
>>>> +  (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |  \
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) |   \
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |\
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |  \
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |\
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |  \
>>>> +   MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
>>>> +
>>>> +#endif
>>>> +
>>>> /*
>>>>  * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal
>>>> memory and
>>>>  * changed during __cpu_setup to Normal Tagged if the system
>>>> supports MTE.
>>>> @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup)
>>>> * Memory region attributes
>>>> */
>>>>mov_q   x5, MAIR_EL1_SET
>>>> +#ifdef CONFIG_ARCH_APPLE
>>>> +  mrs x0, MIDR_EL1
>>>> +  lsr w0, w0, #24
>>>> +  mov_q   x1, MAIR_EL1_SET_APPLE
>>>> +  cmp x0, #0x61   // 0x61 = Implementer: Apple
>>>> +  cselx5, x1, x5, eq
>>> 
>>> Why does this need to be done so early? It would be a lot cleaner if we
>>> could detect this in a similar fashion to other errata and update the
>>> MAIR
>>> appropriately. If that's not possible because of early IO mappings
>>> (which
>>> ones?), then we could instead initialise to nGnRnE unconditionally, but
>>> relax it to nGnRE if we detect that we _don't_ have the erratum.
>> 
>> Would that imply another round-trip into the idmap, much like we do
>> when we switch to non-global mappings? Or do you expect that we can change
>> the MAIR with live mappings?
> 
> I think we should be able to change it live and then invalidate the TLB. At
> least, my reading of the BBM requirements suggests that it isn't required
> for changing between different types of device memory. I can seek
> clarification from Arm if necessary.
> 
Please ignore that patch.

It turns out that the PCIe controller on Apple M1 expects posted writes and so 
the memory range for it ought to be set nGnRE. 
So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.

The MAIR approach isn’t adequate for such a thing, so we’ll have to look 
elsewhere.

Thank you,
> Will

Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

> On 21 Jan 2021, at 14:22, Marc Zyngier  wrote:
> 
> On 2021-01-21 12:50, Mohamed Mediouni wrote:
>>> On 21 Jan 2021, at 13:44, Arnd Bergmann  wrote:
>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
> 
> [...]
> 
>>>> +   aic.fast_ipi = of_property_read_bool(node, "fast-ipi");
>>> Where is this property documented, and what decides which one to use?
>> It’s getting documented in the next patch set.
>> This property is there to enable support for older iPhone processors
>> later on, some of which do not have fast IPI support.
>> On Apple M1, fast-ipi is always on.
> 
> Then please focus on a single implementation. Additional features can
> always be merged later once something is up and running.
> 
> Also, there sysregs can be detected by matching the MIDR, so I don't
> think we need a DT property for that.
> 
> Thanks,
> 
Because UART access adapters for the new M1 Macs aren’t plentiful
at all, I actually use this for development, with iPhones which have 
much more easy to buy Lightning-to-UART adapters.

(That’s why the old implementation is there too)

Might be worth splitting the new one to a new commit though...

Thank you,
>M.
> -- 
> Jazz is not dead. It just smells funny...

Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

> On 21 Jan 2021, at 13:44, Arnd Bergmann  wrote:
> 
> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>  wrote:
> 
>> +#ifdef CONFIG_SMP
>> +static void apple_aic_ipi_send_mask(struct irq_data *d,
>> +   const struct cpumask *mask)
> 
> Not sure we care about the #ifdef here, given that arch/arm64 does not
> allow building a kernel without CONFIG_SMP.
> 
>> +   /*
>> + * Ensure that stores to Normal memory are visible to the
>> + * other CPUs before issuing the IPI.
>> + */
>> +   wmb();
>> +
>> +   for_each_cpu (cpu, mask) {
>> +   smp_mb__before_atomic();
>> +   atomic_or(1u << irqnr, per_cpu_ptr(&aic_ipi_mask, cpu));
>> +   smp_mb__after_atomic();
>> +   lcpu = get_cpu();
>> +   if (aic.fast_ipi) {
>> +   if ((lcpu >> 2) == (cpu >> 2))
>> +   write_sysreg(cpu & 3, SR_APPLE_IPI_LOCAL);
>> +   else
>> +   write_sysreg((cpu & 3) | ((cpu >> 2) << 16),
>> +SR_APPLE_IPI_REMOTE);
>> +   } else
>> +   writel(lcpu == cpu ? REG_IPI_FLAG_SELF :
>> +  (REG_IPI_FLAG_OTHER << 
>> cpu),
>> +  aic.base + REG_IPI_SET);
>> +   put_cpu();
>> +   }
>> +
>> +   /* Force the above writes to be executed */
>> +   if (aic.fast_ipi)
>> +   isb();
>> +}
> 
> Since this just loops over all CPUs, I'd probably just turn it into
> an ipi_send_single() callback and have the caller do the
> loop for simplicity.
> 
> I also have the feeling that splitting one hardware IPI into multiple
> logical interrupts, which are then all registered by the same irq
> handler adds a little more complexity than necessary.
> 
> Changing this would of course require modifications to
> arch/arm64/kernel/smp.c, which is hardwired to use
> CONFIG_GENERIC_IRQ_IPI in smp_cross_call(), and allowing
> a different code path there may be worse than emulating an
> irqchip.
> 
>> @@ -186,8 +325,11 @@ static int __init apple_aic_init(struct device_node 
>> *node,
>>   if (WARN(!aic.base, "unable to map aic registers\n"))
>>   return -EINVAL;
>> 
>> +   aic.fast_ipi = of_property_read_bool(node, "fast-ipi");
> 
> Where is this property documented, and what decides which one to use?
It’s getting documented in the next patch set.

This property is there to enable support for older iPhone processors
later on, some of which do not have fast IPI support.

On Apple M1, fast-ipi is always on.

Thank you,
>   Arnd

Re: [RFC PATCH 2/7] arm64: kernel: Add a WFI hook.

[Mohamed Mediouni]

> On 21 Jan 2021, at 11:52, Arnd Bergmann  wrote:
> 
> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>  wrote:
>> --- a/arch/arm64/kernel/cpu_ops.c
>> +++ b/arch/arm64/kernel/cpu_ops.c
> 
>> #if defined(CONFIG_STACKPROTECTOR) && 
>> !defined(CONFIG_STACKPROTECTOR_PER_TASK)
>> #include 
>> @@ -74,8 +75,14 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, 
>> const char *cmd);
>> 
>> static void noinstr __cpu_do_idle(void)
>> {
>> -   dsb(sy);
>> -   wfi();
>> +   const struct cpu_operations *ops = get_cpu_ops(task_cpu(current));
>> +
>> +   if (ops->cpu_wfi) {
>> +   ops->cpu_wfi();
>> +   } else {
>> +   dsb(sy);
>> +   wfi();
>> +   }
>> }
> 
> I think the correct place to put this would be a platform specific driver
> in drivers/cpuidle/ instead of an added low-level callback in the
> default idle function and a custom cpu_operations structure.
Can we make sure that wfi never gets called even on early
boot when using a cpuidle driver?

Thank you,
> 
>   Arnd

[RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple AIC driver.

[Mohamed Mediouni]

From: Stan Skowronek 

This includes IPI support and a workaround for non-working WFI on
Apple processors.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 drivers/irqchip/irq-apple-aic.c | 177 +---
 1 file changed, 165 insertions(+), 12 deletions(-)

diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
index c601bc4b501a..ce4e39d56fcf 100644
--- a/drivers/irqchip/irq-apple-aic.c
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -17,6 +17,7 @@

 #include 
 #include 
+#include 

 #define REG_ID_REVISION 0x
 #define REG_ID_CONFIG 0x0004
@@ -53,12 +54,17 @@
 #define REG_PERCPU(r, c)   
\
((r) + REG_CPU_REGION - REG_CPU_LOCAL + ((c) << REG_CPU_SHIFT))

+#define NUM_IPI 8
+
 static struct aic_chip_data {
void __iomem *base;
struct irq_domain *domain;
unsigned int num_irqs;
+   bool fast_ipi;
 } aic;

+static DEFINE_PER_CPU(atomic_t, aic_ipi_mask);
+
 static void apple_aic_irq_mask(struct irq_data *d)
 {
writel(REG_IRQ_xABLE_MASK(d->hwirq),
@@ -78,18 +84,71 @@ static struct irq_chip apple_aic_irq_chip = {
.irq_unmask = apple_aic_irq_unmask,
 };

-static void apple_aic_fiq_mask(struct irq_data *d)
+static void apple_aic_fiq_ipi_mask(struct irq_data *d)
 {
 }

-static void apple_aic_fiq_unmask(struct irq_data *d)
+static void apple_aic_fiq_ipi_unmask(struct irq_data *d)
 {
 }

 static struct irq_chip apple_aic_irq_chip_fiq = {
.name = "apple_aic_fiq",
-   .irq_mask = apple_aic_fiq_mask,
-   .irq_unmask = apple_aic_fiq_unmask,
+   .irq_mask = apple_aic_fiq_ipi_mask,
+   .irq_unmask = apple_aic_fiq_ipi_unmask,
+};
+
+#define SR_APPLE_IPI_LOCAL s3_5_c15_c0_0
+#define SR_APPLE_IPI_REMOTE s3_5_c15_c0_1
+#define SR_APPLE_IPI_STAT s3_5_c15_c1_1
+
+#ifdef CONFIG_SMP
+static void apple_aic_ipi_send_mask(struct irq_data *d,
+   const struct cpumask *mask)
+{
+   int cpu, lcpu;
+   int irqnr = d->hwirq - (aic.num_irqs + 2);
+
+   if (WARN_ON(irqnr < 0 || irqnr >= NUM_IPI))
+   return;
+
+   /*
+ * Ensure that stores to Normal memory are visible to the
+ * other CPUs before issuing the IPI.
+ */
+   wmb();
+
+   for_each_cpu (cpu, mask) {
+   smp_mb__before_atomic();
+   atomic_or(1u << irqnr, per_cpu_ptr(&aic_ipi_mask, cpu));
+   smp_mb__after_atomic();
+   lcpu = get_cpu();
+   if (aic.fast_ipi) {
+   if ((lcpu >> 2) == (cpu >> 2))
+   write_sysreg(cpu & 3, SR_APPLE_IPI_LOCAL);
+   else
+   write_sysreg((cpu & 3) | ((cpu >> 2) << 16),
+SR_APPLE_IPI_REMOTE);
+   } else
+   writel(lcpu == cpu ? REG_IPI_FLAG_SELF :
+  (REG_IPI_FLAG_OTHER << cpu),
+  aic.base + REG_IPI_SET);
+   put_cpu();
+   }
+
+   /* Force the above writes to be executed */
+   if (aic.fast_ipi)
+   isb();
+}
+#else
+#define apple_aic_ipi_send_mask NULL
+#endif
+
+static struct irq_chip apple_aic_irq_chip_ipi = {
+   .name = "apple_aic_ipi",
+   .irq_mask = apple_aic_fiq_ipi_mask,
+   .irq_unmask = apple_aic_fiq_ipi_unmask,
+   .ipi_send_mask = apple_aic_ipi_send_mask,
 };

 static int apple_aic_irq_domain_xlate(struct irq_domain *d,
@@ -98,16 +157,27 @@ static int apple_aic_irq_domain_xlate(struct irq_domain *d,
  unsigned long *out_hwirq,
  unsigned int *out_type)
 {
-   if (intspec[0]) { /* FIQ */
+   switch (intspec[0]) {
+   case 0: /* IRQ */
+   if (intspec[1] >= aic.num_irqs)
+   return -EINVAL;
+   if (out_hwirq)
+   *out_hwirq = intspec[1];
+   break;
+   case 1: /* FIQ */
if (intspec[1] >= 2)
return -EINVAL;
if (out_hwirq)
*out_hwirq = aic.num_irqs + intspec[1];
-   } else {
-   if (intspec[1] >= aic.num_irqs)
+   break;
+   case 2: /* IPI */
+   if (intspec[1] >= NUM_IPI)
return -EINVAL;
if (out_hwirq)
-   *out_hwirq = intspec[1];
+   *out_hwirq = aic.num_irqs + 2 + intspec[1];
+   break;
+   default:
+   return -EINVAL;
}

if (out_type)
@@ -118,7 +188,13 @@ static int apple_aic_irq_domain_xlate(struct irq_domain *d,
 static int apple_aic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 

[RFC PATCH 2/7] arm64: kernel: Add a WFI hook.

[Mohamed Mediouni]

From: Stan Skowronek 

WFI drops register state on Apple Silicon for SMP systems.

This hook will be used for a hardware workaround in the
Apple CPU start driver.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 arch/arm64/include/asm/cpu_ops.h |  2 ++
 arch/arm64/kernel/cpu_ops.c  |  6 ++
 arch/arm64/kernel/process.c  | 11 +--
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index e95c4df83911..4be0fc5bcaf9 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -23,6 +23,7 @@
  * @cpu_boot:  Boots a cpu into the kernel.
  * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary
  * synchronisation. Called from the cpu being booted.
+ * @cpu_wfi:Optionally, replace calls to WFI in default idle with this.
  * @cpu_can_disable: Determines whether a CPU can be disabled based on
  * mechanism-specific information.
  * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific
@@ -43,6 +44,7 @@ struct cpu_operations {
int (*cpu_prepare)(unsigned int);
int (*cpu_boot)(unsigned int);
void(*cpu_postboot)(void);
+   void(*cpu_wfi)(void);
 #ifdef CONFIG_HOTPLUG_CPU
bool(*cpu_can_disable)(unsigned int cpu);
int (*cpu_disable)(unsigned int cpu);
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index e133011f64b5..6979fc4490b2 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -19,12 +19,18 @@ extern const struct cpu_operations smp_spin_table_ops;
 extern const struct cpu_operations acpi_parking_protocol_ops;
 #endif
 extern const struct cpu_operations cpu_psci_ops;
+#ifdef CONFIG_ARCH_APPLE
+extern const struct cpu_operations cpu_apple_start_ops;
+#endif

 static const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;

 static const struct cpu_operations *const dt_supported_cpu_ops[] __initconst = 
{
&smp_spin_table_ops,
&cpu_psci_ops,
+#ifdef CONFIG_ARCH_APPLE
+   &cpu_apple_start_ops,
+#endif
NULL,
 };

diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 34ec400288d0..611c639e20be 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -57,6 +57,7 @@
 #include 
 #include 
 #include 
+#include 

 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
 #include 
@@ -74,8 +75,14 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const 
char *cmd);

 static void noinstr __cpu_do_idle(void)
 {
-   dsb(sy);
-   wfi();
+   const struct cpu_operations *ops = get_cpu_ops(task_cpu(current));
+
+   if (ops->cpu_wfi) {
+   ops->cpu_wfi();
+   } else {
+   dsb(sy);
+   wfi();
+   }
 }

 static void noinstr __cpu_do_idle_irqprio(void)
--
2.29.2

[RFC PATCH 5/7] arm64/Kconfig: Add Apple Silicon SoC platform

[Mohamed Mediouni]

From: Stan Skowronek 

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 arch/arm64/Kconfig.platforms | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6eecdef538bd..cc52519d4f67 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -328,4 +328,11 @@ config ARCH_ZYNQMP
help
  This enables support for Xilinx ZynqMP Family

+config ARCH_APPLE
+   bool "Apple Silicon SoC Family"
+   select APPLE_AIC
+   help
+ This enables support for Apple processors present
+ on Mac computers.
+
 endmenu
--
2.29.2

Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Mohamed Mediouni]

> On 20 Jan 2021, at 17:47, Alexander Graf  wrote:
> 
> On 20.01.21 14:27, Mohamed Mediouni wrote:
>> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware 
>> quirk.
>> On Apple processors, writes using the nGnRE device memory type get dropped 
>> in flight,
>> getting to nowhere.
>> Signed-off-by: Stan Skowronek 
>> Signed-off-by: Mohamed Mediouni 
>> ---
>>  arch/arm64/mm/proc.S | 26 ++
>>  1 file changed, 26 insertions(+)
>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>> index 1f7ee8c8b7b8..06436916f137 100644
>> --- a/arch/arm64/mm/proc.S
>> +++ b/arch/arm64/mm/proc.S
>> @@ -51,6 +51,25 @@
>>  #define TCR_KASAN_HW_FLAGS 0
>>  #endif
>> +#ifdef CONFIG_ARCH_APPLE
> 
> Is there any particular reason for this #ifdef?
> 
> 
> Alex
> 
Not a particular reason, as we explicitly check for the implementer ID. However,
without CONFIG_ARCH_APPLE, other parts of the support for Apple CPUs
will not be available anyway.
>> +
>> +/*
>> + * Apple cores appear to black-hole writes done with nGnRE.
>> + * We settled on a work-around that uses MAIR vs changing every single user 
>> of
>> + * nGnRE across the arm64 code.
>> + */
>> +
>> +#define MAIR_EL1_SET_APPLE  \
>> +(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |  \
>> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) |   \
>> + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |\
>> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |  \
>> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |\
>> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |  \
>> + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
>> +
>> +#endif
>> +
>>  /*
>>   * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory 
>> and
>>   * changed during __cpu_setup to Normal Tagged if the system supports MTE.
>> @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup)
>>   * Memory region attributes
>>   */
>>  mov_q   x5, MAIR_EL1_SET
>> +#ifdef CONFIG_ARCH_APPLE
>> +mrs x0, MIDR_EL1
>> +lsr w0, w0, #24
>> +mov_q   x1, MAIR_EL1_SET_APPLE
>> +cmp x0, #0x61   // 0x61 = Implementer: Apple
>> +cselx5, x1, x5, eq
>> +#endif
>>  #ifdef CONFIG_ARM64_MTE
>>  mte_tcr .reqx20
>> --
>> 2.29.2
> 
> 
> 
> 
> Amazon Development Center Germany GmbH
> Krausenstr. 38
> 10117 Berlin
> Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
> Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
> Sitz: Berlin
> Ust-ID: DE 289 237 879

Re: [RFC PATCH 4/7] irqchip/apple-aic: Add support for Apple AIC

[Mohamed Mediouni]

> On 20 Jan 2021, at 18:11, Alexander Graf  wrote:
> 
> On 20.01.21 14:27, Mohamed Mediouni wrote:
>> From: Stan Skowronek 
>> Apple SoCs use the Apple AIC interrupt controller.
>> The Arm architectural timers is wired over FIQ on that hardware.
>> Signed-off-by: Stan Skowronek 
>> Signed-off-by: Mohamed Mediouni 
>> ---
>>  .../interrupt-controller/apple,aic.yaml   |  49 
>>  MAINTAINERS   |   6 +
>>  drivers/irqchip/Kconfig   |   6 +
>>  drivers/irqchip/Makefile  |   1 +
>>  drivers/irqchip/irq-apple-aic.c   | 211 ++
>>  5 files changed, 273 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
>>  create mode 100644 drivers/irqchip/irq-apple-aic.c
>> diff --git 
>> a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml 
>> b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
>> new file mode 100644
>> index ..e615eaaca869
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
>> @@ -0,0 +1,49 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Apple Advanced Interrupt Controller (AIC)
>> +
>> +description:
>> +  Interrupt controller present on Apple processors. AIC
>> +  is used by Apple on their AArch64 SoCs since the Apple A7.
>> +
>> +maintainers:
>> +  - Stan Skowronek 
>> +
>> +properties:
>> +  compatible:
>> +items:
>> +  - const: apple,aic
>> +
>> +  reg:
>> +maxItems: 1
>> +
>> +  '#interrupt-cells':
>> +const: 3
>> +
>> +  interrupt-controller: true
>> +
>> +  fast-ipi:
>> +description:
>> +  Fast IPI support.
>> +
>> +required:
>> +  - compatible
>> +  - '#interrupt-cells'
>> +  - interrupt-controller
>> +  - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +aic: interrupt-controller@23b10 {
>> + compatible = "apple,aic";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0x2 0x3b10 0x0 0x8000>;
>> + fast-ipi;
>> + };
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 00836f6452f0..e609ede99dd4 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1218,6 +1218,12 @@ T:git 
>> git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor
>>  F:  Documentation/admin-guide/LSM/apparmor.rst
>>  F:  security/apparmor/
>> +APPLE ADVANCED INTERRUPT CONTROLLER DRIVER
>> +M:  Stan Skowronek 
> 
> Signing someone else up for maintainership is ... unusual :). Do you have buy 
> in from Stan that he'll be responsive and handle patch reviews?

Yeah, I asked Corellium about it explicitly. :)

>> +L:  linux-arm-ker...@lists.infradead.org
>> +S:  Maintained
>> +F:  drivers/irqchip/irq-apple-aic.c
>> +
> 
> 
> Alex
> 
> 
> 
> Amazon Development Center Germany GmbH
> Krausenstr. 38
> 10117 Berlin
> Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
> Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
> Sitz: Berlin
> Ust-ID: DE 289 237 879

Re: [PATCH 1/3] arm64/kernel: FIQ support

[Mohamed Mediouni]

> On 20 Jan 2021, at 14:16, Marc Zyngier  wrote:
> 
> Hi Mohamed,
> 
> On 2021-01-20 11:36, Mohamed Mediouni wrote:
>> From: Stan Skowronek 
>> On Apple processors, the timer is wired through FIQ.
> 
> Which timer? There are at least 3, potentially 4 timers per CPU
> that can fire.
This is about the Arm architectural timers.
>> As such, add FIQ support to the kernel.
>> Signed-off-by: Stan Skowronek 
> 
> Missing SoB from the sender.
> 
Fixed in the RFC.
>> ---
>> arch/arm64/include/asm/arch_gicv3.h |  2 +-
>> arch/arm64/include/asm/assembler.h  |  8 ++--
>> arch/arm64/include/asm/daifflags.h  |  4 +-
>> arch/arm64/include/asm/irq.h|  4 ++
>> arch/arm64/include/asm/irqflags.h   |  6 +--
>> arch/arm64/kernel/entry.S   | 74 ++---
>> arch/arm64/kernel/irq.c | 14 ++
>> arch/arm64/kernel/process.c |  2 +-
>> 8 files changed, 97 insertions(+), 17 deletions(-)
>> diff --git a/arch/arm64/include/asm/arch_gicv3.h
>> b/arch/arm64/include/asm/arch_gicv3.h
>> index 880b9054d75c..934b9be582d2 100644
>> --- a/arch/arm64/include/asm/arch_gicv3.h
>> +++ b/arch/arm64/include/asm/arch_gicv3.h
>> @@ -173,7 +173,7 @@ static inline void gic_pmr_mask_irqs(void)
>> static inline void gic_arch_enable_irqs(void)
>> {
>> -asm volatile ("msr daifclr, #2" : : : "memory");
>> +asm volatile ("msr daifclr, #3" : : : "memory");
> 
> If I trust the persistent rumour, this system doesn't have a GIC.
> Why this change?
> 
Will ask about why GIC functions were changed too… and yeah
This exclusively has an Apple AIC interrupt controller.

>> #endif /* __ASSEMBLY__ */
>> diff --git a/arch/arm64/include/asm/assembler.h
>> b/arch/arm64/include/asm/assembler.h
>> index bf125c591116..6fe55713dfe0 100644
>> --- a/arch/arm64/include/asm/assembler.h
>> +++ b/arch/arm64/include/asm/assembler.h
>> @@ -40,9 +40,9 @@
>>  msr daif, \flags
>>  .endm
>> -/* IRQ is the lowest priority flag, unconditionally unmask the rest. */
>> -.macro enable_da_f
>> -msr daifclr, #(8 | 4 | 1)
>> +/* IRQ/FIQ is the lowest priority flag, unconditionally unmask the 
>> rest. */
>> +.macro enable_da
>> +msr daifclr, #(8 | 4)
> 
> This cannot be unconditional. This potentially changes existing behaviours,
> and I'd feel a lot safer if FIQ was only messed with on that specific HW.
> 
> I have the feeling that this should be detected on the boot CPU and patched
> before any interrupt can fire.
> 
Could alternatives be the proper mechanism for this?
>>  .endm
>> /*
>> @@ -50,7 +50,7 @@
>>  */
>>  .macro  save_and_disable_irq, flags
>>  mrs \flags, daif
>> -msr daifset, #2
>> +msr daifset, #3
>>  .endm
>>  .macro  restore_irq, flags
>> diff --git a/arch/arm64/include/asm/daifflags.h
>> b/arch/arm64/include/asm/daifflags.h
>> index 1c26d7baa67f..44de96c7fb1a 100644
>> --- a/arch/arm64/include/asm/daifflags.h
>> +++ b/arch/arm64/include/asm/daifflags.h
>> @@ -13,8 +13,8 @@
>> #include 
>> #define DAIF_PROCCTX 0
>> -#define DAIF_PROCCTX_NOIRQ  PSR_I_BIT
>> -#define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT)
>> +#define DAIF_PROCCTX_NOIRQ  (PSR_I_BIT | PSR_F_BIT)
>> +#define DAIF_ERRCTX (PSR_I_BIT | PSR_F_BIT | PSR_A_BIT)
>> #define DAIF_MASK(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
>> diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
>> index b2b0c6405eb0..2d1537d3a245 100644
>> --- a/arch/arm64/include/asm/irq.h
>> +++ b/arch/arm64/include/asm/irq.h
>> @@ -13,5 +13,9 @@ static inline int nr_legacy_irqs(void)
>>  return 0;
>> }
>> +int set_handle_fiq(void (*handle_fiq)(struct pt_regs *));
>> +
>> +extern void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init;
> 
> I guess this is set from the root interrupt controller, which also
> will set handle_arch_irq? Why do we need two entry points? We have
> ISR_EL1 to find out what is pending. Isn't that enough?
> 
>> +
>> #endif /* !__ASSEMBLER__ */
>> #endif
>> diff --git a/arch/arm64/include/asm/irqflags.h
>> b/arch/arm64/include/asm/irqflags.h
>> index ff328e5bbb75..26d7f378113e 100644
>> --- a/arch/arm64/include/asm/irqflags.h
>> +++ b/arch/arm64/include/asm/irqflags.h
>> @@ -35,7 +35,7 @@ static inline void arch_local_irq_enable(void)
>>  }
>>  asm volatile(ALTERNATIVE(
>&g

[RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Mohamed Mediouni]

Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware 
quirk.

On Apple processors, writes using the nGnRE device memory type get dropped in 
flight,
getting to nowhere.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 arch/arm64/mm/proc.S | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 1f7ee8c8b7b8..06436916f137 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -51,6 +51,25 @@
 #define TCR_KASAN_HW_FLAGS 0
 #endif

+#ifdef CONFIG_ARCH_APPLE
+
+/*
+ * Apple cores appear to black-hole writes done with nGnRE.
+ * We settled on a work-around that uses MAIR vs changing every single user of
+ * nGnRE across the arm64 code.
+ */
+
+#define MAIR_EL1_SET_APPLE \
+   (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |  \
+MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) |   \
+MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |\
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |  \
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |\
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |  \
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
+
+#endif
+
 /*
  * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
  * changed during __cpu_setup to Normal Tagged if the system supports MTE.
@@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup)
 * Memory region attributes
 */
mov_q   x5, MAIR_EL1_SET
+#ifdef CONFIG_ARCH_APPLE
+   mrs x0, MIDR_EL1
+   lsr w0, w0, #24
+   mov_q   x1, MAIR_EL1_SET_APPLE
+   cmp x0, #0x61   // 0x61 = Implementer: Apple
+   cselx5, x1, x5, eq
+#endif
 #ifdef CONFIG_ARM64_MTE
mte_tcr .reqx20

--
2.29.2

[RFC PATCH 6/7] arm64: kernel: Apple CPU start driver

[Mohamed Mediouni]

From: Stan Skowronek 

This driver is needed to spawn CPUs for SMP
on Apple Silicon platforms.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 .../devicetree/bindings/arm/cpus.yaml |   1 +
 arch/arm64/kernel/Makefile|   1 +
 arch/arm64/kernel/apple_cpustart.c| 153 ++
 3 files changed, 155 insertions(+)
 create mode 100644 arch/arm64/kernel/apple_cpustart.c

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml 
b/Documentation/devicetree/bindings/arm/cpus.yaml
index 14cd727d3c4b..a6ff8cb3db1e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -176,6 +176,7 @@ properties:
 oneOf:
   # On ARM v8 64-bit this property is required
   - enum:
+  - apple
   - psci
   - spin-table
   # On ARM 32-bit systems this property is optional
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 86364ab6f13f..497f43ca7f0f 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_ARM64_RELOC_TEST)+= 
arm64-reloc-test.o
 arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o
 obj-$(CONFIG_CRASH_DUMP)   += crash_dump.o
 obj-$(CONFIG_CRASH_CORE)   += crash_core.o
+obj-$(CONFIG_ARCH_APPLE)+= apple_cpustart.o
 obj-$(CONFIG_ARM_SDE_INTERFACE)+= sdei.o
 obj-$(CONFIG_ARM64_PTR_AUTH)   += pointer_auth.o
 obj-$(CONFIG_ARM64_MTE)+= mte.o
diff --git a/arch/arm64/kernel/apple_cpustart.c 
b/arch/arm64/kernel/apple_cpustart.c
new file mode 100644
index ..41d049eaaec7
--- /dev/null
+++ b/arch/arm64/kernel/apple_cpustart.c
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 Corellium LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define MAGIC_UNLOCK 0xc5acce55
+
+struct cpu_apple_start_info {
+   void __iomem *pmgr_start;
+   u64 pmgr_start_size;
+   void __iomem *cputrc_rvbar;
+   void __iomem *dbg_unlock;
+};
+
+extern void apple_aic_cpu_prepare(unsigned int cpu);
+
+static int cpu_apple_start0_unlocked = 0;
+static DEFINE_PER_CPU(struct cpu_apple_start_info, cpu_apple_start_info);
+
+static int __init cpu_apple_start_init(unsigned int cpu)
+{
+   return 0;
+}
+
+static int cpu_apple_start_prepare(unsigned int cpu)
+{
+   struct device_node *node;
+   struct cpu_apple_start_info *info;
+
+   info = per_cpu_ptr(&cpu_apple_start_info, cpu);
+
+   if (info->pmgr_start && info->cputrc_rvbar && info->dbg_unlock)
+   return 0;
+
+   node = of_find_compatible_node(NULL, NULL, "apple,startcpu");
+   if (!node) {
+   pr_err("%s: missing startcpu node in device tree.\n", __func__);
+   return -EINVAL;
+   }
+
+   if (!info->pmgr_start) {
+   info->pmgr_start = of_iomap(node, cpu * 3);
+   if (!info->pmgr_start) {
+   pr_err("%s: failed to map start register for CPU %d.\n",
+  __func__, cpu);
+   return -EINVAL;
+   }
+   if (!of_get_address(node, cpu * 3, &info->pmgr_start_size,
+   NULL))
+   info->pmgr_start_size = 8;
+   }
+
+   if (!info->cputrc_rvbar) {
+   info->cputrc_rvbar = of_iomap(node, cpu * 3 + 1);
+   if (!info->cputrc_rvbar) {
+   pr_err("%s: failed to map reset address register for 
CPU %d.\n",
+  __func__, cpu);
+   return -EINVAL;
+   }
+   }
+
+   if (!info->dbg_unlock) {
+   info->dbg_unlock = of_iomap(node, cpu * 3 + 2);
+   if (!info->dbg_unlock) {
+   pr_err("%s: failed to map unlock register for CPU 
%d.\n",
+  __func__, cpu);
+   return -EINVAL;
+   }
+   }
+
+   if (cpu)
+   apple_aic_cpu_prepare(cpu);
+
+   return 0;
+}
+
+static int cpu_apple_start_boot(unsigned int cpu)
+{
+   struct cpu_apple_start_info *info;
+   unsigned long addr;
+
+   if (!cpu_apple_start0_unlocked) {
+   if (!cpu_apple_start_prepare(0)) {
+   info = per_cpu_ptr(&cpu_apple_start_info, 0);
+   writel(MAGIC_UNLOCK, info->dbg_unlock);
+   cpu_apple_start0_unlocked = 1;
+   } else
+   pr_err("%s: failed to unlock boot CPU\n", __func__);
+   }
+
+   info = per_cpu_ptr(&cpu_apple_start_info, cpu);

[RFC PATCH 4/7] irqchip/apple-aic: Add support for Apple AIC

[Mohamed Mediouni]

From: Stan Skowronek 

Apple SoCs use the Apple AIC interrupt controller.
The Arm architectural timers is wired over FIQ on that hardware.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 .../interrupt-controller/apple,aic.yaml   |  49 
 MAINTAINERS   |   6 +
 drivers/irqchip/Kconfig   |   6 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-apple-aic.c   | 211 ++
 5 files changed, 273 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
 create mode 100644 drivers/irqchip/irq-apple-aic.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml 
b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
new file mode 100644
index ..e615eaaca869
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple Advanced Interrupt Controller (AIC)
+
+description:
+  Interrupt controller present on Apple processors. AIC
+  is used by Apple on their AArch64 SoCs since the Apple A7.
+
+maintainers:
+  - Stan Skowronek 
+
+properties:
+  compatible:
+items:
+  - const: apple,aic
+
+  reg:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 3
+
+  interrupt-controller: true
+
+  fast-ipi:
+description:
+  Fast IPI support.
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - interrupt-controller
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+aic: interrupt-controller@23b10 {
+ compatible = "apple,aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2 0x3b10 0x0 0x8000>;
+ fast-ipi;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 00836f6452f0..e609ede99dd4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1218,6 +1218,12 @@ T:   git 
git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor
 F: Documentation/admin-guide/LSM/apparmor.rst
 F: security/apparmor/

+APPLE ADVANCED INTERRUPT CONTROLLER DRIVER
+M: Stan Skowronek 
+L: linux-arm-ker...@lists.infradead.org
+S: Maintained
+F: drivers/irqchip/irq-apple-aic.c
+
 APPLE BCM5974 MULTITOUCH DRIVER
 M: Henrik Rydberg 
 L: linux-in...@vger.kernel.org
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 94920a51c628..3aa9e711324b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -56,6 +56,12 @@ config ARM_GIC_V3_ITS_FSL_MC
depends on FSL_MC_BUS
default ARM_GIC_V3_ITS

+config APPLE_AIC
+   bool
+   select IRQ_DOMAIN_HIERARCHY
+   select GENERIC_IRQ_MULTI_HANDLER
+   select GENERIC_IRQ_EFFECTIVE_AFF_MASK
+
 config ARM_NVIC
bool
select IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0ac93bfaec61..2f5a9a0cf40f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_GIC_V3)  += irq-gic-v3.o 
irq-gic-v3-mbi.o irq-gic-common.o
 obj-$(CONFIG_ARM_GIC_V3_ITS)   += irq-gic-v3-its.o 
irq-gic-v3-its-platform-msi.o irq-gic-v4.o
 obj-$(CONFIG_ARM_GIC_V3_ITS_PCI)   += irq-gic-v3-its-pci-msi.o
 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC)+= irq-gic-v3-its-fsl-mc-msi.o
+obj-$(CONFIG_APPLE_AIC)+= irq-apple-aic.o
 obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
new file mode 100644
index ..c601bc4b501a
--- /dev/null
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Apple chip interrupt controller
+ *
+ * Copyright (C) 2020 Corellium LLC
+ * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define REG_ID_REVISION 0x
+#define REG_ID_CONFIG 0x0004
+#define REG_GLOBAL_CFG 0x0010
+#define REG_TIME_LO 0x0020
+#define REG_TIME_HI 0x0028
+#define REG_ID_CPUID 0x2000
+#define REG_IRQ_ACK 0x2004
+#define REG_IRQ_ACK_TYPE_MASK (15 << 16)
+#define REG_IRQ_ACK_TYPE_NONE (0 << 16)
+#define REG_IRQ_ACK_TYPE_IRQ (1 << 16)
+#define REG_IRQ_ACK_TYPE_IPI (4 << 16)
+#define REG_IRQ_ACK_IPI_OTHER 0x40001
+#define REG_IRQ_ACK_IPI_SELF 0x40002
+#define REG_IRQ_ACK_NUM_MASK (4095)
+#define REG_IPI_SET 0x2008
+#define REG_IPI_FLAG_SELF (1 << 31)
+#define REG_IPI_FLAG_OTHE

[RFC PATCH 0/7] Linux on Apple Silicon

[Mohamed Mediouni]

This patch series contains the changes for a minimal
Linux on Apple Silicon boot, including SMP.

(sorry for the resubmission, I didn't attach the drivers
to the ones beforehand, and didn't submit it properly)

The changes:

- Support for FIQ interrupts in-kernel

This is required for the timer and IPIs on Apple SoCs.

- WFI hook

Apple processors do not keep register state across WFI.
As such, put a mechanism in cpu_ops to put a custom
sleep function instead.

- use nGnRnE instead of nGnRE on Apple processors

Device-nGnRE writes go to nowhere on Apple processors, as
such use MAIR to change those to Device-nGnRE writes.

- Apple AIC driver

Driver for the Apple AIC interrupt controller.

- Apple CPU start driver

On Apple Macs, RVBAR is locked by the bootloader.
And the hardware doesn't have EL3 to provide PSCI
as an option either. This also implements the workaround
for WFI on the hardware.

What is not present:

- Device tree, will be present in a future version of this
patchset

- More devices.

Thank you,

Mohamed Mediouni (1):
  arm64: mm: use nGnRnE instead of nGnRE on Apple processors

Stan Skowronek (6):
  arm64: kernel: FIQ support
  arm64: kernel: Add a WFI hook.
  irqchip/apple-aic: Add support for Apple AIC
  arm64/Kconfig: Add Apple Silicon SoC platform
  arm64: kernel: Apple CPU start driver
  irqchip/apple-aic: add SMP support to the Apple AIC driver.

 .../devicetree/bindings/arm/cpus.yaml |   1 +
 .../interrupt-controller/apple,aic.yaml   |  49 +++
 MAINTAINERS   |   6 +
 arch/arm64/Kconfig.platforms  |   7 +
 arch/arm64/include/asm/arch_gicv3.h   |   2 +-
 arch/arm64/include/asm/assembler.h|   8 +-
 arch/arm64/include/asm/cpu_ops.h  |   2 +
 arch/arm64/include/asm/daifflags.h|   4 +-
 arch/arm64/include/asm/irq.h  |   4 +
 arch/arm64/include/asm/irqflags.h |   6 +-
 arch/arm64/kernel/Makefile|   1 +
 arch/arm64/kernel/apple_cpustart.c| 153 
 arch/arm64/kernel/cpu_ops.c   |   6 +
 arch/arm64/kernel/entry.S |  74 +++-
 arch/arm64/kernel/irq.c   |  14 +
 arch/arm64/kernel/process.c   |  13 +-
 arch/arm64/mm/proc.S  |  26 ++
 drivers/irqchip/Kconfig   |   6 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-apple-aic.c   | 364 ++
 20 files changed, 728 insertions(+), 19 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
 create mode 100644 arch/arm64/kernel/apple_cpustart.c
 create mode 100644 drivers/irqchip/irq-apple-aic.c

--
2.29.2

[RFC PATCH 1/7] arm64: kernel: FIQ support

[Mohamed Mediouni]

From: Stan Skowronek 

On Apple processors, the timer is wired through FIQ.
As such, add FIQ support to the kernel.

Signed-off-by: Stan Skowronek 
Signed-off-by: Mohamed Mediouni 
---
 arch/arm64/include/asm/arch_gicv3.h |  2 +-
 arch/arm64/include/asm/assembler.h  |  8 ++--
 arch/arm64/include/asm/daifflags.h  |  4 +-
 arch/arm64/include/asm/irq.h|  4 ++
 arch/arm64/include/asm/irqflags.h   |  6 +--
 arch/arm64/kernel/entry.S   | 74 ++---
 arch/arm64/kernel/irq.c | 14 ++
 arch/arm64/kernel/process.c |  2 +-
 8 files changed, 97 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h 
b/arch/arm64/include/asm/arch_gicv3.h
index 880b9054d75c..934b9be582d2 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -173,7 +173,7 @@ static inline void gic_pmr_mask_irqs(void)

 static inline void gic_arch_enable_irqs(void)
 {
-   asm volatile ("msr daifclr, #2" : : : "memory");
+   asm volatile ("msr daifclr, #3" : : : "memory");
 }

 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/assembler.h 
b/arch/arm64/include/asm/assembler.h
index bf125c591116..6fe55713dfe0 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -40,9 +40,9 @@
msr daif, \flags
.endm

-   /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
-   .macro enable_da_f
-   msr daifclr, #(8 | 4 | 1)
+   /* IRQ/FIQ is the lowest priority flag, unconditionally unmask the 
rest. */
+   .macro enable_da
+   msr daifclr, #(8 | 4)
.endm

 /*
@@ -50,7 +50,7 @@
  */
.macro  save_and_disable_irq, flags
mrs \flags, daif
-   msr daifset, #2
+   msr daifset, #3
.endm

.macro  restore_irq, flags
diff --git a/arch/arm64/include/asm/daifflags.h 
b/arch/arm64/include/asm/daifflags.h
index 1c26d7baa67f..44de96c7fb1a 100644
--- a/arch/arm64/include/asm/daifflags.h
+++ b/arch/arm64/include/asm/daifflags.h
@@ -13,8 +13,8 @@
 #include 

 #define DAIF_PROCCTX   0
-#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
-#define DAIF_ERRCTX(PSR_I_BIT | PSR_A_BIT)
+#define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
+#define DAIF_ERRCTX(PSR_I_BIT | PSR_F_BIT | PSR_A_BIT)
 #define DAIF_MASK  (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)


diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
index b2b0c6405eb0..2d1537d3a245 100644
--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
@@ -13,5 +13,9 @@ static inline int nr_legacy_irqs(void)
return 0;
 }

+int set_handle_fiq(void (*handle_fiq)(struct pt_regs *));
+
+extern void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init;
+
 #endif /* !__ASSEMBLER__ */
 #endif
diff --git a/arch/arm64/include/asm/irqflags.h 
b/arch/arm64/include/asm/irqflags.h
index ff328e5bbb75..26d7f378113e 100644
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -35,7 +35,7 @@ static inline void arch_local_irq_enable(void)
}

asm volatile(ALTERNATIVE(
-   "msrdaifclr, #2 // arch_local_irq_enable",
+   "msrdaifclr, #3 // arch_local_irq_enable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
ARM64_HAS_IRQ_PRIO_MASKING)
:
@@ -54,7 +54,7 @@ static inline void arch_local_irq_disable(void)
}

asm volatile(ALTERNATIVE(
-   "msrdaifset, #2 // arch_local_irq_disable",
+   "msrdaifset, #3 // arch_local_irq_disable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
ARM64_HAS_IRQ_PRIO_MASKING)
:
@@ -85,7 +85,7 @@ static inline int arch_irqs_disabled_flags(unsigned long 
flags)
int res;

asm volatile(ALTERNATIVE(
-   "and%w0, %w1, #" __stringify(PSR_I_BIT),
+   "and%w0, %w1, #" __stringify(PSR_I_BIT | PSR_F_BIT),
"eor%w0, %w1, #" __stringify(GIC_PRIO_IRQON),
ARM64_HAS_IRQ_PRIO_MASKING)
: "=&r" (res)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index c9bae73f2621..abcca0db0736 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -499,6 +499,14 @@ tsk.reqx28 // current thread_info
irq_stack_exit
.endm

+   .macro  fiq_handler
+   ldr_l   x1, handle_arch_fiq
+   mov x0, sp
+   irq_stack_entry
+   blr x1
+   irq_stack_exit
+   .endm
+
 #ifdef CONFIG_ARM64_PSEUDO_NMI
/*
 * Set res to 0 if irqs were unmasked in interrupted context.
@@ -547,1

[PATCH 1/3] arm64/kernel: FIQ support

[Mohamed Mediouni]

From: Stan Skowronek 

On Apple processors, the timer is wired through FIQ.
As such, add FIQ support to the kernel.

Signed-off-by: Stan Skowronek 
---
 arch/arm64/include/asm/arch_gicv3.h |  2 +-
 arch/arm64/include/asm/assembler.h  |  8 ++--
 arch/arm64/include/asm/daifflags.h  |  4 +-
 arch/arm64/include/asm/irq.h|  4 ++
 arch/arm64/include/asm/irqflags.h   |  6 +--
 arch/arm64/kernel/entry.S   | 74 ++---
 arch/arm64/kernel/irq.c | 14 ++
 arch/arm64/kernel/process.c |  2 +-
 8 files changed, 97 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h 
b/arch/arm64/include/asm/arch_gicv3.h
index 880b9054d75c..934b9be582d2 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -173,7 +173,7 @@ static inline void gic_pmr_mask_irqs(void)
 
 static inline void gic_arch_enable_irqs(void)
 {
-   asm volatile ("msr daifclr, #2" : : : "memory");
+   asm volatile ("msr daifclr, #3" : : : "memory");
 }
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/assembler.h 
b/arch/arm64/include/asm/assembler.h
index bf125c591116..6fe55713dfe0 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -40,9 +40,9 @@
msr daif, \flags
.endm
 
-   /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
-   .macro enable_da_f
-   msr daifclr, #(8 | 4 | 1)
+   /* IRQ/FIQ is the lowest priority flag, unconditionally unmask the 
rest. */
+   .macro enable_da
+   msr daifclr, #(8 | 4)
.endm
 
 /*
@@ -50,7 +50,7 @@
  */
.macro  save_and_disable_irq, flags
mrs \flags, daif
-   msr daifset, #2
+   msr daifset, #3
.endm
 
.macro  restore_irq, flags
diff --git a/arch/arm64/include/asm/daifflags.h 
b/arch/arm64/include/asm/daifflags.h
index 1c26d7baa67f..44de96c7fb1a 100644
--- a/arch/arm64/include/asm/daifflags.h
+++ b/arch/arm64/include/asm/daifflags.h
@@ -13,8 +13,8 @@
 #include 
 
 #define DAIF_PROCCTX   0
-#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
-#define DAIF_ERRCTX(PSR_I_BIT | PSR_A_BIT)
+#define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
+#define DAIF_ERRCTX(PSR_I_BIT | PSR_F_BIT | PSR_A_BIT)
 #define DAIF_MASK  (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
 
 
diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
index b2b0c6405eb0..2d1537d3a245 100644
--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
@@ -13,5 +13,9 @@ static inline int nr_legacy_irqs(void)
return 0;
 }
 
+int set_handle_fiq(void (*handle_fiq)(struct pt_regs *));
+
+extern void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init;
+
 #endif /* !__ASSEMBLER__ */
 #endif
diff --git a/arch/arm64/include/asm/irqflags.h 
b/arch/arm64/include/asm/irqflags.h
index ff328e5bbb75..26d7f378113e 100644
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -35,7 +35,7 @@ static inline void arch_local_irq_enable(void)
}
 
asm volatile(ALTERNATIVE(
-   "msrdaifclr, #2 // arch_local_irq_enable",
+   "msrdaifclr, #3 // arch_local_irq_enable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
ARM64_HAS_IRQ_PRIO_MASKING)
:
@@ -54,7 +54,7 @@ static inline void arch_local_irq_disable(void)
}
 
asm volatile(ALTERNATIVE(
-   "msrdaifset, #2 // arch_local_irq_disable",
+   "msrdaifset, #3 // arch_local_irq_disable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
ARM64_HAS_IRQ_PRIO_MASKING)
:
@@ -85,7 +85,7 @@ static inline int arch_irqs_disabled_flags(unsigned long 
flags)
int res;
 
asm volatile(ALTERNATIVE(
-   "and%w0, %w1, #" __stringify(PSR_I_BIT),
+   "and%w0, %w1, #" __stringify(PSR_I_BIT | PSR_F_BIT),
"eor%w0, %w1, #" __stringify(GIC_PRIO_IRQON),
ARM64_HAS_IRQ_PRIO_MASKING)
: "=&r" (res)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index c9bae73f2621..abcca0db0736 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -499,6 +499,14 @@ tsk.reqx28 // current thread_info
irq_stack_exit
.endm
 
+   .macro  fiq_handler
+   ldr_l   x1, handle_arch_fiq
+   mov x0, sp
+   irq_stack_entry
+   blr x1
+   irq_stack_exit
+   .endm
+
 #ifdef CONFIG_ARM64_PSEUDO_NMI
/*
 * Set res to 0 if irqs were unmasked in interrupted context.
@@ -547,18 +555,18 @@ SYM_CODE_START(vectors)
 
kernel_ventry   1, sync // Synchronous EL1h
kernel_ventry   1, irq  // IRQ EL1h
-   kerne

[PATCH 2/3] arm64: kernel: Add a WFI hook.

[Mohamed Mediouni]

From: Stan Skowronek 

WFI drops register state on Apple Silicon for SMP systems.

This hook will be used for a hardware workaround in the
Apple CPU start driver.

Signed-off-by: Stan Skowronek 
---
 arch/arm64/include/asm/cpu_ops.h |  2 ++
 arch/arm64/kernel/cpu_ops.c  |  6 ++
 arch/arm64/kernel/process.c  | 11 +--
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index e95c4df83911..4be0fc5bcaf9 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -23,6 +23,7 @@
  * @cpu_boot:  Boots a cpu into the kernel.
  * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary
  * synchronisation. Called from the cpu being booted.
+ * @cpu_wfi:Optionally, replace calls to WFI in default idle with this.
  * @cpu_can_disable: Determines whether a CPU can be disabled based on
  * mechanism-specific information.
  * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific
@@ -43,6 +44,7 @@ struct cpu_operations {
int (*cpu_prepare)(unsigned int);
int (*cpu_boot)(unsigned int);
void(*cpu_postboot)(void);
+   void(*cpu_wfi)(void);
 #ifdef CONFIG_HOTPLUG_CPU
bool(*cpu_can_disable)(unsigned int cpu);
int (*cpu_disable)(unsigned int cpu);
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index e133011f64b5..6979fc4490b2 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -19,12 +19,18 @@ extern const struct cpu_operations smp_spin_table_ops;
 extern const struct cpu_operations acpi_parking_protocol_ops;
 #endif
 extern const struct cpu_operations cpu_psci_ops;
+#ifdef CONFIG_ARCH_APPLE
+extern const struct cpu_operations cpu_apple_start_ops;
+#endif
 
 static const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
 
 static const struct cpu_operations *const dt_supported_cpu_ops[] __initconst = 
{
&smp_spin_table_ops,
&cpu_psci_ops,
+#ifdef CONFIG_ARCH_APPLE
+   &cpu_apple_start_ops,
+#endif
NULL,
 };
 
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 34ec400288d0..611c639e20be 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -57,6 +57,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
 #include 
@@ -74,8 +75,14 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const 
char *cmd);
 
 static void noinstr __cpu_do_idle(void)
 {
-   dsb(sy);
-   wfi();
+   const struct cpu_operations *ops = get_cpu_ops(task_cpu(current));
+
+   if (ops->cpu_wfi) {
+   ops->cpu_wfi();
+   } else {
+   dsb(sy);
+   wfi();
+   }
 }
 
 static void noinstr __cpu_do_idle_irqprio(void)
-- 
2.29.2

[PATCH 0/3] Preparations for Linux on Apple Silicon

[Mohamed Mediouni]

This patch series contains the changes to common Linux
kernel code that are required to boot Linux on Apple Silicon
Mac computers.

The changes:

- Support for FIQ interrupts in-kernel

This is required for the timer and IPIs on Apple SoCs.

- WFI hook

Apple processors do not keep register state across WFI.
As such, put a mechanism in cpu_ops to put a custom
sleep function instead.

- use nGnRnE instead of nGnRE on Apple processors

Device-nGnRE writes go to nowhere on Apple processors, as
such use MAIR to change those to Device-nGnRE writes.

Mohamed Mediouni (1):
  arm64: mm: use nGnRnE instead of nGnRE on Apple processors

Stan Skowronek (2):
  arm64/kernel: FIQ support
  arm64: kernel: Add a WFI hook.

 arch/arm64/include/asm/arch_gicv3.h |  2 +-
 arch/arm64/include/asm/assembler.h  |  8 ++--
 arch/arm64/include/asm/cpu_ops.h|  2 +
 arch/arm64/include/asm/daifflags.h  |  4 +-
 arch/arm64/include/asm/irq.h|  4 ++
 arch/arm64/include/asm/irqflags.h   |  6 +--
 arch/arm64/kernel/cpu_ops.c |  6 +++
 arch/arm64/kernel/entry.S   | 74 ++---
 arch/arm64/kernel/irq.c | 14 ++
 arch/arm64/kernel/process.c | 13 +++--
 arch/arm64/mm/proc.S| 26 ++
 11 files changed, 140 insertions(+), 19 deletions(-)

--
2.29.2

[PATCH 3/3] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Mohamed Mediouni]

From: Mohamed Mediouni 

Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware 
quirk.

On Apple processors, writes using the nGnRE device memory type get dropped in 
flight,
getting to nowhere.

Signed-off-by: Mohamed Mediouni 
Signed-off-by: Stan Skowronek 
---
 arch/arm64/mm/proc.S | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 1f7ee8c8b7b8..06436916f137 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -51,6 +51,25 @@
 #define TCR_KASAN_HW_FLAGS 0
 #endif
 
+#ifdef CONFIG_ARCH_APPLE
+
+/*
+ * Apple cores appear to black-hole writes done with nGnRE.
+ * We settled on a work-around that uses MAIR vs changing every single user of
+ * nGnRE across the arm64 code.
+ */
+
+#define MAIR_EL1_SET_APPLE \
+   (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |  \
+MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) |   \
+MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |\
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |  \
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |\
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |  \
+MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
+
+#endif
+
 /*
  * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
  * changed during __cpu_setup to Normal Tagged if the system supports MTE.
@@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup)
 * Memory region attributes
 */
mov_q   x5, MAIR_EL1_SET
+#ifdef CONFIG_ARCH_APPLE
+   mrs x0, MIDR_EL1
+   lsr w0, w0, #24
+   mov_q   x1, MAIR_EL1_SET_APPLE
+   cmp x0, #0x61   // 0x61 = Implementer: Apple
+   cselx5, x1, x5, eq
+#endif
 #ifdef CONFIG_ARM64_MTE
mte_tcr .reqx20
 
-- 
2.29.2