[PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible

[Mylène Josserand]

Add the possible compatible "rockchip,rk3288w-cru" that handles
the difference between the rk3288 and the new revision rk3288w.

This compatible will be added by bootloaders.

Signed-off-by: Mylène Josserand 
---
 .../devicetree/bindings/clock/rockchip,rk3288-cru.txt | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
index 8cb47c39ba53..bf3a9ec19241 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to 
various
 controllers within the SoC and also implements a reset controller for SoC
 peripherals.
 
+A revision of this SoC is available: rk3288w. The clock tree is a bit
+different so another dt-compatible is available. Noticed that it is only
+setting the difference but there is no automatic revision detection. This
+should be performed by bootloaders.
+
 Required Properties:
 
-- compatible: should be "rockchip,rk3288-cru"
+- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
+  case of this revision of Rockchip rk3288.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - #clock-cells: should be 1.
-- 
2.26.2

[PATCH v4 0/2] ARM: Add Rockchip rk3288w support

[Mylène Josserand]

Hello everyone,

Context
---

Here is my V4 of my patches that add the support for the Rockchip
RK3288w which is a revision of the RK3288. It is mostly the same SOC
except for, at least, one clock tree which is different.
This difference is only known by looking at the BSP kernel [1].

Currently, the mainline kernel will not hang on rk3288w but it is
probably by "chance" because we got an issue on a lower kernel version.

According to Rockchip's U-Boot [2], the rk3288w can be detected using
the HDMI revision number (= 0x1A) in this version of the SOC.

Changelog
-

This V4 is pretty much the same than the V3. Added the dt-bindings
documentation in clock-controller dt-bindings and fixed some typos
according to Heiko's reviews.

Changes since v3:
   - Updated clock-controller's dt-bindings
   - Fixed indentation

Best regards,
Mylène Josserand

[1] 
https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/clk/rockchip/clk-rk3288.c#L960..L964
[2] 
https://github.com/rockchip-linux/u-boot/blob/next-dev/arch/arm/mach-rockchip/rk3288/rk3288.c#L378..L388

Mylène Josserand (2):
  clk: rockchip: rk3288: Handle clock tree for rk3288w
  dt-bindings: clocks: rk3288: add possible rk3288w

 .../bindings/clock/rockchip,rk3288-cru.txt|  8 +++-
 drivers/clk/rockchip/clk-rk3288.c | 20 +--
 2 files changed, 25 insertions(+), 3 deletions(-)

-- 
2.26.2

[PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w

[Mylène Josserand]

The revision rk3288w has a different clock tree about "hclk_vio"
clock, according to the BSP kernel code.

This patch handles this difference by detecting which device-tree
we are using. If it is a "rockchip,rk3288-cru", let's register
the clock tree as it was before. If the device-tree node is
"rockchip,rk3288w-cru", we will apply the difference with this
version of this SoC.

Noticed that this new device-tree compatible must be handled in
bootloader such as u-boot.

Signed-off-by: Mylène Josserand 
---
 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index cc2a177bbdbf..204976e2d0cb 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 
CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 0, GFLAGS),
-   DIV(0, "hclk_vio", "aclk_vio0", 0,
-   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 
CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 2, GFLAGS),
@@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, 
IFLAGS),
 };
 
+static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
+   DIV(0, "hclk_vio", "aclk_vio1", 0,
+   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
+static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
+   DIV(0, "hclk_vio", "aclk_vio0", 0,
+   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
 static const char *const rk3288_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
@@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
   RK3288_GRF_SOC_STATUS1);
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
  ARRAY_SIZE(rk3288_clk_branches));
+
+   if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
+   rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
+  
ARRAY_SIZE(rk3288w_hclkvio_branch));
+   else
+   rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
+  
ARRAY_SIZE(rk3288_hclkvio_branch));
+
rockchip_clk_protect_critical(rk3288_critical_clocks,
  ARRAY_SIZE(rk3288_critical_clocks));
 
-- 
2.26.2

[PATCH v3 1/1] clk: rockchip: rk3288: Handle clock tree for rk3288w

[Mylène Josserand]

The revision rk3288w has a different clock tree about "hclk_vio"
clock, according to the BSP kernel code.

This patch handles this difference by detecting which device-tree
we are using. If it is a "rockchip,rk3288-cru", let's register
the clock tree as it was before. If the compatible is
"rockchip,rk3288w-cru", we will apply the difference according to this
version of this SoC.

Noticed that this new device-tree compatible must be handled by
bootloader.

Signed-off-by: Mylène Josserand 
---
 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index cc2a177bbdbf..5018d2f1e54c 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 
CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 0, GFLAGS),
-   DIV(0, "hclk_vio", "aclk_vio0", 0,
-   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 
CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 2, GFLAGS),
@@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, 
IFLAGS),
 };
 
+static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
+   DIV(0, "hclk_vio", "aclk_vio1", 0,
+   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
+static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
+   DIV(0, "hclk_vio", "aclk_vio0", 0,
+   RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
 static const char *const rk3288_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
@@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
   RK3288_GRF_SOC_STATUS1);
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
  ARRAY_SIZE(rk3288_clk_branches));
+
+   if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
+   rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
+  
ARRAY_SIZE(rk3288w_hclkvio_branch));
+   else
+   rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
+  
ARRAY_SIZE(rk3288_hclkvio_branch));
+
rockchip_clk_protect_critical(rk3288_critical_clocks,
  ARRAY_SIZE(rk3288_critical_clocks));
 
-- 
2.26.2

[PATCH v3 0/1] ARM: Add Rockchip rk3288w support

[Mylène Josserand]

Hello everyone,

Context
---

Here is my V3 of my patches that add the support for the Rockchip
RK3288w which is a revision of the RK3288. It is mostly the same SOC
except for, at least, one clock tree which is different.
This difference is only known by looking at the BSP kernel [1].

Currently, the mainline kernel will not hang on rk3288w but it is
probably by "chance" because we got an issue on a lower kernel version.

According to Rockchip's U-Boot [2], the rk3288w can be detected using
the HDMI revision number (= 0x1A) in this version of the SOC.

Changelog
-

In this V3, the revision's detection is not done in the kernel anymore.
This patch will handle the rk3288w clock tree according to a new
compatible "rockchip,rk3288w-cru" that must be provided by bootloaders.

Changes since v2:
   - Remove all codes about revision detection, let's handle that by
   Bootloaders

Best regards,
Mylène Josserand

[1] 
https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/clk/rockchip/clk-rk3288.c#L960..L964
[2] 
https://github.com/rockchip-linux/u-boot/blob/next-dev/arch/arm/mach-rockchip/rk3288/rk3288.c#L378..L388

Mylène Josserand (1):
  clk: rockchip: rk3288: Handle clock tree for rk3288w

 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

-- 
2.26.2

[PATCH v1] tty: serial: max310x: Add optional reset gpio

[Mylène Josserand]

Add the possibility to use a gpio as reset.

Signed-off-by: Mylène Josserand 
---
 Documentation/devicetree/bindings/serial/maxim,max310x.txt | 1 +
 drivers/tty/serial/max310x.c   | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/maxim,max310x.txt 
b/Documentation/devicetree/bindings/serial/maxim,max310x.txt
index 79e10a05a96a..1d7d8a0b4260 100644
--- a/Documentation/devicetree/bindings/serial/maxim,max310x.txt
+++ b/Documentation/devicetree/bindings/serial/maxim,max310x.txt
@@ -15,6 +15,7 @@ Required properties:
   "osc" if an external clock source is used.
 
 Optional properties:
+- reset-gpios: Gpio to use for reset.
 - gpio-controller: Marks the device node as a GPIO controller.
 - #gpio-cells: Should be two. The first cell is the GPIO number and
   the second cell is used to specify the GPIO polarity:
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
index e5aebbf5f302..d056fa2eed1b 100644
--- a/drivers/tty/serial/max310x.c
+++ b/drivers/tty/serial/max310x.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1413,12 +1414,18 @@ static int max310x_spi_probe(struct spi_device *spi)
return ret;
 
if (spi->dev.of_node) {
+   struct gpio_desc *reset_gpio;
const struct of_device_id *of_id =
of_match_device(max310x_dt_ids, >dev);
if (!of_id)
return -ENODEV;
 
devtype = (struct max310x_devtype *)of_id->data;
+   reset_gpio = devm_gpiod_get_optional(>dev, "reset",
+GPIOD_OUT_HIGH);
+   if (IS_ERR(reset_gpio))
+   return PTR_ERR(reset_gpio);
+   gpiod_set_value_cansleep(reset_gpio, 0);
} else {
const struct spi_device_id *id_entry = spi_get_device_id(spi);
 
-- 
2.11.0

[PATCH v1] Input: rotary-encoder - Add gpio as push button

[Mylène Josserand]

Add the support of a gpio that can be defined as a push button.
Thanks to that, it is possible to emit a keycode in case of a
"push" event, if the rotary supports that.

The keycode to emit is defined using "linux,code" property
(such as in gpio-keys).

Signed-off-by: Mylène Josserand 
---
 .../devicetree/bindings/input/rotary-encoder.txt   |  5 +++
 drivers/input/misc/rotary_encoder.c| 50 ++
 2 files changed, 55 insertions(+)

diff --git a/Documentation/devicetree/bindings/input/rotary-encoder.txt 
b/Documentation/devicetree/bindings/input/rotary-encoder.txt
index a644408b33b8..1cfce5d0b5c4 100644
--- a/Documentation/devicetree/bindings/input/rotary-encoder.txt
+++ b/Documentation/devicetree/bindings/input/rotary-encoder.txt
@@ -22,6 +22,9 @@ Optional properties:
 - wakeup-source: Boolean, rotary encoder can wake up the system.
 - rotary-encoder,encoding: String, the method used to encode steps.
   Supported are "gray" (the default and more common) and "binary".
+- push-gpio: a gpio to be used as a detection of a push from the rotary.
+- linux,code: keycode to emit with the push-gpio of this rotary encoder.
+  Required property in case "push-gpio"'s one is used.
 
 Deprecated properties:
 - rotary-encoder,half-period: Makes the driver work on half-period mode.
@@ -47,4 +50,6 @@ Example:
rotary-encoder,steps = <24>;
rotary-encoder,encoding = "binary";
rotary-encoder,rollover;
+   push-gpio = < 20 0>;
+   linux-code = <28> /* KEY_ENTER */
};
diff --git a/drivers/input/misc/rotary_encoder.c 
b/drivers/input/misc/rotary_encoder.c
index d748897bf5e9..556995fb7dde 100644
--- a/drivers/input/misc/rotary_encoder.c
+++ b/drivers/input/misc/rotary_encoder.c
@@ -47,8 +47,10 @@ struct rotary_encoder {
unsigned int pos;
 
struct gpio_descs *gpios;
+   struct gpio_desc *gpio_push;
 
unsigned int *irq;
+   unsigned int code;
 
bool armed;
signed char dir;/* 1 - clockwise, -1 - CCW */
@@ -56,6 +58,23 @@ struct rotary_encoder {
unsigned int last_stable;
 };
 
+static irqreturn_t rotary_push_irq(int irq, void *dev_id)
+{
+   struct rotary_encoder *encoder = dev_id;
+   int val;
+
+   mutex_lock(>access_mutex);
+
+   val = gpiod_get_value_cansleep(encoder->gpio_push);
+
+   input_report_key(encoder->input, encoder->code, val);
+   input_sync(encoder->input);
+
+   mutex_unlock(>access_mutex);
+
+   return IRQ_HANDLED;
+}
+
 static unsigned int rotary_encoder_get_state(struct rotary_encoder *encoder)
 {
int i;
@@ -190,6 +209,7 @@ static int rotary_encoder_probe(struct platform_device 
*pdev)
struct device *dev = >dev;
struct rotary_encoder *encoder;
struct input_dev *input;
+   unsigned int irq_push;
irq_handler_t handler;
u32 steps_per_period;
unsigned int i;
@@ -250,6 +270,20 @@ static int rotary_encoder_probe(struct platform_device 
*pdev)
return -EINVAL;
}
 
+   encoder->gpio_push = devm_gpiod_get_optional(dev, "push", GPIOD_IN);
+   if (IS_ERR(encoder->gpio_push)) {
+   dev_err(dev, "unable to get gpio-push\n");
+   return PTR_ERR(encoder->gpio_push);
+   }
+
+   if (encoder->gpio_push) {
+   if (device_property_read_u32(dev, "linux,code",
+>code)) {
+   dev_err(dev, "gpio-push without keycode\n");
+   return -EINVAL;
+   }
+   }
+
input = devm_input_allocate_device(dev);
if (!input)
return -ENOMEM;
@@ -306,6 +340,22 @@ static int rotary_encoder_probe(struct platform_device 
*pdev)
}
}
 
+   if (encoder->gpio_push) {
+   input_set_capability(encoder->input, EV_KEY, encoder->code);
+
+   irq_push = gpiod_to_irq(encoder->gpio_push);
+   err = devm_request_threaded_irq(dev, irq_push,
+   NULL, rotary_push_irq,
+   IRQF_TRIGGER_RISING |
+   IRQF_TRIGGER_FALLING |
+   IRQF_ONESHOT,
+   DRV_NAME, encoder);
+   if (err) {
+   dev_err(dev, "unable to request IRQ %d\n", irq_push);
+   return err;
+   }
+   }
+
err = input_register_device(input);
if (err) {
dev_err(dev, "failed to register input device\n");
-- 
2.11.0

[PATCH v1 3/3] dt-bindings: iio: afe: Add hwmon example

[Mylène Josserand]

With the support of CHAN_INFO_PROCESSED in voltage-divider,
it is possible to read the processed values directly from iio's
sysfs entries or by using iio-hwmon. Add an example for this last
use case.

Signed-off-by: Mylène Josserand 
---
 .../bindings/iio/afe/voltage-divider.txt   | 24 ++
 1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt 
b/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt
index b452a8406107..f7e1c7cb2744 100644
--- a/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt
+++ b/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt
@@ -51,3 +51,27 @@ sysv {
spi-max-frequency = <100>;
};
 };
+
+It is also possible to retrieve the processed values using hwmon node:
+
+div0: div0 {
+   compatible = "voltage-divider";
+   io-channels = < 0>; /* Channel 0 of the ADC */
+   output-ohms = <47>; /* R2 */
+   full-ohms = <73>; /* R1 (26) + R2 (47) */
+   #io-channel-cells = <1>;
+};
+
+div1: div1 {
+   compatible = "voltage-divider";
+   io-channels = < 1>; /* Channel 1 of the ADC */
+   output-ohms = <47>; /* R2 */
+   full-ohms = <115>; /* R1 (68) + R2 (47) */
+   #io-channel-cells = <1>;
+};
+
+iio-hwmon {
+   compatible = "iio-hwmon";
+   io-channels = < 0>, < 0>;
+   io-channel-names = "3v3", "usb";
+};
-- 
2.11.0

[PATCH v1 1/3] iio: afe: rescale: Move scale conversion to new function

[Mylène Josserand]

To prepare the support of processed value, create a function
to convert the scale according to the voltage-divider node
used in the device-tree.

Signed-off-by: Mylène Josserand 
---
 drivers/iio/afe/iio-rescale.c | 54 +--
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/drivers/iio/afe/iio-rescale.c b/drivers/iio/afe/iio-rescale.c
index e9ceee66d1e7..3e689d6eb501 100644
--- a/drivers/iio/afe/iio-rescale.c
+++ b/drivers/iio/afe/iio-rescale.c
@@ -33,12 +33,41 @@ struct rescale {
s32 denominator;
 };
 
+static int rescale_convert_scale(struct rescale *rescale, int *val, int *val2)
+{
+   unsigned long long tmp;
+   int ret;
+
+   ret = iio_read_channel_scale(rescale->source, val, val2);
+   switch (ret) {
+   case IIO_VAL_FRACTIONAL:
+   *val *= rescale->numerator;
+   *val2 *= rescale->denominator;
+   return ret;
+   case IIO_VAL_INT:
+   *val *= rescale->numerator;
+   if (rescale->denominator == 1)
+   return ret;
+   *val2 = rescale->denominator;
+   return IIO_VAL_FRACTIONAL;
+   case IIO_VAL_FRACTIONAL_LOG2:
+   tmp = *val * 10LL;
+   do_div(tmp, rescale->denominator);
+   tmp *= rescale->numerator;
+   do_div(tmp, 10LL);
+   *val = tmp;
+
+   return ret;
+   default:
+   return -EOPNOTSUPP;
+   }
+}
+
 static int rescale_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
 {
struct rescale *rescale = iio_priv(indio_dev);
-   unsigned long long tmp;
int ret;
 
switch (mask) {
@@ -46,28 +75,7 @@ static int rescale_read_raw(struct iio_dev *indio_dev,
return iio_read_channel_raw(rescale->source, val);
 
case IIO_CHAN_INFO_SCALE:
-   ret = iio_read_channel_scale(rescale->source, val, val2);
-   switch (ret) {
-   case IIO_VAL_FRACTIONAL:
-   *val *= rescale->numerator;
-   *val2 *= rescale->denominator;
-   return ret;
-   case IIO_VAL_INT:
-   *val *= rescale->numerator;
-   if (rescale->denominator == 1)
-   return ret;
-   *val2 = rescale->denominator;
-   return IIO_VAL_FRACTIONAL;
-   case IIO_VAL_FRACTIONAL_LOG2:
-   tmp = *val * 10LL;
-   do_div(tmp, rescale->denominator);
-   tmp *= rescale->numerator;
-   do_div(tmp, 10LL);
-   *val = tmp;
-   return ret;
-   default:
-   return -EOPNOTSUPP;
-   }
+   return rescale_convert_scale(rescale, val, val2);
default:
return -EINVAL;
}
-- 
2.11.0

[PATCH v1 2/3] iio: afe: rescale: Add support of CHAN_INFO_PROCESSED

[Mylène Josserand]

Add the support of the CHAN_INFO_PROCESSED to have directly
the processed value (raw * scale). It will be exported as
in_voltage0_input in sysfs.

Signed-off-by: Mylène Josserand 
---
 drivers/iio/afe/iio-rescale.c | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/afe/iio-rescale.c b/drivers/iio/afe/iio-rescale.c
index 3e689d6eb501..2275571fff64 100644
--- a/drivers/iio/afe/iio-rescale.c
+++ b/drivers/iio/afe/iio-rescale.c
@@ -63,14 +63,54 @@ static int rescale_convert_scale(struct rescale *rescale, 
int *val, int *val2)
}
 }
 
+static int rescale_convert_processed(struct rescale *rescale, int raw,
+int *val, int *val2)
+{
+   unsigned long long tmp, scaled;
+   int ret;
+
+   ret = rescale_convert_scale(rescale, val, val2);
+   switch (ret) {
+   case IIO_VAL_FRACTIONAL:
+   tmp = div_s64((s64)*val * 10LL, *val2);
+   scaled = tmp * raw;
+   *val = (int)div_s64_rem(scaled, 10, val2);
+   return ret;
+   case IIO_VAL_INT:
+   return IIO_VAL_FRACTIONAL;
+   case IIO_VAL_FRACTIONAL_LOG2:
+   tmp = shift_right((s64)*val * 10LL, *val2);
+   scaled = tmp * raw;
+   *val = (int)div_s64_rem(scaled, 10LL, val2);
+   return ret;
+   default:
+   return -EOPNOTSUPP;
+   }
+}
+
 static int rescale_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
 {
struct rescale *rescale = iio_priv(indio_dev);
+   unsigned int raw;
int ret;
 
switch (mask) {
+   case IIO_CHAN_INFO_PROCESSED:
+   /* Read the raw value and the scale */
+   ret = iio_read_channel_raw(rescale->source, );
+   if (!ret)
+   return ret;
+   ret = iio_read_channel_scale(rescale->source, val, val2);
+   if (!ret)
+   return ret;
+   /* Process the correct value with raw * scale */
+   ret = rescale_convert_processed(rescale, raw, val, val2);
+   if (!ret)
+   return ret;
+   return IIO_VAL_INT;
+
case IIO_CHAN_INFO_RAW:
return iio_read_channel_raw(rescale->source, val);
 
@@ -145,7 +185,7 @@ static int rescale_configure_channel(struct device *dev,
}
 
chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-   BIT(IIO_CHAN_INFO_SCALE);
+   BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_PROCESSED);
 
if (iio_channel_has_available(schan, IIO_CHAN_INFO_RAW))
chan->info_mask_separate_available |= BIT(IIO_CHAN_INFO_RAW);
-- 
2.11.0

[PATCH v1 0/3] iio: afe: rescale: Add INFO_PROCESSED support

[Mylène Josserand]

Hello everyone,

You will find a small series that add the support of processed values
for iio-rescale driver.
Thanks to that, it is possible to read processed values in sysfs instead
of getting only raw and scale values.

Here is an example for a 3v3 voltage reading:
# cat /sys/bus/iio/devices/iio\:device1/in_voltage0_scale
3.791015625
# cat /sys/bus/iio/devices/iio\:device1/in_voltage0_raw
879
# cat /sys/bus/iio/devices/iio\:device1/in_voltage0_input
3332

It is also possible to read directly the processed values using iio-hwmon
driver (see example in patch03):

# cat /sys/class/hwmon/hwmon0/in1_input
3328

I seperated my series in 3 patches:
   - Patch01: Move the scale conversion into a function to prepare the
   support of IIO_CHAN_INFO_PROCESSED.
   - Patch02: Add the support of IIO_CHAN_INFO_PROCESSED.
   - Patch03: Add an example of the use of hwmon and voltage-divider nodes
   in device-tree.

If you have any feedbacks on it, I will be pleased to read them!

Best regards,
Mylène

Mylène Josserand (3):
  iio: afe: rescale: Move scale conversion to new function
  iio: afe: rescale: Add support of CHAN_INFO_PROCESSED
  dt-bindings: iio: afe: Add hwmon example

 .../bindings/iio/afe/voltage-divider.txt   | 24 ++
 drivers/iio/afe/iio-rescale.c  | 96 --
 2 files changed, 96 insertions(+), 24 deletions(-)

-- 
2.11.0

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Mon, 13 Aug 2018 08:36:32 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Mon, Aug 13, 2018 at 8:24 AM Mylène Josserand
>  wrote:
> >
> > Hi Dmitry,
> >
> > On Tue, 24 Jul 2018 10:40:53 -0700
> > Dmitry Torokhov  wrote:
> >  
> > > Hi Mylène,
> > >
> > > On Tue, Jul 24, 2018 at 03:00:46PM +0200, Mylène Josserand wrote:  
> > > > Hello Dmitry,
> > > >
> > > > On Wed, 4 Jul 2018 16:21:58 +
> > > > Dmitry Torokhov  wrote:
> > > >  
> > > > > Hi Mylène,
> > > > >
> > > > > On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:  
> > > > > > Hello,
> > > > > >
> > > > > > Here is a V6 series to add the driver of the touchscreen Cypress,
> > > > > > TrueTouch Generation 5.
> > > > > > Based on v4.18-rc3.
> > > > > >
> > > > > > This patch series has already been posted in several iterations:
> > > > > > - v1: Sent on 2017/05/29
> > > > > > - v2: Sent on 2017/08/18
> > > > > > - v3: Sent on 2017/09/27
> > > > > > - v4: Sent on 2017/12/01
> > > > > > - v5: Sent on 2017/12/20
> > > > > >
> > > > > > I did not have any comments the last 4 versions.
> > > > > > And no reviews on my v5 during 6 months. Could I have any updates
> > > > > > or feedback on my series to know why it is not merged (to be able to
> > > > > > correct what is wrong)?  
> > > > >
> > > > > Sorry, I must have missed the v5, sorry about that.
> > > > >
> > > > > I probably asked this question before, but just to make sure - I see
> > > > > references to HID in the patch - the device is really not HID
> > > > > compatible? Is there any hope it could be made work with i2c-hid +
> > > > > hid-multitouch?
> > > > >
> > > > > Thanks.
> > > > >  
> > > >
> > > > I have checked and, for what I have seen, all the HID descriptor stuff
> > > > is HID compliant. We could definitely use i2c-hid and hid-multitouch
> > > > (there is the "hid-cypress" driver that exists also).
> > > >
> > > > The only problem is that this touchscreen has two modes: a bootloader
> > > > mode and an application mode (which is the one where we can send
> > > > HID commands). After a power-on-reset, it is always in "bootloader"
> > > > mode so we need to send some commands (called "bootloader commands") to
> > > > switch to application mode.  
> > >
> > > Is this a documented or observed behavior? In my practice devices (I am
> > > talking in general, not about Cypress) that have proper configuration
> > > loaded and that were brought up with appropriate power up sequence and
> > > timings automatically switch to application mode. They only end up in
> > > bootloader mode when proper power up sequence is not respected and they
> > > are unhappy.  
> >
> > I have checked and indeed, if everything is correctly performed, the
> > bootloader has a timeout to switch to application mode.
> > The datasheet says that this timeout can be configured and the "0" value
> > means that the bootloader will never automatically switch to application
> > unless a bootloader command is sent.
> >
> > In our case, you were right, after a timeout, the touchscreen is
> > correctly switching to Application mode. Great news!
> >  
> > >  
> > > > These commands are not HID-compliant as the
> > > > datasheet indicates:
> > > >
> > > > "Bootloader commands are not HID-over-I2C compliant."  
> > >
> > > Any chance you could share the datasheet?  
> >
> > Sorry, it is not possible, the datasheet is under NDA :(
> >  
> > >  
> > > >
> > > > I think that if the touchscreen would start directly in "application"
> > > > mode, we could directly use i2c-hid and hid-cypress drivers.
> > > > Unfortunately, this is not the case.
> > > >
> > > > In bootloader mode, the ProductID is 0xc101 and in application mode, it
> > > > is 0xc001 (already available in hid-ids.h:
> > > > USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)
> > > >
> 

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Mon, 13 Aug 2018 08:36:32 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Mon, Aug 13, 2018 at 8:24 AM Mylène Josserand
>  wrote:
> >
> > Hi Dmitry,
> >
> > On Tue, 24 Jul 2018 10:40:53 -0700
> > Dmitry Torokhov  wrote:
> >  
> > > Hi Mylène,
> > >
> > > On Tue, Jul 24, 2018 at 03:00:46PM +0200, Mylène Josserand wrote:  
> > > > Hello Dmitry,
> > > >
> > > > On Wed, 4 Jul 2018 16:21:58 +
> > > > Dmitry Torokhov  wrote:
> > > >  
> > > > > Hi Mylène,
> > > > >
> > > > > On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:  
> > > > > > Hello,
> > > > > >
> > > > > > Here is a V6 series to add the driver of the touchscreen Cypress,
> > > > > > TrueTouch Generation 5.
> > > > > > Based on v4.18-rc3.
> > > > > >
> > > > > > This patch series has already been posted in several iterations:
> > > > > > - v1: Sent on 2017/05/29
> > > > > > - v2: Sent on 2017/08/18
> > > > > > - v3: Sent on 2017/09/27
> > > > > > - v4: Sent on 2017/12/01
> > > > > > - v5: Sent on 2017/12/20
> > > > > >
> > > > > > I did not have any comments the last 4 versions.
> > > > > > And no reviews on my v5 during 6 months. Could I have any updates
> > > > > > or feedback on my series to know why it is not merged (to be able to
> > > > > > correct what is wrong)?  
> > > > >
> > > > > Sorry, I must have missed the v5, sorry about that.
> > > > >
> > > > > I probably asked this question before, but just to make sure - I see
> > > > > references to HID in the patch - the device is really not HID
> > > > > compatible? Is there any hope it could be made work with i2c-hid +
> > > > > hid-multitouch?
> > > > >
> > > > > Thanks.
> > > > >  
> > > >
> > > > I have checked and, for what I have seen, all the HID descriptor stuff
> > > > is HID compliant. We could definitely use i2c-hid and hid-multitouch
> > > > (there is the "hid-cypress" driver that exists also).
> > > >
> > > > The only problem is that this touchscreen has two modes: a bootloader
> > > > mode and an application mode (which is the one where we can send
> > > > HID commands). After a power-on-reset, it is always in "bootloader"
> > > > mode so we need to send some commands (called "bootloader commands") to
> > > > switch to application mode.  
> > >
> > > Is this a documented or observed behavior? In my practice devices (I am
> > > talking in general, not about Cypress) that have proper configuration
> > > loaded and that were brought up with appropriate power up sequence and
> > > timings automatically switch to application mode. They only end up in
> > > bootloader mode when proper power up sequence is not respected and they
> > > are unhappy.  
> >
> > I have checked and indeed, if everything is correctly performed, the
> > bootloader has a timeout to switch to application mode.
> > The datasheet says that this timeout can be configured and the "0" value
> > means that the bootloader will never automatically switch to application
> > unless a bootloader command is sent.
> >
> > In our case, you were right, after a timeout, the touchscreen is
> > correctly switching to Application mode. Great news!
> >  
> > >  
> > > > These commands are not HID-compliant as the
> > > > datasheet indicates:
> > > >
> > > > "Bootloader commands are not HID-over-I2C compliant."  
> > >
> > > Any chance you could share the datasheet?  
> >
> > Sorry, it is not possible, the datasheet is under NDA :(
> >  
> > >  
> > > >
> > > > I think that if the touchscreen would start directly in "application"
> > > > mode, we could directly use i2c-hid and hid-cypress drivers.
> > > > Unfortunately, this is not the case.
> > > >
> > > > In bootloader mode, the ProductID is 0xc101 and in application mode, it
> > > > is 0xc001 (already available in hid-ids.h:
> > > > USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)
> > > >
> 

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hi Dmitry,

On Tue, 24 Jul 2018 10:40:53 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 24, 2018 at 03:00:46PM +0200, Mylène Josserand wrote:
> > Hello Dmitry,
> > 
> > On Wed, 4 Jul 2018 16:21:58 +
> > Dmitry Torokhov  wrote:
> >   
> > > Hi Mylène,
> > > 
> > > On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:  
> > > > Hello,
> > > > 
> > > > Here is a V6 series to add the driver of the touchscreen Cypress,
> > > > TrueTouch Generation 5.
> > > > Based on v4.18-rc3.
> > > > 
> > > > This patch series has already been posted in several iterations:
> > > > - v1: Sent on 2017/05/29
> > > > - v2: Sent on 2017/08/18
> > > > - v3: Sent on 2017/09/27
> > > > - v4: Sent on 2017/12/01
> > > > - v5: Sent on 2017/12/20
> > > > 
> > > > I did not have any comments the last 4 versions.
> > > > And no reviews on my v5 during 6 months. Could I have any updates
> > > > or feedback on my series to know why it is not merged (to be able to
> > > > correct what is wrong)?
> > > 
> > > Sorry, I must have missed the v5, sorry about that.
> > > 
> > > I probably asked this question before, but just to make sure - I see
> > > references to HID in the patch - the device is really not HID
> > > compatible? Is there any hope it could be made work with i2c-hid +
> > > hid-multitouch?
> > > 
> > > Thanks.
> > >   
> > 
> > I have checked and, for what I have seen, all the HID descriptor stuff
> > is HID compliant. We could definitely use i2c-hid and hid-multitouch
> > (there is the "hid-cypress" driver that exists also).
> > 
> > The only problem is that this touchscreen has two modes: a bootloader
> > mode and an application mode (which is the one where we can send
> > HID commands). After a power-on-reset, it is always in "bootloader"
> > mode so we need to send some commands (called "bootloader commands") to
> > switch to application mode.  
> 
> Is this a documented or observed behavior? In my practice devices (I am
> talking in general, not about Cypress) that have proper configuration
> loaded and that were brought up with appropriate power up sequence and
> timings automatically switch to application mode. They only end up in
> bootloader mode when proper power up sequence is not respected and they
> are unhappy.

I have checked and indeed, if everything is correctly performed, the
bootloader has a timeout to switch to application mode.
The datasheet says that this timeout can be configured and the "0" value
means that the bootloader will never automatically switch to application
unless a bootloader command is sent.

In our case, you were right, after a timeout, the touchscreen is
correctly switching to Application mode. Great news!

> 
> > These commands are not HID-compliant as the
> > datasheet indicates:
> > 
> > "Bootloader commands are not HID-over-I2C compliant."  
> 
> Any chance you could share the datasheet?

Sorry, it is not possible, the datasheet is under NDA :(

> 
> > 
> > I think that if the touchscreen would start directly in "application"
> > mode, we could directly use i2c-hid and hid-cypress drivers.
> > Unfortunately, this is not the case.
> > 
> > In bootloader mode, the ProductID is 0xc101 and in application mode, it
> > is 0xc001 (already available in hid-ids.h:
> > USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)
> > 
> > What would be the better approach here?
> > Should I add a new product ID to detect the bootloader mode in
> > hid-cypress driver and send non-HID commands to switch to
> > "application" mode in this driver?
> > Anyway, I guess that I will drop this cyttsp5 driver and update the
> > existing one, right?  
> 
> So it still accessible through HID, even when in bootloader mode? OK,
> then I guess there are 2 options:
> 
> - if device is documented to always start in bootloader mode, you could
>   have a small stub driver that switches it into application mode in its
>   probe() code. The "bootloader" device will disappear and
>   "application" device will appear, and standard driver (hid-multitouch)
>   will bind to it.

Okay, I see. In our case, we do not have the timeout to 0 as after a
moment, the application mode is automatically switched.

> 
> - if device supposed to come up in application mode unless configuration
>   is damaged: I'd 

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hi Dmitry,

On Tue, 24 Jul 2018 10:40:53 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 24, 2018 at 03:00:46PM +0200, Mylène Josserand wrote:
> > Hello Dmitry,
> > 
> > On Wed, 4 Jul 2018 16:21:58 +
> > Dmitry Torokhov  wrote:
> >   
> > > Hi Mylène,
> > > 
> > > On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:  
> > > > Hello,
> > > > 
> > > > Here is a V6 series to add the driver of the touchscreen Cypress,
> > > > TrueTouch Generation 5.
> > > > Based on v4.18-rc3.
> > > > 
> > > > This patch series has already been posted in several iterations:
> > > > - v1: Sent on 2017/05/29
> > > > - v2: Sent on 2017/08/18
> > > > - v3: Sent on 2017/09/27
> > > > - v4: Sent on 2017/12/01
> > > > - v5: Sent on 2017/12/20
> > > > 
> > > > I did not have any comments the last 4 versions.
> > > > And no reviews on my v5 during 6 months. Could I have any updates
> > > > or feedback on my series to know why it is not merged (to be able to
> > > > correct what is wrong)?
> > > 
> > > Sorry, I must have missed the v5, sorry about that.
> > > 
> > > I probably asked this question before, but just to make sure - I see
> > > references to HID in the patch - the device is really not HID
> > > compatible? Is there any hope it could be made work with i2c-hid +
> > > hid-multitouch?
> > > 
> > > Thanks.
> > >   
> > 
> > I have checked and, for what I have seen, all the HID descriptor stuff
> > is HID compliant. We could definitely use i2c-hid and hid-multitouch
> > (there is the "hid-cypress" driver that exists also).
> > 
> > The only problem is that this touchscreen has two modes: a bootloader
> > mode and an application mode (which is the one where we can send
> > HID commands). After a power-on-reset, it is always in "bootloader"
> > mode so we need to send some commands (called "bootloader commands") to
> > switch to application mode.  
> 
> Is this a documented or observed behavior? In my practice devices (I am
> talking in general, not about Cypress) that have proper configuration
> loaded and that were brought up with appropriate power up sequence and
> timings automatically switch to application mode. They only end up in
> bootloader mode when proper power up sequence is not respected and they
> are unhappy.

I have checked and indeed, if everything is correctly performed, the
bootloader has a timeout to switch to application mode.
The datasheet says that this timeout can be configured and the "0" value
means that the bootloader will never automatically switch to application
unless a bootloader command is sent.

In our case, you were right, after a timeout, the touchscreen is
correctly switching to Application mode. Great news!

> 
> > These commands are not HID-compliant as the
> > datasheet indicates:
> > 
> > "Bootloader commands are not HID-over-I2C compliant."  
> 
> Any chance you could share the datasheet?

Sorry, it is not possible, the datasheet is under NDA :(

> 
> > 
> > I think that if the touchscreen would start directly in "application"
> > mode, we could directly use i2c-hid and hid-cypress drivers.
> > Unfortunately, this is not the case.
> > 
> > In bootloader mode, the ProductID is 0xc101 and in application mode, it
> > is 0xc001 (already available in hid-ids.h:
> > USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)
> > 
> > What would be the better approach here?
> > Should I add a new product ID to detect the bootloader mode in
> > hid-cypress driver and send non-HID commands to switch to
> > "application" mode in this driver?
> > Anyway, I guess that I will drop this cyttsp5 driver and update the
> > existing one, right?  
> 
> So it still accessible through HID, even when in bootloader mode? OK,
> then I guess there are 2 options:
> 
> - if device is documented to always start in bootloader mode, you could
>   have a small stub driver that switches it into application mode in its
>   probe() code. The "bootloader" device will disappear and
>   "application" device will appear, and standard driver (hid-multitouch)
>   will bind to it.

Okay, I see. In our case, we do not have the timeout to 0 as after a
moment, the application mode is automatically switched.

> 
> - if device supposed to come up in application mode unless configuration
>   is damaged: I'd 

Re: [PATCH v4 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello Dmitry,

Thank you again for the review.

On Wed, 25 Jul 2018 17:47:32 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Wed, Jul 25, 2018 at 09:34:08AM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > Reviewed-by: Rob Herring 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> >  drivers/input/touchscreen/edt-ft5x06.c | 43 
> > ++
> >  2 files changed, 44 insertions(+)
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > index 025cf8c9324a..48e975b9c1aa 100644
> > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > @@ -30,6 +30,7 @@ Required properties:
> >  Optional properties:
> >   - reset-gpios: GPIO specification for the RESET input
> >   - wake-gpios:  GPIO specification for the WAKE input
> > + - vcc-supply:  Regulator that supplies the touchscreen
> >  
> >   - pinctrl-names: should be "default"
> >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > b/drivers/input/touchscreen/edt-ft5x06.c
> > index 1e18ca0d1b4e..dcde719094f7 100644
> > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > @@ -39,6 +39,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #define WORK_REGISTER_THRESHOLD0x00
> >  #define WORK_REGISTER_REPORT_RATE  0x08
> > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > struct touchscreen_properties prop;
> > u16 num_x;
> > u16 num_y;
> > +   struct regulator *vcc;
> >  
> > struct gpio_desc *reset_gpio;
> > struct gpio_desc *wake_gpio;
> > @@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data 
> > *tsdata)
> > }
> >  }
> >  
> > +static void edt_ft5x06_disable_regulator(void *arg)
> > +{
> > +   struct edt_ft5x06_ts_data *data = arg;
> > +
> > +   regulator_disable(data->vcc);
> > +}
> > +
> >  static int edt_ft5x06_ts_probe(struct i2c_client *client,
> >  const struct i2c_device_id *id)
> >  {
> > @@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > *client,
> >  
> > tsdata->max_support_points = chip_data->max_support_points;
> >  
> > +   tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > +   if (IS_ERR(tsdata->vcc)) {
> > +   error = PTR_ERR(tsdata->vcc);
> > +   if (error != -EPROBE_DEFER)
> > +   dev_err(>dev, "failed to request regulator: 
> > %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > +   error = regulator_enable(tsdata->vcc);
> > +   if (error < 0) {
> > +   dev_err(>dev, "failed to enable vcc: %d\n",
> > +   error);
> > +   return error;
> > +   }  
> 
> It is better to put the chip into reset and then power up the regulatori
> and take it out of the reset, rather than power up and then toggle reset
> on and off.

okay, thanks, I will update it.

> 
> > +
> > +   error = devm_add_action_or_reset(>dev,
> > +edt_ft5x06_disable_regulator,
> > +tsdata);
> > +   if (error)
> > +   return error;
> > +
> > tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> >  "reset", GPIOD_OUT_HIGH);
> > if (IS_ERR(tsdata->reset_gpio)) {
> > @@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > *client)
> >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> >  
> > if (device_may_wakeup(dev))
> > enable_irq_wake(client->irq);
> > +   else
> > +   regulator_disable(tsdata->vcc);
> >  
> > return 0;
> >  }
> > @@ -1130,9 +1164,18 @@ static int __maybe_unused 
> > edt_

Re: [PATCH v4 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello Dmitry,

Thank you again for the review.

On Wed, 25 Jul 2018 17:47:32 -0700
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Wed, Jul 25, 2018 at 09:34:08AM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > Reviewed-by: Rob Herring 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> >  drivers/input/touchscreen/edt-ft5x06.c | 43 
> > ++
> >  2 files changed, 44 insertions(+)
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > index 025cf8c9324a..48e975b9c1aa 100644
> > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > @@ -30,6 +30,7 @@ Required properties:
> >  Optional properties:
> >   - reset-gpios: GPIO specification for the RESET input
> >   - wake-gpios:  GPIO specification for the WAKE input
> > + - vcc-supply:  Regulator that supplies the touchscreen
> >  
> >   - pinctrl-names: should be "default"
> >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > b/drivers/input/touchscreen/edt-ft5x06.c
> > index 1e18ca0d1b4e..dcde719094f7 100644
> > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > @@ -39,6 +39,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #define WORK_REGISTER_THRESHOLD0x00
> >  #define WORK_REGISTER_REPORT_RATE  0x08
> > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > struct touchscreen_properties prop;
> > u16 num_x;
> > u16 num_y;
> > +   struct regulator *vcc;
> >  
> > struct gpio_desc *reset_gpio;
> > struct gpio_desc *wake_gpio;
> > @@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data 
> > *tsdata)
> > }
> >  }
> >  
> > +static void edt_ft5x06_disable_regulator(void *arg)
> > +{
> > +   struct edt_ft5x06_ts_data *data = arg;
> > +
> > +   regulator_disable(data->vcc);
> > +}
> > +
> >  static int edt_ft5x06_ts_probe(struct i2c_client *client,
> >  const struct i2c_device_id *id)
> >  {
> > @@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > *client,
> >  
> > tsdata->max_support_points = chip_data->max_support_points;
> >  
> > +   tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > +   if (IS_ERR(tsdata->vcc)) {
> > +   error = PTR_ERR(tsdata->vcc);
> > +   if (error != -EPROBE_DEFER)
> > +   dev_err(>dev, "failed to request regulator: 
> > %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > +   error = regulator_enable(tsdata->vcc);
> > +   if (error < 0) {
> > +   dev_err(>dev, "failed to enable vcc: %d\n",
> > +   error);
> > +   return error;
> > +   }  
> 
> It is better to put the chip into reset and then power up the regulatori
> and take it out of the reset, rather than power up and then toggle reset
> on and off.

okay, thanks, I will update it.

> 
> > +
> > +   error = devm_add_action_or_reset(>dev,
> > +edt_ft5x06_disable_regulator,
> > +tsdata);
> > +   if (error)
> > +   return error;
> > +
> > tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> >  "reset", GPIOD_OUT_HIGH);
> > if (IS_ERR(tsdata->reset_gpio)) {
> > @@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > *client)
> >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> >  
> > if (device_may_wakeup(dev))
> > enable_irq_wake(client->irq);
> > +   else
> > +   regulator_disable(tsdata->vcc);
> >  
> > return 0;
> >  }
> > @@ -1130,9 +1164,18 @@ static int __maybe_unused 
> > edt_

[PATCH v4 3/3] arm: dts: sun8i: a83t: a711: Add touchscreen node

[Mylène Josserand]

Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts 
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
 };
 
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   touchscreen@38 {
+   compatible = "edt,edt-ft5x06";
+   reg = <0x38>;
+   interrupt-parent = <_pio>;
+   interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 3 5 GPIO_ACTIVE_LOW>;
+   vcc-supply = <_ldo_io0>;
+   touchscreen-size-x = <1024>;
+   touchscreen-size-y = <600>;
+   };
+};
+
  {
vmmc-supply = <_dcdc1>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH v4 3/3] arm: dts: sun8i: a83t: a711: Add touchscreen node

[Mylène Josserand]

Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts 
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
 };
 
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   touchscreen@38 {
+   compatible = "edt,edt-ft5x06";
+   reg = <0x38>;
+   interrupt-parent = <_pio>;
+   interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 3 5 GPIO_ACTIVE_LOW>;
+   vcc-supply = <_ldo_io0>;
+   touchscreen-size-x = <1024>;
+   touchscreen-size-y = <600>;
+   };
+};
+
  {
vmmc-supply = <_dcdc1>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH v4 0/3] sun8i-a83t: Add touchscreen support on TBS A711

[Mylène Josserand]

Hello everyone,

This is a V4 of the patch series that adds touchscreen support
(FocalTech EDT-FT5x06 Polytouch) for TBS A711 (Allwinner sun8i-a83t SoC)
and add regulator support for this touchscreen.
Based on last master of linux-input tree.

Changes since v3:
   - Created a new function to disable regulator via
   devm_add_action_or_reset (Dmitry Torokhov's review)
   - Moved regulator_enable/disable functions in device_may_wakeup
   guard (Ondřej Jirman and Dmitry Torokhov's reviews)
   - Added Rob Herring Reviewed-by on patch 01 (sorry again)
Changes since v2:
   - Removed the check if regulator is NULL (Dmitry Torokhov's review)
   - Added EPROBE_DEFER error not to print a error message (Lothar Waßmann's 
review)
   - Added set wake/reset on suspend/resume.
Changes since v1:
   - Removed patches 01 and 02 as Chen-Yu Tsai sent a similar patch:
   https://patchwork.kernel.org/patch/10111431/
   and it is merged on last next-20171222.
   (See commit f066f46ce5a5 "ARM: dts: sun8i: a83t: Add I2C device nodes and 
pinmux settings")
   - Updated regulator according to Dmitry Torokhov's review: removed "optional"
   suffix while retrieving the regulator, renamed it into "vcc" instead of
   "power" and added bindings documentation.
   - Updated device tree according to Maxime Ripard's review: remove the
   label and rename the node.
   - Squashed patch 03 with patch 05 to add I2C0 and touchscreen's node
   in one patch (see patch 02).

Patch 01: Add support for regulator in the FocalTech touchscreen driver
because A711 tablet is using a regulator to power-up the touchscreen.
Patch 02: Add a set wake/reset values on resume and suspend.
Patch 03: Add i2c0 and touchscreen's node for A711 TBS tablet.

Thank you in advance for any review.
Best regards,
Mylène

Mylène Josserand (3):
  Input: edt-ft5x06 - Add support for regulator
  Input: edt-ft5x06 - Set wake/reset values on resume/suspend
  arm: dts: sun8i: a83t: a711: Add touchscreen node

 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts  | 16 +++
 drivers/input/touchscreen/edt-ft5x06.c | 55 ++
 3 files changed, 72 insertions(+)

-- 
2.11.0

[PATCH v4 0/3] sun8i-a83t: Add touchscreen support on TBS A711

[Mylène Josserand]

Hello everyone,

This is a V4 of the patch series that adds touchscreen support
(FocalTech EDT-FT5x06 Polytouch) for TBS A711 (Allwinner sun8i-a83t SoC)
and add regulator support for this touchscreen.
Based on last master of linux-input tree.

Changes since v3:
   - Created a new function to disable regulator via
   devm_add_action_or_reset (Dmitry Torokhov's review)
   - Moved regulator_enable/disable functions in device_may_wakeup
   guard (Ondřej Jirman and Dmitry Torokhov's reviews)
   - Added Rob Herring Reviewed-by on patch 01 (sorry again)
Changes since v2:
   - Removed the check if regulator is NULL (Dmitry Torokhov's review)
   - Added EPROBE_DEFER error not to print a error message (Lothar Waßmann's 
review)
   - Added set wake/reset on suspend/resume.
Changes since v1:
   - Removed patches 01 and 02 as Chen-Yu Tsai sent a similar patch:
   https://patchwork.kernel.org/patch/10111431/
   and it is merged on last next-20171222.
   (See commit f066f46ce5a5 "ARM: dts: sun8i: a83t: Add I2C device nodes and 
pinmux settings")
   - Updated regulator according to Dmitry Torokhov's review: removed "optional"
   suffix while retrieving the regulator, renamed it into "vcc" instead of
   "power" and added bindings documentation.
   - Updated device tree according to Maxime Ripard's review: remove the
   label and rename the node.
   - Squashed patch 03 with patch 05 to add I2C0 and touchscreen's node
   in one patch (see patch 02).

Patch 01: Add support for regulator in the FocalTech touchscreen driver
because A711 tablet is using a regulator to power-up the touchscreen.
Patch 02: Add a set wake/reset values on resume and suspend.
Patch 03: Add i2c0 and touchscreen's node for A711 TBS tablet.

Thank you in advance for any review.
Best regards,
Mylène

Mylène Josserand (3):
  Input: edt-ft5x06 - Add support for regulator
  Input: edt-ft5x06 - Set wake/reset values on resume/suspend
  arm: dts: sun8i: a83t: a711: Add touchscreen node

 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts  | 16 +++
 drivers/input/touchscreen/edt-ft5x06.c | 55 ++
 3 files changed, 72 insertions(+)

-- 
2.11.0

[PATCH v4 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Add the support of regulator to use it as VCC source.

Signed-off-by: Mylène Josserand 
Reviewed-by: Rob Herring 
---
 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 drivers/input/touchscreen/edt-ft5x06.c | 43 ++
 2 files changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..48e975b9c1aa 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -30,6 +30,7 @@ Required properties:
 Optional properties:
  - reset-gpios: GPIO specification for the RESET input
  - wake-gpios:  GPIO specification for the WAKE input
+ - vcc-supply:  Regulator that supplies the touchscreen
 
  - pinctrl-names: should be "default"
  - pinctrl-0:   a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..dcde719094f7 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define WORK_REGISTER_THRESHOLD0x00
 #define WORK_REGISTER_REPORT_RATE  0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+   struct regulator *vcc;
 
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data *tsdata)
}
 }
 
+static void edt_ft5x06_disable_regulator(void *arg)
+{
+   struct edt_ft5x06_ts_data *data = arg;
+
+   regulator_disable(data->vcc);
+}
+
 static int edt_ft5x06_ts_probe(struct i2c_client *client,
 const struct i2c_device_id *id)
 {
@@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
 
tsdata->max_support_points = chip_data->max_support_points;
 
+   tsdata->vcc = devm_regulator_get(>dev, "vcc");
+   if (IS_ERR(tsdata->vcc)) {
+   error = PTR_ERR(tsdata->vcc);
+   if (error != -EPROBE_DEFER)
+   dev_err(>dev, "failed to request regulator: 
%d\n",
+   error);
+   return error;
+   }
+
+   error = regulator_enable(tsdata->vcc);
+   if (error < 0) {
+   dev_err(>dev, "failed to enable vcc: %d\n",
+   error);
+   return error;
+   }
+
+   error = devm_add_action_or_reset(>dev,
+edt_ft5x06_disable_regulator,
+tsdata);
+   if (error)
+   return error;
+
tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
 "reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
*client)
 static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
 
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+   else
+   regulator_disable(tsdata->vcc);
 
return 0;
 }
@@ -1130,9 +1164,18 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
 static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+   int ret;
 
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+   else {
+   ret = regulator_enable(tsdata->vcc);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vcc: %d\n", ret);
+   return ret;
+   }
+   }
 
return 0;
 }
-- 
2.11.0

[PATCH v4 2/3] Input: edt-ft5x06 - Set wake/reset values on resume/suspend

[Mylène Josserand]

On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.

Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/edt-ft5x06.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index dcde719094f7..dad2f1f8bf89 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1158,6 +1158,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
else
regulator_disable(tsdata->vcc);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 0);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 1);
+
return 0;
 }
 
@@ -1177,6 +1183,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct 
device *dev)
}
}
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 1);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 0);
+
return 0;
 }
 
-- 
2.11.0

[PATCH v4 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Add the support of regulator to use it as VCC source.

Signed-off-by: Mylène Josserand 
Reviewed-by: Rob Herring 
---
 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 drivers/input/touchscreen/edt-ft5x06.c | 43 ++
 2 files changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..48e975b9c1aa 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -30,6 +30,7 @@ Required properties:
 Optional properties:
  - reset-gpios: GPIO specification for the RESET input
  - wake-gpios:  GPIO specification for the WAKE input
+ - vcc-supply:  Regulator that supplies the touchscreen
 
  - pinctrl-names: should be "default"
  - pinctrl-0:   a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..dcde719094f7 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define WORK_REGISTER_THRESHOLD0x00
 #define WORK_REGISTER_REPORT_RATE  0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+   struct regulator *vcc;
 
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data *tsdata)
}
 }
 
+static void edt_ft5x06_disable_regulator(void *arg)
+{
+   struct edt_ft5x06_ts_data *data = arg;
+
+   regulator_disable(data->vcc);
+}
+
 static int edt_ft5x06_ts_probe(struct i2c_client *client,
 const struct i2c_device_id *id)
 {
@@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
 
tsdata->max_support_points = chip_data->max_support_points;
 
+   tsdata->vcc = devm_regulator_get(>dev, "vcc");
+   if (IS_ERR(tsdata->vcc)) {
+   error = PTR_ERR(tsdata->vcc);
+   if (error != -EPROBE_DEFER)
+   dev_err(>dev, "failed to request regulator: 
%d\n",
+   error);
+   return error;
+   }
+
+   error = regulator_enable(tsdata->vcc);
+   if (error < 0) {
+   dev_err(>dev, "failed to enable vcc: %d\n",
+   error);
+   return error;
+   }
+
+   error = devm_add_action_or_reset(>dev,
+edt_ft5x06_disable_regulator,
+tsdata);
+   if (error)
+   return error;
+
tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
 "reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
*client)
 static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
 
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+   else
+   regulator_disable(tsdata->vcc);
 
return 0;
 }
@@ -1130,9 +1164,18 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
 static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+   int ret;
 
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+   else {
+   ret = regulator_enable(tsdata->vcc);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vcc: %d\n", ret);
+   return ret;
+   }
+   }
 
return 0;
 }
-- 
2.11.0

[PATCH v4 2/3] Input: edt-ft5x06 - Set wake/reset values on resume/suspend

[Mylène Josserand]

On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.

Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/edt-ft5x06.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index dcde719094f7..dad2f1f8bf89 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1158,6 +1158,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
else
regulator_disable(tsdata->vcc);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 0);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 1);
+
return 0;
 }
 
@@ -1177,6 +1183,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct 
device *dev)
}
}
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 1);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 0);
+
return 0;
 }
 
-- 
2.11.0

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello Dmitry,

Thank you for your review!

On Mon, 23 Jul 2018 15:39:26 -0700
Dmitry Torokhov  wrote:

> On Thu, Jul 19, 2018 at 12:46:45AM +0200, Ondřej Jirman wrote:
> > Hello Mylène,
> > 
> > On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:  
> > > Add the support of regulator to use it as VCC source.
> > > 
> > > Signed-off-by: Mylène Josserand 
> > > ---
> > >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> > >  drivers/input/touchscreen/edt-ft5x06.c | 29 
> > > ++
> > >  2 files changed, 30 insertions(+)
> > > 
> > > diff --git 
> > > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > index 025cf8c9324a..48e975b9c1aa 100644
> > > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > @@ -30,6 +30,7 @@ Required properties:
> > >  Optional properties:
> > >   - reset-gpios: GPIO specification for the RESET input
> > >   - wake-gpios:  GPIO specification for the WAKE input
> > > + - vcc-supply:  Regulator that supplies the touchscreen
> > >  
> > >   - pinctrl-names: should be "default"
> > >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > > b/drivers/input/touchscreen/edt-ft5x06.c
> > > index 1e18ca0d1b4e..aa94494b06b5 100644
> > > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > > @@ -39,6 +39,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >  
> > >  #define WORK_REGISTER_THRESHOLD  0x00
> > >  #define WORK_REGISTER_REPORT_RATE0x08
> > > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > >   struct touchscreen_properties prop;
> > >   u16 num_x;
> > >   u16 num_y;
> > > + struct regulator *vcc;
> > >  
> > >   struct gpio_desc *reset_gpio;
> > >   struct gpio_desc *wake_gpio;
> > > @@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > > *client,
> > >  
> > >   tsdata->max_support_points = chip_data->max_support_points;
> > >  
> > > + tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > > + if (IS_ERR(tsdata->vcc)) {
> > > + error = PTR_ERR(tsdata->vcc);
> > > + if (error != -EPROBE_DEFER)
> > > + dev_err(>dev, "failed to request regulator: 
> > > %d\n",
> > > + error);
> > > + return error;
> > > + }
> > > +
> > > + error = regulator_enable(tsdata->vcc);
> > > + if (error < 0) {
> > > + dev_err(>dev, "failed to enable vcc: %d\n",
> > > + error);
> > > + return error;
> > > + }
> > > +
> > >   tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> > >"reset", GPIOD_OUT_HIGH);
> > >   if (IS_ERR(tsdata->reset_gpio)) {  
> 
> You need to disable regulator here. We do not have
> devm_regulator_enable() (and Mark had some concerns about mixing managed
> and unmanaged APIs for regulators so we can't simply introduce it),
> so I'd recommend using devm_add_action_or_reset() and iunstall custom
> action to turn off regulator.

Yep, I see. Thank you about "devm_add_action_or_reset", I did not know
this function. I will add it in next version.

> 
> > > @@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > > *client)
> > >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> > >  {
> > >   struct i2c_client *client = to_i2c_client(dev);
> > > + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> > >  
> > >   if (device_may_wakeup(dev))
> > >   enable_irq_wake(client->irq);
> > >  
> > > + regulator_disable(tsdata->vcc);
> > > +  
> > 
> > How will the touchscreen wakeup the system with interrupt if you power it 
> > off
> > on suspend? Perhaps guard this with device_may_wakeup() too?   
> 
> Exactly, it should be in an "else" branch.
> 
> Thanks.
> 

I see, I will add it in v4.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello Dmitry,

Thank you for your review!

On Mon, 23 Jul 2018 15:39:26 -0700
Dmitry Torokhov  wrote:

> On Thu, Jul 19, 2018 at 12:46:45AM +0200, Ondřej Jirman wrote:
> > Hello Mylène,
> > 
> > On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:  
> > > Add the support of regulator to use it as VCC source.
> > > 
> > > Signed-off-by: Mylène Josserand 
> > > ---
> > >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> > >  drivers/input/touchscreen/edt-ft5x06.c | 29 
> > > ++
> > >  2 files changed, 30 insertions(+)
> > > 
> > > diff --git 
> > > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > index 025cf8c9324a..48e975b9c1aa 100644
> > > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > > @@ -30,6 +30,7 @@ Required properties:
> > >  Optional properties:
> > >   - reset-gpios: GPIO specification for the RESET input
> > >   - wake-gpios:  GPIO specification for the WAKE input
> > > + - vcc-supply:  Regulator that supplies the touchscreen
> > >  
> > >   - pinctrl-names: should be "default"
> > >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > > b/drivers/input/touchscreen/edt-ft5x06.c
> > > index 1e18ca0d1b4e..aa94494b06b5 100644
> > > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > > @@ -39,6 +39,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >  
> > >  #define WORK_REGISTER_THRESHOLD  0x00
> > >  #define WORK_REGISTER_REPORT_RATE0x08
> > > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > >   struct touchscreen_properties prop;
> > >   u16 num_x;
> > >   u16 num_y;
> > > + struct regulator *vcc;
> > >  
> > >   struct gpio_desc *reset_gpio;
> > >   struct gpio_desc *wake_gpio;
> > > @@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > > *client,
> > >  
> > >   tsdata->max_support_points = chip_data->max_support_points;
> > >  
> > > + tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > > + if (IS_ERR(tsdata->vcc)) {
> > > + error = PTR_ERR(tsdata->vcc);
> > > + if (error != -EPROBE_DEFER)
> > > + dev_err(>dev, "failed to request regulator: 
> > > %d\n",
> > > + error);
> > > + return error;
> > > + }
> > > +
> > > + error = regulator_enable(tsdata->vcc);
> > > + if (error < 0) {
> > > + dev_err(>dev, "failed to enable vcc: %d\n",
> > > + error);
> > > + return error;
> > > + }
> > > +
> > >   tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> > >"reset", GPIOD_OUT_HIGH);
> > >   if (IS_ERR(tsdata->reset_gpio)) {  
> 
> You need to disable regulator here. We do not have
> devm_regulator_enable() (and Mark had some concerns about mixing managed
> and unmanaged APIs for regulators so we can't simply introduce it),
> so I'd recommend using devm_add_action_or_reset() and iunstall custom
> action to turn off regulator.

Yep, I see. Thank you about "devm_add_action_or_reset", I did not know
this function. I will add it in next version.

> 
> > > @@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > > *client)
> > >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> > >  {
> > >   struct i2c_client *client = to_i2c_client(dev);
> > > + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> > >  
> > >   if (device_may_wakeup(dev))
> > >   enable_irq_wake(client->irq);
> > >  
> > > + regulator_disable(tsdata->vcc);
> > > +  
> > 
> > How will the touchscreen wakeup the system with interrupt if you power it 
> > off
> > on suspend? Perhaps guard this with device_may_wakeup() too?   
> 
> Exactly, it should be in an "else" branch.
> 
> Thanks.
> 

I see, I will add it in v4.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello,

Thank you for your review.

On Thu, 19 Jul 2018 00:46:45 +0200
Ondřej Jirman  wrote:

> Hello Mylène,
> 
> On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> >  drivers/input/touchscreen/edt-ft5x06.c | 29 
> > ++
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > index 025cf8c9324a..48e975b9c1aa 100644
> > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > @@ -30,6 +30,7 @@ Required properties:
> >  Optional properties:
> >   - reset-gpios: GPIO specification for the RESET input
> >   - wake-gpios:  GPIO specification for the WAKE input
> > + - vcc-supply:  Regulator that supplies the touchscreen
> >  
> >   - pinctrl-names: should be "default"
> >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > b/drivers/input/touchscreen/edt-ft5x06.c
> > index 1e18ca0d1b4e..aa94494b06b5 100644
> > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > @@ -39,6 +39,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #define WORK_REGISTER_THRESHOLD0x00
> >  #define WORK_REGISTER_REPORT_RATE  0x08
> > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > struct touchscreen_properties prop;
> > u16 num_x;
> > u16 num_y;
> > +   struct regulator *vcc;
> >  
> > struct gpio_desc *reset_gpio;
> > struct gpio_desc *wake_gpio;
> > @@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > *client,
> >  
> > tsdata->max_support_points = chip_data->max_support_points;
> >  
> > +   tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > +   if (IS_ERR(tsdata->vcc)) {
> > +   error = PTR_ERR(tsdata->vcc);
> > +   if (error != -EPROBE_DEFER)
> > +   dev_err(>dev, "failed to request regulator: 
> > %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > +   error = regulator_enable(tsdata->vcc);
> > +   if (error < 0) {
> > +   dev_err(>dev, "failed to enable vcc: %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> >  "reset", GPIOD_OUT_HIGH);
> > if (IS_ERR(tsdata->reset_gpio)) {
> > @@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > *client)
> >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> >  
> > if (device_may_wakeup(dev))
> > enable_irq_wake(client->irq);
> >  
> > +   regulator_disable(tsdata->vcc);
> > +  
> 
> How will the touchscreen wakeup the system with interrupt if you power it off
> on suspend? Perhaps guard this with device_may_wakeup() too? 

True, thank you for pointing it out.

> 
> > return 0;
> >  }
> >  
> >  static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> > +   int ret;
> >  
> > if (device_may_wakeup(dev))
> > disable_irq_wake(client->irq);
> >  
> > +   ret = regulator_enable(tsdata->vcc);
> > +   if (ret < 0) {
> > +   dev_err(dev, "failed to enable vcc: %d\n", ret);
> > +   return ret;
> > +   }
> > +  
> 
> Ditto.

ack

> 
> Regards,
>   o.
> 
> > return 0;
> >  }
> >  
> > -- 
> > 2.11.0
> > 
> > 
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel  


Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello,

Thank you for your review.

On Thu, 19 Jul 2018 00:46:45 +0200
Ondřej Jirman  wrote:

> Hello Mylène,
> 
> On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
> >  drivers/input/touchscreen/edt-ft5x06.c | 29 
> > ++
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
> > b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > index 025cf8c9324a..48e975b9c1aa 100644
> > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> > @@ -30,6 +30,7 @@ Required properties:
> >  Optional properties:
> >   - reset-gpios: GPIO specification for the RESET input
> >   - wake-gpios:  GPIO specification for the WAKE input
> > + - vcc-supply:  Regulator that supplies the touchscreen
> >  
> >   - pinctrl-names: should be "default"
> >   - pinctrl-0:   a phandle pointing to the pin settings for the
> > diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
> > b/drivers/input/touchscreen/edt-ft5x06.c
> > index 1e18ca0d1b4e..aa94494b06b5 100644
> > --- a/drivers/input/touchscreen/edt-ft5x06.c
> > +++ b/drivers/input/touchscreen/edt-ft5x06.c
> > @@ -39,6 +39,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #define WORK_REGISTER_THRESHOLD0x00
> >  #define WORK_REGISTER_REPORT_RATE  0x08
> > @@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
> > struct touchscreen_properties prop;
> > u16 num_x;
> > u16 num_y;
> > +   struct regulator *vcc;
> >  
> > struct gpio_desc *reset_gpio;
> > struct gpio_desc *wake_gpio;
> > @@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client 
> > *client,
> >  
> > tsdata->max_support_points = chip_data->max_support_points;
> >  
> > +   tsdata->vcc = devm_regulator_get(>dev, "vcc");
> > +   if (IS_ERR(tsdata->vcc)) {
> > +   error = PTR_ERR(tsdata->vcc);
> > +   if (error != -EPROBE_DEFER)
> > +   dev_err(>dev, "failed to request regulator: 
> > %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > +   error = regulator_enable(tsdata->vcc);
> > +   if (error < 0) {
> > +   dev_err(>dev, "failed to enable vcc: %d\n",
> > +   error);
> > +   return error;
> > +   }
> > +
> > tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
> >  "reset", GPIOD_OUT_HIGH);
> > if (IS_ERR(tsdata->reset_gpio)) {
> > @@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
> > *client)
> >  static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> >  
> > if (device_may_wakeup(dev))
> > enable_irq_wake(client->irq);
> >  
> > +   regulator_disable(tsdata->vcc);
> > +  
> 
> How will the touchscreen wakeup the system with interrupt if you power it off
> on suspend? Perhaps guard this with device_may_wakeup() too? 

True, thank you for pointing it out.

> 
> > return 0;
> >  }
> >  
> >  static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
> >  {
> > struct i2c_client *client = to_i2c_client(dev);
> > +   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
> > +   int ret;
> >  
> > if (device_may_wakeup(dev))
> > disable_irq_wake(client->irq);
> >  
> > +   ret = regulator_enable(tsdata->vcc);
> > +   if (ret < 0) {
> > +   dev_err(dev, "failed to enable vcc: %d\n", ret);
> > +   return ret;
> > +   }
> > +  
> 
> Ditto.

ack

> 
> Regards,
>   o.
> 
> > return 0;
> >  }
> >  
> > -- 
> > 2.11.0
> > 
> > 
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel  


Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello,

On Fri, 20 Jul 2018 07:43:55 -0600
Rob Herring  wrote:

> On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +  
> 
> Please add acks when posting new versions.

Yes, sorry, I missed it. I will be more careful, next time.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Hello,

On Fri, 20 Jul 2018 07:43:55 -0600
Rob Herring  wrote:

> On Wed, Jul 18, 2018 at 08:27:17PM +0200, Mylène Josserand wrote:
> > Add the support of regulator to use it as VCC source.
> > 
> > Signed-off-by: Mylène Josserand 
> > ---
> >  .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +  
> 
> Please add acks when posting new versions.

Yes, sorry, I missed it. I will be more careful, next time.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Wed, 4 Jul 2018 16:21:58 +
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:
> > Hello,
> > 
> > Here is a V6 series to add the driver of the touchscreen Cypress,
> > TrueTouch Generation 5.
> > Based on v4.18-rc3.
> > 
> > This patch series has already been posted in several iterations:
> > - v1: Sent on 2017/05/29
> > - v2: Sent on 2017/08/18
> > - v3: Sent on 2017/09/27
> > - v4: Sent on 2017/12/01
> > - v5: Sent on 2017/12/20
> > 
> > I did not have any comments the last 4 versions.
> > And no reviews on my v5 during 6 months. Could I have any updates
> > or feedback on my series to know why it is not merged (to be able to
> > correct what is wrong)?  
> 
> Sorry, I must have missed the v5, sorry about that.
> 
> I probably asked this question before, but just to make sure - I see
> references to HID in the patch - the device is really not HID
> compatible? Is there any hope it could be made work with i2c-hid +
> hid-multitouch?
> 
> Thanks.
> 

I have checked and, for what I have seen, all the HID descriptor stuff
is HID compliant. We could definitely use i2c-hid and hid-multitouch
(there is the "hid-cypress" driver that exists also).

The only problem is that this touchscreen has two modes: a bootloader
mode and an application mode (which is the one where we can send
HID commands). After a power-on-reset, it is always in "bootloader"
mode so we need to send some commands (called "bootloader commands") to
switch to application mode. These commands are not HID-compliant as the
datasheet indicates:

"Bootloader commands are not HID-over-I2C compliant."

I think that if the touchscreen would start directly in "application"
mode, we could directly use i2c-hid and hid-cypress drivers.
Unfortunately, this is not the case.

In bootloader mode, the ProductID is 0xc101 and in application mode, it
is 0xc001 (already available in hid-ids.h:
USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)

What would be the better approach here?
Should I add a new product ID to detect the bootloader mode in
hid-cypress driver and send non-HID commands to switch to
"application" mode in this driver?
Anyway, I guess that I will drop this cyttsp5 driver and update the
existing one, right?

Let me know what you think about it.

Thank you in advance,

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Wed, 4 Jul 2018 16:21:58 +
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:
> > Hello,
> > 
> > Here is a V6 series to add the driver of the touchscreen Cypress,
> > TrueTouch Generation 5.
> > Based on v4.18-rc3.
> > 
> > This patch series has already been posted in several iterations:
> > - v1: Sent on 2017/05/29
> > - v2: Sent on 2017/08/18
> > - v3: Sent on 2017/09/27
> > - v4: Sent on 2017/12/01
> > - v5: Sent on 2017/12/20
> > 
> > I did not have any comments the last 4 versions.
> > And no reviews on my v5 during 6 months. Could I have any updates
> > or feedback on my series to know why it is not merged (to be able to
> > correct what is wrong)?  
> 
> Sorry, I must have missed the v5, sorry about that.
> 
> I probably asked this question before, but just to make sure - I see
> references to HID in the patch - the device is really not HID
> compatible? Is there any hope it could be made work with i2c-hid +
> hid-multitouch?
> 
> Thanks.
> 

I have checked and, for what I have seen, all the HID descriptor stuff
is HID compliant. We could definitely use i2c-hid and hid-multitouch
(there is the "hid-cypress" driver that exists also).

The only problem is that this touchscreen has two modes: a bootloader
mode and an application mode (which is the one where we can send
HID commands). After a power-on-reset, it is always in "bootloader"
mode so we need to send some commands (called "bootloader commands") to
switch to application mode. These commands are not HID-compliant as the
datasheet indicates:

"Bootloader commands are not HID-over-I2C compliant."

I think that if the touchscreen would start directly in "application"
mode, we could directly use i2c-hid and hid-cypress drivers.
Unfortunately, this is not the case.

In bootloader mode, the ProductID is 0xc101 and in application mode, it
is 0xc001 (already available in hid-ids.h:
USB_DEVICE_ID_CYPRESS_TRUETOUCH but not handled)

What would be the better approach here?
Should I add a new product ID to detect the bootloader mode in
hid-cypress driver and send non-HID commands to switch to
"application" mode in this driver?
Anyway, I guess that I will drop this cyttsp5 driver and update the
existing one, right?

Let me know what you think about it.

Thank you in advance,

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH v3 2/3] Input: edt-ft5x06 - Set wake/reset values on resume/suspend

[Mylène Josserand]

On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.

Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/edt-ft5x06.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index aa94494b06b5..b013d97006e6 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1143,6 +1143,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 0);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 1);
+
regulator_disable(tsdata->vcc);
 
return 0;
@@ -1157,6 +1163,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct 
device *dev)
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 1);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 0);
+
ret = regulator_enable(tsdata->vcc);
if (ret < 0) {
dev_err(dev, "failed to enable vcc: %d\n", ret);
-- 
2.11.0

[PATCH v3 3/3] arm: dts: sun8i: a83t: a711: Add touchscreen node

[Mylène Josserand]

Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts 
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
 };
 
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   touchscreen@38 {
+   compatible = "edt,edt-ft5x06";
+   reg = <0x38>;
+   interrupt-parent = <_pio>;
+   interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 3 5 GPIO_ACTIVE_LOW>;
+   vcc-supply = <_ldo_io0>;
+   touchscreen-size-x = <1024>;
+   touchscreen-size-y = <600>;
+   };
+};
+
  {
vmmc-supply = <_dcdc1>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH v3 3/3] arm: dts: sun8i: a83t: a711: Add touchscreen node

[Mylène Josserand]

Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts 
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
 };
 
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   touchscreen@38 {
+   compatible = "edt,edt-ft5x06";
+   reg = <0x38>;
+   interrupt-parent = <_pio>;
+   interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 3 5 GPIO_ACTIVE_LOW>;
+   vcc-supply = <_ldo_io0>;
+   touchscreen-size-x = <1024>;
+   touchscreen-size-y = <600>;
+   };
+};
+
  {
vmmc-supply = <_dcdc1>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH v3 2/3] Input: edt-ft5x06 - Set wake/reset values on resume/suspend

[Mylène Josserand]

On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.

Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/edt-ft5x06.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index aa94494b06b5..b013d97006e6 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1143,6 +1143,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct 
device *dev)
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 0);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 1);
+
regulator_disable(tsdata->vcc);
 
return 0;
@@ -1157,6 +1163,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct 
device *dev)
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
 
+   if (tsdata->wake_gpio)
+   gpiod_set_value(tsdata->wake_gpio, 1);
+
+   if (tsdata->reset_gpio)
+   gpiod_set_value(tsdata->reset_gpio, 0);
+
ret = regulator_enable(tsdata->vcc);
if (ret < 0) {
dev_err(dev, "failed to enable vcc: %d\n", ret);
-- 
2.11.0

[PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Add the support of regulator to use it as VCC source.

Signed-off-by: Mylène Josserand 
---
 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 drivers/input/touchscreen/edt-ft5x06.c | 29 ++
 2 files changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..48e975b9c1aa 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -30,6 +30,7 @@ Required properties:
 Optional properties:
  - reset-gpios: GPIO specification for the RESET input
  - wake-gpios:  GPIO specification for the WAKE input
+ - vcc-supply:  Regulator that supplies the touchscreen
 
  - pinctrl-names: should be "default"
  - pinctrl-0:   a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..aa94494b06b5 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define WORK_REGISTER_THRESHOLD0x00
 #define WORK_REGISTER_REPORT_RATE  0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+   struct regulator *vcc;
 
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
 
tsdata->max_support_points = chip_data->max_support_points;
 
+   tsdata->vcc = devm_regulator_get(>dev, "vcc");
+   if (IS_ERR(tsdata->vcc)) {
+   error = PTR_ERR(tsdata->vcc);
+   if (error != -EPROBE_DEFER)
+   dev_err(>dev, "failed to request regulator: 
%d\n",
+   error);
+   return error;
+   }
+
+   error = regulator_enable(tsdata->vcc);
+   if (error < 0) {
+   dev_err(>dev, "failed to enable vcc: %d\n",
+   error);
+   return error;
+   }
+
tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
 "reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
*client)
 static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
 
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
 
+   regulator_disable(tsdata->vcc);
+
return 0;
 }
 
 static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+   int ret;
 
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
 
+   ret = regulator_enable(tsdata->vcc);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vcc: %d\n", ret);
+   return ret;
+   }
+
return 0;
 }
 
-- 
2.11.0

[PATCH v3 0/3] sun8i-a83t: Add touchscreen support on TBS A711

[Mylène Josserand]

Hello everyone,

This is a V3 of the patch series that adds touchscreen support
(FocalTech EDT-FT5x06 Polytouch) for TBS A711 (Allwinner sun8i-a83t SoC).
Based on last master of linux-input tree.

Since I can't test the suspend/resume functions there is no updates in
this series about factory/normal mode.

Changes since v2:
   - Remove the check if regulator is NULL (Dmitry Torokhov's review)
   - Add EPROBE_DEFER error not to print a error message (Lothar Waßmann's 
review)
   - Add set wake/reset on suspend/resume.
Changes since v1:
   - Remove patches 01 and 02 as Chen-Yu Tsai sent a similar patch:
   https://patchwork.kernel.org/patch/10111431/
   and it is merged on last next-20171222.
   (See commit f066f46ce5a5 "ARM: dts: sun8i: a83t: Add I2C device nodes and 
pinmux settings")
   - Update regulator according to Dmitry Torokhov's review: remove "optional"
   suffix while retrieving the regulator, rename it into "vcc" instead of
   "power" and add bindings documentation.
   - Update device tree according to Maxime Ripard's review: remove the
   label and rename the node.
   - Squash patch 03 with patch 05 to add I2C0 and touchscreen's node
   in one patch (see patch 02).

Patch 01: Add support for regulator in the FocalTech touchscreen driver
because A711 tablet is using a regulator to power-up the touchscreen.
Patch 02: Add a set wake/reset values on resume and suspend.
Patch 03: Add i2c0 and touchscreen's node for A711 TBS tablet.

Thank you in advance for any review.
Best regards,
Mylène

Mylène Josserand (3):
  Input: edt-ft5x06 - Add support for regulator
  Input: edt-ft5x06 - Set wake/reset values on resume/suspend
  arm: dts: sun8i: a83t: a711: Add touchscreen node

 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts  | 16 +
 drivers/input/touchscreen/edt-ft5x06.c | 41 ++
 3 files changed, 58 insertions(+)

-- 
2.11.0

[PATCH v3 1/3] Input: edt-ft5x06 - Add support for regulator

[Mylène Josserand]

Add the support of regulator to use it as VCC source.

Signed-off-by: Mylène Josserand 
---
 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 drivers/input/touchscreen/edt-ft5x06.c | 29 ++
 2 files changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 
b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..48e975b9c1aa 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -30,6 +30,7 @@ Required properties:
 Optional properties:
  - reset-gpios: GPIO specification for the RESET input
  - wake-gpios:  GPIO specification for the WAKE input
+ - vcc-supply:  Regulator that supplies the touchscreen
 
  - pinctrl-names: should be "default"
  - pinctrl-0:   a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c 
b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..aa94494b06b5 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define WORK_REGISTER_THRESHOLD0x00
 #define WORK_REGISTER_REPORT_RATE  0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+   struct regulator *vcc;
 
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -991,6 +993,22 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
 
tsdata->max_support_points = chip_data->max_support_points;
 
+   tsdata->vcc = devm_regulator_get(>dev, "vcc");
+   if (IS_ERR(tsdata->vcc)) {
+   error = PTR_ERR(tsdata->vcc);
+   if (error != -EPROBE_DEFER)
+   dev_err(>dev, "failed to request regulator: 
%d\n",
+   error);
+   return error;
+   }
+
+   error = regulator_enable(tsdata->vcc);
+   if (error < 0) {
+   dev_err(>dev, "failed to enable vcc: %d\n",
+   error);
+   return error;
+   }
+
tsdata->reset_gpio = devm_gpiod_get_optional(>dev,
 "reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,20 +1138,31 @@ static int edt_ft5x06_ts_remove(struct i2c_client 
*client)
 static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
 
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
 
+   regulator_disable(tsdata->vcc);
+
return 0;
 }
 
 static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
+   struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+   int ret;
 
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
 
+   ret = regulator_enable(tsdata->vcc);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vcc: %d\n", ret);
+   return ret;
+   }
+
return 0;
 }
 
-- 
2.11.0

[PATCH v3 0/3] sun8i-a83t: Add touchscreen support on TBS A711

[Mylène Josserand]

Hello everyone,

This is a V3 of the patch series that adds touchscreen support
(FocalTech EDT-FT5x06 Polytouch) for TBS A711 (Allwinner sun8i-a83t SoC).
Based on last master of linux-input tree.

Since I can't test the suspend/resume functions there is no updates in
this series about factory/normal mode.

Changes since v2:
   - Remove the check if regulator is NULL (Dmitry Torokhov's review)
   - Add EPROBE_DEFER error not to print a error message (Lothar Waßmann's 
review)
   - Add set wake/reset on suspend/resume.
Changes since v1:
   - Remove patches 01 and 02 as Chen-Yu Tsai sent a similar patch:
   https://patchwork.kernel.org/patch/10111431/
   and it is merged on last next-20171222.
   (See commit f066f46ce5a5 "ARM: dts: sun8i: a83t: Add I2C device nodes and 
pinmux settings")
   - Update regulator according to Dmitry Torokhov's review: remove "optional"
   suffix while retrieving the regulator, rename it into "vcc" instead of
   "power" and add bindings documentation.
   - Update device tree according to Maxime Ripard's review: remove the
   label and rename the node.
   - Squash patch 03 with patch 05 to add I2C0 and touchscreen's node
   in one patch (see patch 02).

Patch 01: Add support for regulator in the FocalTech touchscreen driver
because A711 tablet is using a regulator to power-up the touchscreen.
Patch 02: Add a set wake/reset values on resume and suspend.
Patch 03: Add i2c0 and touchscreen's node for A711 TBS tablet.

Thank you in advance for any review.
Best regards,
Mylène

Mylène Josserand (3):
  Input: edt-ft5x06 - Add support for regulator
  Input: edt-ft5x06 - Set wake/reset values on resume/suspend
  arm: dts: sun8i: a83t: a711: Add touchscreen node

 .../bindings/input/touchscreen/edt-ft5x06.txt  |  1 +
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts  | 16 +
 drivers/input/touchscreen/edt-ft5x06.c | 41 ++
 3 files changed, 58 insertions(+)

-- 
2.11.0

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Wed, 4 Jul 2018 16:21:58 +
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:
> > Hello,
> > 
> > Here is a V6 series to add the driver of the touchscreen Cypress,
> > TrueTouch Generation 5.
> > Based on v4.18-rc3.
> > 
> > This patch series has already been posted in several iterations:
> > - v1: Sent on 2017/05/29
> > - v2: Sent on 2017/08/18
> > - v3: Sent on 2017/09/27
> > - v4: Sent on 2017/12/01
> > - v5: Sent on 2017/12/20
> > 
> > I did not have any comments the last 4 versions.
> > And no reviews on my v5 during 6 months. Could I have any updates
> > or feedback on my series to know why it is not merged (to be able to
> > correct what is wrong)?  
> 
> Sorry, I must have missed the v5, sorry about that.

No problem.

> 
> I probably asked this question before, but just to make sure - I see
> references to HID in the patch - the device is really not HID
> compatible? Is there any hope it could be made work with i2c-hid +
> hid-multitouch?

I do not think it is HID compatible but let me check the i2c-hid and
hid-multitouch drivers to confirm that (or not).

I will let you know in next few days.

Thank you,
Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello Dmitry,

On Wed, 4 Jul 2018 16:21:58 +
Dmitry Torokhov  wrote:

> Hi Mylène,
> 
> On Tue, Jul 03, 2018 at 11:43:07AM +0200, Mylène Josserand wrote:
> > Hello,
> > 
> > Here is a V6 series to add the driver of the touchscreen Cypress,
> > TrueTouch Generation 5.
> > Based on v4.18-rc3.
> > 
> > This patch series has already been posted in several iterations:
> > - v1: Sent on 2017/05/29
> > - v2: Sent on 2017/08/18
> > - v3: Sent on 2017/09/27
> > - v4: Sent on 2017/12/01
> > - v5: Sent on 2017/12/20
> > 
> > I did not have any comments the last 4 versions.
> > And no reviews on my v5 during 6 months. Could I have any updates
> > or feedback on my series to know why it is not merged (to be able to
> > correct what is wrong)?  
> 
> Sorry, I must have missed the v5, sorry about that.

No problem.

> 
> I probably asked this question before, but just to make sure - I see
> references to HID in the patch - the device is really not HID
> compatible? Is there any hope it could be made work with i2c-hid +
> hid-multitouch?

I do not think it is HID compatible but let me check the i2c-hid and
hid-multitouch drivers to confirm that (or not).

I will let you know in next few days.

Thank you,
Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH v6 1/2] Input: Add driver for Cypress Generation 5 touchscreen

[Mylène Josserand]

This is the basic driver for the Cypress TrueTouch Gen5 touchscreen
controllers. This driver supports only the I2C bus but it uses regmap
so SPI support could be added later.
The touchscreen can retrieve some defined zone that are handled as
buttons (according to the hardware). That is why it handles
button and multitouch events.

Reviewed-by: Maxime Ripard 
Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/Kconfig   |   16 +
 drivers/input/touchscreen/Makefile  |1 +
 drivers/input/touchscreen/cyttsp5.c | 1110 +++
 3 files changed, 1127 insertions(+)
 create mode 100644 drivers/input/touchscreen/cyttsp5.c

diff --git a/drivers/input/touchscreen/Kconfig 
b/drivers/input/touchscreen/Kconfig
index 32267c1afebc..e1dd127c3b96 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -249,6 +249,22 @@ config TOUCHSCREEN_CYTTSP4_SPI
  To compile this driver as a module, choose M here: the
  module will be called cyttsp4_spi.
 
+config TOUCHSCREEN_CYTTSP5
+   tristate "Cypress TrueTouch Gen5 Touchscreen Driver"
+   depends on OF
+   select REGMAP_I2C
+   select CRC_ITU_T
+   help
+ Driver for Parade TrueTouch Standard Product
+ Generation 5 touchscreen controllers.
+ I2C bus interface support only.
+
+ Say Y here if you have a Cypress Gen5 touchscreen.
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cyttsp5.
+
 config TOUCHSCREEN_DA9034
tristate "Touchscreen support for Dialog Semiconductor DA9034"
depends on PMIC_DA903X
diff --git a/drivers/input/touchscreen/Makefile 
b/drivers/input/touchscreen/Makefile
index fd4fd32fb73f..52e8b9ff35bb 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_SPI)  += cyttsp_spi.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_CORE) += cyttsp4_core.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_I2C)  += cyttsp4_i2c.o cyttsp_i2c_common.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_SPI)  += cyttsp4_spi.o
+obj-$(CONFIG_TOUCHSCREEN_CYTTSP5)  += cyttsp5.o
 obj-$(CONFIG_TOUCHSCREEN_DA9034)   += da9034-ts.o
 obj-$(CONFIG_TOUCHSCREEN_DA9052)   += da9052_tsi.o
 obj-$(CONFIG_TOUCHSCREEN_DYNAPRO)  += dynapro.o
diff --git a/drivers/input/touchscreen/cyttsp5.c 
b/drivers/input/touchscreen/cyttsp5.c
new file mode 100644
index ..dc8c0ce22c9f
--- /dev/null
+++ b/drivers/input/touchscreen/cyttsp5.c
@@ -0,0 +1,1110 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Parade TrueTouch(TM) Standard Product V5 Module.
+ *
+ * Copyright (C) 2015 Parade Technologies
+ * Copyright (C) 2012-2015 Cypress Semiconductor
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author: Mylène Josserand 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CYTTSP5_NAME   "cyttsp5"
+#define CY_I2C_DATA_SIZE   (2 * 256)
+#define HID_VERSION0x0100
+#define CY_MAX_INPUT   512
+#define CYTTSP5_PREALLOCATED_CMD_BUFFER32
+#define CY_BITS_PER_BTN1
+#define CY_NUM_BTN_EVENT_ID((1 << CY_BITS_PER_BTN) - 1)
+
+#define MAX_AREA   255
+#define HID_OUTPUT_BL_SOP  0x1
+#define HID_OUTPUT_BL_EOP  0x17
+#define HID_OUTPUT_BL_LAUNCH_APP   0x3B
+#define HID_OUTPUT_BL_LAUNCH_APP_SIZE  11
+#define HID_OUTPUT_GET_SYSINFO 0x2
+#define HID_OUTPUT_GET_SYSINFO_SIZE5
+
+#define HID_DESC_REG   0x1
+#define HID_INPUT_REG  0x3
+#define HID_OUTPUT_REG 0x4
+
+#define REPORT_ID_TOUCH0x1
+#define REPORT_ID_BTN  0x3
+#define REPORT_SIZE_5  5
+#define REPORT_SIZE_8  8
+#define REPORT_SIZE_16 16
+
+/* Touch reports offsets */
+/* Header offsets */
+#define TOUCH_REPORT_DESC_HDR_CONTACTCOUNT 16
+/* Record offsets */
+#define TOUCH_REPORT_DESC_CONTACTID8
+#define TOUCH_REPORT_DESC_X16
+#define TOUCH_REPORT_DESC_Y32
+#define TOUCH_REPORT_DESC_P48
+#define TOUCH_REPORT_DESC_MAJ  56
+#define TOUCH_REPORT_DESC_MIN  64
+
+/* HID */
+#define HID_TOUCH_REPORT_ID0x1
+#define HID_BTN_REPORT_ID  0x3
+#define HID_APP_RESPONSE_REPORT_ID 0x1F
+#define HID_APP_OUTPUT_REPORT_ID   0x2F
+#define HID_BL_RESPONSE_REPORT_ID  0x30
+#define HID_BL_OUTPUT_REPORT_ID0x40
+
+#define HID_OUTPUT_RE

[PATCH v6 2/2] dt-bindings: input: Add documentation for cyttsp5

[Mylène Josserand]

Add the Cypress TrueTouch Generation 5 touchscreen device tree bindings
documentation. It can use I2C or SPI bus.
This touchscreen can handle some defined zone that are designed and
sent as button. To be able to customize the keycode sent, the
"linux,keycodes" property can be used.

Acked-by: Rob Herring 
Signed-off-by: Mylène Josserand 
---
 .../bindings/input/touchscreen/cypress,cyttsp5.txt | 39 ++
 1 file changed, 39 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt

diff --git 
a/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt 
b/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
new file mode 100644
index ..1e0e90e322c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
@@ -0,0 +1,39 @@
+* Cypress cyttsp touchscreen controller, generation 5
+
+Required properties:
+ - compatible  : must be "cypress,cyttsp5"
+ - reg : Device I2C address or SPI chip select number
+ - interrupt-parent: the phandle for the gpio controller
+ (see interrupt binding[0]).
+ - interrupts  : (gpio) interrupt to which the chip is connected
+ (see interrupt binding[0]).
+
+Optional properties:
+ - reset-gpios : the reset gpio the chip is connected to
+ (see GPIO binding[1] for more details).
+Some other touchscreen optional properties can be defined such as
+"touchscreen-size-x". See ./touchscreen.txt[2] for more details.
+
+This touchscreen can handle some buttons that are touchscreen's defined zones.
+Each button's event can be customized using a property:
+   - linux,keycodes: List of keycode to emit.
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[1]: Documentation/devicetree/bindings/gpio/gpio.txt
+[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
+
+Example:
+ {
+   [...]
+
+   touchscreen@24 {
+   compatible = "cypress,cyttsp5";
+   reg = <0x24>;
+
+   interrupt-parent = <>;
+   interrupts = <1 5 IRQ_TYPE_LEVEL_LOW>;
+   reset-gpios = < 7 1 GPIO_ACTIVE_HIGH>;
+   touchscreen-swapped-x-y;
+   linux,keycodes = , , ;
+   };
+};
-- 
2.11.0

[PATCH v6 1/2] Input: Add driver for Cypress Generation 5 touchscreen

[Mylène Josserand]

This is the basic driver for the Cypress TrueTouch Gen5 touchscreen
controllers. This driver supports only the I2C bus but it uses regmap
so SPI support could be added later.
The touchscreen can retrieve some defined zone that are handled as
buttons (according to the hardware). That is why it handles
button and multitouch events.

Reviewed-by: Maxime Ripard 
Signed-off-by: Mylène Josserand 
---
 drivers/input/touchscreen/Kconfig   |   16 +
 drivers/input/touchscreen/Makefile  |1 +
 drivers/input/touchscreen/cyttsp5.c | 1110 +++
 3 files changed, 1127 insertions(+)
 create mode 100644 drivers/input/touchscreen/cyttsp5.c

diff --git a/drivers/input/touchscreen/Kconfig 
b/drivers/input/touchscreen/Kconfig
index 32267c1afebc..e1dd127c3b96 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -249,6 +249,22 @@ config TOUCHSCREEN_CYTTSP4_SPI
  To compile this driver as a module, choose M here: the
  module will be called cyttsp4_spi.
 
+config TOUCHSCREEN_CYTTSP5
+   tristate "Cypress TrueTouch Gen5 Touchscreen Driver"
+   depends on OF
+   select REGMAP_I2C
+   select CRC_ITU_T
+   help
+ Driver for Parade TrueTouch Standard Product
+ Generation 5 touchscreen controllers.
+ I2C bus interface support only.
+
+ Say Y here if you have a Cypress Gen5 touchscreen.
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cyttsp5.
+
 config TOUCHSCREEN_DA9034
tristate "Touchscreen support for Dialog Semiconductor DA9034"
depends on PMIC_DA903X
diff --git a/drivers/input/touchscreen/Makefile 
b/drivers/input/touchscreen/Makefile
index fd4fd32fb73f..52e8b9ff35bb 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_SPI)  += cyttsp_spi.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_CORE) += cyttsp4_core.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_I2C)  += cyttsp4_i2c.o cyttsp_i2c_common.o
 obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_SPI)  += cyttsp4_spi.o
+obj-$(CONFIG_TOUCHSCREEN_CYTTSP5)  += cyttsp5.o
 obj-$(CONFIG_TOUCHSCREEN_DA9034)   += da9034-ts.o
 obj-$(CONFIG_TOUCHSCREEN_DA9052)   += da9052_tsi.o
 obj-$(CONFIG_TOUCHSCREEN_DYNAPRO)  += dynapro.o
diff --git a/drivers/input/touchscreen/cyttsp5.c 
b/drivers/input/touchscreen/cyttsp5.c
new file mode 100644
index ..dc8c0ce22c9f
--- /dev/null
+++ b/drivers/input/touchscreen/cyttsp5.c
@@ -0,0 +1,1110 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Parade TrueTouch(TM) Standard Product V5 Module.
+ *
+ * Copyright (C) 2015 Parade Technologies
+ * Copyright (C) 2012-2015 Cypress Semiconductor
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author: Mylène Josserand 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CYTTSP5_NAME   "cyttsp5"
+#define CY_I2C_DATA_SIZE   (2 * 256)
+#define HID_VERSION0x0100
+#define CY_MAX_INPUT   512
+#define CYTTSP5_PREALLOCATED_CMD_BUFFER32
+#define CY_BITS_PER_BTN1
+#define CY_NUM_BTN_EVENT_ID((1 << CY_BITS_PER_BTN) - 1)
+
+#define MAX_AREA   255
+#define HID_OUTPUT_BL_SOP  0x1
+#define HID_OUTPUT_BL_EOP  0x17
+#define HID_OUTPUT_BL_LAUNCH_APP   0x3B
+#define HID_OUTPUT_BL_LAUNCH_APP_SIZE  11
+#define HID_OUTPUT_GET_SYSINFO 0x2
+#define HID_OUTPUT_GET_SYSINFO_SIZE5
+
+#define HID_DESC_REG   0x1
+#define HID_INPUT_REG  0x3
+#define HID_OUTPUT_REG 0x4
+
+#define REPORT_ID_TOUCH0x1
+#define REPORT_ID_BTN  0x3
+#define REPORT_SIZE_5  5
+#define REPORT_SIZE_8  8
+#define REPORT_SIZE_16 16
+
+/* Touch reports offsets */
+/* Header offsets */
+#define TOUCH_REPORT_DESC_HDR_CONTACTCOUNT 16
+/* Record offsets */
+#define TOUCH_REPORT_DESC_CONTACTID8
+#define TOUCH_REPORT_DESC_X16
+#define TOUCH_REPORT_DESC_Y32
+#define TOUCH_REPORT_DESC_P48
+#define TOUCH_REPORT_DESC_MAJ  56
+#define TOUCH_REPORT_DESC_MIN  64
+
+/* HID */
+#define HID_TOUCH_REPORT_ID0x1
+#define HID_BTN_REPORT_ID  0x3
+#define HID_APP_RESPONSE_REPORT_ID 0x1F
+#define HID_APP_OUTPUT_REPORT_ID   0x2F
+#define HID_BL_RESPONSE_REPORT_ID  0x30
+#define HID_BL_OUTPUT_REPORT_ID0x40
+
+#define HID_OUTPUT_RE

[PATCH v6 2/2] dt-bindings: input: Add documentation for cyttsp5

[Mylène Josserand]

Add the Cypress TrueTouch Generation 5 touchscreen device tree bindings
documentation. It can use I2C or SPI bus.
This touchscreen can handle some defined zone that are designed and
sent as button. To be able to customize the keycode sent, the
"linux,keycodes" property can be used.

Acked-by: Rob Herring 
Signed-off-by: Mylène Josserand 
---
 .../bindings/input/touchscreen/cypress,cyttsp5.txt | 39 ++
 1 file changed, 39 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt

diff --git 
a/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt 
b/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
new file mode 100644
index ..1e0e90e322c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
@@ -0,0 +1,39 @@
+* Cypress cyttsp touchscreen controller, generation 5
+
+Required properties:
+ - compatible  : must be "cypress,cyttsp5"
+ - reg : Device I2C address or SPI chip select number
+ - interrupt-parent: the phandle for the gpio controller
+ (see interrupt binding[0]).
+ - interrupts  : (gpio) interrupt to which the chip is connected
+ (see interrupt binding[0]).
+
+Optional properties:
+ - reset-gpios : the reset gpio the chip is connected to
+ (see GPIO binding[1] for more details).
+Some other touchscreen optional properties can be defined such as
+"touchscreen-size-x". See ./touchscreen.txt[2] for more details.
+
+This touchscreen can handle some buttons that are touchscreen's defined zones.
+Each button's event can be customized using a property:
+   - linux,keycodes: List of keycode to emit.
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[1]: Documentation/devicetree/bindings/gpio/gpio.txt
+[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
+
+Example:
+ {
+   [...]
+
+   touchscreen@24 {
+   compatible = "cypress,cyttsp5";
+   reg = <0x24>;
+
+   interrupt-parent = <>;
+   interrupts = <1 5 IRQ_TYPE_LEVEL_LOW>;
+   reset-gpios = < 7 1 GPIO_ACTIVE_HIGH>;
+   touchscreen-swapped-x-y;
+   linux,keycodes = , , ;
+   };
+};
-- 
2.11.0

[PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello,

Here is a V6 series to add the driver of the touchscreen Cypress,
TrueTouch Generation 5.
Based on v4.18-rc3.

This patch series has already been posted in several iterations:
- v1: Sent on 2017/05/29
- v2: Sent on 2017/08/18
- v3: Sent on 2017/09/27
- v4: Sent on 2017/12/01
- v5: Sent on 2017/12/20

I did not have any comments the last 4 versions.
And no reviews on my v5 during 6 months. Could I have any updates
or feedback on my series to know why it is not merged (to be able to
correct what is wrong)?

Changes since v5:
   - Rebased on v4.17-rc3
   - Use SPDX header
   - Called "touchscreen_report_pos" function to perform some
   DT properties on position (such as X/Y swapping)
   - Called "__set_bit" for ABS_X, ABS_Y and BTN_TOUCH to be able
   to use "ts_lib" otherwise, it returns an error:
  tslib: Selected device is not a touchscreen (must support
 ABS and KEY event types)
Changes since v4:
   - Fixed kbuild errors about enum hid_cmd_state and .owner
Changes since v3:
   - Rebased on last input's branch
   - Changed the CRC table to use crc_itu_t_table instead of
   crc_ccitt_false_table which is not merged.
   - Added selection of CRC_ITU_T on KConfig
Changes since v2:
   - Removed pinctrl in dt-binding example which is uncessecary.
   - Added Acked-by and Reviewed-by received.
Changes since v1:
   - Updated the driver according to reviews. Most important modifications:
   removed unnecessary mutex, updated dev_err output, handled return cases
   in a better way, created a HID_ENUM, removed magic value, used an
   existing CRC table and used "linux-keycodes" instead of sub-nodes.
   - Updated the dt-bindings to use linux-keycodes and removed properties'
   description that comes from touchscreen's binding.

Patch 01: Add the basis of the driver for Cypress Gen5 Touchscreen.
Patch 02: Add the binding documentation for this driver.

Thank you,

Best regards,
Mylène

Mylène Josserand (2):
  Input: Add driver for Cypress Generation 5 touchscreen
  dt-bindings: input: Add documentation for cyttsp5

 .../bindings/input/touchscreen/cypress,cyttsp5.txt |   39 +
 drivers/input/touchscreen/Kconfig  |   16 +
 drivers/input/touchscreen/Makefile |1 +
 drivers/input/touchscreen/cyttsp5.c| 1110 
 4 files changed, 1166 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
 create mode 100644 drivers/input/touchscreen/cyttsp5.c

-- 
2.11.0

[PATCH v6 0/2] Input: Add Cypress Gen5 Touchscreen driver

[Mylène Josserand]

Hello,

Here is a V6 series to add the driver of the touchscreen Cypress,
TrueTouch Generation 5.
Based on v4.18-rc3.

This patch series has already been posted in several iterations:
- v1: Sent on 2017/05/29
- v2: Sent on 2017/08/18
- v3: Sent on 2017/09/27
- v4: Sent on 2017/12/01
- v5: Sent on 2017/12/20

I did not have any comments the last 4 versions.
And no reviews on my v5 during 6 months. Could I have any updates
or feedback on my series to know why it is not merged (to be able to
correct what is wrong)?

Changes since v5:
   - Rebased on v4.17-rc3
   - Use SPDX header
   - Called "touchscreen_report_pos" function to perform some
   DT properties on position (such as X/Y swapping)
   - Called "__set_bit" for ABS_X, ABS_Y and BTN_TOUCH to be able
   to use "ts_lib" otherwise, it returns an error:
  tslib: Selected device is not a touchscreen (must support
 ABS and KEY event types)
Changes since v4:
   - Fixed kbuild errors about enum hid_cmd_state and .owner
Changes since v3:
   - Rebased on last input's branch
   - Changed the CRC table to use crc_itu_t_table instead of
   crc_ccitt_false_table which is not merged.
   - Added selection of CRC_ITU_T on KConfig
Changes since v2:
   - Removed pinctrl in dt-binding example which is uncessecary.
   - Added Acked-by and Reviewed-by received.
Changes since v1:
   - Updated the driver according to reviews. Most important modifications:
   removed unnecessary mutex, updated dev_err output, handled return cases
   in a better way, created a HID_ENUM, removed magic value, used an
   existing CRC table and used "linux-keycodes" instead of sub-nodes.
   - Updated the dt-bindings to use linux-keycodes and removed properties'
   description that comes from touchscreen's binding.

Patch 01: Add the basis of the driver for Cypress Gen5 Touchscreen.
Patch 02: Add the binding documentation for this driver.

Thank you,

Best regards,
Mylène

Mylène Josserand (2):
  Input: Add driver for Cypress Generation 5 touchscreen
  dt-bindings: input: Add documentation for cyttsp5

 .../bindings/input/touchscreen/cypress,cyttsp5.txt |   39 +
 drivers/input/touchscreen/Kconfig  |   16 +
 drivers/input/touchscreen/Makefile |1 +
 drivers/input/touchscreen/cyttsp5.c| 1110 
 4 files changed, 1166 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/input/touchscreen/cypress,cyttsp5.txt
 create mode 100644 drivers/input/touchscreen/cyttsp5.c

-- 
2.11.0

[PATCH v9 01/12] ARM: Allow this header to be included by assembly files

[Mylène Josserand]

From: Doug Berger <open...@gmail.com>

The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
don't need to be defined in multiple places.

Signed-off-by: Doug Berger <open...@gmail.com>
Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/include/asm/cputype.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb546425da8a..e7632f536633 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
-#include 
-#include 
-
 #define CPUID_ID   0
 #define CPUID_CACHETYPE1
 #define CPUID_TCM  2
@@ -98,6 +95,11 @@
 /* Qualcomm implemented cores */
 #define ARM_CPU_PART_SCORPION  0x510002d0
 
+#ifndef __ASSEMBLY__
+
+#include 
+#include 
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -326,4 +328,6 @@ static inline int __attribute_const__ 
cpuid_feature_extract_field(u32 features,
 #define cpuid_feature_extract(reg, field) \
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
2.11.0

[PATCH v9 01/12] ARM: Allow this header to be included by assembly files

[Mylène Josserand]

From: Doug Berger 

The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
don't need to be defined in multiple places.

Signed-off-by: Doug Berger 
Signed-off-by: Florian Fainelli 
Signed-off-by: Mylène Josserand 
---
 arch/arm/include/asm/cputype.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb546425da8a..e7632f536633 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
-#include 
-#include 
-
 #define CPUID_ID   0
 #define CPUID_CACHETYPE1
 #define CPUID_TCM  2
@@ -98,6 +95,11 @@
 /* Qualcomm implemented cores */
 #define ARM_CPU_PART_SCORPION  0x510002d0
 
+#ifndef __ASSEMBLY__
+
+#include 
+#include 
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -326,4 +328,6 @@ static inline int __attribute_const__ 
cpuid_feature_extract_field(u32 features,
 #define cpuid_feature_extract(reg, field) \
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
2.11.0

[PATCH v9 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v9 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v9 02/12] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ * Mylène Josserand <mylene.josser...@bootlin.com>
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-  

[PATCH v9 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v9 02/12] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai 
+ * Mylène Josserand 
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xf

[PATCH v9 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v9 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v9 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v9 07/12] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
bl  sunxi_mc_smp_cluster_cache_enable
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..752e0748b0c8 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
-   "allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat  = sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_a83t_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+   secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+   "allwinner,sun8i-a83t",
+   NULL,
+};
+
+DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+   .init_early = sun8i_a83t_cntvoff_init,
+   .init_time  = sun6i_timer_init,
+   .dt_compat  = sun8i_a83t_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
-- 
2.11.0

[PATCH v9 07/12] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
bl  sunxi_mc_smp_cluster_cache_enable
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..752e0748b0c8 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
-   "allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat  = sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_a83t_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+   secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+   "allwinner,sun8i-a83t",
+   NULL,
+};
+
+DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+   .init_early = sun8i_a83t_cntvoff_init,
+   .init_time  = sun6i_timer_init,
+   .dt_compat  = sun8i_a83t_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
-- 
2.11.0

[PATCH v9 06/12] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v9 06/12] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v9 09/12] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v9 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v9 09/12] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v9 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v9 10/12] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if

[PATCH v9 10/12] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;

[PATCH v9 08/12] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v9 08/12] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v9 12/12] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
Acked-by: Simon Horman <horms+rene...@verge.net.au>
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v9 12/12] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Simon Horman 
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v9 00/12] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V9 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

The difference with the v8 is just that the machine is renamed in sun8i-a83t
(see patch 07), according to Maxime's review.

Thank you in advance,
Best regards,
Mylène

Changes from v8:
- Rename machine into "sun8i-a83t"

Changes from v7:
- Add the patch of Doug Berger in my series.
- Rename the machine name to start secure_cntvoff into "sun8i-a83t",
according to Maxime's review.
- Change the type of is_a83t field from integer into boolean.

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
    patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts:

[PATCH v9 00/12] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V9 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

The difference with the v8 is just that the machine is renamed in sun8i-a83t
(see patch 07), according to Maxime's review.

Thank you in advance,
Best regards,
Mylène

Changes from v8:
- Rename machine into "sun8i-a83t"

Changes from v7:
- Add the patch of Doug Berger in my series.
- Rename the machine name to start secure_cntvoff into "sun8i-a83t",
according to Maxime's review.
- Change the type of is_a83t field from integer into boolean.

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
    patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts:

Re: [PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Hi Maxime,

On Wed, 2 May 2018 15:08:42 +0200
Maxime Ripard <maxime.rip...@bootlin.com> wrote:

> On Tue, May 01, 2018 at 02:31:26PM +0200, Mylène Josserand wrote:
> > Add the initialization of CNTVOFF for sun8i-a83t.
> > 
> > For boot CPU, create a new machine that handles this
> > function's call in an "init_early" callback. We need to initialize
> > CNTVOFF before the arch timer's initialization otherwise, it will
> > not be taken into account and fails to boot correctly.
> > Because of that, this function can't be called in SMP's early_initcall
> > function which is called after timer's init.
> > 
> > For secondary CPUs, add this function into secondary_startup
> > assembly entry.
> > 
> > Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
> > Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
> > ---
> >  arch/arm/mach-sunxi/headsmp.S |  1 +
> >  arch/arm/mach-sunxi/sunxi.c   | 20 +++-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> > index 37dc772701f3..32d76be98541 100644
> > --- a/arch/arm/mach-sunxi/headsmp.S
> > +++ b/arch/arm/mach-sunxi/headsmp.S
> > @@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> >  
> >  ENTRY(sunxi_mc_smp_secondary_startup)
> > bl  sunxi_mc_smp_cluster_cache_enable
> > +   bl  secure_cntvoff_init
> > b   secondary_startup
> >  ENDPROC(sunxi_mc_smp_secondary_startup)
> >  
> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > index 5e9602ce1573..2770a31a9278 100644
> > --- a/arch/arm/mach-sunxi/sunxi.c
> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > @@ -16,6 +16,7 @@
> >  #include 
> >  
> >  #include 
> > +#include 
> >  
> >  static const char * const sunxi_board_dt_compat[] = {
> > "allwinner,sun4i-a10",
> > @@ -62,7 +63,6 @@ MACHINE_END
> >  static const char * const sun8i_board_dt_compat[] = {
> > "allwinner,sun8i-a23",
> > "allwinner,sun8i-a33",
> > -   "allwinner,sun8i-a83t",
> > "allwinner,sun8i-h2-plus",
> > "allwinner,sun8i-h3",
> > "allwinner,sun8i-r40",
> > @@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> > .dt_compat  = sun8i_board_dt_compat,
> >  MACHINE_END
> >  
> > +void __init sun8i_a83t_cntvoff_init(void)
> > +{
> > +#ifdef CONFIG_SMP
> > +   secure_cntvoff_init();
> > +#endif
> > +}
> > +
> > +static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
> > +   "allwinner,sun8i-a83t",
> > +   NULL,
> > +};
> > +
> > +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")  
> 
> I put my Acked-by on the condition that you would fix this. And you
> still didn't.

Grrr, stupid me.
I modified the names of functions but I forgot the machine. Sorry
about that.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

Re: [PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Hi Maxime,

On Wed, 2 May 2018 15:08:42 +0200
Maxime Ripard  wrote:

> On Tue, May 01, 2018 at 02:31:26PM +0200, Mylène Josserand wrote:
> > Add the initialization of CNTVOFF for sun8i-a83t.
> > 
> > For boot CPU, create a new machine that handles this
> > function's call in an "init_early" callback. We need to initialize
> > CNTVOFF before the arch timer's initialization otherwise, it will
> > not be taken into account and fails to boot correctly.
> > Because of that, this function can't be called in SMP's early_initcall
> > function which is called after timer's init.
> > 
> > For secondary CPUs, add this function into secondary_startup
> > assembly entry.
> > 
> > Signed-off-by: Mylène Josserand 
> > Acked-by: Maxime Ripard 
> > ---
> >  arch/arm/mach-sunxi/headsmp.S |  1 +
> >  arch/arm/mach-sunxi/sunxi.c   | 20 +++-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> > index 37dc772701f3..32d76be98541 100644
> > --- a/arch/arm/mach-sunxi/headsmp.S
> > +++ b/arch/arm/mach-sunxi/headsmp.S
> > @@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> >  
> >  ENTRY(sunxi_mc_smp_secondary_startup)
> > bl  sunxi_mc_smp_cluster_cache_enable
> > +   bl  secure_cntvoff_init
> > b   secondary_startup
> >  ENDPROC(sunxi_mc_smp_secondary_startup)
> >  
> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > index 5e9602ce1573..2770a31a9278 100644
> > --- a/arch/arm/mach-sunxi/sunxi.c
> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > @@ -16,6 +16,7 @@
> >  #include 
> >  
> >  #include 
> > +#include 
> >  
> >  static const char * const sunxi_board_dt_compat[] = {
> > "allwinner,sun4i-a10",
> > @@ -62,7 +63,6 @@ MACHINE_END
> >  static const char * const sun8i_board_dt_compat[] = {
> > "allwinner,sun8i-a23",
> > "allwinner,sun8i-a33",
> > -   "allwinner,sun8i-a83t",
> > "allwinner,sun8i-h2-plus",
> > "allwinner,sun8i-h3",
> > "allwinner,sun8i-r40",
> > @@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> > .dt_compat  = sun8i_board_dt_compat,
> >  MACHINE_END
> >  
> > +void __init sun8i_a83t_cntvoff_init(void)
> > +{
> > +#ifdef CONFIG_SMP
> > +   secure_cntvoff_init();
> > +#endif
> > +}
> > +
> > +static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
> > +   "allwinner,sun8i-a83t",
> > +   NULL,
> > +};
> > +
> > +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")  
> 
> I put my Acked-by on the condition that you would fix this. And you
> still didn't.

Grrr, stupid me.
I modified the names of functions but I forgot the machine. Sorry
about that.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ * Mylène Josserand <mylene.josser...@bootlin.com>
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   

[PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai 
+ * Mylène Josserand 
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0x) 
"\

[PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
   

[PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;
 
+   /* For A83T,

[PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v8 00/12] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v7:
- Add the patch of Doug Berger in my series.
- Rename the machine name to start secure_cntvoff into "sun8i-a83t",
according to Maxime's review.
- Change the type of is_a83t field from integer into boolean.

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-

[PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v8 00/12] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v7:
- Add the patch of Doug Berger in my series.
- Rename the machine name to start secure_cntvoff into "sun8i-a83t",
according to Maxime's review.
- Change the type of is_a83t field from integer into boolean.

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-

[PATCH v8 01/12] ARM: Allow this header to be included by assembly files

[Mylène Josserand]

From: Doug Berger <open...@gmail.com>

The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
don't need to be defined in multiple places.

Signed-off-by: Doug Berger <open...@gmail.com>
Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
---
 arch/arm/include/asm/cputype.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb546425da8a..e7632f536633 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
-#include 
-#include 
-
 #define CPUID_ID   0
 #define CPUID_CACHETYPE1
 #define CPUID_TCM  2
@@ -98,6 +95,11 @@
 /* Qualcomm implemented cores */
 #define ARM_CPU_PART_SCORPION  0x510002d0
 
+#ifndef __ASSEMBLY__
+
+#include 
+#include 
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -326,4 +328,6 @@ static inline int __attribute_const__ 
cpuid_feature_extract_field(u32 features,
 #define cpuid_feature_extract(reg, field) \
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
2.11.0