Re: [PATCH v8 0/5] soc: qcom: add in-kernel pd-mapper implementation
On 11/05/2024 23:56, Dmitry Baryshkov wrote: Protection domain mapper is a QMI service providing mapping between 'protection domains' and services supported / allowed in these domains. For example such mapping is required for loading of the WiFi firmware or for properly starting up the UCSI / altmode / battery manager support. The existing userspace implementation has several issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't reread the JSON files if the firmware location is changed (or if the firmware was not available at the time pd-mapper was started but the corresponding directory is mounted later), etc. However this configuration is largely static and common between different platforms. Provide in-kernel service implementing static per-platform data. To: Bjorn Andersson To: Konrad Dybcio To: Sibi Sankar To: Mathieu Poirier Cc: linux-arm-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-remotep...@vger.kernel.org Cc: Johan Hovold Cc: Xilin Wu Cc: "Bryan O'Donoghue" Cc: Steev Klimaszewski Cc: Alexey Minnekhanov -- Changes in v8: - Reworked pd-mapper to register as an rproc_subdev / auxdev - Dropped Tested-by from Steev and Alexey from the last patch since the implementation was changed significantly. - Add sensors, cdsp and mpss_root domains to 660 config (Alexey Minnekhanov) - Added platform entry for sm4250 (used for qrb4210 / RB2) - Added locking to the pdr_get_domain_list() (Chris Lew) - Remove the call to qmi_del_server() and corresponding API (Chris Lew) - In qmi_handle_init() changed 1024 to a defined constant (Chris Lew) - Link to v7: https://lore.kernel.org/r/20240424-qcom-pd-mapper-v7-0-05f7fc646...@linaro.org Changes in v7: - Fixed modular build (Steev) - Link to v6: https://lore.kernel.org/r/20240422-qcom-pd-mapper-v6-0-f96957d01...@linaro.org Changes in v6: - Reworked mutex to fix lockdep issue on deregistration - Fixed dependencies between PD-mapper and remoteproc to fix modular builds (Krzysztof) - Added EXPORT_SYMBOL_GPL to fix modular builds (Krzysztof) - Fixed kerneldocs (Krzysztof) - Removed extra pr_debug messages (Krzysztof) - Fixed wcss build (Krzysztof) - Added platforms which do not require protection domain mapping to silence the notice on those platforms - Link to v5: https://lore.kernel.org/r/20240419-qcom-pd-mapper-v5-0-e35b6f847...@linaro.org Changes in v5: - pdr: drop lock in pdr_register_listener, list_lock is already held (Chris Lew) - pd_mapper: reworked to provide static configuration per platform (Bjorn) - Link to v4: https://lore.kernel.org/r/20240311-qcom-pd-mapper-v4-0-24679cca5...@linaro.org Changes in v4: - Fixed missing chunk, reenabled kfree in qmi_del_server (Konrad) - Added configuration for sm6350 (Thanks to Luca) - Removed RFC tag (Konrad) - Link to v3: https://lore.kernel.org/r/20240304-qcom-pd-mapper-v3-0-6858fa1ac...@linaro.org Changes in RFC v3: - Send start / stop notifications when PD-mapper domain list is changed - Reworked the way PD-mapper treats protection domains, register all of them in a single batch - Added SC7180 domains configuration based on TCL Book 14 GO - Link to v2: https://lore.kernel.org/r/20240301-qcom-pd-mapper-v2-0-5d12a081d...@linaro.org Changes in RFC v2: - Swapped num_domains / domains (Konrad) - Fixed an issue with battery not working on sc8280xp - Added missing configuration for QCS404 --- Dmitry Baryshkov (5): soc: qcom: pdr: protect locator_addr with the main mutex soc: qcom: pdr: fix parsing of domains lists soc: qcom: pdr: extract PDR message marshalling data soc: qcom: add pd-mapper implementation remoteproc: qcom: enable in-kernel PD mapper drivers/remoteproc/qcom_common.c| 87 + drivers/remoteproc/qcom_common.h| 10 + drivers/remoteproc/qcom_q6v5_adsp.c | 3 + drivers/remoteproc/qcom_q6v5_mss.c | 3 + drivers/remoteproc/qcom_q6v5_pas.c | 3 + drivers/remoteproc/qcom_q6v5_wcss.c | 3 + drivers/soc/qcom/Kconfig| 15 + drivers/soc/qcom/Makefile | 2 + drivers/soc/qcom/pdr_interface.c| 17 +- drivers/soc/qcom/pdr_internal.h | 318 ++--- drivers/soc/qcom/qcom_pd_mapper.c | 676 drivers/soc/qcom/qcom_pdr_msg.c | 353 +++ 12 files changed, 1190 insertions(+), 300 deletions(-) --- base-commit: e5119bbdaca76cd3c15c3c975d51d840bbfb2488 change-id: 20240301-qcom-pd-mapper-e12d622d4ad0 Best regards, Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-QRD Thanks, Neil
Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
On 22/05/2024 15:04, Bartosz Golaszewski wrote: On Wed, May 22, 2024 at 2:42 PM wrote: On 22/05/2024 14:08, Bartosz Golaszewski wrote: From: Tengfei Fan Document the compatibles for the components used to boot the ADSP, CDSP0, CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC. Signed-off-by: Tengfei Fan Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 73fda7565cd1..9d3a862c39e1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -16,6 +16,11 @@ description: properties: compatible: enum: + - qcom,sa8775p-adsp-pas + - qcom,sa8775p-cdsp0-pas + - qcom,sa8775p-cdsp1-pas + - qcom,sa8775p-gpdsp0-pas + - qcom,sa8775p-gpdsp1-pas - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas @@ -44,12 +49,13 @@ properties: firmware-name: $ref: /schemas/types.yaml#/definitions/string-array +minItems: 1 This will allow a single firmware name for all compatible, which is wrong So increasing the limit from the default under allOf doesn't seem to work, should I instead keep this and make the lower limit stricter for all other models? Yes add minItems in all the allOf:if: and add the missing allOf:if: for the new compatibles to set the minItems, same for memory-region. Or you may simply spin off a new yaml, this one is getting quite large. Neil Bart items: - description: Firmware name of the Hexagon core - description: Firmware name of the Hexagon Devicetree memory-region: -minItems: 2 +minItems: 1 Same here items: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication @@ -81,6 +87,21 @@ allOf: maxItems: 5 memory-region: maxItems: 2 + - if: + properties: +compatible: + enum: +- qcom,sa8775p-adsp-pas +- qcom,sa8775p-cdsp0-pas +- qcom,sa8775p-cdsp1-pas +- qcom,sa8775p-gpdsp0-pas +- qcom,sa8775p-gpdsp1-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 - if: properties: compatible: @@ -128,6 +149,7 @@ allOf: properties: compatible: enum: +- qcom,sa8775p-adsp-pas - qcom,sm8550-adsp-pas - qcom,sm8650-adsp-pas - qcom,x1e80100-adsp-pas @@ -177,6 +199,58 @@ allOf: - const: cx - const: mxc - const: nsp + - if: + properties: +compatible: + enum: +- qcom,sa8775p-cdsp-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +- description: NSP0 power domain +power-domain-names: + items: +- const: cx +- const: mxc +- const: nsp0 + + - if: + properties: +compatible: + enum: +- qcom,sa8775p-cdsp1-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +- description: NSP1 power domain +power-domain-names: + items: +- const: cx +- const: mxc +- const: nsp1 + + - if: + properties: +compatible: + enum: +- qcom,sa8775p-gpdsp0-pas +- qcom,sa8775p-gpdsp1-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +power-domain-names: + items: +- const: cx +- const: mxc unevaluatedProperties: false
Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
On 22/05/2024 14:08, Bartosz Golaszewski wrote: From: Tengfei Fan Document the compatibles for the components used to boot the ADSP, CDSP0, CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC. Signed-off-by: Tengfei Fan Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 73fda7565cd1..9d3a862c39e1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -16,6 +16,11 @@ description: properties: compatible: enum: + - qcom,sa8775p-adsp-pas + - qcom,sa8775p-cdsp0-pas + - qcom,sa8775p-cdsp1-pas + - qcom,sa8775p-gpdsp0-pas + - qcom,sa8775p-gpdsp1-pas - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas @@ -44,12 +49,13 @@ properties: firmware-name: $ref: /schemas/types.yaml#/definitions/string-array +minItems: 1 This will allow a single firmware name for all compatible, which is wrong items: - description: Firmware name of the Hexagon core - description: Firmware name of the Hexagon Devicetree memory-region: -minItems: 2 +minItems: 1 Same here items: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication @@ -81,6 +87,21 @@ allOf: maxItems: 5 memory-region: maxItems: 2 + - if: + properties: +compatible: + enum: +- qcom,sa8775p-adsp-pas +- qcom,sa8775p-cdsp0-pas +- qcom,sa8775p-cdsp1-pas +- qcom,sa8775p-gpdsp0-pas +- qcom,sa8775p-gpdsp1-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 - if: properties: compatible: @@ -128,6 +149,7 @@ allOf: properties: compatible: enum: +- qcom,sa8775p-adsp-pas - qcom,sm8550-adsp-pas - qcom,sm8650-adsp-pas - qcom,x1e80100-adsp-pas @@ -177,6 +199,58 @@ allOf: - const: cx - const: mxc - const: nsp + - if: + properties: +compatible: + enum: +- qcom,sa8775p-cdsp-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +- description: NSP0 power domain +power-domain-names: + items: +- const: cx +- const: mxc +- const: nsp0 + + - if: + properties: +compatible: + enum: +- qcom,sa8775p-cdsp1-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +- description: NSP1 power domain +power-domain-names: + items: +- const: cx +- const: mxc +- const: nsp1 + + - if: + properties: +compatible: + enum: +- qcom,sa8775p-gpdsp0-pas +- qcom,sa8775p-gpdsp1-pas +then: + properties: +power-domains: + items: +- description: CX power domain +- description: MXC power domain +power-domain-names: + items: +- const: cx +- const: mxc unevaluatedProperties: false
Re: [PATCH 01/12] soc: qcom: add firmware name helper
On 21/05/2024 11:45, Dmitry Baryshkov wrote:
Qualcomm platforms have different sets of the firmware files, which
differ from platform to platform (and from board to board, due to the
embedded signatures). Rather than listing all the firmware files,
including full paths, in the DT, provide a way to determine firmware
path based on the root DT node compatible.
Ok this looks quite over-engineered but necessary to handle the legacy,
but I really think we should add a way to look for a board-specific path
first and fallback to those SoC specific paths.
Neil
Suggested-by: Arnd Bergmann
Signed-off-by: Dmitry Baryshkov
---
drivers/soc/qcom/Kconfig | 5 +++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/qcom_fw_helper.c | 86 ++
include/linux/soc/qcom/fw_helper.h | 10 +
4 files changed, 102 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 5af33b0e3470..b663774d65f8 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -62,6 +62,11 @@ config QCOM_MDT_LOADER
tristate
select QCOM_SCM
+config QCOM_FW_HELPER
+ tristate "NONE FW HELPER"
+ help
+ Helpers to return platform-specific location for the firmware files.
+
config QCOM_OCMEM
tristate "Qualcomm On Chip Memory (OCMEM) driver"
depends on ARCH_QCOM
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ca0bece0dfff..e612bee5b955 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
+obj-$(CONFIG_QCOM_FW_HELPER) += qcom_fw_helper.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
obj-$(CONFIG_QCOM_PDR_HELPERS)+= pdr_interface.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/qcom_fw_helper.c
b/drivers/soc/qcom/qcom_fw_helper.c
new file mode 100644
index ..13123c2514b8
--- /dev/null
+++ b/drivers/soc/qcom/qcom_fw_helper.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Firmware loading data
+ *
+ * Copyright (C) 2024 Linaro Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static DEFINE_MUTEX(qcom_fw_mutex);
+static const char *fw_path;
+
+static const struct of_device_id qcom_fw_paths[] = {
+ /* device-specific entries */
+ { .compatible = "thundercomm,db845c", .data =
"qcom/sdm845/Thundercomm/db845c", },
+ { .compatible = "qcom,qrb5165-rb5", .data =
"qcom/sm8250/Thundercomm/RB5", },
+ /* SoC default entries */
+ { .compatible = "qcom,apq8016", .data = "qcom/apq8016", },
+ { .compatible = "qcom,apq8096", .data = "qcom/apq8096", },
+ { .compatible = "qcom,sdm845", .data = "qcom/sdm845", },
+ { .compatible = "qcom,sm8250", .data = "qcom/sm8250", },
+ { .compatible = "qcom,sm8350", .data = "qcom/sm8350", },
+ { .compatible = "qcom,sm8450", .data = "qcom/sm8450", },
+ { .compatible = "qcom,sm8550", .data = "qcom/sm8550", },
+ { .compatible = "qcom,sm8650", .data = "qcom/sm8650", },
+ {},
+};
+
+static int qcom_fw_ensure_init(void)
+{
+ const struct of_device_id *match;
+ struct device_node *root;
+
+ if (fw_path)
+ return 0;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return -ENODEV;
+
+ match = of_match_node(qcom_fw_paths, root);
+ of_node_put(root);
+ if (!match || !match->data) {
+ pr_notice("Platform not supported by qcom_fw_helper\n");
+ return -ENODEV;
+ }
+
+ fw_path = match->data;
+
+ return 0;
+}
+
+const char *qcom_get_board_fw(const char *firmware)
+{
+ if (strchr(firmware, '/'))
+ return kstrdup(firmware, GFP_KERNEL);
+
+ scoped_guard(mutex, _fw_mutex) {
+ if (!qcom_fw_ensure_init())
+ return kasprintf(GFP_KERNEL, "%s/%s", fw_path,
firmware);
+ }
+
+ return kstrdup(firmware, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(qcom_get_board_fw);
+
+const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware)
+{
+ if (strchr(firmware, '/'))
+ return devm_kstrdup(dev, firmware, GFP_KERNEL);
+
+ scoped_guard(mutex, _fw_mutex) {
+ if (!qcom_fw_ensure_init())
+ return devm_kasprintf(dev, GFP_KERNEL, "%s/%s",
fw_path, firmware);
+ }
+
+ return devm_kstrdup(dev, firmware, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(devm_qcom_get_board_fw);
+
+MODULE_DESCRIPTION("Firmware helpers for Qualcomm devices");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/soc/qcom/fw_helper.h
b/include/linux/soc/qcom/fw_helper.h
new file mode 100644
index ..755645386bba
--- /dev/null
+++
Re: [PATCH 06/12] remoteproc: qcom_q6v5_pas: switch to mbn files by default
On 21/05/2024 11:45, Dmitry Baryshkov wrote:
We have been pushing userspace to use mbn files by default for ages.
As a preparation for making the firmware-name optional, make the driver
use .mbn instead of .mdt files by default.
I think we should have a mechanism to fallback to .mdt since downstream
uses split mdt on the devices filesystem.
Perhaps only specify .firmware_name = "adsp" and add a list of allowed extension
it will try in a loop ?
Neil
Signed-off-by: Dmitry Baryshkov
---
drivers/remoteproc/qcom_q6v5_pas.c | 76 +++---
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 54d8005d40a3..4694ec4f038d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -812,7 +812,7 @@ static void adsp_remove(struct platform_device *pdev)
static const struct adsp_data adsp_resource_init = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.ssr_name = "lpass",
@@ -822,7 +822,7 @@ static const struct adsp_data adsp_resource_init = {
static const struct adsp_data sdm845_adsp_resource_init = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.load_state = "adsp",
@@ -833,7 +833,7 @@ static const struct adsp_data sdm845_adsp_resource_init = {
static const struct adsp_data sm6350_adsp_resource = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -849,7 +849,7 @@ static const struct adsp_data sm6350_adsp_resource = {
static const struct adsp_data sm6375_mpss_resource = {
.crash_reason_smem = 421,
- .firmware_name = "modem.mdt",
+ .firmware_name = "modem.mbn",
.pas_id = 4,
.minidump_id = 3,
.auto_boot = false,
@@ -864,7 +864,7 @@ static const struct adsp_data sm6375_mpss_resource = {
static const struct adsp_data sm8150_adsp_resource = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -879,7 +879,7 @@ static const struct adsp_data sm8150_adsp_resource = {
static const struct adsp_data sm8250_adsp_resource = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -895,7 +895,7 @@ static const struct adsp_data sm8250_adsp_resource = {
static const struct adsp_data sm8350_adsp_resource = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -911,7 +911,7 @@ static const struct adsp_data sm8350_adsp_resource = {
static const struct adsp_data msm8996_adsp_resource = {
.crash_reason_smem = 423,
- .firmware_name = "adsp.mdt",
+ .firmware_name = "adsp.mbn",
.pas_id = 1,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -925,7 +925,7 @@ static const struct adsp_data msm8996_adsp_resource = {
static const struct adsp_data cdsp_resource_init = {
.crash_reason_smem = 601,
- .firmware_name = "cdsp.mdt",
+ .firmware_name = "cdsp.mbn",
.pas_id = 18,
.auto_boot = true,
.ssr_name = "cdsp",
@@ -935,7 +935,7 @@ static const struct adsp_data cdsp_resource_init = {
static const struct adsp_data sdm845_cdsp_resource_init = {
.crash_reason_smem = 601,
- .firmware_name = "cdsp.mdt",
+ .firmware_name = "cdsp.mbn",
.pas_id = 18,
.auto_boot = true,
.load_state = "cdsp",
@@ -946,7 +946,7 @@ static const struct adsp_data sdm845_cdsp_resource_init = {
static const struct adsp_data sm6350_cdsp_resource = {
.crash_reason_smem = 601,
- .firmware_name = "cdsp.mdt",
+ .firmware_name = "cdsp.mbn",
.pas_id = 18,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -962,7 +962,7 @@ static const struct adsp_data sm6350_cdsp_resource = {
static const struct adsp_data sm8150_cdsp_resource = {
.crash_reason_smem = 601,
- .firmware_name = "cdsp.mdt",
+ .firmware_name = "cdsp.mbn",
.pas_id = 18,
.auto_boot = true,
.proxy_pd_names = (char*[]){
@@ -977,7 +977,7 @@ static const struct adsp_data sm8150_cdsp_resource = {
static const struct adsp_data sm8250_cdsp_resource = {
.crash_reason_smem = 601,
- .firmware_name = "cdsp.mdt",
+ .firmware_name =
[PATCH v7 4/4] arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss
The qlink_logging memory region is also used by the modem firmware,
add it to the reserved memories and add it to the MPSS memory regions.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..7a1cbc823306 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -525,6 +525,11 @@ qdss_mem: qdss@8280 {
no-map;
};
+ qlink_logging_mem: qlink-logging@8480 {
+ reg = <0 0x8480 0 0x20>;
+ no-map;
+ };
+
mpss_dsm_mem: mpss-dsm@86b0 {
reg = <0 0x86b0 0 0x490>;
no-map;
@@ -2627,7 +2632,8 @@ remoteproc_mpss: remoteproc@408 {
"mss";
memory-region = <_mem>, <_mpss_dtb_mem>,
- <_dsm_mem>, <_dsm_mem_2>;
+ <_dsm_mem>, <_dsm_mem_2>,
+ <_logging_mem>;
qcom,qmp = <_qmp>;
--
2.34.1
[PATCH v7 3/4] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 09e8ad9f08c4..d0b1f0f38347 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1213,6 +1213,53 @@ static const struct adsp_data sc7280_wpss_resource = {
.ssctl_id = 0x19,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 3,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1268,6 +1315,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
[PATCH v7 2/4] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 100 -
1 file changed, 66 insertions(+), 34 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index a9dd58608052..09e8ad9f08c4 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 3
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_owners[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,53 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
struct device_node *node;
+ unsigned int perm_size;
+ int offset;
int ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_owners[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_s
[PATCH v7 1/4] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 45 +- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..5f63b6b9a8f5 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,8 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 + - description: Memory region for Qlink Logging required: - compatible @@ -63,6 +68,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +77,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +104,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 5 + maxItems: 5 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +142,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +158,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v7 0/4] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, two more are required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v7: - Rebased on v6.8-rc1 - Add another memory region for MPSS, in bindings, code and DT - Kepts Krzysztof's review on bindings after agreement on irc - Kept drivers patches reviews because it's only a miminal change (value 2 -> 3) - Link to v6: https://lore.kernel.org/r/20231218-topic-sm8650-upstream-remoteproc-v6-0-3d16b37f1...@linaro.org Changes in v6: - Rebased on next-20231218, last patch did not apply anymore - Link to v5: https://lore.kernel.org/r/20231212-topic-sm8650-upstream-remoteproc-v5-0-e749a1a48...@linaro.org Changes in v5: - Rename _perms to _owners per Konrad suggestion - Link to v4: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-remoteproc-v4-0-a96c3e5f0...@linaro.org Changes in v4: - Collected review from Mukesh Ojha - Fixed adsp_unassign_memory_region() as suggested by Mukesh Ojha - Link to v3: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-remoteproc-v3-0-dbd4cabae...@linaro.org Changes in v3: - Collected bindings review tags - Small fixes suggested by Mukesh Ojha - Link to v2: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e...@linaro.org Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (4): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss .../bindings/remoteproc/qcom,sm8550-pas.yaml | 45 ++- arch/arm64/boot/dts/qcom/sm8650.dtsi | 8 +- drivers/remoteproc/qcom_q6v5_pas.c | 150 - 3 files changed, 167 insertions(+), 36 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
[PATCH v6 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 100 -
1 file changed, 66 insertions(+), 34 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index a9dd58608052..e90783fd1129 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_owners[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,53 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
struct device_node *node;
+ unsigned int perm_size;
+ int offset;
int ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_owners[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_s
[PATCH v6 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index e90783fd1129..f7967a25ecdb 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1213,6 +1213,53 @@ static const struct adsp_data sc7280_wpss_resource = {
.ssctl_id = 0x19,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1268,6 +1315,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
[PATCH v6 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..4e8ce9e7e9fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +103,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 + maxItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +141,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +157,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v6 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v6: - Rebased on next-20231218, last patch did not apply anymore - Link to v5: https://lore.kernel.org/r/20231212-topic-sm8650-upstream-remoteproc-v5-0-e749a1a48...@linaro.org Changes in v5: - Rename _perms to _owners per Konrad suggestion - Link to v4: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-remoteproc-v4-0-a96c3e5f0...@linaro.org Changes in v4: - Collected review from Mukesh Ojha - Fixed adsp_unassign_memory_region() as suggested by Mukesh Ojha - Link to v3: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-remoteproc-v3-0-dbd4cabae...@linaro.org Changes in v3: - Collected bindings review tags - Small fixes suggested by Mukesh Ojha - Link to v2: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e...@linaro.org Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- drivers/remoteproc/qcom_q6v5_pas.c | 150 - 2 files changed, 159 insertions(+), 35 deletions(-) --- base-commit: ceb2fe0d438644e1de06b9a6468a1fb8e2199c70 change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
[PATCH v5 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 46d744fbe8ad..83dcde2dec61 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1197,6 +1197,53 @@ static const struct adsp_data sm8550_mpss_resource = {
.region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1249,6 +1296,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
[PATCH v5 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 100 -
1 file changed, 66 insertions(+), 34 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..46d744fbe8ad 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_owners[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,53 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
struct device_node *node;
+ unsigned int perm_size;
+ int offset;
int ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_owners[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_s
[PATCH v5 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..4e8ce9e7e9fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +103,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 + maxItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +141,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +157,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v5 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v5: - Rename _perms to _owners per Konrad suggestion - Link to v4: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-remoteproc-v4-0-a96c3e5f0...@linaro.org Changes in v4: - Collected review from Mukesh Ojha - Fixed adsp_unassign_memory_region() as suggested by Mukesh Ojha - Link to v3: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-remoteproc-v3-0-dbd4cabae...@linaro.org Changes in v3: - Collected bindings review tags - Small fixes suggested by Mukesh Ojha - Link to v2: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e...@linaro.org Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- drivers/remoteproc/qcom_q6v5_pas.c | 150 - 2 files changed, 159 insertions(+), 35 deletions(-) --- base-commit: bbd220ce4e29ed55ab079007cff0b550895258eb change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
Re: [PATCH v4 2/3] remoteproc: qcom: pas: make region assign more generic
On 11/12/2023 10:54, Konrad Dybcio wrote:
On 11.12.2023 10:37, Neil Armstrong wrote:
On 09/12/2023 19:06, Konrad Dybcio wrote:
On 8.12.2023 16:04, Neil Armstrong wrote:
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
[...]
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
Shouldn't this only be called when parse_phandle succeeds? (separate
patch with a fix + cc stable if so?)
It's not a bug, it was added like that because of_node_put() already
checks for a NULL pointer:
https://elixir.bootlin.com/linux/v6.7-rc5/source/drivers/of/dynamic.c#L45
Ack
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable memory-region index
%d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
I think this should be renamed to region_assign_owner(s)
Why ? this bitfield is names "perms" everywhere qcom_scm_assign_mem is used
And IMO that's not correct - there's the qcom_scm_vmperm.perm field which
is oneOf r/w/x/rw/rwx and this one is filled with ORed BIT()-ed elements
allowed in qcom_scm_vmperm.vmid (QCOM_SCM_VMID_...)
Ok right I just use the same namings as in rmtfs_mem, fastrpc & ath10k/qmi,
but indeed the qcom_scm_assign_mem() 3rd param name is srcvm but doc says "vmid for
current set of owners",
so yeah it could be named owners.
I'll send a v5 with the rename.
Neil
Konrad
Re: [PATCH v4 2/3] remoteproc: qcom: pas: make region assign more generic
On 09/12/2023 19:06, Konrad Dybcio wrote:
On 8.12.2023 16:04, Neil Armstrong wrote:
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
[...]
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
Shouldn't this only be called when parse_phandle succeeds? (separate
patch with a fix + cc stable if so?)
It's not a bug, it was added like that because of_node_put() already
checks for a NULL pointer:
https://elixir.bootlin.com/linux/v6.7-rc5/source/drivers/of/dynamic.c#L45
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
I think this should be renamed to region_assign_owner(s)
Why ? this bitfield is names "perms" everywhere qcom_scm_assign_mem is used
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_size[offset],
+ >region_assign_perms[offset],
+ perm, perm_size);
+ if (ret < 0) {
+ dev_err(adsp->dev, "assign memory %d failed\n", offset);
+ return ret;
+ }
}
return 0;
@@ -629,20 +653,23 @@ static int adsp_assign_memory_region(struct qcom_adsp
*adsp)
static void adsp_unassign_memory_region(struct qcom_adsp *adsp)
{
struct qcom_scm_vmperm perm;
+ int offset;
int ret;
- if (!adsp->region_assign_idx)
+ if (!adsp->region_assign_idx || adsp->region_assign_shared)
So when it's *shared*, we don't want to un-assign it?
Exact, when shared the region stays shared, as downstream does, un-assigning
will fail
in this case.
Konrad
Thanks,
Neil
[PATCH v4 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 46371f1ad32d..01effbd969a5 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1197,6 +1197,53 @@ static const struct adsp_data sm8550_mpss_resource = {
.region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1249,6 +1296,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
[PATCH v4 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Reviewed-by: Mukesh Ojha
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 100 -
1 file changed, 66 insertions(+), 34 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..46371f1ad32d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,53 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
struct device_node *node;
+ unsigned int perm_size;
+ int offset;
int ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_
[PATCH v4 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..4e8ce9e7e9fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +103,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 + maxItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +141,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +157,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v4 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v4: - Collected review from Mukesh Ojha - Fixed adsp_unassign_memory_region() as suggested by Mukesh Ojha - Link to v3: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-remoteproc-v3-0-dbd4cabae...@linaro.org Changes in v3: - Collected bindings review tags - Small fixes suggested by Mukesh Ojha - Link to v2: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e...@linaro.org Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- drivers/remoteproc/qcom_q6v5_pas.c | 150 - 2 files changed, 159 insertions(+), 35 deletions(-) --- base-commit: 0f5f12ac05f36f117e793656c3f560625e927f1b change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
[PATCH v3 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 2ea364a04d4c..8f7429d86a6f 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1196,6 +1196,53 @@ static const struct adsp_data sm8550_mpss_resource = {
.region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1248,6 +1295,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
[PATCH v3 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..4e8ce9e7e9fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +103,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 + maxItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +141,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +157,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v3 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 101 -
1 file changed, 66 insertions(+), 35 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..2ea364a04d4c 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,53 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
struct device_node *node;
+ unsigned int perm_size;
+ int offset;
int ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_size[offset],
+
[PATCH v3 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v3: - Collected bindings review tags - Small fixes suggested by Mukesh Ojha - Link to v2: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e...@linaro.org Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- drivers/remoteproc/qcom_q6v5_pas.c | 151 - 2 files changed, 159 insertions(+), 36 deletions(-) --- base-commit: fe1998aa935b44ef873193c0772c43bce74f17dc change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
Re: [PATCH v2 2/3] remoteproc: qcom: pas: make region assign more generic
On 01/11/2023 15:42, Mukesh Ojha wrote:
On 10/31/2023 10:36 PM, Neil Armstrong wrote:
Hi,
On 30/10/2023 14:10, Mukesh Ojha wrote:
On 10/30/2023 3:33 PM, Neil Armstrong wrote:
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 102 -
1 file changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..4829fd26e17d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,52 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
+ unsigned int perm_size = 1;
AFAICS, not need of initialization.
Indeed, removed
struct device_node *node;
- int ret;
+ int offset, ret;
Nit: one variable per line.
Done
if (!adsp->region_assign_idx)
Not related to this patch..
Should not this be valid only for > 1 ?
I don't understand, only region_assign_idx > 1 triggers a memory_assign,
and this check discards configurations with region_assign_idx == 0 as
expected.
Ah, you can ignore the comments, I got the intention after commenting
here ..
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable memory-region index
%d\n",
+ offset);
+ return -EINVAL; > + }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
Do we need array for this, is this changing ?
We need to keep region_assign_perms for unassign, but for the other 2 we would
need to duplicate the code from adsp_assign_memory_region into
adsp_unassign_memory_region.
Thanks got it.
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
-
Re: [PATCH v2 2/3] remoteproc: qcom: pas: make region assign more generic
Hi,
On 30/10/2023 14:10, Mukesh Ojha wrote:
On 10/30/2023 3:33 PM, Neil Armstrong wrote:
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 102 -
1 file changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..4829fd26e17d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,52 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
+ unsigned int perm_size = 1;
AFAICS, not need of initialization.
Indeed, removed
struct device_node *node;
- int ret;
+ int offset, ret;
Nit: one variable per line.
Done
if (!adsp->region_assign_idx)
Not related to this patch..
Should not this be valid only for > 1 ?
I don't understand, only region_assign_idx > 1 triggers a memory_assign,
and this check discards configurations with region_assign_idx == 0 as
expected.
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable memory-region index
%d\n",
+ offset);
+ return -EINVAL; > + }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
Do we need array for this, is this changing ?
We need to keep region_assign_perms for unassign, but for the other 2 we would
need to duplicate the code from adsp_assign_memory_region into
adsp_unassign_memory_region.
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n
[PATCH v2 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 102 -
1 file changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..4829fd26e17d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,52 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
+ unsigned int perm_size = 1;
struct device_node *node;
- int ret;
+ int offset, ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_size[offset],
+
[PATCH v2 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong --- Changes in v2: - Fixed sm8650 entries in allOf:if:then to match Krzysztof's comments - Collected reviewed-by on patch 3 - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-remoteproc-v1-0-a8d20e4ce...@linaro.org --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- drivers/remoteproc/qcom_q6v5_pas.c | 152 - 2 files changed, 159 insertions(+), 37 deletions(-) --- base-commit: fe1998aa935b44ef873193c0772c43bce74f17dc change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
[PATCH v2 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 44 +- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..4e8ce9e7e9fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + maxItems: 5 +interrupt-names: + maxItems: 5 +memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +103,28 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 + maxItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +141,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +157,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH v2 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 4829fd26e17d..c593e6d529b3 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1195,6 +1195,53 @@ static const struct adsp_data sm8550_mpss_resource = {
.region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1247,6 +1294,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
Re: [PATCH 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
On 27/10/2023 09:36, Krzysztof Kozlowski wrote: On 25/10/2023 09:35, Neil Armstrong wrote: Document the DSP Peripheral Authentication Service on the SM8650 Platform. Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 41 +- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..316371c8ee6e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,25 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + minItems: 5 maxItems +interrupt-names: + minItems: 5 maxItems +memory-region: + minItems: 3 maxItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +102,26 @@ allOf: minItems: 6 memory-region: minItems: 3 You need to add here maxItems. Ok, I fixed all that + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: I am not sure if keeping it in the same binding as sm8550 avoids that much duplication. Yes it does, 70% is the bindings would be the same, still if it's still preferable I can duplicate. Thanks, Neil Best regards, Krzysztof
[PATCH 2/3] remoteproc: qcom: pas: make region assign more generic
The current memory region assign only supports a single
memory region.
But new platforms introduces more regions to make the
memory requirements more flexible for various use cases.
Those new platforms also shares the memory region between the
DSP and HLOS.
To handle this, make the region assign more generic in order
to support more than a single memory region and also permit
setting the regions permissions as shared.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 102 -
1 file changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 913a5d2068e8..4829fd26e17d 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,8 @@
#define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
+#define MAX_ASSIGN_COUNT 2
+
struct adsp_data {
int crash_reason_smem;
const char *firmware_name;
@@ -51,6 +53,9 @@ struct adsp_data {
int ssctl_id;
int region_assign_idx;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
};
struct qcom_adsp {
@@ -87,15 +92,18 @@ struct qcom_adsp {
phys_addr_t dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
- phys_addr_t region_assign_phys;
+ phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void *mem_region;
void *dtb_mem_region;
size_t mem_size;
size_t dtb_mem_size;
- size_t region_assign_size;
+ size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
- u64 region_assign_perms;
+ int region_assign_count;
+ bool region_assign_shared;
+ int region_assign_vmid;
+ u64 region_assign_perms[MAX_ASSIGN_COUNT];
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
@@ -590,37 +598,52 @@ static int adsp_alloc_memory_region(struct qcom_adsp
*adsp)
static int adsp_assign_memory_region(struct qcom_adsp *adsp)
{
- struct reserved_mem *rmem = NULL;
- struct qcom_scm_vmperm perm;
+ struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
+ unsigned int perm_size = 1;
struct device_node *node;
- int ret;
+ int offset, ret;
if (!adsp->region_assign_idx)
return 0;
- node = of_parse_phandle(adsp->dev->of_node, "memory-region",
adsp->region_assign_idx);
- if (node)
- rmem = of_reserved_mem_lookup(node);
- of_node_put(node);
- if (!rmem) {
- dev_err(adsp->dev, "unable to resolve shareable
memory-region\n");
- return -EINVAL;
- }
+ for (offset = 0; offset < adsp->region_assign_count; ++offset) {
+ struct reserved_mem *rmem = NULL;
+
+ node = of_parse_phandle(adsp->dev->of_node, "memory-region",
+ adsp->region_assign_idx + offset);
+ if (node)
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(adsp->dev, "unable to resolve shareable
memory-region index %d\n",
+ offset);
+ return -EINVAL;
+ }
- perm.vmid = QCOM_SCM_VMID_MSS_MSA;
- perm.perm = QCOM_SCM_PERM_RW;
+ if (adsp->region_assign_shared) {
+ perm[0].vmid = QCOM_SCM_VMID_HLOS;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm[1].vmid = adsp->region_assign_vmid;
+ perm[1].perm = QCOM_SCM_PERM_RW;
+ perm_size = 2;
+ } else {
+ perm[0].vmid = adsp->region_assign_vmid;
+ perm[0].perm = QCOM_SCM_PERM_RW;
+ perm_size = 1;
+ }
- adsp->region_assign_phys = rmem->base;
- adsp->region_assign_size = rmem->size;
- adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS);
+ adsp->region_assign_phys[offset] = rmem->base;
+ adsp->region_assign_size[offset] = rmem->size;
+ adsp->region_assign_perms[offset] = BIT(QCOM_SCM_VMID_HLOS);
- ret = qcom_scm_assign_mem(adsp->region_assign_phys,
- adsp->region_assign_size,
- >region_assign_perms,
- , 1);
- if (ret < 0) {
- dev_err(adsp->dev, "assign memory failed\n");
- return ret;
+ ret = qcom_scm_assign_mem(adsp->region_assign_phys[offset],
+ adsp->region_assign_size[offset],
+
[PATCH 0/3] remoteproc: qcom: Introduce DSP support for SM8650
Add the bindings and driver changes for DSP support on the SM8650 platform in order to enable the aDSP, cDSP and MPSS subsystems to boot. Compared to SM8550, where SM8650 uses the same dual firmware files, (dtb file and main firmware) the memory zones requirement has changed: - cDSP: now requires 2 memory zones to be configured as shared between the cDSP and the HLOS subsystem - MPSS: In addition to the memory zone required for the SM8550 MPSS, another one is required to be configured for MPSS usage only. In order to handle this and avoid code duplication, the region_assign_* code patch has been made more generic and is able handle multiple DSP-only memory zones (for MPSS) or DSP-HLOS shared memory zones (cDSP) in the same region_assign functions. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm85650/upstream/integ Signed-off-by: Neil Armstrong --- Neil Armstrong (3): dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS remoteproc: qcom: pas: make region assign more generic remoteproc: qcom: pas: Add SM8650 remoteproc support .../bindings/remoteproc/qcom,sm8550-pas.yaml | 41 +- drivers/remoteproc/qcom_q6v5_pas.c | 152 - 2 files changed, 156 insertions(+), 37 deletions(-) --- base-commit: fe1998aa935b44ef873193c0772c43bce74f17dc change-id: 20231016-topic-sm8650-upstream-remoteproc-66a87eeb6fee Best regards, -- Neil Armstrong
[PATCH 1/3] dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
Document the DSP Peripheral Authentication Service on the SM8650 Platform. Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 41 +- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb06..316371c8ee6e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,9 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas reg: maxItems: 1 @@ -49,6 +52,7 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 required: - compatible @@ -63,6 +67,7 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas +- qcom,sm8650-adsp-pas then: properties: interrupts: @@ -71,7 +76,25 @@ allOf: maxItems: 5 memory-region: maxItems: 2 -else: + - if: + properties: +compatible: + enum: +- qcom,sm8650-cdsp-pas +then: + properties: +interrupts: + minItems: 5 +interrupt-names: + minItems: 5 +memory-region: + minItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8550-mpss-pas +then: properties: interrupts: minItems: 6 @@ -79,12 +102,26 @@ allOf: minItems: 6 memory-region: minItems: 3 + - if: + properties: +compatible: + enum: +- qcom,sm8650-mpss-pas +then: + properties: +interrupts: + minItems: 6 +interrupt-names: + minItems: 6 +memory-region: + minItems: 4 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas +- qcom,sm8650-adsp-pas then: properties: power-domains: @@ -101,6 +138,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas +- qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +154,7 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas +- qcom,sm8650-cdsp-pas then: properties: power-domains: -- 2.34.1
[PATCH 3/3] remoteproc: qcom: pas: Add SM8650 remoteproc support
Add DSP Peripheral Authentication Service support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
drivers/remoteproc/qcom_q6v5_pas.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 4829fd26e17d..c593e6d529b3 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1195,6 +1195,53 @@ static const struct adsp_data sm8550_mpss_resource = {
.region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
};
+static const struct adsp_data sm8650_cdsp_resource = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .dtb_firmware_name = "cdsp_dtb.mdt",
+ .pas_id = 18,
+ .dtb_pas_id = 0x25,
+ .minidump_id = 7,
+ .auto_boot = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mxc",
+ "nsp",
+ NULL
+ },
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+ .region_assign_idx = 2,
+ .region_assign_count = 1,
+ .region_assign_shared = true,
+ .region_assign_vmid = QCOM_SCM_VMID_CDSP,
+};
+
+static const struct adsp_data sm8650_mpss_resource = {
+ .crash_reason_smem = 421,
+ .firmware_name = "modem.mdt",
+ .dtb_firmware_name = "modem_dtb.mdt",
+ .pas_id = 4,
+ .dtb_pas_id = 0x26,
+ .minidump_id = 3,
+ .auto_boot = false,
+ .decrypt_shutdown = true,
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .load_state = "modem",
+ .ssr_name = "mpss",
+ .sysmon_name = "modem",
+ .ssctl_id = 0x12,
+ .region_assign_idx = 2,
+ .region_assign_count = 2,
+ .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
+};
+
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,msm8226-adsp-pil", .data = _resource_init},
{ .compatible = "qcom,msm8953-adsp-pil", .data =
_adsp_resource},
@@ -1247,6 +1294,9 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sm8550-adsp-pas", .data = _adsp_resource},
{ .compatible = "qcom,sm8550-cdsp-pas", .data = _cdsp_resource},
{ .compatible = "qcom,sm8550-mpss-pas", .data = _mpss_resource},
+ { .compatible = "qcom,sm8650-adsp-pas", .data = _adsp_resource},
+ { .compatible = "qcom,sm8650-cdsp-pas", .data = _cdsp_resource},
+ { .compatible = "qcom,sm8650-mpss-pas", .data = _mpss_resource},
{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);
--
2.34.1
Re: [PATCH 2/2] usb: typec: add support for PTN36502 redriver
On 20/10/2023 08:13, Luca Weiss wrote: On Tue Oct 17, 2023 at 10:34 AM CEST, Heikki Krogerus wrote: Hi, On Fri, Oct 13, 2023 at 04:24:48PM +0200, Luca Weiss wrote: Add a driver for the NXP PTN36502 Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver. Signed-off-by: Luca Weiss Looks OK to me, but couple of nitpicks below. With those fixed: Reviewed-by: Heikki Krogerus --- drivers/usb/typec/mux/Kconfig| 10 + drivers/usb/typec/mux/Makefile | 1 + drivers/usb/typec/mux/ptn36502.c | 421 +++ 3 files changed, 432 insertions(+) diff --git a/drivers/usb/typec/mux/Kconfig b/drivers/usb/typec/mux/Kconfig index 65da61150ba7..816b9bd08355 100644 --- a/drivers/usb/typec/mux/Kconfig +++ b/drivers/usb/typec/mux/Kconfig @@ -46,4 +46,14 @@ config TYPEC_MUX_NB7VPQ904M Say Y or M if your system has a On Semiconductor NB7VPQ904M Type-C redriver chip found on some devices with a Type-C port. +config TYPEC_MUX_PTN36502 + tristate "NXP PTN36502 Type-C redriver driver" + depends on I2C + depends on DRM || DRM=n + select DRM_PANEL_BRIDGE if DRM + select REGMAP_I2C + help + Say Y or M if your system has a NXP PTN36502 Type-C redriver chip + found on some devices with a Type-C port. + endmenu diff --git a/drivers/usb/typec/mux/Makefile b/drivers/usb/typec/mux/Makefile index 76196096ef41..9d6a5557b0bd 100644 --- a/drivers/usb/typec/mux/Makefile +++ b/drivers/usb/typec/mux/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_TYPEC_MUX_GPIO_SBU)+= gpio-sbu-mux.o obj-$(CONFIG_TYPEC_MUX_PI3USB30532) += pi3usb30532.o obj-$(CONFIG_TYPEC_MUX_INTEL_PMC) += intel_pmc_mux.o obj-$(CONFIG_TYPEC_MUX_NB7VPQ904M)+= nb7vpq904m.o +obj-$(CONFIG_TYPEC_MUX_PTN36502) += ptn36502.o diff --git a/drivers/usb/typec/mux/ptn36502.c b/drivers/usb/typec/mux/ptn36502.c new file mode 100644 index ..91684a856f3a --- /dev/null +++ b/drivers/usb/typec/mux/ptn36502.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP PTN36502 Type-C driver + * + * Copyright (C) 2023 Luca Weiss + * + * Based on NB7VPQ904M driver: + * Copyright (C) 2023 Dmitry Baryshkov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PTN36502_CHIP_ID_REG 0x00 +#define PTN36502_CHIP_ID 0x02 + +#define PTN36502_CHIP_REVISION_REG 0x01 +#define PTN36502_CHIP_REVISION_BASE(val) FIELD_GET(GENMASK(7, 4), (val)) +#define PTN36502_CHIP_REVISION_METAL(val) FIELD_GET(GENMASK(3, 0), (val)) + +#define PTN36502_DP_LINK_CTRL_REG 0x06 +#define PTN36502_DP_LINK_CTRL_LANES_2 (2 << 2) +#define PTN36502_DP_LINK_CTRL_LANES_4 (3 << 2) +#define PTN36502_DP_LINK_CTRL_LINK_RATE_5_4GBPS(2 << 0) + +/* Registers for lane 0 (0x07) to lane 3 (0x0a) have the same layout */ +#define PTN36502_DP_LANE_CTRL_REG(n) (0x07 + (n)) +#define PTN36502_DP_LANE_CTRL_RX_GAIN_3DB (2<<4) +#define PTN36502_DP_LANE_CTRL_TX_SWING_800MVPPD(2<<2) +#define PTN36502_DP_LANE_CTRL_PRE_EMPHASIS_3_5DB (1<<0) + +#define PTN36502_MODE_CTRL1_REG0x0b +#define PTN36502_MODE_CTRL1_PLUG_ORIENT_REVERSE(1<<5) +#define PTN36502_MODE_CTRL1_AUX_CROSSBAR_SW_ON (1<<3) +#define PTN36502_MODE_CTRL1_MODE_OFF (0<<0) +#define PTN36502_MODE_CTRL1_MODE_USB_ONLY (1<<0) +#define PTN36502_MODE_CTRL1_MODE_USB_DP(2<<0) +#define PTN36502_MODE_CTRL1_MODE_DP(3<<0) + +#define PTN36502_DEVICE_CTRL_REG 0x0d +#define PTN36502_DEVICE_CTRL_AUX_MONITORING_EN (1<<7) You have couple of different styles here. Please try to always use BIT() and GENMASK() macros when possible. At the very least put spaces around << and >>. Hi Heikki, I was wondering when writing that whether GENMASK was actually proper use for values you write to registers, when not actually used as a bitmask. Since the datasheet refers to e.g. with TX_SWING_800MVPPD (2<<2) that you write a '2' to the correct bits of this register. But when using BIT(3) kind of hides this relationship if someone refers back to the datasheet. Or same with "3<<2" -> GENMASK(3, 2) or whatever. The proper way is to define the MASK for the field GENMASK(3, 2) and then use FIELD_PREP(GENMASK(3, 2), 2) to write 2 in this field. You could replace with: #define PTN36502_DP_LANE_CTRL_TX_SWING_MASK GENMASK(3, 2) #define PTN36502_DP_LANE_CTRL_TX_SWING_800MVPPD (2) and in the code lane_ctrl_val = FIELD_PREP(PTN36502_DP_LANE_CTRL_RX_GAIN_MASK, PTN36502_DP_LANE_CTRL_RX_GAIN_3DB) |
Re: [PATCH 1/3] dt-bindings: usb: fsa4480: Add data-lanes property to endpoint
On 16/10/2023 16:22, Rob Herring wrote: On Fri, Oct 13, 2023 at 01:38:05PM +0200, Luca Weiss wrote: Allow specifying data-lanes to reverse the SBU muxing orientation where necessary by the hardware design. What situation in the hardware design makes this necessary. Please describe the problem. Signed-off-by: Luca Weiss --- .../devicetree/bindings/usb/fcs,fsa4480.yaml | 29 +- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml b/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml index f6e7a5c1ff0b..86f6d633c2fb 100644 --- a/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml +++ b/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml @@ -32,10 +32,37 @@ properties: type: boolean port: -$ref: /schemas/graph.yaml#/properties/port +$ref: /schemas/graph.yaml#/$defs/port-base description: A port node to link the FSA4480 to a TypeC controller for the purpose of handling altmode muxing and orientation switching. +unevaluatedProperties: false + +properties: + endpoint: +$ref: /schemas/graph.yaml#/$defs/endpoint-base +unevaluatedProperties: false + +properties: + data-lanes: +$ref: /schemas/types.yaml#/definitions/uint32-array +description: + Specifies how the AUX+/- lines are connected to SBU1/2. Doesn't this depend on the connector orientation? Or it is both that and the lines can be swapped on the PCB? Seems like an abuse of data-lanes which already has a definition which is not about swapping + and - differential lanes. The FSA acts as a mux between DP AUX, Audio lanes on one side and the USB-C SBU lanes on the other side. ___ __ | | | |-- HP --| | |-- MIC --| |or SoC | | MUX |-- SBU1 ---> To the USB-C Codec |-- AUX+ --| |-- SBU2 ---> connected |-- AUX- --| | __| | | The SBU1 & SBU2 are connected to the USB-C connector, and the actual orientation to the connected devices/cable/whatever is determined by the TPCM and the MUX in the FSA4480 with be dynamically changed according to the CC1/CC2 detection and PD alt mode. But on the other side the orientation of the AUX+/AUX- connected to the SoC is not tied to the USB-C orientation but how it's routed on the PCB. This describes how the AUX+/AUX- are physically routed to the FSA4480 chip. Neil Rob
Re: [PATCH 2/3] usb: typec: fsa4480: Add support to swap SBU orientation
On 13/10/2023 13:38, Luca Weiss wrote:
On some hardware designs the AUX+/- lanes are connected reversed to
SBU1/2 compared to the expected design by FSA4480.
Made more complicated, the otherwise compatible Orient-Chip OCP96011
expects the lanes to be connected reversed compared to FSA4480.
* FSA4480 block diagram shows AUX+ connected to SBU2 and AUX- to SBU1.
* OCP96011 block diagram shows AUX+ connected to SBU1 and AUX- to SBU2.
So if OCP96011 is used as drop-in for FSA4480 then the orientation
handling in the driver needs to be reversed to match the expectation of
the OCP96011 hardware.
Support parsing the data-lanes parameter in the endpoint node to swap
this in the driver.
The parse_data_lanes_mapping function is mostly taken from nb7vpq904m.c.
I see the inspiration :-)
Signed-off-by: Luca Weiss
---
drivers/usb/typec/mux/fsa4480.c | 81 +
1 file changed, 81 insertions(+)
diff --git a/drivers/usb/typec/mux/fsa4480.c b/drivers/usb/typec/mux/fsa4480.c
index e0ee1f621abb..6ee467c96fb6 100644
--- a/drivers/usb/typec/mux/fsa4480.c
+++ b/drivers/usb/typec/mux/fsa4480.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -60,6 +61,7 @@ struct fsa4480 {
unsigned int svid;
u8 cur_enable;
+ bool swap_sbu_lanes;
};
static const struct regmap_config fsa4480_regmap_config = {
@@ -76,6 +78,9 @@ static int fsa4480_set(struct fsa4480 *fsa)
u8 enable = FSA4480_ENABLE_DEVICE;
u8 sel = 0;
+ if (fsa->swap_sbu_lanes)
+ reverse = !reverse;
+
/* USB Mode */
if (fsa->mode < TYPEC_STATE_MODAL ||
(!fsa->svid && (fsa->mode == TYPEC_MODE_USB2 ||
@@ -179,12 +184,84 @@ static int fsa4480_mux_set(struct typec_mux_dev *mux,
struct typec_mux_state *st
return ret;
}
+enum {
+ NORMAL_LANE_MAPPING,
+ INVERT_LANE_MAPPING,
+};
+
+#define DATA_LANES_COUNT 2
+
+static const int supported_data_lane_mapping[][DATA_LANES_COUNT] = {
+ [NORMAL_LANE_MAPPING] = { 0, 1 },
+ [INVERT_LANE_MAPPING] = { 1, 0 },
+};
+
+static int fsa4480_parse_data_lanes_mapping(struct fsa4480 *fsa)
+{
+ struct device_node *ep;
+ u32 data_lanes[DATA_LANES_COUNT];
+ int ret, i, j;
+
+ ep = of_graph_get_next_endpoint(fsa->client->dev.of_node, NULL);
+ if (!ep)
+ return 0;
+
+ ret = of_property_count_u32_elems(ep, "data-lanes");
+ if (ret == -EINVAL)
+ /* Property isn't here, consider default mapping */
+ goto out_done;
+ if (ret < 0)
+ goto out_error;
+
+ if (ret != DATA_LANES_COUNT) {
+ dev_err(>client->dev, "expected 2 data lanes\n");
+ ret = -EINVAL;
+ goto out_error;
+ }
+
+ ret = of_property_read_u32_array(ep, "data-lanes", data_lanes,
DATA_LANES_COUNT);
+ if (ret)
+ goto out_error;
+
+ for (i = 0; i < ARRAY_SIZE(supported_data_lane_mapping); i++) {
+ for (j = 0; j < DATA_LANES_COUNT; j++) {
+ if (data_lanes[j] != supported_data_lane_mapping[i][j])
+ break;
+ }
+
+ if (j == DATA_LANES_COUNT)
+ break;
+ }
+
+ switch (i) {
+ case NORMAL_LANE_MAPPING:
+ break;
+ case INVERT_LANE_MAPPING:
+ fsa->swap_sbu_lanes = true;
+ dev_info(>client->dev, "using inverted data lanes
mapping\n");
+ break;
+ default:
+ dev_err(>client->dev, "invalid data lanes mapping\n");
+ ret = -EINVAL;
+ goto out_error;
+ }
+
+out_done:
+ ret = 0;
+
+out_error:
+ of_node_put(ep);
+
+ return ret;
+}
It's probbaly slighly over engineered for 2 lanes, and at some point
this could go into an helper somewhere because we will need it for all
SBU muxes and redrivers/retimers.
+
static int fsa4480_probe(struct i2c_client *client)
{
struct device *dev = >dev;
struct typec_switch_desc sw_desc = { };
struct typec_mux_desc mux_desc = { };
struct fsa4480 *fsa;
+ int ret;
fsa = devm_kzalloc(dev, sizeof(*fsa), GFP_KERNEL);
if (!fsa)
@@ -193,6 +270,10 @@ static int fsa4480_probe(struct i2c_client *client)
fsa->client = client;
mutex_init(>lock);
+ ret = fsa4480_parse_data_lanes_mapping(fsa);
+ if (ret)
+ return ret;
+
fsa->regmap = devm_regmap_init_i2c(client, _regmap_config);
if (IS_ERR(fsa->regmap))
return dev_err_probe(dev, PTR_ERR(fsa->regmap), "failed to
initialize regmap\n");
But since I did the same in nb7vpq904m, and the SBU can be inverted, LGTM
Reviewed-by: Neil Armstrong
Neil
Re: [PATCH v11 2/4] arm64: dts: mt8183: Add node for the Mali GPU
On 26/01/2021 02:17, Nicolas Boichat wrote:
> Add a basic GPU node for mt8183.
>
> Signed-off-by: Nicolas Boichat
> ---
> The binding we use with out-of-tree Mali drivers includes more
> clocks, this is used for devfreq: the out-of-tree driver switches
> clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> switches clk_mux back to clk_main_parent:
> (see
> https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
> clocks =
> < CLK_TOP_MFGPLL_CK>,
> < CLK_TOP_MUX_MFG>,
> <>,
> < CLK_MFG_BG3D>;
> clock-names =
> "clk_main_parent",
> "clk_mux",
> "clk_sub_parent",
> "subsys_mfg_cg";
> (based on discussions, this probably belongs in the clock core)
>
> This only matters for devfreq, that is disabled anyway as we don't
> have platform-specific code to handle >1 supplies.
>
> Changes in v11:
> - mt8183*.dts: remove incorrect supply-names
>
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6:
> - Add gpu regulators to kukui dtsi as well.
> - Power domains are now attached to spm, not scpsys
> - Drop R-B.
>
> Changes in v5:
> - Rename "2d" power domain to "core2" (keep R-B again).
>
> Changes in v4:
> - Add power-domain-names to describe the 3 domains.
>(kept Alyssa's reviewed-by as the change is minor)
>
> Changes in v3: None
> Changes in v2:
> - Use sram instead of mali_sram as SRAM supply name.
> - Rename mali@ to gpu@.
>
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 5 +
> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 5 +
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++
> 3 files changed, 115 insertions(+)
>
If you re-spin, you can also add the same changes to mt8183-pumpkin.dts :
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index eb6e595c2975..cc23e5df391e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -68,6 +68,11 @@ {
status = "okay";
};
+ {
+ mali-supply = <_vgpu_reg>;
+ sram-supply = <_vsram_gpu_reg>;
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_0>;
I did a boot-test of the platform with panfrost and drm-misc-next and it worked
fine.
Thanks,
Neil
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index cba2d8933e79..1cfbea5a0101 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -42,6 +42,11 @@ {
> status = "okay";
> };
>
> + {
> + mali-supply = <_vgpu_reg>;
> + sram-supply = <_vsram_gpu_reg>;
> +};
> +
> {
> pinctrl-names = "default";
> pinctrl-0 = <_pins_0>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index bf2ad1294dd3..a38315b604df 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -249,6 +249,11 @@ {
> proc-supply = <_vproc11_reg>;
> };
>
> + {
> + mali-supply = <_vgpu_reg>;
> + sram-supply = <_vsram_gpu_reg>;
> +};
> +
> {
> pinctrl-names = "default";
> pinctrl-0 = <_pins>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 5b782a4769e7..5430e05e18a0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -964,6 +964,111 @@ mfgcfg: syscon@1300 {
> #clock-cells = <1>;
> };
>
> + gpu: gpu@1304 {
> + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
> + reg = <0 0x1304 0 0x4000>;
> + interrupts =
> + ,
> + ,
> + ;
> + interrupt-names = "job", "mmu", "gpu";
> +
> + clocks = < CLK_TOP_MFGPLL_CK>;
> +
> + power-domains =
> + < MT8183_POWER_DOMAIN_MFG_CORE0>,
> + < MT8183_POWER_DOMAIN_MFG_CORE1>,
> + < MT8183_POWER_DOMAIN_MFG_2D>;
> + power-domain-names = "core0", "core1", "core2";
> +
> + operating-points-v2 = <_opp_table>;
> + };
> +
> + gpu_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + opp-microvolt = <625000>, <85>;
> + };
> +
> +
Re: [PATCH 0/2] drm/bridge: dw-hdmi: disable loading of DW-HDMI CEC sub-driver
On 20/04/2021 17:13, Hans Verkuil wrote: > On 16/04/2021 13:38, Neil Armstrong wrote: >> On 16/04/2021 11:58, Laurent Pinchart wrote: >>> Hi Neil, >>> >>> On Fri, Apr 16, 2021 at 11:27:35AM +0200, Neil Armstrong wrote: >>>> This adds DW-HDMI driver a glue option to disable loading of the CEC >>>> sub-driver. >>>> >>>> On some SoCs, the CEC functionality is enabled in the IP config bits, but >>>> the >>>> CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit >>>> is set >>>> but the DW-HDMI CEC signal is not connected to a physical pin, leading to >>>> some >>>> confusion when the DW-HDMI CEC controller can't communicate on the bus. >>> >>> If we can't trust the CEC config bit, would it be better to not use it >>> at all, and instead let each platform glue logic tell whether to enable >>> CEC or not ? >> >> Actually, the CEC config bit is right, the HW exists and should be >> functional, but >> this bit doesn't tell if the CEC signal is connected to something. >> >> This lies in the IP integration, like other bits under the >> "amlogic,meson-*-dw-hdmi" >> umbrella. >> >> The first attempt was by Hans using DT, but adding a property in DT for a >> vendor >> specific compatible doesn't make sense. Another idea would be to describe the >> CEC signal endpoint like we do for video signal, but I think this is out of >> scope and >> this solution is much simpler and straightforward, and it's more an >> exception than >> a general use case to solve. > > While a DT property might not make sense in this particular case, I still > believe that it is a perfectly valid approach in general: whether or not > the CEC pin is connected is at the hardware level decision, it is not > something that software can detect. If the designer of the board didn't > connect it, then the only place you can define that is in the device tree. Agreed, we need to define a smart way to declare CEC bus relationship in DT, the side effect would be to handle this particular case. > > Anyway, for meson I am fine with this solution. At least it prevents creating > a non-functioning cec device. So for this series: > > Acked-by: Hans Verkuil Thanks, Applying this serie to drm-misc-next Neil > > Regards, > > Hans > >> >> Neil >> >>> >>>> Jernej Skrabec (1): >>>> drm/bridge/synopsys: dw-hdmi: Add an option to suppress loading CEC >>>> driver >>>> >>>> Neil Armstrong (1): >>>> drm/meson: dw-hdmi: disable DW-HDMI CEC sub-driver >>>> >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- >>>> drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 + >>>> include/drm/bridge/dw_hdmi.h | 2 ++ >>>> 3 files changed, 4 insertions(+), 1 deletion(-) >>>> >>> >> >> ___ >> dri-devel mailing list >> dri-de...@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel >> >
Re: [v2,PATCH 1/3] drm/mediatek: dpi dual edge sample mode support
Hi,
On 14/04/2021 15:35, Rex-BC Chen wrote:
> DPI can sample on falling, rising or both edge.
> When DPI sample the data both rising and falling edge.
> It can reduce half data io pins.
>
> Signed-off-by: Jitao Shi
> Signed-off-by: Rex-BC Chen
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index b05f900d9322..21a3a7b78835 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -83,6 +83,7 @@ struct mtk_dpi {
> struct pinctrl *pinctrl;
> struct pinctrl_state *pins_gpio;
> struct pinctrl_state *pins_dpi;
> + bool ddr_edge_sel;
> int refcount;
> };
>
> @@ -121,6 +122,7 @@ struct mtk_dpi_conf {
> unsigned int (*cal_factor)(int clock);
> u32 reg_h_fre_con;
> bool edge_sel_en;
> + bool dual_edge;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -380,6 +382,15 @@ static void mtk_dpi_config_color_format(struct mtk_dpi
> *dpi,
> }
> }
>
> +static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
> +{
> + if (dpi->conf->dual_edge) {
> + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> + DDR_EN | DDR_4PHASE);
> + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->ddr_edge_sel ?
> EDGE_SEL : 0, EDGE_SEL);
> + }
> +}
> +
By using the downstream code as reference:
- clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+ clk_set_rate(dpi->pixel_clk, vm.pixelclock * (dpi->conf->dual_edge ? 2
: 1));
is missing in mtk_dpi_set_display_mode()
> static void mtk_dpi_power_off(struct mtk_dpi *dpi)
> {
> if (WARN_ON(dpi->refcount == 0))
> @@ -518,6 +529,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> mtk_dpi_config_color_format(dpi, dpi->color_format);
> mtk_dpi_config_2n_h_fre(dpi);
> + mtk_dpi_dual_edge(dpi);
> mtk_dpi_config_disable_edge(dpi);
> mtk_dpi_sw_reset(dpi, false);
>
>
Neil
[PATCH v3 4/5] gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock
Some SoCs like the MT8167 have a hard limit on the maximal supported HDMI TMDS
clock, so add a configuration value to filter out those modes.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0539262e69d3..bc50d97f2553 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -149,6 +149,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
+ unsigned long max_mode_clock;
};
struct mtk_hdmi {
@@ -1226,6 +1227,10 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge
*bridge,
if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
return MODE_BAD;
+ if (hdmi->conf->max_mode_clock &&
+ mode->clock > hdmi->conf->max_mode_clock)
+ return MODE_CLOCK_HIGH;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
[PATCH v3 5/5] gpu/drm: mediatek: hdmi: add MT8167 configuration
The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
and is not validated and supported for HDMI modes out of HDMI CEA modes,
so add a configuration entry linked to the MT8167 compatible.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index bc50d97f2553..c1651a83700d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1787,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701
= {
.tz_disabled = true,
};
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
+ .max_mode_clock = 148500,
+ .cea_modes_only = true,
+};
+
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi",
.data = _hdmi_conf_mt2701,
},
+ { .compatible = "mediatek,mt8167-hdmi",
+ .data = _hdmi_conf_mt8167,
+ },
{ .compatible = "mediatek,mt8173-hdmi",
},
{}
--
2.25.1
[PATCH v3 3/5] gpu/drm: mediatek: hdmi: add check for CEA modes only
Some SoCs like the MT8167 are not validated and supported for HDMI modes
out of HDMI CEA modes, so add a configuration boolean to filter out
non-CEA modes.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index dea46d66e712..0539262e69d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -148,6 +148,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
+ bool cea_modes_only;
};
struct mtk_hdmi {
@@ -1222,6 +1223,9 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge
*bridge,
return MODE_BAD;
}
+ if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
+ return MODE_BAD;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
[PATCH v3 2/5] dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings
Add mt8167 SoC compatible to Mediatek hdmi, hdmi-ddc and cec schema bindings. Signed-off-by: Neil Armstrong --- .../devicetree/bindings/display/mediatek/mediatek,cec.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi.yaml | 1 + 3 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml index b38d8732d7e0..66288b9f0aa6 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-cec + - mediatek,mt8167-cec - mediatek,mt8173-cec reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml index c8ba94d6908b..b6fcdfb99ab2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-hdmi-ddc + - mediatek,mt8167-hdmi-ddc - mediatek,mt8173-hdmi-ddc reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml index 6a144faed682..111967efa999 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -19,6 +19,7 @@ properties: enum: - mediatek,mt2701-hdmi - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: -- 2.25.1
[PATCH v3 1/5] dt-bindings: display: mediatek,hdmi: Convert to use graph schema
Update the mediatek,dpi binding to use the graph schema.
Signed-off-by: Neil Armstrong
---
.../display/mediatek/mediatek,cec.yaml| 51 +++
.../display/mediatek/mediatek,hdmi-ddc.yaml | 57
.../display/mediatek/mediatek,hdmi.txt| 136 --
.../display/mediatek/mediatek,hdmi.yaml | 132 +
4 files changed, 240 insertions(+), 136 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
delete mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
new file mode 100644
index ..b38d8732d7e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI CEC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The HDMI CEC controller handles hotplug detection and CEC communication.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt7623-cec
+ - mediatek,mt8173-cec
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+cec: cec@10013000 {
+compatible = "mediatek,mt8173-cec";
+reg = <0x10013000 0xbc>;
+interrupts = ;
+clocks = < CLK_INFRA_CEC>;
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
new file mode 100644
index ..c8ba94d6908b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt7623-hdmi-ddc
+ - mediatek,mt8173-hdmi-ddc
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+hdmi_ddc0: i2c@11012000 {
+compatible = "mediatek,mt8173-hdmi-ddc";
+reg = <0x11012000 0x1c>;
+interrupts = ;
+clocks = < CLK_PERI_I2C5>;
+clock-names = "ddc-i2c";
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
deleted file mode 100644
index b284ca51b913..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-Mediatek HDMI Encoder
-=
-
-The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
-its parallel input.
-
-Required properties:
-- compatible: Should be "mediatek,-hdmi".
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
-- phys: phandle link to the HDMI PHY node.
- See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
-- phy-names: must contain "hdmi"
-- mediatek,syscon-hdmi: phandle link and register offset to the system
- configuration registers. For mt8173 this must be offset 0x900 into the
- MMSYS_CONFIG region: < 0x900>.
-- ports: A node containing input and output port nodes with endpoint
- definitions as documented in Documentation/devicetree/bindings/graph.txt.
-- port@0: The input port in the ports node should be connected to a DPI output
- port.
-- port@1: Th
[PATCH v3 0/5] mediatek: hdmi: add MT8167 configuration
The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock, and is not validated and supported for HDMI modes out of HDMI CEA modes. To achieve this: - switch the mediatek HDMI bindings to YAML - add the MT8167 compatible - add a boolean to discard the non-CEA modes - add a value to specify mac TMDS supported clock - add a conf entry for the MT8167 compatible Changes since v4: - fixed bindings Neil Armstrong (5): dt-bindings: display: mediatek,hdmi: Convert to use graph schema dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings gpu/drm: mediatek: hdmi: add check for CEA modes only gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock gpu/drm: mediatek: hdmi: add MT8167 configuration .../display/mediatek/mediatek,cec.yaml| 52 +++ .../display/mediatek/mediatek,hdmi-ddc.yaml | 58 .../display/mediatek/mediatek,hdmi.txt| 136 -- .../display/mediatek/mediatek,hdmi.yaml | 133 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +++ 5 files changed, 260 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml -- 2.25.1
[PATCH v4 1/3] dt-bindings: display: bridge: add it66121 bindings
From: Phong LE
Add the ITE bridge HDMI it66121 bindings.
Signed-off-by: Phong LE
Signed-off-by: Neil Armstrong
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/ite,it66121.yaml | 124 ++
1 file changed, 124 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
new file mode 100644
index ..6ec1d5fbb8bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE it66121 HDMI bridge Device Tree Bindings
+
+maintainers:
+ - Phong LE
+ - Neil Armstrong
+
+description: |
+ The IT66121 is a high-performance and low-power single channel HDMI
+ transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible
+ to DVI 1.0 specifications.
+
+properties:
+ compatible:
+const: ite,it66121
+
+ reg:
+maxItems: 1
+
+ reset-gpios:
+maxItems: 1
+description: GPIO connected to active low reset
+
+ vrf12-supply:
+description: Regulator for 1.2V analog core power.
+
+ vcn33-supply:
+description: Regulator for 3.3V digital core power.
+
+ vcn18-supply:
+description: Regulator for 1.8V IO core power.
+
+ interrupts:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DPI input port.
+
+properties:
+ endpoint:
+$ref: /schemas/graph.yaml#/$defs/endpoint-base
+unevaluatedProperties: false
+
+properties:
+ bus-width:
+description:
+ Endpoint bus width.
+enum:
+ - 12 # 12 data lines connected and dual-edge mode
+ - 24 # 24 data lines connected and single-edge mode
+default: 24
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: HDMI Connector port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vrf12-supply
+ - vcn33-supply
+ - vcn18-supply
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+it66121hdmitx: hdmitx@4c {
+compatible = "ite,it66121";
+pinctrl-names = "default";
+pinctrl-0 = <_pins_default>;
+vcn33-supply = <_vcn33_wifi_reg>;
+vcn18-supply = <_vcn18_reg>;
+vrf12-supply = <_vrf12_reg>;
+reset-gpios = < 160 GPIO_ACTIVE_LOW>;
+interrupt-parent = <>;
+interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+reg = <0x4c>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+it66121_in: endpoint {
+bus-width = <12>;
+remote-endpoint = <_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+hdmi_conn_out: endpoint {
+remote-endpoint = <_conn_in>;
+};
+};
+};
+};
+};
--
2.25.1
[PATCH v4 3/3] MAINTAINERS: add it66121 HDMI bridge driver entry
From: Phong LE Add Neil Armstrong and myself as maintainers Signed-off-by: Phong LE Signed-off-by: Neil Armstrong Reviewed-by: Robert Foss --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9ae8444c96b4..313b3374a51e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9515,6 +9515,14 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ T: git git://linuxtv.org/anttip/media_tree.git F: drivers/media/tuners/it913x* +ITE IT66121 HDMI BRIDGE DRIVER +M: Phong LE +M: Neil Armstrong +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml +F: drivers/gpu/drm/bridge/ite-it66121.c + IVTV VIDEO4LINUX DRIVER M: Andy Walls L: linux-me...@vger.kernel.org -- 2.25.1
[PATCH v4 2/3] drm: bridge: add it66121 driver
From: Phong LE This commit is a simple driver for bridge HMDI it66121. The input format is RBG and there is no color conversion. Audio, HDCP and CEC are not supported yet. Signed-off-by: Phong LE Signed-off-by: Neil Armstrong --- drivers/gpu/drm/bridge/Kconfig |8 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it66121.c | 1021 ++ 3 files changed, 1030 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6ca7b3..6915c38fa459 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -74,6 +74,14 @@ config DRM_LONTIUM_LT9611UXC HDMI signals Please say Y if you have such hardware. +config DRM_ITE_IT66121 + tristate "ITE IT66121 HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + Support for ITE IT66121 HDMI bridge. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc76f8d..4f725753117c 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o +obj-$(CONFIG_DRM_ITE_IT66121) += ite-it66121.o obj-y += analogix/ obj-y += cadence/ diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c new file mode 100644 index ..d8a60691fd32 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it66121.c @@ -0,0 +1,1021 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 BayLibre, SAS + * Author: Phong LE + * Copyright (C) 2018-2019, Artem Mygaiev + * Copyright (C) 2017, Fresco Logic, Incorporated. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define IT66121_VENDOR_ID0_REG 0x00 +#define IT66121_VENDOR_ID1_REG 0x01 +#define IT66121_DEVICE_ID0_REG 0x02 +#define IT66121_DEVICE_ID1_REG 0x03 + +#define IT66121_VENDOR_ID0 0x54 +#define IT66121_VENDOR_ID1 0x49 +#define IT66121_DEVICE_ID0 0x12 +#define IT66121_DEVICE_ID1 0x06 +#define IT66121_REVISION_MASK GENMASK(7, 4) +#define IT66121_DEVICE_ID1_MASKGENMASK(3, 0) + +#define IT66121_MASTER_SEL_REG 0x10 +#define IT66121_MASTER_SEL_HOSTBIT(0) + +#define IT66121_AFE_DRV_REG0x61 +#define IT66121_AFE_DRV_RSTBIT(4) +#define IT66121_AFE_DRV_PWDBIT(5) + +#define IT66121_INPUT_MODE_REG 0x70 +#define IT66121_INPUT_MODE_RGB (0 << 6) +#define IT66121_INPUT_MODE_YUV422 BIT(6) +#define IT66121_INPUT_MODE_YUV444 (2 << 6) +#define IT66121_INPUT_MODE_CCIR656 BIT(4) +#define IT66121_INPUT_MODE_SYNCEMB BIT(3) +#define IT66121_INPUT_MODE_DDR BIT(2) + +#define IT66121_INPUT_CSC_REG 0x72 +#define IT66121_INPUT_CSC_ENDITHER BIT(7) +#define IT66121_INPUT_CSC_ENUDFILTER BIT(6) +#define IT66121_INPUT_CSC_DNFREE_GOBIT(5) +#define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 +#define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 +#define IT66121_INPUT_CSC_NO_CONV 0x00 + +#define IT66121_AFE_XP_REG 0x62 +#define IT66121_AFE_XP_GAINBIT BIT(7) +#define IT66121_AFE_XP_PWDPLL BIT(6) +#define IT66121_AFE_XP_ENI BIT(5) +#define IT66121_AFE_XP_ENO BIT(4) +#define IT66121_AFE_XP_RESETB BIT(3) +#define IT66121_AFE_XP_PWDIBIT(2) + +#define IT66121_AFE_IP_REG 0x64 +#define IT66121_AFE_IP_GAINBIT BIT(7) +#define IT66121_AFE_IP_PWDPLL BIT(6) +#define IT66121_AFE_IP_CKSEL_05(0 << 4) +#define IT66121_AFE_IP_CKSEL_1 BIT(4) +#define IT66121_AFE_IP_CKSEL_2 (2 << 4) +#define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) +#define IT66121_AFE_IP_ER0 BIT(3) +#define IT66121_AFE_IP_RESETB BIT(2) +#define IT66121_AFE_IP_ENC BIT(1) +#define IT66121_AFE_IP_EC1 BIT(0) + +#define IT66121_AFE_XP_EC1_REG 0x68 +#define IT6612
[PATCH v4 0/3] drm/bridge: Add it66121 driver
The IT66121 is a high-performance and low-power single channel HDMI transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible to DVI 1.0 specifications. It supports pixel rates from 25MHz to 165MHz. This series contains document bindings, add vendor prefix, Kconfig to enable or not. For now, the driver handles only RGB without color conversion. Audio, CEC and HDCP are not implemented yet. Changes since v3 at [2]: - DT - removed i2c reg description - used 4 spaces indent in example - added review tags - driver - added missing includes - added missing atomic bridge callbacks - dropped connector creation completely, only supports NO_CONNECTOR - moved single line helpers to inline - some more indentation cleanups - MAINTAINER - fixed order - added review tags Changes since v2 at [1]: - fixed DT bindings by: - adding bus-width property to input port - correctly defining ports - other minor fixes - fixed bridge driver by: - general cleanup following Andy's comments - implemented support for NO_CONNECTOR - makes basic usage of the bus width property - add support for bus format negociation - other minor fixes - fixed order of MAINTAINERS entries [1] https://lore.kernel.org/r/20200311125135.30832-1-...@baylibre.com [2] https://lore.kernel.org/r/20210412154648.3719153-1-narmstr...@baylibre.com Phong LE (3): dt-bindings: display: bridge: add it66121 bindings drm: bridge: add it66121 driver MAINTAINERS: add it66121 HDMI bridge driver entry .../bindings/display/bridge/ite,it66121.yaml | 124 ++ MAINTAINERS |8 + drivers/gpu/drm/bridge/Kconfig|8 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it66121.c | 1021 + 5 files changed, 1162 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c -- 2.25.1
Re: [PATCH 0/2] drm/bridge: dw-hdmi: disable loading of DW-HDMI CEC sub-driver
On 16/04/2021 11:58, Laurent Pinchart wrote: > Hi Neil, > > On Fri, Apr 16, 2021 at 11:27:35AM +0200, Neil Armstrong wrote: >> This adds DW-HDMI driver a glue option to disable loading of the CEC >> sub-driver. >> >> On some SoCs, the CEC functionality is enabled in the IP config bits, but the >> CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit is >> set >> but the DW-HDMI CEC signal is not connected to a physical pin, leading to >> some >> confusion when the DW-HDMI CEC controller can't communicate on the bus. > > If we can't trust the CEC config bit, would it be better to not use it > at all, and instead let each platform glue logic tell whether to enable > CEC or not ? Actually, the CEC config bit is right, the HW exists and should be functional, but this bit doesn't tell if the CEC signal is connected to something. This lies in the IP integration, like other bits under the "amlogic,meson-*-dw-hdmi" umbrella. The first attempt was by Hans using DT, but adding a property in DT for a vendor specific compatible doesn't make sense. Another idea would be to describe the CEC signal endpoint like we do for video signal, but I think this is out of scope and this solution is much simpler and straightforward, and it's more an exception than a general use case to solve. Neil > >> Jernej Skrabec (1): >> drm/bridge/synopsys: dw-hdmi: Add an option to suppress loading CEC >> driver >> >> Neil Armstrong (1): >> drm/meson: dw-hdmi: disable DW-HDMI CEC sub-driver >> >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- >> drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 + >> include/drm/bridge/dw_hdmi.h | 2 ++ >> 3 files changed, 4 insertions(+), 1 deletion(-) >> >
[PATCH v2] mmc: meson-gx: replace WARN_ONCE with dev_warn_once about scatterlist size alignment in block mode
Since commit e085b51c74cc ("mmc: meson-gx: check for scatterlist size alignment
in block mode"),
support for SDIO SD_IO_RW_EXTENDED transferts are properly filtered but some
driver
like brcmfmac still gives a block sg buffer size not aligned with SDIO block,
triggerring a WARN_ONCE() with scary stacktrace even if the transfer works fine
but with possible degraded performances.
Simply replace with dev_warn_once() to inform user this should be fixed to avoid
degraded performance.
This should be ultimately fixed in brcmfmac, but since it's only a performance
issue
the warning should be removed.
Fixes: e085b51c74cc ("mmc: meson-gx: check for scatterlist size alignment in
block mode")
Reported-by: Marek Szyprowski
Signed-off-by: Neil Armstrong
---
Changes since v1:
- replace WARN_ONCE with dev_warn_once and explicit the warning message
drivers/mmc/host/meson-gx-mmc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index eb6c02bc4a02..b8b771b643cc 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -247,8 +247,9 @@ static void meson_mmc_get_transfer_mode(struct mmc_host
*mmc,
*/
for_each_sg(data->sg, sg, data->sg_len, i) {
if (sg->length % data->blksz) {
- WARN_ONCE(1, "unaligned sg len %u blksize %u\n",
- sg->length, data->blksz);
+ dev_warn_once(mmc_dev(mmc),
+ "unaligned sg len %u blksize %u,
disabling descriptor DMA for transfer\n",
+ sg->length, data->blksz);
return;
}
}
--
2.25.1
Re: [PATCH] mmc: meson-gx: remove useless warning about scatterlist size alignment in block mode
On 15/04/2021 11:07, Ulf Hansson wrote:
> On Wed, 14 Apr 2021 at 12:00, Neil Armstrong wrote:
>>
>> Since commit e085b51c74cc ("mmc: meson-gx: check for scatterlist size
>> alignment in block mode"),
>> support for SDIO SD_IO_RW_EXTENDED transferts are properly filtered but some
>> driver
>> like brcmfmac still gives a block sg buffer size not aligned with SDIO block,
>> triggerring a warning even if the transfer works in degraded mode.
>>
>> This should be ultimately fixed in brcmfmac, but since it's only a
>> performance issue
>> the warning should be removed.
>>
>> Fixes: e085b51c74cc ("mmc: meson-gx: check for scatterlist size alignment in
>> block mode")
>> Reported-by: Marek Szyprowski
>> Signed-off-by: Neil Armstrong
>> ---
>> drivers/mmc/host/meson-gx-mmc.c | 5 +
>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/drivers/mmc/host/meson-gx-mmc.c
>> b/drivers/mmc/host/meson-gx-mmc.c
>> index eb6c02bc4a02..6bc151045843 100644
>> --- a/drivers/mmc/host/meson-gx-mmc.c
>> +++ b/drivers/mmc/host/meson-gx-mmc.c
>> @@ -246,11 +246,8 @@ static void meson_mmc_get_transfer_mode(struct mmc_host
>> *mmc,
>> * size, otherwise chain mode could not be used.
>> */
>> for_each_sg(data->sg, sg, data->sg_len, i) {
>> - if (sg->length % data->blksz) {
>> - WARN_ONCE(1, "unaligned sg len %u blksize
>> %u\n",
>> - sg->length, data->blksz);
>
> Rather than removing this warning, perhaps an option could be to use
> dev_warn_once() instead?
Yep, I'll re-spin.
Neil
>
>> + if (sg->length % data->blksz)
>> return;
>> - }
>> }
>> }
>>
>
> Kind regards
> Uffe
>
[PATCH 1/2] drm/bridge/synopsys: dw-hdmi: Add an option to suppress loading CEC driver
From: Jernej Skrabec
This adds DW-HDMI driver a glue option to disable loading of the CEC sub-driver.
On some SoCs, the CEC functionality is enabled in the IP config bits, but the
CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit is set
but the DW-HDMI CEC signal is not connected to a physical pin, leading to some
confusion when the DW-HDMI CEC controller can't communicate on the bus.
Reviewed-by: Neil Armstrong
Signed-off-by: Jernej Skrabec
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +-
include/drm/bridge/dw_hdmi.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index dda4fa9a1a08..ae97513ef886 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -3421,7 +3421,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device
*pdev,
hdmi->audio = platform_device_register_full();
}
- if (config0 & HDMI_CONFIG0_CEC) {
+ if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
cec.hdmi = hdmi;
cec.ops = _hdmi_cec_ops;
cec.irq = irq;
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index ea34ca146b82..6a5716655619 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -153,6 +153,8 @@ struct dw_hdmi_plat_data {
const struct dw_hdmi_phy_config *phy_config;
int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
unsigned long mpixelclock);
+
+ unsigned int disable_cec : 1;
};
struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
--
2.25.1
[PATCH 2/2] drm/meson: dw-hdmi: disable DW-HDMI CEC sub-driver
On the Amlogic SoCs, the DW-HDMI HW support is here but the DW-HDMI CEC signal is not connected to a physical pin, leading to confusion when the dw-hdmi cec controller can't communicate on the bus. Disable it to avoid exposing a non-functinal bus. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index aad75a22dc33..2ed87cfdd735 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -1103,6 +1103,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; dw_plat_data->ycbcr_420_allowed = true; + dw_plat_data->disable_cec = true; if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || -- 2.25.1
[PATCH 0/2] drm/bridge: dw-hdmi: disable loading of DW-HDMI CEC sub-driver
This adds DW-HDMI driver a glue option to disable loading of the CEC sub-driver. On some SoCs, the CEC functionality is enabled in the IP config bits, but the CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit is set but the DW-HDMI CEC signal is not connected to a physical pin, leading to some confusion when the DW-HDMI CEC controller can't communicate on the bus. Jernej Skrabec (1): drm/bridge/synopsys: dw-hdmi: Add an option to suppress loading CEC driver Neil Armstrong (1): drm/meson: dw-hdmi: disable DW-HDMI CEC sub-driver drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 + include/drm/bridge/dw_hdmi.h | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) -- 2.25.1
Re: [PATCH v3 2/3] drm: bridge: add it66121 driver
On 14/04/2021 19:35, Paul Cercueil wrote: > Hi Neil, > > Le mer. 14 avril 2021 à 8:17, Neil Armstrong a > écrit : >> Hi, >> >> Le 13/04/2021 à 22:56, Paul Cercueil a écrit : >>> Hi Neil, >>> >>> I get build failures locally: >>> >>> drivers/gpu/drm/bridge/ite-it66121.c: In function ‘it66121_hw_reset’: >>> drivers/gpu/drm/bridge/ite-it66121.c:242:2: error: implicit declaration of >>> function ‘gpiod_set_value’ [-Werror=implicit-function-declaration] >>> 242 | gpiod_set_value(ctx->gpio_reset, 1); >>> | ^~~ >>> drivers/gpu/drm/bridge/ite-it66121.c: In function ‘it66121_probe’: >>> drivers/gpu/drm/bridge/ite-it66121.c:1016:16: error: implicit declaration >>> of function ‘FIELD_GET’; did you mean ‘FOLL_GET’? >>> [-Werror=implicit-function-declaration] >>> 1016 | revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); >>> | ^ >>> | FOLL_GET >>> >>> Nothing difficult to fix, but the includes should be added nonetheless. >> >> Exact, I got the CI build failures, I'll fix these for v4. >> >> Were you able to test on your setup ? >> The v2 always forced DDR mode, with this v3, I also switch to normal 24input >> mode, but totally untested. > > It triggers a warning: > > [ 277.870247] WARNING: CPU: 0 PID: 310 at drivers/gpu/drm/drm_bridge.c:892 > drm_atomic_bridge_chain_check+0x304/0x324 > [ 277.870290] Modules linked in: > [ 277.870306] CPU: 0 PID: 310 Comm: modetest Tainted: G W > 5.12.0-rc7-opendingux-00121-g828a3020b5d3 #371 > [ 277.870322] Stack : 83f62580 80163b58 0004 b1f39d7e > 83581a9c 80ab42b0 > [ 277.870367] 808a 808a 835c82f0 808a0dab 80ab42b0 0001 > 83581a48 b1f39d7e > [ 277.870412] 807e9030 00b8 835818fc > 7875676e > [ 277.870456] 3130302d 80abaa43 80abaa9f 672d3132 808a 8000 > 0009 037c > [ 277.870500] 82a2d0f8 83043b80 fffc > 2098 80ab > [ 277.870544] ... > [ 277.870556] Call Trace: > [ 277.870560] [<80109010>] show_stack+0x40/0x128 > [ 277.870588] [<80123350>] __warn+0xe0/0x154 > [ 277.870608] [<80123428>] warn_slowpath_fmt+0x64/0xb8 > [ 277.870625] [<80504e70>] drm_atomic_bridge_chain_check+0x304/0x324 > [ 277.870642] [<804e3244>] drm_atomic_helper_check_modeset+0x9f4/0xc58 > [ 277.870667] [<804e4338>] drm_atomic_helper_check+0x20/0xa8 > [ 277.870685] [<80503644>] drm_atomic_check_only+0x538/0x98c > [ 277.870700] [<80503ab4>] drm_atomic_commit+0x1c/0x70 > [ 277.870716] [<8051c3e4>] drm_mode_atomic_ioctl+0x920/0xb44 > [ 277.870736] [<804f033c>] drm_ioctl+0x20c/0x3d8 > [ 277.870754] [<80283658>] sys_ioctl+0x358/0x860 > [ 277.870772] [<801107ec>] syscall_common+0x34/0x58 > > [ 277.870795] ---[ end trace e973f3b21c63aa1d ]--- Will fix this, Neil > > That causes my atomic commit to fail, so I can't test it further. > > Cheers, > -Paul > >> Thanks, >> Neil >> >>> >>> Cheers, >>> -Paul >>> >>> >>> Le lun. 12 avril 2021 à 17:46, Neil Armstrong a >>> écrit : >>>> From: Phong LE >>>> >>>> This commit is a simple driver for bridge HMDI it66121. >>>> The input format is RBG and there is no color conversion. >>>> Audio, HDCP and CEC are not supported yet. >>>> >>>> Signed-off-by: Phong LE >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> drivers/gpu/drm/bridge/Kconfig | 8 + >>>> drivers/gpu/drm/bridge/Makefile | 1 + >>>> drivers/gpu/drm/bridge/ite-it66121.c | 1081 ++ >>>> 3 files changed, 1090 insertions(+) >>>> create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c >>>> >>>> diff --git a/drivers/gpu/drm/bridge/Kconfig >>>> b/drivers/gpu/drm/bridge/Kconfig >>>> index e4110d6ca7b3..6915c38fa459 100644 >>>> --- a/drivers/gpu/drm/bridge/Kconfig >>>> +++ b/drivers/gpu/drm/bridge/Kconfig >>>> @@ -74,6 +74,14 @@ config DRM_LONTIUM_LT9611UXC >>>> HDMI signals >>>> Please say Y if you have such hardware. >>>> >>>> +config DRM_ITE_IT66121 >>>> + tristate "ITE IT66121 HDMI bridge" >>>> + depends on OF >>>> + sele
Re: [PATCH v3 2/3] drm: bridge: add it66121 driver
On 14/04/2021 10:16, Laurent Pinchart wrote:
> Hi Neil,
>
> On Wed, Apr 14, 2021 at 10:08:46AM +0200, Neil Armstrong wrote:
>> On 14/04/2021 10:06, Robert Foss wrote:
>>> On Wed, 14 Apr 2021 at 08:13, Neil Armstrong
>>> wrote:
>>>> Le 13/04/2021 à 22:21, Robert Foss a écrit :
>>>>> Hey Neil & Phong,
>>>>>
>>>>> Thanks for submitting this series!
>>>>>
>>>>>> +
>>>>>> +static const struct drm_bridge_funcs it66121_bridge_funcs = {
>>>>>> + .attach = it66121_bridge_attach,
>>>>>> + .enable = it66121_bridge_enable,
>>>>>> + .disable = it66121_bridge_disable,
>>>>>> + .mode_set = it66121_bridge_mode_set,
>>>>>> + .mode_valid = it66121_bridge_mode_valid,
>>>>>> + .detect = it66121_bridge_detect,
>>>>>> + .get_edid = it66121_bridge_get_edid,
>>>>>> + .atomic_get_output_bus_fmts =
>>>>>> it66121_bridge_atomic_get_output_bus_fmts,
>>>>>> + .atomic_get_input_bus_fmts =
>>>>>> it66121_bridge_atomic_get_input_bus_fmts,
>>>>>> +};
>>>>>
>>>>> I would like to see an implementation of HPD, since it is supported by
>>>>> the hardware[1] (and required by the documentation). IRQ status bit 0
>>>>> seems to be the responsible for notifying us about hot plug detection
>>>>> events.
>>>>
>>>> It's implemented in the IRQ handler with the
>>>> IT66121_INT_STATUS1_HPD_STATUS event.
>>>
>>> I didn't even get that far :)
>>>
>>> Either way, the HPD support should be exposed in drm_bridge_funcs
>>> (.hpd_enable, .hpd_disable (and possibly .hpd_notify)) and
>>> drm_bridge.ops (DRM_BRIDGE_OP_HPD).
>>
>> Indeed I forgot these calls in the NO_CONNECTOR implementation...
>
> For new bridges, you should no implement connector creation, only the
> DRM_BRIDGE_ATTACH_NO_CONNECTOR case should be supported.
>
Right, time to make a clean bridge-only implementation then !
Thanks for your feedbacks,
Neil
[PATCH] mmc: meson-gx: remove useless warning about scatterlist size alignment in block mode
Since commit e085b51c74cc ("mmc: meson-gx: check for scatterlist size alignment
in block mode"),
support for SDIO SD_IO_RW_EXTENDED transferts are properly filtered but some
driver
like brcmfmac still gives a block sg buffer size not aligned with SDIO block,
triggerring a warning even if the transfer works in degraded mode.
This should be ultimately fixed in brcmfmac, but since it's only a performance
issue
the warning should be removed.
Fixes: e085b51c74cc ("mmc: meson-gx: check for scatterlist size alignment in
block mode")
Reported-by: Marek Szyprowski
Signed-off-by: Neil Armstrong
---
drivers/mmc/host/meson-gx-mmc.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index eb6c02bc4a02..6bc151045843 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -246,11 +246,8 @@ static void meson_mmc_get_transfer_mode(struct mmc_host
*mmc,
* size, otherwise chain mode could not be used.
*/
for_each_sg(data->sg, sg, data->sg_len, i) {
- if (sg->length % data->blksz) {
- WARN_ONCE(1, "unaligned sg len %u blksize %u\n",
- sg->length, data->blksz);
+ if (sg->length % data->blksz)
return;
- }
}
}
--
2.25.1
Re: [PATCH v3 1/3] dt-bindings: display: bridge: add it66121 bindings
On 13/04/2021 18:03, Laurent Pinchart wrote:
> Hi Neil,
>
> Thank you for the patch.
>
> On Mon, Apr 12, 2021 at 05:46:46PM +0200, Neil Armstrong wrote:
>> From: Phong LE
>>
>> Add the ITE bridge HDMI it66121 bindings.
>>
>> Signed-off-by: Phong LE
>> Signed-off-by: Neil Armstrong
>> ---
>> .../bindings/display/bridge/ite,it66121.yaml | 123 ++
>> 1 file changed, 123 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
>> b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
>> new file mode 100644
>> index ..61ed6dc7740b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
>> @@ -0,0 +1,123 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: ITE it66121 HDMI bridge Device Tree Bindings
>> +
>> +maintainers:
>> + - Phong LE
>> + - Neil Armstrong
>> +
>> +description: |
>> + The IT66121 is a high-performance and low-power single channel HDMI
>> + transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward
>> compatible
>> + to DVI 1.0 specifications.
>> +
>> +properties:
>> + compatible:
>> +const: ite,it66121
>> +
>> + reg:
>> +maxItems: 1
>> +description: base I2C address of the device
>
> You can drop the description.
Done
>
>> +
>> + reset-gpios:
>> +maxItems: 1
>> +description: GPIO connected to active low reset
>> +
>> + vrf12-supply:
>> +description: Regulator for 1.2V analog core power.
>> +
>> + vcn33-supply:
>> +description: Regulator for 3.3V digital core power.
>> +
>> + vcn18-supply:
>> +description: Regulator for 1.8V IO core power.
>> +
>> + interrupts:
>> +maxItems: 1
>> +
>> + ports:
>> +$ref: /schemas/graph.yaml#/properties/ports
>> +
>> +properties:
>> + port@0:
>> +$ref: /schemas/graph.yaml#/$defs/port-base
>> +unevaluatedProperties: false
>> +description: DPI input port.
>> +
>> +properties:
>> + endpoint:
>> +$ref: /schemas/graph.yaml#/$defs/endpoint-base
>> +unevaluatedProperties: false
>> +
>> +properties:
>> + bus-width:
>> +description:
>> + Endpoint bus width.
>> +enum:
>> + - 12 # 12 data lines connected and dual-edge mode
>> + - 24 # 24 data lines connected and single-edge mode
>> +default: 24
>> +
>> + port@1:
>> +$ref: /schemas/graph.yaml#/properties/port
>> +description: HDMI Connector port.
>> +
>> +required:
>> + - port@0
>> + - port@1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reset-gpios
>> + - vrf12-supply
>> + - vcn33-supply
>> + - vcn18-supply
>> + - interrupts
>> + - ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> +i2c {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>
> It's customary to indent DT examples with 4 spaces.
Done
>
>> +
>> + it66121hdmitx: it66121hdmitx@4c {
>> +compatible = "ite,it66121";
>> +pinctrl-names = "default";
>> +pinctrl-0 = <_pins_default>;
>> +vcn33-supply = <_vcn33_wifi_reg>;
>> +vcn18-supply = <_vcn18_reg>;
>> +vrf12-supply = <_vrf12_reg>;
>> +reset-gpios = < 160 1 /* GPIO_ACTIVE_LOW */>;
>
> You can #include the necessary headers at the top of the example, and
> use GPIO_ACTIVE_LOW and IRQ_TYPE_LEVEL_LOW to replace the numerical
> values.
Done
>
> Reviewed-by: Laurent Pinchart
Thanks,
Neil
>
>> +interrupt-parent = <>;
>> +interrupts = <4 8 /* IRQ_TYPE_LEVEL_LOW */>;
>> +reg = <0x4c>;
>> +
>> +ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> +reg = <0>;
>> +it66121_in: endpoint {
>> + bus-width = <12>;
>> + remote-endpoint = <_out>;
>> +};
>> + };
>> +
>> + port@1 {
>> +reg = <1>;
>> +hdmi_conn_out: endpoint {
>> + remote-endpoint = <_conn_in>;
>> +};
>> + };
>> +};
>> + };
>> +};
>
Re: [PATCH v3 2/3] drm: bridge: add it66121 driver
On 14/04/2021 10:06, Robert Foss wrote:
> On Wed, 14 Apr 2021 at 08:13, Neil Armstrong wrote:
>>
>> Hi Rob,
>>
>> Le 13/04/2021 à 22:21, Robert Foss a écrit :
>>> Hey Neil & Phong,
>>>
>>> Thanks for submitting this series!
>>>
>>>> +
>>>> +static const struct drm_bridge_funcs it66121_bridge_funcs = {
>>>> + .attach = it66121_bridge_attach,
>>>> + .enable = it66121_bridge_enable,
>>>> + .disable = it66121_bridge_disable,
>>>> + .mode_set = it66121_bridge_mode_set,
>>>> + .mode_valid = it66121_bridge_mode_valid,
>>>> + .detect = it66121_bridge_detect,
>>>> + .get_edid = it66121_bridge_get_edid,
>>>> + .atomic_get_output_bus_fmts =
>>>> it66121_bridge_atomic_get_output_bus_fmts,
>>>> + .atomic_get_input_bus_fmts =
>>>> it66121_bridge_atomic_get_input_bus_fmts,
>>>> +};
>>>
>>> I would like to see an implementation of HPD, since it is supported by
>>> the hardware[1] (and required by the documentation). IRQ status bit 0
>>> seems to be the responsible for notifying us about hot plug detection
>>> events.
>>
>> It's implemented in the IRQ handler with the IT66121_INT_STATUS1_HPD_STATUS
>> event.
>>
>
> I didn't even get that far :)
>
> Either way, the HPD support should be exposed in drm_bridge_funcs
> (.hpd_enable, .hpd_disable (and possibly .hpd_notify)) and
> drm_bridge.ops (DRM_BRIDGE_OP_HPD).
>
Indeed I forgot these calls in the NO_CONNECTOR implementation...
Neil
Re: [PATCH v3 2/3] drm: bridge: add it66121 driver
Hi, Le 13/04/2021 à 22:56, Paul Cercueil a écrit : > Hi Neil, > > I get build failures locally: > > drivers/gpu/drm/bridge/ite-it66121.c: In function ‘it66121_hw_reset’: > drivers/gpu/drm/bridge/ite-it66121.c:242:2: error: implicit declaration of > function ‘gpiod_set_value’ [-Werror=implicit-function-declaration] > 242 | gpiod_set_value(ctx->gpio_reset, 1); > | ^~~ > drivers/gpu/drm/bridge/ite-it66121.c: In function ‘it66121_probe’: > drivers/gpu/drm/bridge/ite-it66121.c:1016:16: error: implicit declaration of > function ‘FIELD_GET’; did you mean ‘FOLL_GET’? > [-Werror=implicit-function-declaration] > 1016 | revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); > | ^ > | FOLL_GET > > Nothing difficult to fix, but the includes should be added nonetheless. Exact, I got the CI build failures, I'll fix these for v4. Were you able to test on your setup ? The v2 always forced DDR mode, with this v3, I also switch to normal 24input mode, but totally untested. Thanks, Neil > > Cheers, > -Paul > > > Le lun. 12 avril 2021 à 17:46, Neil Armstrong a > écrit : >> From: Phong LE >> >> This commit is a simple driver for bridge HMDI it66121. >> The input format is RBG and there is no color conversion. >> Audio, HDCP and CEC are not supported yet. >> >> Signed-off-by: Phong LE >> Signed-off-by: Neil Armstrong >> --- >> drivers/gpu/drm/bridge/Kconfig | 8 + >> drivers/gpu/drm/bridge/Makefile | 1 + >> drivers/gpu/drm/bridge/ite-it66121.c | 1081 ++ >> 3 files changed, 1090 insertions(+) >> create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c >> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig >> index e4110d6ca7b3..6915c38fa459 100644 >> --- a/drivers/gpu/drm/bridge/Kconfig >> +++ b/drivers/gpu/drm/bridge/Kconfig >> @@ -74,6 +74,14 @@ config DRM_LONTIUM_LT9611UXC >> HDMI signals >> Please say Y if you have such hardware. >> >> +config DRM_ITE_IT66121 >> + tristate "ITE IT66121 HDMI bridge" >> + depends on OF >> + select DRM_KMS_HELPER >> + select REGMAP_I2C >> + help >> + Support for ITE IT66121 HDMI bridge. >> + >> config DRM_LVDS_CODEC >> tristate "Transparent LVDS encoders and decoders support" >> depends on OF >> diff --git a/drivers/gpu/drm/bridge/Makefile >> b/drivers/gpu/drm/bridge/Makefile >> index 86e7acc76f8d..4f725753117c 100644 >> --- a/drivers/gpu/drm/bridge/Makefile >> +++ b/drivers/gpu/drm/bridge/Makefile >> @@ -24,6 +24,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o >> obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o >> obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o >> obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o >> +obj-$(CONFIG_DRM_ITE_IT66121) += ite-it66121.o >> >> obj-y += analogix/ >> obj-y += cadence/ >> diff --git a/drivers/gpu/drm/bridge/ite-it66121.c >> b/drivers/gpu/drm/bridge/ite-it66121.c >> new file mode 100644 >> index ..73af49b29dfa >> --- /dev/null >> +++ b/drivers/gpu/drm/bridge/ite-it66121.c >> @@ -0,0 +1,1081 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2020 BayLibre, SAS >> + * Author: Phong LE >> + * Copyright (C) 2018-2019, Artem Mygaiev >> + * Copyright (C) 2017, Fresco Logic, Incorporated. >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define IT66121_VENDOR_ID0_REG 0x00 >> +#define IT66121_VENDOR_ID1_REG 0x01 >> +#define IT66121_DEVICE_ID0_REG 0x02 >> +#define IT66121_DEVICE_ID1_REG 0x03 >> + >> +#define IT66121_VENDOR_ID0 0x54 >> +#define IT66121_VENDOR_ID1 0x49 >> +#define IT66121_DEVICE_ID0 0x12 >> +#define IT66121_DEVICE_ID1 0x06 >> +#define IT66121_REVISION_MASK GENMASK(7, 4) >> +#define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) >> + >> +#define IT66121_MASTER_SEL_REG 0x10 >> +#define IT66121_MASTER_SEL_HOST BIT(0) >> + >> +#define IT66121_AFE_DRV_REG 0x61 >> +#define IT66121_AFE_DRV_RST BIT(4) >> +#define IT6
Re: [PATCH v3 2/3] drm: bridge: add it66121 driver
Hi Rob,
Le 13/04/2021 à 22:21, Robert Foss a écrit :
> Hey Neil & Phong,
>
> Thanks for submitting this series!
>
>> +
>> +static const struct drm_bridge_funcs it66121_bridge_funcs = {
>> + .attach = it66121_bridge_attach,
>> + .enable = it66121_bridge_enable,
>> + .disable = it66121_bridge_disable,
>> + .mode_set = it66121_bridge_mode_set,
>> + .mode_valid = it66121_bridge_mode_valid,
>> + .detect = it66121_bridge_detect,
>> + .get_edid = it66121_bridge_get_edid,
>> + .atomic_get_output_bus_fmts =
>> it66121_bridge_atomic_get_output_bus_fmts,
>> + .atomic_get_input_bus_fmts =
>> it66121_bridge_atomic_get_input_bus_fmts,
>> +};
>
> I would like to see an implementation of HPD, since it is supported by
> the hardware[1] (and required by the documentation). IRQ status bit 0
> seems to be the responsible for notifying us about hot plug detection
> events.
It's implemented in the IRQ handler with the IT66121_INT_STATUS1_HPD_STATUS
event.
Neil
>
> [1] https://rockchip.fr/radxa/IT66121_Programming_Guide.v1.05.pdf
>
>
> Rob.
>
Re: [PATCH v2 1/5] dt-bindings: display: mediatek,hdmi: Convert to use graph schema
On 12/04/2021 11:39, Neil Armstrong wrote: > Update the mediatek,dpi binding to use the graph schema. > > Signed-off-by: Neil Armstrong > --- > .../display/mediatek/mediatek,cec.yaml| 51 +++ > .../display/mediatek/mediatek,hdmi-ddc.yaml | 57 > .../display/mediatek/mediatek,hdmi.txt| 136 -- > .../display/mediatek/mediatek,hdmi.yaml | 131 + > 4 files changed, 239 insertions(+), 136 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml > delete mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml > new file mode 100644 > index ..408e7dfce409 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek HDMI CEC Controller Device Tree Bindings > + > +maintainers: > + - CK Hu > + - Jitao shi > + > +description: | > + The HDMI CEC controller handles hotplug detection and CEC communication. > + > +properties: > + compatible: > +enum: > + - mediatek,mt7623-hdmi => mediatek,mt7623-cec > + - mediatek,mt8173-hdmi => mediatek,mt8173-cec > + > + reg: > +maxItems: 1 > + > + interrupts: > +maxItems: 1 > + > + clocks: > +maxItems: 1 [..] > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml > new file mode 100644 > index ..c15b3470d652 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek HDMI DDC Device Tree Bindings > + > +maintainers: > + - CK Hu > + - Jitao shi > + > +description: | > + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > + > +properties: > + compatible: > +enum: > + - mediatek,mt7623-hdmi => mediatek,mt7623-hdmi-ddc > + - mediatek,mt8173-hdmi => mediatek,mt8173-hdmi-ddc > + > + reg: > +maxItems: 1 [..] will repost with these fixes in a few days, Neil
Re: [PATCH v3 3/3] MAINTAINERS: add it66121 HDMI bridge driver entry
On 12/04/2021 17:46, Neil Armstrong wrote: > From: Phong LE > > Add Neil Armstrong and myself as maintainers > > Signed-off-by: Phong LE Obviously: Signed-off-by: Neil Armstrong > --- > MAINTAINERS | 8 > 1 file changed, 8 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9ae8444c96b4..ff6450c83049 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -9515,6 +9515,14 @@ Q: > http://patchwork.linuxtv.org/project/linux-media/list/ > T: git git://linuxtv.org/anttip/media_tree.git > F: drivers/media/tuners/it913x* > > +ITE IT66121 HDMI BRIDGE DRIVER > +M: Phong LE > +M: Neil Armstrong > +S: Maintained > +F: drivers/gpu/drm/bridge/ite-it66121.c > +T: git git://anongit.freedesktop.org/drm/drm-misc > +F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml > + > IVTV VIDEO4LINUX DRIVER > M: Andy Walls > L: linux-me...@vger.kernel.org >
[PATCH v3 2/3] drm: bridge: add it66121 driver
From: Phong LE This commit is a simple driver for bridge HMDI it66121. The input format is RBG and there is no color conversion. Audio, HDCP and CEC are not supported yet. Signed-off-by: Phong LE Signed-off-by: Neil Armstrong --- drivers/gpu/drm/bridge/Kconfig |8 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it66121.c | 1081 ++ 3 files changed, 1090 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6ca7b3..6915c38fa459 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -74,6 +74,14 @@ config DRM_LONTIUM_LT9611UXC HDMI signals Please say Y if you have such hardware. +config DRM_ITE_IT66121 + tristate "ITE IT66121 HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + Support for ITE IT66121 HDMI bridge. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc76f8d..4f725753117c 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o +obj-$(CONFIG_DRM_ITE_IT66121) += ite-it66121.o obj-y += analogix/ obj-y += cadence/ diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c new file mode 100644 index ..73af49b29dfa --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it66121.c @@ -0,0 +1,1081 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 BayLibre, SAS + * Author: Phong LE + * Copyright (C) 2018-2019, Artem Mygaiev + * Copyright (C) 2017, Fresco Logic, Incorporated. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define IT66121_VENDOR_ID0_REG 0x00 +#define IT66121_VENDOR_ID1_REG 0x01 +#define IT66121_DEVICE_ID0_REG 0x02 +#define IT66121_DEVICE_ID1_REG 0x03 + +#define IT66121_VENDOR_ID0 0x54 +#define IT66121_VENDOR_ID1 0x49 +#define IT66121_DEVICE_ID0 0x12 +#define IT66121_DEVICE_ID1 0x06 +#define IT66121_REVISION_MASK GENMASK(7, 4) +#define IT66121_DEVICE_ID1_MASKGENMASK(3, 0) + +#define IT66121_MASTER_SEL_REG 0x10 +#define IT66121_MASTER_SEL_HOSTBIT(0) + +#define IT66121_AFE_DRV_REG0x61 +#define IT66121_AFE_DRV_RSTBIT(4) +#define IT66121_AFE_DRV_PWDBIT(5) + +#define IT66121_INPUT_MODE_REG 0x70 +#define IT66121_INPUT_MODE_RGB (0 << 6) +#define IT66121_INPUT_MODE_YUV422 BIT(6) +#define IT66121_INPUT_MODE_YUV444 (2 << 6) +#define IT66121_INPUT_MODE_CCIR656 BIT(4) +#define IT66121_INPUT_MODE_SYNCEMB BIT(3) +#define IT66121_INPUT_MODE_DDR BIT(2) + +#define IT66121_INPUT_CSC_REG 0x72 +#define IT66121_INPUT_CSC_ENDITHER BIT(7) +#define IT66121_INPUT_CSC_ENUDFILTER BIT(6) +#define IT66121_INPUT_CSC_DNFREE_GOBIT(5) +#define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 +#define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 +#define IT66121_INPUT_CSC_NO_CONV 0x00 + +#define IT66121_AFE_XP_REG 0x62 +#define IT66121_AFE_XP_GAINBIT BIT(7) +#define IT66121_AFE_XP_PWDPLL BIT(6) +#define IT66121_AFE_XP_ENI BIT(5) +#define IT66121_AFE_XP_ENO BIT(4) +#define IT66121_AFE_XP_RESETB BIT(3) +#define IT66121_AFE_XP_PWDIBIT(2) + +#define IT66121_AFE_IP_REG 0x64 +#define IT66121_AFE_IP_GAINBIT BIT(7) +#define IT66121_AFE_IP_PWDPLL BIT(6) +#define IT66121_AFE_IP_CKSEL_05(0 << 4) +#define IT66121_AFE_IP_CKSEL_1 BIT(4) +#define IT66121_AFE_IP_CKSEL_2 (2 << 4) +#define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) +#define IT66121_AFE_IP_ER0 BIT(3) +#define IT66121_AFE_IP_RESETB BIT(2) +#define IT66121_AFE_IP_ENC BIT(1) +#define IT66121_AFE_IP_EC1 BIT(0) + +#define IT66121_AFE_XP_EC1_REG 0x68 +#define IT66121_AFE_XP_EC1_LOWCLK
[PATCH v3 3/3] MAINTAINERS: add it66121 HDMI bridge driver entry
From: Phong LE Add Neil Armstrong and myself as maintainers Signed-off-by: Phong LE --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9ae8444c96b4..ff6450c83049 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9515,6 +9515,14 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ T: git git://linuxtv.org/anttip/media_tree.git F: drivers/media/tuners/it913x* +ITE IT66121 HDMI BRIDGE DRIVER +M: Phong LE +M: Neil Armstrong +S: Maintained +F: drivers/gpu/drm/bridge/ite-it66121.c +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml + IVTV VIDEO4LINUX DRIVER M: Andy Walls L: linux-me...@vger.kernel.org -- 2.25.1
[PATCH v3 1/3] dt-bindings: display: bridge: add it66121 bindings
From: Phong LE
Add the ITE bridge HDMI it66121 bindings.
Signed-off-by: Phong LE
Signed-off-by: Neil Armstrong
---
.../bindings/display/bridge/ite,it66121.yaml | 123 ++
1 file changed, 123 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
new file mode 100644
index ..61ed6dc7740b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE it66121 HDMI bridge Device Tree Bindings
+
+maintainers:
+ - Phong LE
+ - Neil Armstrong
+
+description: |
+ The IT66121 is a high-performance and low-power single channel HDMI
+ transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible
+ to DVI 1.0 specifications.
+
+properties:
+ compatible:
+const: ite,it66121
+
+ reg:
+maxItems: 1
+description: base I2C address of the device
+
+ reset-gpios:
+maxItems: 1
+description: GPIO connected to active low reset
+
+ vrf12-supply:
+description: Regulator for 1.2V analog core power.
+
+ vcn33-supply:
+description: Regulator for 3.3V digital core power.
+
+ vcn18-supply:
+description: Regulator for 1.8V IO core power.
+
+ interrupts:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DPI input port.
+
+properties:
+ endpoint:
+$ref: /schemas/graph.yaml#/$defs/endpoint-base
+unevaluatedProperties: false
+
+properties:
+ bus-width:
+description:
+ Endpoint bus width.
+enum:
+ - 12 # 12 data lines connected and dual-edge mode
+ - 24 # 24 data lines connected and single-edge mode
+default: 24
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: HDMI Connector port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vrf12-supply
+ - vcn33-supply
+ - vcn18-supply
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ it66121hdmitx: it66121hdmitx@4c {
+compatible = "ite,it66121";
+pinctrl-names = "default";
+pinctrl-0 = <_pins_default>;
+vcn33-supply = <_vcn33_wifi_reg>;
+vcn18-supply = <_vcn18_reg>;
+vrf12-supply = <_vrf12_reg>;
+reset-gpios = < 160 1 /* GPIO_ACTIVE_LOW */>;
+interrupt-parent = <>;
+interrupts = <4 8 /* IRQ_TYPE_LEVEL_LOW */>;
+reg = <0x4c>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+reg = <0>;
+it66121_in: endpoint {
+ bus-width = <12>;
+ remote-endpoint = <_out>;
+};
+ };
+
+ port@1 {
+reg = <1>;
+hdmi_conn_out: endpoint {
+ remote-endpoint = <_conn_in>;
+};
+ };
+};
+ };
+};
--
2.25.1
[PATCH v3 0/3] drm/bridge: Add it66121 driver
The IT66121 is a high-performance and low-power single channel HDMI transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible to DVI 1.0 specifications. It supports pixel rates from 25MHz to 165MHz. This series contains document bindings, add vendor prefix, Kconfig to enable or not. For now, the driver handles only RGB without color conversion. Audio, CEC and HDCP are not implemented yet. Changes since v2 at [1]: - fixed DT bindings by: - adding bus-width property to input port - correctly defining ports - other minor fixes - fixed bridge driver by: - general cleanup following Andy's comments - implemented support for NO_CONNECTOR - makes basic usage of the bus width property - add support for bus format negociation - other minor fixes - fixed order of MAINTAINERS entries [1] https://lore.kernel.org/r/20200311125135.30832-1-...@baylibre.com Phong LE (3): dt-bindings: display: bridge: add it66121 bindings drm: bridge: add it66121 driver MAINTAINERS: add it66121 HDMI bridge driver entry .../bindings/display/bridge/ite,it66121.yaml | 123 ++ MAINTAINERS |8 + drivers/gpu/drm/bridge/Kconfig|8 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it66121.c | 1081 + 5 files changed, 1221 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml create mode 100644 drivers/gpu/drm/bridge/ite-it66121.c -- 2.25.1
[PATCH] media: meson-ge2d: fix rotation parameters
With these settings, 90deg and 270deg rotation leads to inverted
vertical, fix them to have correct rotation.
Fixes: 59a635327ca7 ("media: meson: Add M2M driver for the Amlogic GE2D
Accelerator Unit")
Signed-off-by: Neil Armstrong
---
drivers/media/platform/meson/ge2d/ge2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/meson/ge2d/ge2d.c
b/drivers/media/platform/meson/ge2d/ge2d.c
index 153612ca96fc..a1393fefa8ae 100644
--- a/drivers/media/platform/meson/ge2d/ge2d.c
+++ b/drivers/media/platform/meson/ge2d/ge2d.c
@@ -757,7 +757,7 @@ static int ge2d_s_ctrl(struct v4l2_ctrl *ctrl)
if (ctrl->val == 90) {
ctx->hflip = 0;
- ctx->vflip = 0;
+ ctx->vflip = 1;
ctx->xy_swap = 1;
} else if (ctrl->val == 180) {
ctx->hflip = 1;
@@ -765,7 +765,7 @@ static int ge2d_s_ctrl(struct v4l2_ctrl *ctrl)
ctx->xy_swap = 0;
} else if (ctrl->val == 270) {
ctx->hflip = 1;
- ctx->vflip = 1;
+ ctx->vflip = 0;
ctx->xy_swap = 1;
} else {
ctx->hflip = 0;
--
2.25.1
Re: [PATCH v2] staging: media: meson: vdec: declare u32 as const and static const
On 12/04/2021 14:45, Mitali Borkar wrote:
> On Mon, Apr 12, 2021 at 11:17:22AM +0200, Hans Verkuil wrote:
>> On 10/04/2021 21:59, Mitali Borkar wrote:
>>> Declared 32 bit unsigned int as static constant inside a function and
>>> replaced u32[] {x,y} as canvas1, canvas2 in codec_mpeg12.c
>>> This indicates the value of canvas indexes will remain constant throughout
>>> execution.
>>> Replaced u32 reg_base and u32 reg_name with const u32 reg_base and const
>>> u32 reg_name as it will contain data/registry bases to write static
>>> const indexes declared above and will keep track of of contiguos
>>> registers after each reg_base.
>>> This makes code look better, neater. It improves readability.
>>>
>>> Signed-off-by: Mitali Borkar
>>> ---
>>> drivers/staging/media/meson/vdec/codec_mpeg12.c | 5 +++--
>>
>> Also change drivers/staging/media/meson/vdec/codec_h264.c.
>>
>> It's a nice improvement, so let's do this for both callers of
>> amvdec_set_canvases().
>>
> I have done chnages in codec_h264.c Now, should I send that as new
> patch?
Yes please,
Neil
>
>> Regards,
>>
>> Hans
>>
>>> drivers/staging/media/meson/vdec/vdec_helpers.c | 2 +-
>>> drivers/staging/media/meson/vdec/vdec_helpers.h | 2 +-
>>> 3 files changed, 5 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/staging/media/meson/vdec/codec_mpeg12.c
>>> b/drivers/staging/media/meson/vdec/codec_mpeg12.c
>>> index 21e93a13356c..861d8584f22f 100644
>>> --- a/drivers/staging/media/meson/vdec/codec_mpeg12.c
>>> +++ b/drivers/staging/media/meson/vdec/codec_mpeg12.c
>>> @@ -65,6 +65,8 @@ static int codec_mpeg12_start(struct amvdec_session *sess)
>>> struct amvdec_core *core = sess->core;
>>> struct codec_mpeg12 *mpeg12;
>>> int ret;
>>> + static const u32 canvas1[] = { AV_SCRATCH_0, 0 };
>>> + static const u32 canvas2[] = { 8, 0 }
>>>
>>> mpeg12 = kzalloc(sizeof(*mpeg12), GFP_KERNEL);
>>> if (!mpeg12)
>>> @@ -80,8 +82,7 @@ static int codec_mpeg12_start(struct amvdec_session *sess)
>>> goto free_mpeg12;
>>> }
>>>
>>> - ret = amvdec_set_canvases(sess, (u32[]){ AV_SCRATCH_0, 0 },
>>> - (u32[]){ 8, 0 });
>>> + ret = amvdec_set_canvases(sess, canvas1, canvas2);
>>> if (ret)
>>> goto free_workspace;
>>>
>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c
>>> b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>> index 7f07a9175815..df5c27266c44 100644
>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>> @@ -177,7 +177,7 @@ static int set_canvas_nv12m(struct amvdec_session *sess,
>>> }
>>>
>>> int amvdec_set_canvases(struct amvdec_session *sess,
>>> - u32 reg_base[], u32 reg_num[])
>>> + const u32 reg_base[], const u32 reg_num[])
>>> {
>>> struct v4l2_m2m_buffer *buf;
>>> u32 pixfmt = sess->pixfmt_cap;
>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h
>>> b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>> index cfaed52ab526..ace8897c34fe 100644
>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>> @@ -17,7 +17,7 @@
>>> * @reg_num: number of contiguous registers after each reg_base (including
>>> it)
>>> */
>>> int amvdec_set_canvases(struct amvdec_session *sess,
>>> - u32 reg_base[], u32 reg_num[]);
>>> + const u32 reg_base[], const u32 reg_num[]);
>>>
>>> /* Helpers to read/write to the various IPs (DOS, PARSER) */
>>> u32 amvdec_read_dos(struct amvdec_core *core, u32 reg);
>>>
>>
[PATCH v2 2/5] dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings
Add mt8167 SoC compatible to Mediatek hdmi, hdmi-ddc and cec schema bindings. Signed-off-by: Neil Armstrong --- .../devicetree/bindings/display/mediatek/mediatek,cec.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi.yaml | 1 + 3 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml index 408e7dfce409..23e21656ca55 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml index c15b3470d652..9d7148b1a7c3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml index 9c125d7c8934..01ab0e8e02bc 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -19,6 +19,7 @@ properties: enum: - mediatek,mt2701-hdmi - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: -- 2.25.1
[PATCH v2 4/5] gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock
Some SoCs like the MT8167 have a hard limit on the maximal supported HDMI TMDS
clock, so add a configuration value to filter out those modes.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0539262e69d3..bc50d97f2553 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -149,6 +149,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
+ unsigned long max_mode_clock;
};
struct mtk_hdmi {
@@ -1226,6 +1227,10 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge
*bridge,
if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
return MODE_BAD;
+ if (hdmi->conf->max_mode_clock &&
+ mode->clock > hdmi->conf->max_mode_clock)
+ return MODE_CLOCK_HIGH;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
[PATCH v2 5/5] gpu/drm: mediatek: hdmi: add MT8167 configuration
The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
and is not validated and supported for HDMI modes out of HDMI CEA modes,
so add a configuration entry linked to the MT8167 compatible.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index bc50d97f2553..c1651a83700d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1787,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701
= {
.tz_disabled = true,
};
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
+ .max_mode_clock = 148500,
+ .cea_modes_only = true,
+};
+
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi",
.data = _hdmi_conf_mt2701,
},
+ { .compatible = "mediatek,mt8167-hdmi",
+ .data = _hdmi_conf_mt8167,
+ },
{ .compatible = "mediatek,mt8173-hdmi",
},
{}
--
2.25.1
[PATCH v2 1/5] dt-bindings: display: mediatek,hdmi: Convert to use graph schema
Update the mediatek,dpi binding to use the graph schema.
Signed-off-by: Neil Armstrong
---
.../display/mediatek/mediatek,cec.yaml| 51 +++
.../display/mediatek/mediatek,hdmi-ddc.yaml | 57
.../display/mediatek/mediatek,hdmi.txt| 136 --
.../display/mediatek/mediatek,hdmi.yaml | 131 +
4 files changed, 239 insertions(+), 136 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
delete mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
new file mode 100644
index ..408e7dfce409
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI CEC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The HDMI CEC controller handles hotplug detection and CEC communication.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt7623-hdmi
+ - mediatek,mt8173-hdmi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+cec: cec@10013000 {
+compatible = "mediatek,mt8173-cec";
+reg = <0x10013000 0xbc>;
+interrupts = ;
+clocks = < CLK_INFRA_CEC>;
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
new file mode 100644
index ..c15b3470d652
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings
+
+maintainers:
+ - CK Hu
+ - Jitao shi
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt7623-hdmi
+ - mediatek,mt8173-hdmi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+hdmi_ddc0: i2c@11012000 {
+compatible = "mediatek,mt8173-hdmi-ddc";
+reg = <0x11012000 0x1c>;
+interrupts = ;
+clocks = < CLK_PERI_I2C5>;
+clock-names = "ddc-i2c";
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
deleted file mode 100644
index b284ca51b913..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-Mediatek HDMI Encoder
-=
-
-The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
-its parallel input.
-
-Required properties:
-- compatible: Should be "mediatek,-hdmi".
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
-- phys: phandle link to the HDMI PHY node.
- See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
-- phy-names: must contain "hdmi"
-- mediatek,syscon-hdmi: phandle link and register offset to the system
- configuration registers. For mt8173 this must be offset 0x900 into the
- MMSYS_CONFIG region: < 0x900>.
-- ports: A node containing input and output port nodes with endpoint
- definitions as documented in Documentation/devicetree/bindings/graph.txt.
-- port@0: The input port in the ports node should be connected to a DPI output
- port.
-- port@1: Th
[PATCH v2 3/5] gpu/drm: mediatek: hdmi: add check for CEA modes only
Some SoCs like the MT8167 are not validated and supported for HDMI modes
out of HDMI CEA modes, so add a configuration boolean to filter out
non-CEA modes.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index dea46d66e712..0539262e69d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -148,6 +148,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
+ bool cea_modes_only;
};
struct mtk_hdmi {
@@ -1222,6 +1223,9 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge
*bridge,
return MODE_BAD;
}
+ if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
+ return MODE_BAD;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
[PATCH v2 0/5] mediatek: hdmi: add MT8167 configuration
The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock, and is not validated and supported for HDMI modes out of HDMI CEA modes. To achieve this: - switch the mediatek HDMI bindings to YAML - add the MT8167 compatible - add a boolean to discard the non-CEA modes - add a value to specify mac TMDS supported clock - add a conf entry for the MT8167 compatible Neil Armstrong (5): dt-bindings: display: mediatek,hdmi: Convert to use graph schema dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings gpu/drm: mediatek: hdmi: add check for CEA modes only gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock gpu/drm: mediatek: hdmi: add MT8167 configuration .../display/mediatek/mediatek,cec.yaml| 52 +++ .../display/mediatek/mediatek,hdmi-ddc.yaml | 58 .../display/mediatek/mediatek,hdmi.txt| 136 -- .../display/mediatek/mediatek,hdmi.yaml | 132 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +++ 5 files changed, 259 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml -- 2.25.1
Re: [PATCH] gpu/drm: mediatek: hdmi: check for valid modes on MT8167
On 10/04/2021 00:41, Chun-Kuang Hu wrote:
> Hi, Neil:
>
> Neil Armstrong 於 2021年4月9日 週五 下午4:43寫道：
>>
>> On MT8167, only CEA modes and anything using a clock below 148500 is
>> supported for HDMI. This change adds some checks to make sure the
>> video format is OK for MT8167.
>
> I think this patch should be separated to 3 patches. check CEA mode,
> check clock, add mt8167 hdmi support.
Ok
>
>>
>> Signed-off-by: Fabien Parent
>> Signed-off-by: Neil Armstrong
>> ---
>> drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
>> b/drivers/gpu/drm/mediatek/mtk_hdmi.c
>> index 8ee55f9e2954..991e2e935b93 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
>> @@ -148,6 +148,8 @@ struct hdmi_audio_param {
>>
>> struct mtk_hdmi_conf {
>> bool tz_disabled;
>> + unsigned long max_mode_clock;
>> + bool cea_modes_only;
>> };
>>
>> struct mtk_hdmi {
>> @@ -1259,6 +1261,13 @@ static int mtk_hdmi_conn_mode_valid(struct
>> drm_connector *conn,
>> return MODE_BAD;
>> }
>>
>> + if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
>> + return MODE_BAD;
>> +
>> + if (hdmi->conf->max_mode_clock &&
>> + mode->clock > hdmi->conf->max_mode_clock)
>> + return MODE_CLOCK_HIGH;
>> +
>> if (mode->clock < 27000)
>> return MODE_CLOCK_LOW;
>> if (mode->clock > 297000)
>> @@ -1810,10 +1819,18 @@ static const struct mtk_hdmi_conf
>> mtk_hdmi_conf_mt2701 = {
>> .tz_disabled = true,
>> };
>>
>> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
>> + .max_mode_clock = 148500,
>> + .cea_modes_only = true,
>> +};
>> +
>> static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
>> { .compatible = "mediatek,mt2701-hdmi",
>> .data = _hdmi_conf_mt2701,
>> },
>> + { .compatible = "mediatek,mt8167-hdmi",
>
> "mediatek,mt8167-hdmi" does not exist in binding document, so add this
> to binding document first.
> In addition, could you also transfer mediatek,hdmi.txt to yaml format?
Sure
Thanks,
Neil
>
> Regards,
> Chun-Kuang.
>
>> + .data = _hdmi_conf_mt8167,
>> + },
>> { .compatible = "mediatek,mt8173-hdmi",
>> },
>> {}
>> --
>> 2.25.1
>>
[PATCH] gpu/drm: mediatek: hdmi: check for valid modes on MT8167
On MT8167, only CEA modes and anything using a clock below 148500 is
supported for HDMI. This change adds some checks to make sure the
video format is OK for MT8167.
Signed-off-by: Fabien Parent
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 8ee55f9e2954..991e2e935b93 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -148,6 +148,8 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
+ unsigned long max_mode_clock;
+ bool cea_modes_only;
};
struct mtk_hdmi {
@@ -1259,6 +1261,13 @@ static int mtk_hdmi_conn_mode_valid(struct drm_connector
*conn,
return MODE_BAD;
}
+ if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
+ return MODE_BAD;
+
+ if (hdmi->conf->max_mode_clock &&
+ mode->clock > hdmi->conf->max_mode_clock)
+ return MODE_CLOCK_HIGH;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
@@ -1810,10 +1819,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701
= {
.tz_disabled = true,
};
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
+ .max_mode_clock = 148500,
+ .cea_modes_only = true,
+};
+
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi",
.data = _hdmi_conf_mt2701,
},
+ { .compatible = "mediatek,mt8167-hdmi",
+ .data = _hdmi_conf_mt8167,
+ },
{ .compatible = "mediatek,mt8173-hdmi",
},
{}
--
2.25.1
Re: [PATCH] thermal: amlogic: Omit superfluous error message in amlogic_thermal_probe()
On 22/02/2021 07:11, Tang Bin wrote:
> The function devm_platform_ioremap_resource has already contains error
> message, so remove the redundant dev_err here.
>
> Signed-off-by: Tang Bin
> ---
> drivers/thermal/amlogic_thermal.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/thermal/amlogic_thermal.c
> b/drivers/thermal/amlogic_thermal.c
> index ccb1fe18e..bba9f3b14 100644
> --- a/drivers/thermal/amlogic_thermal.c
> +++ b/drivers/thermal/amlogic_thermal.c
> @@ -253,10 +253,8 @@ static int amlogic_thermal_probe(struct platform_device
> *pdev)
> platform_set_drvdata(pdev, pdata);
>
> base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(base)) {
> - dev_err(dev, "failed to get io address\n");
> + if (IS_ERR(base))
> return PTR_ERR(base);
> - }
>
> pdata->regmap = devm_regmap_init_mmio(dev, base,
> pdata->data->regmap_config);
>
Reviewed-by: Neil Armstrong
Re: [PATCH 3/3] arm64: dts: meson: add initial device-tree for MeCool KIII Pro
On 29/03/2021 17:47, Christian Hewitt wrote:
> MeCool (Videostrong) KIII Pro is based on the Amlogic Q200 reference
> board with an S912 chip and the following specs:
>
> - 3GB DDR3 RAM
> - 16GB eMMC
> - 10/100/1000 Base-T Ethernet
> - BCM4335 Wireless (802.11 b/g/n/ac, BT 4.0)
> - DVB-C/T/T2/S/S2 (AVL6862TA demod + R912 tuner)
> - HDMI 2.0a video
> - S/PDIF optical output
> - CVBS/Analogue output
> - 4x USB 2.0 ports
> - IR receiver
> - 1x Power button (with integrated blue LED)
> - 1x Update/Reset button (underside)
> - 1x micro SD card slot
>
> Tested-by: Drazen Spio
> Signed-off-by: Christian Hewitt
> ---
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../dts/amlogic/meson-gxm-mecool-kiii-pro.dts | 113 ++
> 2 files changed, 114 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index f8f515c93055..a58ccecfcb55 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
> b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
> new file mode 100644
> index ..0651756d7fb5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
> @@ -0,0 +1,113 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +/*
> + * Author: Christian Hewitt
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-gxm.dtsi"
> +#include "meson-gx-p23x-q20x.dtsi"
> +#include
> +#include
> +
> +/ {
> + compatible = "videostrong,gxm-kiii-pro", "amlogic,s912",
> "amlogic,meson-gxm";
> + model = "MeCool KIII Pro";
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0xC000>;
> + };
> +
> + adc-keys {
> + compatible = "adc-keys";
> + io-channels = < 0>;
> + io-channel-names = "buttons";
> + keyup-threshold-microvolt = <171>;
> +
> + button-function {
> + label = "Update";
> + linux,code = ;
> + press-threshold-microvolt = <1>;
> + };
> + };
> +
> + gpio-keys-polled {
> + compatible = "gpio-keys-polled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + poll-interval = <100>;
> +
> + button@0 {
> + label = "power";
> + linux,code = ;
> + gpios = <_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + blue {
> + color = ;
> + function = LED_FUNCTION_POWER;
> + gpios = < GPIODV_24 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + panic-indicator;
> + };
> + };
> +};
> +
> + {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> +
> + phy-handle = <_phy>;
> +
> + amlogic,tx-delay-ns = <2>;
> +
> + phy-mode = "rgmii";
> +};
> +
> +_mdio {
> + external_phy: ethernet-phy@0 {
> + /* Realtek RTL8211F (0x001cc916) */
> + reg = <0>;
> + max-speed = <1000>;
> +
> + reset-assert-us = <1>;
> + reset-deassert-us = <8>;
> + reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
> +
> + interrupt-parent = <_intc>;
> + /* MAC_INTR on GPIOZ_15 */
> + interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> + {
> + linux,rc-map-name = "rc-mecool-kiii-pro";
> +};
> +
> +_emmc_a {
> + brcmf: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +_A {
> + status = "okay";
> + pinctrl-0 = <_a_pins>, <_a_cts_rts_pins>;
> + pinctrl-names = "default";
> + uart-has-rtscts;
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + shutdown-gpios = < GPIOX_17 GPIO_ACTIVE_HIGH>;
> + max-speed = <200>;
> + clocks = <>;
> + clock-names = "lpo";
> + };
> +};
>
Reviewed-by: Neil Armstrong
Re: [PATCH 2/3] arm64: dts: meson: add initial device-tree for MeCool KII Pro
On 29/03/2021 17:47, Christian Hewitt wrote:
> MeCool (Videostrong) KII Pro is based on the Amlogic P230 reference
> board with an S905D chip and the following specs:
>
> - 2GB DDR3 RAM
> - 16GB eMMC
> - 10/100 Base-T Ethernet
> - BCM4335 Wireless (802.11 b/g/n/ac, BT 4.0)
> - DVB-C/T/T2/S/S2 (AVL6862TA demod + R848 tuner)
> - HDMI 2.0a video
> - S/PDIF optical output
> - CVBS/Analogue output
> - 4x USB 2.0 ports
> - IR receiver
> - 1x Power button (with integrated blue LED)
> - 1x micro SD card slot
>
> Tested-by: Drazen Spio
> Signed-off-by: Christian Hewitt
> ---
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../meson-gxl-s905d-mecool-kii-pro.dts| 86 +++
> 2 files changed, 87 insertions(+)
> create mode 100644
> arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index aebd49c88719..f8f515c93055 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
> b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
> new file mode 100644
> index ..5ab5d3aa0646
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +/*
> + * Author: Christian Hewitt
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-gxl-s905d.dtsi"
> +#include "meson-gx-p23x-q20x.dtsi"
> +#include
> +#include
> +
> +/ {
> + compatible = "videostrong,gxl-kii-pro", "amlogic,s905d",
> "amlogic,meson-gxl";
> + model = "MeCool KII Pro";
> +
> + adc-keys {
> + compatible = "adc-keys";
> + io-channels = < 0>;
> + io-channel-names = "buttons";
> + keyup-threshold-microvolt = <171>;
> +
> + button-function {
> + label = "Update";
> + linux,code = ;
> + press-threshold-microvolt = <1>;
> + };
> + };
> +
> + gpio-keys-polled {
> + compatible = "gpio-keys-polled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + poll-interval = <100>;
> +
> + button@0 {
> + label = "power";
> + linux,code = ;
> + gpios = <_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + blue {
> + color = ;
> + function = LED_FUNCTION_POWER;
> + gpios = < GPIODV_24 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + panic-indicator;
> + };
> + };
> +};
> +
> + {
> + phy-mode = "rmii";
> + phy-handle = <_phy>;
> +};
> +
> + {
> + linux,rc-map-name = "rc-mecool-kii-pro";
> +};
> +
> +_emmc_a {
> + brcmf: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +_A {
> + status = "okay";
> + pinctrl-0 = <_a_pins>, <_a_cts_rts_pins>;
> + pinctrl-names = "default";
> + uart-has-rtscts;
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + shutdown-gpios = < GPIOX_17 GPIO_ACTIVE_HIGH>;
> + max-speed = <200>;
> + clocks = <>;
> + clock-names = "lpo";
> + };
> +};
>
Reviewed-by: Neil Armstrong
Re: [PATCH 3/3] arm64: dts: meson: add GPIO line names to ODROID N2/N2+
On 29/03/2021 18:12, Christian Hewitt wrote:
> From: Hyeonki Hong
>
> Add GPIO line-name identifiers to the ODROID N2/N2+ common dtsi.
>
> Signed-off-by: Hyeonki Hong
> ---
> .../dts/amlogic/meson-g12b-odroid-n2.dtsi | 45 +++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> index 139c12cf9f66..4489715fc4f3 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> @@ -446,6 +446,51 @@
> };
>
> {
> + gpio-line-names =
> + /* GPIOZ */
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + /* GPIOH */
> + "", "", "", "", "", "", "", "",
> + "",
> + /* BOOT */
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + /* GPIOC */
> + "", "", "", "", "", "", "", "",
> + /* GPIOA */
> + "PIN_44", /* GPIOA_0 */
> + "PIN_46", /* GPIOA_1 */
> + "PIN_45", /* GPIOA_2 */
> + "PIN_47", /* GPIOA_3 */
> + "PIN_26", /* GPIOA_4 */
> + "", "", "", "", "", "",
> + "PIN_42", /* GPIOA_11 */
> + "PIN_32", /* GPIOA_12 */
> + "PIN_7", /* GPIOA_13 */
> + "PIN_27", /* GPIOA_14 */
> + "PIN_28", /* GPIOA_15 */
> + /* GPIOX */
> + "PIN_16", /* GPIOX_0 */
> + "PIN_18", /* GPIOX_1 */
> + "PIN_22", /* GPIOX_2 */
> + "PIN_11", /* GPIOX_3 */
> + "PIN_13", /* GPIOX_4 */
> + "PIN_33", /* GPIOX_5 */
> + "PIN_35", /* GPIOX_6 */
> + "PIN_15", /* GPIOX_7 */
> + "PIN_19", /* GPIOX_8 */
> + "PIN_21", /* GPIOX_9 */
> + "PIN_24", /* GPIOX_10 */
> + "PIN_23", /* GPIOX_11 */
> + "PIN_8", /* GPIOX_12 */
> + "PIN_10", /* GPIOX_13 */
> + "PIN_29", /* GPIOX_14 */
> + "PIN_31", /* GPIOX_15 */
> + "PIN_12", /* GPIOX_16 */
> + "PIN_3", /* GPIOX_17 */
> + "PIN_5", /* GPIOX_18 */
> + "PIN_36"; /* GPIOX_19 */
> /*
>* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
>* to be turned high in order to be detected by the USB Controller
>
Reviewed-by: Neil Armstrong
Re: [PATCH 2/3] arm64: dts: meson: add saradc node to ODROID N2/N2+
Hi,
On 29/03/2021 18:12, Christian Hewitt wrote:
> From: Hyeonki Hong
>
> Add the meson saradc node to the ODROID N2/N2+ common dtsi.
Not sure why this is needed, does it fix something ?
Neil
>
> Signed-off-by: Hyeonki Hong
> ---
> arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> index 2f8d574c30c0..139c12cf9f66 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> @@ -508,6 +508,10 @@
> status = "okay";
> };
>
> + {
> + status = "okay";
> +};
> +
> /* SD card */
> _emmc_b {
> status = "okay";
>
Re: [PATCH 1/3] arm64: dts: meson: remove extra tab from ODROID N2/N2+ ext_mdio node
On 29/03/2021 18:12, Christian Hewitt wrote:
> Remove an extra tab from the ext_mdio node in the ODROID N2/N2+ common
> dtsi file.
>
> Signed-off-by: Christian Hewitt
> ---
> arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> index 58ce569b2ace..2f8d574c30c0 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
> @@ -410,7 +410,7 @@
>
> _mdio {
> external_phy: ethernet-phy@0 {
> - /* Realtek RTL8211F (0x001cc916) */
> + /* Realtek RTL8211F (0x001cc916) */
> reg = <0>;
> max-speed = <1000>;
>
>
Reviewed-by: Neil Armstrong
[PATCH v2 3/3] arm64: dts: meson: set 128bytes FIFO size on uart A
The first UART controller in "Everything-Else" power domain, usually used
for Bluetooth HCI has 128bytes FIFO depth.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 1 +
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d945c84ab697..db3dae932a08 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1872,6 +1872,7 @@ uart_A: serial@24000 {
status = "disabled";
clocks = <>, < CLKID_UART0>, <>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index b858c5e43cc8..4f5b85ad3120 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2311,6 +2311,7 @@ uart_A: serial@24000 {
clocks = <>, < CLKID_UART0>, <>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 0edd137151f8..8eae0b7d1642 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -295,6 +295,7 @@ uart_A: serial@84c0 {
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
--
2.25.1
[PATCH v2 2/3] tty: serial: meson: retrieve port FIFO size from DT
Now the DT bindings has a property to get the FIFO size for a particular port,
retrieve it and use to setup the FIFO interrupts threshold.
Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
---
drivers/tty/serial/meson_uart.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
index 69eeef9edfa5..ce4dbfb0bd24 100644
--- a/drivers/tty/serial/meson_uart.c
+++ b/drivers/tty/serial/meson_uart.c
@@ -717,6 +717,7 @@ static int meson_uart_probe(struct platform_device *pdev)
{
struct resource *res_mem, *res_irq;
struct uart_port *port;
+ u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */
int ret = 0;
int id = -1;
@@ -743,6 +744,8 @@ static int meson_uart_probe(struct platform_device *pdev)
if (!res_irq)
return -ENODEV;
+ of_property_read_u32(pdev->dev.of_node, "fifo-size", );
+
if (meson_ports[pdev->id]) {
dev_err(>dev, "port %d already allocated\n", pdev->id);
return -EBUSY;
@@ -772,7 +775,7 @@ static int meson_uart_probe(struct platform_device *pdev)
port->type = PORT_MESON;
port->x_char = 0;
port->ops = _uart_ops;
- port->fifosize = 64;
+ port->fifosize = fifosize;
meson_ports[pdev->id] = port;
platform_set_drvdata(pdev, port);
--
2.25.1
[PATCH v2 1/3] dt-bindings: serial: amlogic,meson-uart: add fifo-size property
On most of the Amlogic SoCs, the first UART controller in the "Everything-Else" power domain has 128bytes of RX & TX FIFO, so add an optional property to describe a different FIFO size from the other ports (64bytes). Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- .../devicetree/bindings/serial/amlogic,meson-uart.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 75ebc9952a99..8ece7f420c19 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -55,6 +55,12 @@ properties: - const: pclk - const: baud + + fifo-size: +description: The fifo size supported by the UART channel. +$ref: /schemas/types.yaml#/definitions/uint32 +enum: [64, 128] + required: - compatible - reg -- 2.25.1
[PATCH v2 0/3] tty: serial: meson: add amlogic,uart-fifosize property
On most of the Amlogic SoCs, the first UART controller in the "Everything-Else" power domain has 128bytes of RX & TX FIFO, so add an optional property to describe a different FIFO size from the other ports (64bytes). This adds a property in the bindings, reads the property from the driver and updates the DT with the new property. Changes since v1: - switched to a more generic "fifo-size" Neil Armstrong (3): dt-bindings: serial: amlogic,meson-uart: add fifo-size property tty: serial: meson: retrieve port FIFO size from DT arm64: dts: meson: set 128bytes FIFO size on uart A .../devicetree/bindings/serial/amlogic,meson-uart.yaml | 6 ++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + drivers/tty/serial/meson_uart.c | 5 - 5 files changed, 13 insertions(+), 1 deletion(-) -- 2.25.1
Re: [PATCH v1] MAINTAINERS: Update Maintainers of DRM Bridge Drivers
Hi ! On 24/03/2021 11:20, Robert Foss wrote: > Add myself as co-maintainer of DRM Bridge Drivers. Repository > commit access has already been granted. > > https://gitlab.freedesktop.org/freedesktop/freedesktop/-/issues/338 > > Cc: Neil Armstrong > Cc: Laurent Pinchart > Cc: Jonas Karlman > Cc: Andrzej Hajda > Cc: Jernej Škrabec > Cc: Daniel Vetter > Signed-off-by: Robert Foss + CC: dri-de...@lists.freedesktop.org > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 4b705ba51c54..16ace8f58649 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5902,6 +5902,7 @@ F: drivers/gpu/drm/atmel-hlcdc/ > DRM DRIVERS FOR BRIDGE CHIPS > M: Andrzej Hajda > M: Neil Armstrong > +M: Robert Foss > R: Laurent Pinchart > R: Jonas Karlman > R: Jernej Skrabec > Acked-by: Neil Armstrong Welcome to the team, help is needed ! Neil
Re: [PATCH] drm/meson: Fix few typo
On 18/03/2021 12:00, Bhaskar Chowdhury wrote: > > s/initialy/initially/ > s/desined/designed/ > > Signed-off-by: Bhaskar Chowdhury > --- > drivers/gpu/drm/meson/meson_venc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/meson/meson_venc.c > b/drivers/gpu/drm/meson/meson_venc.c > index 5e2236ec189f..3c55ed003359 100644 > --- a/drivers/gpu/drm/meson/meson_venc.c > +++ b/drivers/gpu/drm/meson/meson_venc.c > @@ -45,7 +45,7 @@ > * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC > * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. > * The ENCP is designed for Progressive encoding but can also generate > - * 1080i interlaced pixels, and was initialy desined to encode pixels for > + * 1080i interlaced pixels, and was initially designed to encode pixels for > * VDAC to output RGB ou YUV analog outputs. > * It's output is only used through the ENCP_DVI encoder for HDMI. > * The ENCL LVDS encoder is not implemented. > -- > 2.26.2 > Thanks, Applied to drm-misc-next Neil
[PATCH 1/3] dt-bindings: serial: amlogic,meson-uart: add amlogic,uart-fifosize property
On most of the Amlogic SoCs, the first UART controller in the "Everything-Else" power domain has 128bytes of RX & TX FIFO, so add an optional property to describe a different FIFO size from the other ports (64bytes). Signed-off-by: Neil Armstrong --- .../devicetree/bindings/serial/amlogic,meson-uart.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 75ebc9952a99..e0a742112783 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -55,6 +55,12 @@ properties: - const: pclk - const: baud + + amlogic,uart-fifosize: +description: The fifo size supported by the UART channel. +$ref: /schemas/types.yaml#/definitions/uint32 +enum: [64, 128] + required: - compatible - reg -- 2.25.1
[PATCH 3/3] arm64: dts: meson: set 128bytes FIFO size on uart A
The first UART controller in "Everything-Else" power domain, usually used
for Bluetooth HCI has 128bytes FIFO depth.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 1 +
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d945c84ab697..571383c12855 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1872,6 +1872,7 @@ uart_A: serial@24000 {
status = "disabled";
clocks = <>, < CLKID_UART0>, <>;
clock-names = "xtal", "pclk", "baud";
+ amlogic,uart-fifosize = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index b858c5e43cc8..9e898479f118 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2311,6 +2311,7 @@ uart_A: serial@24000 {
clocks = <>, < CLKID_UART0>, <>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ amlogic,uart-fifosize = <128>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 0edd137151f8..bd0b049787fd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -295,6 +295,7 @@ uart_A: serial@84c0 {
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
+ amlogic,uart-fifosize = <128>;
};
uart_B: serial@84dc {
--
2.25.1
[PATCH 2/3] tty: serial: meson: retrieve port FIFO size from DT
Now the DT bindings has a property to get the FIFO size for a particular port,
retrieve it and use to setup the FIFO interrupts threshold.
Signed-off-by: Neil Armstrong
---
drivers/tty/serial/meson_uart.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
index 69eeef9edfa5..7244b12aefab 100644
--- a/drivers/tty/serial/meson_uart.c
+++ b/drivers/tty/serial/meson_uart.c
@@ -717,6 +717,7 @@ static int meson_uart_probe(struct platform_device *pdev)
{
struct resource *res_mem, *res_irq;
struct uart_port *port;
+ u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */
int ret = 0;
int id = -1;
@@ -743,6 +744,8 @@ static int meson_uart_probe(struct platform_device *pdev)
if (!res_irq)
return -ENODEV;
+ of_property_read_u32(pdev->dev.of_node, "amlogic,uart-fifosize",
);
+
if (meson_ports[pdev->id]) {
dev_err(>dev, "port %d already allocated\n", pdev->id);
return -EBUSY;
@@ -772,7 +775,7 @@ static int meson_uart_probe(struct platform_device *pdev)
port->type = PORT_MESON;
port->x_char = 0;
port->ops = _uart_ops;
- port->fifosize = 64;
+ port->fifosize = fifosize;
meson_ports[pdev->id] = port;
platform_set_drvdata(pdev, port);
--
2.25.1
[PATCH 0/3] tty: serial: meson: add amlogic,uart-fifosize property
On most of the Amlogic SoCs, the first UART controller in the "Everything-Else" power domain has 128bytes of RX & TX FIFO, so add an optional property to describe a different FIFO size from the other ports (64bytes). This adds a property in the bindings, reads the property from the driver and updates the DT with the new property. Neil Armstrong (3): dt-bindings: serial: amlogic,meson-uart: add amlogic,uart-fifosize property tty: serial: meson: retrieve port FIFO size from DT arm64: dts: meson: set 128bytes FIFO size on uart A .../devicetree/bindings/serial/amlogic,meson-uart.yaml | 6 ++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + drivers/tty/serial/meson_uart.c | 5 - 5 files changed, 13 insertions(+), 1 deletion(-) -- 2.25.1
