[PATCH v4 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
Add the compatibles for Variscite i.MX6UL compatibles Signed-off-by: Oliver Graute --- Changelog: v4: - added missing 6 in i.MX6 v3: - rebased v2: - renamed binding - removed superflous " Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f..e67b622 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -499,6 +499,7 @@ properties: - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi + - variscite,imx6ul-var-6ulcustomboard # i.MX6 UltraLite Carrier-board - const: fsl,imx6ul - description: i.MX6UL Armadeus Systems OPOS6UL SoM Board -- 2.7.4
[PATCH v9 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
Cc: Parthiban Nallathambi
---
Changelog:
v9:
- removed display-timing node
- added 5V power supply for display
- added assigned clocks for display
v8:
- backlight droped the status line
- port the display panel
- added pinctrl for touch
v7:
- fixed wakeup-source
v6:
- added some muxing
- added codec in sound node
- added adc1 node
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 255
2 files changed, 256 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ce66ffd..9f72446 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -626,6 +626,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index ..bf1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2021 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
+
+ backlight_lcd: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ panel1: panel-lcd {
+ compatible = "sgd,gktw70sdad1sd";
+
+ backlight = <&backlight_lcd>;
+ label = "gktw70sdad1sd";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,frame-master = <&codec_dai>;
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8731>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ statu
[PATCH v9 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
Cc: Parthiban Nallathambi
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 314 +
1 file changed, 314 insertions(+)
Changelog:
v9:
- added 3V and 5V regulator
- move phy reset to subnode
- added pwm-cells
- fixed pad pin conflict
v8:
- remove can node
- remove flexscan pinctrl
- moved lcd and i2c pinctrl
- sorted regulators
- add dedicated pinctrl for dvfs regulator
v7:
- removed cpu0 node
- fixed phy problem
v6:
- renamed touch regulator
- renamed rmii clock
- moved some muxing to baseboard
- added pinctrl for gpio key
- added bus-width to usdhc1
- fixed missing subnode on partitions
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index ..b95fdc5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ clk_rmii_ref: clock-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvfs_reg>;
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ enable-active-high;
+ states = <130 0x1 140 0x0>;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_touch_3v3: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+};
+
+&adc1 {
+ vref-supply = <®_touch_3v3>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reset-names = "phy";
+ reset-gpios=<&gpio5 10 1>;
+ reset-assert-us = <100>;
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ pinctrl-names = "default";
+ pinctr
[PATCH v9 0/3] Variscite DART-6UL SoM support
This patch series adds support for the Variscite DART-6UL SoM Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (3): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles Documentation/devicetree/bindings/arm/fsl.yaml | 1 + arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 314 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 255 + 4 files changed, 604 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
[PATCH v4] drm/panel: simple: add SGD GKTW70SDAD1SD
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
Reviewed-by: Marco Felsch
Reviewed-by: Fabio Estevam
---
v4:
- added the datasheet labels
- added Reviewed-by
v3:
- added flags
- added delay
v2:
- changed bpc to 6
- set max value of pixelclock
- increased hfront_porch and hback_porch
- dropped connector-type
adding of bus_format = MEDIA_BUS_FMT_RGB666_1X18 results in wrong colors.
omitting bus_format and using some default is better (Tux Pinguin is colored
fine)
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 2be358f..c63f6a8 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3336,6 +3336,36 @@ static const struct panel_desc satoz_sat050at40h12r2 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing sgd_gktw70sdad1sd_timing = {
+ .pixelclock = {3000, 3000, 4000},
+ .hactive = { 800, 800, 800},
+ .hfront_porch = {40, 40, 40},
+ .hback_porch = {40, 40, 40},
+ .hsync_len = {48, 48, 48},
+ .vactive = {480, 480, 480},
+ .vfront_porch = {13, 13, 13},
+ .vback_porch = {29, 29, 29},
+ .vsync_len = {3, 3, 3},
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+ DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+};
+
+static const struct panel_desc sgd_gktw70sdad1sd = {
+ .timings = &sgd_gktw70sdad1sd_timing,
+ .num_timings = 1,
+ .bpc = 6,
+ .size = {
+ .width = 153,
+ .height = 86,
+ },
+ .delay = {
+ .prepare = 20 + 20 + 10 + 10, /* T0 + T2 + T3 + T4 */
+ .enable = 50, /* T5 */
+ .disable = 50, /* T5 */
+ .unprepare = 10 + 10 + 20 + 20, /* T4 + T3 + T2 + T0 */
+ },
+};
+
static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
.clock = 168480,
.hdisplay = 1920,
@@ -4222,6 +4252,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "satoz,sat050at40h12r2",
.data = &satoz_sat050at40h12r2,
}, {
+ .compatible = "sgd,gktw70sdad1sd",
+ .data = &sgd_gktw70sdad1sd,
+ }, {
.compatible = "sharp,ld-d5116z01b",
.data = &sharp_ld_d5116z01b,
}, {
--
2.7.4
Re: [PATCH v3] drm/panel: simple: add SGD GKTW70SDAD1SD
On 02/02/21, Marco Felsch wrote: > Hi Oliver, > > On 21-02-02 18:35, Oliver Graute wrote: > > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD > > to panel-simple. > > > > The panel spec from Variscite can be found at: > > https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf > > > > Signed-off-by: Oliver Graute > > Cc: Marco Felsch > > Cc: Fabio Estevam > > --- > > > > v3: > > > > - added flags > > - added delay > > Thanks, did you test the changes? > I just picked it from the datasheet. yes, it didn't break anything. Best regards, Oliver
[PATCH v3] drm/panel: simple: add SGD GKTW70SDAD1SD
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
Cc: Marco Felsch
Cc: Fabio Estevam
---
v3:
- added flags
- added delay
v2:
- changed bpc to 6
- set max value of pixelclock
- increased hfront_porch and hback_porch
- dropped connector-type
adding of bus_format = MEDIA_BUS_FMT_RGB666_1X18 results in wrong colors.
omitting bus_format and using some default is better (Tux Pinguin is colored
fine)
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 2be358f..c63f6a8 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3336,6 +3336,36 @@ static const struct panel_desc satoz_sat050at40h12r2 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing sgd_gktw70sdad1sd_timing = {
+ .pixelclock = {3000, 3000, 4000},
+ .hactive = { 800, 800, 800},
+ .hfront_porch = {40, 40, 40},
+ .hback_porch = {40, 40, 40},
+ .hsync_len = {48, 48, 48},
+ .vactive = {480, 480, 480},
+ .vfront_porch = {13, 13, 13},
+ .vback_porch = {29, 29, 29},
+ .vsync_len = {3, 3, 3},
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+ DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+};
+
+static const struct panel_desc sgd_gktw70sdad1sd = {
+ .timings = &sgd_gktw70sdad1sd_timing,
+ .num_timings = 1,
+ .bpc = 6,
+ .size = {
+ .width = 153,
+ .height = 86,
+ },
+ .delay = {
+ .prepare = 20 + 20 + 10 + 10,
+ .enable = 50,
+ .disable = 50,
+ .unprepare = 10 + 10 + 20 + 20,
+ },
+};
+
static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
.clock = 168480,
.hdisplay = 1920,
@@ -4222,6 +4252,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "satoz,sat050at40h12r2",
.data = &satoz_sat050at40h12r2,
}, {
+ .compatible = "sgd,gktw70sdad1sd",
+ .data = &sgd_gktw70sdad1sd,
+ }, {
.compatible = "sharp,ld-d5116z01b",
.data = &sharp_ld_d5116z01b,
}, {
--
2.7.4
Re: [PATCH v2] drm/panel: simple: add SGD GKTW70SDAD1SD
On 01/02/21, Marco Felsch wrote:
> Hi Oliver,
>
> thanks for the patch :)
>
> On 21-01-29 20:09, Oliver Graute wrote:
> > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
> > to panel-simple.
> >
> > The panel spec from Variscite can be found at:
> > https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
> >
> > Signed-off-by: Oliver Graute
> > Cc: Marco Felsch
> > Cc: Fabio Estevam
> > ---
> >
> > v2:
> >
> > - changed bpc to 6
> > - set max value of pixelclock
> > - increased hfront_porch and hback_porch
> > - dropped connector-type
> >
> > adding of bus_format = MEDIA_BUS_FMT_RGB666_1X18 results in wrong colors.
> > omitting bus_format and using some default is good (Tux Pinguin is colored
> > fine)
> >
> > drivers/gpu/drm/panel/panel-simple.c | 26 ++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
> > b/drivers/gpu/drm/panel/panel-simple.c
> > index 2be358f..c129a8c 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -3336,6 +3336,28 @@ static const struct panel_desc satoz_sat050at40h12r2
> > = {
> > .connector_type = DRM_MODE_CONNECTOR_LVDS,
> > };
> >
> > +static const struct display_timing sgd_gktw70sdad1sd_timing = {
> > + .pixelclock = {3000, 3000, 4000},
> > + .hactive = { 800, 800, 800},
> > + .hfront_porch = {40, 40, 40},
> > + .hback_porch = {40, 40, 40},
> > + .hsync_len = {48, 48, 48},
> > + .vactive = {480, 480, 480},
> > + .vfront_porch = {13, 13, 13},
> > + .vback_porch = {29, 29, 29},
> > + .vsync_len = {3, 3, 3},
>
> Please add also:
>
> .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
>DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
ok will do
>
> > +};
> > +
> > +static const struct panel_desc sgd_gktw70sdad1sd = {
> > + .timings = &sgd_gktw70sdad1sd_timing,
> > + .num_timings = 1,
> > + .bpc = 6,
> > + .size = {
> > + .width = 153,
> > + .height = 86,
> > + },
>
> and:
>
> .delay = {
> .prepare = 20 + 20 + 10 + 10, /* T0 + T2 + T3 + T4 */
> .enable = 50, /* T5 */
> .disable = 50, /* T5 */
> .unprepare = 10 + 10 + 20 + 20, /* T4 + T3 + T2 + T0 */
> };
ok will do
thx for your review.
Best regards,
Oliver
[PATCH v2] drm/panel: simple: add SGD GKTW70SDAD1SD
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
Cc: Marco Felsch
Cc: Fabio Estevam
---
v2:
- changed bpc to 6
- set max value of pixelclock
- increased hfront_porch and hback_porch
- dropped connector-type
adding of bus_format = MEDIA_BUS_FMT_RGB666_1X18 results in wrong colors.
omitting bus_format and using some default is good (Tux Pinguin is colored
fine)
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 2be358f..c129a8c 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3336,6 +3336,28 @@ static const struct panel_desc satoz_sat050at40h12r2 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing sgd_gktw70sdad1sd_timing = {
+ .pixelclock = {3000, 3000, 4000},
+ .hactive = { 800, 800, 800},
+ .hfront_porch = {40, 40, 40},
+ .hback_porch = {40, 40, 40},
+ .hsync_len = {48, 48, 48},
+ .vactive = {480, 480, 480},
+ .vfront_porch = {13, 13, 13},
+ .vback_porch = {29, 29, 29},
+ .vsync_len = {3, 3, 3},
+};
+
+static const struct panel_desc sgd_gktw70sdad1sd = {
+ .timings = &sgd_gktw70sdad1sd_timing,
+ .num_timings = 1,
+ .bpc = 6,
+ .size = {
+ .width = 153,
+ .height = 86,
+ },
+};
+
static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
.clock = 168480,
.hdisplay = 1920,
@@ -4222,6 +4244,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "satoz,sat050at40h12r2",
.data = &satoz_sat050at40h12r2,
}, {
+ .compatible = "sgd,gktw70sdad1sd",
+ .data = &sgd_gktw70sdad1sd,
+ }, {
.compatible = "sharp,ld-d5116z01b",
.data = &sharp_ld_d5116z01b,
}, {
--
2.7.4
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 26/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Mon, Jan 25, 2021 at 7:17 PM Oliver Graute wrote: > > > I would prefer mine, because I got a wrong colored penguin on bootup > > with yours :-) The wrong colored Tux is caused by the bus_format: .bus_format = MEDIA_BUS_FMT_RGB888_1X24, So I assume I need another bus_format here. > > I have originally passed .bpc = 8, but looking at the panel datasheet, > this should be: > .bpc = 6 instead. yes this is right. I found it too in the datasheet. I'll fix it in next version of the patch. > > In your patch, you pass the timing parameters three times, but they > are all the same. > > Usually, it is meant to be: minimal, typical, maximum values. yes because on a lot of entries there is just the typical value and no min and max. But not on all of them. Best regards, Oliver
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 16/01/21, Fabio Estevam wrote: > On Sat, Jan 16, 2021 at 9:49 AM Oliver Graute wrote: > > > > power-supply = <®_touch_3v3> is not correct, as the reg_touch_3v3 > > > does not power the LCD. > > > > yes, but how is the LCD correctly powered then? > > J4 is powered by VCC_5V and VCC_3V#. > > > [7.795980] pwm-backlight backlight: supply power not found, using dummy > > regulator > > [7.804436] OF: /backlight: #pwm-cells = 3 found -1 > > [7.806563] of_pwm_get(): can't parse "pwms" property > > [7.812026] pwm-backlight backlight: unable to request PWM > > [7.822929] pwm-backlight: probe of backlight failed with error -22 > > You need to fix this. > > > [7.876831] imx-sdma 20ec000.sdma: Direct firmware load for > > imx/sdma/sdma-imx6q.bin failed with error -2 > > [7.884231] imx-sdma 20ec000.sdma: Falling back to sysfs fallback for: > > imx/sdma/sdma-imx6q.bin > > [7.916013] printk: console [ttymxc0] enabled > > [7.916013] printk: console [ttymxc0] enabled > > [7.922351] printk: bootconsole [ec_imx6q0] disabled > > [7.922351] printk: bootconsole [ec_imx6q0] disabled > > [7.952397] 21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 68, > > base_baud = 500) is a IMX > > [7.970794] 21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 69, > > base_baud = 500) is a IMX > > [8.033015] [ cut here ] > > [8.037826] WARNING: CPU: 0 PID: 1 at > > ../drivers/gpu/drm/panel/panel-simple.c:577 panel_simple_probe+0x5dc/0x6b8 > > And this too > > > [8.846104] imx6ul-pinctrl 20e.pinctrl: pin MX6UL_PAD_NAND_CE0_B > > already requested by regulator-gpio; cannot claim for > > 1806000.nand-controller > > [8.859641] imx6ul-pinctrl 20e.pinctrl: pin-107 > > (1806000.nand-controller) status -22 > > [8.867851] imx6ul-pinctrl 20e.pinctrl: could not request pin 107 > > (MX6UL_PAD_NAND_CE0_B) from group gpminandgrp on device 20e.pinctrl > > [8.880930] gpmi-nand 1806000.nand-controller: Error applying setting, > > reverse things back > > [8.889726] gpmi-nand: probe of 1806000.nand-controller failed with > > error -22 > > And this pin conflict too. Ok I fixed the pin conflict with regulator-gpio and added a 5V regulator node in my dts file. Now the display is working fine! I'll post the dts files soon and check if there is something to improve for this patch. Many thanks for your help, Oliver
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 25/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Mon, Jan 25, 2021 at 6:29 PM Oliver Graute wrote: > > > Ok I fixed the pin conflict with regulator-gpio and added a 5V > > regulator node in my dts file. Now the display is working fine! > > That's good news :-) > > > I'll post the dts files soon and check if there is something to > > improve for this patch. > > Did the panel patch I sent earlier work? > https://pastebin.com/raw/diTMVsh8 > > If it does, I can send it formally if you want. I would prefer mine, because I got a wrong colored penguin on bootup with yours :-) Best regards, Oliver
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 10/01/21, Fabio Estevam wrote: > On Sun, Jan 10, 2021 at 5:09 PM Oliver Graute wrote: > > > here the schematics and my dts. The board is using a LVDS connector for > > the display. > > The schematics shows the GKTW70SDAD1SD panel in the J4 connector, not > the LVDS J7 connector. yes you are right. But how to I map this fact correctly in my dts? > > https://www.variscite.de/wp-content/uploads/2017/12/VAR-6ULCustomboard-Schematics.pdf > > https://lore.kernel.org/linux-arm-kernel/1610144511-19018-3-git-send-email-oliver.gra...@gmail.com/ > > As I mentioned earlier you should remove the display timings from the > dts when using the compatible string for the panel. I got this and removed the display timings. > > power-supply = <®_touch_3v3> is not correct, as the reg_touch_3v3 > does not power the LCD. yes, but how is the LCD correctly powered then? > > Another hint is to use the PLL5_VIDEO as the clock source for the > lcdif controller as done in the imx6ul evk dtsi. I already figured it out and tried it. But because of the faults above it didn't make any difference. > > It would also help if you could share the complete boot log. here is the boot log Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 5.10.0-test-6-gc24ef7716d4b (oliver@ripley) (arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609, GNU ld (GNU Binutils for Ubuntu) 2.26.1) #1 SMP Sat Jan 16 13:28:37 CET 2021 [0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [0.00] CPU: div instructions available: patching division code [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] OF: fdt: Machine model: Variscite i.MX6 UltraLite Carrier-board [0.00] earlycon: ec_imx6q0 at MMIO 0x0202 (options '') [0.00] printk: bootconsole [ec_imx6q0] enabled [0.00] Memory policy: Data cache writealloc [0.00] cma: Reserved 64 MiB at 0x9c00 [0.00] Zone ranges: [0.00] Normal [mem 0x8000-0x9fff] [0.00] HighMem empty [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x8000-0x9fff] [0.00] Initmem setup node 0 [mem 0x8000-0x9fff] [0.00] percpu: Embedded 18 pages/cpu s51692 r0 d22036 u73728 [0.00] Built 1 zonelists, mobility grouping on. Total pages: 130048 [0.00] Kernel command line: console=ttymxc0,115200,115200 root=/dev/nfs ip=dhcp nfsroot=192.168.3.13:/volume1/nfs/rootfs/,v3,tcp rw earlycon [0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear) [0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear) [0.00] mem auto-init: stack:off, heap alloc:off, heap free:off [0.00] Memory: 422620K/524288K available (16384K kernel code, 2090K rwdata, 4636K rodata, 1024K init, 6680K bss, 36132K reserved, 65536K cma-reserved, 0K highmem) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] rcu: Hierarchical RCU implementation. [0.00] rcu: RCU event tracing is enabled. [0.00] rcu: RCU lockdep checking is enabled. [0.00] rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1. [0.00] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. [0.00] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 [0.00] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 [0.00] random: get_random_bytes called from start_kernel+0x350/0x570 with crng_init=0 [0.00] Switching to timer-based delay loop, resolution 41ns [0.23] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns [0.007847] clocksource: mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 79635851949 ns [0.021360] Console: colour dummy device 80x30 [0.023088] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.031763] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.034908] ... MAX_LOCK_DEPTH: 48 [0.039082] ... MAX_LOCKDEP_KEYS:8192 [0.043532] ... CLASSHASH_SIZE: 4096 [0.047784] ... MAX_LOCKDEP_ENTRIES: 32768 [0.052216] ... MAX_LOCKDEP_CHAINS: 65536 [0.056739] ... CHAINHASH_SIZE: 32768 [0.061095] memory used by lock dependency info: 4061 kB [0.066484] memory used for stack traces: 2112 kB [0.071350] per task-struct memory footprint: 1536 bytes [0.076832] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=24) [0.087133] pid_max: default: 32768 minimum: 301 [
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 10/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Sun, Jan 10, 2021 at 12:35 PM Oliver Graute > wrote: > > > the first two errors are gone. But I still get this: > > > > [ 42.387107] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 > > > > The panel is still off perhaps I miss something else. > > Some suggestions: > > - Take a look at arch/arm/boot/dts/imx6ul-14x14-evk.dtsi as a > reference as it has display functional > - Use imx_v6_v7_defconfig to make sure all the required drivers are selected ok I checked imx6ul-14x14-evk.dtsi and use imx_v6_v7_defconfig > - If it still does not work, share the dts and schematics here the schematics and my dts. The board is using a LVDS connector for the display. https://www.variscite.de/wp-content/uploads/2017/12/VAR-6ULCustomboard-Schematics.pdf https://lore.kernel.org/linux-arm-kernel/1610144511-19018-3-git-send-email-oliver.gra...@gmail.com/ Thx for your help, Best Regards, Oliver
Re: [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
On 09/01/21, Fabio Estevam wrote:
> On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute wrote:
>
> > + panel1: panel-lcd {
> > + compatible = "sgd,gktw70sdad1sd";
> > +
> > + backlight = <&backlight_lcd>;
> > + power-supply = <®_touch_3v3>;
> > + label = "gktw70sdad1sd";
> > +
> > + display-timing {
>
> If you pass the compatible, then you don't need to add the
> display-timing in the device tree.
thx I`ll drop it
Best Regards,
Oliver
Re: [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
On 09/01/21, Fabio Estevam wrote: > On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute wrote: > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml > > b/Documentation/devicetree/bindings/arm/fsl.yaml > > index 05906e2..5f74d78 100644 > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > > @@ -240,6 +240,7 @@ properties: > >- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL > > Pico-Dwarf > >- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL > > Pico-Hobbit > >- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi > > + - variscite,imx6ul-var-6ulcustomboard # i.MX UltraLite > > Carrier-board > > You missed to add a "6" in the description: i.MX6 UltraLite Carrier-board I will add it. thx Best regards, Oliver
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 09/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Fri, Jan 8, 2021 at 7:24 PM Oliver Graute wrote: > > > > On 19/12/20, Oliver Graute wrote: > > > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD > > > to panel-simple. > > > > > > The panel spec from Variscite can be found at: > > > https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf > > > > some clue what bus_format and bus_flags I have to use? > > > > [ 42.505156] panel-simple panel-lcd: Specify missing bus_flags > > [ 42.511090] panel-simple panel-lcd: Specify missing bus_format > > [ 42.615131] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 > > Does this patch work? > https://pastebin.com/raw/diTMVsh8 the first two errors are gone. But I still get this: [ 42.387107] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 The panel is still off perhaps I miss something else. Best Regards, Oliver
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 19/12/20, Oliver Graute wrote: > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD > to panel-simple. > > The panel spec from Variscite can be found at: > https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf some clue what bus_format and bus_flags I have to use? [ 42.505156] panel-simple panel-lcd: Specify missing bus_flags [ 42.511090] panel-simple panel-lcd: Specify missing bus_format [ 42.615131] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 Best Regards, Oliver
[PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
Add the compatibles for Variscite i.MX6UL compatibles Signed-off-by: Oliver Graute --- Changelog: v3: - rebased v2: - renamed binding - removed superflous " Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 05906e2..5f74d78 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -240,6 +240,7 @@ properties: - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi + - variscite,imx6ul-var-6ulcustomboard # i.MX UltraLite Carrier-board - const: fsl,imx6ul - description: i.MX6UL PHYTEC phyBOARD-Segin -- 2.7.4
[PATCH v8 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
Cc: Parthiban Nallathambi
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 300 +
1 file changed, 300 insertions(+)
Changelog:
v8:
- remove can node
- remove flexscan pinctrl
- moved lcd and i2c pinctrl
- sorted regulators
- add dedicated pinctrl for dvfs regulator
v7:
- removed cpu0 node
- fixed phy problem
v6:
- renamed touch regulator
- renamed rmii clock
- moved some muxing to baseboard
- added pinctrl for gpio key
- added bus-width to usdhc1
- fixed missing subnode on partitions
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index ..913a66f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ clk_rmii_ref: clock-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvfs_reg>;
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ enable-active-high;
+ states = <130 0x1 140 0x0>;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_touch_3v3: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+};
+
+&adc1 {
+ vref-supply = <®_touch_3v3>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ phy-reset-gpios=<&gpio5 10 1>;
+ phy-reset-duration=<100>;
+ phy-reset-on-resume;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+ <&clks IMX6UL_CLK_SAI2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disab
[PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
Cc: Parthiban Nallathambi
---
Changelog:
v8:
- backlight droped the status line
- port the display panel
- added pinctrl for touch
v7:
- fixed wakeup-source
v6:
- added some muxing
- added codec in sound node
- added adc1 node
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 270
2 files changed, 271 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3d1ea0b..7a73b72 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -634,6 +634,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index ..e647d22
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2021 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
+
+ backlight_lcd: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ panel1: panel-lcd {
+ compatible = "sgd,gktw70sdad1sd";
+
+ backlight = <&backlight_lcd>;
+ power-supply = <®_touch_3v3>;
+ label = "gktw70sdad1sd";
+
+ display-timing {
+ /* clock-frequency = <29232000>; */
+ clock-frequency = <3500>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ vsync-len = <48>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ hsync-len = <3>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "
[PATCH v8 0/3] Variscite DART-6UL SoM support
This patch series adds support for the Variscite DART-6UL SoM Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (3): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles Documentation/devicetree/bindings/arm/fsl.yaml | 1 + arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 300 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 270 +++ 4 files changed, 598 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
[PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
---
panel-timing {
clock-frequency = <3500>;
hactive = <800>;
vactive = <480>;
hback-porch = <39>;
hfront-porch = <39>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index c1374be..c2f20ac 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3139,6 +3139,29 @@ static const struct panel_desc satoz_sat050at40h12r2 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing sgd_gktw70sdad1sd_timing = {
+ .pixelclock = {3500, 3500, 3500},
+ .hactive = { 800, 800, 800},
+ .hfront_porch = {39, 39, 39},
+ .hback_porch = {39, 39, 39},
+ .hsync_len = {48, 48, 48},
+ .vactive = {480, 480, 480},
+ .vfront_porch = {13, 13, 13},
+ .vback_porch = {29, 29, 29},
+ .vsync_len = {3, 3, 3},
+};
+
+static const struct panel_desc sgd_gktw70sdad1sd = {
+ .timings = &sgd_gktw70sdad1sd_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 153,
+ .height = 86,
+ },
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
.clock = 168480,
.hdisplay = 1920,
@@ -3999,6 +4022,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "satoz,sat050at40h12r2",
.data = &satoz_sat050at40h12r2,
}, {
+ .compatible = "sgd,gktw70sdad1sd",
+ .data = &sgd_gktw70sdad1sd,
+ }, {
.compatible = "sharp,ld-d5116z01b",
.data = &sharp_ld_d5116z01b,
}, {
--
2.7.4
PGP pathfinder service is no longer maintained
Hello, Unfortunately the site https://pgp.cs.uu.nl/ is not maintained anymore and the "Finding paths to Linus" link in the Kernel Maintainer PGP guide is dead. Is there any alternative sites to find a way through the web of trust? Best Regards, Oliver
[PATCH v2] arm64: dts: imx8qm: added lvds pwm
Add nodes for lvds pwms
Signed-off-by: Oliver Graute
---
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 84 +++
drivers/clk/imx/clk-imx8qxp.c | 14 +++-
drivers/firmware/imx/scu-pd.c | 6 +-
include/dt-bindings/clock/imx8-clock.h| 12 +++
4 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index c21e0818887b..be241813fbea 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -7,6 +7,90 @@
#include
#include
+lvds0_subsys: bus@5624
+{
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5624 0x0 0x5624 0x1>;
+
+ lvds0_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "lvds0_ipg_clk";
+ };
+
+ lvds0_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+<&lvds0_ipg_clk>;
+ clock-indices = , ;
+ clock-output-names = "lvds0_pwm_lpcg_clk",
+"lvds0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ };
+
+ lvds0_pwm: pwm@56244000 {
+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x56244000 0x1000>;
+ clocks = <&lvds0_lpcg IMX_LPCG_CLK_0>,
+<&lvds0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0
IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <2400>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ status = "disabled";
+ };
+};
+
+lvds1_subsys: bus@5724
+{
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5724 0x0 0x5724 0x1>;
+
+ lvds1_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "lvds1_ipg_clk";
+ };
+
+ lvds1_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+<&lvds1_ipg_clk>;
+ clock-indices = , ;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+"lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
+ lvds1_pwm: pwm@57244000 {
+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x57244000 0x1000>;
+ clocks = <&lvds1_lpcg IMX_LPCG_CLK_0>,
+<&lvds1_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0
IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <2400>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ status = "disabled";
+ };
+};
+
lsio_subsys: bus@5d00 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index a6b690d94025..45b63ed06619 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -97,8 +97,6 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk",
IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk",
IMX_SC_R_FTM
[RFC] arm64: dts: imx8qm: added lvds pwm
Hello Aisheng,
I tried to add lvds pwm to imx8qm.dtsi to get backlight working. But without
success. I'am running into this issue:
[0.858737] lcd0-pwm0: failed to power up resource 188 ret -22
Can you review and comment please?
This patch is based on your patch series.
Best regards,
Oliver
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index fd0e706ea011..cf9aea4b26f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -137,6 +137,22 @@ hsio: hsio@5f08 {
reg = <0x0 0x5f08 0x0 0xF>; /* lpcg, csr, msic, gpio */
};
+
+ lvds1_pwm: pwm@57244000 {
+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x57244000 0x1000>;
+ clocks = <&pwm0_lpcg IMX_LPCG_CLK_4>,
+<&pwm0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <2400>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ status = "disabled";
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = ;
--
2.26.0
Re: arm64: imx8qm: tlb SW workaround for IMX8QM
On 27/04/20, Oliver Graute wrote: > On 27/04/20, Oliver Graute wrote: > > Hello, > > > > is this nxp software workaround already proposed to linux community? can > > someone point me to the discussion if available. > > > > https://source.codeaurora.org/external/imx/linux-imx/commit/?h=3Dimx_5.4.3_= > > 2.0.0&id=3D593bea4e36d8c8a4fd65ef4f07fb8144dab2de1c > > sry for the broken link. Here the right one: > > https://source.codeaurora.org/external/imx/linux-imx/commit/?h=imx_5.4.3_2.0.0&id=593bea4e36d8c8a4fd65ef4f07fb8144dab2de1c this patch is not applicable anymore since next-20200713. Is there an updated one? Best Regards, Oliver
Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
On 12/11/19, Fabio Estevam wrote:
> Hi Oliver,
>
> On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute wrote:
>
> > +&lcdif {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_lcdif>;
> > + display = <&display0>;
> > + status = "okay";
> > +
> > + display0: display0 {
> > + bits-per-pixel = <16>;
> > + bus-width = <24>;
> > +
> > + display-timings {
> > + native-mode = <&timing0>;
> > + timing0: timing0 {
> > + clock-frequency =<3500>;
> > + hactive = <800>;
> > + vactive = <480>;
> > + hfront-porch = <40>;
> > + hback-porch = <40>;
> > + hsync-len = <48>;
> > + vback-porch = <29>;
> > + vfront-porch = <13>;
> > + vsync-len = <3>;
> > + hsync-active = <0>;
> > + vsync-active = <0>;
> > + de-active = <1>;
> > + pixelclk-active = <0>;
> > + };
> > + };
> > + };
> > +};
>
> You are using the deprecated bindings.
>
> Please switch to the DRM bindings as stated at
> Documentation/devicetree/bindings/display/mxsfb.txt
>
> You should also add your panel to the simple panel driver.
ok thx for you comments, coming back to this. I now added this to
panel-simple.c. Is this the way to go?
Best Regards,
Oliver
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index c1374be..c2f20ac 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3139,6 +3139,29 @@ static const struct panel_desc satoz_sat050at40h12r2 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing sgd_gktw70sdad1sd_timing = {
+ .pixelclock = {3500, 3500, 3500},
+ .hactive = { 800, 800, 800},
+ .hfront_porch = {39, 39, 39},
+ .hback_porch = {39, 39, 39},
+ .hsync_len = {48, 48, 48},
+ .vactive = {480, 480, 480},
+ .vfront_porch = {13, 13, 13},
+ .vback_porch = {29, 29, 29},
+ .vsync_len = {3, 3, 3},
+};
+
+static const struct panel_desc sgd_gktw70sdad1sd = {
+ .timings = &sgd_gktw70sdad1sd_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 153,
+ .height = 86,
+ },
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
.clock = 168480,
.hdisplay = 1920,
@@ -3999,6 +4022,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "satoz,sat050at40h12r2",
.data = &satoz_sat050at40h12r2,
}, {
+ .compatible = "sgd,gktw70sdad1sd",
+ .data = &sgd_gktw70sdad1sd,
+ }, {
.compatible = "sharp,ld-d5116z01b",
Re: [PATCH] staging: fbtft: fb_st7789v: make HSD20_IPS numeric and not a string
On 21/05/20, Colin King wrote:
> From: Colin Ian King
>
> Currently HSD20_IPS is defined as "true" and will always result in a
> non-zero result even if it is defined as "false" because it is an array
> and that will never be zero. Fix this by defining it as an integer 1
> rather than a literal string.
>
> Addessses-Coverity: ("Array compared against 0")
> Fixes: f03c9b788472 ("staging: fbtft: fb_st7789v: Initialize the Display")
> Signed-off-by: Colin Ian King
> ---
> drivers/staging/fbtft/fb_st7789v.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/fbtft/fb_st7789v.c
> b/drivers/staging/fbtft/fb_st7789v.c
> index ebc17e05ecd0..3a280cc1892c 100644
> --- a/drivers/staging/fbtft/fb_st7789v.c
> +++ b/drivers/staging/fbtft/fb_st7789v.c
> @@ -24,7 +24,7 @@
> "D0 05 0A 09 08 05 2E 44 45 0F 17 16 2B 33\n" \
> "D0 05 0A 09 08 05 2E 43 45 0F 16 16 2B 33"
>
> -#define HSD20_IPS "true"
> +#define HSD20_IPS 1
>
> /**
> * enum st7789v_command - ST7789V display controller commands
Acked-by: Oliver Graute
[PATCH v2] staging: fbtft: fb_st7789v: Initialize the Display
From: Oliver Graute
Set Gamma Values and Register Values for the HSD20_IPS Panel
Signed-off-by: Oliver Graute
---
need information howto set HSD20_IPS Panel at run time and not at compile time
Changes for v2:
- added define for HSD20_IPS_GAMMA values
- check for HSD20_IPS define
- enabled MIPI_DCS_ENTER_INVERT_MODE
drivers/staging/fbtft/fb_st7789v.c | 32 +-
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/fbtft/fb_st7789v.c
b/drivers/staging/fbtft/fb_st7789v.c
index 3c3f387936e8..ebc17e05ecd0 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -20,6 +20,12 @@
"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25\n" \
"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25"
+#define HSD20_IPS_GAMMA \
+ "D0 05 0A 09 08 05 2E 44 45 0F 17 16 2B 33\n" \
+ "D0 05 0A 09 08 05 2E 43 45 0F 16 16 2B 33"
+
+#define HSD20_IPS "true"
+
/**
* enum st7789v_command - ST7789V display controller commands
*
@@ -82,14 +88,20 @@ static int init_display(struct fbtft_par *par)
/* set pixel format to RGB-565 */
write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
+ if (HSD20_IPS)
+ write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33);
- write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22);
+ else
+ write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22);
/*
* VGH = 13.26V
* VGL = -10.43V
*/
- write_reg(par, GCTRL, 0x35);
+ if (HSD20_IPS)
+ write_reg(par, GCTRL, 0x75);
+ else
+ write_reg(par, GCTRL, 0x35);
/*
* VDV and VRH register values come from command write
@@ -101,13 +113,19 @@ static int init_display(struct fbtft_par *par)
* VAP = 4.1V + (VCOM + VCOM offset + 0.5 * VDV)
* VAN = -4.1V + (VCOM + VCOM offset + 0.5 * VDV)
*/
- write_reg(par, VRHS, 0x0B);
+ if (HSD20_IPS)
+ write_reg(par, VRHS, 0x13);
+ else
+ write_reg(par, VRHS, 0x0B);
/* VDV = 0V */
write_reg(par, VDVS, 0x20);
/* VCOM = 0.9V */
- write_reg(par, VCOMS, 0x20);
+ if (HSD20_IPS)
+ write_reg(par, VCOMS, 0x22);
+ else
+ write_reg(par, VCOMS, 0x20);
/* VCOM offset = 0V */
write_reg(par, VCMOFSET, 0x20);
@@ -120,6 +138,10 @@ static int init_display(struct fbtft_par *par)
write_reg(par, PWCTRL1, 0xA4, 0xA1);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
+
+ if (HSD20_IPS)
+ write_reg(par, MIPI_DCS_ENTER_INVERT_MODE);
+
return 0;
}
@@ -234,7 +256,7 @@ static struct fbtft_display display = {
.height = 320,
.gamma_num = 2,
.gamma_len = 14,
- .gamma = DEFAULT_GAMMA,
+ .gamma = HSD20_IPS_GAMMA,
.fbtftops = {
.init_display = init_display,
.set_var = set_var,
--
2.17.1
Re: [PATCHv6 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
On 14/10/19, Shawn Guo wrote:
> On Tue, Sep 24, 2019 at 06:20:21PM +0200, Oliver Graute wrote:
> > This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
> >
> > Signed-off-by: Oliver Graute
> > Cc: Shawn Guo
> > Cc: Neil Armstrong
> > Cc: Marco Felsch
> > ---
> > Changelog:
> > v6:
> > - added some muxing
> > - added codec in sound node
> > - added adc1 node
> >
> > arch/arm/boot/dts/Makefile | 1 +
> > arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 221
> >
> > 2 files changed, 222 insertions(+)
> > create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index a24a6a1..a2a69e4 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -579,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> > imx6ul-tx6ul-0010.dtb \
> > imx6ul-tx6ul-0011.dtb \
> > imx6ul-tx6ul-mainboard.dtb \
> > + imx6ul-var-6ulcustomboard.dtb \
> > imx6ull-14x14-evk.dtb \
> > imx6ull-colibri-eval-v3.dtb \
> > imx6ull-colibri-wifi-eval-v3.dtb \
> > diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> > b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> > new file mode 100644
> > index ..031d8d4
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: (GPL-2.0)
> > +/*
> > + * Support for Variscite DART-6UL Module
> > + *
> > + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
> > + * Copyright (C) 2018-2019 Oliver Graute
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include
> > +#include "imx6ul-imx6ull-var-dart-common.dtsi"
> > +
> > +/ {
> > + model = "Variscite i.MX6 UltraLite Carrier-board";
> > + compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
>
> The compatible needs to be documented.
I'am not sure if I got this right. Is this the way to document it?
or is there more to do?
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
b/Documentation/devicetree/bindings/arm/fsl.yaml
index 41db01d..3ed497b 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -173,6 +173,7 @@ properties:
- armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on
OPOS6ULDev board
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
+ - variscite,6ulcustomboard" # i.MX UltraLite Carrier-board
- const: fsl,imx6ul
Best Regards,
Oliver
[PATCHv6 0/2] Variscite DART-6UL SoM support
Need feedback to the following patches which adds support for a DART-6UL Board Need feedback if the division between customboard and SoM is done right Need some feedback why ethernet RX is not working the right way. RX is deaf. Need feedback howto document propertys and compatible the right way Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (2): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 196 + 3 files changed, 642 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
[PATCHv6 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
---
Changelog:
v6:
- added some muxing
- added codec in sound node
- added adc1 node
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 221
2 files changed, 222 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a24a6a1..a2a69e4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -579,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index ..031d8d4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2019 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,frame-master = <&codec_dai>;
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8731>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+};
+
+&adc1 {
+ vref-supply = <®_touch_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ status = "okay";
+};
+
+&i2c
[PATCHv6 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
Cc: Marco Felsch
---
Changelog:
v6:
- renamed touch regulator
- renamed rmii clock
- moved some muxing to baseboard
- added pinctrl for gpio key
- added bus-width to usdhc1
- fixed missing subnode on partitions
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 381 +
1 file changed, 381 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index ..c91b2c6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ clk_rmii_ref: clock-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+
+ reg_touch_3v3: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ states = <130 0x1 140 0x0>;
+ };
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-gpios=<&gpio5 0 1>;
+ phy-reset-duration=<100>;
+ phy-reset-on-resume;
+ phy-handle = <ðphy0>;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ phy-reset-gpios=<&gpio1 10 1>;
+ phy-reset-duration=<100>;
+ phy-reset-on-resume;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+
+ nand@0 {
+
+ partition@0 {
+ label = "spl";
+ reg = <0x 0x0020>;
+ };
+
+ partition@20 {
+ label = "uboot";
+ reg = <0x0020 0x0020>;
+ };
+
+ partition@40 {
+ label = "uboot-env";
+ reg = <0x0040 0x0020>;
+ };
+
+ partition@60 {
+ label = "kernel";
+ reg = <0x0060 0x0080>;
+ };
+
+ partition@e0 {
+ label = "rootfs";
+ reg = <0x00
[PATCH v2] watchdog: imx_sc: this patch just fixes whitespaces
Fix only whitespace errors in imx_sc_wdt_probe() Signed-off-by: Oliver Graute --- drivers/watchdog/imx_sc_wdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/imx_sc_wdt.c b/drivers/watchdog/imx_sc_wdt.c index 9260475439eb..7ea5cf54e94a 100644 --- a/drivers/watchdog/imx_sc_wdt.c +++ b/drivers/watchdog/imx_sc_wdt.c @@ -176,8 +176,8 @@ static int imx_sc_wdt_probe(struct platform_device *pdev) ret = devm_watchdog_register_device(dev, wdog); if (ret) - return ret; - + return ret; + ret = imx_scu_irq_group_enable(SC_IRQ_GROUP_WDOG, SC_IRQ_WDOG, true); -- 2.17.1
Re: [PATCH v1] watchdog: imx_sc: this patch just fixes whitespaces
On 05/09/19, Guenter Roeck wrote: > On 9/5/19 12:44 AM, Oliver Graute wrote: > > Fix only whitespace errors in imx_sc_wdt_probe() > > > > Signed-off-by: Oliver Graute > > This patch no longer applies due to commit "watchdog: imx_sc: Remove > unnecessary error log". > ok I'll rebase patch against linux-staging/watchdog-next Best regards, Oliver
[PATCH v1] watchdog: imx_sc: this patch just fixes whitespaces
Fix only whitespace errors in imx_sc_wdt_probe()
Signed-off-by: Oliver Graute
---
drivers/watchdog/imx_sc_wdt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/watchdog/imx_sc_wdt.c b/drivers/watchdog/imx_sc_wdt.c
index 78eaaf75a263..94db949042c9 100644
--- a/drivers/watchdog/imx_sc_wdt.c
+++ b/drivers/watchdog/imx_sc_wdt.c
@@ -175,12 +175,12 @@ static int imx_sc_wdt_probe(struct platform_device *pdev)
watchdog_stop_on_unregister(wdog);
ret = devm_watchdog_register_device(dev, wdog);
-
- if (ret) {
- dev_err(dev, "Failed to register watchdog device\n");
- return ret;
- }
-
+
+ if (ret) {
+ dev_err(dev, "Failed to register watchdog device\n");
+ return ret;
+ }
+
ret = imx_scu_irq_group_enable(SC_IRQ_GROUP_WDOG,
SC_IRQ_WDOG,
true);
--
2.17.1
[PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 196
2 files changed, 197 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a24a6a1..a2a69e4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -579,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index ..1861b34
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2019 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+
+ sound_master: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&fec1 {
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy0>;
+ status = "okay";
+};
+
+&fec2 {
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock_frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ wm8731: audio-codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <4 0>;
+ touchscreen-size
[PATCHv5 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
Cc: Shawn Guo
Cc: Neil Armstrong
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 +
1 file changed, 445 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index ..f345d69
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,445 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ touch_3v3_regulator: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-always-on;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ states = <130 0x1 140 0x0>;
+ };
+
+ rmii_ref_clk: clock-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+
+};
+
+&adc1 {
+ vref-supply = <&touch_3v3_regulator>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+
+ partition@0 {
+ label = "spl";
+ reg = <0x 0x0020>;
+ };
+
+ partition@20 {
+ label = "uboot";
+ reg = <0x0020 0x0020>;
+ };
+
+ partition@40 {
+ label = "uboot-env";
+ reg = <0x0040 0x0020>;
+ };
+
+ partition@60 {
+ label = "kernel";
+ reg = <0x0060 0x0080>;
+ };
+
+ partition@e0 {
+ label = "rootfs";
+ reg = <0x00e0 0x3f20>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctr
[PATCHv5 0/2] Variscite DART-6UL SoM support
Need feedback to the following patches which adds support for a DART-6UL Board Need feedback howto document propertys and compatible the right way Need feedback why ethernet RX is deaf Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (2): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 196 + 3 files changed, 642 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
[PATCHv1] arm64: dts: imx8qm: add compatible string for usdhc3
add compatible string for usdhc3
---
This Patch is on top of 10/15 of this series:
https://patchwork.kernel.org/patch/11046343/
[v2,10/15] arm64: dts: imx8qm: add conn ss support
---
arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
index 00ae820d5175..8c33edf0744f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
@@ -19,3 +19,7 @@
&usdhc2 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc";
};
+
+&usdhc3 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc";
+};
--
2.17.1
[PATCHv3 1/1] arm64: dts: add basic DTS for imx8qm-rom7720-a1 board
Add basic dts support for a Advantech iMX8QM Qseven Board
Signed-off-by: Oliver Graute
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../boot/dts/freescale/imx8qm-rom7720-a1.dts | 228 ++
2 files changed, 229 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index c5e39cd4fdaf..68dd30ade6df 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-rom7720-a1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
new file mode 100644
index ..f79c2c7a7cda
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+ model = "Advantech iMX8QM Qseven series";
+ compatible = "fsl,imx8qm";
+
+ board {
+ compatible = "proc-board";
+ board-type = "ROM-7720_A1";
+ board-cpu = "iMX8QM";
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path = &lpuart0;
+ };
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x4000>;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3000>;
+ enable-active-high;
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ fsl,rgmii_rxc_dly;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&lsio_gpio4 {
+status = "okay";
+};
+&lsio_gpio5 {
+status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO030x0648
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD
0x14a0
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC
0x0620
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO
0x0620
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
0x0
[PATCHv3 0/1] arm64: dts: add basic DTS for imx8qm-rom7720 board
This patch is ontop of Aisheng Dongs clock driver and imx8 changes for the imx8qm https://patchwork.kernel.org/patch/11046313/ https://patchwork.kernel.org/patch/11046343/ This patch is based on next-20190716 I need some hints and review why the imx8qm-rom-7720 just stops at "Starting kernel ..." with these changes. The device tree is similar to imx8qm-mek.dts. Oliver Graute (1): arm64: dts: add basic DTS for imx8qm-rom7720-a1 board arch/arm64/boot/dts/freescale/Makefile| 1 + .../boot/dts/freescale/imx8qm-rom7720-a1.dts | 228 ++ 2 files changed, 229 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts -- 2.17.1
[PATCHv3] clk: add imx8 clk defines
From: Anson Huang added header defines for imx8qm clock Signed-off-by: Anson Huang Signed-off-by: Oliver Graute Reviewed-by: Rob Herring --- - fixed authorship include/dt-bindings/clock/imx8qm-clock.h | 851 +++ 1 file changed, 851 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qm-clock.h diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index ..47217e4eaa6b --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,851 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP +*/ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV15 +#define IMX8QM_PWM0_CLK16 +#define IMX8QM_PWM1_DIV17 +#define IMX8QM_PWM1_CLK18 +#define IMX8QM_PWM2_DIV19 +#define IMX8QM_PWM2_CLK20 +#define IMX8QM_PWM3_DIV21 +#define IMX8QM_PWM3_CLK22 +#define IMX8QM_PWM4_DIV23 +#define IMX8QM_PWM4_CLK24 +#define IMX8QM_PWM5_DIV26 +#define IMX8QM_PWM5_CLK27 +#define IMX8QM_PWM6_DIV28 +#define IMX8QM_PWM6_CLK29 +#define IMX8QM_PWM7_DIV30 +#define IMX8QM_PWM7_CLK31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV36 +//#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV38 +//#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV40 +#define IMX8QM_GPT2_CLK41 +#define IMX8QM_GPT3_DIV42 +#define IMX8QM_GPT3_CLK43 +#define IMX8QM_GPT4_DIV44 +#define IMX8QM_GPT4_CLK45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK47 +#define IMX8QM_GPMI_APB_BCH_CLK48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV51 +#define IMX8QM_GPMI_BCH_CLK52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CL63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK65 +#define IMX8QM_USB3_IPG_CLK66 +#define IMX8QM_USB3_CORE_PCLK 67
Re: [PATCHv2] clk: add imx8 clk defines
On 11/07/19, Abel Vesa wrote: > On 19-06-19 09:39:52, Oliver Graute wrote: > > From: Oliver Graute > > > > added header defines for imx8qm clock > > > > Signed-off-by: Oliver Graute > > Again, this seems to be taken from some vendor tree, so please keep the > original author. yes the header defines is from NXP vendor tree. One of orginal authors is Author: Anson Huang Date: Thu Jan 19 03:53:31 2017 +0800 MLK-13911-3 ARM64: dts: imx8qm: add dtsi Add i.MX8QM dtsi support. https://github.com/ADVANTECH-Corp/linux-imx6.git Whats is the right way to attribute him? Best regards, Oliver
Re: [PATCHv3 0/2] Variscite DART-6UL SoM support
On 13/06/19, Shawn Guo wrote: > On Thu, Jun 06, 2019 at 06:47:00PM +0200, Oliver Graute wrote: > > Need feedback to the following patches which adds support for a DART-6UL > > Board > > > > Product Page: > > https://www.variscite.com/product/evaluation-kits/dart-6ul-kits > > > > Oliver Graute (2): > > ARM: dts: imx6ul: Add Variscite DART-6UL SoM support > > ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard > > It's already v3? I did not find previous versions. What's changed > since previous versions? The first two version you can find here. I splitted board and SoM part according Neils and Fabios comments. v1 https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=59259 v2 https://patchwork.kernel.org/patch/10748361/ Please review the latest version v4: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=137257 Thx for your time and patience. Oliver
[PATCHv2 2/2] arm64: dts: add basic DTS for imx8qm-rom7720-a1 board
Add basic dts support for a Advantech iMX8QM Qseven Board
Signed-off-by: Oliver Graute
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../boot/dts/freescale/imx8qm-rom7720-a1.dts | 221 ++
2 files changed, 222 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index b8e5e3bd72c5..b013715c5be1 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -23,3 +23,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-rom7720-a1.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
new file mode 100644
index ..229853f4097b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+ model = "Advantech iMX8QM Qseven series";
+ compatible = "fsl,imx8qm";
+
+ board {
+ compatible = "proc-board";
+ board-type = "ROM-7720_A1";
+ board-cpu = "iMX8QM";
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path = &dma_lpuart0;
+ };
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x4000>;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3000>;
+ enable-active-high;
+ };
+};
+
+&dma_lpuart0 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ fsl,rgmii_rxc_dly;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO030x0648
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD
0x14a0
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC
0x0620
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO
0x0620
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
0x0060
+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
0x0060
+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
0x0060
+ IMX8QM_E
[PATCHv2 0/2] arm64: dts: add basic DTS for imx8qm-rom7720 board
This patchset is ontop of Aisheng Dongs clock driver changes for the imx8qm https://patchwork.kernel.org/cover/10824537/ This patchset is based on next-20190222 I need information about the status of the integration of the imx8qm clock driver into mainline. Is this ongoing? I need some hints why the imx8qm-rom7720 do NOT boot with the following changes. It stops at "Starting kernel ..." Oliver Graute (2): arm64: add gpio4 and gpio5 to basic DTS for i.MX8MQ arm64: dts: add basic DTS for imx8qm-rom7720-a1 board arch/arm64/boot/dts/freescale/Makefile| 1 + .../boot/dts/freescale/imx8qm-rom7720-a1.dts | 221 ++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 19 ++ 3 files changed, 241 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-rom7720-a1.dts -- 2.17.1
[PATCHv2 1/2] arm64: add gpio4 and gpio5 to basic DTS for i.MX8MQ
add gpio4 to imx8qm.dtsi
add gpio5 to imx8qm.dtsi
Signed-off-by: Oliver Graute
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 526cbbddc202..fe4c584625cf 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -121,6 +121,25 @@
interrupt-parent = <&gic>;
};
+ gpio4: gpio@5d0c {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0c 0x0 0x1>;
+ interrupts = ;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+ gpio5: gpio@5d0d {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0d 0x0 0x1>;
+ interrupts = ;
+gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = ;
--
2.17.1
[PATCHv4 0/2] Variscite DART-6UL SoM support
Need feedback to the following patches which adds support for a DART-6UL Board Need feedback howto document propertys and compatible the right way Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (2): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 203 + 3 files changed, 662 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
[PATCH 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 +
1 file changed, 458 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index 000..57d62e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ touch_3v3_regulator: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-always-on;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ states = <130 0x1 140 0x0>;
+ };
+
+ clk-phy {
+ /* ref_clk for micrel ethernet phy */
+ rmii_ref_clk: rmii_ref_clk_grp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+ };
+
+ clk-pll {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+ };
+};
+
+&adc1 {
+ vref-supply = <&touch_3v3_regulator>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ dc-supply = <®_gpio_dvfs>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,legacy-bch-geometry;
+ status = "okay";
+
+ partition@0 {
+ label = "spl";
+ reg = <0x 0x0020>;
+ };
+
+ partition@20 {
+ label = "uboot";
+ reg = <0x0020 0x0020>;
+ };
+
+ partition@40 {
+ label = "uboot-env";
+ reg = <0x0040 0x0020>;
+ };
+
+ partition@60 {
+ label = "kernel";
+ reg = <0x0060 0x0080>;
+ };
+
+ partition@e0 {
+ label = "rootfs";
+
[PATCH 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 203
2 files changed, 204 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c4742af..5dc3fbf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -577,6 +577,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index 000..59354e6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2019 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "fsl,6ulcustomboard", "fsl,imx6ul";
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+
+ sound_master: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x2>;
+ fsl,cpu_pupscr_sw = <0x1>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&fec1 {
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy0>;
+ status = "okay";
+};
+
+&fec2 {
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock_frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ wm8731: audio-codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+
[PATCHv2] clk: add imx8 clk defines
From: Oliver Graute added header defines for imx8qm clock Signed-off-by: Oliver Graute --- include/dt-bindings/clock/imx8qm-clock.h | 851 +++ 1 file changed, 851 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qm-clock.h diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index ..47217e4eaa6b --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,851 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP +*/ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV15 +#define IMX8QM_PWM0_CLK16 +#define IMX8QM_PWM1_DIV17 +#define IMX8QM_PWM1_CLK18 +#define IMX8QM_PWM2_DIV19 +#define IMX8QM_PWM2_CLK20 +#define IMX8QM_PWM3_DIV21 +#define IMX8QM_PWM3_CLK22 +#define IMX8QM_PWM4_DIV23 +#define IMX8QM_PWM4_CLK24 +#define IMX8QM_PWM5_DIV26 +#define IMX8QM_PWM5_CLK27 +#define IMX8QM_PWM6_DIV28 +#define IMX8QM_PWM6_CLK29 +#define IMX8QM_PWM7_DIV30 +#define IMX8QM_PWM7_CLK31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV36 +//#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV38 +//#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV40 +#define IMX8QM_GPT2_CLK41 +#define IMX8QM_GPT3_DIV42 +#define IMX8QM_GPT3_CLK43 +#define IMX8QM_GPT4_DIV44 +#define IMX8QM_GPT4_CLK45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK47 +#define IMX8QM_GPMI_APB_BCH_CLK48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV51 +#define IMX8QM_GPMI_BCH_CLK52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CL63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK65 +#define IMX8QM_USB3_IPG_CLK66 +#define IMX8QM_USB3_CORE_PCLK 67 +#define IMX8QM_USB3_PHY_CLK68 +#define
[PATCHv2] clk: add imx8 clk defines
From: Oliver Graute added header defines for imx8qm clock Signed-off-by: Oliver Graute --- include/dt-bindings/clock/imx8qm-clock.h | 851 +++ 1 file changed, 851 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qm-clock.h diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index ..47217e4eaa6b --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,851 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP +*/ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV15 +#define IMX8QM_PWM0_CLK16 +#define IMX8QM_PWM1_DIV17 +#define IMX8QM_PWM1_CLK18 +#define IMX8QM_PWM2_DIV19 +#define IMX8QM_PWM2_CLK20 +#define IMX8QM_PWM3_DIV21 +#define IMX8QM_PWM3_CLK22 +#define IMX8QM_PWM4_DIV23 +#define IMX8QM_PWM4_CLK24 +#define IMX8QM_PWM5_DIV26 +#define IMX8QM_PWM5_CLK27 +#define IMX8QM_PWM6_DIV28 +#define IMX8QM_PWM6_CLK29 +#define IMX8QM_PWM7_DIV30 +#define IMX8QM_PWM7_CLK31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV36 +//#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV38 +//#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV40 +#define IMX8QM_GPT2_CLK41 +#define IMX8QM_GPT3_DIV42 +#define IMX8QM_GPT3_CLK43 +#define IMX8QM_GPT4_DIV44 +#define IMX8QM_GPT4_CLK45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK47 +#define IMX8QM_GPMI_APB_BCH_CLK48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV51 +#define IMX8QM_GPMI_BCH_CLK52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CL63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK65 +#define IMX8QM_USB3_IPG_CLK66 +#define IMX8QM_USB3_CORE_PCLK 67 +#define IMX8QM_USB3_PHY_CLK68 +#define
[PATCHv3 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
This patch adds DeviceTree Bindings for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 209
2 files changed, 210 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5559028..7f03ab5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -577,6 +577,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index 000..80b860a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2019 Oliver Graute
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "fsl,6ulcustomboard", "fsl,imx6ul";
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ d16_led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+
+ sound_master: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x2>;
+ fsl,cpu_pupscr_sw = <0x1>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&fec1 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy0>;
+};
+
+&fec2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+};
+
+&i2c1 {
+ clock-frequency = <40>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock_frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ wm8731: codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
+ };
+
+ touchscreen@38 {
+
[PATCHv3 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 +
1 file changed, 458 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index 000..89e48be
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ touch_3v3_regulator: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-always-on;
+ status = "okay";
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ regulator-min-microvolt = <130>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ states = <130 0x1 140 0x0>;
+ };
+};
+
+&adc1 {
+ vref-supply = <&touch_3v3_regulator>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&clks {
+ /* ref_clk for micrel ethernet phy */
+ rmii_ref_clk: rmii_ref_clk_grp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ clock-output-names = "rmii-ref";
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ dc-supply = <®_gpio_dvfs>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&rmii_ref_clk>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "disabled";
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+ <&clks IMX6UL_CLK_SAI2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <12288000>;
+ fsl,sai-mclk-directi
[PATCHv3 0/2] Variscite DART-6UL SoM support
Need feedback to the following patches which adds support for a DART-6UL Board Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (2): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts| 209 ++ 3 files changed, 668 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4
