[PATCH 4/4] clk: ux500: Clocks definition for u8540
From: Philippe Begnic
First clocks definition version of PRCMU and PRCC clocks for u8540 platform
Signed-off-by: Philippe Begnic
---
drivers/clk/ux500/u8540_clk.c | 560 -
1 file changed, 559 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index 90f3c88..f262588 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -17,5 +17,563 @@
void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
u32 clkrst5_base, u32 clkrst6_base)
{
- /* register clocks here */
+ struct clk *clk;
+
+ /* Clock sources. */
+ /* Fixed ClockGen */
+ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
+ CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+ clk_register_clkdev(clk, "soc0_pll", NULL);
+
+ clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
+ CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+ clk_register_clkdev(clk, "soc1_pll", NULL);
+
+ clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
+ CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+ clk_register_clkdev(clk, "ddr_pll", NULL);
+
+ clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
+ CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+ 32768);
+ clk_register_clkdev(clk, "clk32k", NULL);
+ clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
+
+ clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
+ CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+ 3840);
+
+ clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "UART");
+
+ /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
+ clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
+ PRCMU_MSP02CLK, 0);
+ clk_register_clkdev(clk, NULL, "MSP02");
+
+ clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "MSP1");
+
+ clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "I2C");
+
+ clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "slim");
+
+ clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH1");
+
+ clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH2");
+
+ clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH3");
+
+ clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH5");
+
+ clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH6");
+
+ clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "PERIPH7");
+
+ clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
+ clk_register_clkdev(clk, NULL, "lcd");
+ clk_register_clkdev(clk, "lcd", "mcde");
+
+ clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK,
+ CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "bml");
+
+ clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+ clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+ clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
+ clk_register_clkdev(clk, NULL, "hdmi");
+ clk_register_clkdev(clk, "hdmi", "mcde");
+
+ clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "apeat");
+
+ clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
+ CLK_IS_ROOT);
+ clk_register_clkdev(clk, NULL, "apetrace");
+
+ clk = cl
[PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
From: Philippe Begnic
Align on u8500 version, pass clock base address in clk_init functions
for u8540 and u9540.
Signed-off-by: Linus Walleij
Signed-off-by: Philippe Begnic
---
arch/arm/mach-ux500/cpu.c |6 --
drivers/clk/ux500/u8540_clk.c |4 ++--
drivers/clk/ux500/u9540_clk.c |4 ++--
include/linux/platform_data/clk-ux500.h |6 --
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index b6145ea..e6fb023 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
} else if (cpu_is_u9540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
- u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+ u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE);
} else if (cpu_is_u8540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
- u8540_clk_init();
+ u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+ U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+ U8500_CLKRST6_BASE);
}
}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index 10adfd2..90f3c88 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -12,10 +12,10 @@
#include
#include
#include
-
#include "clk.h"
-void u8540_clk_init(void)
+void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+ u32 clkrst5_base, u32 clkrst6_base)
{
/* register clocks here */
}
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
index dbc0191..4479478 100644
--- a/drivers/clk/ux500/u9540_clk.c
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -12,10 +12,10 @@
#include
#include
#include
-
#include "clk.h"
-void u9540_clk_init(void)
+void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+ u32 clkrst5_base, u32 clkrst6_base)
{
/* register clocks here */
}
diff --git a/include/linux/platform_data/clk-ux500.h
b/include/linux/platform_data/clk-ux500.h
index 320d9c3..9d98f3a 100644
--- a/include/linux/platform_data/clk-ux500.h
+++ b/include/linux/platform_data/clk-ux500.h
@@ -12,7 +12,9 @@
void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
u32 clkrst5_base, u32 clkrst6_base);
-void u9540_clk_init(void);
-void u8540_clk_init(void);
+void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+ u32 clkrst5_base, u32 clkrst6_base);
+void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+ u32 clkrst5_base, u32 clkrst6_base);
#endif /* __CLK_UX500_H */
--
1.7.9.5
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[PATCH 2/4] mfd: db8500: Update register definition for u8540 clock
From: Philippe Begnic
PRCMU and ab8500 registers updated for u8540
Signed-off-by: Philippe Begnic
---
include/linux/mfd/abx500/ab8500-sysctrl.h |4 ++--
include/linux/mfd/dbx500-prcmu.h | 11 +++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h
b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 990bc93..adba89d 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data {
#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 689e6a0..d0ba355 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -134,6 +134,10 @@ enum prcmu_clock {
PRCMU_SIACLK,
PRCMU_SVACLK,
PRCMU_ACLK,
+ PRCMU_HVACLK, /* Ux540 only */
+ PRCMU_G1CLK, /* Ux540 only */
+ PRCMU_SDMMCHCLK,
+ PRCMU_CAMCLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
@@ -148,6 +152,13 @@ enum prcmu_clock {
PRCMU_DSI0ESCCLK,
PRCMU_DSI1ESCCLK,
PRCMU_DSI2ESCCLK,
+ /* LCD DSI PLL - Ux540 only */
+ PRCMU_PLLDSI_LCD,
+ PRCMU_DSI0CLK_LCD,
+ PRCMU_DSI1CLK_LCD,
+ PRCMU_DSI0ESCCLK_LCD,
+ PRCMU_DSI1ESCCLK_LCD,
+ PRCMU_DSI2ESCCLK_LCD,
};
/**
--
1.7.9.5
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[PATCH 3/4] mfd: db8500: Update BML clock register for db8580
From: Philippe Begnic
BML clock register address in DB8580 has changed.Defined a new address
under different name for DB8580.
Signed-off-by: Philippe Begnic
---
drivers/mfd/db8500-prcmu.c |1 +
drivers/mfd/dbx500-prcmu-regs.h |1 +
include/linux/mfd/dbx500-prcmu.h |1 +
3 files changed, 3 insertions(+)
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 66f8097..a292a1d 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
+ CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index d14836e..ca355dd 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -32,6 +32,7 @@
#define PRCM_PER7CLK_MGT (0x040)
#define PRCM_LCDCLK_MGT(0x044)
#define PRCM_BMLCLK_MGT(0x04C)
+#define PRCM_BML8580CLK_MGT(0x108)
#define PRCM_HSITXCLK_MGT (0x050)
#define PRCM_HSIRXCLK_MGT (0x054)
#define PRCM_HDMICLK_MGT (0x058)
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d0ba355..ca0790f 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -138,6 +138,7 @@ enum prcmu_clock {
PRCMU_G1CLK, /* Ux540 only */
PRCMU_SDMMCHCLK,
PRCMU_CAMCLK,
+ PRCMU_BML8580CLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
--
1.7.9.5
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[PATCH 0/4] clk, mfd: u8540 clock tree definition
From: Philippe Begnic Create U8540 clock tree definitions for common clock framework Philippe Begnic (4): clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 mfd: db8500: Update register definition for u8540 clock mfd: db8500: Update BML clock register for db8580 clk: ux500: Clocks definition for u8540 arch/arm/mach-ux500/cpu.c |6 +- drivers/clk/ux500/u8540_clk.c | 564 - drivers/clk/ux500/u9540_clk.c |4 +- drivers/mfd/db8500-prcmu.c|1 + drivers/mfd/dbx500-prcmu-regs.h |1 + include/linux/mfd/abx500/ab8500-sysctrl.h |4 +- include/linux/mfd/dbx500-prcmu.h | 12 + include/linux/platform_data/clk-ux500.h |6 +- 8 files changed, 587 insertions(+), 11 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
