from:"Piyush Mehta"

[PATCH V2] ata: ahci: ceva: Updated code by using dev_err_probe()

2021-03-05 Thread Piyush Mehta

Updated code with already prepared dev_err_probe(). It reduces code size
and simplifies EPROBE_DEFER handling.

Also, unify message format for similar error cases.

Signed-off-by: Piyush Mehta 
Acked-by: Michal Simek 
---
This patch is based on ahci-ceva patches:
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next=5542fabd9e07d6c49c07862e73070c325f93d390

Tree: 
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/tree/?h=for-next

Changes for V2:
- Address review comment- remove curly brackets {}. 
---
 drivers/ata/ahci_ceva.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b980218..50b56cd 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -206,11 +206,9 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
cevapriv->rst = devm_reset_control_get_optional_exclusive(>dev,
  NULL);
-   if (IS_ERR(cevapriv->rst)) {
-   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
-   dev_err(>dev, "failed to get reset: %ld\n",
-   PTR_ERR(cevapriv->rst));
-   }
+   if (IS_ERR(cevapriv->rst))
+   dev_err_probe(>dev, PTR_ERR(cevapriv->rst),
+ "failed to get reset\n");
 
hpriv = ahci_platform_get_resources(pdev, 0);
if (IS_ERR(hpriv))
-- 
2.7.4

[PATCH] ata: ahci: ceva: Updated code by using dev_err_probe()

2021-03-04 Thread Piyush Mehta

Updated code with already prepared dev_err_probe(). It reduces code size
and simplifies EPROBE_DEFER handling.

Also, unify message format for similar error cases.

Signed-off-by: Piyush Mehta 
---
This patch is based on ahci-ceva patches:
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next=5542fabd9e07d6c49c07862e73070c325f93d390

Tree: 
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/tree/?h=for-next
---
 drivers/ata/ahci_ceva.c |5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b980218..a935209 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -207,9 +207,8 @@ static int ceva_ahci_probe(struct platform_device *pdev)
cevapriv->rst = devm_reset_control_get_optional_exclusive(>dev,
  NULL);
if (IS_ERR(cevapriv->rst)) {
-   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
-   dev_err(>dev, "failed to get reset: %ld\n",
-   PTR_ERR(cevapriv->rst));
+   dev_err_probe(>dev, PTR_ERR(cevapriv->rst),
+ "failed to get reset\n");
}
 
hpriv = ahci_platform_get_resources(pdev, 0);
-- 
1.7.1

[PATCH] ata: ahci: ceva: Updated code by using dev_err_probe()

2021-03-04 Thread Piyush Mehta

Updated code with already prepared dev_err_probe(). It reduces code size
and simplifies EPROBE_DEFER handling.

Also, unify message format for similar error cases.

Signed-off-by: Piyush Mehta 
---
This patch is based on ahci-ceva patches:
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next=5542fabd9e07d6c49c07862e73070c325f93d390

Tree: 
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/tree/?h=for-next
---
 drivers/ata/ahci_ceva.c |5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b980218..a935209 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -207,9 +207,8 @@ static int ceva_ahci_probe(struct platform_device *pdev)
cevapriv->rst = devm_reset_control_get_optional_exclusive(>dev,
  NULL);
if (IS_ERR(cevapriv->rst)) {
-   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
-   dev_err(>dev, "failed to get reset: %ld\n",
-   PTR_ERR(cevapriv->rst));
+   dev_err_probe(>dev, PTR_ERR(cevapriv->rst),
+ "failed to get reset\n");
}
 
hpriv = ahci_platform_get_resources(pdev, 0);
-- 
1.7.1

[PATCH V3 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

2021-02-08 Thread Piyush Mehta

This patch updates the documentation for the CEVA controller for adding
the optional properties for 'phys' and 'resets'.

Signed-off-by: Piyush Mehta 
---
 Documentation/devicetree/bindings/ata/ahci-ceva.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt 
b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7561cc4..bfb6da0 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -38,6 +38,8 @@ Required properties:
 
 Optional properties:
   - ceva,broken-gen2: limit to gen1 speed instead of gen2.
+  - phys: phandle for the PHY device
+  - resets: phandle to the reset controller for the SATA IP
 
 Examples:
ahci@fd0c {
@@ -56,4 +58,6 @@ Examples:
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
+   phys = < 1 PHY_TYPE_SATA 1 1>;
+   resets = <_reset ZYNQMP_RESET_SATA>;
};
-- 
2.7.4

[PATCH V3 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2021-02-08 Thread Piyush Mehta

SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can be used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for the SATA controller, the below sequence is expected.

1. Assert the SATA controller reset.
2. Configure the xilinx GT phy lane for SATA controller (phy_init).
3. De-assert the SATA controller reset.
4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).

The ahci_platform_enable_resources() by default does the phy_init()
and phy_power_on() but the default sequence doesn't work with Xilinx
platforms. Because of this reason, updated the driver to support the
new sequence.

Added cevapriv->rst check, for backward compatibility with the older
sequence. If the reset controller is not available, then the SATA
controller will configure with the older sequences.

Signed-off-by: Piyush Mehta 
---
 drivers/ata/ahci_ceva.c | 43 ---
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b10fd4c..b980218 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "ahci.h"
 
 /* Vendor Specific Register Offsets */
@@ -87,6 +88,7 @@ struct ceva_ahci_priv {
u32 axicc;
bool is_cci_enabled;
int flags;
+   struct reset_control *rst;
 };
 
 static unsigned int ceva_ahci_read_id(struct ata_device *dev,
@@ -202,13 +204,48 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
cevapriv->ahci_pdev = pdev;
 
+   cevapriv->rst = devm_reset_control_get_optional_exclusive(>dev,
+ NULL);
+   if (IS_ERR(cevapriv->rst)) {
+   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
+   dev_err(>dev, "failed to get reset: %ld\n",
+   PTR_ERR(cevapriv->rst));
+   }
+
hpriv = ahci_platform_get_resources(pdev, 0);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
 
-   rc = ahci_platform_enable_resources(hpriv);
-   if (rc)
-   return rc;
+   if (!cevapriv->rst) {
+   rc = ahci_platform_enable_resources(hpriv);
+   if (rc)
+   return rc;
+   } else {
+   int i;
+
+   rc = ahci_platform_enable_clks(hpriv);
+   if (rc)
+   return rc;
+   /* Assert the controller reset */
+   reset_control_assert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_init(hpriv->phys[i]);
+   if (rc)
+   return rc;
+   }
+
+   /* De-assert the controller reset */
+   reset_control_deassert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_power_on(hpriv->phys[i]);
+   if (rc) {
+   phy_exit(hpriv->phys[i]);
+   return rc;
+   }
+   }
+   }
 
if (of_property_read_bool(np, "ceva,broken-gen2"))
cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
-- 
2.7.4

[PATCH V3 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2021-02-08 Thread Piyush Mehta

This patch series updates the ceva driver to add support for Xilinx GT phy.
This also updates the documentation with the device tree binding required
for working with Xilinx GT phy.

---
Changes in V2:
 - Added backward compatibility with the older sequence of the CEVA controller.
 - Update dt-bindings document: To make phy and reset properties optional.
 - Remove rst_names property.

Changes in V3:
 - Remove phy-names property.
 - Validate backward compatibility with reset controller availability,
   instead of a flag.
---
Piyush Mehta (2):
  dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller
  ata: ahci: ceva: Update the driver to support xilinx GT phy

 .../devicetree/bindings/ata/ahci-ceva.txt  |  4 ++
 drivers/ata/ahci_ceva.c| 43 --
 2 files changed, 44 insertions(+), 3 deletions(-)

-- 
2.7.4

RE: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Piyush Mehta

Hello Philipp,

Thanks for review.

Regards,
Piyush Mehta

-Original Message-
From: Philipp Zabel  
Sent: Tuesday, September 22, 2020 5:36 PM
To: Piyush Mehta ; ax...@kernel.dk; robh...@kernel.org
Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org; git ; Srinivas Goud 
; Michal Simek 
Subject: Re: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support 
xilinx GT phy

On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote:
> SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy 
> which has 4 GT lanes and can used by 4 peripherals at a time.
> SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure 
> the GT lane for SATA controller, the below sequence is expected.
> 
> 1. Assert the SATA controller reset.
> 2. Configure the xilinx GT phy lane for SATA controller (phy_init).
> 3. De-assert the SATA controller reset.
> 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).
> 
> The ahci_platform_enable_resources() by default does the phy_init() 
> and phy_power_on() but the default sequence doesn't work with Xilinx 
> platforms. Because of this reason, updated the driver to support the 
> new sequence.
> 
> Added is_rst_ctrl flag, for backward compatibility with the older 
> sequence. If the reset controller is not available, then the SATA 
> controller will configure with the older sequences.
> 
> Signed-off-by: Piyush Mehta 
> ---
>  drivers/ata/ahci_ceva.c | 39 +--
>  1 file changed, 37 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index 
> b10fd4c..c704906 100644
> --- a/drivers/ata/ahci_ceva.c
> +++ b/drivers/ata/ahci_ceva.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "ahci.h"
>  
>  /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct 
> ceva_ahci_priv {
>   u32 axicc;
>   bool is_cci_enabled;
>   int flags;
> + struct reset_control *rst;
>  };
>  
>  static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ 
> -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
>   struct ahci_host_priv *hpriv;
>   struct ceva_ahci_priv *cevapriv;
>   enum dev_dma_attr attr;
> - int rc;
> + int rc, i, is_rst_ctrl = 1;
>  
>   cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
>   if (!cevapriv)
> @@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct 
> platform_device *pdev)
>  
>   cevapriv->ahci_pdev = pdev;
>  
> + cevapriv->rst = devm_reset_control_get(>dev, NULL);

Please use devm_reset_control_get_optional_exclusive()

> + if (IS_ERR(cevapriv->rst)) {
> + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
> + dev_err(>dev, "failed to get reset: %ld\n",
> + PTR_ERR(cevapriv->rst));
> + is_rst_ctrl = 0;

is_rst_ctrl will not be required then.

> + }
> +
>   hpriv = ahci_platform_get_resources(pdev, 0);
>   if (IS_ERR(hpriv))
>   return PTR_ERR(hpriv);
> + if (is_rst_ctrl)
> + rc = ahci_platform_enable_clks(hpriv);
> + else
> + rc = ahci_platform_enable_resources(hpriv);
>  
> - rc = ahci_platform_enable_resources(hpriv);
>   if (rc)
>   return rc;
>  
> + if (is_rst_ctrl) {

This can just be "if (cevapriv->rst)"

> + /* Assert the controller reset */
> + reset_control_assert(cevapriv->rst);
> +
> + for (i = 0; i < hpriv->nports; i++) {
> + rc = phy_init(hpriv->phys[i]);
> + if (rc)
> + return rc;
> + }
> +
> + /* De-assert the controller reset */
> + reset_control_deassert(cevapriv->rst);
> +
> + for (i = 0; i < hpriv->nports; i++) {
> + rc = phy_power_on(hpriv->phys[i]);
> + if (rc) {
> + phy_exit(hpriv->phys[i]);
> + return rc;
> + }
> + }
> + }
> +
>   if (of_property_read_bool(np, "ceva,broken-gen2"))
>   cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
>  

regards
Philipp

[PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Piyush Mehta

SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for SATA controller, the below sequence is expected.

1. Assert the SATA controller reset.
2. Configure the xilinx GT phy lane for SATA controller (phy_init).
3. De-assert the SATA controller reset.
4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).

The ahci_platform_enable_resources() by default does the phy_init()
and phy_power_on() but the default sequence doesn't work with Xilinx
platforms. Because of this reason, updated the driver to support the
new sequence.

Added is_rst_ctrl flag, for backward compatibility with the older
sequence. If the reset controller is not available, then the SATA
controller will configure with the older sequences.

Signed-off-by: Piyush Mehta 
---
 drivers/ata/ahci_ceva.c | 39 +--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b10fd4c..c704906 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "ahci.h"
 
 /* Vendor Specific Register Offsets */
@@ -87,6 +88,7 @@ struct ceva_ahci_priv {
u32 axicc;
bool is_cci_enabled;
int flags;
+   struct reset_control *rst;
 };
 
 static unsigned int ceva_ahci_read_id(struct ata_device *dev,
@@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
struct ahci_host_priv *hpriv;
struct ceva_ahci_priv *cevapriv;
enum dev_dma_attr attr;
-   int rc;
+   int rc, i, is_rst_ctrl = 1;
 
cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
if (!cevapriv)
@@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
cevapriv->ahci_pdev = pdev;
 
+   cevapriv->rst = devm_reset_control_get(>dev, NULL);
+   if (IS_ERR(cevapriv->rst)) {
+   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
+   dev_err(>dev, "failed to get reset: %ld\n",
+   PTR_ERR(cevapriv->rst));
+   is_rst_ctrl = 0;
+   }
+
hpriv = ahci_platform_get_resources(pdev, 0);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
+   if (is_rst_ctrl)
+   rc = ahci_platform_enable_clks(hpriv);
+   else
+   rc = ahci_platform_enable_resources(hpriv);
 
-   rc = ahci_platform_enable_resources(hpriv);
if (rc)
return rc;
 
+   if (is_rst_ctrl) {
+   /* Assert the controller reset */
+   reset_control_assert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_init(hpriv->phys[i]);
+   if (rc)
+   return rc;
+   }
+
+   /* De-assert the controller reset */
+   reset_control_deassert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_power_on(hpriv->phys[i]);
+   if (rc) {
+   phy_exit(hpriv->phys[i]);
+   return rc;
+   }
+   }
+   }
+
if (of_property_read_bool(np, "ceva,broken-gen2"))
cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
 
-- 
2.7.4

[PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Piyush Mehta

This patch series updates the ceva driver to add support for Xilinx GT phy.
This also updates the documentation with the device tree binding required
for working with Xilinx GT phy.

---
Changes in V2:
 - Added backward compatibility with the older sequence of the CEVA controller.
 - Update dt-bindings document: To make phy and reset properties optional.
 - Remove rst_names property.
---
Piyush Mehta (2):
  dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller
  ata: ahci: ceva: Update the driver to support xilinx GT phy

 .../devicetree/bindings/ata/ahci-ceva.txt  |  6 
 drivers/ata/ahci_ceva.c| 39 --
 2 files changed, 43 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

2020-09-22 Thread Piyush Mehta

This patch updates the documentation for the CEVA controller for adding
the optional properties for 'phys' and 'resets'.

Signed-off-by: Piyush Mehta 
---
 Documentation/devicetree/bindings/ata/ahci-ceva.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt 
b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7561cc4..da423eb 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -38,6 +38,9 @@ Required properties:
 
 Optional properties:
   - ceva,broken-gen2: limit to gen1 speed instead of gen2.
+  - phys: phandle for the PHY device
+  - phy-names: Should be "sata-phy"
+  - resets: phandle to the reset controller for the SATA IP
 
 Examples:
ahci@fd0c {
@@ -56,4 +59,7 @@ Examples:
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
+   phy-names = "sata-phy";
+   phys = < 1 PHY_TYPE_SATA 1 1>;
+   resets = <_reset ZYNQMP_RESET_SATA>;
};
-- 
2.7.4

RE: [PATCH 2/2] dt-bindings: ata: achi: ceva: Update documentation for CEVA Controller

2020-09-15 Thread Piyush Mehta

Hello Rob Herring,

Thanks for review. 

Regards,
Piyush Mehta

-Original Message-
From: Rob Herring  
Sent: Tuesday, September 15, 2020 1:39 AM
To: Piyush Mehta 
Cc: ax...@kernel.dk; p.za...@pengutronix.de; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; git 
; Srinivas Goud ; Michal Simek 

Subject: Re: [PATCH 2/2] dt-bindings: ata: achi: ceva: Update documentation for 
CEVA Controller

On Wed, Sep 02, 2020 at 12:35:48PM +0530, Piyush Mehta wrote:
> This patch updates the documentation for the CEVA controller for 
> adding the required properties for 'phys' and 'resets'.
> 
> Signed-off-by: Piyush Mehta 
> ---
>  Documentation/devicetree/bindings/ata/ahci-ceva.txt | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt 
> b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> index 7561cc4..f01d317 100644
> --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> @@ -35,6 +35,10 @@ Required properties:
>   ceva,pN-retry-params = /bits/ 16 ;
>   RIT:  Retry Interval Timer.
>   RCT:  Rate Change Timer.
> +  - phys: phandle for the PHY device
> +  - phy-names: Should be "sata-phy"
> +  - resets: phandle to the reset controller for the SATA IP
> +  - reset-names: Should be "sata_rst".

The names here are rather pointless. You don't really need them if only
1 entry.

>  
>  Optional properties:
>- ceva,broken-gen2: limit to gen1 speed instead of gen2.
> @@ -56,4 +60,8 @@ Examples:
>   ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
>   ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
>   ceva,broken-gen2;
> + phy-names = "sata-phy";
> + phys = < 1 PHY_TYPE_SATA 1 1>;
> + reset-names = "sata_rst";
> + resets = <_reset ZYNQMP_RESET_SATA>;
>   };
> --
> 2.7.4
>

[PATCH 2/2] dt-bindings: ata: achi: ceva: Update documentation for CEVA Controller

2020-09-02 Thread Piyush Mehta

This patch updates the documentation for the CEVA controller for adding
the required properties for 'phys' and 'resets'.

Signed-off-by: Piyush Mehta 
---
 Documentation/devicetree/bindings/ata/ahci-ceva.txt | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt 
b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7561cc4..f01d317 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -35,6 +35,10 @@ Required properties:
ceva,pN-retry-params = /bits/ 16 ;
RIT:  Retry Interval Timer.
RCT:  Rate Change Timer.
+  - phys: phandle for the PHY device
+  - phy-names: Should be "sata-phy"
+  - resets: phandle to the reset controller for the SATA IP
+  - reset-names: Should be "sata_rst".
 
 Optional properties:
   - ceva,broken-gen2: limit to gen1 speed instead of gen2.
@@ -56,4 +60,8 @@ Examples:
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
+   phy-names = "sata-phy";
+   phys = < 1 PHY_TYPE_SATA 1 1>;
+   reset-names = "sata_rst";
+   resets = <_reset ZYNQMP_RESET_SATA>;
};
-- 
2.7.4

[PATCH 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-02 Thread Piyush Mehta

This patch series updates the ceva driver to add support for Xilinx GT phy.
This also updates the documentation with the device tree binding required
for working with Xilinx GT phy.

Piyush Mehta (2):
  ata: ahci: ceva: Update the driver to support xilinx GT phy
  dt-bindings: ata: achi: ceva: Update documentation for CEVA Controller

 .../devicetree/bindings/ata/ahci-ceva.txt  |  8 +
 drivers/ata/ahci_ceva.c| 34 --
 2 files changed, 40 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH 1/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-02 Thread Piyush Mehta

SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for SATA controller, the below sequence is expected.

1. Assert the SATA controller reset.
2. Configure the xilinx GT phy lane for SATA controller (phy_init).
3. De-assert the SATA controller reset.
4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).

The ahci_platform_enable_resources() by default does the phy_init()
and phy_power_on() but the default sequence doesn't work with Xilinx
platforms. Because of this reason, updated the driver to support the
new sequence.

Signed-off-by: Piyush Mehta 
---
 drivers/ata/ahci_ceva.c | 34 --
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b10fd4c..5341d89 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "ahci.h"
 
 /* Vendor Specific Register Offsets */
@@ -87,6 +88,7 @@ struct ceva_ahci_priv {
u32 axicc;
bool is_cci_enabled;
int flags;
+   struct reset_control *rst;
 };
 
 static unsigned int ceva_ahci_read_id(struct ata_device *dev,
@@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
struct ahci_host_priv *hpriv;
struct ceva_ahci_priv *cevapriv;
enum dev_dma_attr attr;
-   int rc;
+   int rc, i;
 
cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
if (!cevapriv)
@@ -202,14 +204,42 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
cevapriv->ahci_pdev = pdev;
 
+   cevapriv->rst = devm_reset_control_get(>dev, NULL);
+   if (IS_ERR(cevapriv->rst)) {
+   if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
+   dev_err(>dev, "failed to get reset: %ld\n",
+   PTR_ERR(cevapriv->rst));
+   return PTR_ERR(cevapriv->rst);
+   }
+
hpriv = ahci_platform_get_resources(pdev, 0);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
 
-   rc = ahci_platform_enable_resources(hpriv);
+   rc = ahci_platform_enable_clks(hpriv);
if (rc)
return rc;
 
+   /* Assert the controller reset */
+   reset_control_assert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_init(hpriv->phys[i]);
+   if (rc)
+   return rc;
+   }
+
+   /* De-assert the controller reset */
+   reset_control_deassert(cevapriv->rst);
+
+   for (i = 0; i < hpriv->nports; i++) {
+   rc = phy_power_on(hpriv->phys[i]);
+   if (rc) {
+   phy_exit(hpriv->phys[i]);
+   return rc;
+   }
+   }
+
if (of_property_read_bool(np, "ceva,broken-gen2"))
cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
 
-- 
2.7.4

[PATCH V2] ata: ahci: ceva: Updated code by using dev_err_probe()

[PATCH] ata: ahci: ceva: Updated code by using dev_err_probe()

[PATCH] ata: ahci: ceva: Updated code by using dev_err_probe()

[PATCH V3 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

[PATCH V3 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH V3 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

RE: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

RE: [PATCH 2/2] dt-bindings: ata: achi: ceva: Update documentation for CEVA Controller

[PATCH 2/2] dt-bindings: ata: achi: ceva: Update documentation for CEVA Controller

[PATCH 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH 1/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

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